Merge tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6
[~shefty/rdma-dev.git] / drivers / mtd / nand / gpmi-nand / gpmi-lib.c
1 /*
2  * Freescale GPMI NAND Flash Driver
3  *
4  * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
5  * Copyright (C) 2008 Embedded Alley Solutions, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20  */
21 #include <linux/mtd/gpmi-nand.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <mach/mxs.h>
25
26 #include "gpmi-nand.h"
27 #include "gpmi-regs.h"
28 #include "bch-regs.h"
29
30 struct timing_threshod timing_default_threshold = {
31         .max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
32                                                 BP_GPMI_TIMING0_DATA_SETUP),
33         .internal_data_setup_in_ns   = 0,
34         .max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
35                                                 BP_GPMI_CTRL1_RDN_DELAY),
36         .max_dll_clock_period_in_ns  = 32,
37         .max_dll_delay_in_ns         = 16,
38 };
39
40 /*
41  * Clear the bit and poll it cleared.  This is usually called with
42  * a reset address and mask being either SFTRST(bit 31) or CLKGATE
43  * (bit 30).
44  */
45 static int clear_poll_bit(void __iomem *addr, u32 mask)
46 {
47         int timeout = 0x400;
48
49         /* clear the bit */
50         __mxs_clrl(mask, addr);
51
52         /*
53          * SFTRST needs 3 GPMI clocks to settle, the reference manual
54          * recommends to wait 1us.
55          */
56         udelay(1);
57
58         /* poll the bit becoming clear */
59         while ((readl(addr) & mask) && --timeout)
60                 /* nothing */;
61
62         return !timeout;
63 }
64
65 #define MODULE_CLKGATE          (1 << 30)
66 #define MODULE_SFTRST           (1 << 31)
67 /*
68  * The current mxs_reset_block() will do two things:
69  *  [1] enable the module.
70  *  [2] reset the module.
71  *
72  * In most of the cases, it's ok.
73  * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
74  * If you try to soft reset the BCH block, it becomes unusable until
75  * the next hard reset. This case occurs in the NAND boot mode. When the board
76  * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
77  * So If the driver tries to reset the BCH again, the BCH will not work anymore.
78  * You will see a DMA timeout in this case. The bug has been fixed
79  * in the following chips, such as MX28.
80  *
81  * To avoid this bug, just add a new parameter `just_enable` for
82  * the mxs_reset_block(), and rewrite it here.
83  */
84 static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
85 {
86         int ret;
87         int timeout = 0x400;
88
89         /* clear and poll SFTRST */
90         ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
91         if (unlikely(ret))
92                 goto error;
93
94         /* clear CLKGATE */
95         __mxs_clrl(MODULE_CLKGATE, reset_addr);
96
97         if (!just_enable) {
98                 /* set SFTRST to reset the block */
99                 __mxs_setl(MODULE_SFTRST, reset_addr);
100                 udelay(1);
101
102                 /* poll CLKGATE becoming set */
103                 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
104                         /* nothing */;
105                 if (unlikely(!timeout))
106                         goto error;
107         }
108
109         /* clear and poll SFTRST */
110         ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
111         if (unlikely(ret))
112                 goto error;
113
114         /* clear and poll CLKGATE */
115         ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
116         if (unlikely(ret))
117                 goto error;
118
119         return 0;
120
121 error:
122         pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
123         return -ETIMEDOUT;
124 }
125
126 int gpmi_init(struct gpmi_nand_data *this)
127 {
128         struct resources *r = &this->resources;
129         int ret;
130
131         ret = clk_prepare_enable(r->clock);
132         if (ret)
133                 goto err_out;
134         ret = gpmi_reset_block(r->gpmi_regs, false);
135         if (ret)
136                 goto err_out;
137
138         /* Choose NAND mode. */
139         writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
140
141         /* Set the IRQ polarity. */
142         writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
143                                 r->gpmi_regs + HW_GPMI_CTRL1_SET);
144
145         /* Disable Write-Protection. */
146         writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
147
148         /* Select BCH ECC. */
149         writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
150
151         clk_disable_unprepare(r->clock);
152         return 0;
153 err_out:
154         return ret;
155 }
156
157 /* This function is very useful. It is called only when the bug occur. */
158 void gpmi_dump_info(struct gpmi_nand_data *this)
159 {
160         struct resources *r = &this->resources;
161         struct bch_geometry *geo = &this->bch_geometry;
162         u32 reg;
163         int i;
164
165         pr_err("Show GPMI registers :\n");
166         for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
167                 reg = readl(r->gpmi_regs + i * 0x10);
168                 pr_err("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
169         }
170
171         /* start to print out the BCH info */
172         pr_err("BCH Geometry :\n");
173         pr_err("GF length              : %u\n", geo->gf_len);
174         pr_err("ECC Strength           : %u\n", geo->ecc_strength);
175         pr_err("Page Size in Bytes     : %u\n", geo->page_size);
176         pr_err("Metadata Size in Bytes : %u\n", geo->metadata_size);
177         pr_err("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size);
178         pr_err("ECC Chunk Count        : %u\n", geo->ecc_chunk_count);
179         pr_err("Payload Size in Bytes  : %u\n", geo->payload_size);
180         pr_err("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size);
181         pr_err("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
182         pr_err("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
183         pr_err("Block Mark Bit Offset  : %u\n", geo->block_mark_bit_offset);
184 }
185
186 /* Configures the geometry for BCH.  */
187 int bch_set_geometry(struct gpmi_nand_data *this)
188 {
189         struct resources *r = &this->resources;
190         struct bch_geometry *bch_geo = &this->bch_geometry;
191         unsigned int block_count;
192         unsigned int block_size;
193         unsigned int metadata_size;
194         unsigned int ecc_strength;
195         unsigned int page_size;
196         int ret;
197
198         if (common_nfc_set_geometry(this))
199                 return !0;
200
201         block_count   = bch_geo->ecc_chunk_count - 1;
202         block_size    = bch_geo->ecc_chunk_size;
203         metadata_size = bch_geo->metadata_size;
204         ecc_strength  = bch_geo->ecc_strength >> 1;
205         page_size     = bch_geo->page_size;
206
207         ret = clk_prepare_enable(r->clock);
208         if (ret)
209                 goto err_out;
210
211         /*
212         * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
213         * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
214         * On the other hand, the MX28 needs the reset, because one case has been
215         * seen where the BCH produced ECC errors constantly after 10000
216         * consecutive reboots. The latter case has not been seen on the MX23 yet,
217         * still we don't know if it could happen there as well.
218         */
219         ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
220         if (ret)
221                 goto err_out;
222
223         /* Configure layout 0. */
224         writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
225                         | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
226                         | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)
227                         | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size),
228                         r->bch_regs + HW_BCH_FLASH0LAYOUT0);
229
230         writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
231                         | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)
232                         | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size),
233                         r->bch_regs + HW_BCH_FLASH0LAYOUT1);
234
235         /* Set *all* chip selects to use layout 0. */
236         writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
237
238         /* Enable interrupts. */
239         writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
240                                 r->bch_regs + HW_BCH_CTRL_SET);
241
242         clk_disable_unprepare(r->clock);
243         return 0;
244 err_out:
245         return ret;
246 }
247
248 /* Converts time in nanoseconds to cycles. */
249 static unsigned int ns_to_cycles(unsigned int time,
250                         unsigned int period, unsigned int min)
251 {
252         unsigned int k;
253
254         k = (time + period - 1) / period;
255         return max(k, min);
256 }
257
258 /* Apply timing to current hardware conditions. */
259 static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
260                                         struct gpmi_nfc_hardware_timing *hw)
261 {
262         struct gpmi_nand_platform_data *pdata = this->pdata;
263         struct timing_threshod *nfc = &timing_default_threshold;
264         struct nand_chip *nand = &this->nand;
265         struct nand_timing target = this->timing;
266         bool improved_timing_is_available;
267         unsigned long clock_frequency_in_hz;
268         unsigned int clock_period_in_ns;
269         bool dll_use_half_periods;
270         unsigned int dll_delay_shift;
271         unsigned int max_sample_delay_in_ns;
272         unsigned int address_setup_in_cycles;
273         unsigned int data_setup_in_ns;
274         unsigned int data_setup_in_cycles;
275         unsigned int data_hold_in_cycles;
276         int ideal_sample_delay_in_ns;
277         unsigned int sample_delay_factor;
278         int tEYE;
279         unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
280         unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
281
282         /*
283          * If there are multiple chips, we need to relax the timings to allow
284          * for signal distortion due to higher capacitance.
285          */
286         if (nand->numchips > 2) {
287                 target.data_setup_in_ns    += 10;
288                 target.data_hold_in_ns     += 10;
289                 target.address_setup_in_ns += 10;
290         } else if (nand->numchips > 1) {
291                 target.data_setup_in_ns    += 5;
292                 target.data_hold_in_ns     += 5;
293                 target.address_setup_in_ns += 5;
294         }
295
296         /* Check if improved timing information is available. */
297         improved_timing_is_available =
298                 (target.tREA_in_ns  >= 0) &&
299                 (target.tRLOH_in_ns >= 0) &&
300                 (target.tRHOH_in_ns >= 0) ;
301
302         /* Inspect the clock. */
303         clock_frequency_in_hz = nfc->clock_frequency_in_hz;
304         clock_period_in_ns    = 1000000000 / clock_frequency_in_hz;
305
306         /*
307          * The NFC quantizes setup and hold parameters in terms of clock cycles.
308          * Here, we quantize the setup and hold timing parameters to the
309          * next-highest clock period to make sure we apply at least the
310          * specified times.
311          *
312          * For data setup and data hold, the hardware interprets a value of zero
313          * as the largest possible delay. This is not what's intended by a zero
314          * in the input parameter, so we impose a minimum of one cycle.
315          */
316         data_setup_in_cycles    = ns_to_cycles(target.data_setup_in_ns,
317                                                         clock_period_in_ns, 1);
318         data_hold_in_cycles     = ns_to_cycles(target.data_hold_in_ns,
319                                                         clock_period_in_ns, 1);
320         address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
321                                                         clock_period_in_ns, 0);
322
323         /*
324          * The clock's period affects the sample delay in a number of ways:
325          *
326          * (1) The NFC HAL tells us the maximum clock period the sample delay
327          *     DLL can tolerate. If the clock period is greater than half that
328          *     maximum, we must configure the DLL to be driven by half periods.
329          *
330          * (2) We need to convert from an ideal sample delay, in ns, to a
331          *     "sample delay factor," which the NFC uses. This factor depends on
332          *     whether we're driving the DLL with full or half periods.
333          *     Paraphrasing the reference manual:
334          *
335          *         AD = SDF x 0.125 x RP
336          *
337          * where:
338          *
339          *     AD   is the applied delay, in ns.
340          *     SDF  is the sample delay factor, which is dimensionless.
341          *     RP   is the reference period, in ns, which is a full clock period
342          *          if the DLL is being driven by full periods, or half that if
343          *          the DLL is being driven by half periods.
344          *
345          * Let's re-arrange this in a way that's more useful to us:
346          *
347          *                        8
348          *         SDF  =  AD x ----
349          *                       RP
350          *
351          * The reference period is either the clock period or half that, so this
352          * is:
353          *
354          *                        8       AD x DDF
355          *         SDF  =  AD x -----  =  --------
356          *                      f x P        P
357          *
358          * where:
359          *
360          *       f  is 1 or 1/2, depending on how we're driving the DLL.
361          *       P  is the clock period.
362          *     DDF  is the DLL Delay Factor, a dimensionless value that
363          *          incorporates all the constants in the conversion.
364          *
365          * DDF will be either 8 or 16, both of which are powers of two. We can
366          * reduce the cost of this conversion by using bit shifts instead of
367          * multiplication or division. Thus:
368          *
369          *                 AD << DDS
370          *         SDF  =  ---------
371          *                     P
372          *
373          *     or
374          *
375          *         AD  =  (SDF >> DDS) x P
376          *
377          * where:
378          *
379          *     DDS  is the DLL Delay Shift, the logarithm to base 2 of the DDF.
380          */
381         if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
382                 dll_use_half_periods = true;
383                 dll_delay_shift      = 3 + 1;
384         } else {
385                 dll_use_half_periods = false;
386                 dll_delay_shift      = 3;
387         }
388
389         /*
390          * Compute the maximum sample delay the NFC allows, under current
391          * conditions. If the clock is running too slowly, no sample delay is
392          * possible.
393          */
394         if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
395                 max_sample_delay_in_ns = 0;
396         else {
397                 /*
398                  * Compute the delay implied by the largest sample delay factor
399                  * the NFC allows.
400                  */
401                 max_sample_delay_in_ns =
402                         (nfc->max_sample_delay_factor * clock_period_in_ns) >>
403                                                                 dll_delay_shift;
404
405                 /*
406                  * Check if the implied sample delay larger than the NFC
407                  * actually allows.
408                  */
409                 if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
410                         max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
411         }
412
413         /*
414          * Check if improved timing information is available. If not, we have to
415          * use a less-sophisticated algorithm.
416          */
417         if (!improved_timing_is_available) {
418                 /*
419                  * Fold the read setup time required by the NFC into the ideal
420                  * sample delay.
421                  */
422                 ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
423                                                 nfc->internal_data_setup_in_ns;
424
425                 /*
426                  * The ideal sample delay may be greater than the maximum
427                  * allowed by the NFC. If so, we can trade off sample delay time
428                  * for more data setup time.
429                  *
430                  * In each iteration of the following loop, we add a cycle to
431                  * the data setup time and subtract a corresponding amount from
432                  * the sample delay until we've satisified the constraints or
433                  * can't do any better.
434                  */
435                 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
436                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
437
438                         data_setup_in_cycles++;
439                         ideal_sample_delay_in_ns -= clock_period_in_ns;
440
441                         if (ideal_sample_delay_in_ns < 0)
442                                 ideal_sample_delay_in_ns = 0;
443
444                 }
445
446                 /*
447                  * Compute the sample delay factor that corresponds most closely
448                  * to the ideal sample delay. If the result is too large for the
449                  * NFC, use the maximum value.
450                  *
451                  * Notice that we use the ns_to_cycles function to compute the
452                  * sample delay factor. We do this because the form of the
453                  * computation is the same as that for calculating cycles.
454                  */
455                 sample_delay_factor =
456                         ns_to_cycles(
457                                 ideal_sample_delay_in_ns << dll_delay_shift,
458                                                         clock_period_in_ns, 0);
459
460                 if (sample_delay_factor > nfc->max_sample_delay_factor)
461                         sample_delay_factor = nfc->max_sample_delay_factor;
462
463                 /* Skip to the part where we return our results. */
464                 goto return_results;
465         }
466
467         /*
468          * If control arrives here, we have more detailed timing information,
469          * so we can use a better algorithm.
470          */
471
472         /*
473          * Fold the read setup time required by the NFC into the maximum
474          * propagation delay.
475          */
476         max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
477
478         /*
479          * Earlier, we computed the number of clock cycles required to satisfy
480          * the data setup time. Now, we need to know the actual nanoseconds.
481          */
482         data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
483
484         /*
485          * Compute tEYE, the width of the data eye when reading from the NAND
486          * Flash. The eye width is fundamentally determined by the data setup
487          * time, perturbed by propagation delays and some characteristics of the
488          * NAND Flash device.
489          *
490          * start of the eye = max_prop_delay + tREA
491          * end of the eye   = min_prop_delay + tRHOH + data_setup
492          */
493         tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
494                                                         (int)data_setup_in_ns;
495
496         tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
497
498         /*
499          * The eye must be open. If it's not, we can try to open it by
500          * increasing its main forcer, the data setup time.
501          *
502          * In each iteration of the following loop, we increase the data setup
503          * time by a single clock cycle. We do this until either the eye is
504          * open or we run into NFC limits.
505          */
506         while ((tEYE <= 0) &&
507                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
508                 /* Give a cycle to data setup. */
509                 data_setup_in_cycles++;
510                 /* Synchronize the data setup time with the cycles. */
511                 data_setup_in_ns += clock_period_in_ns;
512                 /* Adjust tEYE accordingly. */
513                 tEYE += clock_period_in_ns;
514         }
515
516         /*
517          * When control arrives here, the eye is open. The ideal time to sample
518          * the data is in the center of the eye:
519          *
520          *     end of the eye + start of the eye
521          *     ---------------------------------  -  data_setup
522          *                    2
523          *
524          * After some algebra, this simplifies to the code immediately below.
525          */
526         ideal_sample_delay_in_ns =
527                 ((int)max_prop_delay_in_ns +
528                         (int)target.tREA_in_ns +
529                                 (int)min_prop_delay_in_ns +
530                                         (int)target.tRHOH_in_ns -
531                                                 (int)data_setup_in_ns) >> 1;
532
533         /*
534          * The following figure illustrates some aspects of a NAND Flash read:
535          *
536          *
537          *           __                   _____________________________________
538          * RDN         \_________________/
539          *
540          *                                         <---- tEYE ----->
541          *                                        /-----------------\
542          * Read Data ----------------------------<                   >---------
543          *                                        \-----------------/
544          *             ^                 ^                 ^              ^
545          *             |                 |                 |              |
546          *             |<--Data Setup -->|<--Delay Time -->|              |
547          *             |                 |                 |              |
548          *             |                 |                                |
549          *             |                 |<--   Quantized Delay Time   -->|
550          *             |                 |                                |
551          *
552          *
553          * We have some issues we must now address:
554          *
555          * (1) The *ideal* sample delay time must not be negative. If it is, we
556          *     jam it to zero.
557          *
558          * (2) The *ideal* sample delay time must not be greater than that
559          *     allowed by the NFC. If it is, we can increase the data setup
560          *     time, which will reduce the delay between the end of the data
561          *     setup and the center of the eye. It will also make the eye
562          *     larger, which might help with the next issue...
563          *
564          * (3) The *quantized* sample delay time must not fall either before the
565          *     eye opens or after it closes (the latter is the problem
566          *     illustrated in the above figure).
567          */
568
569         /* Jam a negative ideal sample delay to zero. */
570         if (ideal_sample_delay_in_ns < 0)
571                 ideal_sample_delay_in_ns = 0;
572
573         /*
574          * Extend the data setup as needed to reduce the ideal sample delay
575          * below the maximum permitted by the NFC.
576          */
577         while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
578                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
579
580                 /* Give a cycle to data setup. */
581                 data_setup_in_cycles++;
582                 /* Synchronize the data setup time with the cycles. */
583                 data_setup_in_ns += clock_period_in_ns;
584                 /* Adjust tEYE accordingly. */
585                 tEYE += clock_period_in_ns;
586
587                 /*
588                  * Decrease the ideal sample delay by one half cycle, to keep it
589                  * in the middle of the eye.
590                  */
591                 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
592
593                 /* Jam a negative ideal sample delay to zero. */
594                 if (ideal_sample_delay_in_ns < 0)
595                         ideal_sample_delay_in_ns = 0;
596         }
597
598         /*
599          * Compute the sample delay factor that corresponds to the ideal sample
600          * delay. If the result is too large, then use the maximum allowed
601          * value.
602          *
603          * Notice that we use the ns_to_cycles function to compute the sample
604          * delay factor. We do this because the form of the computation is the
605          * same as that for calculating cycles.
606          */
607         sample_delay_factor =
608                 ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
609                                                         clock_period_in_ns, 0);
610
611         if (sample_delay_factor > nfc->max_sample_delay_factor)
612                 sample_delay_factor = nfc->max_sample_delay_factor;
613
614         /*
615          * These macros conveniently encapsulate a computation we'll use to
616          * continuously evaluate whether or not the data sample delay is inside
617          * the eye.
618          */
619         #define IDEAL_DELAY  ((int) ideal_sample_delay_in_ns)
620
621         #define QUANTIZED_DELAY  \
622                 ((int) ((sample_delay_factor * clock_period_in_ns) >> \
623                                                         dll_delay_shift))
624
625         #define DELAY_ERROR  (abs(QUANTIZED_DELAY - IDEAL_DELAY))
626
627         #define SAMPLE_IS_NOT_WITHIN_THE_EYE  (DELAY_ERROR > (tEYE >> 1))
628
629         /*
630          * While the quantized sample time falls outside the eye, reduce the
631          * sample delay or extend the data setup to move the sampling point back
632          * toward the eye. Do not allow the number of data setup cycles to
633          * exceed the maximum allowed by the NFC.
634          */
635         while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
636                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
637                 /*
638                  * If control arrives here, the quantized sample delay falls
639                  * outside the eye. Check if it's before the eye opens, or after
640                  * the eye closes.
641                  */
642                 if (QUANTIZED_DELAY > IDEAL_DELAY) {
643                         /*
644                          * If control arrives here, the quantized sample delay
645                          * falls after the eye closes. Decrease the quantized
646                          * delay time and then go back to re-evaluate.
647                          */
648                         if (sample_delay_factor != 0)
649                                 sample_delay_factor--;
650                         continue;
651                 }
652
653                 /*
654                  * If control arrives here, the quantized sample delay falls
655                  * before the eye opens. Shift the sample point by increasing
656                  * data setup time. This will also make the eye larger.
657                  */
658
659                 /* Give a cycle to data setup. */
660                 data_setup_in_cycles++;
661                 /* Synchronize the data setup time with the cycles. */
662                 data_setup_in_ns += clock_period_in_ns;
663                 /* Adjust tEYE accordingly. */
664                 tEYE += clock_period_in_ns;
665
666                 /*
667                  * Decrease the ideal sample delay by one half cycle, to keep it
668                  * in the middle of the eye.
669                  */
670                 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
671
672                 /* ...and one less period for the delay time. */
673                 ideal_sample_delay_in_ns -= clock_period_in_ns;
674
675                 /* Jam a negative ideal sample delay to zero. */
676                 if (ideal_sample_delay_in_ns < 0)
677                         ideal_sample_delay_in_ns = 0;
678
679                 /*
680                  * We have a new ideal sample delay, so re-compute the quantized
681                  * delay.
682                  */
683                 sample_delay_factor =
684                         ns_to_cycles(
685                                 ideal_sample_delay_in_ns << dll_delay_shift,
686                                                         clock_period_in_ns, 0);
687
688                 if (sample_delay_factor > nfc->max_sample_delay_factor)
689                         sample_delay_factor = nfc->max_sample_delay_factor;
690         }
691
692         /* Control arrives here when we're ready to return our results. */
693 return_results:
694         hw->data_setup_in_cycles    = data_setup_in_cycles;
695         hw->data_hold_in_cycles     = data_hold_in_cycles;
696         hw->address_setup_in_cycles = address_setup_in_cycles;
697         hw->use_half_periods        = dll_use_half_periods;
698         hw->sample_delay_factor     = sample_delay_factor;
699
700         /* Return success. */
701         return 0;
702 }
703
704 /* Begin the I/O */
705 void gpmi_begin(struct gpmi_nand_data *this)
706 {
707         struct resources *r = &this->resources;
708         struct timing_threshod *nfc = &timing_default_threshold;
709         unsigned char  *gpmi_regs = r->gpmi_regs;
710         unsigned int   clock_period_in_ns;
711         uint32_t       reg;
712         unsigned int   dll_wait_time_in_us;
713         struct gpmi_nfc_hardware_timing  hw;
714         int ret;
715
716         /* Enable the clock. */
717         ret = clk_prepare_enable(r->clock);
718         if (ret) {
719                 pr_err("We failed in enable the clk\n");
720                 goto err_out;
721         }
722
723         /* set ready/busy timeout */
724         writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT,
725                 gpmi_regs + HW_GPMI_TIMING1);
726
727         /* Get the timing information we need. */
728         nfc->clock_frequency_in_hz = clk_get_rate(r->clock);
729         clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
730
731         gpmi_nfc_compute_hardware_timing(this, &hw);
732
733         /* Set up all the simple timing parameters. */
734         reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
735                 BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles)         |
736                 BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles)       ;
737
738         writel(reg, gpmi_regs + HW_GPMI_TIMING0);
739
740         /*
741          * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
742          */
743         writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
744
745         /* Clear out the DLL control fields. */
746         writel(BM_GPMI_CTRL1_RDN_DELAY,   gpmi_regs + HW_GPMI_CTRL1_CLR);
747         writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
748
749         /* If no sample delay is called for, return immediately. */
750         if (!hw.sample_delay_factor)
751                 return;
752
753         /* Configure the HALF_PERIOD flag. */
754         if (hw.use_half_periods)
755                 writel(BM_GPMI_CTRL1_HALF_PERIOD,
756                                                 gpmi_regs + HW_GPMI_CTRL1_SET);
757
758         /* Set the delay factor. */
759         writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
760                                                 gpmi_regs + HW_GPMI_CTRL1_SET);
761
762         /* Enable the DLL. */
763         writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
764
765         /*
766          * After we enable the GPMI DLL, we have to wait 64 clock cycles before
767          * we can use the GPMI.
768          *
769          * Calculate the amount of time we need to wait, in microseconds.
770          */
771         dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
772
773         if (!dll_wait_time_in_us)
774                 dll_wait_time_in_us = 1;
775
776         /* Wait for the DLL to settle. */
777         udelay(dll_wait_time_in_us);
778
779 err_out:
780         return;
781 }
782
783 void gpmi_end(struct gpmi_nand_data *this)
784 {
785         struct resources *r = &this->resources;
786         clk_disable_unprepare(r->clock);
787 }
788
789 /* Clears a BCH interrupt. */
790 void gpmi_clear_bch(struct gpmi_nand_data *this)
791 {
792         struct resources *r = &this->resources;
793         writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
794 }
795
796 /* Returns the Ready/Busy status of the given chip. */
797 int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
798 {
799         struct resources *r = &this->resources;
800         uint32_t mask = 0;
801         uint32_t reg = 0;
802
803         if (GPMI_IS_MX23(this)) {
804                 mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
805                 reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
806         } else if (GPMI_IS_MX28(this)) {
807                 mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
808                 reg = readl(r->gpmi_regs + HW_GPMI_STAT);
809         } else
810                 pr_err("unknow arch.\n");
811         return reg & mask;
812 }
813
814 static inline void set_dma_type(struct gpmi_nand_data *this,
815                                         enum dma_ops_type type)
816 {
817         this->last_dma_type = this->dma_type;
818         this->dma_type = type;
819 }
820
821 int gpmi_send_command(struct gpmi_nand_data *this)
822 {
823         struct dma_chan *channel = get_dma_chan(this);
824         struct dma_async_tx_descriptor *desc;
825         struct scatterlist *sgl;
826         int chip = this->current_chip;
827         u32 pio[3];
828
829         /* [1] send out the PIO words */
830         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
831                 | BM_GPMI_CTRL0_WORD_LENGTH
832                 | BF_GPMI_CTRL0_CS(chip, this)
833                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
834                 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
835                 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
836                 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
837         pio[1] = pio[2] = 0;
838         desc = dmaengine_prep_slave_sg(channel,
839                                         (struct scatterlist *)pio,
840                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
841         if (!desc) {
842                 pr_err("step 1 error\n");
843                 return -1;
844         }
845
846         /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
847         sgl = &this->cmd_sgl;
848
849         sg_init_one(sgl, this->cmd_buffer, this->command_length);
850         dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
851         desc = dmaengine_prep_slave_sg(channel,
852                                 sgl, 1, DMA_MEM_TO_DEV,
853                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
854
855         if (!desc) {
856                 pr_err("step 2 error\n");
857                 return -1;
858         }
859
860         /* [3] submit the DMA */
861         set_dma_type(this, DMA_FOR_COMMAND);
862         return start_dma_without_bch_irq(this, desc);
863 }
864
865 int gpmi_send_data(struct gpmi_nand_data *this)
866 {
867         struct dma_async_tx_descriptor *desc;
868         struct dma_chan *channel = get_dma_chan(this);
869         int chip = this->current_chip;
870         uint32_t command_mode;
871         uint32_t address;
872         u32 pio[2];
873
874         /* [1] PIO */
875         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
876         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
877
878         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
879                 | BM_GPMI_CTRL0_WORD_LENGTH
880                 | BF_GPMI_CTRL0_CS(chip, this)
881                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
882                 | BF_GPMI_CTRL0_ADDRESS(address)
883                 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
884         pio[1] = 0;
885         desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
886                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
887         if (!desc) {
888                 pr_err("step 1 error\n");
889                 return -1;
890         }
891
892         /* [2] send DMA request */
893         prepare_data_dma(this, DMA_TO_DEVICE);
894         desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
895                                         1, DMA_MEM_TO_DEV,
896                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
897         if (!desc) {
898                 pr_err("step 2 error\n");
899                 return -1;
900         }
901         /* [3] submit the DMA */
902         set_dma_type(this, DMA_FOR_WRITE_DATA);
903         return start_dma_without_bch_irq(this, desc);
904 }
905
906 int gpmi_read_data(struct gpmi_nand_data *this)
907 {
908         struct dma_async_tx_descriptor *desc;
909         struct dma_chan *channel = get_dma_chan(this);
910         int chip = this->current_chip;
911         u32 pio[2];
912
913         /* [1] : send PIO */
914         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
915                 | BM_GPMI_CTRL0_WORD_LENGTH
916                 | BF_GPMI_CTRL0_CS(chip, this)
917                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
918                 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
919                 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
920         pio[1] = 0;
921         desc = dmaengine_prep_slave_sg(channel,
922                                         (struct scatterlist *)pio,
923                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
924         if (!desc) {
925                 pr_err("step 1 error\n");
926                 return -1;
927         }
928
929         /* [2] : send DMA request */
930         prepare_data_dma(this, DMA_FROM_DEVICE);
931         desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
932                                         1, DMA_DEV_TO_MEM,
933                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
934         if (!desc) {
935                 pr_err("step 2 error\n");
936                 return -1;
937         }
938
939         /* [3] : submit the DMA */
940         set_dma_type(this, DMA_FOR_READ_DATA);
941         return start_dma_without_bch_irq(this, desc);
942 }
943
944 int gpmi_send_page(struct gpmi_nand_data *this,
945                         dma_addr_t payload, dma_addr_t auxiliary)
946 {
947         struct bch_geometry *geo = &this->bch_geometry;
948         uint32_t command_mode;
949         uint32_t address;
950         uint32_t ecc_command;
951         uint32_t buffer_mask;
952         struct dma_async_tx_descriptor *desc;
953         struct dma_chan *channel = get_dma_chan(this);
954         int chip = this->current_chip;
955         u32 pio[6];
956
957         /* A DMA descriptor that does an ECC page read. */
958         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
959         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
960         ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
961         buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
962                                 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
963
964         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
965                 | BM_GPMI_CTRL0_WORD_LENGTH
966                 | BF_GPMI_CTRL0_CS(chip, this)
967                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
968                 | BF_GPMI_CTRL0_ADDRESS(address)
969                 | BF_GPMI_CTRL0_XFER_COUNT(0);
970         pio[1] = 0;
971         pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
972                 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
973                 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
974         pio[3] = geo->page_size;
975         pio[4] = payload;
976         pio[5] = auxiliary;
977
978         desc = dmaengine_prep_slave_sg(channel,
979                                         (struct scatterlist *)pio,
980                                         ARRAY_SIZE(pio), DMA_TRANS_NONE,
981                                         DMA_CTRL_ACK);
982         if (!desc) {
983                 pr_err("step 2 error\n");
984                 return -1;
985         }
986         set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
987         return start_dma_with_bch_irq(this, desc);
988 }
989
990 int gpmi_read_page(struct gpmi_nand_data *this,
991                                 dma_addr_t payload, dma_addr_t auxiliary)
992 {
993         struct bch_geometry *geo = &this->bch_geometry;
994         uint32_t command_mode;
995         uint32_t address;
996         uint32_t ecc_command;
997         uint32_t buffer_mask;
998         struct dma_async_tx_descriptor *desc;
999         struct dma_chan *channel = get_dma_chan(this);
1000         int chip = this->current_chip;
1001         u32 pio[6];
1002
1003         /* [1] Wait for the chip to report ready. */
1004         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1005         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1006
1007         pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1008                 | BM_GPMI_CTRL0_WORD_LENGTH
1009                 | BF_GPMI_CTRL0_CS(chip, this)
1010                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1011                 | BF_GPMI_CTRL0_ADDRESS(address)
1012                 | BF_GPMI_CTRL0_XFER_COUNT(0);
1013         pio[1] = 0;
1014         desc = dmaengine_prep_slave_sg(channel,
1015                                 (struct scatterlist *)pio, 2,
1016                                 DMA_TRANS_NONE, 0);
1017         if (!desc) {
1018                 pr_err("step 1 error\n");
1019                 return -1;
1020         }
1021
1022         /* [2] Enable the BCH block and read. */
1023         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
1024         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1025         ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
1026         buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
1027                         | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1028
1029         pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1030                 | BM_GPMI_CTRL0_WORD_LENGTH
1031                 | BF_GPMI_CTRL0_CS(chip, this)
1032                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1033                 | BF_GPMI_CTRL0_ADDRESS(address)
1034                 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1035
1036         pio[1] = 0;
1037         pio[2] =  BM_GPMI_ECCCTRL_ENABLE_ECC
1038                 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1039                 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1040         pio[3] = geo->page_size;
1041         pio[4] = payload;
1042         pio[5] = auxiliary;
1043         desc = dmaengine_prep_slave_sg(channel,
1044                                         (struct scatterlist *)pio,
1045                                         ARRAY_SIZE(pio), DMA_TRANS_NONE,
1046                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1047         if (!desc) {
1048                 pr_err("step 2 error\n");
1049                 return -1;
1050         }
1051
1052         /* [3] Disable the BCH block */
1053         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1054         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1055
1056         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1057                 | BM_GPMI_CTRL0_WORD_LENGTH
1058                 | BF_GPMI_CTRL0_CS(chip, this)
1059                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1060                 | BF_GPMI_CTRL0_ADDRESS(address)
1061                 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1062         pio[1] = 0;
1063         pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
1064         desc = dmaengine_prep_slave_sg(channel,
1065                                 (struct scatterlist *)pio, 3,
1066                                 DMA_TRANS_NONE,
1067                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1068         if (!desc) {
1069                 pr_err("step 3 error\n");
1070                 return -1;
1071         }
1072
1073         /* [4] submit the DMA */
1074         set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
1075         return start_dma_with_bch_irq(this, desc);
1076 }