0fe64442903fa66c5627dab5916ba09f82496656
[~shefty/rdma-dev.git] / drivers / net / ethernet / broadcom / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2013 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
50
51 #include <net/checksum.h>
52 #include <net/ip.h>
53
54 #include <linux/io.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
57
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
60
61 #ifdef CONFIG_SPARC
62 #include <asm/idprom.h>
63 #include <asm/prom.h>
64 #endif
65
66 #define BAR_0   0
67 #define BAR_2   2
68
69 #include "tg3.h"
70
71 /* Functions & macros to verify TG3_FLAGS types */
72
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74 {
75         return test_bit(flag, bits);
76 }
77
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79 {
80         set_bit(flag, bits);
81 }
82
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84 {
85         clear_bit(flag, bits);
86 }
87
88 #define tg3_flag(tp, flag)                              \
89         _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag)                          \
91         _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag)                        \
93         _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
95 #define DRV_MODULE_NAME         "tg3"
96 #define TG3_MAJ_NUM                     3
97 #define TG3_MIN_NUM                     131
98 #define DRV_MODULE_VERSION      \
99         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE      "April 09, 2013"
101
102 #define RESET_KIND_SHUTDOWN     0
103 #define RESET_KIND_INIT         1
104 #define RESET_KIND_SUSPEND      2
105
106 #define TG3_DEF_RX_MODE         0
107 #define TG3_DEF_TX_MODE         0
108 #define TG3_DEF_MSG_ENABLE        \
109         (NETIF_MSG_DRV          | \
110          NETIF_MSG_PROBE        | \
111          NETIF_MSG_LINK         | \
112          NETIF_MSG_TIMER        | \
113          NETIF_MSG_IFDOWN       | \
114          NETIF_MSG_IFUP         | \
115          NETIF_MSG_RX_ERR       | \
116          NETIF_MSG_TX_ERR)
117
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY      100
119
120 /* length of time before we decide the hardware is borked,
121  * and dev->tx_timeout() should be called to fix the problem
122  */
123
124 #define TG3_TX_TIMEOUT                  (5 * HZ)
125
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU                     60
128 #define TG3_MAX_MTU(tp) \
129         (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
130
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132  * You can't change the ring sizes, but you can change where you place
133  * them in the NIC onboard memory.
134  */
135 #define TG3_RX_STD_RING_SIZE(tp) \
136         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING         200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
143
144 /* Do not place this n-ring entries value into the tp struct itself,
145  * we really want to expose these constants to GCC so that modulo et
146  * al.  operations are done with shifts and masks instead of with
147  * hw multiply/modulo instructions.  Another solution would be to
148  * replace things like '% foo' with '& (foo - 1)'.
149  */
150
151 #define TG3_TX_RING_SIZE                512
152 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
153
154 #define TG3_RX_STD_RING_BYTES(tp) \
155         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
161                                  TG3_TX_RING_SIZE)
162 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
164 #define TG3_DMA_BYTE_ENAB               64
165
166 #define TG3_RX_STD_DMA_SZ               1536
167 #define TG3_RX_JMB_DMA_SZ               9046
168
169 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
170
171 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
173
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
176
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
179
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181  * that are at least dword aligned when used in PCIX mode.  The driver
182  * works around this bug by double copying the packet.  This workaround
183  * is built into the normal double copy length check for efficiency.
184  *
185  * However, the double copy is only necessary on those architectures
186  * where unaligned memory accesses are inefficient.  For those architectures
187  * where unaligned memory accesses incur little penalty, we can reintegrate
188  * the 5701 in the normal rx path.  Doing so saves a device structure
189  * dereference by hardcoding the double copy threshold in place.
190  */
191 #define TG3_RX_COPY_THRESHOLD           256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
194 #else
195         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
196 #endif
197
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp)       ((tp)->rx_offset)
200 #else
201 #define TG3_RX_OFFSET(tp)       (NET_SKB_PAD)
202 #endif
203
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K            2048
207 #define TG3_TX_BD_DMA_MAX_4K            4096
208
209 #define TG3_RAW_IP_ALIGN 2
210
211 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
212 #define TG3_FW_UPDATE_FREQ_SEC          (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
213
214 #define FIRMWARE_TG3            "tigon/tg3.bin"
215 #define FIRMWARE_TG357766       "tigon/tg357766.bin"
216 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
217 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
218
219 static char version[] =
220         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
221
222 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224 MODULE_LICENSE("GPL");
225 MODULE_VERSION(DRV_MODULE_VERSION);
226 MODULE_FIRMWARE(FIRMWARE_TG3);
227 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
229
230 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
231 module_param(tg3_debug, int, 0);
232 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
233
234 #define TG3_DRV_DATA_FLAG_10_100_ONLY   0x0001
235 #define TG3_DRV_DATA_FLAG_5705_10_100   0x0002
236
237 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258                         TG3_DRV_DATA_FLAG_5705_10_100},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261                         TG3_DRV_DATA_FLAG_5705_10_100},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265                         TG3_DRV_DATA_FLAG_5705_10_100},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
279         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
283         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
284         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
286         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287                         PCI_VENDOR_ID_LENOVO,
288                         TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
290         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
291         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
300         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
302         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
304         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
305         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
307         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
309         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
311         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312                         PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315                         PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
319         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
322         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
323         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
324         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
325         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
329         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
333         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
334         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
335         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
336         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
337         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
340         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
341         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
342         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
343         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
344         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
345         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
346         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
347         {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
348         {}
349 };
350
351 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
352
353 static const struct {
354         const char string[ETH_GSTRING_LEN];
355 } ethtool_stats_keys[] = {
356         { "rx_octets" },
357         { "rx_fragments" },
358         { "rx_ucast_packets" },
359         { "rx_mcast_packets" },
360         { "rx_bcast_packets" },
361         { "rx_fcs_errors" },
362         { "rx_align_errors" },
363         { "rx_xon_pause_rcvd" },
364         { "rx_xoff_pause_rcvd" },
365         { "rx_mac_ctrl_rcvd" },
366         { "rx_xoff_entered" },
367         { "rx_frame_too_long_errors" },
368         { "rx_jabbers" },
369         { "rx_undersize_packets" },
370         { "rx_in_length_errors" },
371         { "rx_out_length_errors" },
372         { "rx_64_or_less_octet_packets" },
373         { "rx_65_to_127_octet_packets" },
374         { "rx_128_to_255_octet_packets" },
375         { "rx_256_to_511_octet_packets" },
376         { "rx_512_to_1023_octet_packets" },
377         { "rx_1024_to_1522_octet_packets" },
378         { "rx_1523_to_2047_octet_packets" },
379         { "rx_2048_to_4095_octet_packets" },
380         { "rx_4096_to_8191_octet_packets" },
381         { "rx_8192_to_9022_octet_packets" },
382
383         { "tx_octets" },
384         { "tx_collisions" },
385
386         { "tx_xon_sent" },
387         { "tx_xoff_sent" },
388         { "tx_flow_control" },
389         { "tx_mac_errors" },
390         { "tx_single_collisions" },
391         { "tx_mult_collisions" },
392         { "tx_deferred" },
393         { "tx_excessive_collisions" },
394         { "tx_late_collisions" },
395         { "tx_collide_2times" },
396         { "tx_collide_3times" },
397         { "tx_collide_4times" },
398         { "tx_collide_5times" },
399         { "tx_collide_6times" },
400         { "tx_collide_7times" },
401         { "tx_collide_8times" },
402         { "tx_collide_9times" },
403         { "tx_collide_10times" },
404         { "tx_collide_11times" },
405         { "tx_collide_12times" },
406         { "tx_collide_13times" },
407         { "tx_collide_14times" },
408         { "tx_collide_15times" },
409         { "tx_ucast_packets" },
410         { "tx_mcast_packets" },
411         { "tx_bcast_packets" },
412         { "tx_carrier_sense_errors" },
413         { "tx_discards" },
414         { "tx_errors" },
415
416         { "dma_writeq_full" },
417         { "dma_write_prioq_full" },
418         { "rxbds_empty" },
419         { "rx_discards" },
420         { "rx_errors" },
421         { "rx_threshold_hit" },
422
423         { "dma_readq_full" },
424         { "dma_read_prioq_full" },
425         { "tx_comp_queue_full" },
426
427         { "ring_set_send_prod_index" },
428         { "ring_status_update" },
429         { "nic_irqs" },
430         { "nic_avoided_irqs" },
431         { "nic_tx_threshold_hit" },
432
433         { "mbuf_lwm_thresh_hit" },
434 };
435
436 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
437 #define TG3_NVRAM_TEST          0
438 #define TG3_LINK_TEST           1
439 #define TG3_REGISTER_TEST       2
440 #define TG3_MEMORY_TEST         3
441 #define TG3_MAC_LOOPB_TEST      4
442 #define TG3_PHY_LOOPB_TEST      5
443 #define TG3_EXT_LOOPB_TEST      6
444 #define TG3_INTERRUPT_TEST      7
445
446
447 static const struct {
448         const char string[ETH_GSTRING_LEN];
449 } ethtool_test_keys[] = {
450         [TG3_NVRAM_TEST]        = { "nvram test        (online) " },
451         [TG3_LINK_TEST]         = { "link test         (online) " },
452         [TG3_REGISTER_TEST]     = { "register test     (offline)" },
453         [TG3_MEMORY_TEST]       = { "memory test       (offline)" },
454         [TG3_MAC_LOOPB_TEST]    = { "mac loopback test (offline)" },
455         [TG3_PHY_LOOPB_TEST]    = { "phy loopback test (offline)" },
456         [TG3_EXT_LOOPB_TEST]    = { "ext loopback test (offline)" },
457         [TG3_INTERRUPT_TEST]    = { "interrupt test    (offline)" },
458 };
459
460 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
461
462
463 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
464 {
465         writel(val, tp->regs + off);
466 }
467
468 static u32 tg3_read32(struct tg3 *tp, u32 off)
469 {
470         return readl(tp->regs + off);
471 }
472
473 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
474 {
475         writel(val, tp->aperegs + off);
476 }
477
478 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
479 {
480         return readl(tp->aperegs + off);
481 }
482
483 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
484 {
485         unsigned long flags;
486
487         spin_lock_irqsave(&tp->indirect_lock, flags);
488         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
489         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
490         spin_unlock_irqrestore(&tp->indirect_lock, flags);
491 }
492
493 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
494 {
495         writel(val, tp->regs + off);
496         readl(tp->regs + off);
497 }
498
499 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
500 {
501         unsigned long flags;
502         u32 val;
503
504         spin_lock_irqsave(&tp->indirect_lock, flags);
505         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
506         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
507         spin_unlock_irqrestore(&tp->indirect_lock, flags);
508         return val;
509 }
510
511 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
512 {
513         unsigned long flags;
514
515         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
516                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
517                                        TG3_64BIT_REG_LOW, val);
518                 return;
519         }
520         if (off == TG3_RX_STD_PROD_IDX_REG) {
521                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
522                                        TG3_64BIT_REG_LOW, val);
523                 return;
524         }
525
526         spin_lock_irqsave(&tp->indirect_lock, flags);
527         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
528         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
529         spin_unlock_irqrestore(&tp->indirect_lock, flags);
530
531         /* In indirect mode when disabling interrupts, we also need
532          * to clear the interrupt bit in the GRC local ctrl register.
533          */
534         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
535             (val == 0x1)) {
536                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
537                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
538         }
539 }
540
541 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
542 {
543         unsigned long flags;
544         u32 val;
545
546         spin_lock_irqsave(&tp->indirect_lock, flags);
547         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
548         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
549         spin_unlock_irqrestore(&tp->indirect_lock, flags);
550         return val;
551 }
552
553 /* usec_wait specifies the wait time in usec when writing to certain registers
554  * where it is unsafe to read back the register without some delay.
555  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
556  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
557  */
558 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
559 {
560         if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
561                 /* Non-posted methods */
562                 tp->write32(tp, off, val);
563         else {
564                 /* Posted method */
565                 tg3_write32(tp, off, val);
566                 if (usec_wait)
567                         udelay(usec_wait);
568                 tp->read32(tp, off);
569         }
570         /* Wait again after the read for the posted method to guarantee that
571          * the wait time is met.
572          */
573         if (usec_wait)
574                 udelay(usec_wait);
575 }
576
577 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
578 {
579         tp->write32_mbox(tp, off, val);
580         if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
581             (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
582              !tg3_flag(tp, ICH_WORKAROUND)))
583                 tp->read32_mbox(tp, off);
584 }
585
586 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
587 {
588         void __iomem *mbox = tp->regs + off;
589         writel(val, mbox);
590         if (tg3_flag(tp, TXD_MBOX_HWBUG))
591                 writel(val, mbox);
592         if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
593             tg3_flag(tp, FLUSH_POSTED_WRITES))
594                 readl(mbox);
595 }
596
597 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
598 {
599         return readl(tp->regs + off + GRCMBOX_BASE);
600 }
601
602 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
603 {
604         writel(val, tp->regs + off + GRCMBOX_BASE);
605 }
606
607 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
608 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
609 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
610 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
611 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
612
613 #define tw32(reg, val)                  tp->write32(tp, reg, val)
614 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
615 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
616 #define tr32(reg)                       tp->read32(tp, reg)
617
618 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
619 {
620         unsigned long flags;
621
622         if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
623             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
624                 return;
625
626         spin_lock_irqsave(&tp->indirect_lock, flags);
627         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
628                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
629                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
630
631                 /* Always leave this as zero. */
632                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
633         } else {
634                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
635                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
636
637                 /* Always leave this as zero. */
638                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
639         }
640         spin_unlock_irqrestore(&tp->indirect_lock, flags);
641 }
642
643 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
644 {
645         unsigned long flags;
646
647         if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
648             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
649                 *val = 0;
650                 return;
651         }
652
653         spin_lock_irqsave(&tp->indirect_lock, flags);
654         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
655                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
656                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
657
658                 /* Always leave this as zero. */
659                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
660         } else {
661                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
662                 *val = tr32(TG3PCI_MEM_WIN_DATA);
663
664                 /* Always leave this as zero. */
665                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
666         }
667         spin_unlock_irqrestore(&tp->indirect_lock, flags);
668 }
669
670 static void tg3_ape_lock_init(struct tg3 *tp)
671 {
672         int i;
673         u32 regbase, bit;
674
675         if (tg3_asic_rev(tp) == ASIC_REV_5761)
676                 regbase = TG3_APE_LOCK_GRANT;
677         else
678                 regbase = TG3_APE_PER_LOCK_GRANT;
679
680         /* Make sure the driver hasn't any stale locks. */
681         for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
682                 switch (i) {
683                 case TG3_APE_LOCK_PHY0:
684                 case TG3_APE_LOCK_PHY1:
685                 case TG3_APE_LOCK_PHY2:
686                 case TG3_APE_LOCK_PHY3:
687                         bit = APE_LOCK_GRANT_DRIVER;
688                         break;
689                 default:
690                         if (!tp->pci_fn)
691                                 bit = APE_LOCK_GRANT_DRIVER;
692                         else
693                                 bit = 1 << tp->pci_fn;
694                 }
695                 tg3_ape_write32(tp, regbase + 4 * i, bit);
696         }
697
698 }
699
700 static int tg3_ape_lock(struct tg3 *tp, int locknum)
701 {
702         int i, off;
703         int ret = 0;
704         u32 status, req, gnt, bit;
705
706         if (!tg3_flag(tp, ENABLE_APE))
707                 return 0;
708
709         switch (locknum) {
710         case TG3_APE_LOCK_GPIO:
711                 if (tg3_asic_rev(tp) == ASIC_REV_5761)
712                         return 0;
713         case TG3_APE_LOCK_GRC:
714         case TG3_APE_LOCK_MEM:
715                 if (!tp->pci_fn)
716                         bit = APE_LOCK_REQ_DRIVER;
717                 else
718                         bit = 1 << tp->pci_fn;
719                 break;
720         case TG3_APE_LOCK_PHY0:
721         case TG3_APE_LOCK_PHY1:
722         case TG3_APE_LOCK_PHY2:
723         case TG3_APE_LOCK_PHY3:
724                 bit = APE_LOCK_REQ_DRIVER;
725                 break;
726         default:
727                 return -EINVAL;
728         }
729
730         if (tg3_asic_rev(tp) == ASIC_REV_5761) {
731                 req = TG3_APE_LOCK_REQ;
732                 gnt = TG3_APE_LOCK_GRANT;
733         } else {
734                 req = TG3_APE_PER_LOCK_REQ;
735                 gnt = TG3_APE_PER_LOCK_GRANT;
736         }
737
738         off = 4 * locknum;
739
740         tg3_ape_write32(tp, req + off, bit);
741
742         /* Wait for up to 1 millisecond to acquire lock. */
743         for (i = 0; i < 100; i++) {
744                 status = tg3_ape_read32(tp, gnt + off);
745                 if (status == bit)
746                         break;
747                 udelay(10);
748         }
749
750         if (status != bit) {
751                 /* Revoke the lock request. */
752                 tg3_ape_write32(tp, gnt + off, bit);
753                 ret = -EBUSY;
754         }
755
756         return ret;
757 }
758
759 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
760 {
761         u32 gnt, bit;
762
763         if (!tg3_flag(tp, ENABLE_APE))
764                 return;
765
766         switch (locknum) {
767         case TG3_APE_LOCK_GPIO:
768                 if (tg3_asic_rev(tp) == ASIC_REV_5761)
769                         return;
770         case TG3_APE_LOCK_GRC:
771         case TG3_APE_LOCK_MEM:
772                 if (!tp->pci_fn)
773                         bit = APE_LOCK_GRANT_DRIVER;
774                 else
775                         bit = 1 << tp->pci_fn;
776                 break;
777         case TG3_APE_LOCK_PHY0:
778         case TG3_APE_LOCK_PHY1:
779         case TG3_APE_LOCK_PHY2:
780         case TG3_APE_LOCK_PHY3:
781                 bit = APE_LOCK_GRANT_DRIVER;
782                 break;
783         default:
784                 return;
785         }
786
787         if (tg3_asic_rev(tp) == ASIC_REV_5761)
788                 gnt = TG3_APE_LOCK_GRANT;
789         else
790                 gnt = TG3_APE_PER_LOCK_GRANT;
791
792         tg3_ape_write32(tp, gnt + 4 * locknum, bit);
793 }
794
795 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
796 {
797         u32 apedata;
798
799         while (timeout_us) {
800                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
801                         return -EBUSY;
802
803                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
804                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
805                         break;
806
807                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
808
809                 udelay(10);
810                 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
811         }
812
813         return timeout_us ? 0 : -EBUSY;
814 }
815
816 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
817 {
818         u32 i, apedata;
819
820         for (i = 0; i < timeout_us / 10; i++) {
821                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
822
823                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
824                         break;
825
826                 udelay(10);
827         }
828
829         return i == timeout_us / 10;
830 }
831
832 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
833                                    u32 len)
834 {
835         int err;
836         u32 i, bufoff, msgoff, maxlen, apedata;
837
838         if (!tg3_flag(tp, APE_HAS_NCSI))
839                 return 0;
840
841         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
842         if (apedata != APE_SEG_SIG_MAGIC)
843                 return -ENODEV;
844
845         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
846         if (!(apedata & APE_FW_STATUS_READY))
847                 return -EAGAIN;
848
849         bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
850                  TG3_APE_SHMEM_BASE;
851         msgoff = bufoff + 2 * sizeof(u32);
852         maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
853
854         while (len) {
855                 u32 length;
856
857                 /* Cap xfer sizes to scratchpad limits. */
858                 length = (len > maxlen) ? maxlen : len;
859                 len -= length;
860
861                 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
862                 if (!(apedata & APE_FW_STATUS_READY))
863                         return -EAGAIN;
864
865                 /* Wait for up to 1 msec for APE to service previous event. */
866                 err = tg3_ape_event_lock(tp, 1000);
867                 if (err)
868                         return err;
869
870                 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
871                           APE_EVENT_STATUS_SCRTCHPD_READ |
872                           APE_EVENT_STATUS_EVENT_PENDING;
873                 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
874
875                 tg3_ape_write32(tp, bufoff, base_off);
876                 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
877
878                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
879                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
880
881                 base_off += length;
882
883                 if (tg3_ape_wait_for_event(tp, 30000))
884                         return -EAGAIN;
885
886                 for (i = 0; length; i += 4, length -= 4) {
887                         u32 val = tg3_ape_read32(tp, msgoff + i);
888                         memcpy(data, &val, sizeof(u32));
889                         data++;
890                 }
891         }
892
893         return 0;
894 }
895
896 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
897 {
898         int err;
899         u32 apedata;
900
901         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
902         if (apedata != APE_SEG_SIG_MAGIC)
903                 return -EAGAIN;
904
905         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
906         if (!(apedata & APE_FW_STATUS_READY))
907                 return -EAGAIN;
908
909         /* Wait for up to 1 millisecond for APE to service previous event. */
910         err = tg3_ape_event_lock(tp, 1000);
911         if (err)
912                 return err;
913
914         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
915                         event | APE_EVENT_STATUS_EVENT_PENDING);
916
917         tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
918         tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
919
920         return 0;
921 }
922
923 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
924 {
925         u32 event;
926         u32 apedata;
927
928         if (!tg3_flag(tp, ENABLE_APE))
929                 return;
930
931         switch (kind) {
932         case RESET_KIND_INIT:
933                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
934                                 APE_HOST_SEG_SIG_MAGIC);
935                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
936                                 APE_HOST_SEG_LEN_MAGIC);
937                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
938                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
939                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
940                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
941                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
942                                 APE_HOST_BEHAV_NO_PHYLOCK);
943                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
944                                     TG3_APE_HOST_DRVR_STATE_START);
945
946                 event = APE_EVENT_STATUS_STATE_START;
947                 break;
948         case RESET_KIND_SHUTDOWN:
949                 /* With the interface we are currently using,
950                  * APE does not track driver state.  Wiping
951                  * out the HOST SEGMENT SIGNATURE forces
952                  * the APE to assume OS absent status.
953                  */
954                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
955
956                 if (device_may_wakeup(&tp->pdev->dev) &&
957                     tg3_flag(tp, WOL_ENABLE)) {
958                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
959                                             TG3_APE_HOST_WOL_SPEED_AUTO);
960                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
961                 } else
962                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
963
964                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
965
966                 event = APE_EVENT_STATUS_STATE_UNLOAD;
967                 break;
968         case RESET_KIND_SUSPEND:
969                 event = APE_EVENT_STATUS_STATE_SUSPEND;
970                 break;
971         default:
972                 return;
973         }
974
975         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
976
977         tg3_ape_send_event(tp, event);
978 }
979
980 static void tg3_disable_ints(struct tg3 *tp)
981 {
982         int i;
983
984         tw32(TG3PCI_MISC_HOST_CTRL,
985              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
986         for (i = 0; i < tp->irq_max; i++)
987                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
988 }
989
990 static void tg3_enable_ints(struct tg3 *tp)
991 {
992         int i;
993
994         tp->irq_sync = 0;
995         wmb();
996
997         tw32(TG3PCI_MISC_HOST_CTRL,
998              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
999
1000         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1001         for (i = 0; i < tp->irq_cnt; i++) {
1002                 struct tg3_napi *tnapi = &tp->napi[i];
1003
1004                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1005                 if (tg3_flag(tp, 1SHOT_MSI))
1006                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1007
1008                 tp->coal_now |= tnapi->coal_now;
1009         }
1010
1011         /* Force an initial interrupt */
1012         if (!tg3_flag(tp, TAGGED_STATUS) &&
1013             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1014                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1015         else
1016                 tw32(HOSTCC_MODE, tp->coal_now);
1017
1018         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1019 }
1020
1021 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1022 {
1023         struct tg3 *tp = tnapi->tp;
1024         struct tg3_hw_status *sblk = tnapi->hw_status;
1025         unsigned int work_exists = 0;
1026
1027         /* check for phy events */
1028         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1029                 if (sblk->status & SD_STATUS_LINK_CHG)
1030                         work_exists = 1;
1031         }
1032
1033         /* check for TX work to do */
1034         if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1035                 work_exists = 1;
1036
1037         /* check for RX work to do */
1038         if (tnapi->rx_rcb_prod_idx &&
1039             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1040                 work_exists = 1;
1041
1042         return work_exists;
1043 }
1044
1045 /* tg3_int_reenable
1046  *  similar to tg3_enable_ints, but it accurately determines whether there
1047  *  is new work pending and can return without flushing the PIO write
1048  *  which reenables interrupts
1049  */
1050 static void tg3_int_reenable(struct tg3_napi *tnapi)
1051 {
1052         struct tg3 *tp = tnapi->tp;
1053
1054         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1055         mmiowb();
1056
1057         /* When doing tagged status, this work check is unnecessary.
1058          * The last_tag we write above tells the chip which piece of
1059          * work we've completed.
1060          */
1061         if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1062                 tw32(HOSTCC_MODE, tp->coalesce_mode |
1063                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
1064 }
1065
1066 static void tg3_switch_clocks(struct tg3 *tp)
1067 {
1068         u32 clock_ctrl;
1069         u32 orig_clock_ctrl;
1070
1071         if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1072                 return;
1073
1074         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1075
1076         orig_clock_ctrl = clock_ctrl;
1077         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1078                        CLOCK_CTRL_CLKRUN_OENABLE |
1079                        0x1f);
1080         tp->pci_clock_ctrl = clock_ctrl;
1081
1082         if (tg3_flag(tp, 5705_PLUS)) {
1083                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1084                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1085                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1086                 }
1087         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1088                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1089                             clock_ctrl |
1090                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1091                             40);
1092                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
1094                             40);
1095         }
1096         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1097 }
1098
1099 #define PHY_BUSY_LOOPS  5000
1100
1101 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1102                          u32 *val)
1103 {
1104         u32 frame_val;
1105         unsigned int loops;
1106         int ret;
1107
1108         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1109                 tw32_f(MAC_MI_MODE,
1110                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1111                 udelay(80);
1112         }
1113
1114         tg3_ape_lock(tp, tp->phy_ape_lock);
1115
1116         *val = 0x0;
1117
1118         frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1119                       MI_COM_PHY_ADDR_MASK);
1120         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1121                       MI_COM_REG_ADDR_MASK);
1122         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1123
1124         tw32_f(MAC_MI_COM, frame_val);
1125
1126         loops = PHY_BUSY_LOOPS;
1127         while (loops != 0) {
1128                 udelay(10);
1129                 frame_val = tr32(MAC_MI_COM);
1130
1131                 if ((frame_val & MI_COM_BUSY) == 0) {
1132                         udelay(5);
1133                         frame_val = tr32(MAC_MI_COM);
1134                         break;
1135                 }
1136                 loops -= 1;
1137         }
1138
1139         ret = -EBUSY;
1140         if (loops != 0) {
1141                 *val = frame_val & MI_COM_DATA_MASK;
1142                 ret = 0;
1143         }
1144
1145         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1146                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1147                 udelay(80);
1148         }
1149
1150         tg3_ape_unlock(tp, tp->phy_ape_lock);
1151
1152         return ret;
1153 }
1154
1155 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1156 {
1157         return __tg3_readphy(tp, tp->phy_addr, reg, val);
1158 }
1159
1160 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1161                           u32 val)
1162 {
1163         u32 frame_val;
1164         unsigned int loops;
1165         int ret;
1166
1167         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1168             (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1169                 return 0;
1170
1171         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1172                 tw32_f(MAC_MI_MODE,
1173                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1174                 udelay(80);
1175         }
1176
1177         tg3_ape_lock(tp, tp->phy_ape_lock);
1178
1179         frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1180                       MI_COM_PHY_ADDR_MASK);
1181         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1182                       MI_COM_REG_ADDR_MASK);
1183         frame_val |= (val & MI_COM_DATA_MASK);
1184         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1185
1186         tw32_f(MAC_MI_COM, frame_val);
1187
1188         loops = PHY_BUSY_LOOPS;
1189         while (loops != 0) {
1190                 udelay(10);
1191                 frame_val = tr32(MAC_MI_COM);
1192                 if ((frame_val & MI_COM_BUSY) == 0) {
1193                         udelay(5);
1194                         frame_val = tr32(MAC_MI_COM);
1195                         break;
1196                 }
1197                 loops -= 1;
1198         }
1199
1200         ret = -EBUSY;
1201         if (loops != 0)
1202                 ret = 0;
1203
1204         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1205                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1206                 udelay(80);
1207         }
1208
1209         tg3_ape_unlock(tp, tp->phy_ape_lock);
1210
1211         return ret;
1212 }
1213
1214 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1215 {
1216         return __tg3_writephy(tp, tp->phy_addr, reg, val);
1217 }
1218
1219 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1220 {
1221         int err;
1222
1223         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1224         if (err)
1225                 goto done;
1226
1227         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1228         if (err)
1229                 goto done;
1230
1231         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1232                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1233         if (err)
1234                 goto done;
1235
1236         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1237
1238 done:
1239         return err;
1240 }
1241
1242 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1243 {
1244         int err;
1245
1246         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1247         if (err)
1248                 goto done;
1249
1250         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1251         if (err)
1252                 goto done;
1253
1254         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1255                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1256         if (err)
1257                 goto done;
1258
1259         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1260
1261 done:
1262         return err;
1263 }
1264
1265 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1266 {
1267         int err;
1268
1269         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1270         if (!err)
1271                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1272
1273         return err;
1274 }
1275
1276 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1277 {
1278         int err;
1279
1280         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1281         if (!err)
1282                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1283
1284         return err;
1285 }
1286
1287 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1288 {
1289         int err;
1290
1291         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1292                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1293                            MII_TG3_AUXCTL_SHDWSEL_MISC);
1294         if (!err)
1295                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1296
1297         return err;
1298 }
1299
1300 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1301 {
1302         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1303                 set |= MII_TG3_AUXCTL_MISC_WREN;
1304
1305         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1306 }
1307
1308 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1309 {
1310         u32 val;
1311         int err;
1312
1313         err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1314
1315         if (err)
1316                 return err;
1317         if (enable)
1318
1319                 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1320         else
1321                 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1322
1323         err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1324                                    val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1325
1326         return err;
1327 }
1328
1329 static int tg3_bmcr_reset(struct tg3 *tp)
1330 {
1331         u32 phy_control;
1332         int limit, err;
1333
1334         /* OK, reset it, and poll the BMCR_RESET bit until it
1335          * clears or we time out.
1336          */
1337         phy_control = BMCR_RESET;
1338         err = tg3_writephy(tp, MII_BMCR, phy_control);
1339         if (err != 0)
1340                 return -EBUSY;
1341
1342         limit = 5000;
1343         while (limit--) {
1344                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1345                 if (err != 0)
1346                         return -EBUSY;
1347
1348                 if ((phy_control & BMCR_RESET) == 0) {
1349                         udelay(40);
1350                         break;
1351                 }
1352                 udelay(10);
1353         }
1354         if (limit < 0)
1355                 return -EBUSY;
1356
1357         return 0;
1358 }
1359
1360 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1361 {
1362         struct tg3 *tp = bp->priv;
1363         u32 val;
1364
1365         spin_lock_bh(&tp->lock);
1366
1367         if (tg3_readphy(tp, reg, &val))
1368                 val = -EIO;
1369
1370         spin_unlock_bh(&tp->lock);
1371
1372         return val;
1373 }
1374
1375 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1376 {
1377         struct tg3 *tp = bp->priv;
1378         u32 ret = 0;
1379
1380         spin_lock_bh(&tp->lock);
1381
1382         if (tg3_writephy(tp, reg, val))
1383                 ret = -EIO;
1384
1385         spin_unlock_bh(&tp->lock);
1386
1387         return ret;
1388 }
1389
1390 static int tg3_mdio_reset(struct mii_bus *bp)
1391 {
1392         return 0;
1393 }
1394
1395 static void tg3_mdio_config_5785(struct tg3 *tp)
1396 {
1397         u32 val;
1398         struct phy_device *phydev;
1399
1400         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1401         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1402         case PHY_ID_BCM50610:
1403         case PHY_ID_BCM50610M:
1404                 val = MAC_PHYCFG2_50610_LED_MODES;
1405                 break;
1406         case PHY_ID_BCMAC131:
1407                 val = MAC_PHYCFG2_AC131_LED_MODES;
1408                 break;
1409         case PHY_ID_RTL8211C:
1410                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1411                 break;
1412         case PHY_ID_RTL8201E:
1413                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1414                 break;
1415         default:
1416                 return;
1417         }
1418
1419         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1420                 tw32(MAC_PHYCFG2, val);
1421
1422                 val = tr32(MAC_PHYCFG1);
1423                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1424                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1425                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1426                 tw32(MAC_PHYCFG1, val);
1427
1428                 return;
1429         }
1430
1431         if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1432                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1433                        MAC_PHYCFG2_FMODE_MASK_MASK |
1434                        MAC_PHYCFG2_GMODE_MASK_MASK |
1435                        MAC_PHYCFG2_ACT_MASK_MASK   |
1436                        MAC_PHYCFG2_QUAL_MASK_MASK |
1437                        MAC_PHYCFG2_INBAND_ENABLE;
1438
1439         tw32(MAC_PHYCFG2, val);
1440
1441         val = tr32(MAC_PHYCFG1);
1442         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1443                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1444         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1445                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1446                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1447                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1448                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1449         }
1450         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1451                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1452         tw32(MAC_PHYCFG1, val);
1453
1454         val = tr32(MAC_EXT_RGMII_MODE);
1455         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1456                  MAC_RGMII_MODE_RX_QUALITY |
1457                  MAC_RGMII_MODE_RX_ACTIVITY |
1458                  MAC_RGMII_MODE_RX_ENG_DET |
1459                  MAC_RGMII_MODE_TX_ENABLE |
1460                  MAC_RGMII_MODE_TX_LOWPWR |
1461                  MAC_RGMII_MODE_TX_RESET);
1462         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1463                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1464                         val |= MAC_RGMII_MODE_RX_INT_B |
1465                                MAC_RGMII_MODE_RX_QUALITY |
1466                                MAC_RGMII_MODE_RX_ACTIVITY |
1467                                MAC_RGMII_MODE_RX_ENG_DET;
1468                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1469                         val |= MAC_RGMII_MODE_TX_ENABLE |
1470                                MAC_RGMII_MODE_TX_LOWPWR |
1471                                MAC_RGMII_MODE_TX_RESET;
1472         }
1473         tw32(MAC_EXT_RGMII_MODE, val);
1474 }
1475
1476 static void tg3_mdio_start(struct tg3 *tp)
1477 {
1478         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1479         tw32_f(MAC_MI_MODE, tp->mi_mode);
1480         udelay(80);
1481
1482         if (tg3_flag(tp, MDIOBUS_INITED) &&
1483             tg3_asic_rev(tp) == ASIC_REV_5785)
1484                 tg3_mdio_config_5785(tp);
1485 }
1486
1487 static int tg3_mdio_init(struct tg3 *tp)
1488 {
1489         int i;
1490         u32 reg;
1491         struct phy_device *phydev;
1492
1493         if (tg3_flag(tp, 5717_PLUS)) {
1494                 u32 is_serdes;
1495
1496                 tp->phy_addr = tp->pci_fn + 1;
1497
1498                 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1499                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1500                 else
1501                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1502                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1503                 if (is_serdes)
1504                         tp->phy_addr += 7;
1505         } else
1506                 tp->phy_addr = TG3_PHY_MII_ADDR;
1507
1508         tg3_mdio_start(tp);
1509
1510         if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1511                 return 0;
1512
1513         tp->mdio_bus = mdiobus_alloc();
1514         if (tp->mdio_bus == NULL)
1515                 return -ENOMEM;
1516
1517         tp->mdio_bus->name     = "tg3 mdio bus";
1518         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1519                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1520         tp->mdio_bus->priv     = tp;
1521         tp->mdio_bus->parent   = &tp->pdev->dev;
1522         tp->mdio_bus->read     = &tg3_mdio_read;
1523         tp->mdio_bus->write    = &tg3_mdio_write;
1524         tp->mdio_bus->reset    = &tg3_mdio_reset;
1525         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1526         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1527
1528         for (i = 0; i < PHY_MAX_ADDR; i++)
1529                 tp->mdio_bus->irq[i] = PHY_POLL;
1530
1531         /* The bus registration will look for all the PHYs on the mdio bus.
1532          * Unfortunately, it does not ensure the PHY is powered up before
1533          * accessing the PHY ID registers.  A chip reset is the
1534          * quickest way to bring the device back to an operational state..
1535          */
1536         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1537                 tg3_bmcr_reset(tp);
1538
1539         i = mdiobus_register(tp->mdio_bus);
1540         if (i) {
1541                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1542                 mdiobus_free(tp->mdio_bus);
1543                 return i;
1544         }
1545
1546         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1547
1548         if (!phydev || !phydev->drv) {
1549                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1550                 mdiobus_unregister(tp->mdio_bus);
1551                 mdiobus_free(tp->mdio_bus);
1552                 return -ENODEV;
1553         }
1554
1555         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1556         case PHY_ID_BCM57780:
1557                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1558                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1559                 break;
1560         case PHY_ID_BCM50610:
1561         case PHY_ID_BCM50610M:
1562                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1563                                      PHY_BRCM_RX_REFCLK_UNUSED |
1564                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1565                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1566                 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1567                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1568                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1569                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1570                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1571                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1572                 /* fallthru */
1573         case PHY_ID_RTL8211C:
1574                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1575                 break;
1576         case PHY_ID_RTL8201E:
1577         case PHY_ID_BCMAC131:
1578                 phydev->interface = PHY_INTERFACE_MODE_MII;
1579                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1580                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1581                 break;
1582         }
1583
1584         tg3_flag_set(tp, MDIOBUS_INITED);
1585
1586         if (tg3_asic_rev(tp) == ASIC_REV_5785)
1587                 tg3_mdio_config_5785(tp);
1588
1589         return 0;
1590 }
1591
1592 static void tg3_mdio_fini(struct tg3 *tp)
1593 {
1594         if (tg3_flag(tp, MDIOBUS_INITED)) {
1595                 tg3_flag_clear(tp, MDIOBUS_INITED);
1596                 mdiobus_unregister(tp->mdio_bus);
1597                 mdiobus_free(tp->mdio_bus);
1598         }
1599 }
1600
1601 /* tp->lock is held. */
1602 static inline void tg3_generate_fw_event(struct tg3 *tp)
1603 {
1604         u32 val;
1605
1606         val = tr32(GRC_RX_CPU_EVENT);
1607         val |= GRC_RX_CPU_DRIVER_EVENT;
1608         tw32_f(GRC_RX_CPU_EVENT, val);
1609
1610         tp->last_event_jiffies = jiffies;
1611 }
1612
1613 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1614
1615 /* tp->lock is held. */
1616 static void tg3_wait_for_event_ack(struct tg3 *tp)
1617 {
1618         int i;
1619         unsigned int delay_cnt;
1620         long time_remain;
1621
1622         /* If enough time has passed, no wait is necessary. */
1623         time_remain = (long)(tp->last_event_jiffies + 1 +
1624                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1625                       (long)jiffies;
1626         if (time_remain < 0)
1627                 return;
1628
1629         /* Check if we can shorten the wait time. */
1630         delay_cnt = jiffies_to_usecs(time_remain);
1631         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1632                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1633         delay_cnt = (delay_cnt >> 3) + 1;
1634
1635         for (i = 0; i < delay_cnt; i++) {
1636                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1637                         break;
1638                 udelay(8);
1639         }
1640 }
1641
1642 /* tp->lock is held. */
1643 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1644 {
1645         u32 reg, val;
1646
1647         val = 0;
1648         if (!tg3_readphy(tp, MII_BMCR, &reg))
1649                 val = reg << 16;
1650         if (!tg3_readphy(tp, MII_BMSR, &reg))
1651                 val |= (reg & 0xffff);
1652         *data++ = val;
1653
1654         val = 0;
1655         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1656                 val = reg << 16;
1657         if (!tg3_readphy(tp, MII_LPA, &reg))
1658                 val |= (reg & 0xffff);
1659         *data++ = val;
1660
1661         val = 0;
1662         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1663                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1664                         val = reg << 16;
1665                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1666                         val |= (reg & 0xffff);
1667         }
1668         *data++ = val;
1669
1670         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1671                 val = reg << 16;
1672         else
1673                 val = 0;
1674         *data++ = val;
1675 }
1676
1677 /* tp->lock is held. */
1678 static void tg3_ump_link_report(struct tg3 *tp)
1679 {
1680         u32 data[4];
1681
1682         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1683                 return;
1684
1685         tg3_phy_gather_ump_data(tp, data);
1686
1687         tg3_wait_for_event_ack(tp);
1688
1689         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1690         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1691         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1692         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1693         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1694         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1695
1696         tg3_generate_fw_event(tp);
1697 }
1698
1699 /* tp->lock is held. */
1700 static void tg3_stop_fw(struct tg3 *tp)
1701 {
1702         if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1703                 /* Wait for RX cpu to ACK the previous event. */
1704                 tg3_wait_for_event_ack(tp);
1705
1706                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1707
1708                 tg3_generate_fw_event(tp);
1709
1710                 /* Wait for RX cpu to ACK this event. */
1711                 tg3_wait_for_event_ack(tp);
1712         }
1713 }
1714
1715 /* tp->lock is held. */
1716 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1717 {
1718         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1719                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1720
1721         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1722                 switch (kind) {
1723                 case RESET_KIND_INIT:
1724                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1725                                       DRV_STATE_START);
1726                         break;
1727
1728                 case RESET_KIND_SHUTDOWN:
1729                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1730                                       DRV_STATE_UNLOAD);
1731                         break;
1732
1733                 case RESET_KIND_SUSPEND:
1734                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1735                                       DRV_STATE_SUSPEND);
1736                         break;
1737
1738                 default:
1739                         break;
1740                 }
1741         }
1742
1743         if (kind == RESET_KIND_INIT ||
1744             kind == RESET_KIND_SUSPEND)
1745                 tg3_ape_driver_state_change(tp, kind);
1746 }
1747
1748 /* tp->lock is held. */
1749 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1750 {
1751         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1752                 switch (kind) {
1753                 case RESET_KIND_INIT:
1754                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1755                                       DRV_STATE_START_DONE);
1756                         break;
1757
1758                 case RESET_KIND_SHUTDOWN:
1759                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1760                                       DRV_STATE_UNLOAD_DONE);
1761                         break;
1762
1763                 default:
1764                         break;
1765                 }
1766         }
1767
1768         if (kind == RESET_KIND_SHUTDOWN)
1769                 tg3_ape_driver_state_change(tp, kind);
1770 }
1771
1772 /* tp->lock is held. */
1773 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1774 {
1775         if (tg3_flag(tp, ENABLE_ASF)) {
1776                 switch (kind) {
1777                 case RESET_KIND_INIT:
1778                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1779                                       DRV_STATE_START);
1780                         break;
1781
1782                 case RESET_KIND_SHUTDOWN:
1783                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1784                                       DRV_STATE_UNLOAD);
1785                         break;
1786
1787                 case RESET_KIND_SUSPEND:
1788                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1789                                       DRV_STATE_SUSPEND);
1790                         break;
1791
1792                 default:
1793                         break;
1794                 }
1795         }
1796 }
1797
1798 static int tg3_poll_fw(struct tg3 *tp)
1799 {
1800         int i;
1801         u32 val;
1802
1803         if (tg3_flag(tp, IS_SSB_CORE)) {
1804                 /* We don't use firmware. */
1805                 return 0;
1806         }
1807
1808         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1809                 /* Wait up to 20ms for init done. */
1810                 for (i = 0; i < 200; i++) {
1811                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1812                                 return 0;
1813                         udelay(100);
1814                 }
1815                 return -ENODEV;
1816         }
1817
1818         /* Wait for firmware initialization to complete. */
1819         for (i = 0; i < 100000; i++) {
1820                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1821                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1822                         break;
1823                 udelay(10);
1824         }
1825
1826         /* Chip might not be fitted with firmware.  Some Sun onboard
1827          * parts are configured like that.  So don't signal the timeout
1828          * of the above loop as an error, but do report the lack of
1829          * running firmware once.
1830          */
1831         if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1832                 tg3_flag_set(tp, NO_FWARE_REPORTED);
1833
1834                 netdev_info(tp->dev, "No firmware running\n");
1835         }
1836
1837         if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1838                 /* The 57765 A0 needs a little more
1839                  * time to do some important work.
1840                  */
1841                 mdelay(10);
1842         }
1843
1844         return 0;
1845 }
1846
1847 static void tg3_link_report(struct tg3 *tp)
1848 {
1849         if (!netif_carrier_ok(tp->dev)) {
1850                 netif_info(tp, link, tp->dev, "Link is down\n");
1851                 tg3_ump_link_report(tp);
1852         } else if (netif_msg_link(tp)) {
1853                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1854                             (tp->link_config.active_speed == SPEED_1000 ?
1855                              1000 :
1856                              (tp->link_config.active_speed == SPEED_100 ?
1857                               100 : 10)),
1858                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1859                              "full" : "half"));
1860
1861                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1862                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1863                             "on" : "off",
1864                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1865                             "on" : "off");
1866
1867                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1868                         netdev_info(tp->dev, "EEE is %s\n",
1869                                     tp->setlpicnt ? "enabled" : "disabled");
1870
1871                 tg3_ump_link_report(tp);
1872         }
1873
1874         tp->link_up = netif_carrier_ok(tp->dev);
1875 }
1876
1877 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1878 {
1879         u32 flowctrl = 0;
1880
1881         if (adv & ADVERTISE_PAUSE_CAP) {
1882                 flowctrl |= FLOW_CTRL_RX;
1883                 if (!(adv & ADVERTISE_PAUSE_ASYM))
1884                         flowctrl |= FLOW_CTRL_TX;
1885         } else if (adv & ADVERTISE_PAUSE_ASYM)
1886                 flowctrl |= FLOW_CTRL_TX;
1887
1888         return flowctrl;
1889 }
1890
1891 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1892 {
1893         u16 miireg;
1894
1895         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1896                 miireg = ADVERTISE_1000XPAUSE;
1897         else if (flow_ctrl & FLOW_CTRL_TX)
1898                 miireg = ADVERTISE_1000XPSE_ASYM;
1899         else if (flow_ctrl & FLOW_CTRL_RX)
1900                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1901         else
1902                 miireg = 0;
1903
1904         return miireg;
1905 }
1906
1907 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1908 {
1909         u32 flowctrl = 0;
1910
1911         if (adv & ADVERTISE_1000XPAUSE) {
1912                 flowctrl |= FLOW_CTRL_RX;
1913                 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1914                         flowctrl |= FLOW_CTRL_TX;
1915         } else if (adv & ADVERTISE_1000XPSE_ASYM)
1916                 flowctrl |= FLOW_CTRL_TX;
1917
1918         return flowctrl;
1919 }
1920
1921 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1922 {
1923         u8 cap = 0;
1924
1925         if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1926                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1927         } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1928                 if (lcladv & ADVERTISE_1000XPAUSE)
1929                         cap = FLOW_CTRL_RX;
1930                 if (rmtadv & ADVERTISE_1000XPAUSE)
1931                         cap = FLOW_CTRL_TX;
1932         }
1933
1934         return cap;
1935 }
1936
1937 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1938 {
1939         u8 autoneg;
1940         u8 flowctrl = 0;
1941         u32 old_rx_mode = tp->rx_mode;
1942         u32 old_tx_mode = tp->tx_mode;
1943
1944         if (tg3_flag(tp, USE_PHYLIB))
1945                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1946         else
1947                 autoneg = tp->link_config.autoneg;
1948
1949         if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1950                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1951                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1952                 else
1953                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1954         } else
1955                 flowctrl = tp->link_config.flowctrl;
1956
1957         tp->link_config.active_flowctrl = flowctrl;
1958
1959         if (flowctrl & FLOW_CTRL_RX)
1960                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1961         else
1962                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1963
1964         if (old_rx_mode != tp->rx_mode)
1965                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1966
1967         if (flowctrl & FLOW_CTRL_TX)
1968                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1969         else
1970                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1971
1972         if (old_tx_mode != tp->tx_mode)
1973                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1974 }
1975
1976 static void tg3_adjust_link(struct net_device *dev)
1977 {
1978         u8 oldflowctrl, linkmesg = 0;
1979         u32 mac_mode, lcl_adv, rmt_adv;
1980         struct tg3 *tp = netdev_priv(dev);
1981         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1982
1983         spin_lock_bh(&tp->lock);
1984
1985         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1986                                     MAC_MODE_HALF_DUPLEX);
1987
1988         oldflowctrl = tp->link_config.active_flowctrl;
1989
1990         if (phydev->link) {
1991                 lcl_adv = 0;
1992                 rmt_adv = 0;
1993
1994                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1995                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1996                 else if (phydev->speed == SPEED_1000 ||
1997                          tg3_asic_rev(tp) != ASIC_REV_5785)
1998                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1999                 else
2000                         mac_mode |= MAC_MODE_PORT_MODE_MII;
2001
2002                 if (phydev->duplex == DUPLEX_HALF)
2003                         mac_mode |= MAC_MODE_HALF_DUPLEX;
2004                 else {
2005                         lcl_adv = mii_advertise_flowctrl(
2006                                   tp->link_config.flowctrl);
2007
2008                         if (phydev->pause)
2009                                 rmt_adv = LPA_PAUSE_CAP;
2010                         if (phydev->asym_pause)
2011                                 rmt_adv |= LPA_PAUSE_ASYM;
2012                 }
2013
2014                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2015         } else
2016                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2017
2018         if (mac_mode != tp->mac_mode) {
2019                 tp->mac_mode = mac_mode;
2020                 tw32_f(MAC_MODE, tp->mac_mode);
2021                 udelay(40);
2022         }
2023
2024         if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2025                 if (phydev->speed == SPEED_10)
2026                         tw32(MAC_MI_STAT,
2027                              MAC_MI_STAT_10MBPS_MODE |
2028                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2029                 else
2030                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2031         }
2032
2033         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2034                 tw32(MAC_TX_LENGTHS,
2035                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2036                       (6 << TX_LENGTHS_IPG_SHIFT) |
2037                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2038         else
2039                 tw32(MAC_TX_LENGTHS,
2040                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2041                       (6 << TX_LENGTHS_IPG_SHIFT) |
2042                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2043
2044         if (phydev->link != tp->old_link ||
2045             phydev->speed != tp->link_config.active_speed ||
2046             phydev->duplex != tp->link_config.active_duplex ||
2047             oldflowctrl != tp->link_config.active_flowctrl)
2048                 linkmesg = 1;
2049
2050         tp->old_link = phydev->link;
2051         tp->link_config.active_speed = phydev->speed;
2052         tp->link_config.active_duplex = phydev->duplex;
2053
2054         spin_unlock_bh(&tp->lock);
2055
2056         if (linkmesg)
2057                 tg3_link_report(tp);
2058 }
2059
2060 static int tg3_phy_init(struct tg3 *tp)
2061 {
2062         struct phy_device *phydev;
2063
2064         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2065                 return 0;
2066
2067         /* Bring the PHY back to a known state. */
2068         tg3_bmcr_reset(tp);
2069
2070         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2071
2072         /* Attach the MAC to the PHY. */
2073         phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2074                              tg3_adjust_link, phydev->interface);
2075         if (IS_ERR(phydev)) {
2076                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2077                 return PTR_ERR(phydev);
2078         }
2079
2080         /* Mask with MAC supported features. */
2081         switch (phydev->interface) {
2082         case PHY_INTERFACE_MODE_GMII:
2083         case PHY_INTERFACE_MODE_RGMII:
2084                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2085                         phydev->supported &= (PHY_GBIT_FEATURES |
2086                                               SUPPORTED_Pause |
2087                                               SUPPORTED_Asym_Pause);
2088                         break;
2089                 }
2090                 /* fallthru */
2091         case PHY_INTERFACE_MODE_MII:
2092                 phydev->supported &= (PHY_BASIC_FEATURES |
2093                                       SUPPORTED_Pause |
2094                                       SUPPORTED_Asym_Pause);
2095                 break;
2096         default:
2097                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2098                 return -EINVAL;
2099         }
2100
2101         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2102
2103         phydev->advertising = phydev->supported;
2104
2105         return 0;
2106 }
2107
2108 static void tg3_phy_start(struct tg3 *tp)
2109 {
2110         struct phy_device *phydev;
2111
2112         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2113                 return;
2114
2115         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2116
2117         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2118                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2119                 phydev->speed = tp->link_config.speed;
2120                 phydev->duplex = tp->link_config.duplex;
2121                 phydev->autoneg = tp->link_config.autoneg;
2122                 phydev->advertising = tp->link_config.advertising;
2123         }
2124
2125         phy_start(phydev);
2126
2127         phy_start_aneg(phydev);
2128 }
2129
2130 static void tg3_phy_stop(struct tg3 *tp)
2131 {
2132         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2133                 return;
2134
2135         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2136 }
2137
2138 static void tg3_phy_fini(struct tg3 *tp)
2139 {
2140         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2141                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2142                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2143         }
2144 }
2145
2146 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2147 {
2148         int err;
2149         u32 val;
2150
2151         if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2152                 return 0;
2153
2154         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2155                 /* Cannot do read-modify-write on 5401 */
2156                 err = tg3_phy_auxctl_write(tp,
2157                                            MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2158                                            MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2159                                            0x4c20);
2160                 goto done;
2161         }
2162
2163         err = tg3_phy_auxctl_read(tp,
2164                                   MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2165         if (err)
2166                 return err;
2167
2168         val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2169         err = tg3_phy_auxctl_write(tp,
2170                                    MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2171
2172 done:
2173         return err;
2174 }
2175
2176 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2177 {
2178         u32 phytest;
2179
2180         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2181                 u32 phy;
2182
2183                 tg3_writephy(tp, MII_TG3_FET_TEST,
2184                              phytest | MII_TG3_FET_SHADOW_EN);
2185                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2186                         if (enable)
2187                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2188                         else
2189                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2190                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2191                 }
2192                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2193         }
2194 }
2195
2196 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2197 {
2198         u32 reg;
2199
2200         if (!tg3_flag(tp, 5705_PLUS) ||
2201             (tg3_flag(tp, 5717_PLUS) &&
2202              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2203                 return;
2204
2205         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2206                 tg3_phy_fet_toggle_apd(tp, enable);
2207                 return;
2208         }
2209
2210         reg = MII_TG3_MISC_SHDW_WREN |
2211               MII_TG3_MISC_SHDW_SCR5_SEL |
2212               MII_TG3_MISC_SHDW_SCR5_LPED |
2213               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2214               MII_TG3_MISC_SHDW_SCR5_SDTL |
2215               MII_TG3_MISC_SHDW_SCR5_C125OE;
2216         if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2217                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2218
2219         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2220
2221
2222         reg = MII_TG3_MISC_SHDW_WREN |
2223               MII_TG3_MISC_SHDW_APD_SEL |
2224               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2225         if (enable)
2226                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2227
2228         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2229 }
2230
2231 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2232 {
2233         u32 phy;
2234
2235         if (!tg3_flag(tp, 5705_PLUS) ||
2236             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2237                 return;
2238
2239         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2240                 u32 ephy;
2241
2242                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2243                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2244
2245                         tg3_writephy(tp, MII_TG3_FET_TEST,
2246                                      ephy | MII_TG3_FET_SHADOW_EN);
2247                         if (!tg3_readphy(tp, reg, &phy)) {
2248                                 if (enable)
2249                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2250                                 else
2251                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2252                                 tg3_writephy(tp, reg, phy);
2253                         }
2254                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2255                 }
2256         } else {
2257                 int ret;
2258
2259                 ret = tg3_phy_auxctl_read(tp,
2260                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2261                 if (!ret) {
2262                         if (enable)
2263                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2264                         else
2265                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2266                         tg3_phy_auxctl_write(tp,
2267                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2268                 }
2269         }
2270 }
2271
2272 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2273 {
2274         int ret;
2275         u32 val;
2276
2277         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2278                 return;
2279
2280         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2281         if (!ret)
2282                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2283                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2284 }
2285
2286 static void tg3_phy_apply_otp(struct tg3 *tp)
2287 {
2288         u32 otp, phy;
2289
2290         if (!tp->phy_otp)
2291                 return;
2292
2293         otp = tp->phy_otp;
2294
2295         if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2296                 return;
2297
2298         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2299         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2300         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2301
2302         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2303               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2304         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2305
2306         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2307         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2308         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2309
2310         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2311         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2312
2313         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2314         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2315
2316         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2317               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2318         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2319
2320         tg3_phy_toggle_auxctl_smdsp(tp, false);
2321 }
2322
2323 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2324 {
2325         u32 val;
2326
2327         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2328                 return;
2329
2330         tp->setlpicnt = 0;
2331
2332         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2333             current_link_up == 1 &&
2334             tp->link_config.active_duplex == DUPLEX_FULL &&
2335             (tp->link_config.active_speed == SPEED_100 ||
2336              tp->link_config.active_speed == SPEED_1000)) {
2337                 u32 eeectl;
2338
2339                 if (tp->link_config.active_speed == SPEED_1000)
2340                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2341                 else
2342                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2343
2344                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2345
2346                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2347                                   TG3_CL45_D7_EEERES_STAT, &val);
2348
2349                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2350                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2351                         tp->setlpicnt = 2;
2352         }
2353
2354         if (!tp->setlpicnt) {
2355                 if (current_link_up == 1 &&
2356                    !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2357                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2358                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2359                 }
2360
2361                 val = tr32(TG3_CPMU_EEE_MODE);
2362                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2363         }
2364 }
2365
2366 static void tg3_phy_eee_enable(struct tg3 *tp)
2367 {
2368         u32 val;
2369
2370         if (tp->link_config.active_speed == SPEED_1000 &&
2371             (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2372              tg3_asic_rev(tp) == ASIC_REV_5719 ||
2373              tg3_flag(tp, 57765_CLASS)) &&
2374             !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2375                 val = MII_TG3_DSP_TAP26_ALNOKO |
2376                       MII_TG3_DSP_TAP26_RMRXSTO;
2377                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2378                 tg3_phy_toggle_auxctl_smdsp(tp, false);
2379         }
2380
2381         val = tr32(TG3_CPMU_EEE_MODE);
2382         tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2383 }
2384
2385 static int tg3_wait_macro_done(struct tg3 *tp)
2386 {
2387         int limit = 100;
2388
2389         while (limit--) {
2390                 u32 tmp32;
2391
2392                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2393                         if ((tmp32 & 0x1000) == 0)
2394                                 break;
2395                 }
2396         }
2397         if (limit < 0)
2398                 return -EBUSY;
2399
2400         return 0;
2401 }
2402
2403 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2404 {
2405         static const u32 test_pat[4][6] = {
2406         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2407         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2408         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2409         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2410         };
2411         int chan;
2412
2413         for (chan = 0; chan < 4; chan++) {
2414                 int i;
2415
2416                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2417                              (chan * 0x2000) | 0x0200);
2418                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2419
2420                 for (i = 0; i < 6; i++)
2421                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2422                                      test_pat[chan][i]);
2423
2424                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2425                 if (tg3_wait_macro_done(tp)) {
2426                         *resetp = 1;
2427                         return -EBUSY;
2428                 }
2429
2430                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2431                              (chan * 0x2000) | 0x0200);
2432                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2433                 if (tg3_wait_macro_done(tp)) {
2434                         *resetp = 1;
2435                         return -EBUSY;
2436                 }
2437
2438                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2439                 if (tg3_wait_macro_done(tp)) {
2440                         *resetp = 1;
2441                         return -EBUSY;
2442                 }
2443
2444                 for (i = 0; i < 6; i += 2) {
2445                         u32 low, high;
2446
2447                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2448                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2449                             tg3_wait_macro_done(tp)) {
2450                                 *resetp = 1;
2451                                 return -EBUSY;
2452                         }
2453                         low &= 0x7fff;
2454                         high &= 0x000f;
2455                         if (low != test_pat[chan][i] ||
2456                             high != test_pat[chan][i+1]) {
2457                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2458                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2459                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2460
2461                                 return -EBUSY;
2462                         }
2463                 }
2464         }
2465
2466         return 0;
2467 }
2468
2469 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2470 {
2471         int chan;
2472
2473         for (chan = 0; chan < 4; chan++) {
2474                 int i;
2475
2476                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2477                              (chan * 0x2000) | 0x0200);
2478                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2479                 for (i = 0; i < 6; i++)
2480                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2481                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2482                 if (tg3_wait_macro_done(tp))
2483                         return -EBUSY;
2484         }
2485
2486         return 0;
2487 }
2488
2489 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2490 {
2491         u32 reg32, phy9_orig;
2492         int retries, do_phy_reset, err;
2493
2494         retries = 10;
2495         do_phy_reset = 1;
2496         do {
2497                 if (do_phy_reset) {
2498                         err = tg3_bmcr_reset(tp);
2499                         if (err)
2500                                 return err;
2501                         do_phy_reset = 0;
2502                 }
2503
2504                 /* Disable transmitter and interrupt.  */
2505                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2506                         continue;
2507
2508                 reg32 |= 0x3000;
2509                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2510
2511                 /* Set full-duplex, 1000 mbps.  */
2512                 tg3_writephy(tp, MII_BMCR,
2513                              BMCR_FULLDPLX | BMCR_SPEED1000);
2514
2515                 /* Set to master mode.  */
2516                 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2517                         continue;
2518
2519                 tg3_writephy(tp, MII_CTRL1000,
2520                              CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2521
2522                 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2523                 if (err)
2524                         return err;
2525
2526                 /* Block the PHY control access.  */
2527                 tg3_phydsp_write(tp, 0x8005, 0x0800);
2528
2529                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2530                 if (!err)
2531                         break;
2532         } while (--retries);
2533
2534         err = tg3_phy_reset_chanpat(tp);
2535         if (err)
2536                 return err;
2537
2538         tg3_phydsp_write(tp, 0x8005, 0x0000);
2539
2540         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2541         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2542
2543         tg3_phy_toggle_auxctl_smdsp(tp, false);
2544
2545         tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2546
2547         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2548                 reg32 &= ~0x3000;
2549                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2550         } else if (!err)
2551                 err = -EBUSY;
2552
2553         return err;
2554 }
2555
2556 static void tg3_carrier_off(struct tg3 *tp)
2557 {
2558         netif_carrier_off(tp->dev);
2559         tp->link_up = false;
2560 }
2561
2562 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2563 {
2564         if (tg3_flag(tp, ENABLE_ASF))
2565                 netdev_warn(tp->dev,
2566                             "Management side-band traffic will be interrupted during phy settings change\n");
2567 }
2568
2569 /* This will reset the tigon3 PHY if there is no valid
2570  * link unless the FORCE argument is non-zero.
2571  */
2572 static int tg3_phy_reset(struct tg3 *tp)
2573 {
2574         u32 val, cpmuctrl;
2575         int err;
2576
2577         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2578                 val = tr32(GRC_MISC_CFG);
2579                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2580                 udelay(40);
2581         }
2582         err  = tg3_readphy(tp, MII_BMSR, &val);
2583         err |= tg3_readphy(tp, MII_BMSR, &val);
2584         if (err != 0)
2585                 return -EBUSY;
2586
2587         if (netif_running(tp->dev) && tp->link_up) {
2588                 netif_carrier_off(tp->dev);
2589                 tg3_link_report(tp);
2590         }
2591
2592         if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2593             tg3_asic_rev(tp) == ASIC_REV_5704 ||
2594             tg3_asic_rev(tp) == ASIC_REV_5705) {
2595                 err = tg3_phy_reset_5703_4_5(tp);
2596                 if (err)
2597                         return err;
2598                 goto out;
2599         }
2600
2601         cpmuctrl = 0;
2602         if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2603             tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2604                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2605                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2606                         tw32(TG3_CPMU_CTRL,
2607                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2608         }
2609
2610         err = tg3_bmcr_reset(tp);
2611         if (err)
2612                 return err;
2613
2614         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2615                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2616                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2617
2618                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2619         }
2620
2621         if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2622             tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2623                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2624                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2625                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2626                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2627                         udelay(40);
2628                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2629                 }
2630         }
2631
2632         if (tg3_flag(tp, 5717_PLUS) &&
2633             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2634                 return 0;
2635
2636         tg3_phy_apply_otp(tp);
2637
2638         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2639                 tg3_phy_toggle_apd(tp, true);
2640         else
2641                 tg3_phy_toggle_apd(tp, false);
2642
2643 out:
2644         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2645             !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2646                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2647                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2648                 tg3_phy_toggle_auxctl_smdsp(tp, false);
2649         }
2650
2651         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2652                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2653                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2654         }
2655
2656         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2657                 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2658                         tg3_phydsp_write(tp, 0x000a, 0x310b);
2659                         tg3_phydsp_write(tp, 0x201f, 0x9506);
2660                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
2661                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2662                 }
2663         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2664                 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2665                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2666                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2667                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2668                                 tg3_writephy(tp, MII_TG3_TEST1,
2669                                              MII_TG3_TEST1_TRIM_EN | 0x4);
2670                         } else
2671                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2672
2673                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2674                 }
2675         }
2676
2677         /* Set Extended packet length bit (bit 14) on all chips that */
2678         /* support jumbo frames */
2679         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2680                 /* Cannot do read-modify-write on 5401 */
2681                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2682         } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2683                 /* Set bit 14 with read-modify-write to preserve other bits */
2684                 err = tg3_phy_auxctl_read(tp,
2685                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2686                 if (!err)
2687                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2688                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2689         }
2690
2691         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2692          * jumbo frames transmission.
2693          */
2694         if (tg3_flag(tp, JUMBO_CAPABLE)) {
2695                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2696                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2697                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2698         }
2699
2700         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2701                 /* adjust output voltage */
2702                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2703         }
2704
2705         if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2706                 tg3_phydsp_write(tp, 0xffb, 0x4000);
2707
2708         tg3_phy_toggle_automdix(tp, 1);
2709         tg3_phy_set_wirespeed(tp);
2710         return 0;
2711 }
2712
2713 #define TG3_GPIO_MSG_DRVR_PRES           0x00000001
2714 #define TG3_GPIO_MSG_NEED_VAUX           0x00000002
2715 #define TG3_GPIO_MSG_MASK                (TG3_GPIO_MSG_DRVR_PRES | \
2716                                           TG3_GPIO_MSG_NEED_VAUX)
2717 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2718         ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2719          (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2720          (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2721          (TG3_GPIO_MSG_DRVR_PRES << 12))
2722
2723 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2724         ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2725          (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2726          (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2727          (TG3_GPIO_MSG_NEED_VAUX << 12))
2728
2729 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2730 {
2731         u32 status, shift;
2732
2733         if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2734             tg3_asic_rev(tp) == ASIC_REV_5719)
2735                 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2736         else
2737                 status = tr32(TG3_CPMU_DRV_STATUS);
2738
2739         shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2740         status &= ~(TG3_GPIO_MSG_MASK << shift);
2741         status |= (newstat << shift);
2742
2743         if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2744             tg3_asic_rev(tp) == ASIC_REV_5719)
2745                 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2746         else
2747                 tw32(TG3_CPMU_DRV_STATUS, status);
2748
2749         return status >> TG3_APE_GPIO_MSG_SHIFT;
2750 }
2751
2752 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2753 {
2754         if (!tg3_flag(tp, IS_NIC))
2755                 return 0;
2756
2757         if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2758             tg3_asic_rev(tp) == ASIC_REV_5719 ||
2759             tg3_asic_rev(tp) == ASIC_REV_5720) {
2760                 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2761                         return -EIO;
2762
2763                 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2764
2765                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2766                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2767
2768                 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2769         } else {
2770                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2771                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2772         }
2773
2774         return 0;
2775 }
2776
2777 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2778 {
2779         u32 grc_local_ctrl;
2780
2781         if (!tg3_flag(tp, IS_NIC) ||
2782             tg3_asic_rev(tp) == ASIC_REV_5700 ||
2783             tg3_asic_rev(tp) == ASIC_REV_5701)
2784                 return;
2785
2786         grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2787
2788         tw32_wait_f(GRC_LOCAL_CTRL,
2789                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2790                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2791
2792         tw32_wait_f(GRC_LOCAL_CTRL,
2793                     grc_local_ctrl,
2794                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2795
2796         tw32_wait_f(GRC_LOCAL_CTRL,
2797                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2798                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2799 }
2800
2801 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2802 {
2803         if (!tg3_flag(tp, IS_NIC))
2804                 return;
2805
2806         if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2807             tg3_asic_rev(tp) == ASIC_REV_5701) {
2808                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2809                             (GRC_LCLCTRL_GPIO_OE0 |
2810                              GRC_LCLCTRL_GPIO_OE1 |
2811                              GRC_LCLCTRL_GPIO_OE2 |
2812                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2813                              GRC_LCLCTRL_GPIO_OUTPUT1),
2814                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2815         } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2816                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2817                 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2818                 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2819                                      GRC_LCLCTRL_GPIO_OE1 |
2820                                      GRC_LCLCTRL_GPIO_OE2 |
2821                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2822                                      GRC_LCLCTRL_GPIO_OUTPUT1 |
2823                                      tp->grc_local_ctrl;
2824                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2825                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2826
2827                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2828                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2829                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2830
2831                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2832                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2833                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2834         } else {
2835                 u32 no_gpio2;
2836                 u32 grc_local_ctrl = 0;
2837
2838                 /* Workaround to prevent overdrawing Amps. */
2839                 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2840                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2841                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2842                                     grc_local_ctrl,
2843                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2844                 }
2845
2846                 /* On 5753 and variants, GPIO2 cannot be used. */
2847                 no_gpio2 = tp->nic_sram_data_cfg &
2848                            NIC_SRAM_DATA_CFG_NO_GPIO2;
2849
2850                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2851                                   GRC_LCLCTRL_GPIO_OE1 |
2852                                   GRC_LCLCTRL_GPIO_OE2 |
2853                                   GRC_LCLCTRL_GPIO_OUTPUT1 |
2854                                   GRC_LCLCTRL_GPIO_OUTPUT2;
2855                 if (no_gpio2) {
2856                         grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2857                                             GRC_LCLCTRL_GPIO_OUTPUT2);
2858                 }
2859                 tw32_wait_f(GRC_LOCAL_CTRL,
2860                             tp->grc_local_ctrl | grc_local_ctrl,
2861                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2862
2863                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2864
2865                 tw32_wait_f(GRC_LOCAL_CTRL,
2866                             tp->grc_local_ctrl | grc_local_ctrl,
2867                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2868
2869                 if (!no_gpio2) {
2870                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2871                         tw32_wait_f(GRC_LOCAL_CTRL,
2872                                     tp->grc_local_ctrl | grc_local_ctrl,
2873                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2874                 }
2875         }
2876 }
2877
2878 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2879 {
2880         u32 msg = 0;
2881
2882         /* Serialize power state transitions */
2883         if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2884                 return;
2885
2886         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2887                 msg = TG3_GPIO_MSG_NEED_VAUX;
2888
2889         msg = tg3_set_function_status(tp, msg);
2890
2891         if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2892                 goto done;
2893
2894         if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2895                 tg3_pwrsrc_switch_to_vaux(tp);
2896         else
2897                 tg3_pwrsrc_die_with_vmain(tp);
2898
2899 done:
2900         tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2901 }
2902
2903 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2904 {
2905         bool need_vaux = false;
2906
2907         /* The GPIOs do something completely different on 57765. */
2908         if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2909                 return;
2910
2911         if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2912             tg3_asic_rev(tp) == ASIC_REV_5719 ||
2913             tg3_asic_rev(tp) == ASIC_REV_5720) {
2914                 tg3_frob_aux_power_5717(tp, include_wol ?
2915                                         tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2916                 return;
2917         }
2918
2919         if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2920                 struct net_device *dev_peer;
2921
2922                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2923
2924                 /* remove_one() may have been run on the peer. */
2925                 if (dev_peer) {
2926                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2927
2928                         if (tg3_flag(tp_peer, INIT_COMPLETE))
2929                                 return;
2930
2931                         if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2932                             tg3_flag(tp_peer, ENABLE_ASF))
2933                                 need_vaux = true;
2934                 }
2935         }
2936
2937         if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2938             tg3_flag(tp, ENABLE_ASF))
2939                 need_vaux = true;
2940
2941         if (need_vaux)
2942                 tg3_pwrsrc_switch_to_vaux(tp);
2943         else
2944                 tg3_pwrsrc_die_with_vmain(tp);
2945 }
2946
2947 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2948 {
2949         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2950                 return 1;
2951         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2952                 if (speed != SPEED_10)
2953                         return 1;
2954         } else if (speed == SPEED_10)
2955                 return 1;
2956
2957         return 0;
2958 }
2959
2960 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2961 {
2962         u32 val;
2963
2964         if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
2965                 return;
2966
2967         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2968                 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
2969                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2970                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2971
2972                         sg_dig_ctrl |=
2973                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2974                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2975                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2976                 }
2977                 return;
2978         }
2979
2980         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2981                 tg3_bmcr_reset(tp);
2982                 val = tr32(GRC_MISC_CFG);
2983                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2984                 udelay(40);
2985                 return;
2986         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2987                 u32 phytest;
2988                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2989                         u32 phy;
2990
2991                         tg3_writephy(tp, MII_ADVERTISE, 0);
2992                         tg3_writephy(tp, MII_BMCR,
2993                                      BMCR_ANENABLE | BMCR_ANRESTART);
2994
2995                         tg3_writephy(tp, MII_TG3_FET_TEST,
2996                                      phytest | MII_TG3_FET_SHADOW_EN);
2997                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2998                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2999                                 tg3_writephy(tp,
3000                                              MII_TG3_FET_SHDW_AUXMODE4,
3001                                              phy);
3002                         }
3003                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3004                 }
3005                 return;
3006         } else if (do_low_power) {
3007                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3008                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3009
3010                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3011                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3012                       MII_TG3_AUXCTL_PCTL_VREG_11V;
3013                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3014         }
3015
3016         /* The PHY should not be powered down on some chips because
3017          * of bugs.
3018          */
3019         if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
3020             tg3_asic_rev(tp) == ASIC_REV_5704 ||
3021             (tg3_asic_rev(tp) == ASIC_REV_5780 &&
3022              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
3023             (tg3_asic_rev(tp) == ASIC_REV_5717 &&
3024              !tp->pci_fn))
3025                 return;
3026
3027         if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3028             tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3029                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3030                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3031                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3032                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3033         }
3034
3035         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3036 }
3037
3038 /* tp->lock is held. */
3039 static int tg3_nvram_lock(struct tg3 *tp)
3040 {
3041         if (tg3_flag(tp, NVRAM)) {
3042                 int i;
3043
3044                 if (tp->nvram_lock_cnt == 0) {
3045                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3046                         for (i = 0; i < 8000; i++) {
3047                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3048                                         break;
3049                                 udelay(20);
3050                         }
3051                         if (i == 8000) {
3052                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3053                                 return -ENODEV;
3054                         }
3055                 }
3056                 tp->nvram_lock_cnt++;
3057         }
3058         return 0;
3059 }
3060
3061 /* tp->lock is held. */
3062 static void tg3_nvram_unlock(struct tg3 *tp)
3063 {
3064         if (tg3_flag(tp, NVRAM)) {
3065                 if (tp->nvram_lock_cnt > 0)
3066                         tp->nvram_lock_cnt--;
3067                 if (tp->nvram_lock_cnt == 0)
3068                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3069         }
3070 }
3071
3072 /* tp->lock is held. */
3073 static void tg3_enable_nvram_access(struct tg3 *tp)
3074 {
3075         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3076                 u32 nvaccess = tr32(NVRAM_ACCESS);
3077
3078                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3079         }
3080 }
3081
3082 /* tp->lock is held. */
3083 static void tg3_disable_nvram_access(struct tg3 *tp)
3084 {
3085         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3086                 u32 nvaccess = tr32(NVRAM_ACCESS);
3087
3088                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3089         }
3090 }
3091
3092 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3093                                         u32 offset, u32 *val)
3094 {
3095         u32 tmp;
3096         int i;
3097
3098         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3099                 return -EINVAL;
3100
3101         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3102                                         EEPROM_ADDR_DEVID_MASK |
3103                                         EEPROM_ADDR_READ);
3104         tw32(GRC_EEPROM_ADDR,
3105              tmp |
3106              (0 << EEPROM_ADDR_DEVID_SHIFT) |
3107              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3108               EEPROM_ADDR_ADDR_MASK) |
3109              EEPROM_ADDR_READ | EEPROM_ADDR_START);
3110
3111         for (i = 0; i < 1000; i++) {
3112                 tmp = tr32(GRC_EEPROM_ADDR);
3113
3114                 if (tmp & EEPROM_ADDR_COMPLETE)
3115                         break;
3116                 msleep(1);
3117         }
3118         if (!(tmp & EEPROM_ADDR_COMPLETE))
3119                 return -EBUSY;
3120
3121         tmp = tr32(GRC_EEPROM_DATA);
3122
3123         /*
3124          * The data will always be opposite the native endian
3125          * format.  Perform a blind byteswap to compensate.
3126          */
3127         *val = swab32(tmp);
3128
3129         return 0;
3130 }
3131
3132 #define NVRAM_CMD_TIMEOUT 10000
3133
3134 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3135 {
3136         int i;
3137
3138         tw32(NVRAM_CMD, nvram_cmd);
3139         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3140                 udelay(10);
3141                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3142                         udelay(10);
3143                         break;
3144                 }
3145         }
3146
3147         if (i == NVRAM_CMD_TIMEOUT)
3148                 return -EBUSY;
3149
3150         return 0;
3151 }
3152
3153 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3154 {
3155         if (tg3_flag(tp, NVRAM) &&
3156             tg3_flag(tp, NVRAM_BUFFERED) &&
3157             tg3_flag(tp, FLASH) &&
3158             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3159             (tp->nvram_jedecnum == JEDEC_ATMEL))
3160
3161                 addr = ((addr / tp->nvram_pagesize) <<
3162                         ATMEL_AT45DB0X1B_PAGE_POS) +
3163                        (addr % tp->nvram_pagesize);
3164
3165         return addr;
3166 }
3167
3168 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3169 {
3170         if (tg3_flag(tp, NVRAM) &&
3171             tg3_flag(tp, NVRAM_BUFFERED) &&
3172             tg3_flag(tp, FLASH) &&
3173             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3174             (tp->nvram_jedecnum == JEDEC_ATMEL))
3175
3176                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3177                         tp->nvram_pagesize) +
3178                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3179
3180         return addr;
3181 }
3182
3183 /* NOTE: Data read in from NVRAM is byteswapped according to
3184  * the byteswapping settings for all other register accesses.
3185  * tg3 devices are BE devices, so on a BE machine, the data
3186  * returned will be exactly as it is seen in NVRAM.  On a LE
3187  * machine, the 32-bit value will be byteswapped.
3188  */
3189 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3190 {
3191         int ret;
3192
3193         if (!tg3_flag(tp, NVRAM))
3194                 return tg3_nvram_read_using_eeprom(tp, offset, val);
3195
3196         offset = tg3_nvram_phys_addr(tp, offset);
3197
3198         if (offset > NVRAM_ADDR_MSK)
3199                 return -EINVAL;
3200
3201         ret = tg3_nvram_lock(tp);
3202         if (ret)
3203                 return ret;
3204
3205         tg3_enable_nvram_access(tp);
3206
3207         tw32(NVRAM_ADDR, offset);
3208         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3209                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3210
3211         if (ret == 0)
3212                 *val = tr32(NVRAM_RDDATA);
3213
3214         tg3_disable_nvram_access(tp);
3215
3216         tg3_nvram_unlock(tp);
3217
3218         return ret;
3219 }
3220
3221 /* Ensures NVRAM data is in bytestream format. */
3222 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3223 {
3224         u32 v;
3225         int res = tg3_nvram_read(tp, offset, &v);
3226         if (!res)
3227                 *val = cpu_to_be32(v);
3228         return res;
3229 }
3230
3231 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3232                                     u32 offset, u32 len, u8 *buf)
3233 {
3234         int i, j, rc = 0;
3235         u32 val;
3236
3237         for (i = 0; i < len; i += 4) {
3238                 u32 addr;
3239                 __be32 data;
3240
3241                 addr = offset + i;
3242
3243                 memcpy(&data, buf + i, 4);
3244
3245                 /*
3246                  * The SEEPROM interface expects the data to always be opposite
3247                  * the native endian format.  We accomplish this by reversing
3248                  * all the operations that would have been performed on the
3249                  * data from a call to tg3_nvram_read_be32().
3250                  */
3251                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3252
3253                 val = tr32(GRC_EEPROM_ADDR);
3254                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3255
3256                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3257                         EEPROM_ADDR_READ);
3258                 tw32(GRC_EEPROM_ADDR, val |
3259                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
3260                         (addr & EEPROM_ADDR_ADDR_MASK) |
3261                         EEPROM_ADDR_START |
3262                         EEPROM_ADDR_WRITE);
3263
3264                 for (j = 0; j < 1000; j++) {
3265                         val = tr32(GRC_EEPROM_ADDR);
3266
3267                         if (val & EEPROM_ADDR_COMPLETE)
3268                                 break;
3269                         msleep(1);
3270                 }
3271                 if (!(val & EEPROM_ADDR_COMPLETE)) {
3272                         rc = -EBUSY;
3273                         break;
3274                 }
3275         }
3276
3277         return rc;
3278 }
3279
3280 /* offset and length are dword aligned */
3281 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3282                 u8 *buf)
3283 {
3284         int ret = 0;
3285         u32 pagesize = tp->nvram_pagesize;
3286         u32 pagemask = pagesize - 1;
3287         u32 nvram_cmd;
3288         u8 *tmp;
3289
3290         tmp = kmalloc(pagesize, GFP_KERNEL);
3291         if (tmp == NULL)
3292                 return -ENOMEM;
3293
3294         while (len) {
3295                 int j;
3296                 u32 phy_addr, page_off, size;
3297
3298                 phy_addr = offset & ~pagemask;
3299
3300                 for (j = 0; j < pagesize; j += 4) {
3301                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
3302                                                   (__be32 *) (tmp + j));
3303                         if (ret)
3304                                 break;
3305                 }
3306                 if (ret)
3307                         break;
3308
3309                 page_off = offset & pagemask;
3310                 size = pagesize;
3311                 if (len < size)
3312                         size = len;
3313
3314                 len -= size;
3315
3316                 memcpy(tmp + page_off, buf, size);
3317
3318                 offset = offset + (pagesize - page_off);
3319
3320                 tg3_enable_nvram_access(tp);
3321
3322                 /*
3323                  * Before we can erase the flash page, we need
3324                  * to issue a special "write enable" command.
3325                  */
3326                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3327
3328                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3329                         break;
3330
3331                 /* Erase the target page */
3332                 tw32(NVRAM_ADDR, phy_addr);
3333
3334                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3335                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3336
3337                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3338                         break;
3339
3340                 /* Issue another write enable to start the write. */
3341                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3342
3343                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3344                         break;
3345
3346                 for (j = 0; j < pagesize; j += 4) {
3347                         __be32 data;
3348
3349                         data = *((__be32 *) (tmp + j));
3350
3351                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
3352
3353                         tw32(NVRAM_ADDR, phy_addr + j);
3354
3355                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3356                                 NVRAM_CMD_WR;
3357
3358                         if (j == 0)
3359                                 nvram_cmd |= NVRAM_CMD_FIRST;
3360                         else if (j == (pagesize - 4))
3361                                 nvram_cmd |= NVRAM_CMD_LAST;
3362
3363                         ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3364                         if (ret)
3365                                 break;
3366                 }
3367                 if (ret)
3368                         break;
3369         }
3370
3371         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3372         tg3_nvram_exec_cmd(tp, nvram_cmd);
3373
3374         kfree(tmp);
3375
3376         return ret;
3377 }
3378
3379 /* offset and length are dword aligned */
3380 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3381                 u8 *buf)
3382 {
3383         int i, ret = 0;
3384
3385         for (i = 0; i < len; i += 4, offset += 4) {
3386                 u32 page_off, phy_addr, nvram_cmd;
3387                 __be32 data;
3388
3389                 memcpy(&data, buf + i, 4);
3390                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3391
3392                 page_off = offset % tp->nvram_pagesize;
3393
3394                 phy_addr = tg3_nvram_phys_addr(tp, offset);
3395
3396                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3397
3398                 if (page_off == 0 || i == 0)
3399                         nvram_cmd |= NVRAM_CMD_FIRST;
3400                 if (page_off == (tp->nvram_pagesize - 4))
3401                         nvram_cmd |= NVRAM_CMD_LAST;
3402
3403                 if (i == (len - 4))
3404                         nvram_cmd |= NVRAM_CMD_LAST;
3405
3406                 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3407                     !tg3_flag(tp, FLASH) ||
3408                     !tg3_flag(tp, 57765_PLUS))
3409                         tw32(NVRAM_ADDR, phy_addr);
3410
3411                 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3412                     !tg3_flag(tp, 5755_PLUS) &&
3413                     (tp->nvram_jedecnum == JEDEC_ST) &&
3414                     (nvram_cmd & NVRAM_CMD_FIRST)) {
3415                         u32 cmd;
3416
3417                         cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3418                         ret = tg3_nvram_exec_cmd(tp, cmd);
3419                         if (ret)
3420                                 break;
3421                 }
3422                 if (!tg3_flag(tp, FLASH)) {
3423                         /* We always do complete word writes to eeprom. */
3424                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3425                 }
3426
3427                 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3428                 if (ret)
3429                         break;
3430         }
3431         return ret;
3432 }
3433
3434 /* offset and length are dword aligned */
3435 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3436 {
3437         int ret;
3438
3439         if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3440                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3441                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
3442                 udelay(40);
3443         }
3444
3445         if (!tg3_flag(tp, NVRAM)) {
3446                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3447         } else {
3448                 u32 grc_mode;
3449
3450                 ret = tg3_nvram_lock(tp);
3451                 if (ret)
3452                         return ret;
3453
3454                 tg3_enable_nvram_access(tp);
3455                 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3456                         tw32(NVRAM_WRITE1, 0x406);
3457
3458                 grc_mode = tr32(GRC_MODE);
3459                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3460
3461                 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3462                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
3463                                 buf);
3464                 } else {
3465                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3466                                 buf);
3467                 }
3468
3469                 grc_mode = tr32(GRC_MODE);
3470                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3471
3472                 tg3_disable_nvram_access(tp);
3473                 tg3_nvram_unlock(tp);
3474         }
3475
3476         if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3477                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3478                 udelay(40);
3479         }
3480
3481         return ret;
3482 }
3483
3484 #define RX_CPU_SCRATCH_BASE     0x30000
3485 #define RX_CPU_SCRATCH_SIZE     0x04000
3486 #define TX_CPU_SCRATCH_BASE     0x34000
3487 #define TX_CPU_SCRATCH_SIZE     0x04000
3488
3489 /* tp->lock is held. */
3490 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3491 {
3492         int i;
3493         const int iters = 10000;
3494
3495         for (i = 0; i < iters; i++) {
3496                 tw32(cpu_base + CPU_STATE, 0xffffffff);
3497                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
3498                 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3499                         break;
3500         }
3501
3502         return (i == iters) ? -EBUSY : 0;
3503 }
3504
3505 /* tp->lock is held. */
3506 static int tg3_rxcpu_pause(struct tg3 *tp)
3507 {
3508         int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3509
3510         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3511         tw32_f(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
3512         udelay(10);
3513
3514         return rc;
3515 }
3516
3517 /* tp->lock is held. */
3518 static int tg3_txcpu_pause(struct tg3 *tp)
3519 {
3520         return tg3_pause_cpu(tp, TX_CPU_BASE);
3521 }
3522
3523 /* tp->lock is held. */
3524 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3525 {
3526         tw32(cpu_base + CPU_STATE, 0xffffffff);
3527         tw32_f(cpu_base + CPU_MODE,  0x00000000);
3528 }
3529
3530 /* tp->lock is held. */
3531 static void tg3_rxcpu_resume(struct tg3 *tp)
3532 {
3533         tg3_resume_cpu(tp, RX_CPU_BASE);
3534 }
3535
3536 /* tp->lock is held. */
3537 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3538 {
3539         int rc;
3540
3541         BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3542
3543         if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3544                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3545
3546                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3547                 return 0;
3548         }
3549         if (cpu_base == RX_CPU_BASE) {
3550                 rc = tg3_rxcpu_pause(tp);
3551         } else {
3552                 /*
3553                  * There is only an Rx CPU for the 5750 derivative in the
3554                  * BCM4785.
3555                  */
3556                 if (tg3_flag(tp, IS_SSB_CORE))
3557                         return 0;
3558
3559                 rc = tg3_txcpu_pause(tp);
3560         }
3561
3562         if (rc) {
3563                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3564                            __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3565                 return -ENODEV;
3566         }
3567
3568         /* Clear firmware's nvram arbitration. */
3569         if (tg3_flag(tp, NVRAM))
3570                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3571         return 0;
3572 }
3573
3574 static int tg3_fw_data_len(struct tg3 *tp,
3575                            const struct tg3_firmware_hdr *fw_hdr)
3576 {
3577         int fw_len;
3578
3579         /* Non fragmented firmware have one firmware header followed by a
3580          * contiguous chunk of data to be written. The length field in that
3581          * header is not the length of data to be written but the complete
3582          * length of the bss. The data length is determined based on
3583          * tp->fw->size minus headers.
3584          *
3585          * Fragmented firmware have a main header followed by multiple
3586          * fragments. Each fragment is identical to non fragmented firmware
3587          * with a firmware header followed by a contiguous chunk of data. In
3588          * the main header, the length field is unused and set to 0xffffffff.
3589          * In each fragment header the length is the entire size of that
3590          * fragment i.e. fragment data + header length. Data length is
3591          * therefore length field in the header minus TG3_FW_HDR_LEN.
3592          */
3593         if (tp->fw_len == 0xffffffff)
3594                 fw_len = be32_to_cpu(fw_hdr->len);
3595         else
3596                 fw_len = tp->fw->size;
3597
3598         return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3599 }
3600
3601 /* tp->lock is held. */
3602 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3603                                  u32 cpu_scratch_base, int cpu_scratch_size,
3604                                  const struct tg3_firmware_hdr *fw_hdr)
3605 {
3606         int err, i;
3607         void (*write_op)(struct tg3 *, u32, u32);
3608         int total_len = tp->fw->size;
3609
3610         if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3611                 netdev_err(tp->dev,
3612                            "%s: Trying to load TX cpu firmware which is 5705\n",
3613                            __func__);
3614                 return -EINVAL;
3615         }
3616
3617         if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3618                 write_op = tg3_write_mem;
3619         else
3620                 write_op = tg3_write_indirect_reg32;
3621
3622         if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3623                 /* It is possible that bootcode is still loading at this point.
3624                  * Get the nvram lock first before halting the cpu.
3625                  */
3626                 int lock_err = tg3_nvram_lock(tp);
3627                 err = tg3_halt_cpu(tp, cpu_base);
3628                 if (!lock_err)
3629                         tg3_nvram_unlock(tp);
3630                 if (err)
3631                         goto out;
3632
3633                 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3634                         write_op(tp, cpu_scratch_base + i, 0);
3635                 tw32(cpu_base + CPU_STATE, 0xffffffff);
3636                 tw32(cpu_base + CPU_MODE,
3637                      tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3638         } else {
3639                 /* Subtract additional main header for fragmented firmware and
3640                  * advance to the first fragment
3641                  */
3642                 total_len -= TG3_FW_HDR_LEN;
3643                 fw_hdr++;
3644         }
3645
3646         do {
3647                 u32 *fw_data = (u32 *)(fw_hdr + 1);
3648                 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3649                         write_op(tp, cpu_scratch_base +
3650                                      (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3651                                      (i * sizeof(u32)),
3652                                  be32_to_cpu(fw_data[i]));
3653
3654                 total_len -= be32_to_cpu(fw_hdr->len);
3655
3656                 /* Advance to next fragment */
3657                 fw_hdr = (struct tg3_firmware_hdr *)
3658                          ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3659         } while (total_len > 0);
3660
3661         err = 0;
3662
3663 out:
3664         return err;
3665 }
3666
3667 /* tp->lock is held. */
3668 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3669 {
3670         int i;
3671         const int iters = 5;
3672
3673         tw32(cpu_base + CPU_STATE, 0xffffffff);
3674         tw32_f(cpu_base + CPU_PC, pc);
3675
3676         for (i = 0; i < iters; i++) {
3677                 if (tr32(cpu_base + CPU_PC) == pc)
3678                         break;
3679                 tw32(cpu_base + CPU_STATE, 0xffffffff);
3680                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
3681                 tw32_f(cpu_base + CPU_PC, pc);
3682                 udelay(1000);
3683         }
3684
3685         return (i == iters) ? -EBUSY : 0;
3686 }
3687
3688 /* tp->lock is held. */
3689 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3690 {
3691         const struct tg3_firmware_hdr *fw_hdr;
3692         int err;
3693
3694         fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3695
3696         /* Firmware blob starts with version numbers, followed by
3697            start address and length. We are setting complete length.
3698            length = end_address_of_bss - start_address_of_text.
3699            Remainder is the blob to be loaded contiguously
3700            from start address. */
3701
3702         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3703                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3704                                     fw_hdr);
3705         if (err)
3706                 return err;
3707
3708         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3709                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3710                                     fw_hdr);
3711         if (err)
3712                 return err;
3713
3714         /* Now startup only the RX cpu. */
3715         err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3716                                        be32_to_cpu(fw_hdr->base_addr));
3717         if (err) {
3718                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3719                            "should be %08x\n", __func__,
3720                            tr32(RX_CPU_BASE + CPU_PC),
3721                                 be32_to_cpu(fw_hdr->base_addr));
3722                 return -ENODEV;
3723         }
3724
3725         tg3_rxcpu_resume(tp);
3726
3727         return 0;
3728 }
3729
3730 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3731 {
3732         const int iters = 1000;
3733         int i;
3734         u32 val;
3735
3736         /* Wait for boot code to complete initialization and enter service
3737          * loop. It is then safe to download service patches
3738          */
3739         for (i = 0; i < iters; i++) {
3740                 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3741                         break;
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