drivers/net/ethernet/broadcom/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2012 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/pci.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/mdio.h>
  37 #include <linux/mii.h>
  38 #include <linux/phy.h>
  39 #include <linux/brcmphy.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/ip.h>
  42 #include <linux/tcp.h>
  43 #include <linux/workqueue.h>
  44 #include <linux/prefetch.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/firmware.h>
  47 #include <linux/hwmon.h>
  48 #include <linux/hwmon-sysfs.h>
  49
  50 #include <net/checksum.h>
  51 #include <net/ip.h>
  52
  53 #include <linux/io.h>
  54 #include <asm/byteorder.h>
  55 #include <linux/uaccess.h>
  56
  57 #include <uapi/linux/net_tstamp.h>
  58 #include <linux/ptp_clock_kernel.h>
  59
  60 #ifdef CONFIG_SPARC
  61 #include <asm/idprom.h>
  62 #include <asm/prom.h>
  63 #endif
  64
  65 #define BAR_0   0
  66 #define BAR_2   2
  67
  68 #include "tg3.h"
  69
  70 /* Functions & macros to verify TG3_FLAGS types */
  71
  72 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
  73 {
  74         return test_bit(flag, bits);
  75 }
  76
  77 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
  78 {
  79         set_bit(flag, bits);
  80 }
  81
  82 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
  83 {
  84         clear_bit(flag, bits);
  85 }
  86
  87 #define tg3_flag(tp, flag)                              \
  88         _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
  89 #define tg3_flag_set(tp, flag)                          \
  90         _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
  91 #define tg3_flag_clear(tp, flag)                        \
  92         _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
  93
  94 #define DRV_MODULE_NAME         "tg3"
  95 #define TG3_MAJ_NUM                     3
  96 #define TG3_MIN_NUM                     128
  97 #define DRV_MODULE_VERSION      \
  98         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  99 #define DRV_MODULE_RELDATE      "December 03, 2012"
 100
 101 #define RESET_KIND_SHUTDOWN     0
 102 #define RESET_KIND_INIT         1
 103 #define RESET_KIND_SUSPEND      2
 104
 105 #define TG3_DEF_RX_MODE         0
 106 #define TG3_DEF_TX_MODE         0
 107 #define TG3_DEF_MSG_ENABLE        \
 108         (NETIF_MSG_DRV          | \
 109          NETIF_MSG_PROBE        | \
 110          NETIF_MSG_LINK         | \
 111          NETIF_MSG_TIMER        | \
 112          NETIF_MSG_IFDOWN       | \
 113          NETIF_MSG_IFUP         | \
 114          NETIF_MSG_RX_ERR       | \
 115          NETIF_MSG_TX_ERR)
 116
 117 #define TG3_GRC_LCLCTL_PWRSW_DELAY      100
 118
 119 /* length of time before we decide the hardware is borked,
 120  * and dev->tx_timeout() should be called to fix the problem
 121  */
 122
 123 #define TG3_TX_TIMEOUT                  (5 * HZ)
 124
 125 /* hardware minimum and maximum for a single frame's data payload */
 126 #define TG3_MIN_MTU                     60
 127 #define TG3_MAX_MTU(tp) \
 128         (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
 129
 130 /* These numbers seem to be hard coded in the NIC firmware somehow.
 131  * You can't change the ring sizes, but you can change where you place
 132  * them in the NIC onboard memory.
 133  */
 134 #define TG3_RX_STD_RING_SIZE(tp) \
 135         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
 136          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 137 #define TG3_DEF_RX_RING_PENDING         200
 138 #define TG3_RX_JMB_RING_SIZE(tp) \
 139         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
 140          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 141 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 142
 143 /* Do not place this n-ring entries value into the tp struct itself,
 144  * we really want to expose these constants to GCC so that modulo et
 145  * al.  operations are done with shifts and masks instead of with
 146  * hw multiply/modulo instructions.  Another solution would be to
 147  * replace things like '% foo' with '& (foo - 1)'.
 148  */
 149
 150 #define TG3_TX_RING_SIZE                512
 151 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 152
 153 #define TG3_RX_STD_RING_BYTES(tp) \
 154         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 155 #define TG3_RX_JMB_RING_BYTES(tp) \
 156         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 157 #define TG3_RX_RCB_RING_BYTES(tp) \
 158         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 159 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 160                                  TG3_TX_RING_SIZE)
 161 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 162
 163 #define TG3_DMA_BYTE_ENAB               64
 164
 165 #define TG3_RX_STD_DMA_SZ               1536
 166 #define TG3_RX_JMB_DMA_SZ               9046
 167
 168 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 169
 170 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 171 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 172
 173 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 174         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 175
 176 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 177         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 178
 179 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 180  * that are at least dword aligned when used in PCIX mode.  The driver
 181  * works around this bug by double copying the packet.  This workaround
 182  * is built into the normal double copy length check for efficiency.
 183  *
 184  * However, the double copy is only necessary on those architectures
 185  * where unaligned memory accesses are inefficient.  For those architectures
 186  * where unaligned memory accesses incur little penalty, we can reintegrate
 187  * the 5701 in the normal rx path.  Doing so saves a device structure
 188  * dereference by hardcoding the double copy threshold in place.
 189  */
 190 #define TG3_RX_COPY_THRESHOLD           256
 191 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 192         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 193 #else
 194         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 195 #endif
 196
 197 #if (NET_IP_ALIGN != 0)
 198 #define TG3_RX_OFFSET(tp)       ((tp)->rx_offset)
 199 #else
 200 #define TG3_RX_OFFSET(tp)       (NET_SKB_PAD)
 201 #endif
 202
 203 /* minimum number of free TX descriptors required to wake up TX process */
 204 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 205 #define TG3_TX_BD_DMA_MAX_2K            2048
 206 #define TG3_TX_BD_DMA_MAX_4K            4096
 207
 208 #define TG3_RAW_IP_ALIGN 2
 209
 210 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 211 #define TG3_FW_UPDATE_FREQ_SEC          (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
 212
 213 #define FIRMWARE_TG3            "tigon/tg3.bin"
 214 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 215 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 216
 217 static char version[] =
 218         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 219
 220 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 221 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 222 MODULE_LICENSE("GPL");
 223 MODULE_VERSION(DRV_MODULE_VERSION);
 224 MODULE_FIRMWARE(FIRMWARE_TG3);
 225 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 226 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 227
 228 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 229 module_param(tg3_debug, int, 0);
 230 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 231
 232 #define TG3_DRV_DATA_FLAG_10_100_ONLY   0x0001
 233 #define TG3_DRV_DATA_FLAG_5705_10_100   0x0002
 234
 235 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
 255          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 256                         TG3_DRV_DATA_FLAG_5705_10_100},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
 258          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 259                         TG3_DRV_DATA_FLAG_5705_10_100},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
 262          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 263                         TG3_DRV_DATA_FLAG_5705_10_100},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
 269          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
 275          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 283         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
 284                         PCI_VENDOR_ID_LENOVO,
 285                         TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
 286          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 287         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 288         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
 289          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 290         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 291         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 292         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 293         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 294         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 295         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 296         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 297         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 298         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 299         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 300         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 301         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 302         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 303         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 304         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 305         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 306         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 307         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 308         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
 309                         PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
 310          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 311         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
 312                         PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
 313          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 314         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 315         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 316         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
 317          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 318         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 319         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 320         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
 321         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 322         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 323         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 324         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 325         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 326         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
 327          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 328         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
 329          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 330         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 331         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
 332         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
 333         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 334         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 335         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 336         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 337         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 338         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 339         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 340         {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
 341         {}
 342 };
 343
 344 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 345
 346 static const struct {
 347         const char string[ETH_GSTRING_LEN];
 348 } ethtool_stats_keys[] = {
 349         { "rx_octets" },
 350         { "rx_fragments" },
 351         { "rx_ucast_packets" },
 352         { "rx_mcast_packets" },
 353         { "rx_bcast_packets" },
 354         { "rx_fcs_errors" },
 355         { "rx_align_errors" },
 356         { "rx_xon_pause_rcvd" },
 357         { "rx_xoff_pause_rcvd" },
 358         { "rx_mac_ctrl_rcvd" },
 359         { "rx_xoff_entered" },
 360         { "rx_frame_too_long_errors" },
 361         { "rx_jabbers" },
 362         { "rx_undersize_packets" },
 363         { "rx_in_length_errors" },
 364         { "rx_out_length_errors" },
 365         { "rx_64_or_less_octet_packets" },
 366         { "rx_65_to_127_octet_packets" },
 367         { "rx_128_to_255_octet_packets" },
 368         { "rx_256_to_511_octet_packets" },
 369         { "rx_512_to_1023_octet_packets" },
 370         { "rx_1024_to_1522_octet_packets" },
 371         { "rx_1523_to_2047_octet_packets" },
 372         { "rx_2048_to_4095_octet_packets" },
 373         { "rx_4096_to_8191_octet_packets" },
 374         { "rx_8192_to_9022_octet_packets" },
 375
 376         { "tx_octets" },
 377         { "tx_collisions" },
 378
 379         { "tx_xon_sent" },
 380         { "tx_xoff_sent" },
 381         { "tx_flow_control" },
 382         { "tx_mac_errors" },
 383         { "tx_single_collisions" },
 384         { "tx_mult_collisions" },
 385         { "tx_deferred" },
 386         { "tx_excessive_collisions" },
 387         { "tx_late_collisions" },
 388         { "tx_collide_2times" },
 389         { "tx_collide_3times" },
 390         { "tx_collide_4times" },
 391         { "tx_collide_5times" },
 392         { "tx_collide_6times" },
 393         { "tx_collide_7times" },
 394         { "tx_collide_8times" },
 395         { "tx_collide_9times" },
 396         { "tx_collide_10times" },
 397         { "tx_collide_11times" },
 398         { "tx_collide_12times" },
 399         { "tx_collide_13times" },
 400         { "tx_collide_14times" },
 401         { "tx_collide_15times" },
 402         { "tx_ucast_packets" },
 403         { "tx_mcast_packets" },
 404         { "tx_bcast_packets" },
 405         { "tx_carrier_sense_errors" },
 406         { "tx_discards" },
 407         { "tx_errors" },
 408
 409         { "dma_writeq_full" },
 410         { "dma_write_prioq_full" },
 411         { "rxbds_empty" },
 412         { "rx_discards" },
 413         { "rx_errors" },
 414         { "rx_threshold_hit" },
 415
 416         { "dma_readq_full" },
 417         { "dma_read_prioq_full" },
 418         { "tx_comp_queue_full" },
 419
 420         { "ring_set_send_prod_index" },
 421         { "ring_status_update" },
 422         { "nic_irqs" },
 423         { "nic_avoided_irqs" },
 424         { "nic_tx_threshold_hit" },
 425
 426         { "mbuf_lwm_thresh_hit" },
 427 };
 428
 429 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
 430 #define TG3_NVRAM_TEST          0
 431 #define TG3_LINK_TEST           1
 432 #define TG3_REGISTER_TEST       2
 433 #define TG3_MEMORY_TEST         3
 434 #define TG3_MAC_LOOPB_TEST      4
 435 #define TG3_PHY_LOOPB_TEST      5
 436 #define TG3_EXT_LOOPB_TEST      6
 437 #define TG3_INTERRUPT_TEST      7
 438
 439
 440 static const struct {
 441         const char string[ETH_GSTRING_LEN];
 442 } ethtool_test_keys[] = {
 443         [TG3_NVRAM_TEST]        = { "nvram test        (online) " },
 444         [TG3_LINK_TEST]         = { "link test         (online) " },
 445         [TG3_REGISTER_TEST]     = { "register test     (offline)" },
 446         [TG3_MEMORY_TEST]       = { "memory test       (offline)" },
 447         [TG3_MAC_LOOPB_TEST]    = { "mac loopback test (offline)" },
 448         [TG3_PHY_LOOPB_TEST]    = { "phy loopback test (offline)" },
 449         [TG3_EXT_LOOPB_TEST]    = { "ext loopback test (offline)" },
 450         [TG3_INTERRUPT_TEST]    = { "interrupt test    (offline)" },
 451 };
 452
 453 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
 454
 455
 456 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 457 {
 458         writel(val, tp->regs + off);
 459 }
 460
 461 static u32 tg3_read32(struct tg3 *tp, u32 off)
 462 {
 463         return readl(tp->regs + off);
 464 }
 465
 466 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 467 {
 468         writel(val, tp->aperegs + off);
 469 }
 470
 471 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 472 {
 473         return readl(tp->aperegs + off);
 474 }
 475
 476 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 477 {
 478         unsigned long flags;
 479
 480         spin_lock_irqsave(&tp->indirect_lock, flags);
 481         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 482         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 483         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 484 }
 485
 486 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 487 {
 488         writel(val, tp->regs + off);
 489         readl(tp->regs + off);
 490 }
 491
 492 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 493 {
 494         unsigned long flags;
 495         u32 val;
 496
 497         spin_lock_irqsave(&tp->indirect_lock, flags);
 498         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 499         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 500         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 501         return val;
 502 }
 503
 504 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 505 {
 506         unsigned long flags;
 507
 508         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 509                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 510                                        TG3_64BIT_REG_LOW, val);
 511                 return;
 512         }
 513         if (off == TG3_RX_STD_PROD_IDX_REG) {
 514                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 515                                        TG3_64BIT_REG_LOW, val);
 516                 return;
 517         }
 518
 519         spin_lock_irqsave(&tp->indirect_lock, flags);
 520         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 521         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 522         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 523
 524         /* In indirect mode when disabling interrupts, we also need
 525          * to clear the interrupt bit in the GRC local ctrl register.
 526          */
 527         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 528             (val == 0x1)) {
 529                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 530                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 531         }
 532 }
 533
 534 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 535 {
 536         unsigned long flags;
 537         u32 val;
 538
 539         spin_lock_irqsave(&tp->indirect_lock, flags);
 540         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 541         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 542         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 543         return val;
 544 }
 545
 546 /* usec_wait specifies the wait time in usec when writing to certain registers
 547  * where it is unsafe to read back the register without some delay.
 548  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 549  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 550  */
 551 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 552 {
 553         if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
 554                 /* Non-posted methods */
 555                 tp->write32(tp, off, val);
 556         else {
 557                 /* Posted method */
 558                 tg3_write32(tp, off, val);
 559                 if (usec_wait)
 560                         udelay(usec_wait);
 561                 tp->read32(tp, off);
 562         }
 563         /* Wait again after the read for the posted method to guarantee that
 564          * the wait time is met.
 565          */
 566         if (usec_wait)
 567                 udelay(usec_wait);
 568 }
 569
 570 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 571 {
 572         tp->write32_mbox(tp, off, val);
 573         if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
 574                 tp->read32_mbox(tp, off);
 575 }
 576
 577 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 578 {
 579         void __iomem *mbox = tp->regs + off;
 580         writel(val, mbox);
 581         if (tg3_flag(tp, TXD_MBOX_HWBUG))
 582                 writel(val, mbox);
 583         if (tg3_flag(tp, MBOX_WRITE_REORDER))
 584                 readl(mbox);
 585 }
 586
 587 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 588 {
 589         return readl(tp->regs + off + GRCMBOX_BASE);
 590 }
 591
 592 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 593 {
 594         writel(val, tp->regs + off + GRCMBOX_BASE);
 595 }
 596
 597 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 598 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 599 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 600 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 601 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 602
 603 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 604 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 605 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 606 #define tr32(reg)                       tp->read32(tp, reg)
 607
 608 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 609 {
 610         unsigned long flags;
 611
 612         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 613             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 614                 return;
 615
 616         spin_lock_irqsave(&tp->indirect_lock, flags);
 617         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
 618                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 619                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 620
 621                 /* Always leave this as zero. */
 622                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 623         } else {
 624                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 625                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 626
 627                 /* Always leave this as zero. */
 628                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 629         }
 630         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 631 }
 632
 633 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 634 {
 635         unsigned long flags;
 636
 637         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 638             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 639                 *val = 0;
 640                 return;
 641         }
 642
 643         spin_lock_irqsave(&tp->indirect_lock, flags);
 644         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
 645                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 646                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 647
 648                 /* Always leave this as zero. */
 649                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 650         } else {
 651                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 652                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 653
 654                 /* Always leave this as zero. */
 655                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 656         }
 657         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 658 }
 659
 660 static void tg3_ape_lock_init(struct tg3 *tp)
 661 {
 662         int i;
 663         u32 regbase, bit;
 664
 665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 666                 regbase = TG3_APE_LOCK_GRANT;
 667         else
 668                 regbase = TG3_APE_PER_LOCK_GRANT;
 669
 670         /* Make sure the driver hasn't any stale locks. */
 671         for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
 672                 switch (i) {
 673                 case TG3_APE_LOCK_PHY0:
 674                 case TG3_APE_LOCK_PHY1:
 675                 case TG3_APE_LOCK_PHY2:
 676                 case TG3_APE_LOCK_PHY3:
 677                         bit = APE_LOCK_GRANT_DRIVER;
 678                         break;
 679                 default:
 680                         if (!tp->pci_fn)
 681                                 bit = APE_LOCK_GRANT_DRIVER;
 682                         else
 683                                 bit = 1 << tp->pci_fn;
 684                 }
 685                 tg3_ape_write32(tp, regbase + 4 * i, bit);
 686         }
 687
 688 }
 689
 690 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 691 {
 692         int i, off;
 693         int ret = 0;
 694         u32 status, req, gnt, bit;
 695
 696         if (!tg3_flag(tp, ENABLE_APE))
 697                 return 0;
 698
 699         switch (locknum) {
 700         case TG3_APE_LOCK_GPIO:
 701                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 702                         return 0;
 703         case TG3_APE_LOCK_GRC:
 704         case TG3_APE_LOCK_MEM:
 705                 if (!tp->pci_fn)
 706                         bit = APE_LOCK_REQ_DRIVER;
 707                 else
 708                         bit = 1 << tp->pci_fn;
 709                 break;
 710         case TG3_APE_LOCK_PHY0:
 711         case TG3_APE_LOCK_PHY1:
 712         case TG3_APE_LOCK_PHY2:
 713         case TG3_APE_LOCK_PHY3:
 714                 bit = APE_LOCK_REQ_DRIVER;
 715                 break;
 716         default:
 717                 return -EINVAL;
 718         }
 719
 720         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 721                 req = TG3_APE_LOCK_REQ;
 722                 gnt = TG3_APE_LOCK_GRANT;
 723         } else {
 724                 req = TG3_APE_PER_LOCK_REQ;
 725                 gnt = TG3_APE_PER_LOCK_GRANT;
 726         }
 727
 728         off = 4 * locknum;
 729
 730         tg3_ape_write32(tp, req + off, bit);
 731
 732         /* Wait for up to 1 millisecond to acquire lock. */
 733         for (i = 0; i < 100; i++) {
 734                 status = tg3_ape_read32(tp, gnt + off);
 735                 if (status == bit)
 736                         break;
 737                 udelay(10);
 738         }
 739
 740         if (status != bit) {
 741                 /* Revoke the lock request. */
 742                 tg3_ape_write32(tp, gnt + off, bit);
 743                 ret = -EBUSY;
 744         }
 745
 746         return ret;
 747 }
 748
 749 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 750 {
 751         u32 gnt, bit;
 752
 753         if (!tg3_flag(tp, ENABLE_APE))
 754                 return;
 755
 756         switch (locknum) {
 757         case TG3_APE_LOCK_GPIO:
 758                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 759                         return;
 760         case TG3_APE_LOCK_GRC:
 761         case TG3_APE_LOCK_MEM:
 762                 if (!tp->pci_fn)
 763                         bit = APE_LOCK_GRANT_DRIVER;
 764                 else
 765                         bit = 1 << tp->pci_fn;
 766                 break;
 767         case TG3_APE_LOCK_PHY0:
 768         case TG3_APE_LOCK_PHY1:
 769         case TG3_APE_LOCK_PHY2:
 770         case TG3_APE_LOCK_PHY3:
 771                 bit = APE_LOCK_GRANT_DRIVER;
 772                 break;
 773         default:
 774                 return;
 775         }
 776
 777         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 778                 gnt = TG3_APE_LOCK_GRANT;
 779         else
 780                 gnt = TG3_APE_PER_LOCK_GRANT;
 781
 782         tg3_ape_write32(tp, gnt + 4 * locknum, bit);
 783 }
 784
 785 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
 786 {
 787         u32 apedata;
 788
 789         while (timeout_us) {
 790                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
 791                         return -EBUSY;
 792
 793                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
 794                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
 795                         break;
 796
 797                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 798
 799                 udelay(10);
 800                 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
 801         }
 802
 803         return timeout_us ? 0 : -EBUSY;
 804 }
 805
 806 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
 807 {
 808         u32 i, apedata;
 809
 810         for (i = 0; i < timeout_us / 10; i++) {
 811                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
 812
 813                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
 814                         break;
 815
 816                 udelay(10);
 817         }
 818
 819         return i == timeout_us / 10;
 820 }
 821
 822 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
 823                                    u32 len)
 824 {
 825         int err;
 826         u32 i, bufoff, msgoff, maxlen, apedata;
 827
 828         if (!tg3_flag(tp, APE_HAS_NCSI))
 829                 return 0;
 830
 831         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
 832         if (apedata != APE_SEG_SIG_MAGIC)
 833                 return -ENODEV;
 834
 835         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 836         if (!(apedata & APE_FW_STATUS_READY))
 837                 return -EAGAIN;
 838
 839         bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
 840                  TG3_APE_SHMEM_BASE;
 841         msgoff = bufoff + 2 * sizeof(u32);
 842         maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
 843
 844         while (len) {
 845                 u32 length;
 846
 847                 /* Cap xfer sizes to scratchpad limits. */
 848                 length = (len > maxlen) ? maxlen : len;
 849                 len -= length;
 850
 851                 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 852                 if (!(apedata & APE_FW_STATUS_READY))
 853                         return -EAGAIN;
 854
 855                 /* Wait for up to 1 msec for APE to service previous event. */
 856                 err = tg3_ape_event_lock(tp, 1000);
 857                 if (err)
 858                         return err;
 859
 860                 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
 861                           APE_EVENT_STATUS_SCRTCHPD_READ |
 862                           APE_EVENT_STATUS_EVENT_PENDING;
 863                 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
 864
 865                 tg3_ape_write32(tp, bufoff, base_off);
 866                 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
 867
 868                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 869                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
 870
 871                 base_off += length;
 872
 873                 if (tg3_ape_wait_for_event(tp, 30000))
 874                         return -EAGAIN;
 875
 876                 for (i = 0; length; i += 4, length -= 4) {
 877                         u32 val = tg3_ape_read32(tp, msgoff + i);
 878                         memcpy(data, &val, sizeof(u32));
 879                         data++;
 880                 }
 881         }
 882
 883         return 0;
 884 }
 885
 886 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
 887 {
 888         int err;
 889         u32 apedata;
 890
 891         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
 892         if (apedata != APE_SEG_SIG_MAGIC)
 893                 return -EAGAIN;
 894
 895         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 896         if (!(apedata & APE_FW_STATUS_READY))
 897                 return -EAGAIN;
 898
 899         /* Wait for up to 1 millisecond for APE to service previous event. */
 900         err = tg3_ape_event_lock(tp, 1000);
 901         if (err)
 902                 return err;
 903
 904         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
 905                         event | APE_EVENT_STATUS_EVENT_PENDING);
 906
 907         tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 908         tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
 909
 910         return 0;
 911 }
 912
 913 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
 914 {
 915         u32 event;
 916         u32 apedata;
 917
 918         if (!tg3_flag(tp, ENABLE_APE))
 919                 return;
 920
 921         switch (kind) {
 922         case RESET_KIND_INIT:
 923                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
 924                                 APE_HOST_SEG_SIG_MAGIC);
 925                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
 926                                 APE_HOST_SEG_LEN_MAGIC);
 927                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
 928                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
 929                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
 930                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
 931                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
 932                                 APE_HOST_BEHAV_NO_PHYLOCK);
 933                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
 934                                     TG3_APE_HOST_DRVR_STATE_START);
 935
 936                 event = APE_EVENT_STATUS_STATE_START;
 937                 break;
 938         case RESET_KIND_SHUTDOWN:
 939                 /* With the interface we are currently using,
 940                  * APE does not track driver state.  Wiping
 941                  * out the HOST SEGMENT SIGNATURE forces
 942                  * the APE to assume OS absent status.
 943                  */
 944                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
 945
 946                 if (device_may_wakeup(&tp->pdev->dev) &&
 947                     tg3_flag(tp, WOL_ENABLE)) {
 948                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
 949                                             TG3_APE_HOST_WOL_SPEED_AUTO);
 950                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
 951                 } else
 952                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
 953
 954                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
 955
 956                 event = APE_EVENT_STATUS_STATE_UNLOAD;
 957                 break;
 958         case RESET_KIND_SUSPEND:
 959                 event = APE_EVENT_STATUS_STATE_SUSPEND;
 960                 break;
 961         default:
 962                 return;
 963         }
 964
 965         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
 966
 967         tg3_ape_send_event(tp, event);
 968 }
 969
 970 static void tg3_disable_ints(struct tg3 *tp)
 971 {
 972         int i;
 973
 974         tw32(TG3PCI_MISC_HOST_CTRL,
 975              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 976         for (i = 0; i < tp->irq_max; i++)
 977                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 978 }
 979
 980 static void tg3_enable_ints(struct tg3 *tp)
 981 {
 982         int i;
 983
 984         tp->irq_sync = 0;
 985         wmb();
 986
 987         tw32(TG3PCI_MISC_HOST_CTRL,
 988              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 989
 990         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 991         for (i = 0; i < tp->irq_cnt; i++) {
 992                 struct tg3_napi *tnapi = &tp->napi[i];
 993
 994                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 995                 if (tg3_flag(tp, 1SHOT_MSI))
 996                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 997
 998                 tp->coal_now |= tnapi->coal_now;
 999         }
1000
1001         /* Force an initial interrupt */
1002         if (!tg3_flag(tp, TAGGED_STATUS) &&
1003             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1004                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1005         else
1006                 tw32(HOSTCC_MODE, tp->coal_now);
1007
1008         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1009 }
1010
1011 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1012 {
1013         struct tg3 *tp = tnapi->tp;
1014         struct tg3_hw_status *sblk = tnapi->hw_status;
1015         unsigned int work_exists = 0;
1016
1017         /* check for phy events */
1018         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1019                 if (sblk->status & SD_STATUS_LINK_CHG)
1020                         work_exists = 1;
1021         }
1022
1023         /* check for TX work to do */
1024         if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1025                 work_exists = 1;
1026
1027         /* check for RX work to do */
1028         if (tnapi->rx_rcb_prod_idx &&
1029             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1030                 work_exists = 1;
1031
1032         return work_exists;
1033 }
1034
1035 /* tg3_int_reenable
1036  *  similar to tg3_enable_ints, but it accurately determines whether there
1037  *  is new work pending and can return without flushing the PIO write
1038  *  which reenables interrupts
1039  */
1040 static void tg3_int_reenable(struct tg3_napi *tnapi)
1041 {
1042         struct tg3 *tp = tnapi->tp;
1043
1044         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1045         mmiowb();
1046
1047         /* When doing tagged status, this work check is unnecessary.
1048          * The last_tag we write above tells the chip which piece of
1049          * work we've completed.
1050          */
1051         if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1052                 tw32(HOSTCC_MODE, tp->coalesce_mode |
1053                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
1054 }
1055
1056 static void tg3_switch_clocks(struct tg3 *tp)
1057 {
1058         u32 clock_ctrl;
1059         u32 orig_clock_ctrl;
1060
1061         if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1062                 return;
1063
1064         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1065
1066         orig_clock_ctrl = clock_ctrl;
1067         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1068                        CLOCK_CTRL_CLKRUN_OENABLE |
1069                        0x1f);
1070         tp->pci_clock_ctrl = clock_ctrl;
1071
1072         if (tg3_flag(tp, 5705_PLUS)) {
1073                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1074                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1075                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1076                 }
1077         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1078                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1079                             clock_ctrl |
1080                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1081                             40);
1082                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1083                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
1084                             40);
1085         }
1086         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1087 }
1088
1089 #define PHY_BUSY_LOOPS  5000
1090
1091 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1092 {
1093         u32 frame_val;
1094         unsigned int loops;
1095         int ret;
1096
1097         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1098                 tw32_f(MAC_MI_MODE,
1099                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1100                 udelay(80);
1101         }
1102
1103         tg3_ape_lock(tp, tp->phy_ape_lock);
1104
1105         *val = 0x0;
1106
1107         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1108                       MI_COM_PHY_ADDR_MASK);
1109         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1110                       MI_COM_REG_ADDR_MASK);
1111         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1112
1113         tw32_f(MAC_MI_COM, frame_val);
1114
1115         loops = PHY_BUSY_LOOPS;
1116         while (loops != 0) {
1117                 udelay(10);
1118                 frame_val = tr32(MAC_MI_COM);
1119
1120                 if ((frame_val & MI_COM_BUSY) == 0) {
1121                         udelay(5);
1122                         frame_val = tr32(MAC_MI_COM);
1123                         break;
1124                 }
1125                 loops -= 1;
1126         }
1127
1128         ret = -EBUSY;
1129         if (loops != 0) {
1130                 *val = frame_val & MI_COM_DATA_MASK;
1131                 ret = 0;
1132         }
1133
1134         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1135                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1136                 udelay(80);
1137         }
1138
1139         tg3_ape_unlock(tp, tp->phy_ape_lock);
1140
1141         return ret;
1142 }
1143
1144 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1145 {
1146         u32 frame_val;
1147         unsigned int loops;
1148         int ret;
1149
1150         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1151             (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1152                 return 0;
1153
1154         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1155                 tw32_f(MAC_MI_MODE,
1156                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1157                 udelay(80);
1158         }
1159
1160         tg3_ape_lock(tp, tp->phy_ape_lock);
1161
1162         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1163                       MI_COM_PHY_ADDR_MASK);
1164         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1165                       MI_COM_REG_ADDR_MASK);
1166         frame_val |= (val & MI_COM_DATA_MASK);
1167         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1168
1169         tw32_f(MAC_MI_COM, frame_val);
1170
1171         loops = PHY_BUSY_LOOPS;
1172         while (loops != 0) {
1173                 udelay(10);
1174                 frame_val = tr32(MAC_MI_COM);
1175                 if ((frame_val & MI_COM_BUSY) == 0) {
1176                         udelay(5);
1177                         frame_val = tr32(MAC_MI_COM);
1178                         break;
1179                 }
1180                 loops -= 1;
1181         }
1182
1183         ret = -EBUSY;
1184         if (loops != 0)
1185                 ret = 0;
1186
1187         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1188                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1189                 udelay(80);
1190         }
1191
1192         tg3_ape_unlock(tp, tp->phy_ape_lock);
1193
1194         return ret;
1195 }
1196
1197 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1198 {
1199         int err;
1200
1201         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1206         if (err)
1207                 goto done;
1208
1209         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1210                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1211         if (err)
1212                 goto done;
1213
1214         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1215
1216 done:
1217         return err;
1218 }
1219
1220 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1221 {
1222         int err;
1223
1224         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1225         if (err)
1226                 goto done;
1227
1228         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1229         if (err)
1230                 goto done;
1231
1232         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1233                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1234         if (err)
1235                 goto done;
1236
1237         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1238
1239 done:
1240         return err;
1241 }
1242
1243 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1244 {
1245         int err;
1246
1247         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1248         if (!err)
1249                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1250
1251         return err;
1252 }
1253
1254 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1255 {
1256         int err;
1257
1258         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1259         if (!err)
1260                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1261
1262         return err;
1263 }
1264
1265 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1266 {
1267         int err;
1268
1269         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1270                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1271                            MII_TG3_AUXCTL_SHDWSEL_MISC);
1272         if (!err)
1273                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1274
1275         return err;
1276 }
1277
1278 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1279 {
1280         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1281                 set |= MII_TG3_AUXCTL_MISC_WREN;
1282
1283         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1284 }
1285
1286 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1287 {
1288         u32 val;
1289         int err;
1290
1291         err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1292
1293         if (err)
1294                 return err;
1295         if (enable)
1296
1297                 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1298         else
1299                 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1300
1301         err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1302                                    val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1303
1304         return err;
1305 }
1306
1307 static int tg3_bmcr_reset(struct tg3 *tp)
1308 {
1309         u32 phy_control;
1310         int limit, err;
1311
1312         /* OK, reset it, and poll the BMCR_RESET bit until it
1313          * clears or we time out.
1314          */
1315         phy_control = BMCR_RESET;
1316         err = tg3_writephy(tp, MII_BMCR, phy_control);
1317         if (err != 0)
1318                 return -EBUSY;
1319
1320         limit = 5000;
1321         while (limit--) {
1322                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1323                 if (err != 0)
1324                         return -EBUSY;
1325
1326                 if ((phy_control & BMCR_RESET) == 0) {
1327                         udelay(40);
1328                         break;
1329                 }
1330                 udelay(10);
1331         }
1332         if (limit < 0)
1333                 return -EBUSY;
1334
1335         return 0;
1336 }
1337
1338 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1339 {
1340         struct tg3 *tp = bp->priv;
1341         u32 val;
1342
1343         spin_lock_bh(&tp->lock);
1344
1345         if (tg3_readphy(tp, reg, &val))
1346                 val = -EIO;
1347
1348         spin_unlock_bh(&tp->lock);
1349
1350         return val;
1351 }
1352
1353 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1354 {
1355         struct tg3 *tp = bp->priv;
1356         u32 ret = 0;
1357
1358         spin_lock_bh(&tp->lock);
1359
1360         if (tg3_writephy(tp, reg, val))
1361                 ret = -EIO;
1362
1363         spin_unlock_bh(&tp->lock);
1364
1365         return ret;
1366 }
1367
1368 static int tg3_mdio_reset(struct mii_bus *bp)
1369 {
1370         return 0;
1371 }
1372
1373 static void tg3_mdio_config_5785(struct tg3 *tp)
1374 {
1375         u32 val;
1376         struct phy_device *phydev;
1377
1378         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1379         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1380         case PHY_ID_BCM50610:
1381         case PHY_ID_BCM50610M:
1382                 val = MAC_PHYCFG2_50610_LED_MODES;
1383                 break;
1384         case PHY_ID_BCMAC131:
1385                 val = MAC_PHYCFG2_AC131_LED_MODES;
1386                 break;
1387         case PHY_ID_RTL8211C:
1388                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1389                 break;
1390         case PHY_ID_RTL8201E:
1391                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1392                 break;
1393         default:
1394                 return;
1395         }
1396
1397         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1398                 tw32(MAC_PHYCFG2, val);
1399
1400                 val = tr32(MAC_PHYCFG1);
1401                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1402                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1403                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1404                 tw32(MAC_PHYCFG1, val);
1405
1406                 return;
1407         }
1408
1409         if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1410                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1411                        MAC_PHYCFG2_FMODE_MASK_MASK |
1412                        MAC_PHYCFG2_GMODE_MASK_MASK |
1413                        MAC_PHYCFG2_ACT_MASK_MASK   |
1414                        MAC_PHYCFG2_QUAL_MASK_MASK |
1415                        MAC_PHYCFG2_INBAND_ENABLE;
1416
1417         tw32(MAC_PHYCFG2, val);
1418
1419         val = tr32(MAC_PHYCFG1);
1420         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1421                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1422         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1423                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1424                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1425                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1426                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1427         }
1428         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1429                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1430         tw32(MAC_PHYCFG1, val);
1431
1432         val = tr32(MAC_EXT_RGMII_MODE);
1433         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1434                  MAC_RGMII_MODE_RX_QUALITY |
1435                  MAC_RGMII_MODE_RX_ACTIVITY |
1436                  MAC_RGMII_MODE_RX_ENG_DET |
1437                  MAC_RGMII_MODE_TX_ENABLE |
1438                  MAC_RGMII_MODE_TX_LOWPWR |
1439                  MAC_RGMII_MODE_TX_RESET);
1440         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1441                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1442                         val |= MAC_RGMII_MODE_RX_INT_B |
1443                                MAC_RGMII_MODE_RX_QUALITY |
1444                                MAC_RGMII_MODE_RX_ACTIVITY |
1445                                MAC_RGMII_MODE_RX_ENG_DET;
1446                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1447                         val |= MAC_RGMII_MODE_TX_ENABLE |
1448                                MAC_RGMII_MODE_TX_LOWPWR |
1449                                MAC_RGMII_MODE_TX_RESET;
1450         }
1451         tw32(MAC_EXT_RGMII_MODE, val);
1452 }
1453
1454 static void tg3_mdio_start(struct tg3 *tp)
1455 {
1456         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1457         tw32_f(MAC_MI_MODE, tp->mi_mode);
1458         udelay(80);
1459
1460         if (tg3_flag(tp, MDIOBUS_INITED) &&
1461             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1462                 tg3_mdio_config_5785(tp);
1463 }
1464
1465 static int tg3_mdio_init(struct tg3 *tp)
1466 {
1467         int i;
1468         u32 reg;
1469         struct phy_device *phydev;
1470
1471         if (tg3_flag(tp, 5717_PLUS)) {
1472                 u32 is_serdes;
1473
1474                 tp->phy_addr = tp->pci_fn + 1;
1475
1476                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1477                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1478                 else
1479                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1480                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1481                 if (is_serdes)
1482                         tp->phy_addr += 7;
1483         } else
1484                 tp->phy_addr = TG3_PHY_MII_ADDR;
1485
1486         tg3_mdio_start(tp);
1487
1488         if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1489                 return 0;
1490
1491         tp->mdio_bus = mdiobus_alloc();
1492         if (tp->mdio_bus == NULL)
1493                 return -ENOMEM;
1494
1495         tp->mdio_bus->name     = "tg3 mdio bus";
1496         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1497                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1498         tp->mdio_bus->priv     = tp;
1499         tp->mdio_bus->parent   = &tp->pdev->dev;
1500         tp->mdio_bus->read     = &tg3_mdio_read;
1501         tp->mdio_bus->write    = &tg3_mdio_write;
1502         tp->mdio_bus->reset    = &tg3_mdio_reset;
1503         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1504         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1505
1506         for (i = 0; i < PHY_MAX_ADDR; i++)
1507                 tp->mdio_bus->irq[i] = PHY_POLL;
1508
1509         /* The bus registration will look for all the PHYs on the mdio bus.
1510          * Unfortunately, it does not ensure the PHY is powered up before
1511          * accessing the PHY ID registers.  A chip reset is the
1512          * quickest way to bring the device back to an operational state..
1513          */
1514         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1515                 tg3_bmcr_reset(tp);
1516
1517         i = mdiobus_register(tp->mdio_bus);
1518         if (i) {
1519                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1520                 mdiobus_free(tp->mdio_bus);
1521                 return i;
1522         }
1523
1524         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1525
1526         if (!phydev || !phydev->drv) {
1527                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1528                 mdiobus_unregister(tp->mdio_bus);
1529                 mdiobus_free(tp->mdio_bus);
1530                 return -ENODEV;
1531         }
1532
1533         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1534         case PHY_ID_BCM57780:
1535                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1536                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1537                 break;
1538         case PHY_ID_BCM50610:
1539         case PHY_ID_BCM50610M:
1540                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1541                                      PHY_BRCM_RX_REFCLK_UNUSED |
1542                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1543                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1544                 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1545                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1546                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1547                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1548                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1549                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1550                 /* fallthru */
1551         case PHY_ID_RTL8211C:
1552                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1553                 break;
1554         case PHY_ID_RTL8201E:
1555         case PHY_ID_BCMAC131:
1556                 phydev->interface = PHY_INTERFACE_MODE_MII;
1557                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1558                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1559                 break;
1560         }
1561
1562         tg3_flag_set(tp, MDIOBUS_INITED);
1563
1564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1565                 tg3_mdio_config_5785(tp);
1566
1567         return 0;
1568 }
1569
1570 static void tg3_mdio_fini(struct tg3 *tp)
1571 {
1572         if (tg3_flag(tp, MDIOBUS_INITED)) {
1573                 tg3_flag_clear(tp, MDIOBUS_INITED);
1574                 mdiobus_unregister(tp->mdio_bus);
1575                 mdiobus_free(tp->mdio_bus);
1576         }
1577 }
1578
1579 /* tp->lock is held. */
1580 static inline void tg3_generate_fw_event(struct tg3 *tp)
1581 {
1582         u32 val;
1583
1584         val = tr32(GRC_RX_CPU_EVENT);
1585         val |= GRC_RX_CPU_DRIVER_EVENT;
1586         tw32_f(GRC_RX_CPU_EVENT, val);
1587
1588         tp->last_event_jiffies = jiffies;
1589 }
1590
1591 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1592
1593 /* tp->lock is held. */
1594 static void tg3_wait_for_event_ack(struct tg3 *tp)
1595 {
1596         int i;
1597         unsigned int delay_cnt;
1598         long time_remain;
1599
1600         /* If enough time has passed, no wait is necessary. */
1601         time_remain = (long)(tp->last_event_jiffies + 1 +
1602                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1603                       (long)jiffies;
1604         if (time_remain < 0)
1605                 return;
1606
1607         /* Check if we can shorten the wait time. */
1608         delay_cnt = jiffies_to_usecs(time_remain);
1609         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1610                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1611         delay_cnt = (delay_cnt >> 3) + 1;
1612
1613         for (i = 0; i < delay_cnt; i++) {
1614                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1615                         break;
1616                 udelay(8);
1617         }
1618 }
1619
1620 /* tp->lock is held. */
1621 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1622 {
1623         u32 reg, val;
1624
1625         val = 0;
1626         if (!tg3_readphy(tp, MII_BMCR, &reg))
1627                 val = reg << 16;
1628         if (!tg3_readphy(tp, MII_BMSR, &reg))
1629                 val |= (reg & 0xffff);
1630         *data++ = val;
1631
1632         val = 0;
1633         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1634                 val = reg << 16;
1635         if (!tg3_readphy(tp, MII_LPA, &reg))
1636                 val |= (reg & 0xffff);
1637         *data++ = val;
1638
1639         val = 0;
1640         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1641                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1642                         val = reg << 16;
1643                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1644                         val |= (reg & 0xffff);
1645         }
1646         *data++ = val;
1647
1648         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1649                 val = reg << 16;
1650         else
1651                 val = 0;
1652         *data++ = val;
1653 }
1654
1655 /* tp->lock is held. */
1656 static void tg3_ump_link_report(struct tg3 *tp)
1657 {
1658         u32 data[4];
1659
1660         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1661                 return;
1662
1663         tg3_phy_gather_ump_data(tp, data);
1664
1665         tg3_wait_for_event_ack(tp);
1666
1667         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1668         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1669         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1670         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1671         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1672         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1673
1674         tg3_generate_fw_event(tp);
1675 }
1676
1677 /* tp->lock is held. */
1678 static void tg3_stop_fw(struct tg3 *tp)
1679 {
1680         if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1681                 /* Wait for RX cpu to ACK the previous event. */
1682                 tg3_wait_for_event_ack(tp);
1683
1684                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1685
1686                 tg3_generate_fw_event(tp);
1687
1688                 /* Wait for RX cpu to ACK this event. */
1689                 tg3_wait_for_event_ack(tp);
1690         }
1691 }
1692
1693 /* tp->lock is held. */
1694 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1695 {
1696         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1697                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1698
1699         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1700                 switch (kind) {
1701                 case RESET_KIND_INIT:
1702                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1703                                       DRV_STATE_START);
1704                         break;
1705
1706                 case RESET_KIND_SHUTDOWN:
1707                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1708                                       DRV_STATE_UNLOAD);
1709                         break;
1710
1711                 case RESET_KIND_SUSPEND:
1712                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1713                                       DRV_STATE_SUSPEND);
1714                         break;
1715
1716                 default:
1717                         break;
1718                 }
1719         }
1720
1721         if (kind == RESET_KIND_INIT ||
1722             kind == RESET_KIND_SUSPEND)
1723                 tg3_ape_driver_state_change(tp, kind);
1724 }
1725
1726 /* tp->lock is held. */
1727 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1728 {
1729         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1730                 switch (kind) {
1731                 case RESET_KIND_INIT:
1732                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1733                                       DRV_STATE_START_DONE);
1734                         break;
1735
1736                 case RESET_KIND_SHUTDOWN:
1737                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1738                                       DRV_STATE_UNLOAD_DONE);
1739                         break;
1740
1741                 default:
1742                         break;
1743                 }
1744         }
1745
1746         if (kind == RESET_KIND_SHUTDOWN)
1747                 tg3_ape_driver_state_change(tp, kind);
1748 }
1749
1750 /* tp->lock is held. */
1751 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1752 {
1753         if (tg3_flag(tp, ENABLE_ASF)) {
1754                 switch (kind) {
1755                 case RESET_KIND_INIT:
1756                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1757                                       DRV_STATE_START);
1758                         break;
1759
1760                 case RESET_KIND_SHUTDOWN:
1761                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1762                                       DRV_STATE_UNLOAD);
1763                         break;
1764
1765                 case RESET_KIND_SUSPEND:
1766                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1767                                       DRV_STATE_SUSPEND);
1768                         break;
1769
1770                 default:
1771                         break;
1772                 }
1773         }
1774 }
1775
1776 static int tg3_poll_fw(struct tg3 *tp)
1777 {
1778         int i;
1779         u32 val;
1780
1781         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1782                 /* Wait up to 20ms for init done. */
1783                 for (i = 0; i < 200; i++) {
1784                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1785                                 return 0;
1786                         udelay(100);
1787                 }
1788                 return -ENODEV;
1789         }
1790
1791         /* Wait for firmware initialization to complete. */
1792         for (i = 0; i < 100000; i++) {
1793                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1794                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1795                         break;
1796                 udelay(10);
1797         }
1798
1799         /* Chip might not be fitted with firmware.  Some Sun onboard
1800          * parts are configured like that.  So don't signal the timeout
1801          * of the above loop as an error, but do report the lack of
1802          * running firmware once.
1803          */
1804         if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1805                 tg3_flag_set(tp, NO_FWARE_REPORTED);
1806
1807                 netdev_info(tp->dev, "No firmware running\n");
1808         }
1809
1810         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1811                 /* The 57765 A0 needs a little more
1812                  * time to do some important work.
1813                  */
1814                 mdelay(10);
1815         }
1816
1817         return 0;
1818 }
1819
1820 static void tg3_link_report(struct tg3 *tp)
1821 {
1822         if (!netif_carrier_ok(tp->dev)) {
1823                 netif_info(tp, link, tp->dev, "Link is down\n");
1824                 tg3_ump_link_report(tp);
1825         } else if (netif_msg_link(tp)) {
1826                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1827                             (tp->link_config.active_speed == SPEED_1000 ?
1828                              1000 :
1829                              (tp->link_config.active_speed == SPEED_100 ?
1830                               100 : 10)),
1831                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1832                              "full" : "half"));
1833
1834                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1835                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1836                             "on" : "off",
1837                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1838                             "on" : "off");
1839
1840                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1841                         netdev_info(tp->dev, "EEE is %s\n",
1842                                     tp->setlpicnt ? "enabled" : "disabled");
1843
1844                 tg3_ump_link_report(tp);
1845         }
1846 }
1847
1848 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1849 {
1850         u16 miireg;
1851
1852         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1853                 miireg = ADVERTISE_1000XPAUSE;
1854         else if (flow_ctrl & FLOW_CTRL_TX)
1855                 miireg = ADVERTISE_1000XPSE_ASYM;
1856         else if (flow_ctrl & FLOW_CTRL_RX)
1857                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1858         else
1859                 miireg = 0;
1860
1861         return miireg;
1862 }
1863
1864 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1865 {
1866         u8 cap = 0;
1867
1868         if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1869                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1870         } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1871                 if (lcladv & ADVERTISE_1000XPAUSE)
1872                         cap = FLOW_CTRL_RX;
1873                 if (rmtadv & ADVERTISE_1000XPAUSE)
1874                         cap = FLOW_CTRL_TX;
1875         }
1876
1877         return cap;
1878 }
1879
1880 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1881 {
1882         u8 autoneg;
1883         u8 flowctrl = 0;
1884         u32 old_rx_mode = tp->rx_mode;
1885         u32 old_tx_mode = tp->tx_mode;
1886
1887         if (tg3_flag(tp, USE_PHYLIB))
1888                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1889         else
1890                 autoneg = tp->link_config.autoneg;
1891
1892         if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1893                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1894                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1895                 else
1896                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1897         } else
1898                 flowctrl = tp->link_config.flowctrl;
1899
1900         tp->link_config.active_flowctrl = flowctrl;
1901
1902         if (flowctrl & FLOW_CTRL_RX)
1903                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1904         else
1905                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1906
1907         if (old_rx_mode != tp->rx_mode)
1908                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1909
1910         if (flowctrl & FLOW_CTRL_TX)
1911                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1912         else
1913                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1914
1915         if (old_tx_mode != tp->tx_mode)
1916                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1917 }
1918
1919 static void tg3_adjust_link(struct net_device *dev)
1920 {
1921         u8 oldflowctrl, linkmesg = 0;
1922         u32 mac_mode, lcl_adv, rmt_adv;
1923         struct tg3 *tp = netdev_priv(dev);
1924         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1925
1926         spin_lock_bh(&tp->lock);
1927
1928         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1929                                     MAC_MODE_HALF_DUPLEX);
1930
1931         oldflowctrl = tp->link_config.active_flowctrl;
1932
1933         if (phydev->link) {
1934                 lcl_adv = 0;
1935                 rmt_adv = 0;
1936
1937                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1938                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1939                 else if (phydev->speed == SPEED_1000 ||
1940                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1941                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1942                 else
1943                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1944
1945                 if (phydev->duplex == DUPLEX_HALF)
1946                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1947                 else {
1948                         lcl_adv = mii_advertise_flowctrl(
1949                                   tp->link_config.flowctrl);
1950
1951                         if (phydev->pause)
1952                                 rmt_adv = LPA_PAUSE_CAP;
1953                         if (phydev->asym_pause)
1954                                 rmt_adv |= LPA_PAUSE_ASYM;
1955                 }
1956
1957                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1958         } else
1959                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1960
1961         if (mac_mode != tp->mac_mode) {
1962                 tp->mac_mode = mac_mode;
1963                 tw32_f(MAC_MODE, tp->mac_mode);
1964                 udelay(40);
1965         }
1966
1967         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1968                 if (phydev->speed == SPEED_10)
1969                         tw32(MAC_MI_STAT,
1970                              MAC_MI_STAT_10MBPS_MODE |
1971                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1972                 else
1973                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1974         }
1975
1976         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1977                 tw32(MAC_TX_LENGTHS,
1978                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1979                       (6 << TX_LENGTHS_IPG_SHIFT) |
1980                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1981         else
1982                 tw32(MAC_TX_LENGTHS,
1983                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1984                       (6 << TX_LENGTHS_IPG_SHIFT) |
1985                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1986
1987         if (phydev->link != tp->old_link ||
1988             phydev->speed != tp->link_config.active_speed ||
1989             phydev->duplex != tp->link_config.active_duplex ||
1990             oldflowctrl != tp->link_config.active_flowctrl)
1991                 linkmesg = 1;
1992
1993         tp->old_link = phydev->link;
1994         tp->link_config.active_speed = phydev->speed;
1995         tp->link_config.active_duplex = phydev->duplex;
1996
1997         spin_unlock_bh(&tp->lock);
1998
1999         if (linkmesg)
2000                 tg3_link_report(tp);
2001 }
2002
2003 static int tg3_phy_init(struct tg3 *tp)
2004 {
2005         struct phy_device *phydev;
2006
2007         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2008                 return 0;
2009
2010         /* Bring the PHY back to a known state. */
2011         tg3_bmcr_reset(tp);
2012
2013         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2014
2015         /* Attach the MAC to the PHY. */
2016         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
2017                              phydev->dev_flags, phydev->interface);
2018         if (IS_ERR(phydev)) {
2019                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2020                 return PTR_ERR(phydev);
2021         }
2022
2023         /* Mask with MAC supported features. */
2024         switch (phydev->interface) {
2025         case PHY_INTERFACE_MODE_GMII:
2026         case PHY_INTERFACE_MODE_RGMII:
2027                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2028                         phydev->supported &= (PHY_GBIT_FEATURES |
2029                                               SUPPORTED_Pause |
2030                                               SUPPORTED_Asym_Pause);
2031                         break;
2032                 }
2033                 /* fallthru */
2034         case PHY_INTERFACE_MODE_MII:
2035                 phydev->supported &= (PHY_BASIC_FEATURES |
2036                                       SUPPORTED_Pause |
2037                                       SUPPORTED_Asym_Pause);
2038                 break;
2039         default:
2040                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2041                 return -EINVAL;
2042         }
2043
2044         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2045
2046         phydev->advertising = phydev->supported;
2047
2048         return 0;
2049 }
2050
2051 static void tg3_phy_start(struct tg3 *tp)
2052 {
2053         struct phy_device *phydev;
2054
2055         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2056                 return;
2057
2058         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2059
2060         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2061                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2062                 phydev->speed = tp->link_config.speed;
2063                 phydev->duplex = tp->link_config.duplex;
2064                 phydev->autoneg = tp->link_config.autoneg;
2065                 phydev->advertising = tp->link_config.advertising;
2066         }
2067
2068         phy_start(phydev);
2069
2070         phy_start_aneg(phydev);
2071 }
2072
2073 static void tg3_phy_stop(struct tg3 *tp)
2074 {
2075         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2076                 return;
2077
2078         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2079 }
2080
2081 static void tg3_phy_fini(struct tg3 *tp)
2082 {
2083         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2084                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2085                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2086         }
2087 }
2088
2089 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2090 {
2091         int err;
2092         u32 val;
2093
2094         if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2095                 return 0;
2096
2097         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2098                 /* Cannot do read-modify-write on 5401 */
2099                 err = tg3_phy_auxctl_write(tp,
2100                                            MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2101                                            MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2102                                            0x4c20);
2103                 goto done;
2104         }
2105
2106         err = tg3_phy_auxctl_read(tp,
2107                                   MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2108         if (err)
2109                 return err;
2110
2111         val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2112         err = tg3_phy_auxctl_write(tp,
2113                                    MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2114
2115 done:
2116         return err;
2117 }
2118
2119 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2120 {
2121         u32 phytest;
2122
2123         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2124                 u32 phy;
2125
2126                 tg3_writephy(tp, MII_TG3_FET_TEST,
2127                              phytest | MII_TG3_FET_SHADOW_EN);
2128                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2129                         if (enable)
2130                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2131                         else
2132                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2133                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2134                 }
2135                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2136         }
2137 }
2138
2139 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2140 {
2141         u32 reg;
2142
2143         if (!tg3_flag(tp, 5705_PLUS) ||
2144             (tg3_flag(tp, 5717_PLUS) &&
2145              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2146                 return;
2147
2148         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2149                 tg3_phy_fet_toggle_apd(tp, enable);
2150                 return;
2151         }
2152
2153         reg = MII_TG3_MISC_SHDW_WREN |
2154               MII_TG3_MISC_SHDW_SCR5_SEL |
2155               MII_TG3_MISC_SHDW_SCR5_LPED |
2156               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2157               MII_TG3_MISC_SHDW_SCR5_SDTL |
2158               MII_TG3_MISC_SHDW_SCR5_C125OE;
2159         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2160                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2161
2162         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2163
2164
2165         reg = MII_TG3_MISC_SHDW_WREN |
2166               MII_TG3_MISC_SHDW_APD_SEL |
2167               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2168         if (enable)
2169                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2170
2171         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2172 }
2173
2174 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2175 {
2176         u32 phy;
2177
2178         if (!tg3_flag(tp, 5705_PLUS) ||
2179             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2180                 return;
2181
2182         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2183                 u32 ephy;
2184
2185                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2186                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2187
2188                         tg3_writephy(tp, MII_TG3_FET_TEST,
2189                                      ephy | MII_TG3_FET_SHADOW_EN);
2190                         if (!tg3_readphy(tp, reg, &phy)) {
2191                                 if (enable)
2192                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2193                                 else
2194                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2195                                 tg3_writephy(tp, reg, phy);
2196                         }
2197                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2198                 }
2199         } else {
2200                 int ret;
2201
2202                 ret = tg3_phy_auxctl_read(tp,
2203                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2204                 if (!ret) {
2205                         if (enable)
2206                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2207                         else
2208                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2209                         tg3_phy_auxctl_write(tp,
2210                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2211                 }
2212         }
2213 }
2214
2215 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2216 {
2217         int ret;
2218         u32 val;
2219
2220         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2221                 return;
2222
2223         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2224         if (!ret)
2225                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2226                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2227 }
2228
2229 static void tg3_phy_apply_otp(struct tg3 *tp)
2230 {
2231         u32 otp, phy;
2232
2233         if (!tp->phy_otp)
2234                 return;
2235
2236         otp = tp->phy_otp;
2237
2238         if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2239                 return;
2240
2241         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2242         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2243         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2244
2245         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2246               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2247         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2248
2249         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2250         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2251         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2252
2253         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2254         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2255
2256         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2257         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2258
2259         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2260               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2261         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2262
2263         tg3_phy_toggle_auxctl_smdsp(tp, false);
2264 }
2265
2266 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2267 {
2268         u32 val;
2269
2270         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2271                 return;
2272
2273         tp->setlpicnt = 0;
2274
2275         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2276             current_link_up == 1 &&
2277             tp->link_config.active_duplex == DUPLEX_FULL &&
2278             (tp->link_config.active_speed == SPEED_100 ||
2279              tp->link_config.active_speed == SPEED_1000)) {
2280                 u32 eeectl;
2281
2282                 if (tp->link_config.active_speed == SPEED_1000)
2283                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2284                 else
2285                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2286
2287                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2288
2289                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2290                                   TG3_CL45_D7_EEERES_STAT, &val);
2291
2292                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2293                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2294                         tp->setlpicnt = 2;
2295         }
2296
2297         if (!tp->setlpicnt) {
2298                 if (current_link_up == 1 &&
2299                    !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2300                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2301                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2302                 }
2303
2304                 val = tr32(TG3_CPMU_EEE_MODE);
2305                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2306         }
2307 }
2308
2309 static void tg3_phy_eee_enable(struct tg3 *tp)
2310 {
2311         u32 val;
2312
2313         if (tp->link_config.active_speed == SPEED_1000 &&
2314             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2315              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2316              tg3_flag(tp, 57765_CLASS)) &&
2317             !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2318                 val = MII_TG3_DSP_TAP26_ALNOKO |
2319                       MII_TG3_DSP_TAP26_RMRXSTO;
2320                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2321                 tg3_phy_toggle_auxctl_smdsp(tp, false);
2322         }
2323
2324         val = tr32(TG3_CPMU_EEE_MODE);
2325         tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2326 }
2327
2328 static int tg3_wait_macro_done(struct tg3 *tp)
2329 {
2330         int limit = 100;
2331
2332         while (limit--) {
2333                 u32 tmp32;
2334
2335                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2336                         if ((tmp32 & 0x1000) == 0)
2337                                 break;
2338                 }
2339         }
2340         if (limit < 0)
2341                 return -EBUSY;
2342
2343         return 0;
2344 }
2345
2346 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2347 {
2348         static const u32 test_pat[4][6] = {
2349         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2350         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2351         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2352         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2353         };
2354         int chan;
2355
2356         for (chan = 0; chan < 4; chan++) {
2357                 int i;
2358
2359                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2360                              (chan * 0x2000) | 0x0200);
2361                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2362
2363                 for (i = 0; i < 6; i++)
2364                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2365                                      test_pat[chan][i]);
2366
2367                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2368                 if (tg3_wait_macro_done(tp)) {
2369                         *resetp = 1;
2370                         return -EBUSY;
2371                 }
2372
2373                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2374                              (chan * 0x2000) | 0x0200);
2375                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2376                 if (tg3_wait_macro_done(tp)) {
2377                         *resetp = 1;
2378                         return -EBUSY;
2379                 }
2380
2381                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2382                 if (tg3_wait_macro_done(tp)) {
2383                         *resetp = 1;
2384                         return -EBUSY;
2385                 }
2386
2387                 for (i = 0; i < 6; i += 2) {
2388                         u32 low, high;
2389
2390                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2391                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2392                             tg3_wait_macro_done(tp)) {
2393                                 *resetp = 1;
2394                                 return -EBUSY;
2395                         }
2396                         low &= 0x7fff;
2397                         high &= 0x000f;
2398                         if (low != test_pat[chan][i] ||
2399                             high != test_pat[chan][i+1]) {
2400                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2401                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2402                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2403
2404                                 return -EBUSY;
2405                         }
2406                 }
2407         }
2408
2409         return 0;
2410 }
2411
2412 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2413 {
2414         int chan;
2415
2416         for (chan = 0; chan < 4; chan++) {
2417                 int i;
2418
2419                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2420                              (chan * 0x2000) | 0x0200);
2421                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2422                 for (i = 0; i < 6; i++)
2423                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2424                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2425                 if (tg3_wait_macro_done(tp))
2426                         return -EBUSY;
2427         }
2428
2429         return 0;
2430 }
2431
2432 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2433 {
2434         u32 reg32, phy9_orig;
2435         int retries, do_phy_reset, err;
2436
2437         retries = 10;
2438         do_phy_reset = 1;
2439         do {
2440                 if (do_phy_reset) {
2441                         err = tg3_bmcr_reset(tp);
2442                         if (err)
2443                                 return err;
2444                         do_phy_reset = 0;
2445                 }
2446
2447                 /* Disable transmitter and interrupt.  */
2448                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2449                         continue;
2450
2451                 reg32 |= 0x3000;
2452                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2453
2454                 /* Set full-duplex, 1000 mbps.  */
2455                 tg3_writephy(tp, MII_BMCR,
2456                              BMCR_FULLDPLX | BMCR_SPEED1000);
2457
2458                 /* Set to master mode.  */
2459                 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2460                         continue;
2461
2462                 tg3_writephy(tp, MII_CTRL1000,
2463                              CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2464
2465                 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2466                 if (err)
2467                         return err;
2468
2469                 /* Block the PHY control access.  */
2470                 tg3_phydsp_write(tp, 0x8005, 0x0800);
2471
2472                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2473                 if (!err)
2474                         break;
2475         } while (--retries);
2476
2477         err = tg3_phy_reset_chanpat(tp);
2478         if (err)
2479                 return err;
2480
2481         tg3_phydsp_write(tp, 0x8005, 0x0000);
2482
2483         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2484         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2485
2486         tg3_phy_toggle_auxctl_smdsp(tp, false);
2487
2488         tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2489
2490         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2491                 reg32 &= ~0x3000;
2492                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2493         } else if (!err)
2494                 err = -EBUSY;
2495
2496         return err;
2497 }
2498
2499 static void tg3_carrier_on(struct tg3 *tp)
2500 {
2501         netif_carrier_on(tp->dev);
2502         tp->link_up = true;
2503 }
2504
2505 static void tg3_carrier_off(struct tg3 *tp)
2506 {
2507         netif_carrier_off(tp->dev);
2508         tp->link_up = false;
2509 }
2510
2511 /* This will reset the tigon3 PHY if there is no valid
2512  * link unless the FORCE argument is non-zero.
2513  */
2514 static int tg3_phy_reset(struct tg3 *tp)
2515 {
2516         u32 val, cpmuctrl;
2517         int err;
2518
2519         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2520                 val = tr32(GRC_MISC_CFG);
2521                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2522                 udelay(40);
2523         }
2524         err  = tg3_readphy(tp, MII_BMSR, &val);
2525         err |= tg3_readphy(tp, MII_BMSR, &val);
2526         if (err != 0)
2527                 return -EBUSY;
2528
2529         if (netif_running(tp->dev) && tp->link_up) {
2530                 tg3_carrier_off(tp);
2531                 tg3_link_report(tp);
2532         }
2533
2534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2536             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2537                 err = tg3_phy_reset_5703_4_5(tp);
2538                 if (err)
2539                         return err;
2540                 goto out;
2541         }
2542
2543         cpmuctrl = 0;
2544         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2545             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2546                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2547                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2548                         tw32(TG3_CPMU_CTRL,
2549                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2550         }
2551
2552         err = tg3_bmcr_reset(tp);
2553         if (err)
2554                 return err;
2555
2556         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2557                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2558                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2559
2560                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2561         }
2562
2563         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2564             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2565                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2566                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2567                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2568                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2569                         udelay(40);
2570                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2571                 }
2572         }
2573
2574         if (tg3_flag(tp, 5717_PLUS) &&
2575             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2576                 return 0;
2577
2578         tg3_phy_apply_otp(tp);
2579
2580         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2581                 tg3_phy_toggle_apd(tp, true);
2582         else
2583                 tg3_phy_toggle_apd(tp, false);
2584
2585 out:
2586         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2587             !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2588                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2589                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2590                 tg3_phy_toggle_auxctl_smdsp(tp, false);
2591         }
2592
2593         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2594                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2595                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2596         }
2597
2598         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2599                 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2600                         tg3_phydsp_write(tp, 0x000a, 0x310b);
2601                         tg3_phydsp_write(tp, 0x201f, 0x9506);
2602                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
2603                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2604                 }
2605         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2606                 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2607                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2608                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2609                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2610                                 tg3_writephy(tp, MII_TG3_TEST1,
2611                                              MII_TG3_TEST1_TRIM_EN | 0x4);
2612                         } else
2613                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2614
2615                         tg3_phy_toggle_auxctl_smdsp(tp, false);
2616                 }
2617         }
2618
2619         /* Set Extended packet length bit (bit 14) on all chips that */
2620         /* support jumbo frames */
2621         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2622                 /* Cannot do read-modify-write on 5401 */
2623                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2624         } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2625                 /* Set bit 14 with read-modify-write to preserve other bits */
2626                 err = tg3_phy_auxctl_read(tp,
2627                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2628                 if (!err)
2629                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2630                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2631         }
2632
2633         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2634          * jumbo frames transmission.
2635          */
2636         if (tg3_flag(tp, JUMBO_CAPABLE)) {
2637                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2638                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2639                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2640         }
2641
2642         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2643                 /* adjust output voltage */
2644                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2645         }
2646
2647         tg3_phy_toggle_automdix(tp, 1);
2648         tg3_phy_set_wirespeed(tp);
2649         return 0;
2650 }
2651
2652 #define TG3_GPIO_MSG_DRVR_PRES           0x00000001
2653 #define TG3_GPIO_MSG_NEED_VAUX           0x00000002
2654 #define TG3_GPIO_MSG_MASK                (TG3_GPIO_MSG_DRVR_PRES | \
2655                                           TG3_GPIO_MSG_NEED_VAUX)
2656 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2657         ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2658          (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2659          (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2660          (TG3_GPIO_MSG_DRVR_PRES << 12))
2661
2662 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2663         ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2664          (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2665          (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2666          (TG3_GPIO_MSG_NEED_VAUX << 12))
2667
2668 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2669 {
2670         u32 status, shift;
2671
2672         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2673             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2674                 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2675         else
2676                 status = tr32(TG3_CPMU_DRV_STATUS);
2677
2678         shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2679         status &= ~(TG3_GPIO_MSG_MASK << shift);
2680         status |= (newstat << shift);
2681
2682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2683             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2684                 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2685         else
2686                 tw32(TG3_CPMU_DRV_STATUS, status);
2687
2688         return status >> TG3_APE_GPIO_MSG_SHIFT;
2689 }
2690
2691 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2692 {
2693         if (!tg3_flag(tp, IS_NIC))
2694                 return 0;
2695
2696         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2697             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2698             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2699                 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2700                         return -EIO;
2701
2702                 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2703
2704                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2705                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2706
2707                 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2708         } else {
2709                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2710                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2711         }
2712
2713         return 0;
2714 }
2715
2716 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2717 {
2718         u32 grc_local_ctrl;
2719
2720         if (!tg3_flag(tp, IS_NIC) ||
2721             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2722             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2723                 return;
2724
2725         grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2726
2727         tw32_wait_f(GRC_LOCAL_CTRL,
2728                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2729                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2730
2731         tw32_wait_f(GRC_LOCAL_CTRL,
2732                     grc_local_ctrl,
2733                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2734
2735         tw32_wait_f(GRC_LOCAL_CTRL,
2736                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2737                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2738 }
2739
2740 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2741 {
2742         if (!tg3_flag(tp, IS_NIC))
2743                 return;
2744
2745         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2746             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2747                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2748                             (GRC_LCLCTRL_GPIO_OE0 |
2749                              GRC_LCLCTRL_GPIO_OE1 |
2750                              GRC_LCLCTRL_GPIO_OE2 |
2751                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2752                              GRC_LCLCTRL_GPIO_OUTPUT1),
2753                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2754         } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2755                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2756                 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2757                 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2758                                      GRC_LCLCTRL_GPIO_OE1 |
2759                                      GRC_LCLCTRL_GPIO_OE2 |
2760                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2761                                      GRC_LCLCTRL_GPIO_OUTPUT1 |
2762                                      tp->grc_local_ctrl;
2763                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2764                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2765
2766                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2767                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2768                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2769
2770                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2771                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2772                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2773         } else {
2774                 u32 no_gpio2;
2775                 u32 grc_local_ctrl = 0;
2776
2777                 /* Workaround to prevent overdrawing Amps. */
2778                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2779                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2780                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2781                                     grc_local_ctrl,
2782                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2783                 }
2784
2785                 /* On 5753 and variants, GPIO2 cannot be used. */
2786                 no_gpio2 = tp->nic_sram_data_cfg &
2787                            NIC_SRAM_DATA_CFG_NO_GPIO2;
2788
2789                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2790                                   GRC_LCLCTRL_GPIO_OE1 |
2791                                   GRC_LCLCTRL_GPIO_OE2 |
2792                                   GRC_LCLCTRL_GPIO_OUTPUT1 |
2793                                   GRC_LCLCTRL_GPIO_OUTPUT2;
2794                 if (no_gpio2) {
2795                         grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2796                                             GRC_LCLCTRL_GPIO_OUTPUT2);
2797                 }
2798                 tw32_wait_f(GRC_LOCAL_CTRL,
2799                             tp->grc_local_ctrl | grc_local_ctrl,
2800                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2801
2802                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2803
2804                 tw32_wait_f(GRC_LOCAL_CTRL,
2805                             tp->grc_local_ctrl | grc_local_ctrl,
2806                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2807
2808                 if (!no_gpio2) {
2809                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2810                         tw32_wait_f(GRC_LOCAL_CTRL,
2811                                     tp->grc_local_ctrl | grc_local_ctrl,
2812                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2813                 }
2814         }
2815 }
2816
2817 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2818 {
2819         u32 msg = 0;
2820
2821         /* Serialize power state transitions */
2822         if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2823                 return;
2824
2825         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2826                 msg = TG3_GPIO_MSG_NEED_VAUX;
2827
2828         msg = tg3_set_function_status(tp, msg);
2829
2830         if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2831                 goto done;
2832
2833         if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2834                 tg3_pwrsrc_switch_to_vaux(tp);
2835         else
2836                 tg3_pwrsrc_die_with_vmain(tp);
2837
2838 done:
2839         tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2840 }
2841
2842 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2843 {
2844         bool need_vaux = false;
2845
2846         /* The GPIOs do something completely different on 57765. */
2847         if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2848                 return;
2849
2850         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2851             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2852             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2853                 tg3_frob_aux_power_5717(tp, include_wol ?
2854                                         tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2855                 return;
2856         }
2857
2858         if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2859                 struct net_device *dev_peer;
2860
2861                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2862
2863                 /* remove_one() may have been run on the peer. */
2864                 if (dev_peer) {
2865                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2866
2867                         if (tg3_flag(tp_peer, INIT_COMPLETE))
2868                                 return;
2869
2870                         if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2871                             tg3_flag(tp_peer, ENABLE_ASF))
2872                                 need_vaux = true;
2873                 }
2874         }
2875
2876         if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2877             tg3_flag(tp, ENABLE_ASF))
2878                 need_vaux = true;
2879
2880         if (need_vaux)
2881                 tg3_pwrsrc_switch_to_vaux(tp);
2882         else
2883                 tg3_pwrsrc_die_with_vmain(tp);
2884 }
2885
2886 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2887 {
2888         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2889                 return 1;
2890         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2891                 if (speed != SPEED_10)
2892                         return 1;
2893         } else if (speed == SPEED_10)
2894                 return 1;
2895
2896         return 0;
2897 }
2898
2899 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2900 {
2901         u32 val;
2902
2903         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2904                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2905                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2906                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2907
2908                         sg_dig_ctrl |=
2909                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2910                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2911                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2912                 }
2913                 return;
2914         }
2915
2916         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2917                 tg3_bmcr_reset(tp);
2918                 val = tr32(GRC_MISC_CFG);
2919                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2920                 udelay(40);
2921                 return;
2922         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2923                 u32 phytest;
2924                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2925                         u32 phy;
2926
2927                         tg3_writephy(tp, MII_ADVERTISE, 0);
2928                         tg3_writephy(tp, MII_BMCR,
2929                                      BMCR_ANENABLE | BMCR_ANRESTART);
2930
2931                         tg3_writephy(tp, MII_TG3_FET_TEST,
2932                                      phytest | MII_TG3_FET_SHADOW_EN);
2933                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2934                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2935                                 tg3_writephy(tp,
2936                                              MII_TG3_FET_SHDW_AUXMODE4,
2937                                              phy);
2938                         }
2939                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2940                 }
2941                 return;
2942         } else if (do_low_power) {
2943                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2944                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2945
2946                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2947                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2948                       MII_TG3_AUXCTL_PCTL_VREG_11V;
2949                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2950         }
2951
2952         /* The PHY should not be powered down on some chips because
2953          * of bugs.
2954          */
2955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2957             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2958              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2959             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2960              !tp->pci_fn))
2961                 return;
2962
2963         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2964             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2965                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2966                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2967                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2968                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2969         }
2970
2971         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2972 }
2973
2974 /* tp->lock is held. */
2975 static int tg3_nvram_lock(struct tg3 *tp)
2976 {
2977         if (tg3_flag(tp, NVRAM)) {
2978                 int i;
2979
2980                 if (tp->nvram_lock_cnt == 0) {
2981                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2982                         for (i = 0; i < 8000; i++) {
2983                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2984                                         break;
2985                                 udelay(20);
2986                         }
2987                         if (i == 8000) {
2988                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2989                                 return -ENODEV;
2990                         }
2991                 }
2992                 tp->nvram_lock_cnt++;
2993         }
2994         return 0;
2995 }
2996
2997 /* tp->lock is held. */
2998 static void tg3_nvram_unlock(struct tg3 *tp)
2999 {
3000         if (tg3_flag(tp, NVRAM)) {
3001                 if (tp->nvram_lock_cnt > 0)
3002                         tp->nvram_lock_cnt--;
3003                 if (tp->nvram_lock_cnt == 0)
3004                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3005         }
3006 }
3007
3008 /* tp->lock is held. */
3009 static void tg3_enable_nvram_access(struct tg3 *tp)
3010 {
3011         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3012                 u32 nvaccess = tr32(NVRAM_ACCESS);
3013
3014                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3015         }
3016 }
3017
3018 /* tp->lock is held. */
3019 static void tg3_disable_nvram_access(struct tg3 *tp)
3020 {
3021         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3022                 u32 nvaccess = tr32(NVRAM_ACCESS);
3023
3024                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3025         }
3026 }
3027
3028 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3029                                         u32 offset, u32 *val)
3030 {
3031         u32 tmp;
3032         int i;
3033
3034         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3035                 return -EINVAL;
3036
3037         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3038                                         EEPROM_ADDR_DEVID_MASK |
3039                                         EEPROM_ADDR_READ);
3040         tw32(GRC_EEPROM_ADDR,
3041              tmp |
3042              (0 << EEPROM_ADDR_DEVID_SHIFT) |
3043              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3044               EEPROM_ADDR_ADDR_MASK) |
3045              EEPROM_ADDR_READ | EEPROM_ADDR_START);
3046
3047         for (i = 0; i < 1000; i++) {
3048                 tmp = tr32(GRC_EEPROM_ADDR);
3049
3050                 if (tmp & EEPROM_ADDR_COMPLETE)
3051                         break;
3052                 msleep(1);
3053         }
3054         if (!(tmp & EEPROM_ADDR_COMPLETE))
3055                 return -EBUSY;
3056
3057         tmp = tr32(GRC_EEPROM_DATA);
3058
3059         /*
3060          * The data will always be opposite the native endian
3061          * format.  Perform a blind byteswap to compensate.
3062          */
3063         *val = swab32(tmp);
3064
3065         return 0;
3066 }
3067
3068 #define NVRAM_CMD_TIMEOUT 10000
3069
3070 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3071 {
3072         int i;
3073
3074         tw32(NVRAM_CMD, nvram_cmd);
3075         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3076                 udelay(10);
3077                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3078                         udelay(10);
3079                         break;
3080                 }
3081         }
3082
3083         if (i == NVRAM_CMD_TIMEOUT)
3084                 return -EBUSY;
3085
3086         return 0;
3087 }
3088
3089 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3090 {
3091         if (tg3_flag(tp, NVRAM) &&
3092             tg3_flag(tp, NVRAM_BUFFERED) &&
3093             tg3_flag(tp, FLASH) &&
3094             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3095             (tp->nvram_jedecnum == JEDEC_ATMEL))
3096
3097                 addr = ((addr / tp->nvram_pagesize) <<
3098                         ATMEL_AT45DB0X1B_PAGE_POS) +
3099                        (addr % tp->nvram_pagesize);
3100
3101         return addr;
3102 }
3103
3104 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3105 {
3106         if (tg3_flag(tp, NVRAM) &&
3107             tg3_flag(tp, NVRAM_BUFFERED) &&
3108             tg3_flag(tp, FLASH) &&
3109             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3110             (tp->nvram_jedecnum == JEDEC_ATMEL))
3111
3112                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3113                         tp->nvram_pagesize) +
3114                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3115
3116         return addr;
3117 }
3118
3119 /* NOTE: Data read in from NVRAM is byteswapped according to
3120  * the byteswapping settings for all other register accesses.
3121  * tg3 devices are BE devices, so on a BE machine, the data
3122  * returned will be exactly as it is seen in NVRAM.  On a LE
3123  * machine, the 32-bit value will be byteswapped.
3124  */
3125 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3126 {
3127         int ret;
3128
3129         if (!tg3_flag(tp, NVRAM))
3130                 return tg3_nvram_read_using_eeprom(tp, offset, val);
3131
3132         offset = tg3_nvram_phys_addr(tp, offset);
3133
3134         if (offset > NVRAM_ADDR_MSK)
3135                 return -EINVAL;
3136
3137         ret = tg3_nvram_lock(tp);
3138         if (ret)
3139                 return ret;
3140
3141         tg3_enable_nvram_access(tp);
3142
3143         tw32(NVRAM_ADDR, offset);
3144         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3145                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3146
3147         if (ret == 0)
3148                 *val = tr32(NVRAM_RDDATA);
3149
3150         tg3_disable_nvram_access(tp);
3151
3152         tg3_nvram_unlock(tp);
3153
3154         return ret;
3155 }
3156
3157 /* Ensures NVRAM data is in bytestream format. */
3158 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3159 {
3160         u32 v;
3161         int res = tg3_nvram_read(tp, offset, &v);
3162         if (!res)
3163                 *val = cpu_to_be32(v);
3164         return res;
3165 }
3166
3167 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3168                                     u32 offset, u32 len, u8 *buf)
3169 {
3170         int i, j, rc = 0;
3171         u32 val;
3172
3173         for (i = 0; i < len; i += 4) {
3174                 u32 addr;
3175                 __be32 data;
3176
3177                 addr = offset + i;
3178
3179                 memcpy(&data, buf + i, 4);
3180
3181                 /*
3182                  * The SEEPROM interface expects the data to always be opposite
3183                  * the native endian format.  We accomplish this by reversing
3184                  * all the operations that would have been performed on the
3185                  * data from a call to tg3_nvram_read_be32().
3186                  */
3187                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3188
3189                 val = tr32(GRC_EEPROM_ADDR);
3190                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3191
3192                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3193                         EEPROM_ADDR_READ);
3194                 tw32(GRC_EEPROM_ADDR, val |
3195                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
3196                         (addr & EEPROM_ADDR_ADDR_MASK) |
3197                         EEPROM_ADDR_START |
3198                         EEPROM_ADDR_WRITE);
3199
3200                 for (j = 0; j < 1000; j++) {
3201                         val = tr32(GRC_EEPROM_ADDR);
3202
3203                         if (val & EEPROM_ADDR_COMPLETE)
3204                                 break;
3205                         msleep(1);
3206                 }
3207                 if (!(val & EEPROM_ADDR_COMPLETE)) {
3208                         rc = -EBUSY;
3209                         break;
3210                 }
3211         }
3212
3213         return rc;
3214 }
3215
3216 /* offset and length are dword aligned */
3217 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3218                 u8 *buf)
3219 {
3220         int ret = 0;
3221         u32 pagesize = tp->nvram_pagesize;
3222         u32 pagemask = pagesize - 1;
3223         u32 nvram_cmd;
3224         u8 *tmp;
3225
3226         tmp = kmalloc(pagesize, GFP_KERNEL);
3227         if (tmp == NULL)
3228                 return -ENOMEM;
3229
3230         while (len) {
3231                 int j;
3232                 u32 phy_addr, page_off, size;