]> git.openfabrics.org - ~shefty/rdma-dev.git/blob - drivers/net/ethernet/broadcom/tg3.c
tg3: Avoid null pointer dereference in tg3_interrupt in netconsole mode
[~shefty/rdma-dev.git] / drivers / net / ethernet / broadcom / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2012 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/hwmon.h>
48 #include <linux/hwmon-sysfs.h>
49
50 #include <net/checksum.h>
51 #include <net/ip.h>
52
53 #include <linux/io.h>
54 #include <asm/byteorder.h>
55 #include <linux/uaccess.h>
56
57 #include <uapi/linux/net_tstamp.h>
58 #include <linux/ptp_clock_kernel.h>
59
60 #ifdef CONFIG_SPARC
61 #include <asm/idprom.h>
62 #include <asm/prom.h>
63 #endif
64
65 #define BAR_0   0
66 #define BAR_2   2
67
68 #include "tg3.h"
69
70 /* Functions & macros to verify TG3_FLAGS types */
71
72 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
73 {
74         return test_bit(flag, bits);
75 }
76
77 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 {
79         set_bit(flag, bits);
80 }
81
82 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
83 {
84         clear_bit(flag, bits);
85 }
86
87 #define tg3_flag(tp, flag)                              \
88         _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
89 #define tg3_flag_set(tp, flag)                          \
90         _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
91 #define tg3_flag_clear(tp, flag)                        \
92         _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
93
94 #define DRV_MODULE_NAME         "tg3"
95 #define TG3_MAJ_NUM                     3
96 #define TG3_MIN_NUM                     128
97 #define DRV_MODULE_VERSION      \
98         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
99 #define DRV_MODULE_RELDATE      "December 03, 2012"
100
101 #define RESET_KIND_SHUTDOWN     0
102 #define RESET_KIND_INIT         1
103 #define RESET_KIND_SUSPEND      2
104
105 #define TG3_DEF_RX_MODE         0
106 #define TG3_DEF_TX_MODE         0
107 #define TG3_DEF_MSG_ENABLE        \
108         (NETIF_MSG_DRV          | \
109          NETIF_MSG_PROBE        | \
110          NETIF_MSG_LINK         | \
111          NETIF_MSG_TIMER        | \
112          NETIF_MSG_IFDOWN       | \
113          NETIF_MSG_IFUP         | \
114          NETIF_MSG_RX_ERR       | \
115          NETIF_MSG_TX_ERR)
116
117 #define TG3_GRC_LCLCTL_PWRSW_DELAY      100
118
119 /* length of time before we decide the hardware is borked,
120  * and dev->tx_timeout() should be called to fix the problem
121  */
122
123 #define TG3_TX_TIMEOUT                  (5 * HZ)
124
125 /* hardware minimum and maximum for a single frame's data payload */
126 #define TG3_MIN_MTU                     60
127 #define TG3_MAX_MTU(tp) \
128         (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
129
130 /* These numbers seem to be hard coded in the NIC firmware somehow.
131  * You can't change the ring sizes, but you can change where you place
132  * them in the NIC onboard memory.
133  */
134 #define TG3_RX_STD_RING_SIZE(tp) \
135         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
136          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
137 #define TG3_DEF_RX_RING_PENDING         200
138 #define TG3_RX_JMB_RING_SIZE(tp) \
139         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
140          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
141 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
142
143 /* Do not place this n-ring entries value into the tp struct itself,
144  * we really want to expose these constants to GCC so that modulo et
145  * al.  operations are done with shifts and masks instead of with
146  * hw multiply/modulo instructions.  Another solution would be to
147  * replace things like '% foo' with '& (foo - 1)'.
148  */
149
150 #define TG3_TX_RING_SIZE                512
151 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
152
153 #define TG3_RX_STD_RING_BYTES(tp) \
154         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
155 #define TG3_RX_JMB_RING_BYTES(tp) \
156         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
157 #define TG3_RX_RCB_RING_BYTES(tp) \
158         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
159 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
160                                  TG3_TX_RING_SIZE)
161 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
162
163 #define TG3_DMA_BYTE_ENAB               64
164
165 #define TG3_RX_STD_DMA_SZ               1536
166 #define TG3_RX_JMB_DMA_SZ               9046
167
168 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
169
170 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
171 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
172
173 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
174         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
175
176 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
177         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
178
179 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
180  * that are at least dword aligned when used in PCIX mode.  The driver
181  * works around this bug by double copying the packet.  This workaround
182  * is built into the normal double copy length check for efficiency.
183  *
184  * However, the double copy is only necessary on those architectures
185  * where unaligned memory accesses are inefficient.  For those architectures
186  * where unaligned memory accesses incur little penalty, we can reintegrate
187  * the 5701 in the normal rx path.  Doing so saves a device structure
188  * dereference by hardcoding the double copy threshold in place.
189  */
190 #define TG3_RX_COPY_THRESHOLD           256
191 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
192         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
193 #else
194         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
195 #endif
196
197 #if (NET_IP_ALIGN != 0)
198 #define TG3_RX_OFFSET(tp)       ((tp)->rx_offset)
199 #else
200 #define TG3_RX_OFFSET(tp)       (NET_SKB_PAD)
201 #endif
202
203 /* minimum number of free TX descriptors required to wake up TX process */
204 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
205 #define TG3_TX_BD_DMA_MAX_2K            2048
206 #define TG3_TX_BD_DMA_MAX_4K            4096
207
208 #define TG3_RAW_IP_ALIGN 2
209
210 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
211 #define TG3_FW_UPDATE_FREQ_SEC          (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
212
213 #define FIRMWARE_TG3            "tigon/tg3.bin"
214 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
215 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
216
217 static char version[] =
218         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
219
220 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
221 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
222 MODULE_LICENSE("GPL");
223 MODULE_VERSION(DRV_MODULE_VERSION);
224 MODULE_FIRMWARE(FIRMWARE_TG3);
225 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
226 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
227
228 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
229 module_param(tg3_debug, int, 0);
230 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
231
232 #define TG3_DRV_DATA_FLAG_10_100_ONLY   0x0001
233 #define TG3_DRV_DATA_FLAG_5705_10_100   0x0002
234
235 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
255          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
256                         TG3_DRV_DATA_FLAG_5705_10_100},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
258          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
259                         TG3_DRV_DATA_FLAG_5705_10_100},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
262          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
263                         TG3_DRV_DATA_FLAG_5705_10_100},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
269          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
275          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
278         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
279         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
280         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
281         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
282         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
283         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
284                         PCI_VENDOR_ID_LENOVO,
285                         TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
286          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
287         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
288         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
289          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
290         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
291         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
292         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
293         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
294         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
295         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
296         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
297         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
298         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
299         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
300         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
301         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
302         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
303         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
304         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
305         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
306         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
307         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
308         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
309                         PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
310          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
311         {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312                         PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
313          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
315         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
316         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
317          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
318         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
319         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
320         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
321         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
322         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
323         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
324         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
325         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
326         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
327          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
328         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
329          .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
330         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
331         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
332         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
333         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
334         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
335         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
336         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
337         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
338         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
339         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
340         {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
341         {}
342 };
343
344 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
345
346 static const struct {
347         const char string[ETH_GSTRING_LEN];
348 } ethtool_stats_keys[] = {
349         { "rx_octets" },
350         { "rx_fragments" },
351         { "rx_ucast_packets" },
352         { "rx_mcast_packets" },
353         { "rx_bcast_packets" },
354         { "rx_fcs_errors" },
355         { "rx_align_errors" },
356         { "rx_xon_pause_rcvd" },
357         { "rx_xoff_pause_rcvd" },
358         { "rx_mac_ctrl_rcvd" },
359         { "rx_xoff_entered" },
360         { "rx_frame_too_long_errors" },
361         { "rx_jabbers" },
362         { "rx_undersize_packets" },
363         { "rx_in_length_errors" },
364         { "rx_out_length_errors" },
365         { "rx_64_or_less_octet_packets" },
366         { "rx_65_to_127_octet_packets" },
367         { "rx_128_to_255_octet_packets" },
368         { "rx_256_to_511_octet_packets" },
369         { "rx_512_to_1023_octet_packets" },
370         { "rx_1024_to_1522_octet_packets" },
371         { "rx_1523_to_2047_octet_packets" },
372         { "rx_2048_to_4095_octet_packets" },
373         { "rx_4096_to_8191_octet_packets" },
374         { "rx_8192_to_9022_octet_packets" },
375
376         { "tx_octets" },
377         { "tx_collisions" },
378
379         { "tx_xon_sent" },
380         { "tx_xoff_sent" },
381         { "tx_flow_control" },
382         { "tx_mac_errors" },
383         { "tx_single_collisions" },
384         { "tx_mult_collisions" },
385         { "tx_deferred" },
386         { "tx_excessive_collisions" },
387         { "tx_late_collisions" },
388         { "tx_collide_2times" },
389         { "tx_collide_3times" },
390         { "tx_collide_4times" },
391         { "tx_collide_5times" },
392         { "tx_collide_6times" },
393         { "tx_collide_7times" },
394         { "tx_collide_8times" },
395         { "tx_collide_9times" },
396         { "tx_collide_10times" },
397         { "tx_collide_11times" },
398         { "tx_collide_12times" },
399         { "tx_collide_13times" },
400         { "tx_collide_14times" },
401         { "tx_collide_15times" },
402         { "tx_ucast_packets" },
403         { "tx_mcast_packets" },
404         { "tx_bcast_packets" },
405         { "tx_carrier_sense_errors" },
406         { "tx_discards" },
407         { "tx_errors" },
408
409         { "dma_writeq_full" },
410         { "dma_write_prioq_full" },
411         { "rxbds_empty" },
412         { "rx_discards" },
413         { "rx_errors" },
414         { "rx_threshold_hit" },
415
416         { "dma_readq_full" },
417         { "dma_read_prioq_full" },
418         { "tx_comp_queue_full" },
419
420         { "ring_set_send_prod_index" },
421         { "ring_status_update" },
422         { "nic_irqs" },
423         { "nic_avoided_irqs" },
424         { "nic_tx_threshold_hit" },
425
426         { "mbuf_lwm_thresh_hit" },
427 };
428
429 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
430 #define TG3_NVRAM_TEST          0
431 #define TG3_LINK_TEST           1
432 #define TG3_REGISTER_TEST       2
433 #define TG3_MEMORY_TEST         3
434 #define TG3_MAC_LOOPB_TEST      4
435 #define TG3_PHY_LOOPB_TEST      5
436 #define TG3_EXT_LOOPB_TEST      6
437 #define TG3_INTERRUPT_TEST      7
438
439
440 static const struct {
441         const char string[ETH_GSTRING_LEN];
442 } ethtool_test_keys[] = {
443         [TG3_NVRAM_TEST]        = { "nvram test        (online) " },
444         [TG3_LINK_TEST]         = { "link test         (online) " },
445         [TG3_REGISTER_TEST]     = { "register test     (offline)" },
446         [TG3_MEMORY_TEST]       = { "memory test       (offline)" },
447         [TG3_MAC_LOOPB_TEST]    = { "mac loopback test (offline)" },
448         [TG3_PHY_LOOPB_TEST]    = { "phy loopback test (offline)" },
449         [TG3_EXT_LOOPB_TEST]    = { "ext loopback test (offline)" },
450         [TG3_INTERRUPT_TEST]    = { "interrupt test    (offline)" },
451 };
452
453 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
454
455
456 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
457 {
458         writel(val, tp->regs + off);
459 }
460
461 static u32 tg3_read32(struct tg3 *tp, u32 off)
462 {
463         return readl(tp->regs + off);
464 }
465
466 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
467 {
468         writel(val, tp->aperegs + off);
469 }
470
471 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
472 {
473         return readl(tp->aperegs + off);
474 }
475
476 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
477 {
478         unsigned long flags;
479
480         spin_lock_irqsave(&tp->indirect_lock, flags);
481         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
482         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
483         spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 }
485
486 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
487 {
488         writel(val, tp->regs + off);
489         readl(tp->regs + off);
490 }
491
492 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
493 {
494         unsigned long flags;
495         u32 val;
496
497         spin_lock_irqsave(&tp->indirect_lock, flags);
498         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
499         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
500         spin_unlock_irqrestore(&tp->indirect_lock, flags);
501         return val;
502 }
503
504 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
505 {
506         unsigned long flags;
507
508         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
509                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
510                                        TG3_64BIT_REG_LOW, val);
511                 return;
512         }
513         if (off == TG3_RX_STD_PROD_IDX_REG) {
514                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
515                                        TG3_64BIT_REG_LOW, val);
516                 return;
517         }
518
519         spin_lock_irqsave(&tp->indirect_lock, flags);
520         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
521         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
522         spin_unlock_irqrestore(&tp->indirect_lock, flags);
523
524         /* In indirect mode when disabling interrupts, we also need
525          * to clear the interrupt bit in the GRC local ctrl register.
526          */
527         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
528             (val == 0x1)) {
529                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
530                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
531         }
532 }
533
534 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
535 {
536         unsigned long flags;
537         u32 val;
538
539         spin_lock_irqsave(&tp->indirect_lock, flags);
540         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
541         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
542         spin_unlock_irqrestore(&tp->indirect_lock, flags);
543         return val;
544 }
545
546 /* usec_wait specifies the wait time in usec when writing to certain registers
547  * where it is unsafe to read back the register without some delay.
548  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
549  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
550  */
551 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
552 {
553         if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
554                 /* Non-posted methods */
555                 tp->write32(tp, off, val);
556         else {
557                 /* Posted method */
558                 tg3_write32(tp, off, val);
559                 if (usec_wait)
560                         udelay(usec_wait);
561                 tp->read32(tp, off);
562         }
563         /* Wait again after the read for the posted method to guarantee that
564          * the wait time is met.
565          */
566         if (usec_wait)
567                 udelay(usec_wait);
568 }
569
570 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
571 {
572         tp->write32_mbox(tp, off, val);
573         if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
574                 tp->read32_mbox(tp, off);
575 }
576
577 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
578 {
579         void __iomem *mbox = tp->regs + off;
580         writel(val, mbox);
581         if (tg3_flag(tp, TXD_MBOX_HWBUG))
582                 writel(val, mbox);
583         if (tg3_flag(tp, MBOX_WRITE_REORDER))
584                 readl(mbox);
585 }
586
587 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
588 {
589         return readl(tp->regs + off + GRCMBOX_BASE);
590 }
591
592 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
593 {
594         writel(val, tp->regs + off + GRCMBOX_BASE);
595 }
596
597 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
598 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
599 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
600 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
601 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
602
603 #define tw32(reg, val)                  tp->write32(tp, reg, val)
604 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
605 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
606 #define tr32(reg)                       tp->read32(tp, reg)
607
608 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
609 {
610         unsigned long flags;
611
612         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
613             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
614                 return;
615
616         spin_lock_irqsave(&tp->indirect_lock, flags);
617         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
618                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
619                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
620
621                 /* Always leave this as zero. */
622                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
623         } else {
624                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
625                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
626
627                 /* Always leave this as zero. */
628                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
629         }
630         spin_unlock_irqrestore(&tp->indirect_lock, flags);
631 }
632
633 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
634 {
635         unsigned long flags;
636
637         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
638             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
639                 *val = 0;
640                 return;
641         }
642
643         spin_lock_irqsave(&tp->indirect_lock, flags);
644         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
645                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
646                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
647
648                 /* Always leave this as zero. */
649                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
650         } else {
651                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
652                 *val = tr32(TG3PCI_MEM_WIN_DATA);
653
654                 /* Always leave this as zero. */
655                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
656         }
657         spin_unlock_irqrestore(&tp->indirect_lock, flags);
658 }
659
660 static void tg3_ape_lock_init(struct tg3 *tp)
661 {
662         int i;
663         u32 regbase, bit;
664
665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
666                 regbase = TG3_APE_LOCK_GRANT;
667         else
668                 regbase = TG3_APE_PER_LOCK_GRANT;
669
670         /* Make sure the driver hasn't any stale locks. */
671         for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
672                 switch (i) {
673                 case TG3_APE_LOCK_PHY0:
674                 case TG3_APE_LOCK_PHY1:
675                 case TG3_APE_LOCK_PHY2:
676                 case TG3_APE_LOCK_PHY3:
677                         bit = APE_LOCK_GRANT_DRIVER;
678                         break;
679                 default:
680                         if (!tp->pci_fn)
681                                 bit = APE_LOCK_GRANT_DRIVER;
682                         else
683                                 bit = 1 << tp->pci_fn;
684                 }
685                 tg3_ape_write32(tp, regbase + 4 * i, bit);
686         }
687
688 }
689
690 static int tg3_ape_lock(struct tg3 *tp, int locknum)
691 {
692         int i, off;
693         int ret = 0;
694         u32 status, req, gnt, bit;
695
696         if (!tg3_flag(tp, ENABLE_APE))
697                 return 0;
698
699         switch (locknum) {
700         case TG3_APE_LOCK_GPIO:
701                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
702                         return 0;
703         case TG3_APE_LOCK_GRC:
704         case TG3_APE_LOCK_MEM:
705                 if (!tp->pci_fn)
706                         bit = APE_LOCK_REQ_DRIVER;
707                 else
708                         bit = 1 << tp->pci_fn;
709                 break;
710         case TG3_APE_LOCK_PHY0:
711         case TG3_APE_LOCK_PHY1:
712         case TG3_APE_LOCK_PHY2:
713         case TG3_APE_LOCK_PHY3:
714                 bit = APE_LOCK_REQ_DRIVER;
715                 break;
716         default:
717                 return -EINVAL;
718         }
719
720         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
721                 req = TG3_APE_LOCK_REQ;
722                 gnt = TG3_APE_LOCK_GRANT;
723         } else {
724                 req = TG3_APE_PER_LOCK_REQ;
725                 gnt = TG3_APE_PER_LOCK_GRANT;
726         }
727
728         off = 4 * locknum;
729
730         tg3_ape_write32(tp, req + off, bit);
731
732         /* Wait for up to 1 millisecond to acquire lock. */
733         for (i = 0; i < 100; i++) {
734                 status = tg3_ape_read32(tp, gnt + off);
735                 if (status == bit)
736                         break;
737                 udelay(10);
738         }
739
740         if (status != bit) {
741                 /* Revoke the lock request. */
742                 tg3_ape_write32(tp, gnt + off, bit);
743                 ret = -EBUSY;
744         }
745
746         return ret;
747 }
748
749 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
750 {
751         u32 gnt, bit;
752
753         if (!tg3_flag(tp, ENABLE_APE))
754                 return;
755
756         switch (locknum) {
757         case TG3_APE_LOCK_GPIO:
758                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
759                         return;
760         case TG3_APE_LOCK_GRC:
761         case TG3_APE_LOCK_MEM:
762                 if (!tp->pci_fn)
763                         bit = APE_LOCK_GRANT_DRIVER;
764                 else
765                         bit = 1 << tp->pci_fn;
766                 break;
767         case TG3_APE_LOCK_PHY0:
768         case TG3_APE_LOCK_PHY1:
769         case TG3_APE_LOCK_PHY2:
770         case TG3_APE_LOCK_PHY3:
771                 bit = APE_LOCK_GRANT_DRIVER;
772                 break;
773         default:
774                 return;
775         }
776
777         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
778                 gnt = TG3_APE_LOCK_GRANT;
779         else
780                 gnt = TG3_APE_PER_LOCK_GRANT;
781
782         tg3_ape_write32(tp, gnt + 4 * locknum, bit);
783 }
784
785 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
786 {
787         u32 apedata;
788
789         while (timeout_us) {
790                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
791                         return -EBUSY;
792
793                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
794                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
795                         break;
796
797                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
798
799                 udelay(10);
800                 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
801         }
802
803         return timeout_us ? 0 : -EBUSY;
804 }
805
806 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
807 {
808         u32 i, apedata;
809
810         for (i = 0; i < timeout_us / 10; i++) {
811                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
812
813                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
814                         break;
815
816                 udelay(10);
817         }
818
819         return i == timeout_us / 10;
820 }
821
822 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
823                                    u32 len)
824 {
825         int err;
826         u32 i, bufoff, msgoff, maxlen, apedata;
827
828         if (!tg3_flag(tp, APE_HAS_NCSI))
829                 return 0;
830
831         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
832         if (apedata != APE_SEG_SIG_MAGIC)
833                 return -ENODEV;
834
835         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
836         if (!(apedata & APE_FW_STATUS_READY))
837                 return -EAGAIN;
838
839         bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
840                  TG3_APE_SHMEM_BASE;
841         msgoff = bufoff + 2 * sizeof(u32);
842         maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
843
844         while (len) {
845                 u32 length;
846
847                 /* Cap xfer sizes to scratchpad limits. */
848                 length = (len > maxlen) ? maxlen : len;
849                 len -= length;
850
851                 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
852                 if (!(apedata & APE_FW_STATUS_READY))
853                         return -EAGAIN;
854
855                 /* Wait for up to 1 msec for APE to service previous event. */
856                 err = tg3_ape_event_lock(tp, 1000);
857                 if (err)
858                         return err;
859
860                 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
861                           APE_EVENT_STATUS_SCRTCHPD_READ |
862                           APE_EVENT_STATUS_EVENT_PENDING;
863                 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
864
865                 tg3_ape_write32(tp, bufoff, base_off);
866                 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
867
868                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
869                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
870
871                 base_off += length;
872
873                 if (tg3_ape_wait_for_event(tp, 30000))
874                         return -EAGAIN;
875
876                 for (i = 0; length; i += 4, length -= 4) {
877                         u32 val = tg3_ape_read32(tp, msgoff + i);
878                         memcpy(data, &val, sizeof(u32));
879                         data++;
880                 }
881         }
882
883         return 0;
884 }
885
886 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
887 {
888         int err;
889         u32 apedata;
890
891         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
892         if (apedata != APE_SEG_SIG_MAGIC)
893                 return -EAGAIN;
894
895         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
896         if (!(apedata & APE_FW_STATUS_READY))
897                 return -EAGAIN;
898
899         /* Wait for up to 1 millisecond for APE to service previous event. */
900         err = tg3_ape_event_lock(tp, 1000);
901         if (err)
902                 return err;
903
904         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
905                         event | APE_EVENT_STATUS_EVENT_PENDING);
906
907         tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
908         tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
909
910         return 0;
911 }
912
913 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
914 {
915         u32 event;
916         u32 apedata;
917
918         if (!tg3_flag(tp, ENABLE_APE))
919                 return;
920
921         switch (kind) {
922         case RESET_KIND_INIT:
923                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
924                                 APE_HOST_SEG_SIG_MAGIC);
925                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
926                                 APE_HOST_SEG_LEN_MAGIC);
927                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
928                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
929                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
930                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
931                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
932                                 APE_HOST_BEHAV_NO_PHYLOCK);
933                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
934                                     TG3_APE_HOST_DRVR_STATE_START);
935
936                 event = APE_EVENT_STATUS_STATE_START;
937                 break;
938         case RESET_KIND_SHUTDOWN:
939                 /* With the interface we are currently using,
940                  * APE does not track driver state.  Wiping
941                  * out the HOST SEGMENT SIGNATURE forces
942                  * the APE to assume OS absent status.
943                  */
944                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
945
946                 if (device_may_wakeup(&tp->pdev->dev) &&
947                     tg3_flag(tp, WOL_ENABLE)) {
948                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
949                                             TG3_APE_HOST_WOL_SPEED_AUTO);
950                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
951                 } else
952                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
953
954                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
955
956                 event = APE_EVENT_STATUS_STATE_UNLOAD;
957                 break;
958         case RESET_KIND_SUSPEND:
959                 event = APE_EVENT_STATUS_STATE_SUSPEND;
960                 break;
961         default:
962                 return;
963         }
964
965         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
966
967         tg3_ape_send_event(tp, event);
968 }
969
970 static void tg3_disable_ints(struct tg3 *tp)
971 {
972         int i;
973
974         tw32(TG3PCI_MISC_HOST_CTRL,
975              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
976         for (i = 0; i < tp->irq_max; i++)
977                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
978 }
979
980 static void tg3_enable_ints(struct tg3 *tp)
981 {
982         int i;
983
984         tp->irq_sync = 0;
985         wmb();
986
987         tw32(TG3PCI_MISC_HOST_CTRL,
988              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
989
990         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
991         for (i = 0; i < tp->irq_cnt; i++) {
992                 struct tg3_napi *tnapi = &tp->napi[i];
993
994                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
995                 if (tg3_flag(tp, 1SHOT_MSI))
996                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
997
998                 tp->coal_now |= tnapi->coal_now;
999         }
1000
1001         /* Force an initial interrupt */
1002         if (!tg3_flag(tp, TAGGED_STATUS) &&
1003             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1004                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1005         else
1006                 tw32(HOSTCC_MODE, tp->coal_now);
1007
1008         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1009 }
1010
1011 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1012 {
1013         struct tg3 *tp = tnapi->tp;
1014         struct tg3_hw_status *sblk = tnapi->hw_status;
1015         unsigned int work_exists = 0;
1016
1017         /* check for phy events */
1018         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1019                 if (sblk->status & SD_STATUS_LINK_CHG)
1020                         work_exists = 1;
1021         }
1022
1023         /* check for TX work to do */
1024         if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1025                 work_exists = 1;
1026
1027         /* check for RX work to do */
1028         if (tnapi->rx_rcb_prod_idx &&
1029             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1030                 work_exists = 1;
1031
1032         return work_exists;
1033 }
1034
1035 /* tg3_int_reenable
1036  *  similar to tg3_enable_ints, but it accurately determines whether there
1037  *  is new work pending and can return without flushing the PIO write
1038  *  which reenables interrupts
1039  */
1040 static void tg3_int_reenable(struct tg3_napi *tnapi)
1041 {
1042         struct tg3 *tp = tnapi->tp;
1043
1044         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1045         mmiowb();
1046
1047         /* When doing tagged status, this work check is unnecessary.
1048          * The last_tag we write above tells the chip which piece of
1049          * work we've completed.
1050          */
1051         if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1052                 tw32(HOSTCC_MODE, tp->coalesce_mode |
1053                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
1054 }
1055
1056 static void tg3_switch_clocks(struct tg3 *tp)
1057 {
1058         u32 clock_ctrl;
1059         u32 orig_clock_ctrl;
1060
1061         if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1062                 return;
1063
1064         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1065
1066         orig_clock_ctrl = clock_ctrl;
1067         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1068                        CLOCK_CTRL_CLKRUN_OENABLE |
1069                        0x1f);
1070         tp->pci_clock_ctrl = clock_ctrl;
1071
1072         if (tg3_flag(tp, 5705_PLUS)) {
1073                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1074                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1075                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1076                 }
1077         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1078                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1079                             clock_ctrl |
1080                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1081                             40);
1082                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1083                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
1084                             40);
1085         }
1086         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1087 }
1088
1089 #define PHY_BUSY_LOOPS  5000
1090
1091 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1092 {
1093         u32 frame_val;
1094         unsigned int loops;
1095         int ret;
1096
1097         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1098                 tw32_f(MAC_MI_MODE,
1099                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1100                 udelay(80);
1101         }
1102
1103         tg3_ape_lock(tp, tp->phy_ape_lock);
1104
1105         *val = 0x0;
1106
1107         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1108                       MI_COM_PHY_ADDR_MASK);
1109         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1110                       MI_COM_REG_ADDR_MASK);
1111         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1112
1113         tw32_f(MAC_MI_COM, frame_val);
1114
1115         loops = PHY_BUSY_LOOPS;
1116         while (loops != 0) {
1117                 udelay(10);
1118                 frame_val = tr32(MAC_MI_COM);
1119
1120                 if ((frame_val & MI_COM_BUSY) == 0) {
1121                         udelay(5);
1122                         frame_val = tr32(MAC_MI_COM);
1123                         break;
1124                 }
1125                 loops -= 1;
1126         }
1127
1128         ret = -EBUSY;
1129         if (loops != 0) {
1130                 *val = frame_val & MI_COM_DATA_MASK;
1131                 ret = 0;
1132         }
1133
1134         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1135                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1136                 udelay(80);
1137         }
1138
1139         tg3_ape_unlock(tp, tp->phy_ape_lock);
1140
1141         return ret;
1142 }
1143
1144 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1145 {
1146         u32 frame_val;
1147         unsigned int loops;
1148         int ret;
1149
1150         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1151             (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1152                 return 0;
1153
1154         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1155                 tw32_f(MAC_MI_MODE,
1156                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1157                 udelay(80);
1158         }
1159
1160         tg3_ape_lock(tp, tp->phy_ape_lock);
1161
1162         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1163                       MI_COM_PHY_ADDR_MASK);
1164         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1165                       MI_COM_REG_ADDR_MASK);
1166         frame_val |= (val & MI_COM_DATA_MASK);
1167         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1168
1169         tw32_f(MAC_MI_COM, frame_val);
1170
1171         loops = PHY_BUSY_LOOPS;
1172         while (loops != 0) {
1173                 udelay(10);
1174                 frame_val = tr32(MAC_MI_COM);
1175                 if ((frame_val & MI_COM_BUSY) == 0) {
1176                         udelay(5);
1177                         frame_val = tr32(MAC_MI_COM);
1178                         break;
1179                 }
1180                 loops -= 1;
1181         }
1182
1183         ret = -EBUSY;
1184         if (loops != 0)
1185                 ret = 0;
1186
1187         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1188                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1189                 udelay(80);
1190         }
1191
1192         tg3_ape_unlock(tp, tp->phy_ape_lock);
1193
1194         return ret;
1195 }
1196
1197 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1198 {
1199         int err;
1200
1201         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1206         if (err)
1207                 goto done;
1208
1209         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1210                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1211         if (err)
1212                 goto done;
1213
1214         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1215
1216 done:
1217         return err;
1218 }
1219
1220 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1221 {
1222         int err;
1223
1224         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1225         if (err)
1226                 goto done;
1227
1228         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1229         if (err)
1230                 goto done;
1231
1232         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1233                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1234         if (err)
1235                 goto done;
1236
1237         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1238
1239 done:
1240         return err;
1241 }
1242
1243 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1244 {
1245         int err;
1246
1247         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1248         if (!err)
1249                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1250
1251         return err;
1252 }
1253
1254 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1255 {
1256         int err;
1257
1258         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1259         if (!err)
1260                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1261
1262         return err;
1263 }
1264
1265 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1266 {
1267         int err;
1268
1269         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1270                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1271                            MII_TG3_AUXCTL_SHDWSEL_MISC);
1272         if (!err)
1273                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1274
1275         return err;
1276 }
1277
1278 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1279 {
1280         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1281                 set |= MII_TG3_AUXCTL_MISC_WREN;
1282
1283         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1284 }
1285
1286 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1287         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1288                              MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1289                              MII_TG3_AUXCTL_ACTL_TX_6DB)
1290
1291 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1292         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1293                              MII_TG3_AUXCTL_ACTL_TX_6DB);
1294
1295 static int tg3_bmcr_reset(struct tg3 *tp)
1296 {
1297         u32 phy_control;
1298         int limit, err;
1299
1300         /* OK, reset it, and poll the BMCR_RESET bit until it
1301          * clears or we time out.
1302          */
1303         phy_control = BMCR_RESET;
1304         err = tg3_writephy(tp, MII_BMCR, phy_control);
1305         if (err != 0)
1306                 return -EBUSY;
1307
1308         limit = 5000;
1309         while (limit--) {
1310                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1311                 if (err != 0)
1312                         return -EBUSY;
1313
1314                 if ((phy_control & BMCR_RESET) == 0) {
1315                         udelay(40);
1316                         break;
1317                 }
1318                 udelay(10);
1319         }
1320         if (limit < 0)
1321                 return -EBUSY;
1322
1323         return 0;
1324 }
1325
1326 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1327 {
1328         struct tg3 *tp = bp->priv;
1329         u32 val;
1330
1331         spin_lock_bh(&tp->lock);
1332
1333         if (tg3_readphy(tp, reg, &val))
1334                 val = -EIO;
1335
1336         spin_unlock_bh(&tp->lock);
1337
1338         return val;
1339 }
1340
1341 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1342 {
1343         struct tg3 *tp = bp->priv;
1344         u32 ret = 0;
1345
1346         spin_lock_bh(&tp->lock);
1347
1348         if (tg3_writephy(tp, reg, val))
1349                 ret = -EIO;
1350
1351         spin_unlock_bh(&tp->lock);
1352
1353         return ret;
1354 }
1355
1356 static int tg3_mdio_reset(struct mii_bus *bp)
1357 {
1358         return 0;
1359 }
1360
1361 static void tg3_mdio_config_5785(struct tg3 *tp)
1362 {
1363         u32 val;
1364         struct phy_device *phydev;
1365
1366         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1367         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1368         case PHY_ID_BCM50610:
1369         case PHY_ID_BCM50610M:
1370                 val = MAC_PHYCFG2_50610_LED_MODES;
1371                 break;
1372         case PHY_ID_BCMAC131:
1373                 val = MAC_PHYCFG2_AC131_LED_MODES;
1374                 break;
1375         case PHY_ID_RTL8211C:
1376                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1377                 break;
1378         case PHY_ID_RTL8201E:
1379                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1380                 break;
1381         default:
1382                 return;
1383         }
1384
1385         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1386                 tw32(MAC_PHYCFG2, val);
1387
1388                 val = tr32(MAC_PHYCFG1);
1389                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1390                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1391                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1392                 tw32(MAC_PHYCFG1, val);
1393
1394                 return;
1395         }
1396
1397         if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1398                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1399                        MAC_PHYCFG2_FMODE_MASK_MASK |
1400                        MAC_PHYCFG2_GMODE_MASK_MASK |
1401                        MAC_PHYCFG2_ACT_MASK_MASK   |
1402                        MAC_PHYCFG2_QUAL_MASK_MASK |
1403                        MAC_PHYCFG2_INBAND_ENABLE;
1404
1405         tw32(MAC_PHYCFG2, val);
1406
1407         val = tr32(MAC_PHYCFG1);
1408         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1409                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1410         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1411                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1412                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1413                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1414                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1415         }
1416         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1417                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1418         tw32(MAC_PHYCFG1, val);
1419
1420         val = tr32(MAC_EXT_RGMII_MODE);
1421         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1422                  MAC_RGMII_MODE_RX_QUALITY |
1423                  MAC_RGMII_MODE_RX_ACTIVITY |
1424                  MAC_RGMII_MODE_RX_ENG_DET |
1425                  MAC_RGMII_MODE_TX_ENABLE |
1426                  MAC_RGMII_MODE_TX_LOWPWR |
1427                  MAC_RGMII_MODE_TX_RESET);
1428         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1429                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1430                         val |= MAC_RGMII_MODE_RX_INT_B |
1431                                MAC_RGMII_MODE_RX_QUALITY |
1432                                MAC_RGMII_MODE_RX_ACTIVITY |
1433                                MAC_RGMII_MODE_RX_ENG_DET;
1434                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1435                         val |= MAC_RGMII_MODE_TX_ENABLE |
1436                                MAC_RGMII_MODE_TX_LOWPWR |
1437                                MAC_RGMII_MODE_TX_RESET;
1438         }
1439         tw32(MAC_EXT_RGMII_MODE, val);
1440 }
1441
1442 static void tg3_mdio_start(struct tg3 *tp)
1443 {
1444         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1445         tw32_f(MAC_MI_MODE, tp->mi_mode);
1446         udelay(80);
1447
1448         if (tg3_flag(tp, MDIOBUS_INITED) &&
1449             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1450                 tg3_mdio_config_5785(tp);
1451 }
1452
1453 static int tg3_mdio_init(struct tg3 *tp)
1454 {
1455         int i;
1456         u32 reg;
1457         struct phy_device *phydev;
1458
1459         if (tg3_flag(tp, 5717_PLUS)) {
1460                 u32 is_serdes;
1461
1462                 tp->phy_addr = tp->pci_fn + 1;
1463
1464                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1465                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1466                 else
1467                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1468                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1469                 if (is_serdes)
1470                         tp->phy_addr += 7;
1471         } else
1472                 tp->phy_addr = TG3_PHY_MII_ADDR;
1473
1474         tg3_mdio_start(tp);
1475
1476         if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1477                 return 0;
1478
1479         tp->mdio_bus = mdiobus_alloc();
1480         if (tp->mdio_bus == NULL)
1481                 return -ENOMEM;
1482
1483         tp->mdio_bus->name     = "tg3 mdio bus";
1484         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1485                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1486         tp->mdio_bus->priv     = tp;
1487         tp->mdio_bus->parent   = &tp->pdev->dev;
1488         tp->mdio_bus->read     = &tg3_mdio_read;
1489         tp->mdio_bus->write    = &tg3_mdio_write;
1490         tp->mdio_bus->reset    = &tg3_mdio_reset;
1491         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1492         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1493
1494         for (i = 0; i < PHY_MAX_ADDR; i++)
1495                 tp->mdio_bus->irq[i] = PHY_POLL;
1496
1497         /* The bus registration will look for all the PHYs on the mdio bus.
1498          * Unfortunately, it does not ensure the PHY is powered up before
1499          * accessing the PHY ID registers.  A chip reset is the
1500          * quickest way to bring the device back to an operational state..
1501          */
1502         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1503                 tg3_bmcr_reset(tp);
1504
1505         i = mdiobus_register(tp->mdio_bus);
1506         if (i) {
1507                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1508                 mdiobus_free(tp->mdio_bus);
1509                 return i;
1510         }
1511
1512         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1513
1514         if (!phydev || !phydev->drv) {
1515                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1516                 mdiobus_unregister(tp->mdio_bus);
1517                 mdiobus_free(tp->mdio_bus);
1518                 return -ENODEV;
1519         }
1520
1521         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1522         case PHY_ID_BCM57780:
1523                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1524                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1525                 break;
1526         case PHY_ID_BCM50610:
1527         case PHY_ID_BCM50610M:
1528                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1529                                      PHY_BRCM_RX_REFCLK_UNUSED |
1530                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1531                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1532                 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1533                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1534                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1535                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1536                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1537                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1538                 /* fallthru */
1539         case PHY_ID_RTL8211C:
1540                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1541                 break;
1542         case PHY_ID_RTL8201E:
1543         case PHY_ID_BCMAC131:
1544                 phydev->interface = PHY_INTERFACE_MODE_MII;
1545                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1546                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1547                 break;
1548         }
1549
1550         tg3_flag_set(tp, MDIOBUS_INITED);
1551
1552         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1553                 tg3_mdio_config_5785(tp);
1554
1555         return 0;
1556 }
1557
1558 static void tg3_mdio_fini(struct tg3 *tp)
1559 {
1560         if (tg3_flag(tp, MDIOBUS_INITED)) {
1561                 tg3_flag_clear(tp, MDIOBUS_INITED);
1562                 mdiobus_unregister(tp->mdio_bus);
1563                 mdiobus_free(tp->mdio_bus);
1564         }
1565 }
1566
1567 /* tp->lock is held. */
1568 static inline void tg3_generate_fw_event(struct tg3 *tp)
1569 {
1570         u32 val;
1571
1572         val = tr32(GRC_RX_CPU_EVENT);
1573         val |= GRC_RX_CPU_DRIVER_EVENT;
1574         tw32_f(GRC_RX_CPU_EVENT, val);
1575
1576         tp->last_event_jiffies = jiffies;
1577 }
1578
1579 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1580
1581 /* tp->lock is held. */
1582 static void tg3_wait_for_event_ack(struct tg3 *tp)
1583 {
1584         int i;
1585         unsigned int delay_cnt;
1586         long time_remain;
1587
1588         /* If enough time has passed, no wait is necessary. */
1589         time_remain = (long)(tp->last_event_jiffies + 1 +
1590                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1591                       (long)jiffies;
1592         if (time_remain < 0)
1593                 return;
1594
1595         /* Check if we can shorten the wait time. */
1596         delay_cnt = jiffies_to_usecs(time_remain);
1597         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1598                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1599         delay_cnt = (delay_cnt >> 3) + 1;
1600
1601         for (i = 0; i < delay_cnt; i++) {
1602                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1603                         break;
1604                 udelay(8);
1605         }
1606 }
1607
1608 /* tp->lock is held. */
1609 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1610 {
1611         u32 reg, val;
1612
1613         val = 0;
1614         if (!tg3_readphy(tp, MII_BMCR, &reg))
1615                 val = reg << 16;
1616         if (!tg3_readphy(tp, MII_BMSR, &reg))
1617                 val |= (reg & 0xffff);
1618         *data++ = val;
1619
1620         val = 0;
1621         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1622                 val = reg << 16;
1623         if (!tg3_readphy(tp, MII_LPA, &reg))
1624                 val |= (reg & 0xffff);
1625         *data++ = val;
1626
1627         val = 0;
1628         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1629                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1630                         val = reg << 16;
1631                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1632                         val |= (reg & 0xffff);
1633         }
1634         *data++ = val;
1635
1636         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1637                 val = reg << 16;
1638         else
1639                 val = 0;
1640         *data++ = val;
1641 }
1642
1643 /* tp->lock is held. */
1644 static void tg3_ump_link_report(struct tg3 *tp)
1645 {
1646         u32 data[4];
1647
1648         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1649                 return;
1650
1651         tg3_phy_gather_ump_data(tp, data);
1652
1653         tg3_wait_for_event_ack(tp);
1654
1655         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1656         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1657         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1658         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1659         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1660         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1661
1662         tg3_generate_fw_event(tp);
1663 }
1664
1665 /* tp->lock is held. */
1666 static void tg3_stop_fw(struct tg3 *tp)
1667 {
1668         if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1669                 /* Wait for RX cpu to ACK the previous event. */
1670                 tg3_wait_for_event_ack(tp);
1671
1672                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1673
1674                 tg3_generate_fw_event(tp);
1675
1676                 /* Wait for RX cpu to ACK this event. */
1677                 tg3_wait_for_event_ack(tp);
1678         }
1679 }
1680
1681 /* tp->lock is held. */
1682 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1683 {
1684         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1685                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1686
1687         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1688                 switch (kind) {
1689                 case RESET_KIND_INIT:
1690                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1691                                       DRV_STATE_START);
1692                         break;
1693
1694                 case RESET_KIND_SHUTDOWN:
1695                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1696                                       DRV_STATE_UNLOAD);
1697                         break;
1698
1699                 case RESET_KIND_SUSPEND:
1700                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1701                                       DRV_STATE_SUSPEND);
1702                         break;
1703
1704                 default:
1705                         break;
1706                 }
1707         }
1708
1709         if (kind == RESET_KIND_INIT ||
1710             kind == RESET_KIND_SUSPEND)
1711                 tg3_ape_driver_state_change(tp, kind);
1712 }
1713
1714 /* tp->lock is held. */
1715 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1716 {
1717         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1718                 switch (kind) {
1719                 case RESET_KIND_INIT:
1720                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1721                                       DRV_STATE_START_DONE);
1722                         break;
1723
1724                 case RESET_KIND_SHUTDOWN:
1725                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1726                                       DRV_STATE_UNLOAD_DONE);
1727                         break;
1728
1729                 default:
1730                         break;
1731                 }
1732         }
1733
1734         if (kind == RESET_KIND_SHUTDOWN)
1735                 tg3_ape_driver_state_change(tp, kind);
1736 }
1737
1738 /* tp->lock is held. */
1739 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1740 {
1741         if (tg3_flag(tp, ENABLE_ASF)) {
1742                 switch (kind) {
1743                 case RESET_KIND_INIT:
1744                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1745                                       DRV_STATE_START);
1746                         break;
1747
1748                 case RESET_KIND_SHUTDOWN:
1749                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1750                                       DRV_STATE_UNLOAD);
1751                         break;
1752
1753                 case RESET_KIND_SUSPEND:
1754                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1755                                       DRV_STATE_SUSPEND);
1756                         break;
1757
1758                 default:
1759                         break;
1760                 }
1761         }
1762 }
1763
1764 static int tg3_poll_fw(struct tg3 *tp)
1765 {
1766         int i;
1767         u32 val;
1768
1769         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1770                 /* Wait up to 20ms for init done. */
1771                 for (i = 0; i < 200; i++) {
1772                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1773                                 return 0;
1774                         udelay(100);
1775                 }
1776                 return -ENODEV;
1777         }
1778
1779         /* Wait for firmware initialization to complete. */
1780         for (i = 0; i < 100000; i++) {
1781                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1782                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1783                         break;
1784                 udelay(10);
1785         }
1786
1787         /* Chip might not be fitted with firmware.  Some Sun onboard
1788          * parts are configured like that.  So don't signal the timeout
1789          * of the above loop as an error, but do report the lack of
1790          * running firmware once.
1791          */
1792         if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1793                 tg3_flag_set(tp, NO_FWARE_REPORTED);
1794
1795                 netdev_info(tp->dev, "No firmware running\n");
1796         }
1797
1798         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1799                 /* The 57765 A0 needs a little more
1800                  * time to do some important work.
1801                  */
1802                 mdelay(10);
1803         }
1804
1805         return 0;
1806 }
1807
1808 static void tg3_link_report(struct tg3 *tp)
1809 {
1810         if (!netif_carrier_ok(tp->dev)) {
1811                 netif_info(tp, link, tp->dev, "Link is down\n");
1812                 tg3_ump_link_report(tp);
1813         } else if (netif_msg_link(tp)) {
1814                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1815                             (tp->link_config.active_speed == SPEED_1000 ?
1816                              1000 :
1817                              (tp->link_config.active_speed == SPEED_100 ?
1818                               100 : 10)),
1819                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1820                              "full" : "half"));
1821
1822                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1823                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1824                             "on" : "off",
1825                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1826                             "on" : "off");
1827
1828                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1829                         netdev_info(tp->dev, "EEE is %s\n",
1830                                     tp->setlpicnt ? "enabled" : "disabled");
1831
1832                 tg3_ump_link_report(tp);
1833         }
1834 }
1835
1836 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1837 {
1838         u16 miireg;
1839
1840         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1841                 miireg = ADVERTISE_1000XPAUSE;
1842         else if (flow_ctrl & FLOW_CTRL_TX)
1843                 miireg = ADVERTISE_1000XPSE_ASYM;
1844         else if (flow_ctrl & FLOW_CTRL_RX)
1845                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1846         else
1847                 miireg = 0;
1848
1849         return miireg;
1850 }
1851
1852 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1853 {
1854         u8 cap = 0;
1855
1856         if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1857                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1858         } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1859                 if (lcladv & ADVERTISE_1000XPAUSE)
1860                         cap = FLOW_CTRL_RX;
1861                 if (rmtadv & ADVERTISE_1000XPAUSE)
1862                         cap = FLOW_CTRL_TX;
1863         }
1864
1865         return cap;
1866 }
1867
1868 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1869 {
1870         u8 autoneg;
1871         u8 flowctrl = 0;
1872         u32 old_rx_mode = tp->rx_mode;
1873         u32 old_tx_mode = tp->tx_mode;
1874
1875         if (tg3_flag(tp, USE_PHYLIB))
1876                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1877         else
1878                 autoneg = tp->link_config.autoneg;
1879
1880         if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1881                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1882                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1883                 else
1884                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1885         } else
1886                 flowctrl = tp->link_config.flowctrl;
1887
1888         tp->link_config.active_flowctrl = flowctrl;
1889
1890         if (flowctrl & FLOW_CTRL_RX)
1891                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1892         else
1893                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1894
1895         if (old_rx_mode != tp->rx_mode)
1896                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1897
1898         if (flowctrl & FLOW_CTRL_TX)
1899                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1900         else
1901                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1902
1903         if (old_tx_mode != tp->tx_mode)
1904                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1905 }
1906
1907 static void tg3_adjust_link(struct net_device *dev)
1908 {
1909         u8 oldflowctrl, linkmesg = 0;
1910         u32 mac_mode, lcl_adv, rmt_adv;
1911         struct tg3 *tp = netdev_priv(dev);
1912         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1913
1914         spin_lock_bh(&tp->lock);
1915
1916         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1917                                     MAC_MODE_HALF_DUPLEX);
1918
1919         oldflowctrl = tp->link_config.active_flowctrl;
1920
1921         if (phydev->link) {
1922                 lcl_adv = 0;
1923                 rmt_adv = 0;
1924
1925                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1926                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1927                 else if (phydev->speed == SPEED_1000 ||
1928                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1929                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1930                 else
1931                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1932
1933                 if (phydev->duplex == DUPLEX_HALF)
1934                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1935                 else {
1936                         lcl_adv = mii_advertise_flowctrl(
1937                                   tp->link_config.flowctrl);
1938
1939                         if (phydev->pause)
1940                                 rmt_adv = LPA_PAUSE_CAP;
1941                         if (phydev->asym_pause)
1942                                 rmt_adv |= LPA_PAUSE_ASYM;
1943                 }
1944
1945                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1946         } else
1947                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1948
1949         if (mac_mode != tp->mac_mode) {
1950                 tp->mac_mode = mac_mode;
1951                 tw32_f(MAC_MODE, tp->mac_mode);
1952                 udelay(40);
1953         }
1954
1955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1956                 if (phydev->speed == SPEED_10)
1957                         tw32(MAC_MI_STAT,
1958                              MAC_MI_STAT_10MBPS_MODE |
1959                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1960                 else
1961                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1962         }
1963
1964         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1965                 tw32(MAC_TX_LENGTHS,
1966                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1967                       (6 << TX_LENGTHS_IPG_SHIFT) |
1968                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1969         else
1970                 tw32(MAC_TX_LENGTHS,
1971                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1972                       (6 << TX_LENGTHS_IPG_SHIFT) |
1973                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1974
1975         if (phydev->link != tp->old_link ||
1976             phydev->speed != tp->link_config.active_speed ||
1977             phydev->duplex != tp->link_config.active_duplex ||
1978             oldflowctrl != tp->link_config.active_flowctrl)
1979                 linkmesg = 1;
1980
1981         tp->old_link = phydev->link;
1982         tp->link_config.active_speed = phydev->speed;
1983         tp->link_config.active_duplex = phydev->duplex;
1984
1985         spin_unlock_bh(&tp->lock);
1986
1987         if (linkmesg)
1988                 tg3_link_report(tp);
1989 }
1990
1991 static int tg3_phy_init(struct tg3 *tp)
1992 {
1993         struct phy_device *phydev;
1994
1995         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1996                 return 0;
1997
1998         /* Bring the PHY back to a known state. */
1999         tg3_bmcr_reset(tp);
2000
2001         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2002
2003         /* Attach the MAC to the PHY. */
2004         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
2005                              phydev->dev_flags, phydev->interface);
2006         if (IS_ERR(phydev)) {
2007                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2008                 return PTR_ERR(phydev);
2009         }
2010
2011         /* Mask with MAC supported features. */
2012         switch (phydev->interface) {
2013         case PHY_INTERFACE_MODE_GMII:
2014         case PHY_INTERFACE_MODE_RGMII:
2015                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2016                         phydev->supported &= (PHY_GBIT_FEATURES |
2017                                               SUPPORTED_Pause |
2018                                               SUPPORTED_Asym_Pause);
2019                         break;
2020                 }
2021                 /* fallthru */
2022         case PHY_INTERFACE_MODE_MII:
2023                 phydev->supported &= (PHY_BASIC_FEATURES |
2024                                       SUPPORTED_Pause |
2025                                       SUPPORTED_Asym_Pause);
2026                 break;
2027         default:
2028                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2029                 return -EINVAL;
2030         }
2031
2032         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2033
2034         phydev->advertising = phydev->supported;
2035
2036         return 0;
2037 }
2038
2039 static void tg3_phy_start(struct tg3 *tp)
2040 {
2041         struct phy_device *phydev;
2042
2043         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2044                 return;
2045
2046         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2047
2048         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2049                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2050                 phydev->speed = tp->link_config.speed;
2051                 phydev->duplex = tp->link_config.duplex;
2052                 phydev->autoneg = tp->link_config.autoneg;
2053                 phydev->advertising = tp->link_config.advertising;
2054         }
2055
2056         phy_start(phydev);
2057
2058         phy_start_aneg(phydev);
2059 }
2060
2061 static void tg3_phy_stop(struct tg3 *tp)
2062 {
2063         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2064                 return;
2065
2066         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2067 }
2068
2069 static void tg3_phy_fini(struct tg3 *tp)
2070 {
2071         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2072                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2073                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2074         }
2075 }
2076
2077 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2078 {
2079         int err;
2080         u32 val;
2081
2082         if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2083                 return 0;
2084
2085         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2086                 /* Cannot do read-modify-write on 5401 */
2087                 err = tg3_phy_auxctl_write(tp,
2088                                            MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2089                                            MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2090                                            0x4c20);
2091                 goto done;
2092         }
2093
2094         err = tg3_phy_auxctl_read(tp,
2095                                   MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2096         if (err)
2097                 return err;
2098
2099         val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2100         err = tg3_phy_auxctl_write(tp,
2101                                    MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2102
2103 done:
2104         return err;
2105 }
2106
2107 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2108 {
2109         u32 phytest;
2110
2111         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2112                 u32 phy;
2113
2114                 tg3_writephy(tp, MII_TG3_FET_TEST,
2115                              phytest | MII_TG3_FET_SHADOW_EN);
2116                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2117                         if (enable)
2118                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2119                         else
2120                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2121                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2122                 }
2123                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2124         }
2125 }
2126
2127 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2128 {
2129         u32 reg;
2130
2131         if (!tg3_flag(tp, 5705_PLUS) ||
2132             (tg3_flag(tp, 5717_PLUS) &&
2133              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2134                 return;
2135
2136         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2137                 tg3_phy_fet_toggle_apd(tp, enable);
2138                 return;
2139         }
2140
2141         reg = MII_TG3_MISC_SHDW_WREN |
2142               MII_TG3_MISC_SHDW_SCR5_SEL |
2143               MII_TG3_MISC_SHDW_SCR5_LPED |
2144               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2145               MII_TG3_MISC_SHDW_SCR5_SDTL |
2146               MII_TG3_MISC_SHDW_SCR5_C125OE;
2147         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2148                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2149
2150         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2151
2152
2153         reg = MII_TG3_MISC_SHDW_WREN |
2154               MII_TG3_MISC_SHDW_APD_SEL |
2155               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2156         if (enable)
2157                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2158
2159         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2160 }
2161
2162 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2163 {
2164         u32 phy;
2165
2166         if (!tg3_flag(tp, 5705_PLUS) ||
2167             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2168                 return;
2169
2170         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2171                 u32 ephy;
2172
2173                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2174                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2175
2176                         tg3_writephy(tp, MII_TG3_FET_TEST,
2177                                      ephy | MII_TG3_FET_SHADOW_EN);
2178                         if (!tg3_readphy(tp, reg, &phy)) {
2179                                 if (enable)
2180                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2181                                 else
2182                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2183                                 tg3_writephy(tp, reg, phy);
2184                         }
2185                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2186                 }
2187         } else {
2188                 int ret;
2189
2190                 ret = tg3_phy_auxctl_read(tp,
2191                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2192                 if (!ret) {
2193                         if (enable)
2194                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2195                         else
2196                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2197                         tg3_phy_auxctl_write(tp,
2198                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2199                 }
2200         }
2201 }
2202
2203 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2204 {
2205         int ret;
2206         u32 val;
2207
2208         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2209                 return;
2210
2211         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2212         if (!ret)
2213                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2214                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2215 }
2216
2217 static void tg3_phy_apply_otp(struct tg3 *tp)
2218 {
2219         u32 otp, phy;
2220
2221         if (!tp->phy_otp)
2222                 return;
2223
2224         otp = tp->phy_otp;
2225
2226         if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2227                 return;
2228
2229         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2230         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2231         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2232
2233         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2234               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2235         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2236
2237         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2238         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2239         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2240
2241         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2242         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2243
2244         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2245         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2246
2247         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2248               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2249         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2250
2251         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2252 }
2253
2254 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2255 {
2256         u32 val;
2257
2258         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2259                 return;
2260
2261         tp->setlpicnt = 0;
2262
2263         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2264             current_link_up == 1 &&
2265             tp->link_config.active_duplex == DUPLEX_FULL &&
2266             (tp->link_config.active_speed == SPEED_100 ||
2267              tp->link_config.active_speed == SPEED_1000)) {
2268                 u32 eeectl;
2269
2270                 if (tp->link_config.active_speed == SPEED_1000)
2271                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2272                 else
2273                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2274
2275                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2276
2277                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2278                                   TG3_CL45_D7_EEERES_STAT, &val);
2279
2280                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2281                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2282                         tp->setlpicnt = 2;
2283         }
2284
2285         if (!tp->setlpicnt) {
2286                 if (current_link_up == 1 &&
2287                    !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2288                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2289                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2290                 }
2291
2292                 val = tr32(TG3_CPMU_EEE_MODE);
2293                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2294         }
2295 }
2296
2297 static void tg3_phy_eee_enable(struct tg3 *tp)
2298 {
2299         u32 val;
2300
2301         if (tp->link_config.active_speed == SPEED_1000 &&
2302             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2303              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2304              tg3_flag(tp, 57765_CLASS)) &&
2305             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2306                 val = MII_TG3_DSP_TAP26_ALNOKO |
2307                       MII_TG3_DSP_TAP26_RMRXSTO;
2308                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2309                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2310         }
2311
2312         val = tr32(TG3_CPMU_EEE_MODE);
2313         tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2314 }
2315
2316 static int tg3_wait_macro_done(struct tg3 *tp)
2317 {
2318         int limit = 100;
2319
2320         while (limit--) {
2321                 u32 tmp32;
2322
2323                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2324                         if ((tmp32 & 0x1000) == 0)
2325                                 break;
2326                 }
2327         }
2328         if (limit < 0)
2329                 return -EBUSY;
2330
2331         return 0;
2332 }
2333
2334 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2335 {
2336         static const u32 test_pat[4][6] = {
2337         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2338         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2339         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2340         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2341         };
2342         int chan;
2343
2344         for (chan = 0; chan < 4; chan++) {
2345                 int i;
2346
2347                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2348                              (chan * 0x2000) | 0x0200);
2349                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2350
2351                 for (i = 0; i < 6; i++)
2352                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2353                                      test_pat[chan][i]);
2354
2355                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2356                 if (tg3_wait_macro_done(tp)) {
2357                         *resetp = 1;
2358                         return -EBUSY;
2359                 }
2360
2361                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2362                              (chan * 0x2000) | 0x0200);
2363                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2364                 if (tg3_wait_macro_done(tp)) {
2365                         *resetp = 1;
2366                         return -EBUSY;
2367                 }
2368
2369                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2370                 if (tg3_wait_macro_done(tp)) {
2371                         *resetp = 1;
2372                         return -EBUSY;
2373                 }
2374
2375                 for (i = 0; i < 6; i += 2) {
2376                         u32 low, high;
2377
2378                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2379                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2380                             tg3_wait_macro_done(tp)) {
2381                                 *resetp = 1;
2382                                 return -EBUSY;
2383                         }
2384                         low &= 0x7fff;
2385                         high &= 0x000f;
2386                         if (low != test_pat[chan][i] ||
2387                             high != test_pat[chan][i+1]) {
2388                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2389                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2390                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2391
2392                                 return -EBUSY;
2393                         }
2394                 }
2395         }
2396
2397         return 0;
2398 }
2399
2400 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2401 {
2402         int chan;
2403
2404         for (chan = 0; chan < 4; chan++) {
2405                 int i;
2406
2407                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2408                              (chan * 0x2000) | 0x0200);
2409                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2410                 for (i = 0; i < 6; i++)
2411                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2412                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2413                 if (tg3_wait_macro_done(tp))
2414                         return -EBUSY;
2415         }
2416
2417         return 0;
2418 }
2419
2420 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2421 {
2422         u32 reg32, phy9_orig;
2423         int retries, do_phy_reset, err;
2424
2425         retries = 10;
2426         do_phy_reset = 1;
2427         do {
2428                 if (do_phy_reset) {
2429                         err = tg3_bmcr_reset(tp);
2430                         if (err)
2431                                 return err;
2432                         do_phy_reset = 0;
2433                 }
2434
2435                 /* Disable transmitter and interrupt.  */
2436                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2437                         continue;
2438
2439                 reg32 |= 0x3000;
2440                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2441
2442                 /* Set full-duplex, 1000 mbps.  */
2443                 tg3_writephy(tp, MII_BMCR,
2444                              BMCR_FULLDPLX | BMCR_SPEED1000);
2445
2446                 /* Set to master mode.  */
2447                 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2448                         continue;
2449
2450                 tg3_writephy(tp, MII_CTRL1000,
2451                              CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2452
2453                 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2454                 if (err)
2455                         return err;
2456
2457                 /* Block the PHY control access.  */
2458                 tg3_phydsp_write(tp, 0x8005, 0x0800);
2459
2460                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2461                 if (!err)
2462                         break;
2463         } while (--retries);
2464
2465         err = tg3_phy_reset_chanpat(tp);
2466         if (err)
2467                 return err;
2468
2469         tg3_phydsp_write(tp, 0x8005, 0x0000);
2470
2471         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2472         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2473
2474         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2475
2476         tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2477
2478         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2479                 reg32 &= ~0x3000;
2480                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2481         } else if (!err)
2482                 err = -EBUSY;
2483
2484         return err;
2485 }
2486
2487 static void tg3_carrier_on(struct tg3 *tp)
2488 {
2489         netif_carrier_on(tp->dev);
2490         tp->link_up = true;
2491 }
2492
2493 static void tg3_carrier_off(struct tg3 *tp)
2494 {
2495         netif_carrier_off(tp->dev);
2496         tp->link_up = false;
2497 }
2498
2499 /* This will reset the tigon3 PHY if there is no valid
2500  * link unless the FORCE argument is non-zero.
2501  */
2502 static int tg3_phy_reset(struct tg3 *tp)
2503 {
2504         u32 val, cpmuctrl;
2505         int err;
2506
2507         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2508                 val = tr32(GRC_MISC_CFG);
2509                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2510                 udelay(40);
2511         }
2512         err  = tg3_readphy(tp, MII_BMSR, &val);
2513         err |= tg3_readphy(tp, MII_BMSR, &val);
2514         if (err != 0)
2515                 return -EBUSY;
2516
2517         if (netif_running(tp->dev) && tp->link_up) {
2518                 tg3_carrier_off(tp);
2519                 tg3_link_report(tp);
2520         }
2521
2522         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2523             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2524             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2525                 err = tg3_phy_reset_5703_4_5(tp);
2526                 if (err)
2527                         return err;
2528                 goto out;
2529         }
2530
2531         cpmuctrl = 0;
2532         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2533             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2534                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2535                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2536                         tw32(TG3_CPMU_CTRL,
2537                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2538         }
2539
2540         err = tg3_bmcr_reset(tp);
2541         if (err)
2542                 return err;
2543
2544         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2545                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2546                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2547
2548                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2549         }
2550
2551         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2552             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2553                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2554                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2555                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2556                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2557                         udelay(40);
2558                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2559                 }
2560         }
2561
2562         if (tg3_flag(tp, 5717_PLUS) &&
2563             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2564                 return 0;
2565
2566         tg3_phy_apply_otp(tp);
2567
2568         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2569                 tg3_phy_toggle_apd(tp, true);
2570         else
2571                 tg3_phy_toggle_apd(tp, false);
2572
2573 out:
2574         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2575             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2576                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2577                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2578                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2579         }
2580
2581         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2582                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2583                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2584         }
2585
2586         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2587                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2588                         tg3_phydsp_write(tp, 0x000a, 0x310b);
2589                         tg3_phydsp_write(tp, 0x201f, 0x9506);
2590                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
2591                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2592                 }
2593         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2594                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2595                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2596                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2597                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2598                                 tg3_writephy(tp, MII_TG3_TEST1,
2599                                              MII_TG3_TEST1_TRIM_EN | 0x4);
2600                         } else
2601                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2602
2603                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2604                 }
2605         }
2606
2607         /* Set Extended packet length bit (bit 14) on all chips that */
2608         /* support jumbo frames */
2609         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2610                 /* Cannot do read-modify-write on 5401 */
2611                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2612         } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2613                 /* Set bit 14 with read-modify-write to preserve other bits */
2614                 err = tg3_phy_auxctl_read(tp,
2615                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2616                 if (!err)
2617                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2618                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2619         }
2620
2621         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2622          * jumbo frames transmission.
2623          */
2624         if (tg3_flag(tp, JUMBO_CAPABLE)) {
2625                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2626                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2627                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2628         }
2629
2630         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2631                 /* adjust output voltage */
2632                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2633         }
2634
2635         tg3_phy_toggle_automdix(tp, 1);
2636         tg3_phy_set_wirespeed(tp);
2637         return 0;
2638 }
2639
2640 #define TG3_GPIO_MSG_DRVR_PRES           0x00000001
2641 #define TG3_GPIO_MSG_NEED_VAUX           0x00000002
2642 #define TG3_GPIO_MSG_MASK                (TG3_GPIO_MSG_DRVR_PRES | \
2643                                           TG3_GPIO_MSG_NEED_VAUX)
2644 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2645         ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2646          (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2647          (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2648          (TG3_GPIO_MSG_DRVR_PRES << 12))
2649
2650 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2651         ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2652          (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2653          (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2654          (TG3_GPIO_MSG_NEED_VAUX << 12))
2655
2656 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2657 {
2658         u32 status, shift;
2659
2660         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2661             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2662                 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2663         else
2664                 status = tr32(TG3_CPMU_DRV_STATUS);
2665
2666         shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2667         status &= ~(TG3_GPIO_MSG_MASK << shift);
2668         status |= (newstat << shift);
2669
2670         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2671             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2672                 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2673         else
2674                 tw32(TG3_CPMU_DRV_STATUS, status);
2675
2676         return status >> TG3_APE_GPIO_MSG_SHIFT;
2677 }
2678
2679 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2680 {
2681         if (!tg3_flag(tp, IS_NIC))
2682                 return 0;
2683
2684         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2685             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2686             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2687                 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2688                         return -EIO;
2689
2690                 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2691
2692                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2693                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2694
2695                 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2696         } else {
2697                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2698                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2699         }
2700
2701         return 0;
2702 }
2703
2704 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2705 {
2706         u32 grc_local_ctrl;
2707
2708         if (!tg3_flag(tp, IS_NIC) ||
2709             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2710             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2711                 return;
2712
2713         grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2714
2715         tw32_wait_f(GRC_LOCAL_CTRL,
2716                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2717                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2718
2719         tw32_wait_f(GRC_LOCAL_CTRL,
2720                     grc_local_ctrl,
2721                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2722
2723         tw32_wait_f(GRC_LOCAL_CTRL,
2724                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2725                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2726 }
2727
2728 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2729 {
2730         if (!tg3_flag(tp, IS_NIC))
2731                 return;
2732
2733         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2734             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2735                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2736                             (GRC_LCLCTRL_GPIO_OE0 |
2737                              GRC_LCLCTRL_GPIO_OE1 |
2738                              GRC_LCLCTRL_GPIO_OE2 |
2739                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2740                              GRC_LCLCTRL_GPIO_OUTPUT1),
2741                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2742         } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2743                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2744                 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2745                 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2746                                      GRC_LCLCTRL_GPIO_OE1 |
2747                                      GRC_LCLCTRL_GPIO_OE2 |
2748                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2749                                      GRC_LCLCTRL_GPIO_OUTPUT1 |
2750                                      tp->grc_local_ctrl;
2751                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2752                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2753
2754                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2755                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2756                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2757
2758                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2759                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2760                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2761         } else {
2762                 u32 no_gpio2;
2763                 u32 grc_local_ctrl = 0;
2764
2765                 /* Workaround to prevent overdrawing Amps. */
2766                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2767                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2768                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2769                                     grc_local_ctrl,
2770                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2771                 }
2772
2773                 /* On 5753 and variants, GPIO2 cannot be used. */
2774                 no_gpio2 = tp->nic_sram_data_cfg &
2775                            NIC_SRAM_DATA_CFG_NO_GPIO2;
2776
2777                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2778                                   GRC_LCLCTRL_GPIO_OE1 |
2779                                   GRC_LCLCTRL_GPIO_OE2 |
2780                                   GRC_LCLCTRL_GPIO_OUTPUT1 |
2781                                   GRC_LCLCTRL_GPIO_OUTPUT2;
2782                 if (no_gpio2) {
2783                         grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2784                                             GRC_LCLCTRL_GPIO_OUTPUT2);
2785                 }
2786                 tw32_wait_f(GRC_LOCAL_CTRL,
2787                             tp->grc_local_ctrl | grc_local_ctrl,
2788                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2789
2790                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2791
2792                 tw32_wait_f(GRC_LOCAL_CTRL,
2793                             tp->grc_local_ctrl | grc_local_ctrl,
2794                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2795
2796                 if (!no_gpio2) {
2797                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2798                         tw32_wait_f(GRC_LOCAL_CTRL,
2799                                     tp->grc_local_ctrl | grc_local_ctrl,
2800                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2801                 }
2802         }
2803 }
2804
2805 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2806 {
2807         u32 msg = 0;
2808
2809         /* Serialize power state transitions */
2810         if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2811                 return;
2812
2813         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2814                 msg = TG3_GPIO_MSG_NEED_VAUX;
2815
2816         msg = tg3_set_function_status(tp, msg);
2817
2818         if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2819                 goto done;
2820
2821         if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2822                 tg3_pwrsrc_switch_to_vaux(tp);
2823         else
2824                 tg3_pwrsrc_die_with_vmain(tp);
2825
2826 done:
2827         tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2828 }
2829
2830 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2831 {
2832         bool need_vaux = false;
2833
2834         /* The GPIOs do something completely different on 57765. */
2835         if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2836                 return;
2837
2838         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2839             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2840             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2841                 tg3_frob_aux_power_5717(tp, include_wol ?
2842                                         tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2843                 return;
2844         }
2845
2846         if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2847                 struct net_device *dev_peer;
2848
2849                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2850
2851                 /* remove_one() may have been run on the peer. */
2852                 if (dev_peer) {
2853                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2854
2855                         if (tg3_flag(tp_peer, INIT_COMPLETE))
2856                                 return;
2857
2858                         if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2859                             tg3_flag(tp_peer, ENABLE_ASF))
2860                                 need_vaux = true;
2861                 }
2862         }
2863
2864         if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2865             tg3_flag(tp, ENABLE_ASF))
2866                 need_vaux = true;
2867
2868         if (need_vaux)
2869                 tg3_pwrsrc_switch_to_vaux(tp);
2870         else
2871                 tg3_pwrsrc_die_with_vmain(tp);
2872 }
2873
2874 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2875 {
2876         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2877                 return 1;
2878         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2879                 if (speed != SPEED_10)
2880                         return 1;
2881         } else if (speed == SPEED_10)
2882                 return 1;
2883
2884         return 0;
2885 }
2886
2887 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2888 {
2889         u32 val;
2890
2891         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2892                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2893                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2894                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2895
2896                         sg_dig_ctrl |=
2897                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2898                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2899                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2900                 }
2901                 return;
2902         }
2903
2904         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2905                 tg3_bmcr_reset(tp);
2906                 val = tr32(GRC_MISC_CFG);
2907                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2908                 udelay(40);
2909                 return;
2910         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2911                 u32 phytest;
2912                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2913                         u32 phy;
2914
2915                         tg3_writephy(tp, MII_ADVERTISE, 0);
2916                         tg3_writephy(tp, MII_BMCR,
2917                                      BMCR_ANENABLE | BMCR_ANRESTART);
2918
2919                         tg3_writephy(tp, MII_TG3_FET_TEST,
2920                                      phytest | MII_TG3_FET_SHADOW_EN);
2921                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2922                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2923                                 tg3_writephy(tp,
2924                                              MII_TG3_FET_SHDW_AUXMODE4,
2925                                              phy);
2926                         }
2927                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2928                 }
2929                 return;
2930         } else if (do_low_power) {
2931                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2932                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2933
2934                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2935                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2936                       MII_TG3_AUXCTL_PCTL_VREG_11V;
2937                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2938         }
2939
2940         /* The PHY should not be powered down on some chips because
2941          * of bugs.
2942          */
2943         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2944             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2945             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2946              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2947             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2948              !tp->pci_fn))
2949                 return;
2950
2951         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2952             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2953                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2954                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2955                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2956                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2957         }
2958
2959         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2960 }
2961
2962 /* tp->lock is held. */
2963 static int tg3_nvram_lock(struct tg3 *tp)
2964 {
2965         if (tg3_flag(tp, NVRAM)) {
2966                 int i;
2967
2968                 if (tp->nvram_lock_cnt == 0) {
2969                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2970                         for (i = 0; i < 8000; i++) {
2971                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2972                                         break;
2973                                 udelay(20);
2974                         }
2975                         if (i == 8000) {
2976                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2977                                 return -ENODEV;
2978                         }
2979                 }
2980                 tp->nvram_lock_cnt++;
2981         }
2982         return 0;
2983 }
2984
2985 /* tp->lock is held. */
2986 static void tg3_nvram_unlock(struct tg3 *tp)
2987 {
2988         if (tg3_flag(tp, NVRAM)) {
2989                 if (tp->nvram_lock_cnt > 0)
2990                         tp->nvram_lock_cnt--;
2991                 if (tp->nvram_lock_cnt == 0)
2992                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2993         }
2994 }
2995
2996 /* tp->lock is held. */
2997 static void tg3_enable_nvram_access(struct tg3 *tp)
2998 {
2999         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3000                 u32 nvaccess = tr32(NVRAM_ACCESS);
3001
3002                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3003         }
3004 }
3005
3006 /* tp->lock is held. */
3007 static void tg3_disable_nvram_access(struct tg3 *tp)
3008 {
3009         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3010                 u32 nvaccess = tr32(NVRAM_ACCESS);
3011
3012                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3013         }
3014 }
3015
3016 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3017                                         u32 offset, u32 *val)
3018 {
3019         u32 tmp;
3020         int i;
3021
3022         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3023                 return -EINVAL;
3024
3025         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3026                                         EEPROM_ADDR_DEVID_MASK |
3027                                         EEPROM_ADDR_READ);
3028         tw32(GRC_EEPROM_ADDR,
3029              tmp |
3030              (0 << EEPROM_ADDR_DEVID_SHIFT) |
3031              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3032               EEPROM_ADDR_ADDR_MASK) |
3033              EEPROM_ADDR_READ | EEPROM_ADDR_START);
3034
3035         for (i = 0; i < 1000; i++) {
3036                 tmp = tr32(GRC_EEPROM_ADDR);
3037
3038                 if (tmp & EEPROM_ADDR_COMPLETE)
3039                         break;
3040                 msleep(1);
3041         }
3042         if (!(tmp & EEPROM_ADDR_COMPLETE))
3043                 return -EBUSY;
3044
3045         tmp = tr32(GRC_EEPROM_DATA);
3046
3047         /*
3048          * The data will always be opposite the native endian
3049          * format.  Perform a blind byteswap to compensate.
3050          */
3051         *val = swab32(tmp);
3052
3053         return 0;
3054 }
3055
3056 #define NVRAM_CMD_TIMEOUT 10000
3057
3058 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3059 {
3060         int i;
3061
3062         tw32(NVRAM_CMD, nvram_cmd);
3063         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3064                 udelay(10);
3065                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3066                         udelay(10);
3067                         break;
3068                 }
3069         }
3070
3071         if (i == NVRAM_CMD_TIMEOUT)
3072                 return -EBUSY;
3073
3074         return 0;
3075 }
3076
3077 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3078 {
3079         if (tg3_flag(tp, NVRAM) &&
3080             tg3_flag(tp, NVRAM_BUFFERED) &&
3081             tg3_flag(tp, FLASH) &&
3082             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3083             (tp->nvram_jedecnum == JEDEC_ATMEL))
3084
3085                 addr = ((addr / tp->nvram_pagesize) <<
3086                         ATMEL_AT45DB0X1B_PAGE_POS) +
3087                        (addr % tp->nvram_pagesize);
3088
3089         return addr;
3090 }
3091
3092 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3093 {
3094         if (tg3_flag(tp, NVRAM) &&
3095             tg3_flag(tp, NVRAM_BUFFERED) &&
3096             tg3_flag(tp, FLASH) &&
3097             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3098             (tp->nvram_jedecnum == JEDEC_ATMEL))
3099
3100                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3101                         tp->nvram_pagesize) +
3102                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3103
3104         return addr;
3105 }
3106
3107 /* NOTE: Data read in from NVRAM is byteswapped according to
3108  * the byteswapping settings for all other register accesses.
3109  * tg3 devices are BE devices, so on a BE machine, the data
3110  * returned will be exactly as it is seen in NVRAM.  On a LE
3111  * machine, the 32-bit value will be byteswapped.
3112  */
3113 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3114 {
3115         int ret;
3116
3117         if (!tg3_flag(tp, NVRAM))
3118                 return tg3_nvram_read_using_eeprom(tp, offset, val);
3119
3120         offset = tg3_nvram_phys_addr(tp, offset);
3121
3122         if (offset > NVRAM_ADDR_MSK)
3123                 return -EINVAL;
3124
3125         ret = tg3_nvram_lock(tp);
3126         if (ret)
3127                 return ret;
3128
3129         tg3_enable_nvram_access(tp);
3130
3131         tw32(NVRAM_ADDR, offset);
3132         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3133                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3134
3135         if (ret == 0)
3136                 *val = tr32(NVRAM_RDDATA);
3137
3138         tg3_disable_nvram_access(tp);
3139
3140         tg3_nvram_unlock(tp);
3141
3142         return ret;
3143 }
3144
3145 /* Ensures NVRAM data is in bytestream format. */
3146 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3147 {
3148         u32 v;
3149         int res = tg3_nvram_read(tp, offset, &v);
3150         if (!res)
3151                 *val = cpu_to_be32(v);
3152         return res;
3153 }
3154
3155 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3156                                     u32 offset, u32 len, u8 *buf)
3157 {
3158         int i, j, rc = 0;
3159         u32 val;
3160
3161         for (i = 0; i < len; i += 4) {
3162                 u32 addr;
3163                 __be32 data;
3164
3165                 addr = offset + i;
3166
3167                 memcpy(&data, buf + i, 4);
3168
3169                 /*
3170                  * The SEEPROM interface expects the data to always be opposite
3171                  * the native endian format.  We accomplish this by reversing
3172                  * all the operations that would have been performed on the
3173                  * data from a call to tg3_nvram_read_be32().
3174                  */
3175                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3176
3177                 val = tr32(GRC_EEPROM_ADDR);
3178                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3179
3180                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3181                         EEPROM_ADDR_READ);
3182                 tw32(GRC_EEPROM_ADDR, val |
3183                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
3184                         (addr & EEPROM_ADDR_ADDR_MASK) |
3185                         EEPROM_ADDR_START |
3186                         EEPROM_ADDR_WRITE);
3187
3188                 for (j = 0; j < 1000; j++) {
3189                         val = tr32(GRC_EEPROM_ADDR);
3190
3191                         if (val & EEPROM_ADDR_COMPLETE)
3192                                 break;
3193                         msleep(1);
3194                 }
3195                 if (!(val & EEPROM_ADDR_COMPLETE)) {
3196                         rc = -EBUSY;
3197                         break;
3198                 }
3199         }
3200
3201         return rc;
3202 }
3203
3204 /* offset and length are dword aligned */
3205 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3206                 u8 *buf)
3207 {
3208         int ret = 0;
3209         u32 pagesize = tp->nvram_pagesize;
3210         u32 pagemask = pagesize - 1;
3211         u32 nvram_cmd;
3212         u8 *tmp;
3213
3214         tmp = kmalloc(pagesize, GFP_KERNEL);
3215         if (tmp == NULL)
3216                 return -ENOMEM;
3217
3218         while (len) {
3219                 int j;
3220                 u32 phy_addr, page_off, size;
3221
3222                 phy_addr = offset & ~pagemask;
3223
3224                 for (j = 0; j < pagesize; j += 4) {
3225                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
3226                                                   (__be32 *) (tmp + j));
3227                         if (ret)
3228                                 break;
3229                 }