drivers/net/ethernet/mellanox/mlx4/en_tx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <asm/page.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/vmalloc.h>
  41 #include <linux/tcp.h>
  42 #include <linux/moduleparam.h>
  43
  44 #include "mlx4_en.h"
  45
  46 enum {
  47         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
  48         MAX_BF = 256,
  49 };
  50
  51 static int inline_thold __read_mostly = MAX_INLINE;
  52
  53 module_param_named(inline_thold, inline_thold, int, 0444);
  54 MODULE_PARM_DESC(inline_thold, "threshold for using inline data");
  55
  56 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  57                            struct mlx4_en_tx_ring *ring, int qpn, u32 size,
  58                            u16 stride)
  59 {
  60         struct mlx4_en_dev *mdev = priv->mdev;
  61         int tmp;
  62         int err;
  63
  64         ring->size = size;
  65         ring->size_mask = size - 1;
  66         ring->stride = stride;
  67
  68         inline_thold = min(inline_thold, MAX_INLINE);
  69
  70         spin_lock_init(&ring->comp_lock);
  71
  72         tmp = size * sizeof(struct mlx4_en_tx_info);
  73         ring->tx_info = vmalloc(tmp);
  74         if (!ring->tx_info)
  75                 return -ENOMEM;
  76
  77         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  78                  ring->tx_info, tmp);
  79
  80         ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
  81         if (!ring->bounce_buf) {
  82                 err = -ENOMEM;
  83                 goto err_tx;
  84         }
  85         ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
  86
  87         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
  88                                  2 * PAGE_SIZE);
  89         if (err) {
  90                 en_err(priv, "Failed allocating hwq resources\n");
  91                 goto err_bounce;
  92         }
  93
  94         err = mlx4_en_map_buffer(&ring->wqres.buf);
  95         if (err) {
  96                 en_err(priv, "Failed to map TX buffer\n");
  97                 goto err_hwq_res;
  98         }
  99
 100         ring->buf = ring->wqres.buf.direct.buf;
 101
 102         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
 103                "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
 104                ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
 105
 106         ring->qpn = qpn;
 107         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
 108         if (err) {
 109                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 110                 goto err_map;
 111         }
 112         ring->qp.event = mlx4_en_sqp_event;
 113
 114         err = mlx4_bf_alloc(mdev->dev, &ring->bf);
 115         if (err) {
 116                 en_dbg(DRV, priv, "working without blueflame (%d)", err);
 117                 ring->bf.uar = &mdev->priv_uar;
 118                 ring->bf.uar->map = mdev->uar_map;
 119                 ring->bf_enabled = false;
 120         } else
 121                 ring->bf_enabled = true;
 122
 123         return 0;
 124
 125 err_map:
 126         mlx4_en_unmap_buffer(&ring->wqres.buf);
 127 err_hwq_res:
 128         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 129 err_bounce:
 130         kfree(ring->bounce_buf);
 131         ring->bounce_buf = NULL;
 132 err_tx:
 133         vfree(ring->tx_info);
 134         ring->tx_info = NULL;
 135         return err;
 136 }
 137
 138 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 139                              struct mlx4_en_tx_ring *ring)
 140 {
 141         struct mlx4_en_dev *mdev = priv->mdev;
 142         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 143
 144         if (ring->bf_enabled)
 145                 mlx4_bf_free(mdev->dev, &ring->bf);
 146         mlx4_qp_remove(mdev->dev, &ring->qp);
 147         mlx4_qp_free(mdev->dev, &ring->qp);
 148         mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
 149         mlx4_en_unmap_buffer(&ring->wqres.buf);
 150         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 151         kfree(ring->bounce_buf);
 152         ring->bounce_buf = NULL;
 153         vfree(ring->tx_info);
 154         ring->tx_info = NULL;
 155 }
 156
 157 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 158                              struct mlx4_en_tx_ring *ring,
 159                              int cq)
 160 {
 161         struct mlx4_en_dev *mdev = priv->mdev;
 162         int err;
 163
 164         ring->cqn = cq;
 165         ring->prod = 0;
 166         ring->cons = 0xffffffff;
 167         ring->last_nr_txbb = 1;
 168         ring->poll_cnt = 0;
 169         ring->blocked = 0;
 170         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 171         memset(ring->buf, 0, ring->buf_size);
 172
 173         ring->qp_state = MLX4_QP_STATE_RST;
 174         ring->doorbell_qpn = ring->qp.qpn << 8;
 175
 176         mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
 177                                 ring->cqn, &ring->context);
 178         if (ring->bf_enabled)
 179                 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
 180
 181         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
 182                                &ring->qp, &ring->qp_state);
 183
 184         return err;
 185 }
 186
 187 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 188                                 struct mlx4_en_tx_ring *ring)
 189 {
 190         struct mlx4_en_dev *mdev = priv->mdev;
 191
 192         mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
 193                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
 194 }
 195
 196
 197 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 198                                 struct mlx4_en_tx_ring *ring,
 199                                 int index, u8 owner)
 200 {
 201         struct mlx4_en_dev *mdev = priv->mdev;
 202         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 203         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 204         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 205         struct sk_buff *skb = tx_info->skb;
 206         struct skb_frag_struct *frag;
 207         void *end = ring->buf + ring->buf_size;
 208         int frags = skb_shinfo(skb)->nr_frags;
 209         int i;
 210         __be32 *ptr = (__be32 *)tx_desc;
 211         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 212
 213         /* Optimize the common case when there are no wraparounds */
 214         if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 215                 if (!tx_info->inl) {
 216                         if (tx_info->linear) {
 217                                 pci_unmap_single(mdev->pdev,
 218                                         (dma_addr_t) be64_to_cpu(data->addr),
 219                                          be32_to_cpu(data->byte_count),
 220                                          PCI_DMA_TODEVICE);
 221                                 ++data;
 222                         }
 223
 224                         for (i = 0; i < frags; i++) {
 225                                 frag = &skb_shinfo(skb)->frags[i];
 226                                 pci_unmap_page(mdev->pdev,
 227                                         (dma_addr_t) be64_to_cpu(data[i].addr),
 228                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
 229                         }
 230                 }
 231                 /* Stamp the freed descriptor */
 232                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
 233                         *ptr = stamp;
 234                         ptr += STAMP_DWORDS;
 235                 }
 236
 237         } else {
 238                 if (!tx_info->inl) {
 239                         if ((void *) data >= end) {
 240                                 data = ring->buf + ((void *)data - end);
 241                         }
 242
 243                         if (tx_info->linear) {
 244                                 pci_unmap_single(mdev->pdev,
 245                                         (dma_addr_t) be64_to_cpu(data->addr),
 246                                          be32_to_cpu(data->byte_count),
 247                                          PCI_DMA_TODEVICE);
 248                                 ++data;
 249                         }
 250
 251                         for (i = 0; i < frags; i++) {
 252                                 /* Check for wraparound before unmapping */
 253                                 if ((void *) data >= end)
 254                                         data = ring->buf;
 255                                 frag = &skb_shinfo(skb)->frags[i];
 256                                 pci_unmap_page(mdev->pdev,
 257                                         (dma_addr_t) be64_to_cpu(data->addr),
 258                                          skb_frag_size(frag), PCI_DMA_TODEVICE);
 259                                 ++data;
 260                         }
 261                 }
 262                 /* Stamp the freed descriptor */
 263                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
 264                         *ptr = stamp;
 265                         ptr += STAMP_DWORDS;
 266                         if ((void *) ptr >= end) {
 267                                 ptr = ring->buf;
 268                                 stamp ^= cpu_to_be32(0x80000000);
 269                         }
 270                 }
 271
 272         }
 273         dev_kfree_skb_any(skb);
 274         return tx_info->nr_txbb;
 275 }
 276
 277
 278 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 279 {
 280         struct mlx4_en_priv *priv = netdev_priv(dev);
 281         int cnt = 0;
 282
 283         /* Skip last polled descriptor */
 284         ring->cons += ring->last_nr_txbb;
 285         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 286                  ring->cons, ring->prod);
 287
 288         if ((u32) (ring->prod - ring->cons) > ring->size) {
 289                 if (netif_msg_tx_err(priv))
 290                         en_warn(priv, "Tx consumer passed producer!\n");
 291                 return 0;
 292         }
 293
 294         while (ring->cons != ring->prod) {
 295                 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
 296                                                 ring->cons & ring->size_mask,
 297                                                 !!(ring->cons & ring->size));
 298                 ring->cons += ring->last_nr_txbb;
 299                 cnt++;
 300         }
 301
 302         if (cnt)
 303                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 304
 305         return cnt;
 306 }
 307
 308 static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq)
 309 {
 310         struct mlx4_en_priv *priv = netdev_priv(dev);
 311         struct mlx4_cq *mcq = &cq->mcq;
 312         struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
 313         struct mlx4_cqe *cqe;
 314         u16 index;
 315         u16 new_index, ring_index;
 316         u32 txbbs_skipped = 0;
 317         u32 cons_index = mcq->cons_index;
 318         int size = cq->size;
 319         u32 size_mask = ring->size_mask;
 320         struct mlx4_cqe *buf = cq->buf;
 321
 322         if (!priv->port_up)
 323                 return;
 324
 325         index = cons_index & size_mask;
 326         cqe = &buf[index];
 327         ring_index = ring->cons & size_mask;
 328
 329         /* Process all completed CQEs */
 330         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 331                         cons_index & size)) {
 332                 /*
 333                  * make sure we read the CQE after we read the
 334                  * ownership bit
 335                  */
 336                 rmb();
 337
 338                 /* Skip over last polled CQE */
 339                 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 340
 341                 do {
 342                         txbbs_skipped += ring->last_nr_txbb;
 343                         ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
 344                         /* free next descriptor */
 345                         ring->last_nr_txbb = mlx4_en_free_tx_desc(
 346                                         priv, ring, ring_index,
 347                                         !!((ring->cons + txbbs_skipped) &
 348                                                         ring->size));
 349                 } while (ring_index != new_index);
 350
 351                 ++cons_index;
 352                 index = cons_index & size_mask;
 353                 cqe = &buf[index];
 354         }
 355
 356
 357         /*
 358          * To prevent CQ overflow we first update CQ consumer and only then
 359          * the ring consumer.
 360          */
 361         mcq->cons_index = cons_index;
 362         mlx4_cq_set_ci(mcq);
 363         wmb();
 364         ring->cons += txbbs_skipped;
 365
 366         /* Wakeup Tx queue if this ring stopped it */
 367         if (unlikely(ring->blocked)) {
 368                 if ((u32) (ring->prod - ring->cons) <=
 369                      ring->size - HEADROOM - MAX_DESC_TXBBS) {
 370                         ring->blocked = 0;
 371                         netif_tx_wake_queue(netdev_get_tx_queue(dev, cq->ring));
 372                         priv->port_stats.wake_queue++;
 373                 }
 374         }
 375 }
 376
 377 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 378 {
 379         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 380         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 381         struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
 382
 383         if (!spin_trylock(&ring->comp_lock))
 384                 return;
 385         mlx4_en_process_tx_cq(cq->dev, cq);
 386         mod_timer(&cq->timer, jiffies + 1);
 387         spin_unlock(&ring->comp_lock);
 388 }
 389
 390
 391 void mlx4_en_poll_tx_cq(unsigned long data)
 392 {
 393         struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
 394         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 395         struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
 396         u32 inflight;
 397
 398         INC_PERF_COUNTER(priv->pstats.tx_poll);
 399
 400         if (!spin_trylock_irq(&ring->comp_lock)) {
 401                 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
 402                 return;
 403         }
 404         mlx4_en_process_tx_cq(cq->dev, cq);
 405         inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
 406
 407         /* If there are still packets in flight and the timer has not already
 408          * been scheduled by the Tx routine then schedule it here to guarantee
 409          * completion processing of these packets */
 410         if (inflight && priv->port_up)
 411                 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
 412
 413         spin_unlock_irq(&ring->comp_lock);
 414 }
 415
 416 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 417                                                       struct mlx4_en_tx_ring *ring,
 418                                                       u32 index,
 419                                                       unsigned int desc_size)
 420 {
 421         u32 copy = (ring->size - index) * TXBB_SIZE;
 422         int i;
 423
 424         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 425                 if ((i & (TXBB_SIZE - 1)) == 0)
 426                         wmb();
 427
 428                 *((u32 *) (ring->buf + i)) =
 429                         *((u32 *) (ring->bounce_buf + copy + i));
 430         }
 431
 432         for (i = copy - 4; i >= 4 ; i -= 4) {
 433                 if ((i & (TXBB_SIZE - 1)) == 0)
 434                         wmb();
 435
 436                 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
 437                         *((u32 *) (ring->bounce_buf + i));
 438         }
 439
 440         /* Return real descriptor location */
 441         return ring->buf + index * TXBB_SIZE;
 442 }
 443
 444 static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
 445 {
 446         struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind];
 447         struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind];
 448         unsigned long flags;
 449
 450         /* If we don't have a pending timer, set one up to catch our recent
 451            post in case the interface becomes idle */
 452         if (!timer_pending(&cq->timer))
 453                 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
 454
 455         /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
 456         if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
 457                 if (spin_trylock_irqsave(&ring->comp_lock, flags)) {
 458                         mlx4_en_process_tx_cq(priv->dev, cq);
 459                         spin_unlock_irqrestore(&ring->comp_lock, flags);
 460                 }
 461 }
 462
 463 static int is_inline(struct sk_buff *skb, void **pfrag)
 464 {
 465         void *ptr;
 466
 467         if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) {
 468                 if (skb_shinfo(skb)->nr_frags == 1) {
 469                         ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]);
 470                         if (unlikely(!ptr))
 471                                 return 0;
 472
 473                         if (pfrag)
 474                                 *pfrag = ptr;
 475
 476                         return 1;
 477                 } else if (unlikely(skb_shinfo(skb)->nr_frags))
 478                         return 0;
 479                 else
 480                         return 1;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static int inline_size(struct sk_buff *skb)
 487 {
 488         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 489             <= MLX4_INLINE_ALIGN)
 490                 return ALIGN(skb->len + CTRL_SIZE +
 491                              sizeof(struct mlx4_wqe_inline_seg), 16);
 492         else
 493                 return ALIGN(skb->len + CTRL_SIZE + 2 *
 494                              sizeof(struct mlx4_wqe_inline_seg), 16);
 495 }
 496
 497 static int get_real_size(struct sk_buff *skb, struct net_device *dev,
 498                          int *lso_header_size)
 499 {
 500         struct mlx4_en_priv *priv = netdev_priv(dev);
 501         int real_size;
 502
 503         if (skb_is_gso(skb)) {
 504                 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
 505                 real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE +
 506                         ALIGN(*lso_header_size + 4, DS_SIZE);
 507                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
 508                         /* We add a segment for the skb linear buffer only if
 509                          * it contains data */
 510                         if (*lso_header_size < skb_headlen(skb))
 511                                 real_size += DS_SIZE;
 512                         else {
 513                                 if (netif_msg_tx_err(priv))
 514                                         en_warn(priv, "Non-linear headers\n");
 515                                 return 0;
 516                         }
 517                 }
 518         } else {
 519                 *lso_header_size = 0;
 520                 if (!is_inline(skb, NULL))
 521                         real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE;
 522                 else
 523                         real_size = inline_size(skb);
 524         }
 525
 526         return real_size;
 527 }
 528
 529 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb,
 530                              int real_size, u16 *vlan_tag, int tx_ind, void *fragptr)
 531 {
 532         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 533         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
 534
 535         if (skb->len <= spc) {
 536                 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 537                 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
 538                 if (skb_shinfo(skb)->nr_frags)
 539                         memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr,
 540                                skb_frag_size(&skb_shinfo(skb)->frags[0]));
 541
 542         } else {
 543                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
 544                 if (skb_headlen(skb) <= spc) {
 545                         skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
 546                         if (skb_headlen(skb) < spc) {
 547                                 memcpy(((void *)(inl + 1)) + skb_headlen(skb),
 548                                         fragptr, spc - skb_headlen(skb));
 549                                 fragptr +=  spc - skb_headlen(skb);
 550                         }
 551                         inl = (void *) (inl + 1) + spc;
 552                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
 553                 } else {
 554                         skb_copy_from_linear_data(skb, inl + 1, spc);
 555                         inl = (void *) (inl + 1) + spc;
 556                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
 557                                         skb_headlen(skb) - spc);
 558                         if (skb_shinfo(skb)->nr_frags)
 559                                 memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc,
 560                                         fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0]));
 561                 }
 562
 563                 wmb();
 564                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 565         }
 566         tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag);
 567         tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
 568                 (!!vlan_tx_tag_present(skb));
 569         tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
 570 }
 571
 572 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb)
 573 {
 574         struct mlx4_en_priv *priv = netdev_priv(dev);
 575         u16 vlan_tag = 0;
 576
 577         /* If we support per priority flow control and the packet contains
 578          * a vlan tag, send the packet to the TX ring assigned to that priority
 579          */
 580         if (priv->prof->rx_ppp && vlan_tx_tag_present(skb)) {
 581                 vlan_tag = vlan_tx_tag_get(skb);
 582                 return MLX4_EN_NUM_TX_RINGS + (vlan_tag >> 13);
 583         }
 584
 585         return skb_tx_hash(dev, skb);
 586 }
 587
 588 static void mlx4_bf_copy(unsigned long *dst, unsigned long *src, unsigned bytecnt)
 589 {
 590         __iowrite64_copy(dst, src, bytecnt / 8);
 591 }
 592
 593 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 594 {
 595         struct mlx4_en_priv *priv = netdev_priv(dev);
 596         struct mlx4_en_dev *mdev = priv->mdev;
 597         struct mlx4_en_tx_ring *ring;
 598         struct mlx4_en_cq *cq;
 599         struct mlx4_en_tx_desc *tx_desc;
 600         struct mlx4_wqe_data_seg *data;
 601         struct skb_frag_struct *frag;
 602         struct mlx4_en_tx_info *tx_info;
 603         struct ethhdr *ethh;
 604         int tx_ind = 0;
 605         int nr_txbb;
 606         int desc_size;
 607         int real_size;
 608         dma_addr_t dma;
 609         u32 index, bf_index;
 610         __be32 op_own;
 611         u16 vlan_tag = 0;
 612         int i;
 613         int lso_header_size;
 614         void *fragptr;
 615         bool bounce = false;
 616
 617         if (!priv->port_up)
 618                 goto tx_drop;
 619
 620         real_size = get_real_size(skb, dev, &lso_header_size);
 621         if (unlikely(!real_size))
 622                 goto tx_drop;
 623
 624         /* Align descriptor to TXBB size */
 625         desc_size = ALIGN(real_size, TXBB_SIZE);
 626         nr_txbb = desc_size / TXBB_SIZE;
 627         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
 628                 if (netif_msg_tx_err(priv))
 629                         en_warn(priv, "Oversized header or SG list\n");
 630                 goto tx_drop;
 631         }
 632
 633         tx_ind = skb->queue_mapping;
 634         ring = &priv->tx_ring[tx_ind];
 635         if (vlan_tx_tag_present(skb))
 636                 vlan_tag = vlan_tx_tag_get(skb);
 637
 638         /* Check available TXBBs And 2K spare for prefetch */
 639         if (unlikely(((int)(ring->prod - ring->cons)) >
 640                      ring->size - HEADROOM - MAX_DESC_TXBBS)) {
 641                 /* every full Tx ring stops queue */
 642                 netif_tx_stop_queue(netdev_get_tx_queue(dev, tx_ind));
 643                 ring->blocked = 1;
 644                 priv->port_stats.queue_stopped++;
 645
 646                 /* Use interrupts to find out when queue opened */
 647                 cq = &priv->tx_cq[tx_ind];
 648                 mlx4_en_arm_cq(priv, cq);
 649                 return NETDEV_TX_BUSY;
 650         }
 651
 652         /* Track current inflight packets for performance analysis */
 653         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
 654                          (u32) (ring->prod - ring->cons - 1));
 655
 656         /* Packet is good - grab an index and transmit it */
 657         index = ring->prod & ring->size_mask;
 658         bf_index = ring->prod;
 659
 660         /* See if we have enough space for whole descriptor TXBB for setting
 661          * SW ownership on next descriptor; if not, use a bounce buffer. */
 662         if (likely(index + nr_txbb <= ring->size))
 663                 tx_desc = ring->buf + index * TXBB_SIZE;
 664         else {
 665                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 666                 bounce = true;
 667         }
 668
 669         /* Save skb in tx_info ring */
 670         tx_info = &ring->tx_info[index];
 671         tx_info->skb = skb;
 672         tx_info->nr_txbb = nr_txbb;
 673
 674         /* Prepare ctrl segement apart opcode+ownership, which depends on
 675          * whether LSO is used */
 676         tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
 677         tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
 678                 !!vlan_tx_tag_present(skb);
 679         tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
 680         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 681         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 682                 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 683                                                          MLX4_WQE_CTRL_TCP_UDP_CSUM);
 684                 ring->tx_csum++;
 685         }
 686
 687         /* Copy dst mac address to wqe */
 688         ethh = (struct ethhdr *)skb->data;
 689         tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
 690         tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
 691         /* Handle LSO (TSO) packets */
 692         if (lso_header_size) {
 693                 /* Mark opcode as LSO */
 694                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
 695                         ((ring->prod & ring->size) ?
 696                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 697
 698                 /* Fill in the LSO prefix */
 699                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
 700                         skb_shinfo(skb)->gso_size << 16 | lso_header_size);
 701
 702                 /* Copy headers;
 703                  * note that we already verified that it is linear */
 704                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
 705                 data = ((void *) &tx_desc->lso +
 706                         ALIGN(lso_header_size + 4, DS_SIZE));
 707
 708                 priv->port_stats.tso_packets++;
 709                 i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) +
 710                         !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size);
 711                 ring->bytes += skb->len + (i - 1) * lso_header_size;
 712                 ring->packets += i;
 713         } else {
 714                 /* Normal (Non LSO) packet */
 715                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
 716                         ((ring->prod & ring->size) ?
 717                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 718                 data = &tx_desc->data;
 719                 ring->bytes += max(skb->len, (unsigned int) ETH_ZLEN);
 720                 ring->packets++;
 721
 722         }
 723         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
 724
 725
 726         /* valid only for none inline segments */
 727         tx_info->data_offset = (void *) data - (void *) tx_desc;
 728
 729         tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0;
 730         data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1;
 731
 732         if (!is_inline(skb, &fragptr)) {
 733                 /* Map fragments */
 734                 for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) {
 735                         frag = &skb_shinfo(skb)->frags[i];
 736                         dma = skb_frag_dma_map(&mdev->dev->pdev->dev, frag,
 737                                                0, skb_frag_size(frag),
 738                                                DMA_TO_DEVICE);
 739                         data->addr = cpu_to_be64(dma);
 740                         data->lkey = cpu_to_be32(mdev->mr.key);
 741                         wmb();
 742                         data->byte_count = cpu_to_be32(skb_frag_size(frag));
 743                         --data;
 744                 }
 745
 746                 /* Map linear part */
 747                 if (tx_info->linear) {
 748                         dma = pci_map_single(mdev->dev->pdev, skb->data + lso_header_size,
 749                                              skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE);
 750                         data->addr = cpu_to_be64(dma);
 751                         data->lkey = cpu_to_be32(mdev->mr.key);
 752                         wmb();
 753                         data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size);
 754                 }
 755                 tx_info->inl = 0;
 756         } else {
 757                 build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr);
 758                 tx_info->inl = 1;
 759         }
 760
 761         ring->prod += nr_txbb;
 762
 763         /* If we used a bounce buffer then copy descriptor back into place */
 764         if (bounce)
 765                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
 766
 767         /* Run destructor before passing skb to HW */
 768         if (likely(!skb_shared(skb)))
 769                 skb_orphan(skb);
 770
 771         if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tag) {
 772                 *(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
 773                 op_own |= htonl((bf_index & 0xffff) << 8);
 774                 /* Ensure new descirptor hits memory
 775                 * before setting ownership of this descriptor to HW */
 776                 wmb();
 777                 tx_desc->ctrl.owner_opcode = op_own;
 778
 779                 wmb();
 780
 781                 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl,
 782                      desc_size);
 783
 784                 wmb();
 785
 786                 ring->bf.offset ^= ring->bf.buf_size;
 787         } else {
 788                 /* Ensure new descirptor hits memory
 789                 * before setting ownership of this descriptor to HW */
 790                 wmb();
 791                 tx_desc->ctrl.owner_opcode = op_own;
 792                 wmb();
 793                 iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL);
 794         }
 795
 796         /* Poll CQ here */
 797         mlx4_en_xmit_poll(priv, tx_ind);
 798
 799         return NETDEV_TX_OK;
 800
 801 tx_drop:
 802         dev_kfree_skb_any(skb);
 803         priv->stats.tx_dropped++;
 804         return NETDEV_TX_OK;
 805 }
 806