r8169: fix vlan tag read ordering.
[~shefty/rdma-dev.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
38
39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8168G_1        "rtl_nic/rtl8168g-1.fw"
51
52 #ifdef RTL8169_DEBUG
53 #define assert(expr) \
54         if (!(expr)) {                                  \
55                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
56                 #expr,__FILE__,__func__,__LINE__);              \
57         }
58 #define dprintk(fmt, args...) \
59         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
60 #else
61 #define assert(expr) do {} while (0)
62 #define dprintk(fmt, args...)   do {} while (0)
63 #endif /* RTL8169_DEBUG */
64
65 #define R8169_MSG_DEFAULT \
66         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
67
68 #define TX_SLOTS_AVAIL(tp) \
69         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
73         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
74
75 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
77 static const int multicast_filter_limit = 32;
78
79 #define MAX_READ_REQUEST_SHIFT  12
80 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
81 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
82
83 #define R8169_REGS_SIZE         256
84 #define R8169_NAPI_WEIGHT       64
85 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
86 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
87 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
88 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
89
90 #define RTL8169_TX_TIMEOUT      (6*HZ)
91 #define RTL8169_PHY_TIMEOUT     (10*HZ)
92
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg)             readb (ioaddr + (reg))
98 #define RTL_R16(reg)            readw (ioaddr + (reg))
99 #define RTL_R32(reg)            readl (ioaddr + (reg))
100
101 enum mac_version {
102         RTL_GIGA_MAC_VER_01 = 0,
103         RTL_GIGA_MAC_VER_02,
104         RTL_GIGA_MAC_VER_03,
105         RTL_GIGA_MAC_VER_04,
106         RTL_GIGA_MAC_VER_05,
107         RTL_GIGA_MAC_VER_06,
108         RTL_GIGA_MAC_VER_07,
109         RTL_GIGA_MAC_VER_08,
110         RTL_GIGA_MAC_VER_09,
111         RTL_GIGA_MAC_VER_10,
112         RTL_GIGA_MAC_VER_11,
113         RTL_GIGA_MAC_VER_12,
114         RTL_GIGA_MAC_VER_13,
115         RTL_GIGA_MAC_VER_14,
116         RTL_GIGA_MAC_VER_15,
117         RTL_GIGA_MAC_VER_16,
118         RTL_GIGA_MAC_VER_17,
119         RTL_GIGA_MAC_VER_18,
120         RTL_GIGA_MAC_VER_19,
121         RTL_GIGA_MAC_VER_20,
122         RTL_GIGA_MAC_VER_21,
123         RTL_GIGA_MAC_VER_22,
124         RTL_GIGA_MAC_VER_23,
125         RTL_GIGA_MAC_VER_24,
126         RTL_GIGA_MAC_VER_25,
127         RTL_GIGA_MAC_VER_26,
128         RTL_GIGA_MAC_VER_27,
129         RTL_GIGA_MAC_VER_28,
130         RTL_GIGA_MAC_VER_29,
131         RTL_GIGA_MAC_VER_30,
132         RTL_GIGA_MAC_VER_31,
133         RTL_GIGA_MAC_VER_32,
134         RTL_GIGA_MAC_VER_33,
135         RTL_GIGA_MAC_VER_34,
136         RTL_GIGA_MAC_VER_35,
137         RTL_GIGA_MAC_VER_36,
138         RTL_GIGA_MAC_VER_37,
139         RTL_GIGA_MAC_VER_38,
140         RTL_GIGA_MAC_VER_39,
141         RTL_GIGA_MAC_VER_40,
142         RTL_GIGA_MAC_VER_41,
143         RTL_GIGA_MAC_NONE   = 0xff,
144 };
145
146 enum rtl_tx_desc_version {
147         RTL_TD_0        = 0,
148         RTL_TD_1        = 1,
149 };
150
151 #define JUMBO_1K        ETH_DATA_LEN
152 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
153 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
154 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
155 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
156
157 #define _R(NAME,TD,FW,SZ,B) {   \
158         .name = NAME,           \
159         .txd_version = TD,      \
160         .fw_name = FW,          \
161         .jumbo_max = SZ,        \
162         .jumbo_tx_csum = B      \
163 }
164
165 static const struct {
166         const char *name;
167         enum rtl_tx_desc_version txd_version;
168         const char *fw_name;
169         u16 jumbo_max;
170         bool jumbo_tx_csum;
171 } rtl_chip_infos[] = {
172         /* PCI devices. */
173         [RTL_GIGA_MAC_VER_01] =
174                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
175         [RTL_GIGA_MAC_VER_02] =
176                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
177         [RTL_GIGA_MAC_VER_03] =
178                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
179         [RTL_GIGA_MAC_VER_04] =
180                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
181         [RTL_GIGA_MAC_VER_05] =
182                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
183         [RTL_GIGA_MAC_VER_06] =
184                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
185         /* PCI-E devices. */
186         [RTL_GIGA_MAC_VER_07] =
187                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
188         [RTL_GIGA_MAC_VER_08] =
189                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
190         [RTL_GIGA_MAC_VER_09] =
191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
192         [RTL_GIGA_MAC_VER_10] =
193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
194         [RTL_GIGA_MAC_VER_11] =
195                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
196         [RTL_GIGA_MAC_VER_12] =
197                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
198         [RTL_GIGA_MAC_VER_13] =
199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
200         [RTL_GIGA_MAC_VER_14] =
201                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
202         [RTL_GIGA_MAC_VER_15] =
203                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
204         [RTL_GIGA_MAC_VER_16] =
205                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
206         [RTL_GIGA_MAC_VER_17] =
207                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
208         [RTL_GIGA_MAC_VER_18] =
209                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
210         [RTL_GIGA_MAC_VER_19] =
211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
212         [RTL_GIGA_MAC_VER_20] =
213                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
214         [RTL_GIGA_MAC_VER_21] =
215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
216         [RTL_GIGA_MAC_VER_22] =
217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
218         [RTL_GIGA_MAC_VER_23] =
219                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
220         [RTL_GIGA_MAC_VER_24] =
221                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
222         [RTL_GIGA_MAC_VER_25] =
223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
224                                                         JUMBO_9K, false),
225         [RTL_GIGA_MAC_VER_26] =
226                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
227                                                         JUMBO_9K, false),
228         [RTL_GIGA_MAC_VER_27] =
229                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
230         [RTL_GIGA_MAC_VER_28] =
231                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
232         [RTL_GIGA_MAC_VER_29] =
233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
234                                                         JUMBO_1K, true),
235         [RTL_GIGA_MAC_VER_30] =
236                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
237                                                         JUMBO_1K, true),
238         [RTL_GIGA_MAC_VER_31] =
239                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
240         [RTL_GIGA_MAC_VER_32] =
241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
242                                                         JUMBO_9K, false),
243         [RTL_GIGA_MAC_VER_33] =
244                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
245                                                         JUMBO_9K, false),
246         [RTL_GIGA_MAC_VER_34] =
247                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
248                                                         JUMBO_9K, false),
249         [RTL_GIGA_MAC_VER_35] =
250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
251                                                         JUMBO_9K, false),
252         [RTL_GIGA_MAC_VER_36] =
253                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
254                                                         JUMBO_9K, false),
255         [RTL_GIGA_MAC_VER_37] =
256                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
257                                                         JUMBO_1K, true),
258         [RTL_GIGA_MAC_VER_38] =
259                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
260                                                         JUMBO_9K, false),
261         [RTL_GIGA_MAC_VER_39] =
262                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
263                                                         JUMBO_1K, true),
264         [RTL_GIGA_MAC_VER_40] =
265                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_1,
266                                                         JUMBO_9K, false),
267         [RTL_GIGA_MAC_VER_41] =
268                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
269 };
270 #undef _R
271
272 enum cfg_version {
273         RTL_CFG_0 = 0x00,
274         RTL_CFG_1,
275         RTL_CFG_2
276 };
277
278 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
279         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
280         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
281         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
282         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
283         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
284         { PCI_VENDOR_ID_DLINK,                  0x4300,
285                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
286         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
287         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
288         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
289         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
290         { PCI_VENDOR_ID_LINKSYS,                0x1032,
291                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
292         { 0x0001,                               0x8168,
293                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
294         {0,},
295 };
296
297 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
298
299 static int rx_buf_sz = 16383;
300 static int use_dac;
301 static struct {
302         u32 msg_enable;
303 } debug = { -1 };
304
305 enum rtl_registers {
306         MAC0            = 0,    /* Ethernet hardware address. */
307         MAC4            = 4,
308         MAR0            = 8,    /* Multicast filter. */
309         CounterAddrLow          = 0x10,
310         CounterAddrHigh         = 0x14,
311         TxDescStartAddrLow      = 0x20,
312         TxDescStartAddrHigh     = 0x24,
313         TxHDescStartAddrLow     = 0x28,
314         TxHDescStartAddrHigh    = 0x2c,
315         FLASH           = 0x30,
316         ERSR            = 0x36,
317         ChipCmd         = 0x37,
318         TxPoll          = 0x38,
319         IntrMask        = 0x3c,
320         IntrStatus      = 0x3e,
321
322         TxConfig        = 0x40,
323 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
324 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
325
326         RxConfig        = 0x44,
327 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
328 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
329 #define RXCFG_FIFO_SHIFT                13
330                                         /* No threshold before first PCI xfer */
331 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
332 #define RXCFG_DMA_SHIFT                 8
333                                         /* Unlimited maximum PCI burst. */
334 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
335
336         RxMissed        = 0x4c,
337         Cfg9346         = 0x50,
338         Config0         = 0x51,
339         Config1         = 0x52,
340         Config2         = 0x53,
341 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
342
343         Config3         = 0x54,
344         Config4         = 0x55,
345         Config5         = 0x56,
346         MultiIntr       = 0x5c,
347         PHYAR           = 0x60,
348         PHYstatus       = 0x6c,
349         RxMaxSize       = 0xda,
350         CPlusCmd        = 0xe0,
351         IntrMitigate    = 0xe2,
352         RxDescAddrLow   = 0xe4,
353         RxDescAddrHigh  = 0xe8,
354         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
355
356 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
357
358         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
359
360 #define TxPacketMax     (8064 >> 7)
361 #define EarlySize       0x27
362
363         FuncEvent       = 0xf0,
364         FuncEventMask   = 0xf4,
365         FuncPresetState = 0xf8,
366         FuncForceEvent  = 0xfc,
367 };
368
369 enum rtl8110_registers {
370         TBICSR                  = 0x64,
371         TBI_ANAR                = 0x68,
372         TBI_LPAR                = 0x6a,
373 };
374
375 enum rtl8168_8101_registers {
376         CSIDR                   = 0x64,
377         CSIAR                   = 0x68,
378 #define CSIAR_FLAG                      0x80000000
379 #define CSIAR_WRITE_CMD                 0x80000000
380 #define CSIAR_BYTE_ENABLE               0x0f
381 #define CSIAR_BYTE_ENABLE_SHIFT         12
382 #define CSIAR_ADDR_MASK                 0x0fff
383 #define CSIAR_FUNC_CARD                 0x00000000
384 #define CSIAR_FUNC_SDIO                 0x00010000
385 #define CSIAR_FUNC_NIC                  0x00020000
386         PMCH                    = 0x6f,
387         EPHYAR                  = 0x80,
388 #define EPHYAR_FLAG                     0x80000000
389 #define EPHYAR_WRITE_CMD                0x80000000
390 #define EPHYAR_REG_MASK                 0x1f
391 #define EPHYAR_REG_SHIFT                16
392 #define EPHYAR_DATA_MASK                0xffff
393         DLLPR                   = 0xd0,
394 #define PFM_EN                          (1 << 6)
395         DBG_REG                 = 0xd1,
396 #define FIX_NAK_1                       (1 << 4)
397 #define FIX_NAK_2                       (1 << 3)
398         TWSI                    = 0xd2,
399         MCU                     = 0xd3,
400 #define NOW_IS_OOB                      (1 << 7)
401 #define TX_EMPTY                        (1 << 5)
402 #define RX_EMPTY                        (1 << 4)
403 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
404 #define EN_NDP                          (1 << 3)
405 #define EN_OOB_RESET                    (1 << 2)
406 #define LINK_LIST_RDY                   (1 << 1)
407         EFUSEAR                 = 0xdc,
408 #define EFUSEAR_FLAG                    0x80000000
409 #define EFUSEAR_WRITE_CMD               0x80000000
410 #define EFUSEAR_READ_CMD                0x00000000
411 #define EFUSEAR_REG_MASK                0x03ff
412 #define EFUSEAR_REG_SHIFT               8
413 #define EFUSEAR_DATA_MASK               0xff
414 };
415
416 enum rtl8168_registers {
417         LED_FREQ                = 0x1a,
418         EEE_LED                 = 0x1b,
419         ERIDR                   = 0x70,
420         ERIAR                   = 0x74,
421 #define ERIAR_FLAG                      0x80000000
422 #define ERIAR_WRITE_CMD                 0x80000000
423 #define ERIAR_READ_CMD                  0x00000000
424 #define ERIAR_ADDR_BYTE_ALIGN           4
425 #define ERIAR_TYPE_SHIFT                16
426 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
427 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
428 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
429 #define ERIAR_MASK_SHIFT                12
430 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
431 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
432 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
433 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
434         EPHY_RXER_NUM           = 0x7c,
435         OCPDR                   = 0xb0, /* OCP GPHY access */
436 #define OCPDR_WRITE_CMD                 0x80000000
437 #define OCPDR_READ_CMD                  0x00000000
438 #define OCPDR_REG_MASK                  0x7f
439 #define OCPDR_GPHY_REG_SHIFT            16
440 #define OCPDR_DATA_MASK                 0xffff
441         OCPAR                   = 0xb4,
442 #define OCPAR_FLAG                      0x80000000
443 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
444 #define OCPAR_GPHY_READ_CMD             0x0000f060
445         GPHY_OCP                = 0xb8,
446         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
447         MISC                    = 0xf0, /* 8168e only. */
448 #define TXPLA_RST                       (1 << 29)
449 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
450 #define PWM_EN                          (1 << 22)
451 #define RXDV_GATED_EN                   (1 << 19)
452 #define EARLY_TALLY_EN                  (1 << 16)
453 #define FORCE_CLK                       (1 << 15) /* force clock request */
454 };
455
456 enum rtl_register_content {
457         /* InterruptStatusBits */
458         SYSErr          = 0x8000,
459         PCSTimeout      = 0x4000,
460         SWInt           = 0x0100,
461         TxDescUnavail   = 0x0080,
462         RxFIFOOver      = 0x0040,
463         LinkChg         = 0x0020,
464         RxOverflow      = 0x0010,
465         TxErr           = 0x0008,
466         TxOK            = 0x0004,
467         RxErr           = 0x0002,
468         RxOK            = 0x0001,
469
470         /* RxStatusDesc */
471         RxBOVF  = (1 << 24),
472         RxFOVF  = (1 << 23),
473         RxRWT   = (1 << 22),
474         RxRES   = (1 << 21),
475         RxRUNT  = (1 << 20),
476         RxCRC   = (1 << 19),
477
478         /* ChipCmdBits */
479         StopReq         = 0x80,
480         CmdReset        = 0x10,
481         CmdRxEnb        = 0x08,
482         CmdTxEnb        = 0x04,
483         RxBufEmpty      = 0x01,
484
485         /* TXPoll register p.5 */
486         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
487         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
488         FSWInt          = 0x01,         /* Forced software interrupt */
489
490         /* Cfg9346Bits */
491         Cfg9346_Lock    = 0x00,
492         Cfg9346_Unlock  = 0xc0,
493
494         /* rx_mode_bits */
495         AcceptErr       = 0x20,
496         AcceptRunt      = 0x10,
497         AcceptBroadcast = 0x08,
498         AcceptMulticast = 0x04,
499         AcceptMyPhys    = 0x02,
500         AcceptAllPhys   = 0x01,
501 #define RX_CONFIG_ACCEPT_MASK           0x3f
502
503         /* TxConfigBits */
504         TxInterFrameGapShift = 24,
505         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
506
507         /* Config1 register p.24 */
508         LEDS1           = (1 << 7),
509         LEDS0           = (1 << 6),
510         Speed_down      = (1 << 4),
511         MEMMAP          = (1 << 3),
512         IOMAP           = (1 << 2),
513         VPD             = (1 << 1),
514         PMEnable        = (1 << 0),     /* Power Management Enable */
515
516         /* Config2 register p. 25 */
517         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
518         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
519         PCI_Clock_66MHz = 0x01,
520         PCI_Clock_33MHz = 0x00,
521
522         /* Config3 register p.25 */
523         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
524         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
525         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
526         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
527
528         /* Config4 register */
529         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
530
531         /* Config5 register p.27 */
532         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
533         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
534         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
535         Spi_en          = (1 << 3),
536         LanWake         = (1 << 1),     /* LanWake enable/disable */
537         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
538         ASPM_en         = (1 << 0),     /* ASPM enable */
539
540         /* TBICSR p.28 */
541         TBIReset        = 0x80000000,
542         TBILoopback     = 0x40000000,
543         TBINwEnable     = 0x20000000,
544         TBINwRestart    = 0x10000000,
545         TBILinkOk       = 0x02000000,
546         TBINwComplete   = 0x01000000,
547
548         /* CPlusCmd p.31 */
549         EnableBist      = (1 << 15),    // 8168 8101
550         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
551         Normal_mode     = (1 << 13),    // unused
552         Force_half_dup  = (1 << 12),    // 8168 8101
553         Force_rxflow_en = (1 << 11),    // 8168 8101
554         Force_txflow_en = (1 << 10),    // 8168 8101
555         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
556         ASF             = (1 << 8),     // 8168 8101
557         PktCntrDisable  = (1 << 7),     // 8168 8101
558         Mac_dbgo_sel    = 0x001c,       // 8168
559         RxVlan          = (1 << 6),
560         RxChkSum        = (1 << 5),
561         PCIDAC          = (1 << 4),
562         PCIMulRW        = (1 << 3),
563         INTT_0          = 0x0000,       // 8168
564         INTT_1          = 0x0001,       // 8168
565         INTT_2          = 0x0002,       // 8168
566         INTT_3          = 0x0003,       // 8168
567
568         /* rtl8169_PHYstatus */
569         TBI_Enable      = 0x80,
570         TxFlowCtrl      = 0x40,
571         RxFlowCtrl      = 0x20,
572         _1000bpsF       = 0x10,
573         _100bps         = 0x08,
574         _10bps          = 0x04,
575         LinkStatus      = 0x02,
576         FullDup         = 0x01,
577
578         /* _TBICSRBit */
579         TBILinkOK       = 0x02000000,
580
581         /* DumpCounterCommand */
582         CounterDump     = 0x8,
583 };
584
585 enum rtl_desc_bit {
586         /* First doubleword. */
587         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
588         RingEnd         = (1 << 30), /* End of descriptor ring */
589         FirstFrag       = (1 << 29), /* First segment of a packet */
590         LastFrag        = (1 << 28), /* Final segment of a packet */
591 };
592
593 /* Generic case. */
594 enum rtl_tx_desc_bit {
595         /* First doubleword. */
596         TD_LSO          = (1 << 27),            /* Large Send Offload */
597 #define TD_MSS_MAX                      0x07ffu /* MSS value */
598
599         /* Second doubleword. */
600         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
601 };
602
603 /* 8169, 8168b and 810x except 8102e. */
604 enum rtl_tx_desc_bit_0 {
605         /* First doubleword. */
606 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
607         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
608         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
609         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
610 };
611
612 /* 8102e, 8168c and beyond. */
613 enum rtl_tx_desc_bit_1 {
614         /* Second doubleword. */
615 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
616         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
617         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
618         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
619 };
620
621 static const struct rtl_tx_desc_info {
622         struct {
623                 u32 udp;
624                 u32 tcp;
625         } checksum;
626         u16 mss_shift;
627         u16 opts_offset;
628 } tx_desc_info [] = {
629         [RTL_TD_0] = {
630                 .checksum = {
631                         .udp    = TD0_IP_CS | TD0_UDP_CS,
632                         .tcp    = TD0_IP_CS | TD0_TCP_CS
633                 },
634                 .mss_shift      = TD0_MSS_SHIFT,
635                 .opts_offset    = 0
636         },
637         [RTL_TD_1] = {
638                 .checksum = {
639                         .udp    = TD1_IP_CS | TD1_UDP_CS,
640                         .tcp    = TD1_IP_CS | TD1_TCP_CS
641                 },
642                 .mss_shift      = TD1_MSS_SHIFT,
643                 .opts_offset    = 1
644         }
645 };
646
647 enum rtl_rx_desc_bit {
648         /* Rx private */
649         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
650         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
651
652 #define RxProtoUDP      (PID1)
653 #define RxProtoTCP      (PID0)
654 #define RxProtoIP       (PID1 | PID0)
655 #define RxProtoMask     RxProtoIP
656
657         IPFail          = (1 << 16), /* IP checksum failed */
658         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
659         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
660         RxVlanTag       = (1 << 16), /* VLAN tag available */
661 };
662
663 #define RsvdMask        0x3fffc000
664
665 struct TxDesc {
666         __le32 opts1;
667         __le32 opts2;
668         __le64 addr;
669 };
670
671 struct RxDesc {
672         __le32 opts1;
673         __le32 opts2;
674         __le64 addr;
675 };
676
677 struct ring_info {
678         struct sk_buff  *skb;
679         u32             len;
680         u8              __pad[sizeof(void *) - sizeof(u32)];
681 };
682
683 enum features {
684         RTL_FEATURE_WOL         = (1 << 0),
685         RTL_FEATURE_MSI         = (1 << 1),
686         RTL_FEATURE_GMII        = (1 << 2),
687         RTL_FEATURE_FW_LOADED   = (1 << 3),
688 };
689
690 struct rtl8169_counters {
691         __le64  tx_packets;
692         __le64  rx_packets;
693         __le64  tx_errors;
694         __le32  rx_errors;
695         __le16  rx_missed;
696         __le16  align_errors;
697         __le32  tx_one_collision;
698         __le32  tx_multi_collision;
699         __le64  rx_unicast;
700         __le64  rx_broadcast;
701         __le32  rx_multicast;
702         __le16  tx_aborted;
703         __le16  tx_underun;
704 };
705
706 enum rtl_flag {
707         RTL_FLAG_TASK_ENABLED,
708         RTL_FLAG_TASK_SLOW_PENDING,
709         RTL_FLAG_TASK_RESET_PENDING,
710         RTL_FLAG_TASK_PHY_PENDING,
711         RTL_FLAG_MAX
712 };
713
714 struct rtl8169_stats {
715         u64                     packets;
716         u64                     bytes;
717         struct u64_stats_sync   syncp;
718 };
719
720 struct rtl8169_private {
721         void __iomem *mmio_addr;        /* memory map physical address */
722         struct pci_dev *pci_dev;
723         struct net_device *dev;
724         struct napi_struct napi;
725         u32 msg_enable;
726         u16 txd_version;
727         u16 mac_version;
728         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
729         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
730         u32 dirty_rx;
731         u32 dirty_tx;
732         struct rtl8169_stats rx_stats;
733         struct rtl8169_stats tx_stats;
734         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
735         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
736         dma_addr_t TxPhyAddr;
737         dma_addr_t RxPhyAddr;
738         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
739         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
740         struct timer_list timer;
741         u16 cp_cmd;
742
743         u16 event_slow;
744
745         struct mdio_ops {
746                 void (*write)(struct rtl8169_private *, int, int);
747                 int (*read)(struct rtl8169_private *, int);
748         } mdio_ops;
749
750         struct pll_power_ops {
751                 void (*down)(struct rtl8169_private *);
752                 void (*up)(struct rtl8169_private *);
753         } pll_power_ops;
754
755         struct jumbo_ops {
756                 void (*enable)(struct rtl8169_private *);
757                 void (*disable)(struct rtl8169_private *);
758         } jumbo_ops;
759
760         struct csi_ops {
761                 void (*write)(struct rtl8169_private *, int, int);
762                 u32 (*read)(struct rtl8169_private *, int);
763         } csi_ops;
764
765         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
766         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
767         void (*phy_reset_enable)(struct rtl8169_private *tp);
768         void (*hw_start)(struct net_device *);
769         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
770         unsigned int (*link_ok)(void __iomem *);
771         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
772
773         struct {
774                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
775                 struct mutex mutex;
776                 struct work_struct work;
777         } wk;
778
779         unsigned features;
780
781         struct mii_if_info mii;
782         struct rtl8169_counters counters;
783         u32 saved_wolopts;
784         u32 opts1_mask;
785
786         struct rtl_fw {
787                 const struct firmware *fw;
788
789 #define RTL_VER_SIZE            32
790
791                 char version[RTL_VER_SIZE];
792
793                 struct rtl_fw_phy_action {
794                         __le32 *code;
795                         size_t size;
796                 } phy_action;
797         } *rtl_fw;
798 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
799
800         u32 ocp_base;
801 };
802
803 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
804 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
805 module_param(use_dac, int, 0);
806 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
807 module_param_named(debug, debug.msg_enable, int, 0);
808 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
809 MODULE_LICENSE("GPL");
810 MODULE_VERSION(RTL8169_VERSION);
811 MODULE_FIRMWARE(FIRMWARE_8168D_1);
812 MODULE_FIRMWARE(FIRMWARE_8168D_2);
813 MODULE_FIRMWARE(FIRMWARE_8168E_1);
814 MODULE_FIRMWARE(FIRMWARE_8168E_2);
815 MODULE_FIRMWARE(FIRMWARE_8168E_3);
816 MODULE_FIRMWARE(FIRMWARE_8105E_1);
817 MODULE_FIRMWARE(FIRMWARE_8168F_1);
818 MODULE_FIRMWARE(FIRMWARE_8168F_2);
819 MODULE_FIRMWARE(FIRMWARE_8402_1);
820 MODULE_FIRMWARE(FIRMWARE_8411_1);
821 MODULE_FIRMWARE(FIRMWARE_8106E_1);
822 MODULE_FIRMWARE(FIRMWARE_8168G_1);
823
824 static void rtl_lock_work(struct rtl8169_private *tp)
825 {
826         mutex_lock(&tp->wk.mutex);
827 }
828
829 static void rtl_unlock_work(struct rtl8169_private *tp)
830 {
831         mutex_unlock(&tp->wk.mutex);
832 }
833
834 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
835 {
836         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
837                                            PCI_EXP_DEVCTL_READRQ, force);
838 }
839
840 struct rtl_cond {
841         bool (*check)(struct rtl8169_private *);
842         const char *msg;
843 };
844
845 static void rtl_udelay(unsigned int d)
846 {
847         udelay(d);
848 }
849
850 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
851                           void (*delay)(unsigned int), unsigned int d, int n,
852                           bool high)
853 {
854         int i;
855
856         for (i = 0; i < n; i++) {
857                 delay(d);
858                 if (c->check(tp) == high)
859                         return true;
860         }
861         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
862                   c->msg, !high, n, d);
863         return false;
864 }
865
866 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
867                                       const struct rtl_cond *c,
868                                       unsigned int d, int n)
869 {
870         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
871 }
872
873 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
874                                      const struct rtl_cond *c,
875                                      unsigned int d, int n)
876 {
877         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
878 }
879
880 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
881                                       const struct rtl_cond *c,
882                                       unsigned int d, int n)
883 {
884         return rtl_loop_wait(tp, c, msleep, d, n, true);
885 }
886
887 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
888                                      const struct rtl_cond *c,
889                                      unsigned int d, int n)
890 {
891         return rtl_loop_wait(tp, c, msleep, d, n, false);
892 }
893
894 #define DECLARE_RTL_COND(name)                          \
895 static bool name ## _check(struct rtl8169_private *);   \
896                                                         \
897 static const struct rtl_cond name = {                   \
898         .check  = name ## _check,                       \
899         .msg    = #name                                 \
900 };                                                      \
901                                                         \
902 static bool name ## _check(struct rtl8169_private *tp)
903
904 DECLARE_RTL_COND(rtl_ocpar_cond)
905 {
906         void __iomem *ioaddr = tp->mmio_addr;
907
908         return RTL_R32(OCPAR) & OCPAR_FLAG;
909 }
910
911 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
912 {
913         void __iomem *ioaddr = tp->mmio_addr;
914
915         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
916
917         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
918                 RTL_R32(OCPDR) : ~0;
919 }
920
921 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
922 {
923         void __iomem *ioaddr = tp->mmio_addr;
924
925         RTL_W32(OCPDR, data);
926         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
927
928         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
929 }
930
931 DECLARE_RTL_COND(rtl_eriar_cond)
932 {
933         void __iomem *ioaddr = tp->mmio_addr;
934
935         return RTL_R32(ERIAR) & ERIAR_FLAG;
936 }
937
938 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
939 {
940         void __iomem *ioaddr = tp->mmio_addr;
941
942         RTL_W8(ERIDR, cmd);
943         RTL_W32(ERIAR, 0x800010e8);
944         msleep(2);
945
946         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
947                 return;
948
949         ocp_write(tp, 0x1, 0x30, 0x00000001);
950 }
951
952 #define OOB_CMD_RESET           0x00
953 #define OOB_CMD_DRIVER_START    0x05
954 #define OOB_CMD_DRIVER_STOP     0x06
955
956 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
957 {
958         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
959 }
960
961 DECLARE_RTL_COND(rtl_ocp_read_cond)
962 {
963         u16 reg;
964
965         reg = rtl8168_get_ocp_reg(tp);
966
967         return ocp_read(tp, 0x0f, reg) & 0x00000800;
968 }
969
970 static void rtl8168_driver_start(struct rtl8169_private *tp)
971 {
972         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
973
974         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
975 }
976
977 static void rtl8168_driver_stop(struct rtl8169_private *tp)
978 {
979         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
980
981         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
982 }
983
984 static int r8168dp_check_dash(struct rtl8169_private *tp)
985 {
986         u16 reg = rtl8168_get_ocp_reg(tp);
987
988         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
989 }
990
991 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
992 {
993         if (reg & 0xffff0001) {
994                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
995                 return true;
996         }
997         return false;
998 }
999
1000 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1001 {
1002         void __iomem *ioaddr = tp->mmio_addr;
1003
1004         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1005 }
1006
1007 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1008 {
1009         void __iomem *ioaddr = tp->mmio_addr;
1010
1011         if (rtl_ocp_reg_failure(tp, reg))
1012                 return;
1013
1014         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1015
1016         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1017 }
1018
1019 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1020 {
1021         void __iomem *ioaddr = tp->mmio_addr;
1022
1023         if (rtl_ocp_reg_failure(tp, reg))
1024                 return 0;
1025
1026         RTL_W32(GPHY_OCP, reg << 15);
1027
1028         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1029                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1030 }
1031
1032 static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1033 {
1034         int val;
1035
1036         val = r8168_phy_ocp_read(tp, reg);
1037         r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1038 }
1039
1040 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1041 {
1042         void __iomem *ioaddr = tp->mmio_addr;
1043
1044         if (rtl_ocp_reg_failure(tp, reg))
1045                 return;
1046
1047         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1048 }
1049
1050 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1051 {
1052         void __iomem *ioaddr = tp->mmio_addr;
1053
1054         if (rtl_ocp_reg_failure(tp, reg))
1055                 return 0;
1056
1057         RTL_W32(OCPDR, reg << 15);
1058
1059         return RTL_R32(OCPDR);
1060 }
1061
1062 #define OCP_STD_PHY_BASE        0xa400
1063
1064 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065 {
1066         if (reg == 0x1f) {
1067                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1068                 return;
1069         }
1070
1071         if (tp->ocp_base != OCP_STD_PHY_BASE)
1072                 reg -= 0x10;
1073
1074         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1075 }
1076
1077 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1078 {
1079         if (tp->ocp_base != OCP_STD_PHY_BASE)
1080                 reg -= 0x10;
1081
1082         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1083 }
1084
1085 DECLARE_RTL_COND(rtl_phyar_cond)
1086 {
1087         void __iomem *ioaddr = tp->mmio_addr;
1088
1089         return RTL_R32(PHYAR) & 0x80000000;
1090 }
1091
1092 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1093 {
1094         void __iomem *ioaddr = tp->mmio_addr;
1095
1096         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1097
1098         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1099         /*
1100          * According to hardware specs a 20us delay is required after write
1101          * complete indication, but before sending next command.
1102          */
1103         udelay(20);
1104 }
1105
1106 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1107 {
1108         void __iomem *ioaddr = tp->mmio_addr;
1109         int value;
1110
1111         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1112
1113         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1114                 RTL_R32(PHYAR) & 0xffff : ~0;
1115
1116         /*
1117          * According to hardware specs a 20us delay is required after read
1118          * complete indication, but before sending next command.
1119          */
1120         udelay(20);
1121
1122         return value;
1123 }
1124
1125 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1126 {
1127         void __iomem *ioaddr = tp->mmio_addr;
1128
1129         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1130         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1131         RTL_W32(EPHY_RXER_NUM, 0);
1132
1133         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1134 }
1135
1136 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1137 {
1138         r8168dp_1_mdio_access(tp, reg,
1139                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1140 }
1141
1142 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1143 {
1144         void __iomem *ioaddr = tp->mmio_addr;
1145
1146         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1147
1148         mdelay(1);
1149         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1150         RTL_W32(EPHY_RXER_NUM, 0);
1151
1152         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1153                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1154 }
1155
1156 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1157
1158 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1159 {
1160         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1161 }
1162
1163 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1164 {
1165         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1166 }
1167
1168 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1169 {
1170         void __iomem *ioaddr = tp->mmio_addr;
1171
1172         r8168dp_2_mdio_start(ioaddr);
1173
1174         r8169_mdio_write(tp, reg, value);
1175
1176         r8168dp_2_mdio_stop(ioaddr);
1177 }
1178
1179 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1180 {
1181         void __iomem *ioaddr = tp->mmio_addr;
1182         int value;
1183
1184         r8168dp_2_mdio_start(ioaddr);
1185
1186         value = r8169_mdio_read(tp, reg);
1187
1188         r8168dp_2_mdio_stop(ioaddr);
1189
1190         return value;
1191 }
1192
1193 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1194 {
1195         tp->mdio_ops.write(tp, location, val);
1196 }
1197
1198 static int rtl_readphy(struct rtl8169_private *tp, int location)
1199 {
1200         return tp->mdio_ops.read(tp, location);
1201 }
1202
1203 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1204 {
1205         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1206 }
1207
1208 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1209 {
1210         int val;
1211
1212         val = rtl_readphy(tp, reg_addr);
1213         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1214 }
1215
1216 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1217                            int val)
1218 {
1219         struct rtl8169_private *tp = netdev_priv(dev);
1220
1221         rtl_writephy(tp, location, val);
1222 }
1223
1224 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1225 {
1226         struct rtl8169_private *tp = netdev_priv(dev);
1227
1228         return rtl_readphy(tp, location);
1229 }
1230
1231 DECLARE_RTL_COND(rtl_ephyar_cond)
1232 {
1233         void __iomem *ioaddr = tp->mmio_addr;
1234
1235         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1236 }
1237
1238 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1239 {
1240         void __iomem *ioaddr = tp->mmio_addr;
1241
1242         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1243                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1244
1245         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1246
1247         udelay(10);
1248 }
1249
1250 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1251 {
1252         void __iomem *ioaddr = tp->mmio_addr;
1253
1254         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1255
1256         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1257                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1258 }
1259
1260 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1261                           u32 val, int type)
1262 {
1263         void __iomem *ioaddr = tp->mmio_addr;
1264
1265         BUG_ON((addr & 3) || (mask == 0));
1266         RTL_W32(ERIDR, val);
1267         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1268
1269         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1270 }
1271
1272 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1273 {
1274         void __iomem *ioaddr = tp->mmio_addr;
1275
1276         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1277
1278         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1279                 RTL_R32(ERIDR) : ~0;
1280 }
1281
1282 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1283                          u32 m, int type)
1284 {
1285         u32 val;
1286
1287         val = rtl_eri_read(tp, addr, type);
1288         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1289 }
1290
1291 struct exgmac_reg {
1292         u16 addr;
1293         u16 mask;
1294         u32 val;
1295 };
1296
1297 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1298                                    const struct exgmac_reg *r, int len)
1299 {
1300         while (len-- > 0) {
1301                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1302                 r++;
1303         }
1304 }
1305
1306 DECLARE_RTL_COND(rtl_efusear_cond)
1307 {
1308         void __iomem *ioaddr = tp->mmio_addr;
1309
1310         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1311 }
1312
1313 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1314 {
1315         void __iomem *ioaddr = tp->mmio_addr;
1316
1317         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1318
1319         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1320                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1321 }
1322
1323 static u16 rtl_get_events(struct rtl8169_private *tp)
1324 {
1325         void __iomem *ioaddr = tp->mmio_addr;
1326
1327         return RTL_R16(IntrStatus);
1328 }
1329
1330 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1331 {
1332         void __iomem *ioaddr = tp->mmio_addr;
1333
1334         RTL_W16(IntrStatus, bits);
1335         mmiowb();
1336 }
1337
1338 static void rtl_irq_disable(struct rtl8169_private *tp)
1339 {
1340         void __iomem *ioaddr = tp->mmio_addr;
1341
1342         RTL_W16(IntrMask, 0);
1343         mmiowb();
1344 }
1345
1346 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1347 {
1348         void __iomem *ioaddr = tp->mmio_addr;
1349
1350         RTL_W16(IntrMask, bits);
1351 }
1352
1353 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1354 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1355 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1356
1357 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1358 {
1359         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1360 }
1361
1362 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1363 {
1364         void __iomem *ioaddr = tp->mmio_addr;
1365
1366         rtl_irq_disable(tp);
1367         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1368         RTL_R8(ChipCmd);
1369 }
1370
1371 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1372 {
1373         void __iomem *ioaddr = tp->mmio_addr;
1374
1375         return RTL_R32(TBICSR) & TBIReset;
1376 }
1377
1378 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1379 {
1380         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1381 }
1382
1383 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1384 {
1385         return RTL_R32(TBICSR) & TBILinkOk;
1386 }
1387
1388 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1389 {
1390         return RTL_R8(PHYstatus) & LinkStatus;
1391 }
1392
1393 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1394 {
1395         void __iomem *ioaddr = tp->mmio_addr;
1396
1397         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1398 }
1399
1400 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1401 {
1402         unsigned int val;
1403
1404         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1405         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1406 }
1407
1408 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1409 {
1410         void __iomem *ioaddr = tp->mmio_addr;
1411         struct net_device *dev = tp->dev;
1412
1413         if (!netif_running(dev))
1414                 return;
1415
1416         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1417             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1418                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1419                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1420                                       ERIAR_EXGMAC);
1421                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1422                                       ERIAR_EXGMAC);
1423                 } else if (RTL_R8(PHYstatus) & _100bps) {
1424                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1425                                       ERIAR_EXGMAC);
1426                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1427                                       ERIAR_EXGMAC);
1428                 } else {
1429                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1430                                       ERIAR_EXGMAC);
1431                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1432                                       ERIAR_EXGMAC);
1433                 }
1434                 /* Reset packet filter */
1435                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1436                              ERIAR_EXGMAC);
1437                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1438                              ERIAR_EXGMAC);
1439         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1440                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1441                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1442                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1443                                       ERIAR_EXGMAC);
1444                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1445                                       ERIAR_EXGMAC);
1446                 } else {
1447                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1448                                       ERIAR_EXGMAC);
1449                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1450                                       ERIAR_EXGMAC);
1451                 }
1452         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1453                 if (RTL_R8(PHYstatus) & _10bps) {
1454                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1455                                       ERIAR_EXGMAC);
1456                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1457                                       ERIAR_EXGMAC);
1458                 } else {
1459                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1460                                       ERIAR_EXGMAC);
1461                 }
1462         }
1463 }
1464
1465 static void __rtl8169_check_link_status(struct net_device *dev,
1466                                         struct rtl8169_private *tp,
1467                                         void __iomem *ioaddr, bool pm)
1468 {
1469         if (tp->link_ok(ioaddr)) {
1470                 rtl_link_chg_patch(tp);
1471                 /* This is to cancel a scheduled suspend if there's one. */
1472                 if (pm)
1473                         pm_request_resume(&tp->pci_dev->dev);
1474                 netif_carrier_on(dev);
1475                 if (net_ratelimit())
1476                         netif_info(tp, ifup, dev, "link up\n");
1477         } else {
1478                 netif_carrier_off(dev);
1479                 netif_info(tp, ifdown, dev, "link down\n");
1480                 if (pm)
1481                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1482         }
1483 }
1484
1485 static void rtl8169_check_link_status(struct net_device *dev,
1486                                       struct rtl8169_private *tp,
1487                                       void __iomem *ioaddr)
1488 {
1489         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1490 }
1491
1492 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1493
1494 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1495 {
1496         void __iomem *ioaddr = tp->mmio_addr;
1497         u8 options;
1498         u32 wolopts = 0;
1499
1500         options = RTL_R8(Config1);
1501         if (!(options & PMEnable))
1502                 return 0;
1503
1504         options = RTL_R8(Config3);
1505         if (options & LinkUp)
1506                 wolopts |= WAKE_PHY;
1507         if (options & MagicPacket)
1508                 wolopts |= WAKE_MAGIC;
1509
1510         options = RTL_R8(Config5);
1511         if (options & UWF)
1512                 wolopts |= WAKE_UCAST;
1513         if (options & BWF)
1514                 wolopts |= WAKE_BCAST;
1515         if (options & MWF)
1516                 wolopts |= WAKE_MCAST;
1517
1518         return wolopts;
1519 }
1520
1521 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1522 {
1523         struct rtl8169_private *tp = netdev_priv(dev);
1524
1525         rtl_lock_work(tp);
1526
1527         wol->supported = WAKE_ANY;
1528         wol->wolopts = __rtl8169_get_wol(tp);
1529
1530         rtl_unlock_work(tp);
1531 }
1532
1533 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1534 {
1535         void __iomem *ioaddr = tp->mmio_addr;
1536         unsigned int i;
1537         static const struct {
1538                 u32 opt;
1539                 u16 reg;
1540                 u8  mask;
1541         } cfg[] = {
1542                 { WAKE_PHY,   Config3, LinkUp },
1543                 { WAKE_MAGIC, Config3, MagicPacket },
1544                 { WAKE_UCAST, Config5, UWF },
1545                 { WAKE_BCAST, Config5, BWF },
1546                 { WAKE_MCAST, Config5, MWF },
1547                 { WAKE_ANY,   Config5, LanWake }
1548         };
1549         u8 options;
1550
1551         RTL_W8(Cfg9346, Cfg9346_Unlock);
1552
1553         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1554                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1555                 if (wolopts & cfg[i].opt)
1556                         options |= cfg[i].mask;
1557                 RTL_W8(cfg[i].reg, options);
1558         }
1559
1560         switch (tp->mac_version) {
1561         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1562                 options = RTL_R8(Config1) & ~PMEnable;
1563                 if (wolopts)
1564                         options |= PMEnable;
1565                 RTL_W8(Config1, options);
1566                 break;
1567         default:
1568                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1569                 if (wolopts)
1570                         options |= PME_SIGNAL;
1571                 RTL_W8(Config2, options);
1572                 break;
1573         }
1574
1575         RTL_W8(Cfg9346, Cfg9346_Lock);
1576 }
1577
1578 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1579 {
1580         struct rtl8169_private *tp = netdev_priv(dev);
1581
1582         rtl_lock_work(tp);
1583
1584         if (wol->wolopts)
1585                 tp->features |= RTL_FEATURE_WOL;
1586         else
1587                 tp->features &= ~RTL_FEATURE_WOL;
1588         __rtl8169_set_wol(tp, wol->wolopts);
1589
1590         rtl_unlock_work(tp);
1591
1592         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1593
1594         return 0;
1595 }
1596
1597 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1598 {
1599         return rtl_chip_infos[tp->mac_version].fw_name;
1600 }
1601
1602 static void rtl8169_get_drvinfo(struct net_device *dev,
1603                                 struct ethtool_drvinfo *info)
1604 {
1605         struct rtl8169_private *tp = netdev_priv(dev);
1606         struct rtl_fw *rtl_fw = tp->rtl_fw;
1607
1608         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1609         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1610         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1611         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1612         if (!IS_ERR_OR_NULL(rtl_fw))
1613                 strlcpy(info->fw_version, rtl_fw->version,
1614                         sizeof(info->fw_version));
1615 }
1616
1617 static int rtl8169_get_regs_len(struct net_device *dev)
1618 {
1619         return R8169_REGS_SIZE;
1620 }
1621
1622 static int rtl8169_set_speed_tbi(struct net_device *dev,
1623                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1624 {
1625         struct rtl8169_private *tp = netdev_priv(dev);
1626         void __iomem *ioaddr = tp->mmio_addr;
1627         int ret = 0;
1628         u32 reg;
1629
1630         reg = RTL_R32(TBICSR);
1631         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1632             (duplex == DUPLEX_FULL)) {
1633                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1634         } else if (autoneg == AUTONEG_ENABLE)
1635                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1636         else {
1637                 netif_warn(tp, link, dev,
1638                            "incorrect speed setting refused in TBI mode\n");
1639                 ret = -EOPNOTSUPP;
1640         }
1641
1642         return ret;
1643 }
1644
1645 static int rtl8169_set_speed_xmii(struct net_device *dev,
1646                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1647 {
1648         struct rtl8169_private *tp = netdev_priv(dev);
1649         int giga_ctrl, bmcr;
1650         int rc = -EINVAL;
1651
1652         rtl_writephy(tp, 0x1f, 0x0000);
1653
1654         if (autoneg == AUTONEG_ENABLE) {
1655                 int auto_nego;
1656
1657                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1658                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1659                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1660
1661                 if (adv & ADVERTISED_10baseT_Half)
1662                         auto_nego |= ADVERTISE_10HALF;
1663                 if (adv & ADVERTISED_10baseT_Full)
1664                         auto_nego |= ADVERTISE_10FULL;
1665                 if (adv & ADVERTISED_100baseT_Half)
1666                         auto_nego |= ADVERTISE_100HALF;
1667                 if (adv & ADVERTISED_100baseT_Full)
1668                         auto_nego |= ADVERTISE_100FULL;
1669
1670                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1671
1672                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1673                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1674
1675                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1676                 if (tp->mii.supports_gmii) {
1677                         if (adv & ADVERTISED_1000baseT_Half)
1678                                 giga_ctrl |= ADVERTISE_1000HALF;
1679                         if (adv & ADVERTISED_1000baseT_Full)
1680                                 giga_ctrl |= ADVERTISE_1000FULL;
1681                 } else if (adv & (ADVERTISED_1000baseT_Half |
1682                                   ADVERTISED_1000baseT_Full)) {
1683                         netif_info(tp, link, dev,
1684                                    "PHY does not support 1000Mbps\n");
1685                         goto out;
1686                 }
1687
1688                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1689
1690                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1691                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1692         } else {
1693                 giga_ctrl = 0;
1694
1695                 if (speed == SPEED_10)
1696                         bmcr = 0;
1697                 else if (speed == SPEED_100)
1698                         bmcr = BMCR_SPEED100;
1699                 else
1700                         goto out;
1701
1702                 if (duplex == DUPLEX_FULL)
1703                         bmcr |= BMCR_FULLDPLX;
1704         }
1705
1706         rtl_writephy(tp, MII_BMCR, bmcr);
1707
1708         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1709             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1710                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1711                         rtl_writephy(tp, 0x17, 0x2138);
1712                         rtl_writephy(tp, 0x0e, 0x0260);
1713                 } else {
1714                         rtl_writephy(tp, 0x17, 0x2108);
1715                         rtl_writephy(tp, 0x0e, 0x0000);
1716                 }
1717         }
1718
1719         rc = 0;
1720 out:
1721         return rc;
1722 }
1723
1724 static int rtl8169_set_speed(struct net_device *dev,
1725                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1726 {
1727         struct rtl8169_private *tp = netdev_priv(dev);
1728         int ret;
1729
1730         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1731         if (ret < 0)
1732                 goto out;
1733
1734         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1735             (advertising & ADVERTISED_1000baseT_Full)) {
1736                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1737         }
1738 out:
1739         return ret;
1740 }
1741
1742 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1743 {
1744         struct rtl8169_private *tp = netdev_priv(dev);
1745         int ret;
1746
1747         del_timer_sync(&tp->timer);
1748
1749         rtl_lock_work(tp);
1750         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1751                                 cmd->duplex, cmd->advertising);
1752         rtl_unlock_work(tp);
1753
1754         return ret;
1755 }
1756
1757 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1758         netdev_features_t features)
1759 {
1760         struct rtl8169_private *tp = netdev_priv(dev);
1761
1762         if (dev->mtu > TD_MSS_MAX)
1763                 features &= ~NETIF_F_ALL_TSO;
1764
1765         if (dev->mtu > JUMBO_1K &&
1766             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1767                 features &= ~NETIF_F_IP_CSUM;
1768
1769         return features;
1770 }
1771
1772 static void __rtl8169_set_features(struct net_device *dev,
1773                                    netdev_features_t features)
1774 {
1775         struct rtl8169_private *tp = netdev_priv(dev);
1776         netdev_features_t changed = features ^ dev->features;
1777         void __iomem *ioaddr = tp->mmio_addr;
1778
1779         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1780                 return;
1781
1782         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1783                 if (features & NETIF_F_RXCSUM)
1784                         tp->cp_cmd |= RxChkSum;
1785                 else
1786                         tp->cp_cmd &= ~RxChkSum;
1787
1788                 if (dev->features & NETIF_F_HW_VLAN_RX)
1789                         tp->cp_cmd |= RxVlan;
1790                 else
1791                         tp->cp_cmd &= ~RxVlan;
1792
1793                 RTL_W16(CPlusCmd, tp->cp_cmd);
1794                 RTL_R16(CPlusCmd);
1795         }
1796         if (changed & NETIF_F_RXALL) {
1797                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1798                 if (features & NETIF_F_RXALL)
1799                         tmp |= (AcceptErr | AcceptRunt);
1800                 RTL_W32(RxConfig, tmp);
1801         }
1802 }
1803
1804 static int rtl8169_set_features(struct net_device *dev,
1805                                 netdev_features_t features)
1806 {
1807         struct rtl8169_private *tp = netdev_priv(dev);
1808
1809         rtl_lock_work(tp);
1810         __rtl8169_set_features(dev, features);
1811         rtl_unlock_work(tp);
1812
1813         return 0;
1814 }
1815
1816
1817 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1818 {
1819         return (vlan_tx_tag_present(skb)) ?
1820                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1821 }
1822
1823 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1824 {
1825         u32 opts2 = le32_to_cpu(desc->opts2);
1826
1827         if (opts2 & RxVlanTag)
1828                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1829 }
1830
1831 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1832 {
1833         struct rtl8169_private *tp = netdev_priv(dev);
1834         void __iomem *ioaddr = tp->mmio_addr;
1835         u32 status;
1836
1837         cmd->supported =
1838                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1839         cmd->port = PORT_FIBRE;
1840         cmd->transceiver = XCVR_INTERNAL;
1841
1842         status = RTL_R32(TBICSR);
1843         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1844         cmd->autoneg = !!(status & TBINwEnable);
1845
1846         ethtool_cmd_speed_set(cmd, SPEED_1000);
1847         cmd->duplex = DUPLEX_FULL; /* Always set */
1848
1849         return 0;
1850 }
1851
1852 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1853 {
1854         struct rtl8169_private *tp = netdev_priv(dev);
1855
1856         return mii_ethtool_gset(&tp->mii, cmd);
1857 }
1858
1859 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1860 {
1861         struct rtl8169_private *tp = netdev_priv(dev);
1862         int rc;
1863
1864         rtl_lock_work(tp);
1865         rc = tp->get_settings(dev, cmd);
1866         rtl_unlock_work(tp);
1867
1868         return rc;
1869 }
1870
1871 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1872                              void *p)
1873 {
1874         struct rtl8169_private *tp = netdev_priv(dev);
1875
1876         if (regs->len > R8169_REGS_SIZE)
1877                 regs->len = R8169_REGS_SIZE;
1878
1879         rtl_lock_work(tp);
1880         memcpy_fromio(p, tp->mmio_addr, regs->len);
1881         rtl_unlock_work(tp);
1882 }
1883
1884 static u32 rtl8169_get_msglevel(struct net_device *dev)
1885 {
1886         struct rtl8169_private *tp = netdev_priv(dev);
1887
1888         return tp->msg_enable;
1889 }
1890
1891 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1892 {
1893         struct rtl8169_private *tp = netdev_priv(dev);
1894
1895         tp->msg_enable = value;
1896 }
1897
1898 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1899         "tx_packets",
1900         "rx_packets",
1901         "tx_errors",
1902         "rx_errors",
1903         "rx_missed",
1904         "align_errors",
1905         "tx_single_collisions",
1906         "tx_multi_collisions",
1907         "unicast",
1908         "broadcast",
1909         "multicast",
1910         "tx_aborted",
1911         "tx_underrun",
1912 };
1913
1914 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1915 {
1916         switch (sset) {
1917         case ETH_SS_STATS:
1918                 return ARRAY_SIZE(rtl8169_gstrings);
1919         default:
1920                 return -EOPNOTSUPP;
1921         }
1922 }
1923
1924 DECLARE_RTL_COND(rtl_counters_cond)
1925 {
1926         void __iomem *ioaddr = tp->mmio_addr;
1927
1928         return RTL_R32(CounterAddrLow) & CounterDump;
1929 }
1930
1931 static void rtl8169_update_counters(struct net_device *dev)
1932 {
1933         struct rtl8169_private *tp = netdev_priv(dev);
1934         void __iomem *ioaddr = tp->mmio_addr;
1935         struct device *d = &tp->pci_dev->dev;
1936         struct rtl8169_counters *counters;
1937         dma_addr_t paddr;
1938         u32 cmd;
1939
1940         /*
1941          * Some chips are unable to dump tally counters when the receiver
1942          * is disabled.
1943          */
1944         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1945                 return;
1946
1947         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1948         if (!counters)
1949                 return;
1950
1951         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1952         cmd = (u64)paddr & DMA_BIT_MASK(32);
1953         RTL_W32(CounterAddrLow, cmd);
1954         RTL_W32(CounterAddrLow, cmd | CounterDump);
1955
1956         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1957                 memcpy(&tp->counters, counters, sizeof(*counters));
1958
1959         RTL_W32(CounterAddrLow, 0);
1960         RTL_W32(CounterAddrHigh, 0);
1961
1962         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1963 }
1964
1965 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1966                                       struct ethtool_stats *stats, u64 *data)
1967 {
1968         struct rtl8169_private *tp = netdev_priv(dev);
1969
1970         ASSERT_RTNL();
1971
1972         rtl8169_update_counters(dev);
1973
1974         data[0] = le64_to_cpu(tp->counters.tx_packets);
1975         data[1] = le64_to_cpu(tp->counters.rx_packets);
1976         data[2] = le64_to_cpu(tp->counters.tx_errors);
1977         data[3] = le32_to_cpu(tp->counters.rx_errors);
1978         data[4] = le16_to_cpu(tp->counters.rx_missed);
1979         data[5] = le16_to_cpu(tp->counters.align_errors);
1980         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1981         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1982         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1983         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1984         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1985         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1986         data[12] = le16_to_cpu(tp->counters.tx_underun);
1987 }
1988
1989 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1990 {
1991         switch(stringset) {
1992         case ETH_SS_STATS:
1993                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1994                 break;
1995         }
1996 }
1997
1998 static const struct ethtool_ops rtl8169_ethtool_ops = {
1999         .get_drvinfo            = rtl8169_get_drvinfo,
2000         .get_regs_len           = rtl8169_get_regs_len,
2001         .get_link               = ethtool_op_get_link,
2002         .get_settings           = rtl8169_get_settings,
2003         .set_settings           = rtl8169_set_settings,
2004         .get_msglevel           = rtl8169_get_msglevel,
2005         .set_msglevel           = rtl8169_set_msglevel,
2006         .get_regs               = rtl8169_get_regs,
2007         .get_wol                = rtl8169_get_wol,
2008         .set_wol                = rtl8169_set_wol,
2009         .get_strings            = rtl8169_get_strings,
2010         .get_sset_count         = rtl8169_get_sset_count,
2011         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2012         .get_ts_info            = ethtool_op_get_ts_info,
2013 };
2014
2015 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2016                                     struct net_device *dev, u8 default_version)
2017 {
2018         void __iomem *ioaddr = tp->mmio_addr;
2019         /*
2020          * The driver currently handles the 8168Bf and the 8168Be identically
2021          * but they can be identified more specifically through the test below
2022          * if needed:
2023          *
2024          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2025          *
2026          * Same thing for the 8101Eb and the 8101Ec:
2027          *
2028          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2029          */
2030         static const struct rtl_mac_info {
2031                 u32 mask;
2032                 u32 val;
2033                 int mac_version;
2034         } mac_info[] = {
2035                 /* 8168G family. */
2036                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2037                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2038
2039                 /* 8168F family. */
2040                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2041                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2042                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2043
2044                 /* 8168E family. */
2045                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2046                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2047                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2048                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2049
2050                 /* 8168D family. */
2051                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2052                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2053                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2054
2055                 /* 8168DP family. */
2056                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2057                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2058                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2059
2060                 /* 8168C family. */
2061                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2062                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2063                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2064                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2065                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2066                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2067                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2068                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2069                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2070
2071                 /* 8168B family. */
2072                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2073                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2074                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2075                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2076
2077                 /* 8101 family. */
2078                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2079                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2080                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2081                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2082                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2083                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2084                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2085                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2086                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2087                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2088                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2089                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2090                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2091                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2092                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2093                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2094                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2095                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2096                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2097                 /* FIXME: where did these entries come from ? -- FR */
2098                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2099                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2100
2101                 /* 8110 family. */
2102                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2103                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2104                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2105                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2106                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2107                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2108
2109                 /* Catch-all */
2110                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2111         };
2112         const struct rtl_mac_info *p = mac_info;
2113         u32 reg;
2114
2115         reg = RTL_R32(TxConfig);
2116         while ((reg & p->mask) != p->val)
2117                 p++;
2118         tp->mac_version = p->mac_version;
2119
2120         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2121                 netif_notice(tp, probe, dev,
2122                              "unknown MAC, using family default\n");
2123                 tp->mac_version = default_version;
2124         }
2125 }
2126
2127 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2128 {
2129         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2130 }
2131
2132 struct phy_reg {
2133         u16 reg;
2134         u16 val;
2135 };
2136
2137 static void rtl_writephy_batch(struct rtl8169_private *tp,
2138                                const struct phy_reg *regs, int len)
2139 {
2140         while (len-- > 0) {
2141                 rtl_writephy(tp, regs->reg, regs->val);
2142                 regs++;
2143         }
2144 }
2145
2146 #define PHY_READ                0x00000000
2147 #define PHY_DATA_OR             0x10000000
2148 #define PHY_DATA_AND            0x20000000
2149 #define PHY_BJMPN               0x30000000
2150 #define PHY_READ_EFUSE          0x40000000
2151 #define PHY_READ_MAC_BYTE       0x50000000
2152 #define PHY_WRITE_MAC_BYTE      0x60000000
2153 #define PHY_CLEAR_READCOUNT     0x70000000
2154 #define PHY_WRITE               0x80000000
2155 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2156 #define PHY_COMP_EQ_SKIPN       0xa0000000
2157 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2158 #define PHY_WRITE_PREVIOUS      0xc0000000
2159 #define PHY_SKIPN               0xd0000000
2160 #define PHY_DELAY_MS            0xe0000000
2161 #define PHY_WRITE_ERI_WORD      0xf0000000
2162
2163 struct fw_info {
2164         u32     magic;
2165         char    version[RTL_VER_SIZE];
2166         __le32  fw_start;
2167         __le32  fw_len;
2168         u8      chksum;
2169 } __packed;
2170
2171 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2172
2173 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2174 {
2175         const struct firmware *fw = rtl_fw->fw;
2176         struct fw_info *fw_info = (struct fw_info *)fw->data;
2177         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2178         char *version = rtl_fw->version;
2179         bool rc = false;
2180
2181         if (fw->size < FW_OPCODE_SIZE)
2182                 goto out;
2183
2184         if (!fw_info->magic) {
2185                 size_t i, size, start;
2186                 u8 checksum = 0;
2187
2188                 if (fw->size < sizeof(*fw_info))
2189                         goto out;
2190
2191                 for (i = 0; i < fw->size; i++)
2192                         checksum += fw->data[i];
2193                 if (checksum != 0)
2194                         goto out;
2195
2196                 start = le32_to_cpu(fw_info->fw_start);
2197                 if (start > fw->size)
2198                         goto out;
2199
2200                 size = le32_to_cpu(fw_info->fw_len);
2201                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2202                         goto out;
2203
2204                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2205
2206                 pa->code = (__le32 *)(fw->data + start);
2207                 pa->size = size;
2208         } else {
2209                 if (fw->size % FW_OPCODE_SIZE)
2210                         goto out;
2211
2212                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2213
2214                 pa->code = (__le32 *)fw->data;
2215                 pa->size = fw->size / FW_OPCODE_SIZE;
2216         }
2217         version[RTL_VER_SIZE - 1] = 0;
2218
2219         rc = true;
2220 out:
2221         return rc;
2222 }
2223
2224 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2225                            struct rtl_fw_phy_action *pa)
2226 {
2227         bool rc = false;
2228         size_t index;
2229
2230         for (index = 0; index < pa->size; index++) {
2231                 u32 action = le32_to_cpu(pa->code[index]);
2232                 u32 regno = (action & 0x0fff0000) >> 16;
2233
2234                 switch(action & 0xf0000000) {
2235                 case PHY_READ:
2236                 case PHY_DATA_OR:
2237                 case PHY_DATA_AND:
2238                 case PHY_READ_EFUSE:
2239                 case PHY_CLEAR_READCOUNT:
2240                 case PHY_WRITE:
2241                 case PHY_WRITE_PREVIOUS:
2242                 case PHY_DELAY_MS:
2243                         break;
2244
2245                 case PHY_BJMPN:
2246                         if (regno > index) {
2247                                 netif_err(tp, ifup, tp->dev,
2248                                           "Out of range of firmware\n");
2249                                 goto out;
2250                         }
2251                         break;
2252                 case PHY_READCOUNT_EQ_SKIP:
2253                         if (index + 2 >= pa->size) {
2254                                 netif_err(tp, ifup, tp->dev,
2255                                           "Out of range of firmware\n");
2256                                 goto out;
2257                         }
2258                         break;
2259                 case PHY_COMP_EQ_SKIPN:
2260                 case PHY_COMP_NEQ_SKIPN:
2261                 case PHY_SKIPN:
2262                         if (index + 1 + regno >= pa->size) {
2263                                 netif_err(tp, ifup, tp->dev,
2264                                           "Out of range of firmware\n");
2265                                 goto out;
2266                         }
2267                         break;
2268
2269                 case PHY_READ_MAC_BYTE:
2270                 case PHY_WRITE_MAC_BYTE:
2271                 case PHY_WRITE_ERI_WORD:
2272                 default:
2273                         netif_err(tp, ifup, tp->dev,
2274                                   "Invalid action 0x%08x\n", action);
2275                         goto out;
2276                 }
2277         }
2278         rc = true;
2279 out:
2280         return rc;
2281 }
2282
2283 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2284 {
2285         struct net_device *dev = tp->dev;
2286         int rc = -EINVAL;
2287
2288         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2289                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2290                 goto out;
2291         }
2292
2293         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2294                 rc = 0;
2295 out:
2296         return rc;
2297 }
2298
2299 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2300 {
2301         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2302         u32 predata, count;
2303         size_t index;
2304
2305         predata = count = 0;
2306
2307         for (index = 0; index < pa->size; ) {
2308                 u32 action = le32_to_cpu(pa->code[index]);
2309                 u32 data = action & 0x0000ffff;
2310                 u32 regno = (action & 0x0fff0000) >> 16;
2311
2312                 if (!action)
2313                         break;
2314
2315                 switch(action & 0xf0000000) {
2316                 case PHY_READ:
2317                         predata = rtl_readphy(tp, regno);
2318                         count++;
2319                         index++;
2320                         break;
2321                 case PHY_DATA_OR:
2322                         predata |= data;
2323                         index++;
2324                         break;
2325                 case PHY_DATA_AND:
2326                         predata &= data;
2327                         index++;
2328                         break;
2329                 case PHY_BJMPN:
2330                         index -= regno;
2331                         break;
2332                 case PHY_READ_EFUSE:
2333                         predata = rtl8168d_efuse_read(tp, regno);
2334                         index++;
2335                         break;
2336                 case PHY_CLEAR_READCOUNT:
2337                         count = 0;
2338                         index++;
2339                         break;
2340                 case PHY_WRITE:
2341                         rtl_writephy(tp, regno, data);
2342                         index++;
2343                         break;
2344                 case PHY_READCOUNT_EQ_SKIP:
2345                         index += (count == data) ? 2 : 1;
2346                         break;
2347                 case PHY_COMP_EQ_SKIPN:
2348                         if (predata == data)
2349                                 index += regno;
2350                         index++;
2351                         break;
2352                 case PHY_COMP_NEQ_SKIPN:
2353                         if (predata != data)
2354                                 index += regno;
2355                         index++;
2356                         break;
2357                 case PHY_WRITE_PREVIOUS:
2358                         rtl_writephy(tp, regno, predata);
2359                         index++;
2360                         break;
2361                 case PHY_SKIPN:
2362                         index += regno + 1;
2363                         break;
2364                 case PHY_DELAY_MS:
2365                         mdelay(data);
2366                         index++;
2367                         break;
2368
2369                 case PHY_READ_MAC_BYTE:
2370                 case PHY_WRITE_MAC_BYTE:
2371                 case PHY_WRITE_ERI_WORD:
2372                 default:
2373                         BUG();
2374                 }
2375         }
2376 }
2377
2378 static void rtl_release_firmware(struct rtl8169_private *tp)
2379 {
2380         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2381                 release_firmware(tp->rtl_fw->fw);
2382                 kfree(tp->rtl_fw);
2383         }
2384         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2385 }
2386
2387 static void rtl_apply_firmware(struct rtl8169_private *tp)
2388 {
2389         struct rtl_fw *rtl_fw = tp->rtl_fw;
2390
2391         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2392         if (!IS_ERR_OR_NULL(rtl_fw)) {
2393                 rtl_phy_write_fw(tp, rtl_fw);
2394                 tp->features |= RTL_FEATURE_FW_LOADED;
2395         }
2396 }
2397
2398 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2399 {
2400         if (rtl_readphy(tp, reg) != val)
2401                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2402         else
2403                 rtl_apply_firmware(tp);
2404 }
2405
2406 static void r810x_aldps_disable(struct rtl8169_private *tp)
2407 {
2408         rtl_writephy(tp, 0x1f, 0x0000);
2409         rtl_writephy(tp, 0x18, 0x0310);
2410         msleep(100);
2411 }
2412
2413 static void r810x_aldps_enable(struct rtl8169_private *tp)
2414 {
2415         if (!(tp->features & RTL_FEATURE_FW_LOADED))
2416                 return;
2417
2418         rtl_writephy(tp, 0x1f, 0x0000);
2419         rtl_writephy(tp, 0x18, 0x8310);
2420 }
2421
2422 static void r8168_aldps_enable_1(struct rtl8169_private *tp)
2423 {
2424         if (!(tp->features & RTL_FEATURE_FW_LOADED))
2425                 return;
2426
2427         rtl_writephy(tp, 0x1f, 0x0000);
2428         rtl_w1w0_phy(tp, 0x15, 0x1000, 0x0000);
2429 }
2430
2431 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2432 {
2433         static const struct phy_reg phy_reg_init[] = {
2434                 { 0x1f, 0x0001 },
2435                 { 0x06, 0x006e },
2436                 { 0x08, 0x0708 },
2437                 { 0x15, 0x4000 },
2438                 { 0x18, 0x65c7 },
2439
2440                 { 0x1f, 0x0001 },
2441                 { 0x03, 0x00a1 },
2442                 { 0x02, 0x0008 },
2443                 { 0x01, 0x0120 },
2444                 { 0x00, 0x1000 },
2445                 { 0x04, 0x0800 },
2446                 { 0x04, 0x0000 },
2447
2448                 { 0x03, 0xff41 },
2449                 { 0x02, 0xdf60 },
2450                 { 0x01, 0x0140 },
2451                 { 0x00, 0x0077 },
2452                 { 0x04, 0x7800 },
2453                 { 0x04, 0x7000 },
2454
2455                 { 0x03, 0x802f },
2456                 { 0x02, 0x4f02 },
2457                 { 0x01, 0x0409 },
2458                 { 0x00, 0xf0f9 },
2459                 { 0x04, 0x9800 },
2460                 { 0x04, 0x9000 },
2461
2462                 { 0x03, 0xdf01 },
2463                 { 0x02, 0xdf20 },
2464                 { 0x01, 0xff95 },
2465                 { 0x00, 0xba00 },
2466                 { 0x04, 0xa800 },
2467                 { 0x04, 0xa000 },
2468
2469                 { 0x03, 0xff41 },
2470                 { 0x02, 0xdf20 },
2471                 { 0x01, 0x0140 },
2472                 { 0x00, 0x00bb },
2473                 { 0x04, 0xb800 },
2474                 { 0x04, 0xb000 },
2475
2476                 { 0x03, 0xdf41 },
2477                 { 0x02, 0xdc60 },
2478                 { 0x01, 0x6340 },
2479                 { 0x00, 0x007d },
2480                 { 0x04, 0xd800 },
2481                 { 0x04, 0xd000 },
2482
2483                 { 0x03, 0xdf01 },
2484                 { 0x02, 0xdf20 },
2485                 { 0x01, 0x100a },
2486                 { 0x00, 0xa0ff },
2487                 { 0x04, 0xf800 },
2488                 { 0x04, 0xf000 },
2489
2490                 { 0x1f, 0x0000 },
2491                 { 0x0b, 0x0000 },
2492                 { 0x00, 0x9200 }
2493         };
2494
2495         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2496 }
2497
2498 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2499 {
2500         static const struct phy_reg phy_reg_init[] = {
2501                 { 0x1f, 0x0002 },
2502                 { 0x01, 0x90d0 },
2503                 { 0x1f, 0x0000 }
2504         };
2505
2506         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2507 }
2508
2509 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2510 {
2511         struct pci_dev *pdev = tp->pci_dev;
2512
2513         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2514             (pdev->subsystem_device != 0xe000))
2515                 return;
2516
2517         rtl_writephy(tp, 0x1f, 0x0001);
2518         rtl_writephy(tp, 0x10, 0xf01b);
2519         rtl_writephy(tp, 0x1f, 0x0000);
2520 }
2521
2522 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2523 {
2524         static const struct phy_reg phy_reg_init[] = {
2525                 { 0x1f, 0x0001 },
2526                 { 0x04, 0x0000 },
2527                 { 0x03, 0x00a1 },
2528                 { 0x02, 0x0008 },
2529                 { 0x01, 0x0120 },
2530                 { 0x00, 0x1000 },
2531                 { 0x04, 0x0800 },
2532                 { 0x04, 0x9000 },
2533                 { 0x03, 0x802f },
2534                 { 0x02, 0x4f02 },
2535                 { 0x01, 0x0409 },
2536                 { 0x00, 0xf099 },
2537                 { 0x04, 0x9800 },
2538                 { 0x04, 0xa000 },
2539                 { 0x03, 0xdf01 },
2540                 { 0x02, 0xdf20 },
2541                 { 0x01, 0xff95 },
2542                 { 0x00, 0xba00 },
2543                 { 0x04, 0xa800 },
2544                 { 0x04, 0xf000 },
2545                 { 0x03, 0xdf01 },
2546                 { 0x02, 0xdf20 },
2547                 { 0x01, 0x101a },
2548                 { 0x00, 0xa0ff },
2549                 { 0x04, 0xf800 },
2550                 { 0x04, 0x0000 },
2551                 { 0x1f, 0x0000 },
2552
2553                 { 0x1f, 0x0001 },
2554                 { 0x10, 0xf41b },
2555                 { 0x14, 0xfb54 },
2556                 { 0x18, 0xf5c7 },
2557                 { 0x1f, 0x0000 },
2558
2559                 { 0x1f, 0x0001 },
2560                 { 0x17, 0x0cc0 },
2561                 { 0x1f, 0x0000 }
2562         };
2563
2564         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2565
2566         rtl8169scd_hw_phy_config_quirk(tp);
2567 }
2568
2569 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2570 {
2571         static const struct phy_reg phy_reg_init[] = {
2572                 { 0x1f, 0x0001 },
2573                 { 0x04, 0x0000 },
2574                 { 0x03, 0x00a1 },
2575                 { 0x02, 0x0008 },
2576                 { 0x01, 0x0120 },
2577                 { 0x00, 0x1000 },
2578                 { 0x04, 0x0800 },
2579                 { 0x04, 0x9000 },
2580                 { 0x03, 0x802f },
2581                 { 0x02, 0x4f02 },
2582                 { 0x01, 0x0409 },
2583                 { 0x00, 0xf099 },
2584                 { 0x04, 0x9800 },
2585                 { 0x04, 0xa000 },
2586                 { 0x03, 0xdf01 },
2587                 { 0x02, 0xdf20 },
2588                 { 0x01, 0xff95 },
2589                 { 0x00, 0xba00 },
2590                 { 0x04, 0xa800 },
2591                 { 0x04, 0xf000 },
2592                 { 0x03, 0xdf01 },
2593                 { 0x02, 0xdf20 },
2594                 { 0x01, 0x101a },
2595                 { 0x00, 0xa0ff },
2596                 { 0x04, 0xf800 },
2597                 { 0x04, 0x0000 },
2598                 { 0x1f, 0x0000 },
2599
2600                 { 0x1f, 0x0001 },
2601                 { 0x0b, 0x8480 },
2602                 { 0x1f, 0x0000 },
2603
2604                 { 0x1f, 0x0001 },
2605                 { 0x18, 0x67c7 },
2606                 { 0x04, 0x2000 },
2607                 { 0x03, 0x002f },
2608                 { 0x02, 0x4360 },
2609                 { 0x01, 0x0109 },
2610                 { 0x00, 0x3022 },
2611                 { 0x04, 0x2800 },
2612                 { 0x1f, 0x0000 },
2613
2614                 { 0x1f, 0x0001 },
2615                 { 0x17, 0x0cc0 },
2616                 { 0x1f, 0x0000 }
2617         };
2618
2619         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2620 }
2621
2622 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2623 {
2624         static const struct phy_reg phy_reg_init[] = {
2625                 { 0x10, 0xf41b },
2626                 { 0x1f, 0x0000 }
2627         };
2628
2629         rtl_writephy(tp, 0x1f, 0x0001);
2630         rtl_patchphy(tp, 0x16, 1 << 0);
2631
2632         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2633 }
2634
2635 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2636 {
2637         static const struct phy_reg phy_reg_init[] = {
2638                 { 0x1f, 0x0001 },
2639                 { 0x10, 0xf41b },
2640                 { 0x1f, 0x0000 }
2641         };
2642
2643         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2644 }
2645
2646 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2647 {
2648         static const struct phy_reg phy_reg_init[] = {
2649                 { 0x1f, 0x0000 },
2650                 { 0x1d, 0x0f00 },
2651                 { 0x1f, 0x0002 },
2652                 { 0x0c, 0x1ec8 },
2653                 { 0x1f, 0x0000 }
2654         };
2655
2656         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2657 }
2658
2659 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2660 {
2661         static const struct phy_reg phy_reg_init[] = {
2662                 { 0x1f, 0x0001 },
2663                 { 0x1d, 0x3d98 },
2664                 { 0x1f, 0x0000 }
2665         };
2666
2667         rtl_writephy(tp, 0x1f, 0x0000);
2668         rtl_patchphy(tp, 0x14, 1 << 5);
2669         rtl_patchphy(tp, 0x0d, 1 << 5);
2670
2671         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2672 }
2673
2674 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2675 {
2676         static const struct phy_reg phy_reg_init[] = {
2677                 { 0x1f, 0x0001 },
2678                 { 0x12, 0x2300 },
2679                 { 0x1f, 0x0002 },
2680                 { 0x00, 0x88d4 },
2681                 { 0x01, 0x82b1 },
2682                 { 0x03, 0x7002 },
2683                 { 0x08, 0x9e30 },
2684                 { 0x09, 0x01f0 },
2685                 { 0x0a, 0x5500 },
2686                 { 0x0c, 0x00c8 },
2687                 { 0x1f, 0x0003 },
2688                 { 0x12, 0xc096 },
2689                 { 0x16, 0x000a },
2690                 { 0x1f, 0x0000 },
2691                 { 0x1f, 0x0000 },
2692                 { 0x09, 0x2000 },
2693                 { 0x09, 0x0000 }
2694         };
2695
2696         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2697
2698         rtl_patchphy(tp, 0x14, 1 << 5);
2699         rtl_patchphy(tp, 0x0d, 1 << 5);
2700         rtl_writephy(tp, 0x1f, 0x0000);
2701 }
2702
2703 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2704 {
2705         static const struct phy_reg phy_reg_init[] = {
2706                 { 0x1f, 0x0001 },
2707                 { 0x12, 0x2300 },
2708                 { 0x03, 0x802f },
2709                 { 0x02, 0x4f02 },
2710                 { 0x01, 0x0409 },
2711                 { 0x00, 0xf099 },
2712                 { 0x04, 0x9800 },
2713                 { 0x04, 0x9000 },
2714                 { 0x1d, 0x3d98 },
2715                 { 0x1f, 0x0002 },
2716                 { 0x0c, 0x7eb8 },
2717                 { 0x06, 0x0761 },
2718                 { 0x1f, 0x0003 },
2719                 { 0x16, 0x0f0a },
2720                 { 0x1f, 0x0000 }
2721         };
2722
2723         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2724
2725         rtl_patchphy(tp, 0x16, 1 << 0);
2726         rtl_patchphy(tp, 0x14, 1 << 5);
2727         rtl_patchphy(tp, 0x0d, 1 << 5);
2728         rtl_writephy(tp, 0x1f, 0x0000);
2729 }
2730
2731 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2732 {
2733         static const struct phy_reg phy_reg_init[] = {
2734                 { 0x1f, 0x0001 },
2735                 { 0x12, 0x2300 },
2736                 { 0x1d, 0x3d98 },
2737                 { 0x1f, 0x0002 },
2738                 { 0x0c, 0x7eb8 },
2739                 { 0x06, 0x5461 },
2740                 { 0x1f, 0x0003 },
2741                 { 0x16, 0x0f0a },
2742                 { 0x1f, 0x0000 }
2743         };
2744
2745         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746
2747         rtl_patchphy(tp, 0x16, 1 << 0);
2748         rtl_patchphy(tp, 0x14, 1 << 5);
2749         rtl_patchphy(tp, 0x0d, 1 << 5);
2750         rtl_writephy(tp, 0x1f, 0x0000);
2751 }
2752
2753 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2754 {
2755         rtl8168c_3_hw_phy_config(tp);
2756 }
2757
2758 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2759 {
2760         static const struct phy_reg phy_reg_init_0[] = {
2761                 /* Channel Estimation */
2762                 { 0x1f, 0x0001 },
2763                 { 0x06, 0x4064 },
2764                 { 0x07, 0x2863 },
2765                 { 0x08, 0x059c },
2766                 { 0x09, 0x26b4 },
2767                 { 0x0a, 0x6a19 },
2768                 { 0x0b, 0xdcc8 },
2769                 { 0x10, 0xf06d },
2770                 { 0x14, 0x7f68 },
2771                 { 0x18, 0x7fd9 },
2772                 { 0x1c, 0xf0ff },
2773                 { 0x1d, 0x3d9c },
2774                 { 0x1f, 0x0003 },
2775                 { 0x12, 0xf49f },
2776                 { 0x13, 0x070b },
2777                 { 0x1a, 0x05ad },
2778                 { 0x14, 0x94c0 },
2779
2780                 /*
2781                  * Tx Error Issue
2782                  * Enhance line driver power
2783                  */
2784                 { 0x1f, 0x0002 },
2785                 { 0x06, 0x5561 },
2786                 { 0x1f, 0x0005 },
2787                 { 0x05, 0x8332 },
2788                 { 0x06, 0x5561 },
2789
2790                 /*
2791                  * Can not link to 1Gbps with bad cable
2792                  * Decrease SNR threshold form 21.07dB to 19.04dB
2793                  */
2794                 { 0x1f, 0x0001 },
2795                 { 0x17, 0x0cc0 },
2796
2797                 { 0x1f, 0x0000 },
2798                 { 0x0d, 0xf880 }
2799         };
2800
2801         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2802
2803         /*
2804          * Rx Error Issue
2805          * Fine Tune Switching regulator parameter
2806          */
2807         rtl_writephy(tp, 0x1f, 0x0002);
2808         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2809         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2810
2811         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2812                 static const struct phy_reg phy_reg_init[] = {
2813                         { 0x1f, 0x0002 },
2814                         { 0x05, 0x669a },
2815                         { 0x1f, 0x0005 },
2816                         { 0x05, 0x8330 },
2817                         { 0x06, 0x669a },
2818                         { 0x1f, 0x0002 }
2819                 };
2820                 int val;
2821
2822                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2823
2824                 val = rtl_readphy(tp, 0x0d);
2825
2826                 if ((val & 0x00ff) != 0x006c) {
2827                         static const u32 set[] = {
2828                                 0x0065, 0x0066, 0x0067, 0x0068,
2829                                 0x0069, 0x006a, 0x006b, 0x006c
2830                         };
2831                         int i;
2832
2833                         rtl_writephy(tp, 0x1f, 0x0002);
2834
2835                         val &= 0xff00;
2836                         for (i = 0; i < ARRAY_SIZE(set); i++)
2837                                 rtl_writephy(tp, 0x0d, val | set[i]);
2838                 }
2839         } else {
2840                 static const struct phy_reg phy_reg_init[] = {
2841                         { 0x1f, 0x0002 },
2842                         { 0x05, 0x6662 },
2843                         { 0x1f, 0x0005 },
2844                         { 0x05, 0x8330 },
2845                         { 0x06, 0x6662 }
2846                 };
2847
2848                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2849         }
2850
2851         /* RSET couple improve */
2852         rtl_writephy(tp, 0x1f, 0x0002);
2853         rtl_patchphy(tp, 0x0d, 0x0300);
2854         rtl_patchphy(tp, 0x0f, 0x0010);
2855
2856         /* Fine tune PLL performance */
2857         rtl_writephy(tp, 0x1f, 0x0002);
2858         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2859         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2860
2861         rtl_writephy(tp, 0x1f, 0x0005);
2862         rtl_writephy(tp, 0x05, 0x001b);
2863
2864         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2865
2866         rtl_writephy(tp, 0x1f, 0x0000);
2867 }
2868
2869 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2870 {
2871         static const struct phy_reg phy_reg_init_0[] = {
2872                 /* Channel Estimation */
2873                 { 0x1f, 0x0001 },
2874                 { 0x06, 0x4064 },
2875                 { 0x07, 0x2863 },
2876                 { 0x08, 0x059c },
2877                 { 0x09, 0x26b4 },
2878                 { 0x0a, 0x6a19 },
2879                 { 0x0b, 0xdcc8 },
2880                 { 0x10, 0xf06d },
2881                 { 0x14, 0x7f68 },
2882                 { 0x18, 0x7fd9 },
2883                 { 0x1c, 0xf0ff },
2884                 { 0x1d, 0x3d9c },
2885                 { 0x1f, 0x0003 },
2886                 { 0x12, 0xf49f },
2887                 { 0x13, 0x070b },
2888                 { 0x1a, 0x05ad },
2889                 { 0x14, 0x94c0 },
2890
2891                 /*
2892                  * Tx Error Issue
2893                  * Enhance line driver power
2894                  */
2895                 { 0x1f, 0x0002 },
2896                 { 0x06, 0x5561 },
2897                 { 0x1f, 0x0005 },
2898                 { 0x05, 0x8332 },
2899                 { 0x06, 0x5561 },
2900
2901                 /*
2902                  * Can not link to 1Gbps with bad cable
2903                  * Decrease SNR threshold form 21.07dB to 19.04dB
2904                  */
2905                 { 0x1f, 0x0001 },
2906                 { 0x17, 0x0cc0 },
2907
2908                 { 0x1f, 0x0000 },
2909                 { 0x0d, 0xf880 }
2910         };
2911
2912         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2913
2914         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2915                 static const struct phy_reg phy_reg_init[] = {
2916                         { 0x1f, 0x0002 },
2917                         { 0x05, 0x669a },
2918                         { 0x1f, 0x0005 },
2919                         { 0x05, 0x8330 },
2920                         { 0x06, 0x669a },
2921
2922                         { 0x1f, 0x0002 }
2923                 };
2924                 int val;
2925
2926                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2927
2928                 val = rtl_readphy(tp, 0x0d);
2929                 if ((val & 0x00ff) != 0x006c) {
2930                         static const u32 set[] = {
2931                                 0x0065, 0x0066, 0x0067, 0x0068,
2932                                 0x0069, 0x006a, 0x006b, 0x006c
2933                         };
2934                         int i;
2935
2936                         rtl_writephy(tp, 0x1f, 0x0002);
2937
2938                         val &= 0xff00;
2939                         for (i = 0; i < ARRAY_SIZE(set); i++)
2940                                 rtl_writephy(tp, 0x0d, val | set[i]);
2941                 }
2942         } else {
2943                 static const struct phy_reg phy_reg_init[] = {
2944                         { 0x1f, 0x0002 },
2945                         { 0x05, 0x2642 },
2946                         { 0x1f, 0x0005 },
2947                         { 0x05, 0x8330 },
2948                         { 0x06, 0x2642 }
2949                 };
2950
2951                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2952         }
2953
2954         /* Fine tune PLL performance */
2955         rtl_writephy(tp, 0x1f, 0x0002);
2956         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2957         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2958
2959         /* Switching regulator Slew rate */
2960         rtl_writephy(tp, 0x1f, 0x0002);
2961         rtl_patchphy(tp, 0x0f, 0x0017);
2962
2963         rtl_writephy(tp, 0x1f, 0x0005);
2964         rtl_writephy(tp, 0x05, 0x001b);
2965
2966         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2967
2968         rtl_writephy(tp, 0x1f, 0x0000);
2969 }
2970
2971 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2972 {
2973         static const struct phy_reg phy_reg_init[] = {
2974                 { 0x1f, 0x0002 },
2975                 { 0x10, 0x0008 },
2976                 { 0x0d, 0x006c },
2977
2978                 { 0x1f, 0x0000 },
2979                 { 0x0d, 0xf880 },
2980
2981                 { 0x1f, 0x0001 },
2982                 { 0x17, 0x0cc0 },
2983
2984                 { 0x1f, 0x0001 },
2985                 { 0x0b, 0xa4d8 },
2986                 { 0x09, 0x281c },
2987                 { 0x07, 0x2883 },
2988                 { 0x0a, 0x6b35 },
2989                 { 0x1d, 0x3da4 },
2990                 { 0x1c, 0xeffd },
2991                 { 0x14, 0x7f52 },
2992                 { 0x18, 0x7fc6 },
2993                 { 0x08, 0x0601 },
2994                 { 0x06, 0x4063 },
2995                 { 0x10, 0xf074 },
2996                 { 0x1f, 0x0003 },
2997                 { 0x13, 0x0789 },
2998                 { 0x12, 0xf4bd },
2999                 { 0x1a, 0x04fd },
3000                 { 0x14, 0x84b0 },
3001                 { 0x1f, 0x0000 },
3002                 { 0x00, 0x9200 },
3003
3004                 { 0x1f, 0x0005 },
3005                 { 0x01, 0x0340 },
3006                 { 0x1f, 0x0001 },
3007                 { 0x04, 0x4000 },
3008                 { 0x03, 0x1d21 },
3009                 { 0x02, 0x0c32 },
3010                 { 0x01, 0x0200 },
3011                 { 0x00, 0x5554 },
3012                 { 0x04, 0x4800 },
3013                 { 0x04, 0x4000 },
3014                 { 0x04, 0xf000 },
3015                 { 0x03, 0xdf01 },
3016                 { 0x02, 0xdf20 },
3017                 { 0x01, 0x101a },
3018                 { 0x00, 0xa0ff },
3019                 { 0x04, 0xf800 },
3020                 { 0x04, 0xf000 },
3021                 { 0x1f, 0x0000 },
3022
3023                 { 0x1f, 0x0007 },
3024                 { 0x1e, 0x0023 },
3025                 { 0x16, 0x0000 },
3026                 { 0x1f, 0x0000 }
3027         };
3028
3029         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3030 }
3031
3032 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3033 {
3034         static const struct phy_reg phy_reg_init[] = {
3035                 { 0x1f, 0x0001 },
3036                 { 0x17, 0x0cc0 },
3037
3038                 { 0x1f, 0x0007 },
3039                 { 0x1e, 0x002d },
3040                 { 0x18, 0x0040 },
3041                 { 0x1f, 0x0000 }
3042         };
3043
3044         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3045         rtl_patchphy(tp, 0x0d, 1 << 5);
3046 }
3047
3048 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3049 {
3050         static const struct phy_reg phy_reg_init[] = {
3051                 /* Enable Delay cap */
3052                 { 0x1f, 0x0005 },
3053                 { 0x05, 0x8b80 },
3054                 { 0x06, 0xc896 },
3055                 { 0x1f, 0x0000 },
3056
3057                 /* Channel estimation fine tune */
3058                 { 0x1f, 0x0001 },
3059                 { 0x0b, 0x6c20 },
3060                 { 0x07, 0x2872 },
3061                 { 0x1c, 0xefff },
3062                 { 0x1f, 0x0003 },
3063                 { 0x14, 0x6420 },
3064                 { 0x1f, 0x0000 },
3065
3066                 /* Update PFM & 10M TX idle timer */
3067                 { 0x1f, 0x0007 },
3068                 { 0x1e, 0x002f },
3069                 { 0x15, 0x1919 },
3070                 { 0x1f, 0x0000 },
3071
3072                 { 0x1f, 0x0007 },
3073                 { 0x1e, 0x00ac },
3074                 { 0x18, 0x0006 },
3075                 { 0x1f, 0x0000 }
3076         };
3077
3078         rtl_apply_firmware(tp);
3079
3080         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3081
3082         /* DCO enable for 10M IDLE Power */
3083         rtl_writephy(tp, 0x1f, 0x0007);
3084         rtl_writephy(tp, 0x1e, 0x0023);
3085         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3086         rtl_writephy(tp, 0x1f, 0x0000);
3087
3088         /* For impedance matching */
3089         rtl_writephy(tp, 0x1f, 0x0002);
3090         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3091         rtl_writephy(tp, 0x1f, 0x0000);
3092
3093         /* PHY auto speed down */
3094         rtl_writephy(tp, 0x1f, 0x0007);
3095         rtl_writephy(tp, 0x1e, 0x002d);
3096         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3097         rtl_writephy(tp, 0x1f, 0x0000);
3098         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3099
3100         rtl_writephy(tp, 0x1f, 0x0005);
3101         rtl_writephy(tp, 0x05, 0x8b86);
3102         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3103         rtl_writephy(tp, 0x1f, 0x0000);
3104
3105         rtl_writephy(tp, 0x1f, 0x0005);
3106         rtl_writephy(tp, 0x05, 0x8b85);
3107         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3108         rtl_writephy(tp, 0x1f, 0x0007);
3109         rtl_writephy(tp, 0x1e, 0x0020);
3110         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3111         rtl_writephy(tp, 0x1f, 0x0006);
3112         rtl_writephy(tp, 0x00, 0x5a00);
3113         rtl_writephy(tp, 0x1f, 0x0000);
3114         rtl_writephy(tp, 0x0d, 0x0007);
3115         rtl_writephy(tp, 0x0e, 0x003c);
3116         rtl_writephy(tp, 0x0d, 0x4007);
3117         rtl_writephy(tp, 0x0e, 0x0000);
3118         rtl_writephy(tp, 0x0d, 0x0000);
3119 }
3120
3121 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3122 {
3123         const u16 w[] = {
3124                 addr[0] | (addr[1] << 8),
3125                 addr[2] | (addr[3] << 8),
3126                 addr[4] | (addr[5] << 8)
3127         };
3128         const struct exgmac_reg e[] = {
3129                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3130                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3131                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3132                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3133         };
3134
3135         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3136 }
3137
3138 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3139 {
3140         static const struct phy_reg phy_reg_init[] = {
3141                 /* Enable Delay cap */
3142                 { 0x1f, 0x0004 },
3143                 { 0x1f, 0x0007 },
3144                 { 0x1e, 0x00ac },
3145                 { 0x18, 0x0006 },
3146                 { 0x1f, 0x0002 },
3147                 { 0x1f, 0x0000 },
3148                 { 0x1f, 0x0000 },
3149
3150                 /* Channel estimation fine tune */
3151                 { 0x1f, 0x0003 },
3152                 { 0x09, 0xa20f },
3153                 { 0x1f, 0x0000 },
3154                 { 0x1f, 0x0000 },
3155
3156                 /* Green Setting */
3157                 { 0x1f, 0x0005 },
3158                 { 0x05, 0x8b5b },
3159                 { 0x06, 0x9222 },
3160                 { 0x05, 0x8b6d },
3161                 { 0x06, 0x8000 },
3162                 { 0x05, 0x8b76 },
3163                 { 0x06, 0x8000 },
3164                 { 0x1f, 0x0000 }
3165         };
3166
3167         rtl_apply_firmware(tp);
3168
3169         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3170
3171         /* For 4-corner performance improve */
3172         rtl_writephy(tp, 0x1f, 0x0005);
3173         rtl_writephy(tp, 0x05, 0x8b80);
3174         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3175         rtl_writephy(tp, 0x1f, 0x0000);
3176
3177         /* PHY auto speed down */
3178         rtl_writephy(tp, 0x1f, 0x0004);
3179         rtl_writephy(tp, 0x1f, 0x0007);
3180         rtl_writephy(tp, 0x1e, 0x002d);
3181         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3182         rtl_writephy(tp, 0x1f, 0x0002);
3183         rtl_writephy(tp, 0x1f, 0x0000);
3184         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3185
3186         /* improve 10M EEE waveform */
3187         rtl_writephy(tp, 0x1f, 0x0005);
3188         rtl_writephy(tp, 0x05, 0x8b86);
3189         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3190         rtl_writephy(tp, 0x1f, 0x0000);
3191
3192         /* Improve 2-pair detection performance */
3193         rtl_writephy(tp, 0x1f, 0x0005);
3194         rtl_writephy(tp, 0x05, 0x8b85);
3195         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3196         rtl_writephy(tp, 0x1f, 0x0000);
3197
3198         /* EEE setting */
3199         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3200         rtl_writephy(tp, 0x1f, 0x0005);
3201         rtl_writephy(tp, 0x05, 0x8b85);
3202         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3203         rtl_writephy(tp, 0x1f, 0x0004);
3204      &n