c28bc318cec63ecd8878e1d88de2ae38bcbbb428
[~shefty/rdma-dev.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
38
39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8168G_1        "rtl_nic/rtl8168g-1.fw"
51
52 #ifdef RTL8169_DEBUG
53 #define assert(expr) \
54         if (!(expr)) {                                  \
55                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
56                 #expr,__FILE__,__func__,__LINE__);              \
57         }
58 #define dprintk(fmt, args...) \
59         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
60 #else
61 #define assert(expr) do {} while (0)
62 #define dprintk(fmt, args...)   do {} while (0)
63 #endif /* RTL8169_DEBUG */
64
65 #define R8169_MSG_DEFAULT \
66         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
67
68 #define TX_SLOTS_AVAIL(tp) \
69         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
73         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
74
75 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
77 static const int multicast_filter_limit = 32;
78
79 #define MAX_READ_REQUEST_SHIFT  12
80 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
81 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
82
83 #define R8169_REGS_SIZE         256
84 #define R8169_NAPI_WEIGHT       64
85 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
86 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
87 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
88 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
89
90 #define RTL8169_TX_TIMEOUT      (6*HZ)
91 #define RTL8169_PHY_TIMEOUT     (10*HZ)
92
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg)             readb (ioaddr + (reg))
98 #define RTL_R16(reg)            readw (ioaddr + (reg))
99 #define RTL_R32(reg)            readl (ioaddr + (reg))
100
101 enum mac_version {
102         RTL_GIGA_MAC_VER_01 = 0,
103         RTL_GIGA_MAC_VER_02,
104         RTL_GIGA_MAC_VER_03,
105         RTL_GIGA_MAC_VER_04,
106         RTL_GIGA_MAC_VER_05,
107         RTL_GIGA_MAC_VER_06,
108         RTL_GIGA_MAC_VER_07,
109         RTL_GIGA_MAC_VER_08,
110         RTL_GIGA_MAC_VER_09,
111         RTL_GIGA_MAC_VER_10,
112         RTL_GIGA_MAC_VER_11,
113         RTL_GIGA_MAC_VER_12,
114         RTL_GIGA_MAC_VER_13,
115         RTL_GIGA_MAC_VER_14,
116         RTL_GIGA_MAC_VER_15,
117         RTL_GIGA_MAC_VER_16,
118         RTL_GIGA_MAC_VER_17,
119         RTL_GIGA_MAC_VER_18,
120         RTL_GIGA_MAC_VER_19,
121         RTL_GIGA_MAC_VER_20,
122         RTL_GIGA_MAC_VER_21,
123         RTL_GIGA_MAC_VER_22,
124         RTL_GIGA_MAC_VER_23,
125         RTL_GIGA_MAC_VER_24,
126         RTL_GIGA_MAC_VER_25,
127         RTL_GIGA_MAC_VER_26,
128         RTL_GIGA_MAC_VER_27,
129         RTL_GIGA_MAC_VER_28,
130         RTL_GIGA_MAC_VER_29,
131         RTL_GIGA_MAC_VER_30,
132         RTL_GIGA_MAC_VER_31,
133         RTL_GIGA_MAC_VER_32,
134         RTL_GIGA_MAC_VER_33,
135         RTL_GIGA_MAC_VER_34,
136         RTL_GIGA_MAC_VER_35,
137         RTL_GIGA_MAC_VER_36,
138         RTL_GIGA_MAC_VER_37,
139         RTL_GIGA_MAC_VER_38,
140         RTL_GIGA_MAC_VER_39,
141         RTL_GIGA_MAC_VER_40,
142         RTL_GIGA_MAC_VER_41,
143         RTL_GIGA_MAC_NONE   = 0xff,
144 };
145
146 enum rtl_tx_desc_version {
147         RTL_TD_0        = 0,
148         RTL_TD_1        = 1,
149 };
150
151 #define JUMBO_1K        ETH_DATA_LEN
152 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
153 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
154 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
155 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
156
157 #define _R(NAME,TD,FW,SZ,B) {   \
158         .name = NAME,           \
159         .txd_version = TD,      \
160         .fw_name = FW,          \
161         .jumbo_max = SZ,        \
162         .jumbo_tx_csum = B      \
163 }
164
165 static const struct {
166         const char *name;
167         enum rtl_tx_desc_version txd_version;
168         const char *fw_name;
169         u16 jumbo_max;
170         bool jumbo_tx_csum;
171 } rtl_chip_infos[] = {
172         /* PCI devices. */
173         [RTL_GIGA_MAC_VER_01] =
174                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
175         [RTL_GIGA_MAC_VER_02] =
176                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
177         [RTL_GIGA_MAC_VER_03] =
178                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
179         [RTL_GIGA_MAC_VER_04] =
180                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
181         [RTL_GIGA_MAC_VER_05] =
182                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
183         [RTL_GIGA_MAC_VER_06] =
184                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
185         /* PCI-E devices. */
186         [RTL_GIGA_MAC_VER_07] =
187                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
188         [RTL_GIGA_MAC_VER_08] =
189                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
190         [RTL_GIGA_MAC_VER_09] =
191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
192         [RTL_GIGA_MAC_VER_10] =
193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
194         [RTL_GIGA_MAC_VER_11] =
195                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
196         [RTL_GIGA_MAC_VER_12] =
197                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
198         [RTL_GIGA_MAC_VER_13] =
199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
200         [RTL_GIGA_MAC_VER_14] =
201                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
202         [RTL_GIGA_MAC_VER_15] =
203                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
204         [RTL_GIGA_MAC_VER_16] =
205                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
206         [RTL_GIGA_MAC_VER_17] =
207                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
208         [RTL_GIGA_MAC_VER_18] =
209                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
210         [RTL_GIGA_MAC_VER_19] =
211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
212         [RTL_GIGA_MAC_VER_20] =
213                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
214         [RTL_GIGA_MAC_VER_21] =
215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
216         [RTL_GIGA_MAC_VER_22] =
217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
218         [RTL_GIGA_MAC_VER_23] =
219                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
220         [RTL_GIGA_MAC_VER_24] =
221                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
222         [RTL_GIGA_MAC_VER_25] =
223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
224                                                         JUMBO_9K, false),
225         [RTL_GIGA_MAC_VER_26] =
226                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
227                                                         JUMBO_9K, false),
228         [RTL_GIGA_MAC_VER_27] =
229                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
230         [RTL_GIGA_MAC_VER_28] =
231                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
232         [RTL_GIGA_MAC_VER_29] =
233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
234                                                         JUMBO_1K, true),
235         [RTL_GIGA_MAC_VER_30] =
236                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
237                                                         JUMBO_1K, true),
238         [RTL_GIGA_MAC_VER_31] =
239                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
240         [RTL_GIGA_MAC_VER_32] =
241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
242                                                         JUMBO_9K, false),
243         [RTL_GIGA_MAC_VER_33] =
244                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
245                                                         JUMBO_9K, false),
246         [RTL_GIGA_MAC_VER_34] =
247                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
248                                                         JUMBO_9K, false),
249         [RTL_GIGA_MAC_VER_35] =
250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
251                                                         JUMBO_9K, false),
252         [RTL_GIGA_MAC_VER_36] =
253                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
254                                                         JUMBO_9K, false),
255         [RTL_GIGA_MAC_VER_37] =
256                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
257                                                         JUMBO_1K, true),
258         [RTL_GIGA_MAC_VER_38] =
259                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
260                                                         JUMBO_9K, false),
261         [RTL_GIGA_MAC_VER_39] =
262                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
263                                                         JUMBO_1K, true),
264         [RTL_GIGA_MAC_VER_40] =
265                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_1,
266                                                         JUMBO_9K, false),
267         [RTL_GIGA_MAC_VER_41] =
268                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
269 };
270 #undef _R
271
272 enum cfg_version {
273         RTL_CFG_0 = 0x00,
274         RTL_CFG_1,
275         RTL_CFG_2
276 };
277
278 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
279         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
280         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
281         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
282         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
283         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
284         { PCI_VENDOR_ID_DLINK,                  0x4300,
285                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
286         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
287         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
288         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
289         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
290         { PCI_VENDOR_ID_LINKSYS,                0x1032,
291                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
292         { 0x0001,                               0x8168,
293                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
294         {0,},
295 };
296
297 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
298
299 static int rx_buf_sz = 16383;
300 static int use_dac;
301 static struct {
302         u32 msg_enable;
303 } debug = { -1 };
304
305 enum rtl_registers {
306         MAC0            = 0,    /* Ethernet hardware address. */
307         MAC4            = 4,
308         MAR0            = 8,    /* Multicast filter. */
309         CounterAddrLow          = 0x10,
310         CounterAddrHigh         = 0x14,
311         TxDescStartAddrLow      = 0x20,
312         TxDescStartAddrHigh     = 0x24,
313         TxHDescStartAddrLow     = 0x28,
314         TxHDescStartAddrHigh    = 0x2c,
315         FLASH           = 0x30,
316         ERSR            = 0x36,
317         ChipCmd         = 0x37,
318         TxPoll          = 0x38,
319         IntrMask        = 0x3c,
320         IntrStatus      = 0x3e,
321
322         TxConfig        = 0x40,
323 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
324 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
325
326         RxConfig        = 0x44,
327 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
328 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
329 #define RXCFG_FIFO_SHIFT                13
330                                         /* No threshold before first PCI xfer */
331 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
332 #define RXCFG_DMA_SHIFT                 8
333                                         /* Unlimited maximum PCI burst. */
334 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
335
336         RxMissed        = 0x4c,
337         Cfg9346         = 0x50,
338         Config0         = 0x51,
339         Config1         = 0x52,
340         Config2         = 0x53,
341 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
342
343         Config3         = 0x54,
344         Config4         = 0x55,
345         Config5         = 0x56,
346         MultiIntr       = 0x5c,
347         PHYAR           = 0x60,
348         PHYstatus       = 0x6c,
349         RxMaxSize       = 0xda,
350         CPlusCmd        = 0xe0,
351         IntrMitigate    = 0xe2,
352         RxDescAddrLow   = 0xe4,
353         RxDescAddrHigh  = 0xe8,
354         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
355
356 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
357
358         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
359
360 #define TxPacketMax     (8064 >> 7)
361 #define EarlySize       0x27
362
363         FuncEvent       = 0xf0,
364         FuncEventMask   = 0xf4,
365         FuncPresetState = 0xf8,
366         FuncForceEvent  = 0xfc,
367 };
368
369 enum rtl8110_registers {
370         TBICSR                  = 0x64,
371         TBI_ANAR                = 0x68,
372         TBI_LPAR                = 0x6a,
373 };
374
375 enum rtl8168_8101_registers {
376         CSIDR                   = 0x64,
377         CSIAR                   = 0x68,
378 #define CSIAR_FLAG                      0x80000000
379 #define CSIAR_WRITE_CMD                 0x80000000
380 #define CSIAR_BYTE_ENABLE               0x0f
381 #define CSIAR_BYTE_ENABLE_SHIFT         12
382 #define CSIAR_ADDR_MASK                 0x0fff
383 #define CSIAR_FUNC_CARD                 0x00000000
384 #define CSIAR_FUNC_SDIO                 0x00010000
385 #define CSIAR_FUNC_NIC                  0x00020000
386         PMCH                    = 0x6f,
387         EPHYAR                  = 0x80,
388 #define EPHYAR_FLAG                     0x80000000
389 #define EPHYAR_WRITE_CMD                0x80000000
390 #define EPHYAR_REG_MASK                 0x1f
391 #define EPHYAR_REG_SHIFT                16
392 #define EPHYAR_DATA_MASK                0xffff
393         DLLPR                   = 0xd0,
394 #define PFM_EN                          (1 << 6)
395         DBG_REG                 = 0xd1,
396 #define FIX_NAK_1                       (1 << 4)
397 #define FIX_NAK_2                       (1 << 3)
398         TWSI                    = 0xd2,
399         MCU                     = 0xd3,
400 #define NOW_IS_OOB                      (1 << 7)
401 #define TX_EMPTY                        (1 << 5)
402 #define RX_EMPTY                        (1 << 4)
403 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
404 #define EN_NDP                          (1 << 3)
405 #define EN_OOB_RESET                    (1 << 2)
406 #define LINK_LIST_RDY                   (1 << 1)
407         EFUSEAR                 = 0xdc,
408 #define EFUSEAR_FLAG                    0x80000000
409 #define EFUSEAR_WRITE_CMD               0x80000000
410 #define EFUSEAR_READ_CMD                0x00000000
411 #define EFUSEAR_REG_MASK                0x03ff
412 #define EFUSEAR_REG_SHIFT               8
413 #define EFUSEAR_DATA_MASK               0xff
414 };
415
416 enum rtl8168_registers {
417         LED_FREQ                = 0x1a,
418         EEE_LED                 = 0x1b,
419         ERIDR                   = 0x70,
420         ERIAR                   = 0x74,
421 #define ERIAR_FLAG                      0x80000000
422 #define ERIAR_WRITE_CMD                 0x80000000
423 #define ERIAR_READ_CMD                  0x00000000
424 #define ERIAR_ADDR_BYTE_ALIGN           4
425 #define ERIAR_TYPE_SHIFT                16
426 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
427 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
428 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
429 #define ERIAR_MASK_SHIFT                12
430 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
431 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
432 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
433 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
434         EPHY_RXER_NUM           = 0x7c,
435         OCPDR                   = 0xb0, /* OCP GPHY access */
436 #define OCPDR_WRITE_CMD                 0x80000000
437 #define OCPDR_READ_CMD                  0x00000000
438 #define OCPDR_REG_MASK                  0x7f
439 #define OCPDR_GPHY_REG_SHIFT            16
440 #define OCPDR_DATA_MASK                 0xffff
441         OCPAR                   = 0xb4,
442 #define OCPAR_FLAG                      0x80000000
443 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
444 #define OCPAR_GPHY_READ_CMD             0x0000f060
445         GPHY_OCP                = 0xb8,
446         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
447         MISC                    = 0xf0, /* 8168e only. */
448 #define TXPLA_RST                       (1 << 29)
449 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
450 #define PWM_EN                          (1 << 22)
451 #define RXDV_GATED_EN                   (1 << 19)
452 #define EARLY_TALLY_EN                  (1 << 16)
453 #define FORCE_CLK                       (1 << 15) /* force clock request */
454 };
455
456 enum rtl_register_content {
457         /* InterruptStatusBits */
458         SYSErr          = 0x8000,
459         PCSTimeout      = 0x4000,
460         SWInt           = 0x0100,
461         TxDescUnavail   = 0x0080,
462         RxFIFOOver      = 0x0040,
463         LinkChg         = 0x0020,
464         RxOverflow      = 0x0010,
465         TxErr           = 0x0008,
466         TxOK            = 0x0004,
467         RxErr           = 0x0002,
468         RxOK            = 0x0001,
469
470         /* RxStatusDesc */
471         RxBOVF  = (1 << 24),
472         RxFOVF  = (1 << 23),
473         RxRWT   = (1 << 22),
474         RxRES   = (1 << 21),
475         RxRUNT  = (1 << 20),
476         RxCRC   = (1 << 19),
477
478         /* ChipCmdBits */
479         StopReq         = 0x80,
480         CmdReset        = 0x10,
481         CmdRxEnb        = 0x08,
482         CmdTxEnb        = 0x04,
483         RxBufEmpty      = 0x01,
484
485         /* TXPoll register p.5 */
486         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
487         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
488         FSWInt          = 0x01,         /* Forced software interrupt */
489
490         /* Cfg9346Bits */
491         Cfg9346_Lock    = 0x00,
492         Cfg9346_Unlock  = 0xc0,
493
494         /* rx_mode_bits */
495         AcceptErr       = 0x20,
496         AcceptRunt      = 0x10,
497         AcceptBroadcast = 0x08,
498         AcceptMulticast = 0x04,
499         AcceptMyPhys    = 0x02,
500         AcceptAllPhys   = 0x01,
501 #define RX_CONFIG_ACCEPT_MASK           0x3f
502
503         /* TxConfigBits */
504         TxInterFrameGapShift = 24,
505         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
506
507         /* Config1 register p.24 */
508         LEDS1           = (1 << 7),
509         LEDS0           = (1 << 6),
510         Speed_down      = (1 << 4),
511         MEMMAP          = (1 << 3),
512         IOMAP           = (1 << 2),
513         VPD             = (1 << 1),
514         PMEnable        = (1 << 0),     /* Power Management Enable */
515
516         /* Config2 register p. 25 */
517         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
518         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
519         PCI_Clock_66MHz = 0x01,
520         PCI_Clock_33MHz = 0x00,
521
522         /* Config3 register p.25 */
523         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
524         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
525         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
526         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
527
528         /* Config4 register */
529         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
530
531         /* Config5 register p.27 */
532         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
533         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
534         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
535         Spi_en          = (1 << 3),
536         LanWake         = (1 << 1),     /* LanWake enable/disable */
537         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
538         ASPM_en         = (1 << 0),     /* ASPM enable */
539
540         /* TBICSR p.28 */
541         TBIReset        = 0x80000000,
542         TBILoopback     = 0x40000000,
543         TBINwEnable     = 0x20000000,
544         TBINwRestart    = 0x10000000,
545         TBILinkOk       = 0x02000000,
546         TBINwComplete   = 0x01000000,
547
548         /* CPlusCmd p.31 */
549         EnableBist      = (1 << 15),    // 8168 8101
550         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
551         Normal_mode     = (1 << 13),    // unused
552         Force_half_dup  = (1 << 12),    // 8168 8101
553         Force_rxflow_en = (1 << 11),    // 8168 8101
554         Force_txflow_en = (1 << 10),    // 8168 8101
555         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
556         ASF             = (1 << 8),     // 8168 8101
557         PktCntrDisable  = (1 << 7),     // 8168 8101
558         Mac_dbgo_sel    = 0x001c,       // 8168
559         RxVlan          = (1 << 6),
560         RxChkSum        = (1 << 5),
561         PCIDAC          = (1 << 4),
562         PCIMulRW        = (1 << 3),
563         INTT_0          = 0x0000,       // 8168
564         INTT_1          = 0x0001,       // 8168
565         INTT_2          = 0x0002,       // 8168
566         INTT_3          = 0x0003,       // 8168
567
568         /* rtl8169_PHYstatus */
569         TBI_Enable      = 0x80,
570         TxFlowCtrl      = 0x40,
571         RxFlowCtrl      = 0x20,
572         _1000bpsF       = 0x10,
573         _100bps         = 0x08,
574         _10bps          = 0x04,
575         LinkStatus      = 0x02,
576         FullDup         = 0x01,
577
578         /* _TBICSRBit */
579         TBILinkOK       = 0x02000000,
580
581         /* DumpCounterCommand */
582         CounterDump     = 0x8,
583 };
584
585 enum rtl_desc_bit {
586         /* First doubleword. */
587         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
588         RingEnd         = (1 << 30), /* End of descriptor ring */
589         FirstFrag       = (1 << 29), /* First segment of a packet */
590         LastFrag        = (1 << 28), /* Final segment of a packet */
591 };
592
593 /* Generic case. */
594 enum rtl_tx_desc_bit {
595         /* First doubleword. */
596         TD_LSO          = (1 << 27),            /* Large Send Offload */
597 #define TD_MSS_MAX                      0x07ffu /* MSS value */
598
599         /* Second doubleword. */
600         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
601 };
602
603 /* 8169, 8168b and 810x except 8102e. */
604 enum rtl_tx_desc_bit_0 {
605         /* First doubleword. */
606 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
607         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
608         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
609         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
610 };
611
612 /* 8102e, 8168c and beyond. */
613 enum rtl_tx_desc_bit_1 {
614         /* Second doubleword. */
615 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
616         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
617         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
618         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
619 };
620
621 static const struct rtl_tx_desc_info {
622         struct {
623                 u32 udp;
624                 u32 tcp;
625         } checksum;
626         u16 mss_shift;
627         u16 opts_offset;
628 } tx_desc_info [] = {
629         [RTL_TD_0] = {
630                 .checksum = {
631                         .udp    = TD0_IP_CS | TD0_UDP_CS,
632                         .tcp    = TD0_IP_CS | TD0_TCP_CS
633                 },
634                 .mss_shift      = TD0_MSS_SHIFT,
635                 .opts_offset    = 0
636         },
637         [RTL_TD_1] = {
638                 .checksum = {
639                         .udp    = TD1_IP_CS | TD1_UDP_CS,
640                         .tcp    = TD1_IP_CS | TD1_TCP_CS
641                 },
642                 .mss_shift      = TD1_MSS_SHIFT,
643                 .opts_offset    = 1
644         }
645 };
646
647 enum rtl_rx_desc_bit {
648         /* Rx private */
649         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
650         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
651
652 #define RxProtoUDP      (PID1)
653 #define RxProtoTCP      (PID0)
654 #define RxProtoIP       (PID1 | PID0)
655 #define RxProtoMask     RxProtoIP
656
657         IPFail          = (1 << 16), /* IP checksum failed */
658         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
659         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
660         RxVlanTag       = (1 << 16), /* VLAN tag available */
661 };
662
663 #define RsvdMask        0x3fffc000
664
665 struct TxDesc {
666         __le32 opts1;
667         __le32 opts2;
668         __le64 addr;
669 };
670
671 struct RxDesc {
672         __le32 opts1;
673         __le32 opts2;
674         __le64 addr;
675 };
676
677 struct ring_info {
678         struct sk_buff  *skb;
679         u32             len;
680         u8              __pad[sizeof(void *) - sizeof(u32)];
681 };
682
683 enum features {
684         RTL_FEATURE_WOL         = (1 << 0),
685         RTL_FEATURE_MSI         = (1 << 1),
686         RTL_FEATURE_GMII        = (1 << 2),
687         RTL_FEATURE_FW_LOADED   = (1 << 3),
688 };
689
690 struct rtl8169_counters {
691         __le64  tx_packets;
692         __le64  rx_packets;
693         __le64  tx_errors;
694         __le32  rx_errors;
695         __le16  rx_missed;
696         __le16  align_errors;
697         __le32  tx_one_collision;
698         __le32  tx_multi_collision;
699         __le64  rx_unicast;
700         __le64  rx_broadcast;
701         __le32  rx_multicast;
702         __le16  tx_aborted;
703         __le16  tx_underun;
704 };
705
706 enum rtl_flag {
707         RTL_FLAG_TASK_ENABLED,
708         RTL_FLAG_TASK_SLOW_PENDING,
709         RTL_FLAG_TASK_RESET_PENDING,
710         RTL_FLAG_TASK_PHY_PENDING,
711         RTL_FLAG_MAX
712 };
713
714 struct rtl8169_stats {
715         u64                     packets;
716         u64                     bytes;
717         struct u64_stats_sync   syncp;
718 };
719
720 struct rtl8169_private {
721         void __iomem *mmio_addr;        /* memory map physical address */
722         struct pci_dev *pci_dev;
723         struct net_device *dev;
724         struct napi_struct napi;
725         u32 msg_enable;
726         u16 txd_version;
727         u16 mac_version;
728         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
729         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
730         u32 dirty_rx;
731         u32 dirty_tx;
732         struct rtl8169_stats rx_stats;
733         struct rtl8169_stats tx_stats;
734         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
735         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
736         dma_addr_t TxPhyAddr;
737         dma_addr_t RxPhyAddr;
738         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
739         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
740         struct timer_list timer;
741         u16 cp_cmd;
742
743         u16 event_slow;
744
745         struct mdio_ops {
746                 void (*write)(struct rtl8169_private *, int, int);
747                 int (*read)(struct rtl8169_private *, int);
748         } mdio_ops;
749
750         struct pll_power_ops {
751                 void (*down)(struct rtl8169_private *);
752                 void (*up)(struct rtl8169_private *);
753         } pll_power_ops;
754
755         struct jumbo_ops {
756                 void (*enable)(struct rtl8169_private *);
757                 void (*disable)(struct rtl8169_private *);
758         } jumbo_ops;
759
760         struct csi_ops {
761                 void (*write)(struct rtl8169_private *, int, int);
762                 u32 (*read)(struct rtl8169_private *, int);
763         } csi_ops;
764
765         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
766         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
767         void (*phy_reset_enable)(struct rtl8169_private *tp);
768         void (*hw_start)(struct net_device *);
769         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
770         unsigned int (*link_ok)(void __iomem *);
771         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
772
773         struct {
774                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
775                 struct mutex mutex;
776                 struct work_struct work;
777         } wk;
778
779         unsigned features;
780
781         struct mii_if_info mii;
782         struct rtl8169_counters counters;
783         u32 saved_wolopts;
784         u32 opts1_mask;
785
786         struct rtl_fw {
787                 const struct firmware *fw;
788
789 #define RTL_VER_SIZE            32
790
791                 char version[RTL_VER_SIZE];
792
793                 struct rtl_fw_phy_action {
794                         __le32 *code;
795                         size_t size;
796                 } phy_action;
797         } *rtl_fw;
798 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
799
800         u32 ocp_base;
801 };
802
803 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
804 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
805 module_param(use_dac, int, 0);
806 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
807 module_param_named(debug, debug.msg_enable, int, 0);
808 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
809 MODULE_LICENSE("GPL");
810 MODULE_VERSION(RTL8169_VERSION);
811 MODULE_FIRMWARE(FIRMWARE_8168D_1);
812 MODULE_FIRMWARE(FIRMWARE_8168D_2);
813 MODULE_FIRMWARE(FIRMWARE_8168E_1);
814 MODULE_FIRMWARE(FIRMWARE_8168E_2);
815 MODULE_FIRMWARE(FIRMWARE_8168E_3);
816 MODULE_FIRMWARE(FIRMWARE_8105E_1);
817 MODULE_FIRMWARE(FIRMWARE_8168F_1);
818 MODULE_FIRMWARE(FIRMWARE_8168F_2);
819 MODULE_FIRMWARE(FIRMWARE_8402_1);
820 MODULE_FIRMWARE(FIRMWARE_8411_1);
821 MODULE_FIRMWARE(FIRMWARE_8106E_1);
822 MODULE_FIRMWARE(FIRMWARE_8168G_1);
823
824 static void rtl_lock_work(struct rtl8169_private *tp)
825 {
826         mutex_lock(&tp->wk.mutex);
827 }
828
829 static void rtl_unlock_work(struct rtl8169_private *tp)
830 {
831         mutex_unlock(&tp->wk.mutex);
832 }
833
834 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
835 {
836         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
837                                            PCI_EXP_DEVCTL_READRQ, force);
838 }
839
840 struct rtl_cond {
841         bool (*check)(struct rtl8169_private *);
842         const char *msg;
843 };
844
845 static void rtl_udelay(unsigned int d)
846 {
847         udelay(d);
848 }
849
850 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
851                           void (*delay)(unsigned int), unsigned int d, int n,
852                           bool high)
853 {
854         int i;
855
856         for (i = 0; i < n; i++) {
857                 delay(d);
858                 if (c->check(tp) == high)
859                         return true;
860         }
861         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
862                   c->msg, !high, n, d);
863         return false;
864 }
865
866 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
867                                       const struct rtl_cond *c,
868                                       unsigned int d, int n)
869 {
870         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
871 }
872
873 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
874                                      const struct rtl_cond *c,
875                                      unsigned int d, int n)
876 {
877         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
878 }
879
880 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
881                                       const struct rtl_cond *c,
882                                       unsigned int d, int n)
883 {
884         return rtl_loop_wait(tp, c, msleep, d, n, true);
885 }
886
887 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
888                                      const struct rtl_cond *c,
889                                      unsigned int d, int n)
890 {
891         return rtl_loop_wait(tp, c, msleep, d, n, false);
892 }
893
894 #define DECLARE_RTL_COND(name)                          \
895 static bool name ## _check(struct rtl8169_private *);   \
896                                                         \
897 static const struct rtl_cond name = {                   \
898         .check  = name ## _check,                       \
899         .msg    = #name                                 \
900 };                                                      \
901                                                         \
902 static bool name ## _check(struct rtl8169_private *tp)
903
904 DECLARE_RTL_COND(rtl_ocpar_cond)
905 {
906         void __iomem *ioaddr = tp->mmio_addr;
907
908         return RTL_R32(OCPAR) & OCPAR_FLAG;
909 }
910
911 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
912 {
913         void __iomem *ioaddr = tp->mmio_addr;
914
915         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
916
917         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
918                 RTL_R32(OCPDR) : ~0;
919 }
920
921 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
922 {
923         void __iomem *ioaddr = tp->mmio_addr;
924
925         RTL_W32(OCPDR, data);
926         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
927
928         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
929 }
930
931 DECLARE_RTL_COND(rtl_eriar_cond)
932 {
933         void __iomem *ioaddr = tp->mmio_addr;
934
935         return RTL_R32(ERIAR) & ERIAR_FLAG;
936 }
937
938 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
939 {
940         void __iomem *ioaddr = tp->mmio_addr;
941
942         RTL_W8(ERIDR, cmd);
943         RTL_W32(ERIAR, 0x800010e8);
944         msleep(2);
945
946         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
947                 return;
948
949         ocp_write(tp, 0x1, 0x30, 0x00000001);
950 }
951
952 #define OOB_CMD_RESET           0x00
953 #define OOB_CMD_DRIVER_START    0x05
954 #define OOB_CMD_DRIVER_STOP     0x06
955
956 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
957 {
958         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
959 }
960
961 DECLARE_RTL_COND(rtl_ocp_read_cond)
962 {
963         u16 reg;
964
965         reg = rtl8168_get_ocp_reg(tp);
966
967         return ocp_read(tp, 0x0f, reg) & 0x00000800;
968 }
969
970 static void rtl8168_driver_start(struct rtl8169_private *tp)
971 {
972         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
973
974         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
975 }
976
977 static void rtl8168_driver_stop(struct rtl8169_private *tp)
978 {
979         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
980
981         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
982 }
983
984 static int r8168dp_check_dash(struct rtl8169_private *tp)
985 {
986         u16 reg = rtl8168_get_ocp_reg(tp);
987
988         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
989 }
990
991 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
992 {
993         if (reg & 0xffff0001) {
994                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
995                 return true;
996         }
997         return false;
998 }
999
1000 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1001 {
1002         void __iomem *ioaddr = tp->mmio_addr;
1003
1004         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1005 }
1006
1007 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1008 {
1009         void __iomem *ioaddr = tp->mmio_addr;
1010
1011         if (rtl_ocp_reg_failure(tp, reg))
1012                 return;
1013
1014         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1015
1016         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1017 }
1018
1019 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1020 {
1021         void __iomem *ioaddr = tp->mmio_addr;
1022
1023         if (rtl_ocp_reg_failure(tp, reg))
1024                 return 0;
1025
1026         RTL_W32(GPHY_OCP, reg << 15);
1027
1028         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1029                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1030 }
1031
1032 static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1033 {
1034         int val;
1035
1036         val = r8168_phy_ocp_read(tp, reg);
1037         r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1038 }
1039
1040 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1041 {
1042         void __iomem *ioaddr = tp->mmio_addr;
1043
1044         if (rtl_ocp_reg_failure(tp, reg))
1045                 return;
1046
1047         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1048 }
1049
1050 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1051 {
1052         void __iomem *ioaddr = tp->mmio_addr;
1053
1054         if (rtl_ocp_reg_failure(tp, reg))
1055                 return 0;
1056
1057         RTL_W32(OCPDR, reg << 15);
1058
1059         return RTL_R32(OCPDR);
1060 }
1061
1062 #define OCP_STD_PHY_BASE        0xa400
1063
1064 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065 {
1066         if (reg == 0x1f) {
1067                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1068                 return;
1069         }
1070
1071         if (tp->ocp_base != OCP_STD_PHY_BASE)
1072                 reg -= 0x10;
1073
1074         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1075 }
1076
1077 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1078 {
1079         if (tp->ocp_base != OCP_STD_PHY_BASE)
1080                 reg -= 0x10;
1081
1082         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1083 }
1084
1085 DECLARE_RTL_COND(rtl_phyar_cond)
1086 {
1087         void __iomem *ioaddr = tp->mmio_addr;
1088
1089         return RTL_R32(PHYAR) & 0x80000000;
1090 }
1091
1092 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1093 {
1094         void __iomem *ioaddr = tp->mmio_addr;
1095
1096         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1097
1098         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1099         /*
1100          * According to hardware specs a 20us delay is required after write
1101          * complete indication, but before sending next command.
1102          */
1103         udelay(20);
1104 }
1105
1106 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1107 {
1108         void __iomem *ioaddr = tp->mmio_addr;
1109         int value;
1110
1111         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1112
1113         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1114                 RTL_R32(PHYAR) & 0xffff : ~0;
1115
1116         /*
1117          * According to hardware specs a 20us delay is required after read
1118          * complete indication, but before sending next command.
1119          */
1120         udelay(20);
1121
1122         return value;
1123 }
1124
1125 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1126 {
1127         void __iomem *ioaddr = tp->mmio_addr;
1128
1129         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1130         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1131         RTL_W32(EPHY_RXER_NUM, 0);
1132
1133         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1134 }
1135
1136 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1137 {
1138         r8168dp_1_mdio_access(tp, reg,
1139                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1140 }
1141
1142 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1143 {
1144         void __iomem *ioaddr = tp->mmio_addr;
1145
1146         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1147
1148         mdelay(1);
1149         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1150         RTL_W32(EPHY_RXER_NUM, 0);
1151
1152         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1153                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1154 }
1155
1156 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1157
1158 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1159 {
1160         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1161 }
1162
1163 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1164 {
1165         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1166 }
1167
1168 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1169 {
1170         void __iomem *ioaddr = tp->mmio_addr;
1171
1172         r8168dp_2_mdio_start(ioaddr);
1173
1174         r8169_mdio_write(tp, reg, value);
1175
1176         r8168dp_2_mdio_stop(ioaddr);
1177 }
1178
1179 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1180 {
1181         void __iomem *ioaddr = tp->mmio_addr;
1182         int value;
1183
1184         r8168dp_2_mdio_start(ioaddr);
1185
1186         value = r8169_mdio_read(tp, reg);
1187
1188         r8168dp_2_mdio_stop(ioaddr);
1189
1190         return value;
1191 }
1192
1193 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1194 {
1195         tp->mdio_ops.write(tp, location, val);
1196 }
1197
1198 static int rtl_readphy(struct rtl8169_private *tp, int location)
1199 {
1200         return tp->mdio_ops.read(tp, location);
1201 }
1202
1203 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1204 {
1205         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1206 }
1207
1208 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1209 {
1210         int val;
1211
1212         val = rtl_readphy(tp, reg_addr);
1213         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1214 }
1215
1216 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1217                            int val)
1218 {
1219         struct rtl8169_private *tp = netdev_priv(dev);
1220
1221         rtl_writephy(tp, location, val);
1222 }
1223
1224 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1225 {
1226         struct rtl8169_private *tp = netdev_priv(dev);
1227
1228         return rtl_readphy(tp, location);
1229 }
1230
1231 DECLARE_RTL_COND(rtl_ephyar_cond)
1232 {
1233         void __iomem *ioaddr = tp->mmio_addr;
1234
1235         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1236 }
1237
1238 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1239 {
1240         void __iomem *ioaddr = tp->mmio_addr;
1241
1242         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1243                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1244
1245         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1246
1247         udelay(10);
1248 }
1249
1250 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1251 {
1252         void __iomem *ioaddr = tp->mmio_addr;
1253
1254         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1255
1256         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1257                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1258 }
1259
1260 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1261                           u32 val, int type)
1262 {
1263         void __iomem *ioaddr = tp->mmio_addr;
1264
1265         BUG_ON((addr & 3) || (mask == 0));
1266         RTL_W32(ERIDR, val);
1267         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1268
1269         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1270 }
1271
1272 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1273 {
1274         void __iomem *ioaddr = tp->mmio_addr;
1275
1276         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1277
1278         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1279                 RTL_R32(ERIDR) : ~0;
1280 }
1281
1282 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1283                          u32 m, int type)
1284 {
1285         u32 val;
1286
1287         val = rtl_eri_read(tp, addr, type);
1288         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1289 }
1290
1291 struct exgmac_reg {
1292         u16 addr;
1293         u16 mask;
1294         u32 val;
1295 };
1296
1297 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1298                                    const struct exgmac_reg *r, int len)
1299 {
1300         while (len-- > 0) {
1301                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1302                 r++;
1303         }
1304 }
1305
1306 DECLARE_RTL_COND(rtl_efusear_cond)
1307 {
1308         void __iomem *ioaddr = tp->mmio_addr;
1309
1310         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1311 }
1312
1313 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1314 {
1315         void __iomem *ioaddr = tp->mmio_addr;
1316
1317         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1318
1319         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1320                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1321 }
1322
1323 static u16 rtl_get_events(struct rtl8169_private *tp)
1324 {
1325         void __iomem *ioaddr = tp->mmio_addr;
1326
1327         return RTL_R16(IntrStatus);
1328 }
1329
1330 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1331 {
1332         void __iomem *ioaddr = tp->mmio_addr;
1333
1334         RTL_W16(IntrStatus, bits);
1335         mmiowb();
1336 }
1337
1338 static void rtl_irq_disable(struct rtl8169_private *tp)
1339 {
1340         void __iomem *ioaddr = tp->mmio_addr;
1341
1342         RTL_W16(IntrMask, 0);
1343         mmiowb();
1344 }
1345
1346 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1347 {
1348         void __iomem *ioaddr = tp->mmio_addr;
1349
1350         RTL_W16(IntrMask, bits);
1351 }
1352
1353 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1354 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1355 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1356
1357 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1358 {
1359         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1360 }
1361
1362 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1363 {
1364         void __iomem *ioaddr = tp->mmio_addr;
1365
1366         rtl_irq_disable(tp);
1367         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1368         RTL_R8(ChipCmd);
1369 }
1370
1371 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1372 {
1373         void __iomem *ioaddr = tp->mmio_addr;
1374
1375         return RTL_R32(TBICSR) & TBIReset;
1376 }
1377
1378 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1379 {
1380         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1381 }
1382
1383 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1384 {
1385         return RTL_R32(TBICSR) & TBILinkOk;
1386 }
1387
1388 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1389 {
1390         return RTL_R8(PHYstatus) & LinkStatus;
1391 }
1392
1393 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1394 {
1395         void __iomem *ioaddr = tp->mmio_addr;
1396
1397         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1398 }
1399
1400 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1401 {
1402         unsigned int val;
1403
1404         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1405         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1406 }
1407
1408 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1409 {
1410         void __iomem *ioaddr = tp->mmio_addr;
1411         struct net_device *dev = tp->dev;
1412
1413         if (!netif_running(dev))
1414                 return;
1415
1416         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1417             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1418                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1419                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1420                                       ERIAR_EXGMAC);
1421                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1422                                       ERIAR_EXGMAC);
1423                 } else if (RTL_R8(PHYstatus) & _100bps) {
1424                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1425                                       ERIAR_EXGMAC);
1426                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1427                                       ERIAR_EXGMAC);
1428                 } else {
1429                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1430                                       ERIAR_EXGMAC);
1431                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1432                                       ERIAR_EXGMAC);
1433                 }
1434                 /* Reset packet filter */
1435                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1436                              ERIAR_EXGMAC);
1437                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1438                              ERIAR_EXGMAC);
1439         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1440                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1441                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1442                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1443                                       ERIAR_EXGMAC);
1444                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1445                                       ERIAR_EXGMAC);
1446                 } else {
1447                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1448                                       ERIAR_EXGMAC);
1449                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1450                                       ERIAR_EXGMAC);
1451                 }
1452         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1453                 if (RTL_R8(PHYstatus) & _10bps) {
1454                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1455                                       ERIAR_EXGMAC);
1456                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1457                                       ERIAR_EXGMAC);
1458                 } else {
1459                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1460                                       ERIAR_EXGMAC);
1461                 }
1462         }
1463 }
1464
1465 static void __rtl8169_check_link_status(struct net_device *dev,
1466                                         struct rtl8169_private *tp,
1467                                         void __iomem *ioaddr, bool pm)
1468 {
1469         if (tp->link_ok(ioaddr)) {
1470                 rtl_link_chg_patch(tp);
1471                 /* This is to cancel a scheduled suspend if there's one. */
1472                 if (pm)
1473                         pm_request_resume(&tp->pci_dev->dev);
1474                 netif_carrier_on(dev);
1475                 if (net_ratelimit())
1476                         netif_info(tp, ifup, dev, "link up\n");
1477         } else {
1478                 netif_carrier_off(dev);
1479                 netif_info(tp, ifdown, dev, "link down\n");
1480                 if (pm)
1481                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1482         }
1483 }
1484
1485 static void rtl8169_check_link_status(struct net_device *dev,
1486                                       struct rtl8169_private *tp,
1487                                       void __iomem *ioaddr)
1488 {
1489         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1490 }
1491
1492 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1493
1494 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1495 {
1496         void __iomem *ioaddr = tp->mmio_addr;
1497         u8 options;
1498         u32 wolopts = 0;
1499
1500         options = RTL_R8(Config1);
1501         if (!(options & PMEnable))
1502                 return 0;
1503
1504         options = RTL_R8(Config3);
1505         if (options & LinkUp)
1506                 wolopts |= WAKE_PHY;
1507         if (options & MagicPacket)
1508                 wolopts |= WAKE_MAGIC;
1509
1510         options = RTL_R8(Config5);
1511         if (options & UWF)
1512                 wolopts |= WAKE_UCAST;
1513         if (options & BWF)
1514                 wolopts |= WAKE_BCAST;
1515         if (options & MWF)
1516                 wolopts |= WAKE_MCAST;
1517
1518         return wolopts;
1519 }
1520
1521 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1522 {
1523         struct rtl8169_private *tp = netdev_priv(dev);
1524
1525         rtl_lock_work(tp);
1526
1527         wol->supported = WAKE_ANY;
1528         wol->wolopts = __rtl8169_get_wol(tp);
1529
1530         rtl_unlock_work(tp);
1531 }
1532
1533 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1534 {
1535         void __iomem *ioaddr = tp->mmio_addr;
1536         unsigned int i;
1537         static const struct {
1538                 u32 opt;
1539                 u16 reg;
1540                 u8  mask;
1541         } cfg[] = {
1542                 { WAKE_PHY,   Config3, LinkUp },
1543                 { WAKE_MAGIC, Config3, MagicPacket },
1544                 { WAKE_UCAST, Config5, UWF },
1545                 { WAKE_BCAST, Config5, BWF },
1546                 { WAKE_MCAST, Config5, MWF },
1547                 { WAKE_ANY,   Config5, LanWake }
1548         };
1549         u8 options;
1550
1551         RTL_W8(Cfg9346, Cfg9346_Unlock);
1552
1553         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1554                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1555                 if (wolopts & cfg[i].opt)
1556                         options |= cfg[i].mask;
1557                 RTL_W8(cfg[i].reg, options);
1558         }
1559
1560         switch (tp->mac_version) {
1561         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1562                 options = RTL_R8(Config1) & ~PMEnable;
1563                 if (wolopts)
1564                         options |= PMEnable;
1565                 RTL_W8(Config1, options);
1566                 break;
1567         default:
1568                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1569                 if (wolopts)
1570                         options |= PME_SIGNAL;
1571                 RTL_W8(Config2, options);
1572                 break;
1573         }
1574
1575         RTL_W8(Cfg9346, Cfg9346_Lock);
1576 }
1577
1578 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1579 {
1580         struct rtl8169_private *tp = netdev_priv(dev);
1581
1582         rtl_lock_work(tp);
1583
1584         if (wol->wolopts)
1585                 tp->features |= RTL_FEATURE_WOL;
1586         else
1587                 tp->features &= ~RTL_FEATURE_WOL;
1588         __rtl8169_set_wol(tp, wol->wolopts);
1589
1590         rtl_unlock_work(tp);
1591
1592         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1593
1594         return 0;
1595 }
1596
1597 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1598 {
1599         return rtl_chip_infos[tp->mac_version].fw_name;
1600 }
1601
1602 static void rtl8169_get_drvinfo(struct net_device *dev,
1603                                 struct ethtool_drvinfo *info)
1604 {
1605         struct rtl8169_private *tp = netdev_priv(dev);
1606         struct rtl_fw *rtl_fw = tp->rtl_fw;
1607
1608         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1609         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1610         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1611         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1612         if (!IS_ERR_OR_NULL(rtl_fw))
1613                 strlcpy(info->fw_version, rtl_fw->version,
1614                         sizeof(info->fw_version));
1615 }
1616
1617 static int rtl8169_get_regs_len(struct net_device *dev)
1618 {
1619         return R8169_REGS_SIZE;
1620 }
1621
1622 static int rtl8169_set_speed_tbi(struct net_device *dev,
1623                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1624 {
1625         struct rtl8169_private *tp = netdev_priv(dev);
1626         void __iomem *ioaddr = tp->mmio_addr;
1627         int ret = 0;
1628         u32 reg;
1629
1630         reg = RTL_R32(TBICSR);
1631         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1632             (duplex == DUPLEX_FULL)) {
1633                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1634         } else if (autoneg == AUTONEG_ENABLE)
1635                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1636         else {
1637                 netif_warn(tp, link, dev,
1638                            "incorrect speed setting refused in TBI mode\n");
1639                 ret = -EOPNOTSUPP;
1640         }
1641
1642         return ret;
1643 }
1644
1645 static int rtl8169_set_speed_xmii(struct net_device *dev,
1646                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1647 {
1648         struct rtl8169_private *tp = netdev_priv(dev);
1649         int giga_ctrl, bmcr;
1650         int rc = -EINVAL;
1651
1652         rtl_writephy(tp, 0x1f, 0x0000);
1653
1654         if (autoneg == AUTONEG_ENABLE) {
1655                 int auto_nego;
1656
1657                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1658                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1659                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1660
1661                 if (adv & ADVERTISED_10baseT_Half)
1662                         auto_nego |= ADVERTISE_10HALF;
1663                 if (adv & ADVERTISED_10baseT_Full)
1664                         auto_nego |= ADVERTISE_10FULL;
1665                 if (adv & ADVERTISED_100baseT_Half)
1666                         auto_nego |= ADVERTISE_100HALF;
1667                 if (adv & ADVERTISED_100baseT_Full)
1668                         auto_nego |= ADVERTISE_100FULL;
1669
1670                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1671
1672                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1673                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1674
1675                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1676                 if (tp->mii.supports_gmii) {
1677                         if (adv & ADVERTISED_1000baseT_Half)
1678                                 giga_ctrl |= ADVERTISE_1000HALF;
1679                         if (adv & ADVERTISED_1000baseT_Full)
1680                                 giga_ctrl |= ADVERTISE_1000FULL;
1681                 } else if (adv & (ADVERTISED_1000baseT_Half |
1682                                   ADVERTISED_1000baseT_Full)) {
1683                         netif_info(tp, link, dev,
1684                                    "PHY does not support 1000Mbps\n");
1685                         goto out;
1686                 }
1687
1688                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1689
1690                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1691                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1692         } else {
1693                 giga_ctrl = 0;
1694
1695                 if (speed == SPEED_10)
1696                         bmcr = 0;
1697                 else if (speed == SPEED_100)
1698                         bmcr = BMCR_SPEED100;
1699                 else
1700                         goto out;
1701
1702                 if (duplex == DUPLEX_FULL)
1703                         bmcr |= BMCR_FULLDPLX;
1704         }
1705
1706         rtl_writephy(tp, MII_BMCR, bmcr);
1707
1708         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1709             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1710                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1711                         rtl_writephy(tp, 0x17, 0x2138);
1712                         rtl_writephy(tp, 0x0e, 0x0260);
1713                 } else {
1714                         rtl_writephy(tp, 0x17, 0x2108);
1715                         rtl_writephy(tp, 0x0e, 0x0000);
1716                 }
1717         }
1718
1719         rc = 0;
1720 out:
1721         return rc;
1722 }
1723
1724 static int rtl8169_set_speed(struct net_device *dev,
1725                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1726 {
1727         struct rtl8169_private *tp = netdev_priv(dev);
1728         int ret;
1729
1730         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1731         if (ret < 0)
1732                 goto out;
1733
1734         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1735             (advertising & ADVERTISED_1000baseT_Full)) {
1736                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1737         }
1738 out:
1739         return ret;
1740 }
1741
1742 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1743 {
1744         struct rtl8169_private *tp = netdev_priv(dev);
1745         int ret;
1746
1747         del_timer_sync(&tp->timer);
1748
1749         rtl_lock_work(tp);
1750         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1751                                 cmd->duplex, cmd->advertising);
1752         rtl_unlock_work(tp);
1753
1754         return ret;
1755 }
1756
1757 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1758         netdev_features_t features)
1759 {
1760         struct rtl8169_private *tp = netdev_priv(dev);
1761
1762         if (dev->mtu > TD_MSS_MAX)
1763                 features &= ~NETIF_F_ALL_TSO;
1764
1765         if (dev->mtu > JUMBO_1K &&
1766             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1767                 features &= ~NETIF_F_IP_CSUM;
1768
1769         return features;
1770 }
1771
1772 static void __rtl8169_set_features(struct net_device *dev,
1773                                    netdev_features_t features)
1774 {
1775         struct rtl8169_private *tp = netdev_priv(dev);
1776         netdev_features_t changed = features ^ dev->features;
1777         void __iomem *ioaddr = tp->mmio_addr;
1778
1779         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1780                 return;
1781
1782         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1783                 if (features & NETIF_F_RXCSUM)
1784                         tp->cp_cmd |= RxChkSum;
1785                 else
1786                         tp->cp_cmd &= ~RxChkSum;
1787
1788                 if (dev->features & NETIF_F_HW_VLAN_RX)
1789                         tp->cp_cmd |= RxVlan;
1790                 else
1791                         tp->cp_cmd &= ~RxVlan;
1792
1793                 RTL_W16(CPlusCmd, tp->cp_cmd);
1794                 RTL_R16(CPlusCmd);
1795         }
1796         if (changed & NETIF_F_RXALL) {
1797                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1798                 if (features & NETIF_F_RXALL)
1799                         tmp |= (AcceptErr | AcceptRunt);
1800                 RTL_W32(RxConfig, tmp);
1801         }
1802 }
1803
1804 static int rtl8169_set_features(struct net_device *dev,
1805                                 netdev_features_t features)
1806 {
1807         struct rtl8169_private *tp = netdev_priv(dev);
1808
1809         rtl_lock_work(tp);
1810         __rtl8169_set_features(dev, features);
1811         rtl_unlock_work(tp);
1812
1813         return 0;
1814 }
1815
1816
1817 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1818 {
1819         return (vlan_tx_tag_present(skb)) ?
1820                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1821 }
1822
1823 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1824 {
1825         u32 opts2 = le32_to_cpu(desc->opts2);
1826
1827         if (opts2 & RxVlanTag)
1828                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1829
1830         desc->opts2 = 0;
1831 }
1832
1833 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1834 {
1835         struct rtl8169_private *tp = netdev_priv(dev);
1836         void __iomem *ioaddr = tp->mmio_addr;
1837         u32 status;
1838
1839         cmd->supported =
1840                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1841         cmd->port = PORT_FIBRE;
1842         cmd->transceiver = XCVR_INTERNAL;
1843
1844         status = RTL_R32(TBICSR);
1845         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1846         cmd->autoneg = !!(status & TBINwEnable);
1847
1848         ethtool_cmd_speed_set(cmd, SPEED_1000);
1849         cmd->duplex = DUPLEX_FULL; /* Always set */
1850
1851         return 0;
1852 }
1853
1854 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1855 {
1856         struct rtl8169_private *tp = netdev_priv(dev);
1857
1858         return mii_ethtool_gset(&tp->mii, cmd);
1859 }
1860
1861 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1862 {
1863         struct rtl8169_private *tp = netdev_priv(dev);
1864         int rc;
1865
1866         rtl_lock_work(tp);
1867         rc = tp->get_settings(dev, cmd);
1868         rtl_unlock_work(tp);
1869
1870         return rc;
1871 }
1872
1873 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1874                              void *p)
1875 {
1876         struct rtl8169_private *tp = netdev_priv(dev);
1877
1878         if (regs->len > R8169_REGS_SIZE)
1879                 regs->len = R8169_REGS_SIZE;
1880
1881         rtl_lock_work(tp);
1882         memcpy_fromio(p, tp->mmio_addr, regs->len);
1883         rtl_unlock_work(tp);
1884 }
1885
1886 static u32 rtl8169_get_msglevel(struct net_device *dev)
1887 {
1888         struct rtl8169_private *tp = netdev_priv(dev);
1889
1890         return tp->msg_enable;
1891 }
1892
1893 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1894 {
1895         struct rtl8169_private *tp = netdev_priv(dev);
1896
1897         tp->msg_enable = value;
1898 }
1899
1900 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1901         "tx_packets",
1902         "rx_packets",
1903         "tx_errors",
1904         "rx_errors",
1905         "rx_missed",
1906         "align_errors",
1907         "tx_single_collisions",
1908         "tx_multi_collisions",
1909         "unicast",
1910         "broadcast",
1911         "multicast",
1912         "tx_aborted",
1913         "tx_underrun",
1914 };
1915
1916 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1917 {
1918         switch (sset) {
1919         case ETH_SS_STATS:
1920                 return ARRAY_SIZE(rtl8169_gstrings);
1921         default:
1922                 return -EOPNOTSUPP;
1923         }
1924 }
1925
1926 DECLARE_RTL_COND(rtl_counters_cond)
1927 {
1928         void __iomem *ioaddr = tp->mmio_addr;
1929
1930         return RTL_R32(CounterAddrLow) & CounterDump;
1931 }
1932
1933 static void rtl8169_update_counters(struct net_device *dev)
1934 {
1935         struct rtl8169_private *tp = netdev_priv(dev);
1936         void __iomem *ioaddr = tp->mmio_addr;
1937         struct device *d = &tp->pci_dev->dev;
1938         struct rtl8169_counters *counters;
1939         dma_addr_t paddr;
1940         u32 cmd;
1941
1942         /*
1943          * Some chips are unable to dump tally counters when the receiver
1944          * is disabled.
1945          */
1946         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1947                 return;
1948
1949         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1950         if (!counters)
1951                 return;
1952
1953         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1954         cmd = (u64)paddr & DMA_BIT_MASK(32);
1955         RTL_W32(CounterAddrLow, cmd);
1956         RTL_W32(CounterAddrLow, cmd | CounterDump);
1957
1958         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1959                 memcpy(&tp->counters, counters, sizeof(*counters));
1960
1961         RTL_W32(CounterAddrLow, 0);
1962         RTL_W32(CounterAddrHigh, 0);
1963
1964         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1965 }
1966
1967 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1968                                       struct ethtool_stats *stats, u64 *data)
1969 {
1970         struct rtl8169_private *tp = netdev_priv(dev);
1971
1972         ASSERT_RTNL();
1973
1974         rtl8169_update_counters(dev);
1975
1976         data[0] = le64_to_cpu(tp->counters.tx_packets);
1977         data[1] = le64_to_cpu(tp->counters.rx_packets);
1978         data[2] = le64_to_cpu(tp->counters.tx_errors);
1979         data[3] = le32_to_cpu(tp->counters.rx_errors);
1980         data[4] = le16_to_cpu(tp->counters.rx_missed);
1981         data[5] = le16_to_cpu(tp->counters.align_errors);
1982         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1983         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1984         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1985         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1986         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1987         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1988         data[12] = le16_to_cpu(tp->counters.tx_underun);
1989 }
1990
1991 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1992 {
1993         switch(stringset) {
1994         case ETH_SS_STATS:
1995                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1996                 break;
1997         }
1998 }
1999
2000 static const struct ethtool_ops rtl8169_ethtool_ops = {
2001         .get_drvinfo            = rtl8169_get_drvinfo,
2002         .get_regs_len           = rtl8169_get_regs_len,
2003         .get_link               = ethtool_op_get_link,
2004         .get_settings           = rtl8169_get_settings,
2005         .set_settings           = rtl8169_set_settings,
2006         .get_msglevel           = rtl8169_get_msglevel,
2007         .set_msglevel           = rtl8169_set_msglevel,
2008         .get_regs               = rtl8169_get_regs,
2009         .get_wol                = rtl8169_get_wol,
2010         .set_wol                = rtl8169_set_wol,
2011         .get_strings            = rtl8169_get_strings,
2012         .get_sset_count         = rtl8169_get_sset_count,
2013         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2014         .get_ts_info            = ethtool_op_get_ts_info,
2015 };
2016
2017 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2018                                     struct net_device *dev, u8 default_version)
2019 {
2020         void __iomem *ioaddr = tp->mmio_addr;
2021         /*
2022          * The driver currently handles the 8168Bf and the 8168Be identically
2023          * but they can be identified more specifically through the test below
2024          * if needed:
2025          *
2026          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2027          *
2028          * Same thing for the 8101Eb and the 8101Ec:
2029          *
2030          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2031          */
2032         static const struct rtl_mac_info {
2033                 u32 mask;
2034                 u32 val;
2035                 int mac_version;
2036         } mac_info[] = {
2037                 /* 8168G family. */
2038                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2039                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2040
2041                 /* 8168F family. */
2042                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2043                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2044                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2045
2046                 /* 8168E family. */
2047                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2048                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2049                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2050                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2051
2052                 /* 8168D family. */
2053                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2054                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2055                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2056
2057                 /* 8168DP family. */
2058                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2059                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2060                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2061
2062                 /* 8168C family. */
2063                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2064                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2065                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2066                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2067                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2068                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2069                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2070                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2071                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2072
2073                 /* 8168B family. */
2074                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2075                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2076                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2077                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2078
2079                 /* 8101 family. */
2080                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2081                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2082                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2083                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2084                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2085                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2086                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2087                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2088                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2089                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2090                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2091                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2092                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2093                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2094                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2095                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2096                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2097                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2098                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2099                 /* FIXME: where did these entries come from ? -- FR */
2100                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2101                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2102
2103                 /* 8110 family. */
2104                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2105                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2106                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2107                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2108                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2109                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2110
2111                 /* Catch-all */
2112                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2113         };
2114         const struct rtl_mac_info *p = mac_info;
2115         u32 reg;
2116
2117         reg = RTL_R32(TxConfig);
2118         while ((reg & p->mask) != p->val)
2119                 p++;
2120         tp->mac_version = p->mac_version;
2121
2122         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2123                 netif_notice(tp, probe, dev,
2124                              "unknown MAC, using family default\n");
2125                 tp->mac_version = default_version;
2126         }
2127 }
2128
2129 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2130 {
2131         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2132 }
2133
2134 struct phy_reg {
2135         u16 reg;
2136         u16 val;
2137 };
2138
2139 static void rtl_writephy_batch(struct rtl8169_private *tp,
2140                                const struct phy_reg *regs, int len)
2141 {
2142         while (len-- > 0) {
2143                 rtl_writephy(tp, regs->reg, regs->val);
2144                 regs++;
2145         }
2146 }
2147
2148 #define PHY_READ                0x00000000
2149 #define PHY_DATA_OR             0x10000000
2150 #define PHY_DATA_AND            0x20000000
2151 #define PHY_BJMPN               0x30000000
2152 #define PHY_READ_EFUSE          0x40000000
2153 #define PHY_READ_MAC_BYTE       0x50000000
2154 #define PHY_WRITE_MAC_BYTE      0x60000000
2155 #define PHY_CLEAR_READCOUNT     0x70000000
2156 #define PHY_WRITE               0x80000000
2157 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2158 #define PHY_COMP_EQ_SKIPN       0xa0000000
2159 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2160 #define PHY_WRITE_PREVIOUS      0xc0000000
2161 #define PHY_SKIPN               0xd0000000
2162 #define PHY_DELAY_MS            0xe0000000
2163 #define PHY_WRITE_ERI_WORD      0xf0000000
2164
2165 struct fw_info {
2166         u32     magic;
2167         char    version[RTL_VER_SIZE];
2168         __le32  fw_start;
2169         __le32  fw_len;
2170         u8      chksum;
2171 } __packed;
2172
2173 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2174
2175 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2176 {
2177         const struct firmware *fw = rtl_fw->fw;
2178         struct fw_info *fw_info = (struct fw_info *)fw->data;
2179         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2180         char *version = rtl_fw->version;
2181         bool rc = false;
2182
2183         if (fw->size < FW_OPCODE_SIZE)
2184                 goto out;
2185
2186         if (!fw_info->magic) {
2187                 size_t i, size, start;
2188                 u8 checksum = 0;
2189
2190                 if (fw->size < sizeof(*fw_info))
2191                         goto out;
2192
2193                 for (i = 0; i < fw->size; i++)
2194                         checksum += fw->data[i];
2195                 if (checksum != 0)
2196                         goto out;
2197
2198                 start = le32_to_cpu(fw_info->fw_start);
2199                 if (start > fw->size)
2200                         goto out;
2201
2202                 size = le32_to_cpu(fw_info->fw_len);
2203                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2204                         goto out;
2205
2206                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2207
2208                 pa->code = (__le32 *)(fw->data + start);
2209                 pa->size = size;
2210         } else {
2211                 if (fw->size % FW_OPCODE_SIZE)
2212                         goto out;
2213
2214                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2215
2216                 pa->code = (__le32 *)fw->data;
2217                 pa->size = fw->size / FW_OPCODE_SIZE;
2218         }
2219         version[RTL_VER_SIZE - 1] = 0;
2220
2221         rc = true;
2222 out:
2223         return rc;
2224 }
2225
2226 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2227                            struct rtl_fw_phy_action *pa)
2228 {
2229         bool rc = false;
2230         size_t index;
2231
2232         for (index = 0; index < pa->size; index++) {
2233                 u32 action = le32_to_cpu(pa->code[index]);
2234                 u32 regno = (action & 0x0fff0000) >> 16;
2235
2236                 switch(action & 0xf0000000) {
2237                 case PHY_READ:
2238                 case PHY_DATA_OR:
2239                 case PHY_DATA_AND:
2240                 case PHY_READ_EFUSE:
2241                 case PHY_CLEAR_READCOUNT:
2242                 case PHY_WRITE:
2243                 case PHY_WRITE_PREVIOUS:
2244                 case PHY_DELAY_MS:
2245                         break;
2246
2247                 case PHY_BJMPN:
2248                         if (regno > index) {
2249                                 netif_err(tp, ifup, tp->dev,
2250                                           "Out of range of firmware\n");
2251                                 goto out;
2252                         }
2253                         break;
2254                 case PHY_READCOUNT_EQ_SKIP:
2255                         if (index + 2 >= pa->size) {
2256                                 netif_err(tp, ifup, tp->dev,
2257                                           "Out of range of firmware\n");
2258                                 goto out;
2259                         }
2260                         break;
2261                 case PHY_COMP_EQ_SKIPN:
2262                 case PHY_COMP_NEQ_SKIPN:
2263                 case PHY_SKIPN:
2264                         if (index + 1 + regno >= pa->size) {
2265                                 netif_err(tp, ifup, tp->dev,
2266                                           "Out of range of firmware\n");
2267                                 goto out;
2268                         }
2269                         break;
2270
2271                 case PHY_READ_MAC_BYTE:
2272                 case PHY_WRITE_MAC_BYTE:
2273                 case PHY_WRITE_ERI_WORD:
2274                 default:
2275                         netif_err(tp, ifup, tp->dev,
2276                                   "Invalid action 0x%08x\n", action);
2277                         goto out;
2278                 }
2279         }
2280         rc = true;
2281 out:
2282         return rc;
2283 }
2284
2285 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2286 {
2287         struct net_device *dev = tp->dev;
2288         int rc = -EINVAL;
2289
2290         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2291                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2292                 goto out;
2293         }
2294
2295         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2296                 rc = 0;
2297 out:
2298         return rc;
2299 }
2300
2301 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2302 {
2303         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2304         u32 predata, count;
2305         size_t index;
2306
2307         predata = count = 0;
2308
2309         for (index = 0; index < pa->size; ) {
2310                 u32 action = le32_to_cpu(pa->code[index]);
2311                 u32 data = action & 0x0000ffff;
2312                 u32 regno = (action & 0x0fff0000) >> 16;
2313
2314                 if (!action)
2315                         break;
2316
2317                 switch(action & 0xf0000000) {
2318                 case PHY_READ:
2319                         predata = rtl_readphy(tp, regno);
2320                         count++;
2321                         index++;
2322                         break;
2323                 case PHY_DATA_OR:
2324                         predata |= data;
2325                         index++;
2326                         break;
2327                 case PHY_DATA_AND:
2328                         predata &= data;
2329                         index++;
2330                         break;
2331                 case PHY_BJMPN:
2332                         index -= regno;
2333                         break;
2334                 case PHY_READ_EFUSE:
2335                         predata = rtl8168d_efuse_read(tp, regno);
2336                         index++;
2337                         break;
2338                 case PHY_CLEAR_READCOUNT:
2339                         count = 0;
2340                         index++;
2341                         break;
2342                 case PHY_WRITE:
2343                         rtl_writephy(tp, regno, data);
2344                         index++;
2345                         break;
2346                 case PHY_READCOUNT_EQ_SKIP:
2347                         index += (count == data) ? 2 : 1;
2348                         break;
2349                 case PHY_COMP_EQ_SKIPN:
2350                         if (predata == data)
2351                                 index += regno;
2352                         index++;
2353                         break;
2354                 case PHY_COMP_NEQ_SKIPN:
2355                         if (predata != data)
2356                                 index += regno;
2357                         index++;
2358                         break;
2359                 case PHY_WRITE_PREVIOUS:
2360                         rtl_writephy(tp, regno, predata);
2361                         index++;
2362                         break;
2363                 case PHY_SKIPN:
2364                         index += regno + 1;
2365                         break;
2366                 case PHY_DELAY_MS:
2367                         mdelay(data);
2368                         index++;
2369                         break;
2370
2371                 case PHY_READ_MAC_BYTE:
2372                 case PHY_WRITE_MAC_BYTE:
2373                 case PHY_WRITE_ERI_WORD:
2374                 default:
2375                         BUG();
2376                 }
2377         }
2378 }
2379
2380 static void rtl_release_firmware(struct rtl8169_private *tp)
2381 {
2382         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2383                 release_firmware(tp->rtl_fw->fw);
2384                 kfree(tp->rtl_fw);
2385         }
2386         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2387 }
2388
2389 static void rtl_apply_firmware(struct rtl8169_private *tp)
2390 {
2391         struct rtl_fw *rtl_fw = tp->rtl_fw;
2392
2393         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2394         if (!IS_ERR_OR_NULL(rtl_fw)) {
2395                 rtl_phy_write_fw(tp, rtl_fw);
2396                 tp->features |= RTL_FEATURE_FW_LOADED;
2397         }
2398 }
2399
2400 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2401 {
2402         if (rtl_readphy(tp, reg) != val)
2403                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2404         else
2405                 rtl_apply_firmware(tp);
2406 }
2407
2408 static void r810x_aldps_disable(struct rtl8169_private *tp)
2409 {
2410         rtl_writephy(tp, 0x1f, 0x0000);
2411         rtl_writephy(tp, 0x18, 0x0310);
2412         msleep(100);
2413 }
2414
2415 static void r810x_aldps_enable(struct rtl8169_private *tp)
2416 {
2417         if (!(tp->features & RTL_FEATURE_FW_LOADED))
2418                 return;
2419
2420         rtl_writephy(tp, 0x1f, 0x0000);
2421         rtl_writephy(tp, 0x18, 0x8310);
2422 }
2423
2424 static void r8168_aldps_enable_1(struct rtl8169_private *tp)
2425 {
2426         if (!(tp->features & RTL_FEATURE_FW_LOADED))
2427                 return;
2428
2429         rtl_writephy(tp, 0x1f, 0x0000);
2430         rtl_w1w0_phy(tp, 0x15, 0x1000, 0x0000);
2431 }
2432
2433 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2434 {
2435         static const struct phy_reg phy_reg_init[] = {
2436                 { 0x1f, 0x0001 },
2437                 { 0x06, 0x006e },
2438                 { 0x08, 0x0708 },
2439                 { 0x15, 0x4000 },
2440                 { 0x18, 0x65c7 },
2441
2442                 { 0x1f, 0x0001 },
2443                 { 0x03, 0x00a1 },
2444                 { 0x02, 0x0008 },
2445                 { 0x01, 0x0120 },
2446                 { 0x00, 0x1000 },
2447                 { 0x04, 0x0800 },
2448                 { 0x04, 0x0000 },
2449
2450                 { 0x03, 0xff41 },
2451                 { 0x02, 0xdf60 },
2452                 { 0x01, 0x0140 },
2453                 { 0x00, 0x0077 },
2454                 { 0x04, 0x7800 },
2455                 { 0x04, 0x7000 },
2456
2457                 { 0x03, 0x802f },
2458                 { 0x02, 0x4f02 },
2459                 { 0x01, 0x0409 },
2460                 { 0x00, 0xf0f9 },
2461                 { 0x04, 0x9800 },
2462                 { 0x04, 0x9000 },
2463
2464                 { 0x03, 0xdf01 },
2465                 { 0x02, 0xdf20 },
2466                 { 0x01, 0xff95 },
2467                 { 0x00, 0xba00 },
2468                 { 0x04, 0xa800 },
2469                 { 0x04, 0xa000 },
2470
2471                 { 0x03, 0xff41 },
2472                 { 0x02, 0xdf20 },
2473                 { 0x01, 0x0140 },
2474                 { 0x00, 0x00bb },
2475                 { 0x04, 0xb800 },
2476                 { 0x04, 0xb000 },
2477
2478                 { 0x03, 0xdf41 },
2479                 { 0x02, 0xdc60 },
2480                 { 0x01, 0x6340 },
2481                 { 0x00, 0x007d },
2482                 { 0x04, 0xd800 },
2483                 { 0x04, 0xd000 },
2484
2485                 { 0x03, 0xdf01 },
2486                 { 0x02, 0xdf20 },
2487                 { 0x01, 0x100a },
2488                 { 0x00, 0xa0ff },
2489                 { 0x04, 0xf800 },
2490                 { 0x04, 0xf000 },
2491
2492                 { 0x1f, 0x0000 },
2493                 { 0x0b, 0x0000 },
2494                 { 0x00, 0x9200 }
2495         };
2496
2497         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2498 }
2499
2500 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2501 {
2502         static const struct phy_reg phy_reg_init[] = {
2503                 { 0x1f, 0x0002 },
2504                 { 0x01, 0x90d0 },
2505                 { 0x1f, 0x0000 }
2506         };
2507
2508         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2509 }
2510
2511 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2512 {
2513         struct pci_dev *pdev = tp->pci_dev;
2514
2515         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2516             (pdev->subsystem_device != 0xe000))
2517                 return;
2518
2519         rtl_writephy(tp, 0x1f, 0x0001);
2520         rtl_writephy(tp, 0x10, 0xf01b);
2521         rtl_writephy(tp, 0x1f, 0x0000);
2522 }
2523
2524 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2525 {
2526         static const struct phy_reg phy_reg_init[] = {
2527                 { 0x1f, 0x0001 },
2528                 { 0x04, 0x0000 },
2529                 { 0x03, 0x00a1 },
2530                 { 0x02, 0x0008 },
2531                 { 0x01, 0x0120 },
2532                 { 0x00, 0x1000 },
2533                 { 0x04, 0x0800 },
2534                 { 0x04, 0x9000 },
2535                 { 0x03, 0x802f },
2536                 { 0x02, 0x4f02 },
2537                 { 0x01, 0x0409 },
2538                 { 0x00, 0xf099 },
2539                 { 0x04, 0x9800 },
2540                 { 0x04, 0xa000 },
2541                 { 0x03, 0xdf01 },
2542                 { 0x02, 0xdf20 },
2543                 { 0x01, 0xff95 },
2544                 { 0x00, 0xba00 },
2545                 { 0x04, 0xa800 },
2546                 { 0x04, 0xf000 },
2547                 { 0x03, 0xdf01 },
2548                 { 0x02, 0xdf20 },
2549                 { 0x01, 0x101a },
2550                 { 0x00, 0xa0ff },
2551                 { 0x04, 0xf800 },
2552                 { 0x04, 0x0000 },
2553                 { 0x1f, 0x0000 },
2554
2555                 { 0x1f, 0x0001 },
2556                 { 0x10, 0xf41b },
2557                 { 0x14, 0xfb54 },
2558                 { 0x18, 0xf5c7 },
2559                 { 0x1f, 0x0000 },
2560
2561                 { 0x1f, 0x0001 },
2562                 { 0x17, 0x0cc0 },
2563                 { 0x1f, 0x0000 }
2564         };
2565
2566         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2567
2568         rtl8169scd_hw_phy_config_quirk(tp);
2569 }
2570
2571 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2572 {
2573         static const struct phy_reg phy_reg_init[] = {
2574                 { 0x1f, 0x0001 },
2575                 { 0x04, 0x0000 },
2576                 { 0x03, 0x00a1 },
2577                 { 0x02, 0x0008 },
2578                 { 0x01, 0x0120 },
2579                 { 0x00, 0x1000 },
2580                 { 0x04, 0x0800 },
2581                 { 0x04, 0x9000 },
2582                 { 0x03, 0x802f },
2583                 { 0x02, 0x4f02 },
2584                 { 0x01, 0x0409 },
2585                 { 0x00, 0xf099 },
2586                 { 0x04, 0x9800 },
2587                 { 0x04, 0xa000 },
2588                 { 0x03, 0xdf01 },
2589                 { 0x02, 0xdf20 },
2590                 { 0x01, 0xff95 },
2591                 { 0x00, 0xba00 },
2592                 { 0x04, 0xa800 },
2593                 { 0x04, 0xf000 },
2594                 { 0x03, 0xdf01 },
2595                 { 0x02, 0xdf20 },
2596                 { 0x01, 0x101a },
2597                 { 0x00, 0xa0ff },
2598                 { 0x04, 0xf800 },
2599                 { 0x04, 0x0000 },
2600                 { 0x1f, 0x0000 },
2601
2602                 { 0x1f, 0x0001 },
2603                 { 0x0b, 0x8480 },
2604                 { 0x1f, 0x0000 },
2605
2606                 { 0x1f, 0x0001 },
2607                 { 0x18, 0x67c7 },
2608                 { 0x04, 0x2000 },
2609                 { 0x03, 0x002f },
2610                 { 0x02, 0x4360 },
2611                 { 0x01, 0x0109 },
2612                 { 0x00, 0x3022 },
2613                 { 0x04, 0x2800 },
2614                 { 0x1f, 0x0000 },
2615
2616                 { 0x1f, 0x0001 },
2617                 { 0x17, 0x0cc0 },
2618                 { 0x1f, 0x0000 }
2619         };
2620
2621         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2622 }
2623
2624 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2625 {
2626         static const struct phy_reg phy_reg_init[] = {
2627                 { 0x10, 0xf41b },
2628                 { 0x1f, 0x0000 }
2629         };
2630
2631         rtl_writephy(tp, 0x1f, 0x0001);
2632         rtl_patchphy(tp, 0x16, 1 << 0);
2633
2634         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2635 }
2636
2637 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2638 {
2639         static const struct phy_reg phy_reg_init[] = {
2640                 { 0x1f, 0x0001 },
2641                 { 0x10, 0xf41b },
2642                 { 0x1f, 0x0000 }
2643         };
2644
2645         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2646 }
2647
2648 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2649 {
2650         static const struct phy_reg phy_reg_init[] = {
2651                 { 0x1f, 0x0000 },
2652                 { 0x1d, 0x0f00 },
2653                 { 0x1f, 0x0002 },
2654                 { 0x0c, 0x1ec8 },
2655                 { 0x1f, 0x0000 }
2656         };
2657
2658         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2659 }
2660
2661 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2662 {
2663         static const struct phy_reg phy_reg_init[] = {
2664                 { 0x1f, 0x0001 },
2665                 { 0x1d, 0x3d98 },
2666                 { 0x1f, 0x0000 }
2667         };
2668
2669         rtl_writephy(tp, 0x1f, 0x0000);
2670         rtl_patchphy(tp, 0x14, 1 << 5);
2671         rtl_patchphy(tp, 0x0d, 1 << 5);
2672
2673         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2674 }
2675
2676 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2677 {
2678         static const struct phy_reg phy_reg_init[] = {
2679                 { 0x1f, 0x0001 },
2680                 { 0x12, 0x2300 },
2681                 { 0x1f, 0x0002 },
2682                 { 0x00, 0x88d4 },
2683                 { 0x01, 0x82b1 },
2684                 { 0x03, 0x7002 },
2685                 { 0x08, 0x9e30 },
2686                 { 0x09, 0x01f0 },
2687                 { 0x0a, 0x5500 },
2688                 { 0x0c, 0x00c8 },
2689                 { 0x1f, 0x0003 },
2690                 { 0x12, 0xc096 },
2691                 { 0x16, 0x000a },
2692                 { 0x1f, 0x0000 },
2693                 { 0x1f, 0x0000 },
2694                 { 0x09, 0x2000 },
2695                 { 0x09, 0x0000 }
2696         };
2697
2698         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2699
2700         rtl_patchphy(tp, 0x14, 1 << 5);
2701         rtl_patchphy(tp, 0x0d, 1 << 5);
2702         rtl_writephy(tp, 0x1f, 0x0000);
2703 }
2704
2705 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2706 {
2707         static const struct phy_reg phy_reg_init[] = {
2708                 { 0x1f, 0x0001 },
2709                 { 0x12, 0x2300 },
2710                 { 0x03, 0x802f },
2711                 { 0x02, 0x4f02 },
2712                 { 0x01, 0x0409 },
2713                 { 0x00, 0xf099 },
2714                 { 0x04, 0x9800 },
2715                 { 0x04, 0x9000 },
2716                 { 0x1d, 0x3d98 },
2717                 { 0x1f, 0x0002 },
2718                 { 0x0c, 0x7eb8 },
2719                 { 0x06, 0x0761 },
2720                 { 0x1f, 0x0003 },
2721                 { 0x16, 0x0f0a },
2722                 { 0x1f, 0x0000 }
2723         };
2724
2725         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2726
2727         rtl_patchphy(tp, 0x16, 1 << 0);
2728         rtl_patchphy(tp, 0x14, 1 << 5);
2729         rtl_patchphy(tp, 0x0d, 1 << 5);
2730         rtl_writephy(tp, 0x1f, 0x0000);
2731 }
2732
2733 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2734 {
2735         static const struct phy_reg phy_reg_init[] = {
2736                 { 0x1f, 0x0001 },
2737                 { 0x12, 0x2300 },
2738                 { 0x1d, 0x3d98 },
2739                 { 0x1f, 0x0002 },
2740                 { 0x0c, 0x7eb8 },
2741                 { 0x06, 0x5461 },
2742                 { 0x1f, 0x0003 },
2743                 { 0x16, 0x0f0a },
2744                 { 0x1f, 0x0000 }
2745         };
2746
2747         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2748
2749         rtl_patchphy(tp, 0x16, 1 << 0);
2750         rtl_patchphy(tp, 0x14, 1 << 5);
2751         rtl_patchphy(tp, 0x0d, 1 << 5);
2752         rtl_writephy(tp, 0x1f, 0x0000);
2753 }
2754
2755 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2756 {
2757         rtl8168c_3_hw_phy_config(tp);
2758 }
2759
2760 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2761 {
2762         static const struct phy_reg phy_reg_init_0[] = {
2763                 /* Channel Estimation */
2764                 { 0x1f, 0x0001 },
2765                 { 0x06, 0x4064 },
2766                 { 0x07, 0x2863 },
2767                 { 0x08, 0x059c },
2768                 { 0x09, 0x26b4 },
2769                 { 0x0a, 0x6a19 },
2770                 { 0x0b, 0xdcc8 },
2771                 { 0x10, 0xf06d },
2772                 { 0x14, 0x7f68 },
2773                 { 0x18, 0x7fd9 },
2774                 { 0x1c, 0xf0ff },
2775                 { 0x1d, 0x3d9c },
2776                 { 0x1f, 0x0003 },
2777                 { 0x12, 0xf49f },
2778                 { 0x13, 0x070b },
2779                 { 0x1a, 0x05ad },
2780                 { 0x14, 0x94c0 },
2781
2782                 /*
2783                  * Tx Error Issue
2784                  * Enhance line driver power
2785                  */
2786                 { 0x1f, 0x0002 },
2787                 { 0x06, 0x5561 },
2788                 { 0x1f, 0x0005 },
2789                 { 0x05, 0x8332 },
2790                 { 0x06, 0x5561 },
2791
2792                 /*
2793                  * Can not link to 1Gbps with bad cable
2794                  * Decrease SNR threshold form 21.07dB to 19.04dB
2795                  */
2796                 { 0x1f, 0x0001 },
2797                 { 0x17, 0x0cc0 },
2798
2799                 { 0x1f, 0x0000 },
2800                 { 0x0d, 0xf880 }
2801         };
2802
2803         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2804
2805         /*
2806          * Rx Error Issue
2807          * Fine Tune Switching regulator parameter
2808          */
2809         rtl_writephy(tp, 0x1f, 0x0002);
2810         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2811         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2812
2813         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2814                 static const struct phy_reg phy_reg_init[] = {
2815                         { 0x1f, 0x0002 },
2816                         { 0x05, 0x669a },
2817                         { 0x1f, 0x0005 },
2818                         { 0x05, 0x8330 },
2819                         { 0x06, 0x669a },
2820                         { 0x1f, 0x0002 }
2821                 };
2822                 int val;
2823
2824                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2825
2826                 val = rtl_readphy(tp, 0x0d);
2827
2828                 if ((val & 0x00ff) != 0x006c) {
2829                         static const u32 set[] = {
2830                                 0x0065, 0x0066, 0x0067, 0x0068,
2831                                 0x0069, 0x006a, 0x006b, 0x006c
2832                         };
2833                         int i;
2834
2835                         rtl_writephy(tp, 0x1f, 0x0002);
2836
2837                         val &= 0xff00;
2838                         for (i = 0; i < ARRAY_SIZE(set); i++)
2839                                 rtl_writephy(tp, 0x0d, val | set[i]);
2840                 }
2841         } else {
2842                 static const struct phy_reg phy_reg_init[] = {
2843                         { 0x1f, 0x0002 },
2844                         { 0x05, 0x6662 },
2845                         { 0x1f, 0x0005 },
2846                         { 0x05, 0x8330 },
2847                         { 0x06, 0x6662 }
2848                 };
2849
2850                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851         }
2852
2853         /* RSET couple improve */
2854         rtl_writephy(tp, 0x1f, 0x0002);
2855         rtl_patchphy(tp, 0x0d, 0x0300);
2856         rtl_patchphy(tp, 0x0f, 0x0010);
2857
2858         /* Fine tune PLL performance */
2859         rtl_writephy(tp, 0x1f, 0x0002);
2860         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2861         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2862
2863         rtl_writephy(tp, 0x1f, 0x0005);
2864         rtl_writephy(tp, 0x05, 0x001b);
2865
2866         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2867
2868         rtl_writephy(tp, 0x1f, 0x0000);
2869 }
2870
2871 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2872 {
2873         static const struct phy_reg phy_reg_init_0[] = {
2874                 /* Channel Estimation */
2875                 { 0x1f, 0x0001 },
2876                 { 0x06, 0x4064 },
2877                 { 0x07, 0x2863 },
2878                 { 0x08, 0x059c },
2879                 { 0x09, 0x26b4 },
2880                 { 0x0a, 0x6a19 },
2881                 { 0x0b, 0xdcc8 },
2882                 { 0x10, 0xf06d },
2883                 { 0x14, 0x7f68 },
2884                 { 0x18, 0x7fd9 },
2885                 { 0x1c, 0xf0ff },
2886                 { 0x1d, 0x3d9c },
2887                 { 0x1f, 0x0003 },
2888                 { 0x12, 0xf49f },
2889                 { 0x13, 0x070b },
2890                 { 0x1a, 0x05ad },
2891                 { 0x14, 0x94c0 },
2892
2893                 /*
2894                  * Tx Error Issue
2895                  * Enhance line driver power
2896                  */
2897                 { 0x1f, 0x0002 },
2898                 { 0x06, 0x5561 },
2899                 { 0x1f, 0x0005 },
2900                 { 0x05, 0x8332 },
2901                 { 0x06, 0x5561 },
2902
2903                 /*
2904                  * Can not link to 1Gbps with bad cable
2905                  * Decrease SNR threshold form 21.07dB to 19.04dB
2906                  */
2907                 { 0x1f, 0x0001 },
2908                 { 0x17, 0x0cc0 },
2909
2910                 { 0x1f, 0x0000 },
2911                 { 0x0d, 0xf880 }
2912         };
2913
2914         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2915
2916         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2917                 static const struct phy_reg phy_reg_init[] = {
2918                         { 0x1f, 0x0002 },
2919                         { 0x05, 0x669a },
2920                         { 0x1f, 0x0005 },
2921                         { 0x05, 0x8330 },
2922                         { 0x06, 0x669a },
2923
2924                         { 0x1f, 0x0002 }
2925                 };
2926                 int val;
2927
2928                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2929
2930                 val = rtl_readphy(tp, 0x0d);
2931                 if ((val & 0x00ff) != 0x006c) {
2932                         static const u32 set[] = {
2933                                 0x0065, 0x0066, 0x0067, 0x0068,
2934                                 0x0069, 0x006a, 0x006b, 0x006c
2935                         };
2936                         int i;
2937
2938                         rtl_writephy(tp, 0x1f, 0x0002);
2939
2940                         val &= 0xff00;
2941                         for (i = 0; i < ARRAY_SIZE(set); i++)
2942                                 rtl_writephy(tp, 0x0d, val | set[i]);
2943                 }
2944         } else {
2945                 static const struct phy_reg phy_reg_init[] = {
2946                         { 0x1f, 0x0002 },
2947                         { 0x05, 0x2642 },
2948                         { 0x1f, 0x0005 },
2949                         { 0x05, 0x8330 },
2950                         { 0x06, 0x2642 }
2951                 };
2952
2953                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2954         }
2955
2956         /* Fine tune PLL performance */
2957         rtl_writephy(tp, 0x1f, 0x0002);
2958         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2959         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2960
2961         /* Switching regulator Slew rate */
2962         rtl_writephy(tp, 0x1f, 0x0002);
2963         rtl_patchphy(tp, 0x0f, 0x0017);
2964
2965         rtl_writephy(tp, 0x1f, 0x0005);
2966         rtl_writephy(tp, 0x05, 0x001b);
2967
2968         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2969
2970         rtl_writephy(tp, 0x1f, 0x0000);
2971 }
2972
2973 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2974 {
2975         static const struct phy_reg phy_reg_init[] = {
2976                 { 0x1f, 0x0002 },
2977                 { 0x10, 0x0008 },
2978                 { 0x0d, 0x006c },
2979
2980                 { 0x1f, 0x0000 },
2981                 { 0x0d, 0xf880 },
2982
2983                 { 0x1f, 0x0001 },
2984                 { 0x17, 0x0cc0 },
2985
2986                 { 0x1f, 0x0001 },
2987                 { 0x0b, 0xa4d8 },
2988                 { 0x09, 0x281c },
2989                 { 0x07, 0x2883 },
2990                 { 0x0a, 0x6b35 },
2991                 { 0x1d, 0x3da4 },
2992                 { 0x1c, 0xeffd },
2993                 { 0x14, 0x7f52 },
2994                 { 0x18, 0x7fc6 },
2995                 { 0x08, 0x0601 },
2996                 { 0x06, 0x4063 },
2997                 { 0x10, 0xf074 },
2998                 { 0x1f, 0x0003 },
2999                 { 0x13, 0x0789 },
3000                 { 0x12, 0xf4bd },
3001                 { 0x1a, 0x04fd },
3002                 { 0x14, 0x84b0 },
3003                 { 0x1f, 0x0000 },
3004                 { 0x00, 0x9200 },
3005
3006                 { 0x1f, 0x0005 },
3007                 { 0x01, 0x0340 },
3008                 { 0x1f, 0x0001 },
3009                 { 0x04, 0x4000 },
3010                 { 0x03, 0x1d21 },
3011                 { 0x02, 0x0c32 },
3012                 { 0x01, 0x0200 },
3013                 { 0x00, 0x5554 },
3014                 { 0x04, 0x4800 },
3015                 { 0x04, 0x4000 },
3016                 { 0x04, 0xf000 },
3017                 { 0x03, 0xdf01 },
3018                 { 0x02, 0xdf20 },
3019                 { 0x01, 0x101a },
3020                 { 0x00, 0xa0ff },
3021                 { 0x04, 0xf800 },
3022                 { 0x04, 0xf000 },
3023                 { 0x1f, 0x0000 },
3024
3025                 { 0x1f, 0x0007 },
3026                 { 0x1e, 0x0023 },
3027                 { 0x16, 0x0000 },
3028                 { 0x1f, 0x0000 }
3029         };
3030
3031         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3032 }
3033
3034 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3035 {
3036         static const struct phy_reg phy_reg_init[] = {
3037                 { 0x1f, 0x0001 },
3038                 { 0x17, 0x0cc0 },
3039
3040                 { 0x1f, 0x0007 },
3041                 { 0x1e, 0x002d },
3042                 { 0x18, 0x0040 },
3043                 { 0x1f, 0x0000 }
3044         };
3045
3046         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3047         rtl_patchphy(tp, 0x0d, 1 << 5);
3048 }
3049
3050 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3051 {
3052         static const struct phy_reg phy_reg_init[] = {
3053                 /* Enable Delay cap */
3054                 { 0x1f, 0x0005 },
3055                 { 0x05, 0x8b80 },
3056                 { 0x06, 0xc896 },
3057                 { 0x1f, 0x0000 },
3058
3059                 /* Channel estimation fine tune */
3060                 { 0x1f, 0x0001 },
3061                 { 0x0b, 0x6c20 },
3062                 { 0x07, 0x2872 },
3063                 { 0x1c, 0xefff },
3064                 { 0x1f, 0x0003 },
3065                 { 0x14, 0x6420 },
3066                 { 0x1f, 0x0000 },
3067
3068                 /* Update PFM & 10M TX idle timer */
3069                 { 0x1f, 0x0007 },
3070                 { 0x1e, 0x002f },
3071                 { 0x15, 0x1919 },
3072                 { 0x1f, 0x0000 },
3073
3074                 { 0x1f, 0x0007 },
3075                 { 0x1e, 0x00ac },
3076                 { 0x18, 0x0006 },
3077                 { 0x1f, 0x0000 }
3078         };
3079
3080         rtl_apply_firmware(tp);
3081
3082         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3083
3084         /* DCO enable for 10M IDLE Power */
3085         rtl_writephy(tp, 0x1f, 0x0007);
3086         rtl_writephy(tp, 0x1e, 0x0023);
3087         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3088         rtl_writephy(tp, 0x1f, 0x0000);
3089
3090         /* For impedance matching */
3091         rtl_writephy(tp, 0x1f, 0x0002);
3092         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3093         rtl_writephy(tp, 0x1f, 0x0000);
3094
3095         /* PHY auto speed down */
3096         rtl_writephy(tp, 0x1f, 0x0007);
3097         rtl_writephy(tp, 0x1e, 0x002d);
3098         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3099         rtl_writephy(tp, 0x1f, 0x0000);
3100         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3101
3102         rtl_writephy(tp, 0x1f, 0x0005);
3103         rtl_writephy(tp, 0x05, 0x8b86);
3104         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3105         rtl_writephy(tp, 0x1f, 0x0000);
3106
3107         rtl_writephy(tp, 0x1f, 0x0005);
3108         rtl_writephy(tp, 0x05, 0x8b85);
3109         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3110         rtl_writephy(tp, 0x1f, 0x0007);
3111         rtl_writephy(tp, 0x1e, 0x0020);
3112         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3113         rtl_writephy(tp, 0x1f, 0x0006);
3114         rtl_writephy(tp, 0x00, 0x5a00);
3115         rtl_writephy(tp, 0x1f, 0x0000);
3116         rtl_writephy(tp, 0x0d, 0x0007);
3117         rtl_writephy(tp, 0x0e, 0x003c);
3118         rtl_writephy(tp, 0x0d, 0x4007);
3119         rtl_writephy(tp, 0x0e, 0x0000);
3120         rtl_writephy(tp, 0x0d, 0x0000);
3121 }
3122
3123 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3124 {
3125         const u16 w[] = {
3126                 addr[0] | (addr[1] << 8),
3127                 addr[2] | (addr[3] << 8),
3128                 addr[4] | (addr[5] << 8)
3129         };
3130         const struct exgmac_reg e[] = {
3131                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3132                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3133                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3134                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3135         };
3136
3137         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3138 }
3139
3140 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3141 {
3142         static const struct phy_reg phy_reg_init[] = {
3143                 /* Enable Delay cap */
3144                 { 0x1f, 0x0004 },
3145                 { 0x1f, 0x0007 },
3146                 { 0x1e, 0x00ac },
3147                 { 0x18, 0x0006 },
3148                 { 0x1f, 0x0002 },
3149                 { 0x1f, 0x0000 },
3150                 { 0x1f, 0x0000 },
3151
3152                 /* Channel estimation fine tune */
3153                 { 0x1f, 0x0003 },
3154                 { 0x09, 0xa20f },
3155                 { 0x1f, 0x0000 },
3156                 { 0x1f, 0x0000 },
3157
3158                 /* Green Setting */
3159                 { 0x1f, 0x0005 },
3160                 { 0x05, 0x8b5b },
3161                 { 0x06, 0x9222 },
3162                 { 0x05, 0x8b6d },
3163                 { 0x06, 0x8000 },
3164                 { 0x05, 0x8b76 },
3165                 { 0x06, 0x8000 },
3166                 { 0x1f, 0x0000 }
3167         };
3168
3169         rtl_apply_firmware(tp);
3170
3171         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3172
3173         /* For 4-corner performance improve */
3174         rtl_writephy(tp, 0x1f, 0x0005);
3175         rtl_writephy(tp, 0x05, 0x8b80);
3176         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3177         rtl_writephy(tp, 0x1f, 0x0000);
3178
3179         /* PHY auto speed down */
3180         rtl_writephy(tp, 0x1f, 0x0004);
3181         rtl_writephy(tp, 0x1f, 0x0007);
3182         rtl_writephy(tp, 0x1e, 0x002d);
3183         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3184         rtl_writephy(tp, 0x1f, 0x0002);
3185         rtl_writephy(tp, 0x1f, 0x0000);
3186         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3187
3188         /* improve 10M EEE waveform */
3189         rtl_writephy(tp, 0x1f, 0x0005);
3190         rtl_writephy(tp, 0x05, 0x8b86);
3191         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3192         rtl_writephy(tp, 0x1f, 0x0000);
3193
3194         /* Improve 2-pair detection performance */
3195         rtl_writephy(tp, 0x1f, 0x0005);
3196         rtl_writephy(tp, 0x05, 0x8b85);
3197         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3198         rtl_writephy(tp, 0x1f, 0x0000);
3199
3200         /* EEE setting */
3201         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3202         rtl_writephy(tp, 0x1f, 0x0005);
3203         rtl_writephy(tp, 0x05, 0x8b85);
3204         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3205         rtl_writephy(tp, 0x1f, 0x0004);
3206         rtl_writephy(tp, 0x1f, 0x0007);
3207         rtl_writephy(tp, 0x1e, 0x0020);
3208         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3209         rtl_writephy(tp, 0x1f, 0x0002);
3210         rtl_writephy(tp, 0x1f, 0x0000);
3211         rtl_writephy(tp, 0x0d, 0x0007);
3212         rtl_writephy(tp, 0x0e, 0x003c);
3213         rtl_writephy(tp, 0x0d, 0x4007);
3214         rtl_writephy(tp, 0x0e, 0x0000);
3215         rtl_writephy(tp, 0x0d, 0x0000);
3216
3217         /* Green feature */
3218         rtl_writephy(tp, 0x1f, 0x0003);
3219         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3220         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3221         rtl_writephy(tp, 0x1f, 0x0000);
3222
3223         r8168_aldps_enable_1(tp);
3224
3225         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3226         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3227 }
3228
3229 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3230 {
3231         /* For 4-corner performance improve */
3232         rtl_writephy(tp, 0x1f, 0x0005);
3233         rtl_writephy(tp, 0x05, 0x8b80);
3234         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3235         rtl_writephy(tp, 0x1f, 0x0000);
3236
3237         /* PHY auto speed down */
3238         rtl_writephy(tp, 0x1f, 0x0007);
3239         rtl_writephy(tp, 0x1e, 0x002d);
3240         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3241         rtl_writephy(tp, 0x1f, 0x0000);
3242         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3243
3244         /* Improve 10M EEE waveform */
3245         rtl_writephy(tp, 0x1f, 0x0005);
3246         rtl_writephy(tp, 0x05, 0x8b86);
3247         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3248         rtl_writephy(tp, 0x1f, 0x0000);
3249 }
3250
3251 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3252 {
3253         static const struct phy_reg phy_reg_init[] = {
3254                 /* Channel estimation fine tune */
3255                 { 0x1f, 0x0003 },
3256                 { 0x09, 0xa20f },
3257                 { 0x1f, 0x0000 },
3258
3259                 /* Modify green table for giga & fnet */
3260                 { 0x1f, 0x0005 },
3261                 { 0x05, 0x8b55 },
3262                 { 0x06, 0x0000 },
3263                 { 0x05, 0x8b5e },
3264                 { 0x06, 0x0000 },
3265                 { 0x05, 0x8b67 },
3266                 { 0x06, 0x0000 },
3267                 { 0x05, 0x8b70 },
3268                 { 0x06, 0x0000 },
3269                 { 0x1f, 0x0000 },
3270                 { 0x1f, 0x0007 },
3271                 { 0x1e, 0x0078 },
3272                 { 0x17, 0x0000 },
3273                 { 0x19, 0x00fb },
3274                 { 0x1f, 0x0000 },
3275
3276                 /* Modify green table for 10M */
3277                 { 0x1f, 0x0005 },
3278                 { 0x05, 0x8b79 },
3279                 { 0x06, 0xaa00 },
3280                 { 0x1f, 0x0000 },
3281
3282                 /* Disable hiimpedance detection (RTCT) */
3283                 { 0x1f, 0x0003 },
3284                 { 0x01, 0x328a },
3285                 { 0x1f, 0x0000 }
3286         };
3287
3288         rtl_apply_firmware(tp);
3289
3290         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3291
3292         rtl8168f_hw_phy_config(tp);
3293
3294         /* Improve 2-pair detection performance */
3295         rtl_writephy(tp, 0x1f, 0x0005);
3296         rtl_writephy(tp, 0x05, 0x8b85);
3297         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3298         rtl_writephy(tp, 0x1f, 0x0000);
3299
3300         r8168_aldps_enable_1(tp);
3301 }
3302
3303 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3304 {
3305         rtl_apply_firmware(tp);
3306
3307         rtl8168f_hw_phy_config(tp);
3308
3309         r8168_aldps_enable_1(tp);
3310 }
3311
3312 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3313 {
3314         static const struct phy_reg phy_reg_init[] = {
3315                 /* Channel estimation fine tune */
3316                 { 0x1f, 0x0003 },
3317                 { 0x09, 0xa20f },
3318                 { 0x1f, 0x0000 },
3319
3320                 /* Modify green table for giga & fnet */
3321                 { 0x1f, 0x0005 },
3322                 { 0x05, 0x8b55 },
3323                 { 0x06, 0x0000 },
3324                 { 0x05, 0x8b5e },
3325                 { 0x06, 0x0000 },
3326                 { 0x05, 0x8b67 },
3327                 { 0x06, 0x0000 },
3328                 { 0x05, 0x8b70 },
3329                 { 0x06, 0x0000 },
3330                 { 0x1f, 0x0000 },
3331                 { 0x1f, 0x0007 },
3332                 { 0x1e, 0x0078 },
3333                 { 0x17, 0x0000 },
3334                 { 0x19, 0x00aa },
3335                 { 0x1f, 0x0000 },
3336
3337                 /* Modify green table for 10M */
3338                 { 0x1f, 0x0005 },
3339                 { 0x05, 0x8b79 },
3340                 { 0x06, 0xaa00 },
3341                 { 0x1f, 0x0000 },
3342
3343                 /* Disable hiimpedance detection (RTCT) */
3344                 { 0x1f, 0x0003 },
3345                 { 0x01, 0x328a },
3346                 { 0x1f, 0x0000 }
3347         };
3348
3349
3350         rtl_apply_firmware(tp);
3351
3352         rtl8168f_hw_phy_config(tp);
3353
3354         /* Improve 2-pair detection performance */
3355         rtl_writephy(tp, 0x1f, 0x0005);
3356         rtl_writephy(tp, 0x05, 0x8b85);
3357         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3358         rtl_writephy(tp, 0x1f, 0x0000);
3359
3360         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3361
3362         /* Modify green table for giga */
3363         rtl_writephy(tp, 0x1f, 0x0005);
3364         rtl_writephy(tp, 0x05, 0x8b54);
3365         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3366         rtl_writephy(tp, 0x05, 0x8b5d);
3367         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3368         rtl_writephy(tp, 0x05, 0x8a7c);
3369         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3370         rtl_writephy(tp, 0x05, 0x8a7f);
3371         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3372         rtl_writephy(tp, 0x05, 0x8a82);
3373         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3374         rtl_writephy(tp, 0x05, 0x8a85);
3375         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3376         rtl_writephy(tp, 0x05, 0x8a88);
3377         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3378         rtl_writephy(tp, 0x1f, 0x0000);
3379
3380         /* uc same-seed solution */
3381         rtl_writephy(tp, 0x1f, 0x0005);
3382         rtl_writephy(tp, 0x05, 0x8b85);
3383         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3384         rtl_writephy(tp, 0x1f, 0x0000);
3385
3386         /* eee setting */
3387         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3388         rtl_writephy(tp, 0x1f, 0x0005);
3389         rtl_writephy(tp, 0x05, 0x8b85);
3390         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3391         rtl_writephy(tp, 0x1f, 0x0004);
3392         rtl_writephy(tp, 0x1f, 0x0007);
3393         rtl_writephy(tp, 0x1e, 0x0020);
3394         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3395         rtl_writephy(tp, 0x1f, 0x0000);
3396         rtl_writephy(tp, 0x0d, 0x0007);
3397         rtl_writephy(tp, 0x0e, 0x003c);
3398         rtl_writephy(tp, 0x0d, 0x4007);
3399         rtl_writephy(tp, 0x0e, 0x0000);
3400         rtl_writephy(tp, 0x0d, 0x0000);
3401
3402         /* Green feature */
3403         rtl_writephy(tp, 0x1f, 0x0003);
3404         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3405         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3406         rtl_writephy(tp, 0x1f, 0x0000);
3407
3408         r8168_aldps_enable_1(tp);
3409 }
3410
3411 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3412 {
3413         static const u16 mac_ocp_patch[] = {
3414                 0xe008, 0xe01b, 0xe01d, 0xe01f,
3415                 0xe021, 0xe023, 0xe025, 0xe027,
3416                 0x49d2, 0xf10d, 0x766c, 0x49e2,
3417                 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
3418
3419                 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
3420                 0xc707, 0x8ee1, 0x9d6c, 0xc603,
3421                 0xbe00, 0xb416, 0x0076, 0xe86c,
3422                 0xc602, 0xbe00, 0x0000, 0xc602,
3423
3424                 0xbe00, 0x0000, 0xc602, 0xbe00,
3425                 0x0000, 0xc602, 0xbe00, 0x0000,
3426                 0xc602, 0xbe00, 0x0000, 0xc602,
3427                 0xbe00, 0x0000, 0xc602, 0xbe00,
3428
3429                 0x0000, 0x0000, 0x0000, 0x0000
3430         };
3431         u32 i;
3432
3433         /* Patch code for GPHY reset */
3434         for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
3435                 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
3436         r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
3437         r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
3438
3439         rtl_apply_firmware(tp);
3440
3441         if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3442                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3443         else
3444                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3445
3446         if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3447                 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3448         else
3449                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3450
3451         rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3452         rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3453
3454         r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3455         rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3456
3457         rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3458 }
3459
3460 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3461 {
3462         static const struct phy_reg phy_reg_init[] = {
3463                 { 0x1f, 0x0003 },
3464                 { 0x08, 0x441d },
3465                 { 0x01, 0x9100 },
3466                 { 0x1f, 0x0000 }
3467         };
3468
3469         rtl_writephy(tp, 0x1f, 0x0000);
3470         rtl_patchphy(tp, 0x11, 1 << 12);
3471         rtl_patchphy(tp, 0x19, 1 << 13);
3472         rtl_patchphy(tp, 0x10, 1 << 15);
3473
3474         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3475 }
3476
3477 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3478 {
3479         static const struct phy_reg phy_reg_init[] = {
3480                 { 0x1f, 0x0005 },
3481                 { 0x1a, 0x0000 },
3482                 { 0x1f, 0x0000 },
3483
3484                 { 0x1f, 0x0004 },
3485                 { 0x1c, 0x0000 },
3486                 { 0x1f, 0x0000 },
3487
3488                 { 0x1f, 0x0001 },
3489                 { 0x15, 0x7701 },
3490                 { 0x1f, 0x0000 }
3491         };
3492
3493         /* Disable ALDPS before ram code */
3494         r810x_aldps_disable(tp);
3495
3496         rtl_apply_firmware(tp);
3497
3498         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3499
3500         r810x_aldps_enable(tp);
3501 }
3502
3503 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3504 {
3505         /* Disable ALDPS before setting firmware */
3506         r810x_aldps_disable(tp);
3507
3508         rtl_apply_firmware(tp);
3509
3510         /* EEE setting */
3511         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3512         rtl_writephy(tp, 0x1f, 0x0004);
3513         rtl_writephy(tp, 0x10, 0x401f);
3514         rtl_writephy(tp, 0x19, 0x7030);
3515         rtl_writephy(tp, 0x1f, 0x0000);
3516
3517         r810x_aldps_enable(tp);
3518 }
3519
3520 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3521 {
3522         static const struct phy_reg phy_reg_init[] = {
3523                 { 0x1f, 0x0004 },
3524                 { 0x10, 0xc07f },
3525                 { 0x19, 0x7030 },
3526                 { 0x1f, 0x0000 }
3527         };
3528
3529         /* Disable ALDPS before ram code */
3530         r810x_aldps_disable(tp);
3531
3532         rtl_apply_firmware(tp);
3533
3534         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3535         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3536
3537         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3538
3539         r810x_aldps_enable(tp);
3540 }
3541
3542 static void rtl_hw_phy_config(struct net_device *dev)
3543 {
3544         struct rtl8169_private *tp = netdev_priv(dev);
3545
3546         rtl8169_print_mac_version(tp);
3547
3548         switch (tp->mac_version) {
3549         case RTL_GIGA_MAC_VER_01:
3550                 break;
3551         case RTL_GIGA_MAC_VER_02:
3552         case RTL_GIGA_MAC_VER_03:
3553                 rtl8169s_hw_phy_config(tp);
3554                 break;
3555         case RTL_GIGA_MAC_VER_04:
3556                 rtl8169sb_hw_phy_config(tp);
3557                 break;
3558         case RTL_GIGA_MAC_VER_05:
3559                 rtl8169scd_hw_phy_config(tp);
3560                 break;
3561         case RTL_GIGA_MAC_VER_06:
3562                 rtl8169sce_hw_phy_config(tp);
3563                 break;
3564         case RTL_GIGA_MAC_VER_07:
3565         case RTL_GIGA_MAC_VER_08:
3566         case RTL_GIGA_MAC_VER_09:
3567                 rtl8102e_hw_phy_config(tp);
3568                 break;
3569         case RTL_GIGA_MAC_VER_11:
3570                 rtl8168bb_hw_phy_config(tp);
3571                 break;
3572         case RTL_GIGA_MAC_VER_12:
3573                 rtl8168bef_hw_phy_config(tp);
3574                 break;
3575         case RTL_GIGA_MAC_VER_17:
3576                 rtl8168bef_hw_phy_config(tp);
3577                 break;
3578         case RTL_GIGA_MAC_VER_18:
3579                 rtl8168cp_1_hw_phy_config(tp);
3580                 break;
3581         case RTL_GIGA_MAC_VER_19:
3582                 rtl8168c_1_hw_phy_config(tp);
3583                 break;
3584         case RTL_GIGA_MAC_VER_20:
3585                 rtl8168c_2_hw_phy_config(tp);
3586                 break;
3587         case RTL_GIGA_MAC_VER_21:
3588                 rtl8168c_3_hw_phy_config(tp);
3589                 break;
3590         case RTL_GIGA_MAC_VER_22:
3591                 rtl8168c_4_hw_phy_config(tp);
3592                 break;
3593         case RTL_GIGA_MAC_VER_23:
3594         case RTL_GIGA_MAC_VER_24:
3595                 rtl8168cp_2_hw_phy_config(tp);
3596                 break;
3597         case RTL_GIGA_MAC_VER_25:
3598                 rtl8168d_1_hw_phy_config(tp);
3599                 break;
3600         case RTL_GIGA_MAC_VER_26:
3601                 rtl8168d_2_hw_phy_config(tp);
3602                 break;
3603         case RTL_GIGA_MAC_VER_27:
3604                 rtl8168d_3_hw_phy_config(tp);
3605                 break;
3606         case RTL_GIGA_MAC_VER_28:
3607                 rtl8168d_4_hw_phy_config(tp);
3608                 break;
3609         case RTL_GIGA_MAC_VER_29:
3610         case RTL_GIGA_MAC_VER_30:
3611                 rtl8105e_hw_phy_config(tp);
3612                 break;
3613         case RTL_GIGA_MAC_VER_31:
3614                 /* None. */
3615                 break;
3616         case RTL_GIGA_MAC_VER_32:
3617         case RTL_GIGA_MAC_VER_33:
3618                 rtl8168e_1_hw_phy_config(tp);
3619                 break;
3620         case RTL_GIGA_MAC_VER_34:
3621                 rtl8168e_2_hw_phy_config(tp);
3622                 break;
3623         case RTL_GIGA_MAC_VER_35:
3624                 rtl8168f_1_hw_phy_config(tp);
3625                 break;
3626         case RTL_GIGA_MAC_VER_36:
3627                 rtl8168f_2_hw_phy_config(tp);
3628                 break;
3629
3630         case RTL_GIGA_MAC_VER_37:
3631                 rtl8402_hw_phy_config(tp);
3632                 break;
3633
3634         case RTL_GIGA_MAC_VER_38:
3635                 rtl8411_hw_phy_config(tp);
3636                 break;
3637
3638         case RTL_GIGA_MAC_VER_39:
3639                 rtl8106e_hw_phy_config(tp);
3640                 break;
3641
3642         case RTL_GIGA_MAC_VER_40:
3643                 rtl8168g_1_hw_phy_config(tp);
3644                 break;
3645
3646         case RTL_GIGA_MAC_VER_41:
3647         default:
3648                 break;
3649         }
3650 }
3651
3652 static void rtl_phy_work(struct rtl8169_private *tp)
3653 {
3654         struct timer_list *timer = &tp->timer;
3655         void __iomem *ioaddr = tp->mmio_addr;
3656         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3657
3658         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3659
3660         if (tp->phy_reset_pending(tp)) {
3661                 /*
3662                  * A busy loop could burn quite a few cycles on nowadays CPU.
3663                  * Let's delay the execution of the timer for a few ticks.
3664                  */
3665                 timeout = HZ/10;
3666                 goto out_mod_timer;
3667         }
3668
3669         if (tp->link_ok(ioaddr))
3670                 return;
3671
3672         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3673
3674         tp->phy_reset_enable(tp);
3675
3676 out_mod_timer:
3677         mod_timer(timer, jiffies + timeout);
3678 }
3679
3680 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3681 {
3682         if (!test_and_set_bit(flag, tp->wk.flags))
3683                 schedule_work(&tp->wk.work);
3684 }
3685
3686 static void rtl8169_phy_timer(unsigned long __opaque)
3687 {
3688         struct net_device *dev = (struct net_device *)__opaque;
3689         struct rtl8169_private *tp = netdev_priv(dev);
3690
3691         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3692 }
3693
3694 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3695                                   void __iomem *ioaddr)
3696 {
3697         iounmap(ioaddr);
3698         pci_release_regions(pdev);
3699         pci_clear_mwi(pdev);
3700         pci_disable_device(pdev);
3701         free_netdev(dev);
3702 }
3703
3704 DECLARE_RTL_COND(rtl_phy_reset_cond)
3705 {
3706         return tp->phy_reset_pending(tp);
3707 }
3708
3709 static void rtl8169_phy_reset(struct net_device *dev,
3710                               struct rtl8169_private *tp)
3711 {
3712         tp->phy_reset_enable(tp);
3713         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3714 }
3715
3716 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3717 {
3718         void __iomem *ioaddr = tp->mmio_addr;
3719
3720         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3721             (RTL_R8(PHYstatus) & TBI_Enable);
3722 }
3723
3724 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3725 {
3726         void __iomem *ioaddr = tp->mmio_addr;
3727
3728         rtl_hw_phy_config(dev);
3729
3730         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3731                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3732