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gianfar: do vlan cleanup
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1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12  *
13  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
14  * Copyright 2007 MontaVista Software, Inc.
15  *
16  * This program is free software; you can redistribute  it and/or modify it
17  * under  the terms of  the GNU General  Public License as published by the
18  * Free Software Foundation;  either version 2 of the  License, or (at your
19  * option) any later version.
20  *
21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
22  *  RA 11 31 24.2
23  *  Dec +69 19 52
24  *  V 3.84
25  *  B-V +1.62
26  *
27  *  Theory of operation
28  *
29  *  The driver is initialized through of_device. Configuration information
30  *  is therefore conveyed through an OF-style device tree.
31  *
32  *  The Gianfar Ethernet Controller uses a ring of buffer
33  *  descriptors.  The beginning is indicated by a register
34  *  pointing to the physical address of the start of the ring.
35  *  The end is determined by a "wrap" bit being set in the
36  *  last descriptor of the ring.
37  *
38  *  When a packet is received, the RXF bit in the
39  *  IEVENT register is set, triggering an interrupt when the
40  *  corresponding bit in the IMASK register is also set (if
41  *  interrupt coalescing is active, then the interrupt may not
42  *  happen immediately, but will wait until either a set number
43  *  of frames or amount of time have passed).  In NAPI, the
44  *  interrupt handler will signal there is work to be done, and
45  *  exit. This method will start at the last known empty
46  *  descriptor, and process every subsequent descriptor until there
47  *  are none left with data (NAPI will stop after a set number of
48  *  packets to give time to other tasks, but will eventually
49  *  process all the packets).  The data arrives inside a
50  *  pre-allocated skb, and so after the skb is passed up to the
51  *  stack, a new skb must be allocated, and the address field in
52  *  the buffer descriptor must be updated to indicate this new
53  *  skb.
54  *
55  *  When the kernel requests that a packet be transmitted, the
56  *  driver starts where it left off last time, and points the
57  *  descriptor at the buffer which was passed in.  The driver
58  *  then informs the DMA engine that there are packets ready to
59  *  be transmitted.  Once the controller is finished transmitting
60  *  the packet, an interrupt may be triggered (under the same
61  *  conditions as for reception, but depending on the TXF bit).
62  *  The driver then cleans up the buffer.
63  */
64
65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66 #define DEBUG
67
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
81 #include <linux/mm.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
84 #include <linux/ip.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
87 #include <linux/in.h>
88 #include <linux/net_tstamp.h>
89
90 #include <asm/io.h>
91 #include <asm/reg.h>
92 #include <asm/irq.h>
93 #include <asm/uaccess.h>
94 #include <linux/module.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/crc32.h>
97 #include <linux/mii.h>
98 #include <linux/phy.h>
99 #include <linux/phy_fixed.h>
100 #include <linux/of.h>
101 #include <linux/of_net.h>
102
103 #include "gianfar.h"
104 #include "fsl_pq_mdio.h"
105
106 #define TX_TIMEOUT      (1*HZ)
107 #undef BRIEF_GFAR_ERRORS
108 #undef VERBOSE_GFAR_ERRORS
109
110 const char gfar_driver_name[] = "Gianfar Ethernet";
111 const char gfar_driver_version[] = "1.3";
112
113 static int gfar_enet_open(struct net_device *dev);
114 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
115 static void gfar_reset_task(struct work_struct *work);
116 static void gfar_timeout(struct net_device *dev);
117 static int gfar_close(struct net_device *dev);
118 struct sk_buff *gfar_new_skb(struct net_device *dev);
119 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
120                 struct sk_buff *skb);
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static void init_registers(struct net_device *dev);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll(struct napi_struct *napi, int budget);
136 #ifdef CONFIG_NET_POLL_CONTROLLER
137 static void gfar_netpoll(struct net_device *dev);
138 #endif
139 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
140 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
141 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
142                               int amount_pull);
143 void gfar_halt(struct net_device *dev);
144 static void gfar_halt_nodisable(struct net_device *dev);
145 void gfar_start(struct net_device *dev);
146 static void gfar_clear_exact_match(struct net_device *dev);
147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
148                                   const u8 *addr);
149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
150
151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
153 MODULE_LICENSE("GPL");
154
155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
156                             dma_addr_t buf)
157 {
158         u32 lstatus;
159
160         bdp->bufPtr = buf;
161
162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
164                 lstatus |= BD_LFLAG(RXBD_WRAP);
165
166         eieio();
167
168         bdp->lstatus = lstatus;
169 }
170
171 static int gfar_init_bds(struct net_device *ndev)
172 {
173         struct gfar_private *priv = netdev_priv(ndev);
174         struct gfar_priv_tx_q *tx_queue = NULL;
175         struct gfar_priv_rx_q *rx_queue = NULL;
176         struct txbd8 *txbdp;
177         struct rxbd8 *rxbdp;
178         int i, j;
179
180         for (i = 0; i < priv->num_tx_queues; i++) {
181                 tx_queue = priv->tx_queue[i];
182                 /* Initialize some variables in our dev structure */
183                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
184                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
185                 tx_queue->cur_tx = tx_queue->tx_bd_base;
186                 tx_queue->skb_curtx = 0;
187                 tx_queue->skb_dirtytx = 0;
188
189                 /* Initialize Transmit Descriptor Ring */
190                 txbdp = tx_queue->tx_bd_base;
191                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
192                         txbdp->lstatus = 0;
193                         txbdp->bufPtr = 0;
194                         txbdp++;
195                 }
196
197                 /* Set the last descriptor in the ring to indicate wrap */
198                 txbdp--;
199                 txbdp->status |= TXBD_WRAP;
200         }
201
202         for (i = 0; i < priv->num_rx_queues; i++) {
203                 rx_queue = priv->rx_queue[i];
204                 rx_queue->cur_rx = rx_queue->rx_bd_base;
205                 rx_queue->skb_currx = 0;
206                 rxbdp = rx_queue->rx_bd_base;
207
208                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
209                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
210
211                         if (skb) {
212                                 gfar_init_rxbdp(rx_queue, rxbdp,
213                                                 rxbdp->bufPtr);
214                         } else {
215                                 skb = gfar_new_skb(ndev);
216                                 if (!skb) {
217                                         netdev_err(ndev, "Can't allocate RX buffers\n");
218                                         goto err_rxalloc_fail;
219                                 }
220                                 rx_queue->rx_skbuff[j] = skb;
221
222                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
223                         }
224
225                         rxbdp++;
226                 }
227
228         }
229
230         return 0;
231
232 err_rxalloc_fail:
233         free_skb_resources(priv);
234         return -ENOMEM;
235 }
236
237 static int gfar_alloc_skb_resources(struct net_device *ndev)
238 {
239         void *vaddr;
240         dma_addr_t addr;
241         int i, j, k;
242         struct gfar_private *priv = netdev_priv(ndev);
243         struct device *dev = &priv->ofdev->dev;
244         struct gfar_priv_tx_q *tx_queue = NULL;
245         struct gfar_priv_rx_q *rx_queue = NULL;
246
247         priv->total_tx_ring_size = 0;
248         for (i = 0; i < priv->num_tx_queues; i++)
249                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
250
251         priv->total_rx_ring_size = 0;
252         for (i = 0; i < priv->num_rx_queues; i++)
253                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
254
255         /* Allocate memory for the buffer descriptors */
256         vaddr = dma_alloc_coherent(dev,
257                         sizeof(struct txbd8) * priv->total_tx_ring_size +
258                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
259                         &addr, GFP_KERNEL);
260         if (!vaddr) {
261                 netif_err(priv, ifup, ndev,
262                           "Could not allocate buffer descriptors!\n");
263                 return -ENOMEM;
264         }
265
266         for (i = 0; i < priv->num_tx_queues; i++) {
267                 tx_queue = priv->tx_queue[i];
268                 tx_queue->tx_bd_base = vaddr;
269                 tx_queue->tx_bd_dma_base = addr;
270                 tx_queue->dev = ndev;
271                 /* enet DMA only understands physical addresses */
272                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
274         }
275
276         /* Start the rx descriptor ring where the tx ring leaves off */
277         for (i = 0; i < priv->num_rx_queues; i++) {
278                 rx_queue = priv->rx_queue[i];
279                 rx_queue->rx_bd_base = vaddr;
280                 rx_queue->rx_bd_dma_base = addr;
281                 rx_queue->dev = ndev;
282                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
284         }
285
286         /* Setup the skbuff rings */
287         for (i = 0; i < priv->num_tx_queues; i++) {
288                 tx_queue = priv->tx_queue[i];
289                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
290                                   tx_queue->tx_ring_size, GFP_KERNEL);
291                 if (!tx_queue->tx_skbuff) {
292                         netif_err(priv, ifup, ndev,
293                                   "Could not allocate tx_skbuff\n");
294                         goto cleanup;
295                 }
296
297                 for (k = 0; k < tx_queue->tx_ring_size; k++)
298                         tx_queue->tx_skbuff[k] = NULL;
299         }
300
301         for (i = 0; i < priv->num_rx_queues; i++) {
302                 rx_queue = priv->rx_queue[i];
303                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
304                                   rx_queue->rx_ring_size, GFP_KERNEL);
305
306                 if (!rx_queue->rx_skbuff) {
307                         netif_err(priv, ifup, ndev,
308                                   "Could not allocate rx_skbuff\n");
309                         goto cleanup;
310                 }
311
312                 for (j = 0; j < rx_queue->rx_ring_size; j++)
313                         rx_queue->rx_skbuff[j] = NULL;
314         }
315
316         if (gfar_init_bds(ndev))
317                 goto cleanup;
318
319         return 0;
320
321 cleanup:
322         free_skb_resources(priv);
323         return -ENOMEM;
324 }
325
326 static void gfar_init_tx_rx_base(struct gfar_private *priv)
327 {
328         struct gfar __iomem *regs = priv->gfargrp[0].regs;
329         u32 __iomem *baddr;
330         int i;
331
332         baddr = &regs->tbase0;
333         for(i = 0; i < priv->num_tx_queues; i++) {
334                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
335                 baddr   += 2;
336         }
337
338         baddr = &regs->rbase0;
339         for(i = 0; i < priv->num_rx_queues; i++) {
340                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
341                 baddr   += 2;
342         }
343 }
344
345 static void gfar_init_mac(struct net_device *ndev)
346 {
347         struct gfar_private *priv = netdev_priv(ndev);
348         struct gfar __iomem *regs = priv->gfargrp[0].regs;
349         u32 rctrl = 0;
350         u32 tctrl = 0;
351         u32 attrs = 0;
352
353         /* write the tx/rx base registers */
354         gfar_init_tx_rx_base(priv);
355
356         /* Configure the coalescing support */
357         gfar_configure_coalescing(priv, 0xFF, 0xFF);
358
359         if (priv->rx_filer_enable) {
360                 rctrl |= RCTRL_FILREN;
361                 /* Program the RIR0 reg with the required distribution */
362                 gfar_write(&regs->rir0, DEFAULT_RIR0);
363         }
364
365         if (ndev->features & NETIF_F_RXCSUM)
366                 rctrl |= RCTRL_CHECKSUMMING;
367
368         if (priv->extended_hash) {
369                 rctrl |= RCTRL_EXTHASH;
370
371                 gfar_clear_exact_match(ndev);
372                 rctrl |= RCTRL_EMEN;
373         }
374
375         if (priv->padding) {
376                 rctrl &= ~RCTRL_PAL_MASK;
377                 rctrl |= RCTRL_PADDING(priv->padding);
378         }
379
380         /* Insert receive time stamps into padding alignment bytes */
381         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
382                 rctrl &= ~RCTRL_PAL_MASK;
383                 rctrl |= RCTRL_PADDING(8);
384                 priv->padding = 8;
385         }
386
387         /* Enable HW time stamping if requested from user space */
388         if (priv->hwts_rx_en)
389                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
390
391         /* keep vlan related bits if it's enabled */
392         if (ndev->features & NETIF_F_HW_VLAN_TX)
393                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
394
395         if (ndev->features & NETIF_F_HW_VLAN_RX)
396                 tctrl |= TCTRL_VLINS;
397
398         /* Init rctrl based on our settings */
399         gfar_write(&regs->rctrl, rctrl);
400
401         if (ndev->features & NETIF_F_IP_CSUM)
402                 tctrl |= TCTRL_INIT_CSUM;
403
404         tctrl |= TCTRL_TXSCHED_PRIO;
405
406         gfar_write(&regs->tctrl, tctrl);
407
408         /* Set the extraction length and index */
409         attrs = ATTRELI_EL(priv->rx_stash_size) |
410                 ATTRELI_EI(priv->rx_stash_index);
411
412         gfar_write(&regs->attreli, attrs);
413
414         /* Start with defaults, and add stashing or locking
415          * depending on the approprate variables */
416         attrs = ATTR_INIT_SETTINGS;
417
418         if (priv->bd_stash_en)
419                 attrs |= ATTR_BDSTASH;
420
421         if (priv->rx_stash_size != 0)
422                 attrs |= ATTR_BUFSTASH;
423
424         gfar_write(&regs->attr, attrs);
425
426         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
427         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
428         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
429 }
430
431 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
432 {
433         struct gfar_private *priv = netdev_priv(dev);
434         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
435         unsigned long tx_packets = 0, tx_bytes = 0;
436         int i = 0;
437
438         for (i = 0; i < priv->num_rx_queues; i++) {
439                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
440                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
441                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
442         }
443
444         dev->stats.rx_packets = rx_packets;
445         dev->stats.rx_bytes = rx_bytes;
446         dev->stats.rx_dropped = rx_dropped;
447
448         for (i = 0; i < priv->num_tx_queues; i++) {
449                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
450                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
451         }
452
453         dev->stats.tx_bytes = tx_bytes;
454         dev->stats.tx_packets = tx_packets;
455
456         return &dev->stats;
457 }
458
459 static const struct net_device_ops gfar_netdev_ops = {
460         .ndo_open = gfar_enet_open,
461         .ndo_start_xmit = gfar_start_xmit,
462         .ndo_stop = gfar_close,
463         .ndo_change_mtu = gfar_change_mtu,
464         .ndo_set_features = gfar_set_features,
465         .ndo_set_multicast_list = gfar_set_multi,
466         .ndo_tx_timeout = gfar_timeout,
467         .ndo_do_ioctl = gfar_ioctl,
468         .ndo_get_stats = gfar_get_stats,
469         .ndo_set_mac_address = eth_mac_addr,
470         .ndo_validate_addr = eth_validate_addr,
471 #ifdef CONFIG_NET_POLL_CONTROLLER
472         .ndo_poll_controller = gfar_netpoll,
473 #endif
474 };
475
476 void lock_rx_qs(struct gfar_private *priv)
477 {
478         int i = 0x0;
479
480         for (i = 0; i < priv->num_rx_queues; i++)
481                 spin_lock(&priv->rx_queue[i]->rxlock);
482 }
483
484 void lock_tx_qs(struct gfar_private *priv)
485 {
486         int i = 0x0;
487
488         for (i = 0; i < priv->num_tx_queues; i++)
489                 spin_lock(&priv->tx_queue[i]->txlock);
490 }
491
492 void unlock_rx_qs(struct gfar_private *priv)
493 {
494         int i = 0x0;
495
496         for (i = 0; i < priv->num_rx_queues; i++)
497                 spin_unlock(&priv->rx_queue[i]->rxlock);
498 }
499
500 void unlock_tx_qs(struct gfar_private *priv)
501 {
502         int i = 0x0;
503
504         for (i = 0; i < priv->num_tx_queues; i++)
505                 spin_unlock(&priv->tx_queue[i]->txlock);
506 }
507
508 static bool gfar_is_vlan_on(struct gfar_private *priv)
509 {
510         return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
511                (priv->ndev->features & NETIF_F_HW_VLAN_TX);
512 }
513
514 /* Returns 1 if incoming frames use an FCB */
515 static inline int gfar_uses_fcb(struct gfar_private *priv)
516 {
517         return gfar_is_vlan_on(priv) ||
518                 (priv->ndev->features & NETIF_F_RXCSUM) ||
519                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
520 }
521
522 static void free_tx_pointers(struct gfar_private *priv)
523 {
524         int i = 0;
525
526         for (i = 0; i < priv->num_tx_queues; i++)
527                 kfree(priv->tx_queue[i]);
528 }
529
530 static void free_rx_pointers(struct gfar_private *priv)
531 {
532         int i = 0;
533
534         for (i = 0; i < priv->num_rx_queues; i++)
535                 kfree(priv->rx_queue[i]);
536 }
537
538 static void unmap_group_regs(struct gfar_private *priv)
539 {
540         int i = 0;
541
542         for (i = 0; i < MAXGROUPS; i++)
543                 if (priv->gfargrp[i].regs)
544                         iounmap(priv->gfargrp[i].regs);
545 }
546
547 static void disable_napi(struct gfar_private *priv)
548 {
549         int i = 0;
550
551         for (i = 0; i < priv->num_grps; i++)
552                 napi_disable(&priv->gfargrp[i].napi);
553 }
554
555 static void enable_napi(struct gfar_private *priv)
556 {
557         int i = 0;
558
559         for (i = 0; i < priv->num_grps; i++)
560                 napi_enable(&priv->gfargrp[i].napi);
561 }
562
563 static int gfar_parse_group(struct device_node *np,
564                 struct gfar_private *priv, const char *model)
565 {
566         u32 *queue_mask;
567
568         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
569         if (!priv->gfargrp[priv->num_grps].regs)
570                 return -ENOMEM;
571
572         priv->gfargrp[priv->num_grps].interruptTransmit =
573                         irq_of_parse_and_map(np, 0);
574
575         /* If we aren't the FEC we have multiple interrupts */
576         if (model && strcasecmp(model, "FEC")) {
577                 priv->gfargrp[priv->num_grps].interruptReceive =
578                         irq_of_parse_and_map(np, 1);
579                 priv->gfargrp[priv->num_grps].interruptError =
580                         irq_of_parse_and_map(np,2);
581                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
582                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
583                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
584                         return -EINVAL;
585         }
586
587         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
588         priv->gfargrp[priv->num_grps].priv = priv;
589         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
590         if(priv->mode == MQ_MG_MODE) {
591                 queue_mask = (u32 *)of_get_property(np,
592                                         "fsl,rx-bit-map", NULL);
593                 priv->gfargrp[priv->num_grps].rx_bit_map =
594                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
595                 queue_mask = (u32 *)of_get_property(np,
596                                         "fsl,tx-bit-map", NULL);
597                 priv->gfargrp[priv->num_grps].tx_bit_map =
598                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
599         } else {
600                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
601                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
602         }
603         priv->num_grps++;
604
605         return 0;
606 }
607
608 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
609 {
610         const char *model;
611         const char *ctype;
612         const void *mac_addr;
613         int err = 0, i;
614         struct net_device *dev = NULL;
615         struct gfar_private *priv = NULL;
616         struct device_node *np = ofdev->dev.of_node;
617         struct device_node *child = NULL;
618         const u32 *stash;
619         const u32 *stash_len;
620         const u32 *stash_idx;
621         unsigned int num_tx_qs, num_rx_qs;
622         u32 *tx_queues, *rx_queues;
623
624         if (!np || !of_device_is_available(np))
625                 return -ENODEV;
626
627         /* parse the num of tx and rx queues */
628         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
629         num_tx_qs = tx_queues ? *tx_queues : 1;
630
631         if (num_tx_qs > MAX_TX_QS) {
632                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
633                        num_tx_qs, MAX_TX_QS);
634                 pr_err("Cannot do alloc_etherdev, aborting\n");
635                 return -EINVAL;
636         }
637
638         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
639         num_rx_qs = rx_queues ? *rx_queues : 1;
640
641         if (num_rx_qs > MAX_RX_QS) {
642                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
643                        num_rx_qs, MAX_RX_QS);
644                 pr_err("Cannot do alloc_etherdev, aborting\n");
645                 return -EINVAL;
646         }
647
648         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
649         dev = *pdev;
650         if (NULL == dev)
651                 return -ENOMEM;
652
653         priv = netdev_priv(dev);
654         priv->node = ofdev->dev.of_node;
655         priv->ndev = dev;
656
657         priv->num_tx_queues = num_tx_qs;
658         netif_set_real_num_rx_queues(dev, num_rx_qs);
659         priv->num_rx_queues = num_rx_qs;
660         priv->num_grps = 0x0;
661
662         /* Init Rx queue filer rule set linked list*/
663         INIT_LIST_HEAD(&priv->rx_list.list);
664         priv->rx_list.count = 0;
665         mutex_init(&priv->rx_queue_access);
666
667         model = of_get_property(np, "model", NULL);
668
669         for (i = 0; i < MAXGROUPS; i++)
670                 priv->gfargrp[i].regs = NULL;
671
672         /* Parse and initialize group specific information */
673         if (of_device_is_compatible(np, "fsl,etsec2")) {
674                 priv->mode = MQ_MG_MODE;
675                 for_each_child_of_node(np, child) {
676                         err = gfar_parse_group(child, priv, model);
677                         if (err)
678                                 goto err_grp_init;
679                 }
680         } else {
681                 priv->mode = SQ_SG_MODE;
682                 err = gfar_parse_group(np, priv, model);
683                 if(err)
684                         goto err_grp_init;
685         }
686
687         for (i = 0; i < priv->num_tx_queues; i++)
688                priv->tx_queue[i] = NULL;
689         for (i = 0; i < priv->num_rx_queues; i++)
690                 priv->rx_queue[i] = NULL;
691
692         for (i = 0; i < priv->num_tx_queues; i++) {
693                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
694                                             GFP_KERNEL);
695                 if (!priv->tx_queue[i]) {
696                         err = -ENOMEM;
697                         goto tx_alloc_failed;
698                 }
699                 priv->tx_queue[i]->tx_skbuff = NULL;
700                 priv->tx_queue[i]->qindex = i;
701                 priv->tx_queue[i]->dev = dev;
702                 spin_lock_init(&(priv->tx_queue[i]->txlock));
703         }
704
705         for (i = 0; i < priv->num_rx_queues; i++) {
706                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
707                                             GFP_KERNEL);
708                 if (!priv->rx_queue[i]) {
709                         err = -ENOMEM;
710                         goto rx_alloc_failed;
711                 }
712                 priv->rx_queue[i]->rx_skbuff = NULL;
713                 priv->rx_queue[i]->qindex = i;
714                 priv->rx_queue[i]->dev = dev;
715                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
716         }
717
718
719         stash = of_get_property(np, "bd-stash", NULL);
720
721         if (stash) {
722                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
723                 priv->bd_stash_en = 1;
724         }
725
726         stash_len = of_get_property(np, "rx-stash-len", NULL);
727
728         if (stash_len)
729                 priv->rx_stash_size = *stash_len;
730
731         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
732
733         if (stash_idx)
734                 priv->rx_stash_index = *stash_idx;
735
736         if (stash_len || stash_idx)
737                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
738
739         mac_addr = of_get_mac_address(np);
740         if (mac_addr)
741                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
742
743         if (model && !strcasecmp(model, "TSEC"))
744                 priv->device_flags =
745                         FSL_GIANFAR_DEV_HAS_GIGABIT |
746                         FSL_GIANFAR_DEV_HAS_COALESCE |
747                         FSL_GIANFAR_DEV_HAS_RMON |
748                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
749         if (model && !strcasecmp(model, "eTSEC"))
750                 priv->device_flags =
751                         FSL_GIANFAR_DEV_HAS_GIGABIT |
752                         FSL_GIANFAR_DEV_HAS_COALESCE |
753                         FSL_GIANFAR_DEV_HAS_RMON |
754                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
755                         FSL_GIANFAR_DEV_HAS_PADDING |
756                         FSL_GIANFAR_DEV_HAS_CSUM |
757                         FSL_GIANFAR_DEV_HAS_VLAN |
758                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
759                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
760                         FSL_GIANFAR_DEV_HAS_TIMER;
761
762         ctype = of_get_property(np, "phy-connection-type", NULL);
763
764         /* We only care about rgmii-id.  The rest are autodetected */
765         if (ctype && !strcmp(ctype, "rgmii-id"))
766                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
767         else
768                 priv->interface = PHY_INTERFACE_MODE_MII;
769
770         if (of_get_property(np, "fsl,magic-packet", NULL))
771                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
772
773         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
774
775         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
776         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
777
778         return 0;
779
780 rx_alloc_failed:
781         free_rx_pointers(priv);
782 tx_alloc_failed:
783         free_tx_pointers(priv);
784 err_grp_init:
785         unmap_group_regs(priv);
786         free_netdev(dev);
787         return err;
788 }
789
790 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
791                         struct ifreq *ifr, int cmd)
792 {
793         struct hwtstamp_config config;
794         struct gfar_private *priv = netdev_priv(netdev);
795
796         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
797                 return -EFAULT;
798
799         /* reserved for future extensions */
800         if (config.flags)
801                 return -EINVAL;
802
803         switch (config.tx_type) {
804         case HWTSTAMP_TX_OFF:
805                 priv->hwts_tx_en = 0;
806                 break;
807         case HWTSTAMP_TX_ON:
808                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
809                         return -ERANGE;
810                 priv->hwts_tx_en = 1;
811                 break;
812         default:
813                 return -ERANGE;
814         }
815
816         switch (config.rx_filter) {
817         case HWTSTAMP_FILTER_NONE:
818                 if (priv->hwts_rx_en) {
819                         stop_gfar(netdev);
820                         priv->hwts_rx_en = 0;
821                         startup_gfar(netdev);
822                 }
823                 break;
824         default:
825                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
826                         return -ERANGE;
827                 if (!priv->hwts_rx_en) {
828                         stop_gfar(netdev);
829                         priv->hwts_rx_en = 1;
830                         startup_gfar(netdev);
831                 }
832                 config.rx_filter = HWTSTAMP_FILTER_ALL;
833                 break;
834         }
835
836         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
837                 -EFAULT : 0;
838 }
839
840 /* Ioctl MII Interface */
841 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
842 {
843         struct gfar_private *priv = netdev_priv(dev);
844
845         if (!netif_running(dev))
846                 return -EINVAL;
847
848         if (cmd == SIOCSHWTSTAMP)
849                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
850
851         if (!priv->phydev)
852                 return -ENODEV;
853
854         return phy_mii_ioctl(priv->phydev, rq, cmd);
855 }
856
857 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
858 {
859         unsigned int new_bit_map = 0x0;
860         int mask = 0x1 << (max_qs - 1), i;
861         for (i = 0; i < max_qs; i++) {
862                 if (bit_map & mask)
863                         new_bit_map = new_bit_map + (1 << i);
864                 mask = mask >> 0x1;
865         }
866         return new_bit_map;
867 }
868
869 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
870                                    u32 class)
871 {
872         u32 rqfpr = FPR_FILER_MASK;
873         u32 rqfcr = 0x0;
874
875         rqfar--;
876         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
877         priv->ftp_rqfpr[rqfar] = rqfpr;
878         priv->ftp_rqfcr[rqfar] = rqfcr;
879         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
880
881         rqfar--;
882         rqfcr = RQFCR_CMP_NOMATCH;
883         priv->ftp_rqfpr[rqfar] = rqfpr;
884         priv->ftp_rqfcr[rqfar] = rqfcr;
885         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
886
887         rqfar--;
888         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
889         rqfpr = class;
890         priv->ftp_rqfcr[rqfar] = rqfcr;
891         priv->ftp_rqfpr[rqfar] = rqfpr;
892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
893
894         rqfar--;
895         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
896         rqfpr = class;
897         priv->ftp_rqfcr[rqfar] = rqfcr;
898         priv->ftp_rqfpr[rqfar] = rqfpr;
899         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
900
901         return rqfar;
902 }
903
904 static void gfar_init_filer_table(struct gfar_private *priv)
905 {
906         int i = 0x0;
907         u32 rqfar = MAX_FILER_IDX;
908         u32 rqfcr = 0x0;
909         u32 rqfpr = FPR_FILER_MASK;
910
911         /* Default rule */
912         rqfcr = RQFCR_CMP_MATCH;
913         priv->ftp_rqfcr[rqfar] = rqfcr;
914         priv->ftp_rqfpr[rqfar] = rqfpr;
915         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
916
917         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
918         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
919         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
920         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
921         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
922         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
923
924         /* cur_filer_idx indicated the first non-masked rule */
925         priv->cur_filer_idx = rqfar;
926
927         /* Rest are masked rules */
928         rqfcr = RQFCR_CMP_NOMATCH;
929         for (i = 0; i < rqfar; i++) {
930                 priv->ftp_rqfcr[i] = rqfcr;
931                 priv->ftp_rqfpr[i] = rqfpr;
932                 gfar_write_filer(priv, i, rqfcr, rqfpr);
933         }
934 }
935
936 static void gfar_detect_errata(struct gfar_private *priv)
937 {
938         struct device *dev = &priv->ofdev->dev;
939         unsigned int pvr = mfspr(SPRN_PVR);
940         unsigned int svr = mfspr(SPRN_SVR);
941         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
942         unsigned int rev = svr & 0xffff;
943
944         /* MPC8313 Rev 2.0 and higher; All MPC837x */
945         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
946                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
947                 priv->errata |= GFAR_ERRATA_74;
948
949         /* MPC8313 and MPC837x all rev */
950         if ((pvr == 0x80850010 && mod == 0x80b0) ||
951                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
952                 priv->errata |= GFAR_ERRATA_76;
953
954         /* MPC8313 and MPC837x all rev */
955         if ((pvr == 0x80850010 && mod == 0x80b0) ||
956                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
957                 priv->errata |= GFAR_ERRATA_A002;
958
959         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
960         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
961                         (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
962                 priv->errata |= GFAR_ERRATA_12;
963
964         if (priv->errata)
965                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
966                          priv->errata);
967 }
968
969 /* Set up the ethernet device structure, private data,
970  * and anything else we need before we start */
971 static int gfar_probe(struct platform_device *ofdev)
972 {
973         u32 tempval;
974         struct net_device *dev = NULL;
975         struct gfar_private *priv = NULL;
976         struct gfar __iomem *regs = NULL;
977         int err = 0, i, grp_idx = 0;
978         int len_devname;
979         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
980         u32 isrg = 0;
981         u32 __iomem *baddr;
982
983         err = gfar_of_init(ofdev, &dev);
984
985         if (err)
986                 return err;
987
988         priv = netdev_priv(dev);
989         priv->ndev = dev;
990         priv->ofdev = ofdev;
991         priv->node = ofdev->dev.of_node;
992         SET_NETDEV_DEV(dev, &ofdev->dev);
993
994         spin_lock_init(&priv->bflock);
995         INIT_WORK(&priv->reset_task, gfar_reset_task);
996
997         dev_set_drvdata(&ofdev->dev, priv);
998         regs = priv->gfargrp[0].regs;
999
1000         gfar_detect_errata(priv);
1001
1002         /* Stop the DMA engine now, in case it was running before */
1003         /* (The firmware could have used it, and left it running). */
1004         gfar_halt(dev);
1005
1006         /* Reset MAC layer */
1007         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1008
1009         /* We need to delay at least 3 TX clocks */
1010         udelay(2);
1011
1012         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1013         gfar_write(&regs->maccfg1, tempval);
1014
1015         /* Initialize MACCFG2. */
1016         tempval = MACCFG2_INIT_SETTINGS;
1017         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1018                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1019         gfar_write(&regs->maccfg2, tempval);
1020
1021         /* Initialize ECNTRL */
1022         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1023
1024         /* Set the dev->base_addr to the gfar reg region */
1025         dev->base_addr = (unsigned long) regs;
1026
1027         SET_NETDEV_DEV(dev, &ofdev->dev);
1028
1029         /* Fill in the dev structure */
1030         dev->watchdog_timeo = TX_TIMEOUT;
1031         dev->mtu = 1500;
1032         dev->netdev_ops = &gfar_netdev_ops;
1033         dev->ethtool_ops = &gfar_ethtool_ops;
1034
1035         /* Register for napi ...We are registering NAPI for each grp */
1036         for (i = 0; i < priv->num_grps; i++)
1037                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1038
1039         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1040                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1041                         NETIF_F_RXCSUM;
1042                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1043                         NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1044         }
1045
1046         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1047                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1048                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1049         }
1050
1051         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1052                 priv->extended_hash = 1;
1053                 priv->hash_width = 9;
1054
1055                 priv->hash_regs[0] = &regs->igaddr0;
1056                 priv->hash_regs[1] = &regs->igaddr1;
1057                 priv->hash_regs[2] = &regs->igaddr2;
1058                 priv->hash_regs[3] = &regs->igaddr3;
1059                 priv->hash_regs[4] = &regs->igaddr4;
1060                 priv->hash_regs[5] = &regs->igaddr5;
1061                 priv->hash_regs[6] = &regs->igaddr6;
1062                 priv->hash_regs[7] = &regs->igaddr7;
1063                 priv->hash_regs[8] = &regs->gaddr0;
1064                 priv->hash_regs[9] = &regs->gaddr1;
1065                 priv->hash_regs[10] = &regs->gaddr2;
1066                 priv->hash_regs[11] = &regs->gaddr3;
1067                 priv->hash_regs[12] = &regs->gaddr4;
1068                 priv->hash_regs[13] = &regs->gaddr5;
1069                 priv->hash_regs[14] = &regs->gaddr6;
1070                 priv->hash_regs[15] = &regs->gaddr7;
1071
1072         } else {
1073                 priv->extended_hash = 0;
1074                 priv->hash_width = 8;
1075
1076                 priv->hash_regs[0] = &regs->gaddr0;
1077                 priv->hash_regs[1] = &regs->gaddr1;
1078                 priv->hash_regs[2] = &regs->gaddr2;
1079                 priv->hash_regs[3] = &regs->gaddr3;
1080                 priv->hash_regs[4] = &regs->gaddr4;
1081                 priv->hash_regs[5] = &regs->gaddr5;
1082                 priv->hash_regs[6] = &regs->gaddr6;
1083                 priv->hash_regs[7] = &regs->gaddr7;
1084         }
1085
1086         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1087                 priv->padding = DEFAULT_PADDING;
1088         else
1089                 priv->padding = 0;
1090
1091         if (dev->features & NETIF_F_IP_CSUM ||
1092                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1093                 dev->hard_header_len += GMAC_FCB_LEN;
1094
1095         /* Program the isrg regs only if number of grps > 1 */
1096         if (priv->num_grps > 1) {
1097                 baddr = &regs->isrg0;
1098                 for (i = 0; i < priv->num_grps; i++) {
1099                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1100                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1101                         gfar_write(baddr, isrg);
1102                         baddr++;
1103                         isrg = 0x0;
1104                 }
1105         }
1106
1107         /* Need to reverse the bit maps as  bit_map's MSB is q0
1108          * but, for_each_set_bit parses from right to left, which
1109          * basically reverses the queue numbers */
1110         for (i = 0; i< priv->num_grps; i++) {
1111                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1112                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1113                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1114                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1115         }
1116
1117         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1118          * also assign queues to groups */
1119         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1120                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1121                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1122                                 priv->num_rx_queues) {
1123                         priv->gfargrp[grp_idx].num_rx_queues++;
1124                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1125                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1126                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1127                 }
1128                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1129                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1130                                 priv->num_tx_queues) {
1131                         priv->gfargrp[grp_idx].num_tx_queues++;
1132                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1133                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1134                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1135                 }
1136                 priv->gfargrp[grp_idx].rstat = rstat;
1137                 priv->gfargrp[grp_idx].tstat = tstat;
1138                 rstat = tstat =0;
1139         }
1140
1141         gfar_write(&regs->rqueue, rqueue);
1142         gfar_write(&regs->tqueue, tqueue);
1143
1144         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1145
1146         /* Initializing some of the rx/tx queue level parameters */
1147         for (i = 0; i < priv->num_tx_queues; i++) {
1148                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1149                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1150                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1151                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1152         }
1153
1154         for (i = 0; i < priv->num_rx_queues; i++) {
1155                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1156                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1157                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1158         }
1159
1160         /* always enable rx filer*/
1161         priv->rx_filer_enable = 1;
1162         /* Enable most messages by default */
1163         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1164
1165         /* Carrier starts down, phylib will bring it up */
1166         netif_carrier_off(dev);
1167
1168         err = register_netdev(dev);
1169
1170         if (err) {
1171                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1172                 goto register_fail;
1173         }
1174
1175         device_init_wakeup(&dev->dev,
1176                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1177
1178         /* fill out IRQ number and name fields */
1179         len_devname = strlen(dev->name);
1180         for (i = 0; i < priv->num_grps; i++) {
1181                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1182                                 len_devname);
1183                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1184                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1185                                 "_g", sizeof("_g"));
1186                         priv->gfargrp[i].int_name_tx[
1187                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1188                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1189                                 priv->gfargrp[i].int_name_tx)],
1190                                 "_tx", sizeof("_tx") + 1);
1191
1192                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1193                                         len_devname);
1194                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1195                                         "_g", sizeof("_g"));
1196                         priv->gfargrp[i].int_name_rx[
1197                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1198                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1199                                 priv->gfargrp[i].int_name_rx)],
1200                                 "_rx", sizeof("_rx") + 1);
1201
1202                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1203                                         len_devname);
1204                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1205                                 "_g", sizeof("_g"));
1206                         priv->gfargrp[i].int_name_er[strlen(
1207                                         priv->gfargrp[i].int_name_er)] = i+48;
1208                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1209                                 priv->gfargrp[i].int_name_er)],
1210                                 "_er", sizeof("_er") + 1);
1211                 } else
1212                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1213         }
1214
1215         /* Initialize the filer table */
1216         gfar_init_filer_table(priv);
1217
1218         /* Create all the sysfs files */
1219         gfar_init_sysfs(dev);
1220
1221         /* Print out the device info */
1222         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1223
1224         /* Even more device info helps when determining which kernel */
1225         /* provided which set of benchmarks. */
1226         netdev_info(dev, "Running with NAPI enabled\n");
1227         for (i = 0; i < priv->num_rx_queues; i++)
1228                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1229                             i, priv->rx_queue[i]->rx_ring_size);
1230         for(i = 0; i < priv->num_tx_queues; i++)
1231                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1232                             i, priv->tx_queue[i]->tx_ring_size);
1233
1234         return 0;
1235
1236 register_fail:
1237         unmap_group_regs(priv);
1238         free_tx_pointers(priv);
1239         free_rx_pointers(priv);
1240         if (priv->phy_node)
1241                 of_node_put(priv->phy_node);
1242         if (priv->tbi_node)
1243                 of_node_put(priv->tbi_node);
1244         free_netdev(dev);
1245         return err;
1246 }
1247
1248 static int gfar_remove(struct platform_device *ofdev)
1249 {
1250         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1251
1252         if (priv->phy_node)
1253                 of_node_put(priv->phy_node);
1254         if (priv->tbi_node)
1255                 of_node_put(priv->tbi_node);
1256
1257         dev_set_drvdata(&ofdev->dev, NULL);
1258
1259         unregister_netdev(priv->ndev);
1260         unmap_group_regs(priv);
1261         free_netdev(priv->ndev);
1262
1263         return 0;
1264 }
1265
1266 #ifdef CONFIG_PM
1267
1268 static int gfar_suspend(struct device *dev)
1269 {
1270         struct gfar_private *priv = dev_get_drvdata(dev);
1271         struct net_device *ndev = priv->ndev;
1272         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273         unsigned long flags;
1274         u32 tempval;
1275
1276         int magic_packet = priv->wol_en &&
1277                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1278
1279         netif_device_detach(ndev);
1280
1281         if (netif_running(ndev)) {
1282
1283                 local_irq_save(flags);
1284                 lock_tx_qs(priv);
1285                 lock_rx_qs(priv);
1286
1287                 gfar_halt_nodisable(ndev);
1288
1289                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1290                 tempval = gfar_read(&regs->maccfg1);
1291
1292                 tempval &= ~MACCFG1_TX_EN;
1293
1294                 if (!magic_packet)
1295                         tempval &= ~MACCFG1_RX_EN;
1296
1297                 gfar_write(&regs->maccfg1, tempval);
1298
1299                 unlock_rx_qs(priv);
1300                 unlock_tx_qs(priv);
1301                 local_irq_restore(flags);
1302
1303                 disable_napi(priv);
1304
1305                 if (magic_packet) {
1306                         /* Enable interrupt on Magic Packet */
1307                         gfar_write(&regs->imask, IMASK_MAG);
1308
1309                         /* Enable Magic Packet mode */
1310                         tempval = gfar_read(&regs->maccfg2);
1311                         tempval |= MACCFG2_MPEN;
1312                         gfar_write(&regs->maccfg2, tempval);
1313                 } else {
1314                         phy_stop(priv->phydev);
1315                 }
1316         }
1317
1318         return 0;
1319 }
1320
1321 static int gfar_resume(struct device *dev)
1322 {
1323         struct gfar_private *priv = dev_get_drvdata(dev);
1324         struct net_device *ndev = priv->ndev;
1325         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1326         unsigned long flags;
1327         u32 tempval;
1328         int magic_packet = priv->wol_en &&
1329                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1330
1331         if (!netif_running(ndev)) {
1332                 netif_device_attach(ndev);
1333                 return 0;
1334         }
1335
1336         if (!magic_packet && priv->phydev)
1337                 phy_start(priv->phydev);
1338
1339         /* Disable Magic Packet mode, in case something
1340          * else woke us up.
1341          */
1342         local_irq_save(flags);
1343         lock_tx_qs(priv);
1344         lock_rx_qs(priv);
1345
1346         tempval = gfar_read(&regs->maccfg2);
1347         tempval &= ~MACCFG2_MPEN;
1348         gfar_write(&regs->maccfg2, tempval);
1349
1350         gfar_start(ndev);
1351
1352         unlock_rx_qs(priv);
1353         unlock_tx_qs(priv);
1354         local_irq_restore(flags);
1355
1356         netif_device_attach(ndev);
1357
1358         enable_napi(priv);
1359
1360         return 0;
1361 }
1362
1363 static int gfar_restore(struct device *dev)
1364 {
1365         struct gfar_private *priv = dev_get_drvdata(dev);
1366         struct net_device *ndev = priv->ndev;
1367
1368         if (!netif_running(ndev))
1369                 return 0;
1370
1371         gfar_init_bds(ndev);
1372         init_registers(ndev);
1373         gfar_set_mac_address(ndev);
1374         gfar_init_mac(ndev);
1375         gfar_start(ndev);
1376
1377         priv->oldlink = 0;
1378         priv->oldspeed = 0;
1379         priv->oldduplex = -1;
1380
1381         if (priv->phydev)
1382                 phy_start(priv->phydev);
1383
1384         netif_device_attach(ndev);
1385         enable_napi(priv);
1386
1387         return 0;
1388 }
1389
1390 static struct dev_pm_ops gfar_pm_ops = {
1391         .suspend = gfar_suspend,
1392         .resume = gfar_resume,
1393         .freeze = gfar_suspend,
1394         .thaw = gfar_resume,
1395         .restore = gfar_restore,
1396 };
1397
1398 #define GFAR_PM_OPS (&gfar_pm_ops)
1399
1400 #else
1401
1402 #define GFAR_PM_OPS NULL
1403
1404 #endif
1405
1406 /* Reads the controller's registers to determine what interface
1407  * connects it to the PHY.
1408  */
1409 static phy_interface_t gfar_get_interface(struct net_device *dev)
1410 {
1411         struct gfar_private *priv = netdev_priv(dev);
1412         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1413         u32 ecntrl;
1414
1415         ecntrl = gfar_read(&regs->ecntrl);
1416
1417         if (ecntrl & ECNTRL_SGMII_MODE)
1418                 return PHY_INTERFACE_MODE_SGMII;
1419
1420         if (ecntrl & ECNTRL_TBI_MODE) {
1421                 if (ecntrl & ECNTRL_REDUCED_MODE)
1422                         return PHY_INTERFACE_MODE_RTBI;
1423                 else
1424                         return PHY_INTERFACE_MODE_TBI;
1425         }
1426
1427         if (ecntrl & ECNTRL_REDUCED_MODE) {
1428                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1429                         return PHY_INTERFACE_MODE_RMII;
1430                 else {
1431                         phy_interface_t interface = priv->interface;
1432
1433                         /*
1434                          * This isn't autodetected right now, so it must
1435                          * be set by the device tree or platform code.
1436                          */
1437                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1438                                 return PHY_INTERFACE_MODE_RGMII_ID;
1439
1440                         return PHY_INTERFACE_MODE_RGMII;
1441                 }
1442         }
1443
1444         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1445                 return PHY_INTERFACE_MODE_GMII;
1446
1447         return PHY_INTERFACE_MODE_MII;
1448 }
1449
1450
1451 /* Initializes driver's PHY state, and attaches to the PHY.
1452  * Returns 0 on success.
1453  */
1454 static int init_phy(struct net_device *dev)
1455 {
1456         struct gfar_private *priv = netdev_priv(dev);
1457         uint gigabit_support =
1458                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1459                 SUPPORTED_1000baseT_Full : 0;
1460         phy_interface_t interface;
1461
1462         priv->oldlink = 0;
1463         priv->oldspeed = 0;
1464         priv->oldduplex = -1;
1465
1466         interface = gfar_get_interface(dev);
1467
1468         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1469                                       interface);
1470         if (!priv->phydev)
1471                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1472                                                          interface);
1473         if (!priv->phydev) {
1474                 dev_err(&dev->dev, "could not attach to PHY\n");
1475                 return -ENODEV;
1476         }
1477
1478         if (interface == PHY_INTERFACE_MODE_SGMII)
1479                 gfar_configure_serdes(dev);
1480
1481         /* Remove any features not supported by the controller */
1482         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1483         priv->phydev->advertising = priv->phydev->supported;
1484
1485         return 0;
1486 }
1487
1488 /*
1489  * Initialize TBI PHY interface for communicating with the
1490  * SERDES lynx PHY on the chip.  We communicate with this PHY
1491  * through the MDIO bus on each controller, treating it as a
1492  * "normal" PHY at the address found in the TBIPA register.  We assume
1493  * that the TBIPA register is valid.  Either the MDIO bus code will set
1494  * it to a value that doesn't conflict with other PHYs on the bus, or the
1495  * value doesn't matter, as there are no other PHYs on the bus.
1496  */
1497 static void gfar_configure_serdes(struct net_device *dev)
1498 {
1499         struct gfar_private *priv = netdev_priv(dev);
1500         struct phy_device *tbiphy;
1501
1502         if (!priv->tbi_node) {
1503                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1504                                     "device tree specify a tbi-handle\n");
1505                 return;
1506         }
1507
1508         tbiphy = of_phy_find_device(priv->tbi_node);
1509         if (!tbiphy) {
1510                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1511                 return;
1512         }
1513
1514         /*
1515          * If the link is already up, we must already be ok, and don't need to
1516          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1517          * everything for us?  Resetting it takes the link down and requires
1518          * several seconds for it to come back.
1519          */
1520         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1521                 return;
1522
1523         /* Single clk mode, mii mode off(for serdes communication) */
1524         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1525
1526         phy_write(tbiphy, MII_ADVERTISE,
1527                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1528                         ADVERTISE_1000XPSE_ASYM);
1529
1530         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1531                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1532 }
1533
1534 static void init_registers(struct net_device *dev)
1535 {
1536         struct gfar_private *priv = netdev_priv(dev);
1537         struct gfar __iomem *regs = NULL;
1538         int i = 0;
1539
1540         for (i = 0; i < priv->num_grps; i++) {
1541                 regs = priv->gfargrp[i].regs;
1542                 /* Clear IEVENT */
1543                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1544
1545                 /* Initialize IMASK */
1546                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1547         }
1548
1549         regs = priv->gfargrp[0].regs;
1550         /* Init hash registers to zero */
1551         gfar_write(&regs->igaddr0, 0);
1552         gfar_write(&regs->igaddr1, 0);
1553         gfar_write(&regs->igaddr2, 0);
1554         gfar_write(&regs->igaddr3, 0);
1555         gfar_write(&regs->igaddr4, 0);
1556         gfar_write(&regs->igaddr5, 0);
1557         gfar_write(&regs->igaddr6, 0);
1558         gfar_write(&regs->igaddr7, 0);
1559
1560         gfar_write(&regs->gaddr0, 0);
1561         gfar_write(&regs->gaddr1, 0);
1562         gfar_write(&regs->gaddr2, 0);
1563         gfar_write(&regs->gaddr3, 0);
1564         gfar_write(&regs->gaddr4, 0);
1565         gfar_write(&regs->gaddr5, 0);
1566         gfar_write(&regs->gaddr6, 0);
1567         gfar_write(&regs->gaddr7, 0);
1568
1569         /* Zero out the rmon mib registers if it has them */
1570         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1571                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1572
1573                 /* Mask off the CAM interrupts */
1574                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1575                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1576         }
1577
1578         /* Initialize the max receive buffer length */
1579         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1580
1581         /* Initialize the Minimum Frame Length Register */
1582         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1583 }
1584
1585 static int __gfar_is_rx_idle(struct gfar_private *priv)
1586 {
1587         u32 res;
1588
1589         /*
1590          * Normaly TSEC should not hang on GRS commands, so we should
1591          * actually wait for IEVENT_GRSC flag.
1592          */
1593         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1594                 return 0;
1595
1596         /*
1597          * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1598          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1599          * and the Rx can be safely reset.
1600          */
1601         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1602         res &= 0x7f807f80;
1603         if ((res & 0xffff) == (res >> 16))
1604                 return 1;
1605
1606         return 0;
1607 }
1608
1609 /* Halt the receive and transmit queues */
1610 static void gfar_halt_nodisable(struct net_device *dev)
1611 {
1612         struct gfar_private *priv = netdev_priv(dev);
1613         struct gfar __iomem *regs = NULL;
1614         u32 tempval;
1615         int i = 0;
1616
1617         for (i = 0; i < priv->num_grps; i++) {
1618                 regs = priv->gfargrp[i].regs;
1619                 /* Mask all interrupts */
1620                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1621
1622                 /* Clear all interrupts */
1623                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1624         }
1625
1626         regs = priv->gfargrp[0].regs;
1627         /* Stop the DMA, and wait for it to stop */
1628         tempval = gfar_read(&regs->dmactrl);
1629         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1630             != (DMACTRL_GRS | DMACTRL_GTS)) {
1631                 int ret;
1632
1633                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1634                 gfar_write(&regs->dmactrl, tempval);
1635
1636                 do {
1637                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1638                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1639                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1640                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1641                                 ret = __gfar_is_rx_idle(priv);
1642                 } while (!ret);
1643         }
1644 }
1645
1646 /* Halt the receive and transmit queues */
1647 void gfar_halt(struct net_device *dev)
1648 {
1649         struct gfar_private *priv = netdev_priv(dev);
1650         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1651         u32 tempval;
1652
1653         gfar_halt_nodisable(dev);
1654
1655         /* Disable Rx and Tx */
1656         tempval = gfar_read(&regs->maccfg1);
1657         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1658         gfar_write(&regs->maccfg1, tempval);
1659 }
1660
1661 static void free_grp_irqs(struct gfar_priv_grp *grp)
1662 {
1663         free_irq(grp->interruptError, grp);
1664         free_irq(grp->interruptTransmit, grp);
1665         free_irq(grp->interruptReceive, grp);
1666 }
1667
1668 void stop_gfar(struct net_device *dev)
1669 {
1670         struct gfar_private *priv = netdev_priv(dev);
1671         unsigned long flags;
1672         int i;
1673
1674         phy_stop(priv->phydev);
1675
1676
1677         /* Lock it down */
1678         local_irq_save(flags);
1679         lock_tx_qs(priv);
1680         lock_rx_qs(priv);
1681
1682         gfar_halt(dev);
1683
1684         unlock_rx_qs(priv);
1685         unlock_tx_qs(priv);
1686         local_irq_restore(flags);
1687
1688         /* Free the IRQs */
1689         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1690                 for (i = 0; i < priv->num_grps; i++)
1691                         free_grp_irqs(&priv->gfargrp[i]);
1692         } else {
1693                 for (i = 0; i < priv->num_grps; i++)
1694                         free_irq(priv->gfargrp[i].interruptTransmit,
1695                                         &priv->gfargrp[i]);
1696         }
1697
1698         free_skb_resources(priv);
1699 }
1700
1701 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1702 {
1703         struct txbd8 *txbdp;
1704         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1705         int i, j;
1706
1707         txbdp = tx_queue->tx_bd_base;
1708
1709         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1710                 if (!tx_queue->tx_skbuff[i])
1711                         continue;
1712
1713                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1714                                 txbdp->length, DMA_TO_DEVICE);
1715                 txbdp->lstatus = 0;
1716                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1717                                 j++) {
1718                         txbdp++;
1719                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1720                                         txbdp->length, DMA_TO_DEVICE);
1721                 }
1722                 txbdp++;
1723                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1724                 tx_queue->tx_skbuff[i] = NULL;
1725         }
1726         kfree(tx_queue->tx_skbuff);
1727 }
1728
1729 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1730 {
1731         struct rxbd8 *rxbdp;
1732         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1733         int i;
1734
1735         rxbdp = rx_queue->rx_bd_base;
1736
1737         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1738                 if (rx_queue->rx_skbuff[i]) {
1739                         dma_unmap_single(&priv->ofdev->dev,
1740                                         rxbdp->bufPtr, priv->rx_buffer_size,
1741                                         DMA_FROM_DEVICE);
1742                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1743                         rx_queue->rx_skbuff[i] = NULL;
1744                 }
1745                 rxbdp->lstatus = 0;
1746                 rxbdp->bufPtr = 0;
1747                 rxbdp++;
1748         }
1749         kfree(rx_queue->rx_skbuff);
1750 }
1751
1752 /* If there are any tx skbs or rx skbs still around, free them.
1753  * Then free tx_skbuff and rx_skbuff */
1754 static void free_skb_resources(struct gfar_private *priv)
1755 {
1756         struct gfar_priv_tx_q *tx_queue = NULL;
1757         struct gfar_priv_rx_q *rx_queue = NULL;
1758         int i;
1759
1760         /* Go through all the buffer descriptors and free their data buffers */
1761         for (i = 0; i < priv->num_tx_queues; i++) {
1762                 tx_queue = priv->tx_queue[i];
1763                 if(tx_queue->tx_skbuff)
1764                         free_skb_tx_queue(tx_queue);
1765         }
1766
1767         for (i = 0; i < priv->num_rx_queues; i++) {
1768                 rx_queue = priv->rx_queue[i];
1769                 if(rx_queue->rx_skbuff)
1770                         free_skb_rx_queue(rx_queue);
1771         }
1772
1773         dma_free_coherent(&priv->ofdev->dev,
1774                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1775                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1776                         priv->tx_queue[0]->tx_bd_base,
1777                         priv->tx_queue[0]->tx_bd_dma_base);
1778         skb_queue_purge(&priv->rx_recycle);
1779 }
1780
1781 void gfar_start(struct net_device *dev)
1782 {
1783         struct gfar_private *priv = netdev_priv(dev);
1784         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1785         u32 tempval;
1786         int i = 0;
1787
1788         /* Enable Rx and Tx in MACCFG1 */
1789         tempval = gfar_read(&regs->maccfg1);
1790         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1791         gfar_write(&regs->maccfg1, tempval);
1792
1793         /* Initialize DMACTRL to have WWR and WOP */
1794         tempval = gfar_read(&regs->dmactrl);
1795         tempval |= DMACTRL_INIT_SETTINGS;
1796         gfar_write(&regs->dmactrl, tempval);
1797
1798         /* Make sure we aren't stopped */
1799         tempval = gfar_read(&regs->dmactrl);
1800         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1801         gfar_write(&regs->dmactrl, tempval);
1802
1803         for (i = 0; i < priv->num_grps; i++) {
1804                 regs = priv->gfargrp[i].regs;
1805                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1806                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1807                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1808                 /* Unmask the interrupts we look for */
1809                 gfar_write(&regs->imask, IMASK_DEFAULT);
1810         }
1811
1812         dev->trans_start = jiffies; /* prevent tx timeout */
1813 }
1814
1815 void gfar_configure_coalescing(struct gfar_private *priv,
1816         unsigned long tx_mask, unsigned long rx_mask)
1817 {
1818         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1819         u32 __iomem *baddr;
1820         int i = 0;
1821
1822         /* Backward compatible case ---- even if we enable
1823          * multiple queues, there's only single reg to program
1824          */
1825         gfar_write(&regs->txic, 0);
1826         if(likely(priv->tx_queue[0]->txcoalescing))
1827                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1828
1829         gfar_write(&regs->rxic, 0);
1830         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1831                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1832
1833         if (priv->mode == MQ_MG_MODE) {
1834                 baddr = &regs->txic0;
1835                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1836                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1837                                 gfar_write(baddr + i, 0);
1838                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1839                         }
1840                 }
1841
1842                 baddr = &regs->rxic0;
1843                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1844                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1845                                 gfar_write(baddr + i, 0);
1846                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1847                         }
1848                 }
1849         }
1850 }
1851
1852 static int register_grp_irqs(struct gfar_priv_grp *grp)
1853 {
1854         struct gfar_private *priv = grp->priv;
1855         struct net_device *dev = priv->ndev;
1856         int err;
1857
1858         /* If the device has multiple interrupts, register for
1859          * them.  Otherwise, only register for the one */
1860         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1861                 /* Install our interrupt handlers for Error,
1862                  * Transmit, and Receive */
1863                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1864                                 grp->int_name_er,grp)) < 0) {
1865                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1866                                   grp->interruptError);
1867
1868                         goto err_irq_fail;
1869                 }
1870
1871                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1872                                 0, grp->int_name_tx, grp)) < 0) {
1873                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1874                                   grp->interruptTransmit);
1875                         goto tx_irq_fail;
1876                 }
1877
1878                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1879                                 grp->int_name_rx, grp)) < 0) {
1880                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1881                                   grp->interruptReceive);
1882                         goto rx_irq_fail;
1883                 }
1884         } else {
1885                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1886                                 grp->int_name_tx, grp)) < 0) {
1887                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1888                                   grp->interruptTransmit);
1889                         goto err_irq_fail;
1890                 }
1891         }
1892
1893         return 0;
1894
1895 rx_irq_fail:
1896         free_irq(grp->interruptTransmit, grp);
1897 tx_irq_fail:
1898         free_irq(grp->interruptError, grp);
1899 err_irq_fail:
1900         return err;
1901
1902 }
1903
1904 /* Bring the controller up and running */
1905 int startup_gfar(struct net_device *ndev)
1906 {
1907         struct gfar_private *priv = netdev_priv(ndev);
1908         struct gfar __iomem *regs = NULL;
1909         int err, i, j;
1910
1911         for (i = 0; i < priv->num_grps; i++) {
1912                 regs= priv->gfargrp[i].regs;
1913                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1914         }
1915
1916         regs= priv->gfargrp[0].regs;
1917         err = gfar_alloc_skb_resources(ndev);
1918         if (err)
1919                 return err;
1920
1921         gfar_init_mac(ndev);
1922
1923         for (i = 0; i < priv->num_grps; i++) {
1924                 err = register_grp_irqs(&priv->gfargrp[i]);
1925                 if (err) {
1926                         for (j = 0; j < i; j++)
1927                                 free_grp_irqs(&priv->gfargrp[j]);
1928                         goto irq_fail;
1929                 }
1930         }
1931
1932         /* Start the controller */
1933         gfar_start(ndev);
1934
1935         phy_start(priv->phydev);
1936
1937         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1938
1939         return 0;
1940
1941 irq_fail:
1942         free_skb_resources(priv);
1943         return err;
1944 }
1945
1946 /* Called when something needs to use the ethernet device */
1947 /* Returns 0 for success. */
1948 static int gfar_enet_open(struct net_device *dev)
1949 {
1950         struct gfar_private *priv = netdev_priv(dev);
1951         int err;
1952
1953         enable_napi(priv);
1954
1955         skb_queue_head_init(&priv->rx_recycle);
1956
1957         /* Initialize a bunch of registers */
1958         init_registers(dev);
1959
1960         gfar_set_mac_address(dev);
1961
1962         err = init_phy(dev);
1963
1964         if (err) {
1965                 disable_napi(priv);
1966                 return err;
1967         }
1968
1969         err = startup_gfar(dev);
1970         if (err) {
1971                 disable_napi(priv);
1972                 return err;
1973         }
1974
1975         netif_tx_start_all_queues(dev);
1976
1977         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1978
1979         return err;
1980 }
1981
1982 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1983 {
1984         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1985
1986         memset(fcb, 0, GMAC_FCB_LEN);
1987
1988         return fcb;
1989 }
1990
1991 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1992 {
1993         u8 flags = 0;
1994
1995         /* If we're here, it's a IP packet with a TCP or UDP
1996          * payload.  We set it to checksum, using a pseudo-header
1997          * we provide
1998          */
1999         flags = TXFCB_DEFAULT;
2000
2001         /* Tell the controller what the protocol is */
2002         /* And provide the already calculated phcs */
2003         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2004                 flags |= TXFCB_UDP;
2005                 fcb->phcs = udp_hdr(skb)->check;
2006         } else
2007                 fcb->phcs = tcp_hdr(skb)->check;
2008
2009         /* l3os is the distance between the start of the
2010          * frame (skb->data) and the start of the IP hdr.
2011          * l4os is the distance between the start of the
2012          * l3 hdr and the l4 hdr */
2013         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2014         fcb->l4os = skb_network_header_len(skb);
2015
2016         fcb->flags = flags;
2017 }
2018
2019 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2020 {
2021         fcb->flags |= TXFCB_VLN;
2022         fcb->vlctl = vlan_tx_tag_get(skb);
2023 }
2024
2025 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2026                                struct txbd8 *base, int ring_size)
2027 {
2028         struct txbd8 *new_bd = bdp + stride;
2029
2030         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2031 }
2032
2033 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2034                 int ring_size)
2035 {
2036         return skip_txbd(bdp, 1, base, ring_size);
2037 }
2038
2039 /* This is called by the kernel when a frame is ready for transmission. */
2040 /* It is pointed to by the dev->hard_start_xmit function pointer */
2041 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2042 {
2043         struct gfar_private *priv = netdev_priv(dev);
2044         struct gfar_priv_tx_q *tx_queue = NULL;
2045         struct netdev_queue *txq;
2046         struct gfar __iomem *regs = NULL;
2047         struct txfcb *fcb = NULL;
2048         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2049         u32 lstatus;
2050         int i, rq = 0, do_tstamp = 0;
2051         u32 bufaddr;
2052         unsigned long flags;
2053         unsigned int nr_frags, nr_txbds, length;
2054
2055         /*
2056          * TOE=1 frames larger than 2500 bytes may see excess delays
2057          * before start of transmission.
2058          */
2059         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2060                         skb->ip_summed == CHECKSUM_PARTIAL &&
2061                         skb->len > 2500)) {
2062                 int ret;
2063
2064                 ret = skb_checksum_help(skb);
2065                 if (ret)
2066                         return ret;
2067         }
2068
2069         rq = skb->queue_mapping;
2070         tx_queue = priv->tx_queue[rq];
2071         txq = netdev_get_tx_queue(dev, rq);
2072         base = tx_queue->tx_bd_base;
2073         regs = tx_queue->grp->regs;
2074
2075         /* check if time stamp should be generated */
2076         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2077                      priv->hwts_tx_en))
2078                 do_tstamp = 1;
2079
2080         /* make space for additional header when fcb is needed */
2081         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2082                         vlan_tx_tag_present(skb) ||
2083                         unlikely(do_tstamp)) &&
2084                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
2085                 struct sk_buff *skb_new;
2086
2087                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2088                 if (!skb_new) {
2089                         dev->stats.tx_errors++;
2090                         kfree_skb(skb);
2091                         return NETDEV_TX_OK;
2092                 }
2093                 kfree_skb(skb);
2094                 skb = skb_new;
2095         }
2096
2097         /* total number of fragments in the SKB */
2098         nr_frags = skb_shinfo(skb)->nr_frags;
2099
2100         /* calculate the required number of TxBDs for this skb */
2101         if (unlikely(do_tstamp))
2102                 nr_txbds = nr_frags + 2;
2103         else
2104                 nr_txbds = nr_frags + 1;
2105
2106         /* check if there is space to queue this packet */
2107         if (nr_txbds > tx_queue->num_txbdfree) {
2108                 /* no space, stop the queue */
2109                 netif_tx_stop_queue(txq);
2110                 dev->stats.tx_fifo_errors++;
2111                 return NETDEV_TX_BUSY;
2112         }
2113
2114         /* Update transmit stats */
2115         tx_queue->stats.tx_bytes += skb->len;
2116         tx_queue->stats.tx_packets++;
2117
2118         txbdp = txbdp_start = tx_queue->cur_tx;
2119         lstatus = txbdp->lstatus;
2120
2121         /* Time stamp insertion requires one additional TxBD */
2122         if (unlikely(do_tstamp))
2123                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2124                                 tx_queue->tx_ring_size);
2125
2126         if (nr_frags == 0) {
2127                 if (unlikely(do_tstamp))
2128                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2129                                         TXBD_INTERRUPT);
2130                 else
2131                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2132         } else {
2133                 /* Place the fragment addresses and lengths into the TxBDs */
2134                 for (i = 0; i < nr_frags; i++) {
2135                         /* Point at the next BD, wrapping as needed */
2136                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2137
2138                         length = skb_shinfo(skb)->frags[i].size;
2139
2140                         lstatus = txbdp->lstatus | length |
2141                                 BD_LFLAG(TXBD_READY);
2142
2143                         /* Handle the last BD specially */
2144                         if (i == nr_frags - 1)
2145                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2146
2147                         bufaddr = dma_map_page(&priv->ofdev->dev,
2148                                         skb_shinfo(skb)->frags[i].page,
2149                                         skb_shinfo(skb)->frags[i].page_offset,
2150                                         length,
2151                                         DMA_TO_DEVICE);
2152
2153                         /* set the TxBD length and buffer pointer */
2154                         txbdp->bufPtr = bufaddr;
2155                         txbdp->lstatus = lstatus;
2156                 }
2157
2158                 lstatus = txbdp_start->lstatus;
2159         }
2160
2161         /* Set up checksumming */
2162         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2163                 fcb = gfar_add_fcb(skb);
2164                 /* as specified by errata */
2165                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2166                              && ((unsigned long)fcb % 0x20) > 0x18)) {
2167                         __skb_pull(skb, GMAC_FCB_LEN);
2168                         skb_checksum_help(skb);
2169                 } else {
2170                         lstatus |= BD_LFLAG(TXBD_TOE);
2171                         gfar_tx_checksum(skb, fcb);
2172                 }
2173         }
2174
2175         if (vlan_tx_tag_present(skb)) {
2176                 if (unlikely(NULL == fcb)) {
2177                         fcb = gfar_add_fcb(skb);
2178                         lstatus |= BD_LFLAG(TXBD_TOE);
2179                 }
2180
2181                 gfar_tx_vlan(skb, fcb);
2182         }
2183
2184         /* Setup tx hardware time stamping if requested */
2185         if (unlikely(do_tstamp)) {
2186                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2187                 if (fcb == NULL)
2188                         fcb = gfar_add_fcb(skb);
2189                 fcb->ptp = 1;
2190                 lstatus |= BD_LFLAG(TXBD_TOE);
2191         }
2192
2193         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2194                         skb_headlen(skb), DMA_TO_DEVICE);
2195
2196         /*
2197          * If time stamping is requested one additional TxBD must be set up. The
2198          * first TxBD points to the FCB and must have a data length of
2199          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2200          * the full frame length.
2201          */
2202         if (unlikely(do_tstamp)) {
2203                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2204                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2205                                 (skb_headlen(skb) - GMAC_FCB_LEN);
2206                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2207         } else {
2208                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2209         }
2210
2211         /*
2212          * We can work in parallel with gfar_clean_tx_ring(), except
2213          * when modifying num_txbdfree. Note that we didn't grab the lock
2214          * when we were reading the num_txbdfree and checking for available
2215          * space, that's because outside of this function it can only grow,
2216          * and once we've got needed space, it cannot suddenly disappear.
2217          *
2218          * The lock also protects us from gfar_error(), which can modify
2219          * regs->tstat and thus retrigger the transfers, which is why we
2220          * also must grab the lock before setting ready bit for the first
2221          * to be transmitted BD.
2222          */
2223         spin_lock_irqsave(&tx_queue->txlock, flags);
2224
2225         /*
2226          * The powerpc-specific eieio() is used, as wmb() has too strong
2227          * semantics (it requires synchronization between cacheable and
2228          * uncacheable mappings, which eieio doesn't provide and which we
2229          * don't need), thus requiring a more expensive sync instruction.  At
2230          * some point, the set of architecture-independent barrier functions
2231          * should be expanded to include weaker barriers.
2232          */
2233         eieio();
2234
2235         txbdp_start->lstatus = lstatus;
2236
2237         eieio(); /* force lstatus write before tx_skbuff */
2238
2239         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2240
2241         /* Update the current skb pointer to the next entry we will use
2242          * (wrapping if necessary) */
2243         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2244                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2245
2246         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2247
2248         /* reduce TxBD free count */
2249         tx_queue->num_txbdfree -= (nr_txbds);
2250
2251         /* If the next BD still needs to be cleaned up, then the bds
2252            are full.  We need to tell the kernel to stop sending us stuff. */
2253         if (!tx_queue->num_txbdfree) {
2254                 netif_tx_stop_queue(txq);
2255
2256                 dev->stats.tx_fifo_errors++;
2257         }
2258
2259         /* Tell the DMA to go go go */
2260         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2261
2262         /* Unlock priv */
2263         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2264
2265         return NETDEV_TX_OK;
2266 }
2267
2268 /* Stops the kernel queue, and halts the controller */
2269 static int gfar_close(struct net_device *dev)
2270 {
2271         struct gfar_private *priv = netdev_priv(dev);
2272
2273         disable_napi(priv);
2274
2275         cancel_work_sync(&priv->reset_task);
2276         stop_gfar(dev);
2277
2278         /* Disconnect from the PHY */
2279         phy_disconnect(priv->phydev);
2280         priv->phydev = NULL;
2281
2282         netif_tx_stop_all_queues(dev);
2283
2284         return 0;
2285 }
2286
2287 /* Changes the mac address if the controller is not running. */
2288 static int gfar_set_mac_address(struct net_device *dev)
2289 {
2290         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2291
2292         return 0;
2293 }
2294
2295 /* Check if rx parser should be activated */
2296 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2297 {
2298         struct gfar __iomem *regs;
2299         u32 tempval;
2300
2301         regs = priv->gfargrp[0].regs;
2302
2303         tempval = gfar_read(&regs->rctrl);
2304         /* If parse is no longer required, then disable parser */
2305         if (tempval & RCTRL_REQ_PARSER)
2306                 tempval |= RCTRL_PRSDEP_INIT;
2307         else
2308                 tempval &= ~RCTRL_PRSDEP_INIT;
2309         gfar_write(&regs->rctrl, tempval);
2310 }
2311
2312 /* Enables and disables VLAN insertion/extraction */
2313 void gfar_vlan_mode(struct net_device *dev, u32 features)
2314 {
2315         struct gfar_private *priv = netdev_priv(dev);
2316         struct gfar __iomem *regs = NULL;
2317         unsigned long flags;
2318         u32 tempval;
2319
2320         regs = priv->gfargrp[0].regs;
2321         local_irq_save(flags);
2322         lock_rx_qs(priv);
2323
2324         if (features & NETIF_F_HW_VLAN_TX) {
2325                 /* Enable VLAN tag insertion */
2326                 tempval = gfar_read(&regs->tctrl);
2327                 tempval |= TCTRL_VLINS;
2328                 gfar_write(&regs->tctrl, tempval);
2329         } else {
2330                 /* Disable VLAN tag insertion */
2331                 tempval = gfar_read(&regs->tctrl);
2332                 tempval &= ~TCTRL_VLINS;
2333                 gfar_write(&regs->tctrl, tempval);
2334         }
2335
2336         if (features & NETIF_F_HW_VLAN_RX) {
2337                 /* Enable VLAN tag extraction */
2338                 tempval = gfar_read(&regs->rctrl);
2339                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2340                 gfar_write(&regs->rctrl, tempval);
2341         } else {
2342                 /* Disable VLAN tag extraction */
2343                 tempval = gfar_read(&regs->rctrl);
2344                 tempval &= ~RCTRL_VLEX;
2345                 gfar_write(&regs->rctrl, tempval);
2346
2347                 gfar_check_rx_parser_mode(priv);
2348         }
2349
2350         gfar_change_mtu(dev, dev->mtu);
2351
2352         unlock_rx_qs(priv);
2353         local_irq_restore(flags);
2354 }
2355
2356 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2357 {
2358         int tempsize, tempval;
2359         struct gfar_private *priv = netdev_priv(dev);
2360         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2361         int oldsize = priv->rx_buffer_size;
2362         int frame_size = new_mtu + ETH_HLEN;
2363
2364         if (gfar_is_vlan_on(priv))
2365                 frame_size += VLAN_HLEN;
2366
2367         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2368                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2369                 return -EINVAL;
2370         }
2371
2372         if (gfar_uses_fcb(priv))
2373                 frame_size += GMAC_FCB_LEN;
2374
2375         frame_size += priv->padding;
2376
2377         tempsize =
2378             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2379             INCREMENTAL_BUFFER_SIZE;
2380
2381         /* Only stop and start the controller if it isn't already
2382          * stopped, and we changed something */
2383         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2384                 stop_gfar(dev);
2385
2386         priv->rx_buffer_size = tempsize;
2387
2388         dev->mtu = new_mtu;
2389
2390         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2391         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2392
2393         /* If the mtu is larger than the max size for standard
2394          * ethernet frames (ie, a jumbo frame), then set maccfg2
2395          * to allow huge frames, and to check the length */
2396         tempval = gfar_read(&regs->maccfg2);
2397
2398         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2399                         gfar_has_errata(priv, GFAR_ERRATA_74))
2400                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2401         else
2402                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2403
2404         gfar_write(&regs->maccfg2, tempval);
2405
2406         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2407                 startup_gfar(dev);
2408
2409         return 0;
2410 }
2411
2412 /* gfar_reset_task gets scheduled when a packet has not been
2413  * transmitted after a set amount of time.
2414  * For now, assume that clearing out all the structures, and
2415  * starting over will fix the problem.
2416  */
2417 static void gfar_reset_task(struct work_struct *work)
2418 {
2419         struct gfar_private *priv = container_of(work, struct gfar_private,
2420                         reset_task);
2421         struct net_device *dev = priv->ndev;
2422
2423         if (dev->flags & IFF_UP) {
2424                 netif_tx_stop_all_queues(dev);
2425                 stop_gfar(dev);
2426                 startup_gfar(dev);
2427                 netif_tx_start_all_queues(dev);
2428         }
2429
2430         netif_tx_schedule_all(dev);
2431 }
2432
2433 static void gfar_timeout(struct net_device *dev)
2434 {
2435         struct gfar_private *priv = netdev_priv(dev);
2436
2437         dev->stats.tx_errors++;
2438         schedule_work(&priv->reset_task);
2439 }
2440
2441 static void gfar_align_skb(struct sk_buff *skb)
2442 {
2443         /* We need the data buffer to be aligned properly.  We will reserve
2444          * as many bytes as needed to align the data properly
2445          */
2446         skb_reserve(skb, RXBUF_ALIGNMENT -
2447                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2448 }
2449
2450 /* Interrupt Handler for Transmit complete */
2451 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2452 {
2453         struct net_device *dev = tx_queue->dev;
2454         struct gfar_private *priv = netdev_priv(dev);
2455         struct gfar_priv_rx_q *rx_queue = NULL;
2456         struct txbd8 *bdp, *next = NULL;
2457         struct txbd8 *lbdp = NULL;
2458         struct txbd8 *base = tx_queue->tx_bd_base;
2459         struct sk_buff *skb;
2460         int skb_dirtytx;
2461         int tx_ring_size = tx_queue->tx_ring_size;
2462         int frags = 0, nr_txbds = 0;
2463         int i;
2464         int howmany = 0;
2465         u32 lstatus;
2466         size_t buflen;
2467
2468         rx_queue = priv->rx_queue[tx_queue->qindex];
2469         bdp = tx_queue->dirty_tx;
2470         skb_dirtytx = tx_queue->skb_dirtytx;
2471
2472         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2473                 unsigned long flags;
2474
2475                 frags = skb_shinfo(skb)->nr_frags;
2476
2477                 /*
2478                  * When time stamping, one additional TxBD must be freed.
2479                  * Also, we need to dma_unmap_single() the TxPAL.
2480                  */
2481                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2482                         nr_txbds = frags + 2;
2483                 else
2484                         nr_txbds = frags + 1;
2485
2486                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2487
2488                 lstatus = lbdp->lstatus;
2489
2490                 /* Only clean completed frames */
2491                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2492                                 (lstatus & BD_LENGTH_MASK))
2493                         break;
2494
2495                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2496                         next = next_txbd(bdp, base, tx_ring_size);
2497                         buflen = next->length + GMAC_FCB_LEN;
2498                 } else
2499                         buflen = bdp->length;
2500
2501                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2502                                 buflen, DMA_TO_DEVICE);
2503
2504                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2505                         struct skb_shared_hwtstamps shhwtstamps;
2506                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2507                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2508                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2509                         skb_tstamp_tx(skb, &shhwtstamps);
2510                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2511                         bdp = next;
2512                 }
2513
2514                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2515                 bdp = next_txbd(bdp, base, tx_ring_size);
2516
2517                 for (i = 0; i < frags; i++) {
2518                         dma_unmap_page(&priv->ofdev->dev,
2519                                         bdp->bufPtr,
2520                                         bdp->length,
2521                                         DMA_TO_DEVICE);
2522                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2523                         bdp = next_txbd(bdp, base, tx_ring_size);
2524                 }
2525
2526                 /*
2527                  * If there's room in the queue (limit it to rx_buffer_size)
2528                  * we add this skb back into the pool, if it's the right size
2529                  */
2530                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2531                                 skb_recycle_check(skb, priv->rx_buffer_size +
2532                                         RXBUF_ALIGNMENT)) {
2533                         gfar_align_skb(skb);
2534                         skb_queue_head(&priv->rx_recycle, skb);
2535                 } else
2536                         dev_kfree_skb_any(skb);
2537
2538                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2539
2540                 skb_dirtytx = (skb_dirtytx + 1) &
2541                         TX_RING_MOD_MASK(tx_ring_size);
2542
2543                 howmany++;
2544                 spin_lock_irqsave(&tx_queue->txlock, flags);
2545                 tx_queue->num_txbdfree += nr_txbds;
2546                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2547         }
2548
2549         /* If we freed a buffer, we can restart transmission, if necessary */
2550         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2551                 netif_wake_subqueue(dev, tx_queue->qindex);
2552
2553         /* Update dirty indicators */
2554         tx_queue->skb_dirtytx = skb_dirtytx;
2555         tx_queue->dirty_tx = bdp;
2556
2557         return howmany;
2558 }
2559
2560 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2561 {
2562         unsigned long flags;
2563
2564         spin_lock_irqsave(&gfargrp->grplock, flags);
2565         if (napi_schedule_prep(&gfargrp->napi)) {
2566                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2567                 __napi_schedule(&gfargrp->napi);
2568         } else {
2569                 /*
2570                  * Clear IEVENT, so interrupts aren't called again
2571                  * because of the packets that have already arrived.
2572                  */
2573                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2574         }
2575         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2576
2577 }
2578
2579 /* Interrupt Handler for Transmit complete */
2580 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2581 {
2582         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2583         return IRQ_HANDLED;
2584 }
2585
2586 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2587                 struct sk_buff *skb)
2588 {
2589         struct net_device *dev = rx_queue->dev;
2590         struct gfar_private *priv = netdev_priv(dev);
2591         dma_addr_t buf;
2592
2593         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2594                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2595         gfar_init_rxbdp(rx_queue, bdp, buf);
2596 }
2597
2598 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2599 {
2600         struct gfar_private *priv = netdev_priv(dev);
2601         struct sk_buff *skb = NULL;
2602
2603         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2604         if (!skb)
2605                 return NULL;
2606
2607         gfar_align_skb(skb);
2608
2609         return skb;
2610 }
2611
2612 struct sk_buff * gfar_new_skb(struct net_device *dev)
2613 {
2614         struct gfar_private *priv = netdev_priv(dev);
2615         struct sk_buff *skb = NULL;
2616
2617         skb = skb_dequeue(&priv->rx_recycle);
2618         if (!skb)
2619                 skb = gfar_alloc_skb(dev);
2620
2621         return skb;
2622 }
2623
2624 static inline void count_errors(unsigned short status, struct net_device *dev)
2625 {
2626         struct gfar_private *priv = netdev_priv(dev);
2627         struct net_device_stats *stats = &dev->stats;
2628         struct gfar_extra_stats *estats = &priv->extra_stats;
2629
2630         /* If the packet was truncated, none of the other errors
2631          * matter */
2632         if (status & RXBD_TRUNCATED) {
2633                 stats->rx_length_errors++;
2634
2635                 estats->rx_trunc++;
2636
2637                 return;
2638         }
2639         /* Count the errors, if there were any */
2640         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2641                 stats->rx_length_errors++;
2642
2643                 if (status & RXBD_LARGE)
2644                         estats->rx_large++;
2645                 else
2646                         estats->rx_short++;
2647         }
2648         if (status & RXBD_NONOCTET) {
2649                 stats->rx_frame_errors++;
2650                 estats->rx_nonoctet++;
2651         }
2652         if (status & RXBD_CRCERR) {
2653                 estats->rx_crcerr++;
2654                 stats->rx_crc_errors++;
2655         }
2656         if (status & RXBD_OVERRUN) {
2657                 estats->rx_overrun++;
2658                 stats->rx_crc_errors++;
2659         }
2660 }
2661
2662 irqreturn_t gfar_receive(int irq, void *grp_id)
2663 {
2664         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2665         return IRQ_HANDLED;
2666 }
2667
2668 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2669 {
2670         /* If valid headers were found, and valid sums
2671          * were verified, then we tell the kernel that no
2672          * checksumming is necessary.  Otherwise, it is */
2673         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2674                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2675         else
2676                 skb_checksum_none_assert(skb);
2677 }
2678
2679
2680 /* gfar_process_frame() -- handle one incoming packet if skb
2681  * isn't NULL.  */
2682 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2683                               int amount_pull)
2684 {
2685         struct gfar_private *priv = netdev_priv(dev);
2686         struct rxfcb *fcb = NULL;
2687
2688         int ret;
2689
2690         /* fcb is at the beginning if exists */
2691         fcb = (struct rxfcb *)skb->data;
2692
2693         /* Remove the FCB from the skb */
2694         /* Remove the padded bytes, if there are any */
2695         if (amount_pull) {
2696                 skb_record_rx_queue(skb, fcb->rq);
2697                 skb_pull(skb, amount_pull);
2698         }
2699
2700         /* Get receive timestamp from the skb */
2701         if (priv->hwts_rx_en) {
2702                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2703                 u64 *ns = (u64 *) skb->data;
2704                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2705                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2706         }
2707
2708         if (priv->padding)
2709                 skb_pull(skb, priv->padding);
2710
2711         if (dev->features & NETIF_F_RXCSUM)
2712                 gfar_rx_checksum(skb, fcb);
2713
2714         /* Tell the skb what kind of packet this is */
2715         skb->protocol = eth_type_trans(skb, dev);
2716
2717         /* Set vlan tag */
2718         if (fcb->flags & RXFCB_VLN)
2719                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2720
2721         /* Send the packet up the stack */
2722         ret = netif_receive_skb(skb);
2723
2724         if (NET_RX_DROP == ret)
2725                 priv->extra_stats.kernel_dropped++;
2726
2727         return 0;
2728 }
2729
2730 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2731  *   until the budget/quota has been reached. Returns the number
2732  *   of frames handled
2733  */
2734 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2735 {
2736         struct net_device *dev = rx_queue->dev;
2737         struct rxbd8 *bdp, *base;
2738         struct sk_buff *skb;
2739         int pkt_len;
2740         int amount_pull;
2741         int howmany = 0;
2742         struct gfar_private *priv = netdev_priv(dev);
2743
2744         /* Get the first full descriptor */
2745         bdp = rx_queue->cur_rx;
2746         base = rx_queue->rx_bd_base;
2747
2748         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2749
2750         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2751                 struct sk_buff *newskb;
2752                 rmb();
2753
2754                 /* Add another skb for the future */
2755                 newskb = gfar_new_skb(dev);
2756
2757                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2758
2759                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2760                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2761
2762                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2763                                 bdp->length > priv->rx_buffer_size))
2764                         bdp->status = RXBD_LARGE;
2765
2766                 /* We drop the frame if we failed to allocate a new buffer */
2767                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2768                                  bdp->status & RXBD_ERR)) {
2769                         count_errors(bdp->status, dev);
2770
2771                         if (unlikely(!newskb))
2772                                 newskb = skb;
2773                         else if (skb)
2774                                 skb_queue_head(&priv->rx_recycle, skb);
2775                 } else {
2776                         /* Increment the number of packets */
2777                         rx_queue->stats.rx_packets++;
2778                         howmany++;
2779
2780                         if (likely(skb)) {
2781                                 pkt_len = bdp->length - ETH_FCS_LEN;
2782                                 /* Remove the FCS from the packet length */
2783                                 skb_put(skb, pkt_len);
2784                                 rx_queue->stats.rx_bytes += pkt_len;
2785                                 skb_record_rx_queue(skb, rx_queue->qindex);
2786                                 gfar_process_frame(dev, skb, amount_pull);
2787
2788                         } else {
2789                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2790                                 rx_queue->stats.rx_dropped++;
2791                                 priv->extra_stats.rx_skbmissing++;
2792                         }
2793
2794                 }
2795
2796                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2797
2798                 /* Setup the new bdp */
2799                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2800
2801                 /* Update to the next pointer */
2802                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2803
2804                 /* update to point at the next skb */
2805                 rx_queue->skb_currx =
2806                     (rx_queue->skb_currx + 1) &
2807                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2808         }
2809
2810         /* Update the current rxbd pointer to be the next one */
2811         rx_queue->cur_rx = bdp;
2812
2813         return howmany;
2814 }
2815
2816 static int gfar_poll(struct napi_struct *napi, int budget)
2817 {
2818         struct gfar_priv_grp *gfargrp = container_of(napi,
2819                         struct gfar_priv_grp, napi);
2820         struct gfar_private *priv = gfargrp->priv;
2821         struct gfar __iomem *regs = gfargrp->regs;
2822         struct gfar_priv_tx_q *tx_queue = NULL;
2823         struct gfar_priv_rx_q *rx_queue = NULL;
2824         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2825         int tx_cleaned = 0, i, left_over_budget = budget;
2826         unsigned long serviced_queues = 0;
2827         int num_queues = 0;
2828
2829         num_queues = gfargrp->num_rx_queues;
2830         budget_per_queue = budget/num_queues;
2831
2832         /* Clear IEVENT, so interrupts aren't called again
2833          * because of the packets that have already arrived */
2834         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2835
2836         while (num_queues && left_over_budget) {
2837
2838                 budget_per_queue = left_over_budget/num_queues;
2839                 left_over_budget = 0;
2840
2841                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2842                         if (test_bit(i, &serviced_queues))
2843                                 continue;
2844                         rx_queue = priv->rx_queue[i];
2845                         tx_queue = priv->tx_queue[rx_queue->qindex];
2846
2847                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2848                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2849                                                         budget_per_queue);
2850                         rx_cleaned += rx_cleaned_per_queue;
2851                         if(rx_cleaned_per_queue < budget_per_queue) {
2852                                 left_over_budget = left_over_budget +
2853                                         (budget_per_queue - rx_cleaned_per_queue);
2854                                 set_bit(i, &serviced_queues);
2855                                 num_queues--;
2856                         }
2857                 }
2858         }
2859
2860         if (tx_cleaned)
2861                 return budget;
2862
2863         if (rx_cleaned < budget) {
2864                 napi_complete(napi);
2865
2866                 /* Clear the halt bit in RSTAT */
2867                 gfar_write(&regs->rstat, gfargrp->rstat);
2868
2869                 gfar_write(&regs->imask, IMASK_DEFAULT);
2870
2871                 /* If we are coalescing interrupts, update the timer */
2872                 /* Otherwise, clear it */
2873                 gfar_configure_coalescing(priv,
2874                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2875         }
2876
2877         return rx_cleaned;
2878 }
2879
2880 #ifdef CONFIG_NET_POLL_CONTROLLER
2881 /*
2882  * Polling 'interrupt' - used by things like netconsole to send skbs
2883  * without having to re-enable interrupts. It's not called while
2884  * the interrupt routine is executing.
2885  */
2886 static void gfar_netpoll(struct net_device *dev)
2887 {
2888         struct gfar_private *priv = netdev_priv(dev);
2889         int i = 0;
2890
2891         /* If the device has multiple interrupts, run tx/rx */
2892         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2893                 for (i = 0; i < priv->num_grps; i++) {
2894                         disable_irq(priv->gfargrp[i].interruptTransmit);
2895                         disable_irq(priv->gfargrp[i].interruptReceive);
2896                         disable_irq(priv->gfargrp[i].interruptError);
2897                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2898                                                 &priv->gfargrp[i]);
2899                         enable_irq(priv->gfargrp[i].interruptError);
2900                         enable_irq(priv->gfargrp[i].interruptReceive);
2901                         enable_irq(priv->gfargrp[i].interruptTransmit);
2902                 }
2903         } else {
2904                 for (i = 0; i < priv->num_grps; i++) {
2905                         disable_irq(priv->gfargrp[i].interruptTransmit);
2906                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2907                                                 &priv->gfargrp[i]);
2908                         enable_irq(priv->gfargrp[i].interruptTransmit);
2909                 }
2910         }
2911 }
2912 #endif
2913
2914 /* The interrupt handler for devices with one interrupt */
2915 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2916 {
2917         struct gfar_priv_grp *gfargrp = grp_id;
2918
2919         /* Save ievent for future reference */
2920         u32 events = gfar_read(&gfargrp->regs->ievent);
2921
2922         /* Check for reception */
2923         if (events & IEVENT_RX_MASK)
2924                 gfar_receive(irq, grp_id);
2925
2926         /* Check for transmit completion */
2927         if (events & IEVENT_TX_MASK)
2928                 gfar_transmit(irq, grp_id);
2929
2930         /* Check for errors */
2931         if (events & IEVENT_ERR_MASK)
2932                 gfar_error(irq, grp_id);
2933
2934         return IRQ_HANDLED;
2935 }
2936
2937 /* Called every time the controller might need to be made
2938  * aware of new link state.  The PHY code conveys this
2939  * information through variables in the phydev structure, and this
2940  * function converts those variables into the appropriate
2941  * register values, and can bring down the device if needed.
2942  */
2943 static void adjust_link(struct net_device *dev)
2944 {
2945         struct gfar_private *priv = netdev_priv(dev);
2946         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2947         unsigned long flags;
2948         struct phy_device *phydev = priv->phydev;
2949         int new_state = 0;
2950
2951         local_irq_save(flags);
2952         lock_tx_qs(priv);
2953
2954         if (phydev->link) {
2955                 u32 tempval = gfar_read(&regs->maccfg2);
2956                 u32 ecntrl = gfar_read(&regs->ecntrl);
2957
2958                 /* Now we make sure that we can be in full duplex mode.
2959                  * If not, we operate in half-duplex mode. */
2960                 if (phydev->duplex != priv->oldduplex) {
2961                         new_state = 1;
2962                         if (!(phydev->duplex))
2963                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2964                         else
2965                                 tempval |= MACCFG2_FULL_DUPLEX;
2966
2967                         priv->oldduplex = phydev->duplex;
2968                 }
2969
2970                 if (phydev->speed != priv->oldspeed) {
2971                         new_state = 1;
2972                         switch (phydev->speed) {
2973                         case 1000:
2974                                 tempval =
2975                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2976
2977                                 ecntrl &= ~(ECNTRL_R100);
2978                                 break;
2979                         case 100:
2980                         case 10:
2981                                 tempval =
2982                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2983
2984                                 /* Reduced mode distinguishes
2985                                  * between 10 and 100 */
2986                                 if (phydev->speed == SPEED_100)
2987                                         ecntrl |= ECNTRL_R100;
2988                                 else
2989                                         ecntrl &= ~(ECNTRL_R100);
2990                                 break;
2991                         default:
2992                                 netif_warn(priv, link, dev,
2993                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
2994                                            phydev->speed);
2995                                 break;
2996                         }
2997
2998                         priv->oldspeed = phydev->speed;
2999                 }
3000
3001                 gfar_write(&regs->maccfg2, tempval);
3002                 gfar_write(&regs->ecntrl, ecntrl);
3003
3004                 if (!priv->oldlink) {
3005                         new_state = 1;
3006                         priv->oldlink = 1;
3007                 }
3008         } else if (priv->oldlink) {
3009                 new_state = 1;
3010                 priv->oldlink = 0;
3011                 priv->oldspeed = 0;
3012                 priv->oldduplex = -1;
3013         }
3014
3015         if (new_state && netif_msg_link(priv))
3016                 phy_print_status(phydev);
3017         unlock_tx_qs(priv);
3018         local_irq_restore(flags);
3019 }
3020
3021 /* Update the hash table based on the current list of multicast
3022  * addresses we subscribe to.  Also, change the promiscuity of
3023  * the device based on the flags (this function is called
3024  * whenever dev->flags is changed */
3025 static void gfar_set_multi(struct net_device *dev)
3026 {
3027         struct netdev_hw_addr *ha;
3028         struct gfar_private *priv = netdev_priv(dev);
3029         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3030         u32 tempval;
3031
3032         if (dev->flags & IFF_PROMISC) {
3033                 /* Set RCTRL to PROM */
3034                 tempval = gfar_read(&regs->rctrl);
3035                 tempval |= RCTRL_PROM;
3036                 gfar_write(&regs->rctrl, tempval);
3037         } else {
3038                 /* Set RCTRL to not PROM */
3039                 tempval = gfar_read(&regs->rctrl);
3040                 tempval &= ~(RCTRL_PROM);
3041                 gfar_write(&regs->rctrl, tempval);
3042         }
3043
3044         if (dev->flags & IFF_ALLMULTI) {
3045                 /* Set the hash to rx all multicast frames */
3046                 gfar_write(&regs->igaddr0, 0xffffffff);
3047                 gfar_write(&regs->igaddr1, 0xffffffff);
3048                 gfar_write(&regs->igaddr2, 0xffffffff);
3049                 gfar_write(&regs->igaddr3, 0xffffffff);
3050                 gfar_write(&regs->igaddr4, 0xffffffff);
3051                 gfar_write(&regs->igaddr5, 0xffffffff);
3052                 gfar_write(&regs->igaddr6, 0xffffffff);
3053                 gfar_write(&regs->igaddr7, 0xffffffff);
3054                 gfar_write(&regs->gaddr0, 0xffffffff);
3055                 gfar_write(&regs->gaddr1, 0xffffffff);
3056                 gfar_write(&regs->gaddr2, 0xffffffff);
3057                 gfar_write(&regs->gaddr3, 0xffffffff);
3058                 gfar_write(&regs->gaddr4, 0xffffffff);
3059                 gfar_write(&regs->gaddr5, 0xffffffff);
3060                 gfar_write(&regs->gaddr6, 0xffffffff);
3061                 gfar_write(&regs->gaddr7, 0xffffffff);
3062         } else {
3063                 int em_num;
3064                 int idx;
3065
3066                 /* zero out the hash */
3067                 gfar_write(&regs->igaddr0, 0x0);
3068                 gfar_write(&regs->igaddr1, 0x0);
3069                 gfar_write(&regs->igaddr2, 0x0);
3070                 gfar_write(&regs->igaddr3, 0x0);
3071                 gfar_write(&regs->igaddr4, 0x0);
3072                 gfar_write(&regs->igaddr5, 0x0);
3073                 gfar_write(&regs->igaddr6, 0x0);
3074                 gfar_write(&regs->igaddr7, 0x0);
3075                 gfar_write(&regs->gaddr0, 0x0);
3076                 gfar_write(&regs->gaddr1, 0x0);
3077                 gfar_write(&regs->gaddr2, 0x0);
3078                 gfar_write(&regs->gaddr3, 0x0);
3079                 gfar_write(&regs->gaddr4, 0x0);
3080                 gfar_write(&regs->gaddr5, 0x0);
3081                 gfar_write(&regs->gaddr6, 0x0);
3082                 gfar_write(&regs->gaddr7, 0x0);
3083
3084                 /* If we have extended hash tables, we need to
3085                  * clear the exact match registers to prepare for
3086                  * setting them */
3087                 if (priv->extended_hash) {
3088                         em_num = GFAR_EM_NUM + 1;
3089                         gfar_clear_exact_match(dev);
3090                         idx = 1;
3091                 } else {
3092                         idx = 0;
3093                         em_num = 0;
3094                 }
3095
3096                 if (netdev_mc_empty(dev))
3097                         return;
3098
3099                 /* Parse the list, and set the appropriate bits */
3100                 netdev_for_each_mc_addr(ha, dev) {
3101                         if (idx < em_num) {
3102                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3103                                 idx++;
3104                         } else
3105                                 gfar_set_hash_for_addr(dev, ha->addr);
3106                 }
3107         }
3108 }
3109
3110
3111 /* Clears each of the exact match registers to zero, so they
3112  * don't interfere with normal reception */
3113 static void gfar_clear_exact_match(struct net_device *dev)
3114 {
3115         int idx;
3116         static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
3117
3118         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3119                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3120 }
3121
3122 /* Set the appropriate hash bit for the given addr */
3123 /* The algorithm works like so:
3124  * 1) Take the Destination Address (ie the multicast address), and
3125  * do a CRC on it (little endian), and reverse the bits of the
3126  * result.
3127  * 2) Use the 8 most significant bits as a hash into a 256-entry
3128  * table.  The table is controlled through 8 32-bit registers:
3129  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3130  * gaddr7.  This means that the 3 most significant bits in the
3131  * hash index which gaddr register to use, and the 5 other bits
3132  * indicate which bit (assuming an IBM numbering scheme, which
3133  * for PowerPC (tm) is usually the case) in the register holds
3134  * the entry. */
3135 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3136 {
3137         u32 tempval;
3138         struct gfar_private *priv = netdev_priv(dev);
3139         u32 result = ether_crc(MAC_ADDR_LEN, addr);
3140         int width = priv->hash_width;
3141         u8 whichbit = (result >> (32 - width)) & 0x1f;
3142         u8 whichreg = result >> (32 - width + 5);
3143         u32 value = (1 << (31-whichbit));
3144
3145         tempval = gfar_read(priv->hash_regs[whichreg]);
3146         tempval |= value;
3147         gfar_write(priv->hash_regs[whichreg], tempval);
3148 }
3149
3150
3151 /* There are multiple MAC Address register pairs on some controllers
3152  * This function sets the numth pair to a given address
3153  */
3154 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3155                                   const u8 *addr)
3156 {
3157         struct gfar_private *priv = netdev_priv(dev);
3158         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3159         int idx;
3160         char tmpbuf[MAC_ADDR_LEN];
3161         u32 tempval;
3162         u32 __iomem *macptr = &regs->macstnaddr1;
3163
3164         macptr += num*2;
3165
3166         /* Now copy it into the mac registers backwards, cuz */
3167         /* little endian is silly */
3168         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3169                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3170
3171         gfar_write(macptr, *((u32 *) (tmpbuf)));
3172
3173         tempval = *((u32 *) (tmpbuf + 4));
3174
3175         gfar_write(macptr+1, tempval);
3176 }
3177
3178 /* GFAR error interrupt handler */
3179 static irqreturn_t gfar_error(int irq, void *grp_id)
3180 {
3181         struct gfar_priv_grp *gfargrp = grp_id;
3182         struct gfar __iomem *regs = gfargrp->regs;
3183         struct gfar_private *priv= gfargrp->priv;
3184         struct net_device *dev = priv->ndev;
3185
3186         /* Save ievent for future reference */
3187         u32 events = gfar_read(&regs->ievent);
3188
3189         /* Clear IEVENT */
3190         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3191
3192         /* Magic Packet is not an error. */
3193         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3194             (events & IEVENT_MAG))
3195                 events &= ~IEVENT_MAG;
3196
3197         /* Hmm... */
3198         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3199                 netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3200                            events, gfar_read(&regs->imask));
3201
3202         /* Update the error counters */
3203         if (events & IEVENT_TXE) {
3204                 dev->stats.tx_errors++;
3205
3206                 if (events & IEVENT_LC)
3207                         dev->stats.tx_window_errors++;
3208                 if (events & IEVENT_CRL)
3209                         dev->stats.tx_aborted_errors++;
3210                 if (events & IEVENT_XFUN) {
3211                         unsigned long flags;
3212
3213                         netif_dbg(priv, tx_err, dev,
3214                                   "TX FIFO underrun, packet dropped\n");
3215                         dev->stats.tx_dropped++;
3216                         priv->extra_stats.tx_underrun++;
3217
3218                         local_irq_save(flags);
3219                         lock_tx_qs(priv);
3220
3221                         /* Reactivate the Tx Queues */
3222                         gfar_write(&regs->tstat, gfargrp->tstat);
3223
3224                         unlock_tx_qs(priv);
3225                         local_irq_restore(flags);
3226                 }
3227                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3228         }
3229         if (events & IEVENT_BSY) {
3230                 dev->stats.rx_errors++;
3231                 priv->extra_stats.rx_bsy++;
3232
3233                 gfar_receive(irq, grp_id);
3234
3235                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3236                           gfar_read(&regs->rstat));
3237         }
3238         if (events & IEVENT_BABR) {
3239                 dev->stats.rx_errors++;
3240                 priv->extra_stats.rx_babr++;
3241
3242                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3243         }
3244         if (events & IEVENT_EBERR) {
3245                 priv->extra_stats.eberr++;
3246                 netif_dbg(priv, rx_err, dev, "bus error\n");
3247         }
3248         if (events & IEVENT_RXC)
3249                 netif_dbg(priv, rx_status, dev, "control frame\n");
3250
3251         if (events & IEVENT_BABT) {
3252                 priv->extra_stats.tx_babt++;
3253                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3254         }
3255         return IRQ_HANDLED;
3256 }
3257
3258 static struct of_device_id gfar_match[] =
3259 {
3260         {
3261                 .type = "network",
3262                 .compatible = "gianfar",
3263         },
3264         {
3265                 .compatible = "fsl,etsec2",
3266         },
3267         {},
3268 };
3269 MODULE_DEVICE_TABLE(of, gfar_match);
3270
3271 /* Structure for a device driver */
3272 static struct platform_driver gfar_driver = {
3273         .driver = {
3274                 .name = "fsl-gianfar",
3275                 .owner = THIS_MODULE,
3276                 .pm = GFAR_PM_OPS,
3277                 .of_match_table = gfar_match,
3278         },
3279         .probe = gfar_probe,
3280         .remove = gfar_remove,
3281 };
3282
3283 static int __init gfar_init(void)
3284 {
3285         return platform_driver_register(&gfar_driver);
3286 }
3287
3288 static void __exit gfar_exit(void)
3289 {
3290         platform_driver_unregister(&gfar_driver);
3291 }
3292
3293 module_init(gfar_init);
3294 module_exit(gfar_exit);
3295