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[~shefty/rdma-dev.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
44
45 #include "ixgbe.h"
46 #include "ixgbe_common.h"
47
48 char ixgbe_driver_name[] = "ixgbe";
49 static const char ixgbe_driver_string[] =
50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
51
52 #define DRV_VERSION "2.0.34-k2"
53 const char ixgbe_driver_version[] = DRV_VERSION;
54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
55
56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
57         [board_82598] = &ixgbe_82598_info,
58         [board_82599] = &ixgbe_82599_info,
59 };
60
61 /* ixgbe_pci_tbl - PCI Device ID Table
62  *
63  * Wildcard entries (PCI_ANY_ID) should come last
64  * Last entry must be all 0s
65  *
66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67  *   Class, Class Mask, private data (not used) }
68  */
69 static struct pci_device_id ixgbe_pci_tbl[] = {
70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71          board_82598 },
72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
73          board_82598 },
74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
75          board_82598 },
76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77          board_82598 },
78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
79          board_82598 },
80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
81          board_82598 },
82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
83          board_82598 },
84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
85          board_82598 },
86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
87          board_82598 },
88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
89          board_82598 },
90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
91          board_82598 },
92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
93          board_82599 },
94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
95          board_82599 },
96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
97          board_82599 },
98
99         /* required last entry */
100         {0, }
101 };
102 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
103
104 #ifdef CONFIG_IXGBE_DCA
105 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
106                             void *p);
107 static struct notifier_block dca_notifier = {
108         .notifier_call = ixgbe_notify_dca,
109         .next          = NULL,
110         .priority      = 0
111 };
112 #endif
113
114 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
115 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
116 MODULE_LICENSE("GPL");
117 MODULE_VERSION(DRV_VERSION);
118
119 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
120
121 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
122 {
123         u32 ctrl_ext;
124
125         /* Let firmware take over control of h/w */
126         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
127         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
128                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
129 }
130
131 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
132 {
133         u32 ctrl_ext;
134
135         /* Let firmware know the driver has taken over */
136         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
137         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
138                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
139 }
140
141 /*
142  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
143  * @adapter: pointer to adapter struct
144  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
145  * @queue: queue to map the corresponding interrupt to
146  * @msix_vector: the vector to map to the corresponding queue
147  *
148  */
149 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
150                            u8 queue, u8 msix_vector)
151 {
152         u32 ivar, index;
153         struct ixgbe_hw *hw = &adapter->hw;
154         switch (hw->mac.type) {
155         case ixgbe_mac_82598EB:
156                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
157                 if (direction == -1)
158                         direction = 0;
159                 index = (((direction * 64) + queue) >> 2) & 0x1F;
160                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
161                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
162                 ivar |= (msix_vector << (8 * (queue & 0x3)));
163                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
164                 break;
165         case ixgbe_mac_82599EB:
166                 if (direction == -1) {
167                         /* other causes */
168                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
169                         index = ((queue & 1) * 8);
170                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
171                         ivar &= ~(0xFF << index);
172                         ivar |= (msix_vector << index);
173                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
174                         break;
175                 } else {
176                         /* tx or rx causes */
177                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
178                         index = ((16 * (queue & 1)) + (8 * direction));
179                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
180                         ivar &= ~(0xFF << index);
181                         ivar |= (msix_vector << index);
182                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
183                         break;
184                 }
185         default:
186                 break;
187         }
188 }
189
190 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
191                                           u64 qmask)
192 {
193         u32 mask;
194
195         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
196                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
197                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
198         } else {
199                 mask = (qmask & 0xFFFFFFFF);
200                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
201                 mask = (qmask >> 32);
202                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
203         }
204 }
205
206 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
207                                              struct ixgbe_tx_buffer
208                                              *tx_buffer_info)
209 {
210         tx_buffer_info->dma = 0;
211         if (tx_buffer_info->skb) {
212                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
213                               DMA_TO_DEVICE);
214                 dev_kfree_skb_any(tx_buffer_info->skb);
215                 tx_buffer_info->skb = NULL;
216         }
217         tx_buffer_info->time_stamp = 0;
218         /* tx_buffer_info must be completely set up in the transmit path */
219 }
220
221 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
222                                        struct ixgbe_ring *tx_ring,
223                                        unsigned int eop)
224 {
225         struct ixgbe_hw *hw = &adapter->hw;
226
227         /* Detect a transmit hang in hardware, this serializes the
228          * check with the clearing of time_stamp and movement of eop */
229         adapter->detect_tx_hung = false;
230         if (tx_ring->tx_buffer_info[eop].time_stamp &&
231             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
232             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
233                 /* detected Tx unit hang */
234                 union ixgbe_adv_tx_desc *tx_desc;
235                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
236                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
237                         "  Tx Queue             <%d>\n"
238                         "  TDH, TDT             <%x>, <%x>\n"
239                         "  next_to_use          <%x>\n"
240                         "  next_to_clean        <%x>\n"
241                         "tx_buffer_info[next_to_clean]\n"
242                         "  time_stamp           <%lx>\n"
243                         "  jiffies              <%lx>\n",
244                         tx_ring->queue_index,
245                         IXGBE_READ_REG(hw, tx_ring->head),
246                         IXGBE_READ_REG(hw, tx_ring->tail),
247                         tx_ring->next_to_use, eop,
248                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
249                 return true;
250         }
251
252         return false;
253 }
254
255 #define IXGBE_MAX_TXD_PWR       14
256 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
257
258 /* Tx Descriptors needed, worst case */
259 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
260                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
261 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
262         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
263
264 static void ixgbe_tx_timeout(struct net_device *netdev);
265
266 /**
267  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
268  * @q_vector: structure containing interrupt and ring information
269  * @tx_ring: tx ring to clean
270  **/
271 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
272                                struct ixgbe_ring *tx_ring)
273 {
274         struct ixgbe_adapter *adapter = q_vector->adapter;
275         struct net_device *netdev = adapter->netdev;
276         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
277         struct ixgbe_tx_buffer *tx_buffer_info;
278         unsigned int i, eop, count = 0;
279         unsigned int total_bytes = 0, total_packets = 0;
280
281         i = tx_ring->next_to_clean;
282         eop = tx_ring->tx_buffer_info[i].next_to_watch;
283         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
284
285         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
286                (count < tx_ring->work_limit)) {
287                 bool cleaned = false;
288                 for ( ; !cleaned; count++) {
289                         struct sk_buff *skb;
290                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
291                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
292                         cleaned = (i == eop);
293                         skb = tx_buffer_info->skb;
294
295                         if (cleaned && skb) {
296                                 unsigned int segs, bytecount;
297                                 unsigned int hlen = skb_headlen(skb);
298
299                                 /* gso_segs is currently only valid for tcp */
300                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
301 #ifdef IXGBE_FCOE
302                                 /* adjust for FCoE Sequence Offload */
303                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
304                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
305                                     skb_is_gso(skb)) {
306                                         hlen = skb_transport_offset(skb) +
307                                                 sizeof(struct fc_frame_header) +
308                                                 sizeof(struct fcoe_crc_eof);
309                                         segs = DIV_ROUND_UP(skb->len - hlen,
310                                                 skb_shinfo(skb)->gso_size);
311                                 }
312 #endif /* IXGBE_FCOE */
313                                 /* multiply data chunks by size of headers */
314                                 bytecount = ((segs - 1) * hlen) + skb->len;
315                                 total_packets += segs;
316                                 total_bytes += bytecount;
317                         }
318
319                         ixgbe_unmap_and_free_tx_resource(adapter,
320                                                          tx_buffer_info);
321
322                         tx_desc->wb.status = 0;
323
324                         i++;
325                         if (i == tx_ring->count)
326                                 i = 0;
327                 }
328
329                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
330                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
331         }
332
333         tx_ring->next_to_clean = i;
334
335 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
336         if (unlikely(count && netif_carrier_ok(netdev) &&
337                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
338                 /* Make sure that anybody stopping the queue after this
339                  * sees the new next_to_clean.
340                  */
341                 smp_mb();
342                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
343                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
344                         netif_wake_subqueue(netdev, tx_ring->queue_index);
345                         ++adapter->restart_queue;
346                 }
347         }
348
349         if (adapter->detect_tx_hung) {
350                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
351                         /* schedule immediate reset if we believe we hung */
352                         DPRINTK(PROBE, INFO,
353                                 "tx hang %d detected, resetting adapter\n",
354                                 adapter->tx_timeout_count + 1);
355                         ixgbe_tx_timeout(adapter->netdev);
356                 }
357         }
358
359         /* re-arm the interrupt */
360         if (count >= tx_ring->work_limit)
361                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
362
363         tx_ring->total_bytes += total_bytes;
364         tx_ring->total_packets += total_packets;
365         tx_ring->stats.packets += total_packets;
366         tx_ring->stats.bytes += total_bytes;
367         adapter->net_stats.tx_bytes += total_bytes;
368         adapter->net_stats.tx_packets += total_packets;
369         return (count < tx_ring->work_limit);
370 }
371
372 #ifdef CONFIG_IXGBE_DCA
373 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
374                                 struct ixgbe_ring *rx_ring)
375 {
376         u32 rxctrl;
377         int cpu = get_cpu();
378         int q = rx_ring - adapter->rx_ring;
379
380         if (rx_ring->cpu != cpu) {
381                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
382                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
383                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
384                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
385                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
386                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
387                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
388                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
389                 }
390                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
391                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
392                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
393                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
394                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
395                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
396                 rx_ring->cpu = cpu;
397         }
398         put_cpu();
399 }
400
401 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
402                                 struct ixgbe_ring *tx_ring)
403 {
404         u32 txctrl;
405         int cpu = get_cpu();
406         int q = tx_ring - adapter->tx_ring;
407
408         if (tx_ring->cpu != cpu) {
409                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
410                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
411                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
412                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
413                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
414                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
415                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
416                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
417                 }
418                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
419                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
420                 tx_ring->cpu = cpu;
421         }
422         put_cpu();
423 }
424
425 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
426 {
427         int i;
428
429         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
430                 return;
431
432         /* always use CB2 mode, difference is masked in the CB driver */
433         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
434
435         for (i = 0; i < adapter->num_tx_queues; i++) {
436                 adapter->tx_ring[i].cpu = -1;
437                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
438         }
439         for (i = 0; i < adapter->num_rx_queues; i++) {
440                 adapter->rx_ring[i].cpu = -1;
441                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
442         }
443 }
444
445 static int __ixgbe_notify_dca(struct device *dev, void *data)
446 {
447         struct net_device *netdev = dev_get_drvdata(dev);
448         struct ixgbe_adapter *adapter = netdev_priv(netdev);
449         unsigned long event = *(unsigned long *)data;
450
451         switch (event) {
452         case DCA_PROVIDER_ADD:
453                 /* if we're already enabled, don't do it again */
454                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
455                         break;
456                 if (dca_add_requester(dev) == 0) {
457                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
458                         ixgbe_setup_dca(adapter);
459                         break;
460                 }
461                 /* Fall Through since DCA is disabled. */
462         case DCA_PROVIDER_REMOVE:
463                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
464                         dca_remove_requester(dev);
465                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
466                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
467                 }
468                 break;
469         }
470
471         return 0;
472 }
473
474 #endif /* CONFIG_IXGBE_DCA */
475 /**
476  * ixgbe_receive_skb - Send a completed packet up the stack
477  * @adapter: board private structure
478  * @skb: packet to send up
479  * @status: hardware indication of status of receive
480  * @rx_ring: rx descriptor ring (for a specific queue) to setup
481  * @rx_desc: rx descriptor
482  **/
483 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
484                               struct sk_buff *skb, u8 status,
485                               struct ixgbe_ring *ring,
486                               union ixgbe_adv_rx_desc *rx_desc)
487 {
488         struct ixgbe_adapter *adapter = q_vector->adapter;
489         struct napi_struct *napi = &q_vector->napi;
490         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
491         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
492
493         skb_record_rx_queue(skb, ring->queue_index);
494         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
495                 if (adapter->vlgrp && is_vlan && (tag != 0))
496                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
497                 else
498                         napi_gro_receive(napi, skb);
499         } else {
500                 if (adapter->vlgrp && is_vlan && (tag != 0))
501                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
502                 else
503                         netif_rx(skb);
504         }
505 }
506
507 /**
508  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
509  * @adapter: address of board private structure
510  * @status_err: hardware indication of status of receive
511  * @skb: skb currently being received and modified
512  **/
513 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
514                                      union ixgbe_adv_rx_desc *rx_desc,
515                                      struct sk_buff *skb)
516 {
517         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
518
519         skb->ip_summed = CHECKSUM_NONE;
520
521         /* Rx csum disabled */
522         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
523                 return;
524
525         /* if IP and error */
526         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
527             (status_err & IXGBE_RXDADV_ERR_IPE)) {
528                 adapter->hw_csum_rx_error++;
529                 return;
530         }
531
532         if (!(status_err & IXGBE_RXD_STAT_L4CS))
533                 return;
534
535         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
536                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
537
538                 /*
539                  * 82599 errata, UDP frames with a 0 checksum can be marked as
540                  * checksum errors.
541                  */
542                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
543                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
544                         return;
545
546                 adapter->hw_csum_rx_error++;
547                 return;
548         }
549
550         /* It must be a TCP or UDP packet with a valid checksum */
551         skb->ip_summed = CHECKSUM_UNNECESSARY;
552         adapter->hw_csum_rx_good++;
553 }
554
555 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
556                                          struct ixgbe_ring *rx_ring, u32 val)
557 {
558         /*
559          * Force memory writes to complete before letting h/w
560          * know there are new descriptors to fetch.  (Only
561          * applicable for weak-ordered memory model archs,
562          * such as IA-64).
563          */
564         wmb();
565         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
566 }
567
568 /**
569  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
570  * @adapter: address of board private structure
571  **/
572 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
573                                    struct ixgbe_ring *rx_ring,
574                                    int cleaned_count)
575 {
576         struct pci_dev *pdev = adapter->pdev;
577         union ixgbe_adv_rx_desc *rx_desc;
578         struct ixgbe_rx_buffer *bi;
579         unsigned int i;
580
581         i = rx_ring->next_to_use;
582         bi = &rx_ring->rx_buffer_info[i];
583
584         while (cleaned_count--) {
585                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
586
587                 if (!bi->page_dma &&
588                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
589                         if (!bi->page) {
590                                 bi->page = alloc_page(GFP_ATOMIC);
591                                 if (!bi->page) {
592                                         adapter->alloc_rx_page_failed++;
593                                         goto no_buffers;
594                                 }
595                                 bi->page_offset = 0;
596                         } else {
597                                 /* use a half page if we're re-using */
598                                 bi->page_offset ^= (PAGE_SIZE / 2);
599                         }
600
601                         bi->page_dma = pci_map_page(pdev, bi->page,
602                                                     bi->page_offset,
603                                                     (PAGE_SIZE / 2),
604                                                     PCI_DMA_FROMDEVICE);
605                 }
606
607                 if (!bi->skb) {
608                         struct sk_buff *skb;
609                         skb = netdev_alloc_skb(adapter->netdev,
610                                                (rx_ring->rx_buf_len +
611                                                 NET_IP_ALIGN));
612
613                         if (!skb) {
614                                 adapter->alloc_rx_buff_failed++;
615                                 goto no_buffers;
616                         }
617
618                         /*
619                          * Make buffer alignment 2 beyond a 16 byte boundary
620                          * this will result in a 16 byte aligned IP header after
621                          * the 14 byte MAC header is removed
622                          */
623                         skb_reserve(skb, NET_IP_ALIGN);
624
625                         bi->skb = skb;
626                         bi->dma = pci_map_single(pdev, skb->data,
627                                                  rx_ring->rx_buf_len,
628                                                  PCI_DMA_FROMDEVICE);
629                 }
630                 /* Refresh the desc even if buffer_addrs didn't change because
631                  * each write-back erases this info. */
632                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
633                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
634                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
635                 } else {
636                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
637                 }
638
639                 i++;
640                 if (i == rx_ring->count)
641                         i = 0;
642                 bi = &rx_ring->rx_buffer_info[i];
643         }
644
645 no_buffers:
646         if (rx_ring->next_to_use != i) {
647                 rx_ring->next_to_use = i;
648                 if (i-- == 0)
649                         i = (rx_ring->count - 1);
650
651                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
652         }
653 }
654
655 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
656 {
657         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
658 }
659
660 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
661 {
662         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
663 }
664
665 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
666 {
667         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
668                 IXGBE_RXDADV_RSCCNT_MASK) >>
669                 IXGBE_RXDADV_RSCCNT_SHIFT;
670 }
671
672 /**
673  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
674  * @skb: pointer to the last skb in the rsc queue
675  *
676  * This function changes a queue full of hw rsc buffers into a completed
677  * packet.  It uses the ->prev pointers to find the first packet and then
678  * turns it into the frag list owner.
679  **/
680 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
681 {
682         unsigned int frag_list_size = 0;
683
684         while (skb->prev) {
685                 struct sk_buff *prev = skb->prev;
686                 frag_list_size += skb->len;
687                 skb->prev = NULL;
688                 skb = prev;
689         }
690
691         skb_shinfo(skb)->frag_list = skb->next;
692         skb->next = NULL;
693         skb->len += frag_list_size;
694         skb->data_len += frag_list_size;
695         skb->truesize += frag_list_size;
696         return skb;
697 }
698
699 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
700                                struct ixgbe_ring *rx_ring,
701                                int *work_done, int work_to_do)
702 {
703         struct ixgbe_adapter *adapter = q_vector->adapter;
704         struct pci_dev *pdev = adapter->pdev;
705         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
706         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
707         struct sk_buff *skb;
708         unsigned int i, rsc_count = 0;
709         u32 len, staterr;
710         u16 hdr_info;
711         bool cleaned = false;
712         int cleaned_count = 0;
713         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
714 #ifdef IXGBE_FCOE
715         int ddp_bytes = 0;
716 #endif /* IXGBE_FCOE */
717
718         i = rx_ring->next_to_clean;
719         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
720         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
721         rx_buffer_info = &rx_ring->rx_buffer_info[i];
722
723         while (staterr & IXGBE_RXD_STAT_DD) {
724                 u32 upper_len = 0;
725                 if (*work_done >= work_to_do)
726                         break;
727                 (*work_done)++;
728
729                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
730                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
731                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
732                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
733                         if (hdr_info & IXGBE_RXDADV_SPH)
734                                 adapter->rx_hdr_split++;
735                         if (len > IXGBE_RX_HDR_SIZE)
736                                 len = IXGBE_RX_HDR_SIZE;
737                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
738                 } else {
739                         len = le16_to_cpu(rx_desc->wb.upper.length);
740                 }
741
742                 cleaned = true;
743                 skb = rx_buffer_info->skb;
744                 prefetch(skb->data - NET_IP_ALIGN);
745                 rx_buffer_info->skb = NULL;
746
747                 if (rx_buffer_info->dma) {
748                         pci_unmap_single(pdev, rx_buffer_info->dma,
749                                          rx_ring->rx_buf_len,
750                                          PCI_DMA_FROMDEVICE);
751                         rx_buffer_info->dma = 0;
752                         skb_put(skb, len);
753                 }
754
755                 if (upper_len) {
756                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
757                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
758                         rx_buffer_info->page_dma = 0;
759                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
760                                            rx_buffer_info->page,
761                                            rx_buffer_info->page_offset,
762                                            upper_len);
763
764                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
765                             (page_count(rx_buffer_info->page) != 1))
766                                 rx_buffer_info->page = NULL;
767                         else
768                                 get_page(rx_buffer_info->page);
769
770                         skb->len += upper_len;
771                         skb->data_len += upper_len;
772                         skb->truesize += upper_len;
773                 }
774
775                 i++;
776                 if (i == rx_ring->count)
777                         i = 0;
778
779                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
780                 prefetch(next_rxd);
781                 cleaned_count++;
782
783                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
784                         rsc_count = ixgbe_get_rsc_count(rx_desc);
785
786                 if (rsc_count) {
787                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
788                                      IXGBE_RXDADV_NEXTP_SHIFT;
789                         next_buffer = &rx_ring->rx_buffer_info[nextp];
790                         rx_ring->rsc_count += (rsc_count - 1);
791                 } else {
792                         next_buffer = &rx_ring->rx_buffer_info[i];
793                 }
794
795                 if (staterr & IXGBE_RXD_STAT_EOP) {
796                         if (skb->prev)
797                                 skb = ixgbe_transform_rsc_queue(skb);
798                         rx_ring->stats.packets++;
799                         rx_ring->stats.bytes += skb->len;
800                 } else {
801                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
802                                 rx_buffer_info->skb = next_buffer->skb;
803                                 rx_buffer_info->dma = next_buffer->dma;
804                                 next_buffer->skb = skb;
805                                 next_buffer->dma = 0;
806                         } else {
807                                 skb->next = next_buffer->skb;
808                                 skb->next->prev = skb;
809                         }
810                         adapter->non_eop_descs++;
811                         goto next_desc;
812                 }
813
814                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
815                         dev_kfree_skb_irq(skb);
816                         goto next_desc;
817                 }
818
819                 ixgbe_rx_checksum(adapter, rx_desc, skb);
820
821                 /* probably a little skewed due to removing CRC */
822                 total_rx_bytes += skb->len;
823                 total_rx_packets++;
824
825                 skb->protocol = eth_type_trans(skb, adapter->netdev);
826 #ifdef IXGBE_FCOE
827                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
828                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
829                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
830                         if (!ddp_bytes)
831                                 goto next_desc;
832                 }
833 #endif /* IXGBE_FCOE */
834                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
835
836 next_desc:
837                 rx_desc->wb.upper.status_error = 0;
838
839                 /* return some buffers to hardware, one at a time is too slow */
840                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
841                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
842                         cleaned_count = 0;
843                 }
844
845                 /* use prefetched values */
846                 rx_desc = next_rxd;
847                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
848
849                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
850         }
851
852         rx_ring->next_to_clean = i;
853         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
854
855         if (cleaned_count)
856                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
857
858 #ifdef IXGBE_FCOE
859         /* include DDPed FCoE data */
860         if (ddp_bytes > 0) {
861                 unsigned int mss;
862
863                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
864                         sizeof(struct fc_frame_header) -
865                         sizeof(struct fcoe_crc_eof);
866                 if (mss > 512)
867                         mss &= ~511;
868                 total_rx_bytes += ddp_bytes;
869                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
870         }
871 #endif /* IXGBE_FCOE */
872
873         rx_ring->total_packets += total_rx_packets;
874         rx_ring->total_bytes += total_rx_bytes;
875         adapter->net_stats.rx_bytes += total_rx_bytes;
876         adapter->net_stats.rx_packets += total_rx_packets;
877
878         return cleaned;
879 }
880
881 static int ixgbe_clean_rxonly(struct napi_struct *, int);
882 /**
883  * ixgbe_configure_msix - Configure MSI-X hardware
884  * @adapter: board private structure
885  *
886  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
887  * interrupts.
888  **/
889 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
890 {
891         struct ixgbe_q_vector *q_vector;
892         int i, j, q_vectors, v_idx, r_idx;
893         u32 mask;
894
895         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
896
897         /*
898          * Populate the IVAR table and set the ITR values to the
899          * corresponding register.
900          */
901         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
902                 q_vector = adapter->q_vector[v_idx];
903                 /* XXX for_each_bit(...) */
904                 r_idx = find_first_bit(q_vector->rxr_idx,
905                                        adapter->num_rx_queues);
906
907                 for (i = 0; i < q_vector->rxr_count; i++) {
908                         j = adapter->rx_ring[r_idx].reg_idx;
909                         ixgbe_set_ivar(adapter, 0, j, v_idx);
910                         r_idx = find_next_bit(q_vector->rxr_idx,
911                                               adapter->num_rx_queues,
912                                               r_idx + 1);
913                 }
914                 r_idx = find_first_bit(q_vector->txr_idx,
915                                        adapter->num_tx_queues);
916
917                 for (i = 0; i < q_vector->txr_count; i++) {
918                         j = adapter->tx_ring[r_idx].reg_idx;
919                         ixgbe_set_ivar(adapter, 1, j, v_idx);
920                         r_idx = find_next_bit(q_vector->txr_idx,
921                                               adapter->num_tx_queues,
922                                               r_idx + 1);
923                 }
924
925                 /* if this is a tx only vector halve the interrupt rate */
926                 if (q_vector->txr_count && !q_vector->rxr_count)
927                         q_vector->eitr = (adapter->eitr_param >> 1);
928                 else if (q_vector->rxr_count)
929                         /* rx only */
930                         q_vector->eitr = adapter->eitr_param;
931
932                 ixgbe_write_eitr(q_vector);
933         }
934
935         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
936                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
937                                v_idx);
938         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
939                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
940         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
941
942         /* set up to autoclear timer, and the vectors */
943         mask = IXGBE_EIMS_ENABLE_MASK;
944         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
945         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
946 }
947
948 enum latency_range {
949         lowest_latency = 0,
950         low_latency = 1,
951         bulk_latency = 2,
952         latency_invalid = 255
953 };
954
955 /**
956  * ixgbe_update_itr - update the dynamic ITR value based on statistics
957  * @adapter: pointer to adapter
958  * @eitr: eitr setting (ints per sec) to give last timeslice
959  * @itr_setting: current throttle rate in ints/second
960  * @packets: the number of packets during this measurement interval
961  * @bytes: the number of bytes during this measurement interval
962  *
963  *      Stores a new ITR value based on packets and byte
964  *      counts during the last interrupt.  The advantage of per interrupt
965  *      computation is faster updates and more accurate ITR for the current
966  *      traffic pattern.  Constants in this function were computed
967  *      based on theoretical maximum wire speed and thresholds were set based
968  *      on testing data as well as attempting to minimize response time
969  *      while increasing bulk throughput.
970  *      this functionality is controlled by the InterruptThrottleRate module
971  *      parameter (see ixgbe_param.c)
972  **/
973 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
974                            u32 eitr, u8 itr_setting,
975                            int packets, int bytes)
976 {
977         unsigned int retval = itr_setting;
978         u32 timepassed_us;
979         u64 bytes_perint;
980
981         if (packets == 0)
982                 goto update_itr_done;
983
984
985         /* simple throttlerate management
986          *    0-20MB/s lowest (100000 ints/s)
987          *   20-100MB/s low   (20000 ints/s)
988          *  100-1249MB/s bulk (8000 ints/s)
989          */
990         /* what was last interrupt timeslice? */
991         timepassed_us = 1000000/eitr;
992         bytes_perint = bytes / timepassed_us; /* bytes/usec */
993
994         switch (itr_setting) {
995         case lowest_latency:
996                 if (bytes_perint > adapter->eitr_low)
997                         retval = low_latency;
998                 break;
999         case low_latency:
1000                 if (bytes_perint > adapter->eitr_high)
1001                         retval = bulk_latency;
1002                 else if (bytes_perint <= adapter->eitr_low)
1003                         retval = lowest_latency;
1004                 break;
1005         case bulk_latency:
1006                 if (bytes_perint <= adapter->eitr_high)
1007                         retval = low_latency;
1008                 break;
1009         }
1010
1011 update_itr_done:
1012         return retval;
1013 }
1014
1015 /**
1016  * ixgbe_write_eitr - write EITR register in hardware specific way
1017  * @q_vector: structure containing interrupt and ring information
1018  *
1019  * This function is made to be called by ethtool and by the driver
1020  * when it needs to update EITR registers at runtime.  Hardware
1021  * specific quirks/differences are taken care of here.
1022  */
1023 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1024 {
1025         struct ixgbe_adapter *adapter = q_vector->adapter;
1026         struct ixgbe_hw *hw = &adapter->hw;
1027         int v_idx = q_vector->v_idx;
1028         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1029
1030         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1031                 /* must write high and low 16 bits to reset counter */
1032                 itr_reg |= (itr_reg << 16);
1033         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1034                 /*
1035                  * set the WDIS bit to not clear the timer bits and cause an
1036                  * immediate assertion of the interrupt
1037                  */
1038                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1039         }
1040         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1041 }
1042
1043 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1044 {
1045         struct ixgbe_adapter *adapter = q_vector->adapter;
1046         u32 new_itr;
1047         u8 current_itr, ret_itr;
1048         int i, r_idx;
1049         struct ixgbe_ring *rx_ring, *tx_ring;
1050
1051         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1052         for (i = 0; i < q_vector->txr_count; i++) {
1053                 tx_ring = &(adapter->tx_ring[r_idx]);
1054                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1055                                            q_vector->tx_itr,
1056                                            tx_ring->total_packets,
1057                                            tx_ring->total_bytes);
1058                 /* if the result for this queue would decrease interrupt
1059                  * rate for this vector then use that result */
1060                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1061                                     q_vector->tx_itr - 1 : ret_itr);
1062                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1063                                       r_idx + 1);
1064         }
1065
1066         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1067         for (i = 0; i < q_vector->rxr_count; i++) {
1068                 rx_ring = &(adapter->rx_ring[r_idx]);
1069                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1070                                            q_vector->rx_itr,
1071                                            rx_ring->total_packets,
1072                                            rx_ring->total_bytes);
1073                 /* if the result for this queue would decrease interrupt
1074                  * rate for this vector then use that result */
1075                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1076                                     q_vector->rx_itr - 1 : ret_itr);
1077                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1078                                       r_idx + 1);
1079         }
1080
1081         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1082
1083         switch (current_itr) {
1084         /* counts and packets in update_itr are dependent on these numbers */
1085         case lowest_latency:
1086                 new_itr = 100000;
1087                 break;
1088         case low_latency:
1089                 new_itr = 20000; /* aka hwitr = ~200 */
1090                 break;
1091         case bulk_latency:
1092         default:
1093                 new_itr = 8000;
1094                 break;
1095         }
1096
1097         if (new_itr != q_vector->eitr) {
1098                 /* do an exponential smoothing */
1099                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1100
1101                 /* save the algorithm value here, not the smoothed one */
1102                 q_vector->eitr = new_itr;
1103
1104                 ixgbe_write_eitr(q_vector);
1105         }
1106
1107         return;
1108 }
1109
1110 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1111 {
1112         struct ixgbe_hw *hw = &adapter->hw;
1113
1114         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1115             (eicr & IXGBE_EICR_GPI_SDP1)) {
1116                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1117                 /* write to clear the interrupt */
1118                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1119         }
1120 }
1121
1122 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1123 {
1124         struct ixgbe_hw *hw = &adapter->hw;
1125
1126         if (eicr & IXGBE_EICR_GPI_SDP1) {
1127                 /* Clear the interrupt */
1128                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1129                 schedule_work(&adapter->multispeed_fiber_task);
1130         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1131                 /* Clear the interrupt */
1132                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1133                 schedule_work(&adapter->sfp_config_module_task);
1134         } else {
1135                 /* Interrupt isn't for us... */
1136                 return;
1137         }
1138 }
1139
1140 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1141 {
1142         struct ixgbe_hw *hw = &adapter->hw;
1143
1144         adapter->lsc_int++;
1145         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1146         adapter->link_check_timeout = jiffies;
1147         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1148                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1149                 schedule_work(&adapter->watchdog_task);
1150         }
1151 }
1152
1153 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1154 {
1155         struct net_device *netdev = data;
1156         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1157         struct ixgbe_hw *hw = &adapter->hw;
1158         u32 eicr;
1159
1160         /*
1161          * Workaround for Silicon errata.  Use clear-by-write instead
1162          * of clear-by-read.  Reading with EICS will return the
1163          * interrupt causes without clearing, which later be done
1164          * with the write to EICR.
1165          */
1166         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1167         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1168
1169         if (eicr & IXGBE_EICR_LSC)
1170                 ixgbe_check_lsc(adapter);
1171
1172         if (hw->mac.type == ixgbe_mac_82598EB)
1173                 ixgbe_check_fan_failure(adapter, eicr);
1174
1175         if (hw->mac.type == ixgbe_mac_82599EB) {
1176                 ixgbe_check_sfp_event(adapter, eicr);
1177
1178                 /* Handle Flow Director Full threshold interrupt */
1179                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1180                         int i;
1181                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1182                         /* Disable transmits before FDIR Re-initialization */
1183                         netif_tx_stop_all_queues(netdev);
1184                         for (i = 0; i < adapter->num_tx_queues; i++) {
1185                                 struct ixgbe_ring *tx_ring =
1186                                                            &adapter->tx_ring[i];
1187                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1188                                                        &tx_ring->reinit_state))
1189                                         schedule_work(&adapter->fdir_reinit_task);
1190                         }
1191                 }
1192         }
1193         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1194                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1195
1196         return IRQ_HANDLED;
1197 }
1198
1199 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1200                                            u64 qmask)
1201 {
1202         u32 mask;
1203
1204         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1207         } else {
1208                 mask = (qmask & 0xFFFFFFFF);
1209                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1210                 mask = (qmask >> 32);
1211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1212         }
1213         /* skip the flush */
1214 }
1215
1216 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1217                                             u64 qmask)
1218 {
1219         u32 mask;
1220
1221         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1222                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1223                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1224         } else {
1225                 mask = (qmask & 0xFFFFFFFF);
1226                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1227                 mask = (qmask >> 32);
1228                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1229         }
1230         /* skip the flush */
1231 }
1232
1233 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1234 {
1235         struct ixgbe_q_vector *q_vector = data;
1236         struct ixgbe_adapter  *adapter = q_vector->adapter;
1237         struct ixgbe_ring     *tx_ring;
1238         int i, r_idx;
1239
1240         if (!q_vector->txr_count)
1241                 return IRQ_HANDLED;
1242
1243         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1244         for (i = 0; i < q_vector->txr_count; i++) {
1245                 tx_ring = &(adapter->tx_ring[r_idx]);
1246                 tx_ring->total_bytes = 0;
1247                 tx_ring->total_packets = 0;
1248                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1249                                       r_idx + 1);
1250         }
1251
1252         /* disable interrupts on this vector only */
1253         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1254         napi_schedule(&q_vector->napi);
1255
1256         return IRQ_HANDLED;
1257 }
1258
1259 /**
1260  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1261  * @irq: unused
1262  * @data: pointer to our q_vector struct for this interrupt vector
1263  **/
1264 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1265 {
1266         struct ixgbe_q_vector *q_vector = data;
1267         struct ixgbe_adapter  *adapter = q_vector->adapter;
1268         struct ixgbe_ring  *rx_ring;
1269         int r_idx;
1270         int i;
1271
1272         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1273         for (i = 0;  i < q_vector->rxr_count; i++) {
1274                 rx_ring = &(adapter->rx_ring[r_idx]);
1275                 rx_ring->total_bytes = 0;
1276                 rx_ring->total_packets = 0;
1277                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1278                                       r_idx + 1);
1279         }
1280
1281         if (!q_vector->rxr_count)
1282                 return IRQ_HANDLED;
1283
1284         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1285         rx_ring = &(adapter->rx_ring[r_idx]);
1286         /* disable interrupts on this vector only */
1287         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1288         napi_schedule(&q_vector->napi);
1289
1290         return IRQ_HANDLED;
1291 }
1292
1293 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1294 {
1295         struct ixgbe_q_vector *q_vector = data;
1296         struct ixgbe_adapter  *adapter = q_vector->adapter;
1297         struct ixgbe_ring  *ring;
1298         int r_idx;
1299         int i;
1300
1301         if (!q_vector->txr_count && !q_vector->rxr_count)
1302                 return IRQ_HANDLED;
1303
1304         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1305         for (i = 0; i < q_vector->txr_count; i++) {
1306                 ring = &(adapter->tx_ring[r_idx]);
1307                 ring->total_bytes = 0;
1308                 ring->total_packets = 0;
1309                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1310                                       r_idx + 1);
1311         }
1312
1313         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1314         for (i = 0; i < q_vector->rxr_count; i++) {
1315                 ring = &(adapter->rx_ring[r_idx]);
1316                 ring->total_bytes = 0;
1317                 ring->total_packets = 0;
1318                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1319                                       r_idx + 1);
1320         }
1321
1322         /* disable interrupts on this vector only */
1323         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1324         napi_schedule(&q_vector->napi);
1325
1326         return IRQ_HANDLED;
1327 }
1328
1329 /**
1330  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1331  * @napi: napi struct with our devices info in it
1332  * @budget: amount of work driver is allowed to do this pass, in packets
1333  *
1334  * This function is optimized for cleaning one queue only on a single
1335  * q_vector!!!
1336  **/
1337 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1338 {
1339         struct ixgbe_q_vector *q_vector =
1340                                container_of(napi, struct ixgbe_q_vector, napi);
1341         struct ixgbe_adapter *adapter = q_vector->adapter;
1342         struct ixgbe_ring *rx_ring = NULL;
1343         int work_done = 0;
1344         long r_idx;
1345
1346         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1347         rx_ring = &(adapter->rx_ring[r_idx]);
1348 #ifdef CONFIG_IXGBE_DCA
1349         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1350                 ixgbe_update_rx_dca(adapter, rx_ring);
1351 #endif
1352
1353         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1354
1355         /* If all Rx work done, exit the polling mode */
1356         if (work_done < budget) {
1357                 napi_complete(napi);
1358                 if (adapter->itr_setting & 1)
1359                         ixgbe_set_itr_msix(q_vector);
1360                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1361                         ixgbe_irq_enable_queues(adapter,
1362                                                 ((u64)1 << q_vector->v_idx));
1363         }
1364
1365         return work_done;
1366 }
1367
1368 /**
1369  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1370  * @napi: napi struct with our devices info in it
1371  * @budget: amount of work driver is allowed to do this pass, in packets
1372  *
1373  * This function will clean more than one rx queue associated with a
1374  * q_vector.
1375  **/
1376 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1377 {
1378         struct ixgbe_q_vector *q_vector =
1379                                container_of(napi, struct ixgbe_q_vector, napi);
1380         struct ixgbe_adapter *adapter = q_vector->adapter;
1381         struct ixgbe_ring *ring = NULL;
1382         int work_done = 0, i;
1383         long r_idx;
1384         bool tx_clean_complete = true;
1385
1386         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1387         for (i = 0; i < q_vector->txr_count; i++) {
1388                 ring = &(adapter->tx_ring[r_idx]);
1389 #ifdef CONFIG_IXGBE_DCA
1390                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391                         ixgbe_update_tx_dca(adapter, ring);
1392 #endif
1393                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1394                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1395                                       r_idx + 1);
1396         }
1397
1398         /* attempt to distribute budget to each queue fairly, but don't allow
1399          * the budget to go below 1 because we'll exit polling */
1400         budget /= (q_vector->rxr_count ?: 1);
1401         budget = max(budget, 1);
1402         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1403         for (i = 0; i < q_vector->rxr_count; i++) {
1404                 ring = &(adapter->rx_ring[r_idx]);
1405 #ifdef CONFIG_IXGBE_DCA
1406                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1407                         ixgbe_update_rx_dca(adapter, ring);
1408 #endif
1409                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1410                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1411                                       r_idx + 1);
1412         }
1413
1414         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1415         ring = &(adapter->rx_ring[r_idx]);
1416         /* If all Rx work done, exit the polling mode */
1417         if (work_done < budget) {
1418                 napi_complete(napi);
1419                 if (adapter->itr_setting & 1)
1420                         ixgbe_set_itr_msix(q_vector);
1421                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1422                         ixgbe_irq_enable_queues(adapter,
1423                                                 ((u64)1 << q_vector->v_idx));
1424                 return 0;
1425         }
1426
1427         return work_done;
1428 }
1429
1430 /**
1431  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1432  * @napi: napi struct with our devices info in it
1433  * @budget: amount of work driver is allowed to do this pass, in packets
1434  *
1435  * This function is optimized for cleaning one queue only on a single
1436  * q_vector!!!
1437  **/
1438 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1439 {
1440         struct ixgbe_q_vector *q_vector =
1441                                container_of(napi, struct ixgbe_q_vector, napi);
1442         struct ixgbe_adapter *adapter = q_vector->adapter;
1443         struct ixgbe_ring *tx_ring = NULL;
1444         int work_done = 0;
1445         long r_idx;
1446
1447         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1448         tx_ring = &(adapter->tx_ring[r_idx]);
1449 #ifdef CONFIG_IXGBE_DCA
1450         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1451                 ixgbe_update_tx_dca(adapter, tx_ring);
1452 #endif
1453
1454         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1455                 work_done = budget;
1456
1457         /* If all Rx work done, exit the polling mode */
1458         if (work_done < budget) {
1459                 napi_complete(napi);
1460                 if (adapter->itr_setting & 1)
1461                         ixgbe_set_itr_msix(q_vector);
1462                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1463                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1464         }
1465
1466         return work_done;
1467 }
1468
1469 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1470                                      int r_idx)
1471 {
1472         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1473
1474         set_bit(r_idx, q_vector->rxr_idx);
1475         q_vector->rxr_count++;
1476 }
1477
1478 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1479                                      int t_idx)
1480 {
1481         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1482
1483         set_bit(t_idx, q_vector->txr_idx);
1484         q_vector->txr_count++;
1485 }
1486
1487 /**
1488  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1489  * @adapter: board private structure to initialize
1490  * @vectors: allotted vector count for descriptor rings
1491  *
1492  * This function maps descriptor rings to the queue-specific vectors
1493  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1494  * one vector per ring/queue, but on a constrained vector budget, we
1495  * group the rings as "efficiently" as possible.  You would add new
1496  * mapping configurations in here.
1497  **/
1498 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1499                                       int vectors)
1500 {
1501         int v_start = 0;
1502         int rxr_idx = 0, txr_idx = 0;
1503         int rxr_remaining = adapter->num_rx_queues;
1504         int txr_remaining = adapter->num_tx_queues;
1505         int i, j;
1506         int rqpv, tqpv;
1507         int err = 0;
1508
1509         /* No mapping required if MSI-X is disabled. */
1510         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1511                 goto out;
1512
1513         /*
1514          * The ideal configuration...
1515          * We have enough vectors to map one per queue.
1516          */
1517         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1518                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1519                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1520
1521                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1522                         map_vector_to_txq(adapter, v_start, txr_idx);
1523
1524                 goto out;
1525         }
1526
1527         /*
1528          * If we don't have enough vectors for a 1-to-1
1529          * mapping, we'll have to group them so there are
1530          * multiple queues per vector.
1531          */
1532         /* Re-adjusting *qpv takes care of the remainder. */
1533         for (i = v_start; i < vectors; i++) {
1534                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1535                 for (j = 0; j < rqpv; j++) {
1536                         map_vector_to_rxq(adapter, i, rxr_idx);
1537                         rxr_idx++;
1538                         rxr_remaining--;
1539                 }
1540         }
1541         for (i = v_start; i < vectors; i++) {
1542                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1543                 for (j = 0; j < tqpv; j++) {
1544                         map_vector_to_txq(adapter, i, txr_idx);
1545                         txr_idx++;
1546                         txr_remaining--;
1547                 }
1548         }
1549
1550 out:
1551         return err;
1552 }
1553
1554 /**
1555  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1556  * @adapter: board private structure
1557  *
1558  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1559  * interrupts from the kernel.
1560  **/
1561 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1562 {
1563         struct net_device *netdev = adapter->netdev;
1564         irqreturn_t (*handler)(int, void *);
1565         int i, vector, q_vectors, err;
1566         int ri=0, ti=0;
1567
1568         /* Decrement for Other and TCP Timer vectors */
1569         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1570
1571         /* Map the Tx/Rx rings to the vectors we were allotted. */
1572         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1573         if (err)
1574                 goto out;
1575
1576 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1577                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1578                          &ixgbe_msix_clean_many)
1579         for (vector = 0; vector < q_vectors; vector++) {
1580                 handler = SET_HANDLER(adapter->q_vector[vector]);
1581
1582                 if(handler == &ixgbe_msix_clean_rx) {
1583                         sprintf(adapter->name[vector], "%s-%s-%d",
1584                                 netdev->name, "rx", ri++);
1585                 }
1586                 else if(handler == &ixgbe_msix_clean_tx) {
1587                         sprintf(adapter->name[vector], "%s-%s-%d",
1588                                 netdev->name, "tx", ti++);
1589                 }
1590                 else
1591                         sprintf(adapter->name[vector], "%s-%s-%d",
1592                                 netdev->name, "TxRx", vector);
1593
1594                 err = request_irq(adapter->msix_entries[vector].vector,
1595                                   handler, 0, adapter->name[vector],
1596                                   adapter->q_vector[vector]);
1597                 if (err) {
1598                         DPRINTK(PROBE, ERR,
1599                                 "request_irq failed for MSIX interrupt "
1600                                 "Error: %d\n", err);
1601                         goto free_queue_irqs;
1602                 }
1603         }
1604
1605         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1606         err = request_irq(adapter->msix_entries[vector].vector,
1607                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1608         if (err) {
1609                 DPRINTK(PROBE, ERR,
1610                         "request_irq for msix_lsc failed: %d\n", err);
1611                 goto free_queue_irqs;
1612         }
1613
1614         return 0;
1615
1616 free_queue_irqs:
1617         for (i = vector - 1; i >= 0; i--)
1618                 free_irq(adapter->msix_entries[--vector].vector,
1619                          adapter->q_vector[i]);
1620         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1621         pci_disable_msix(adapter->pdev);
1622         kfree(adapter->msix_entries);
1623         adapter->msix_entries = NULL;
1624 out:
1625         return err;
1626 }
1627
1628 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1629 {
1630         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1631         u8 current_itr;
1632         u32 new_itr = q_vector->eitr;
1633         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1634         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1635
1636         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1637                                             q_vector->tx_itr,
1638                                             tx_ring->total_packets,
1639                                             tx_ring->total_bytes);
1640         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1641                                             q_vector->rx_itr,
1642                                             rx_ring->total_packets,
1643                                             rx_ring->total_bytes);
1644
1645         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1646
1647         switch (current_itr) {
1648         /* counts and packets in update_itr are dependent on these numbers */
1649         case lowest_latency:
1650                 new_itr = 100000;
1651                 break;
1652         case low_latency:
1653                 new_itr = 20000; /* aka hwitr = ~200 */
1654                 break;
1655         case bulk_latency:
1656                 new_itr = 8000;
1657                 break;
1658         default:
1659                 break;
1660         }
1661
1662         if (new_itr != q_vector->eitr) {
1663                 /* do an exponential smoothing */
1664                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1665
1666                 /* save the algorithm value here, not the smoothed one */
1667                 q_vector->eitr = new_itr;
1668
1669                 ixgbe_write_eitr(q_vector);
1670         }
1671
1672         return;
1673 }
1674
1675 /**
1676  * ixgbe_irq_enable - Enable default interrupt generation settings
1677  * @adapter: board private structure
1678  **/
1679 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1680 {
1681         u32 mask;
1682
1683         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1684         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1685                 mask |= IXGBE_EIMS_GPI_SDP1;
1686         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1687                 mask |= IXGBE_EIMS_ECC;
1688                 mask |= IXGBE_EIMS_GPI_SDP1;
1689                 mask |= IXGBE_EIMS_GPI_SDP2;
1690         }
1691         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1692             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1693                 mask |= IXGBE_EIMS_FLOW_DIR;
1694
1695         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1696         ixgbe_irq_enable_queues(adapter, ~0);
1697         IXGBE_WRITE_FLUSH(&adapter->hw);
1698 }
1699
1700 /**
1701  * ixgbe_intr - legacy mode Interrupt Handler
1702  * @irq: interrupt number
1703  * @data: pointer to a network interface device structure
1704  **/
1705 static irqreturn_t ixgbe_intr(int irq, void *data)
1706 {
1707         struct net_device *netdev = data;
1708         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1709         struct ixgbe_hw *hw = &adapter->hw;
1710         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1711         u32 eicr;
1712
1713         /*
1714          * Workaround for silicon errata.  Mask the interrupts
1715          * before the read of EICR.
1716          */
1717         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1718
1719         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1720          * therefore no explict interrupt disable is necessary */
1721         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1722         if (!eicr) {
1723                 /* shared interrupt alert!
1724                  * make sure interrupts are enabled because the read will
1725                  * have disabled interrupts due to EIAM */
1726                 ixgbe_irq_enable(adapter);
1727                 return IRQ_NONE;        /* Not our interrupt */
1728         }
1729
1730         if (eicr & IXGBE_EICR_LSC)
1731                 ixgbe_check_lsc(adapter);
1732
1733         if (hw->mac.type == ixgbe_mac_82599EB)
1734                 ixgbe_check_sfp_event(adapter, eicr);
1735
1736         ixgbe_check_fan_failure(adapter, eicr);
1737
1738         if (napi_schedule_prep(&(q_vector->napi))) {
1739                 adapter->tx_ring[0].total_packets = 0;
1740                 adapter->tx_ring[0].total_bytes = 0;
1741                 adapter->rx_ring[0].total_packets = 0;
1742                 adapter->rx_ring[0].total_bytes = 0;
1743                 /* would disable interrupts here but EIAM disabled it */
1744                 __napi_schedule(&(q_vector->napi));
1745         }
1746
1747         return IRQ_HANDLED;
1748 }
1749
1750 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1751 {
1752         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1753
1754         for (i = 0; i < q_vectors; i++) {
1755                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1756                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1757                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1758                 q_vector->rxr_count = 0;
1759                 q_vector->txr_count = 0;
1760         }
1761 }
1762
1763 /**
1764  * ixgbe_request_irq - initialize interrupts
1765  * @adapter: board private structure
1766  *
1767  * Attempts to configure interrupts using the best available
1768  * capabilities of the hardware and kernel.
1769  **/
1770 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1771 {
1772         struct net_device *netdev = adapter->netdev;
1773         int err;
1774
1775         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1776                 err = ixgbe_request_msix_irqs(adapter);
1777         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1778                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1779                                   netdev->name, netdev);
1780         } else {
1781                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1782                                   netdev->name, netdev);
1783         }
1784
1785         if (err)
1786                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1787
1788         return err;
1789 }
1790
1791 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1792 {
1793         struct net_device *netdev = adapter->netdev;
1794
1795         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1796                 int i, q_vectors;
1797
1798                 q_vectors = adapter->num_msix_vectors;
1799
1800                 i = q_vectors - 1;
1801                 free_irq(adapter->msix_entries[i].vector, netdev);
1802
1803                 i--;
1804                 for (; i >= 0; i--) {
1805                         free_irq(adapter->msix_entries[i].vector,
1806                                  adapter->q_vector[i]);
1807                 }
1808
1809                 ixgbe_reset_q_vectors(adapter);
1810         } else {
1811                 free_irq(adapter->pdev->irq, netdev);
1812         }
1813 }
1814
1815 /**
1816  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1817  * @adapter: board private structure
1818  **/
1819 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1820 {
1821         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1822                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1823         } else {
1824                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1825                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1826                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1827         }
1828         IXGBE_WRITE_FLUSH(&adapter->hw);
1829         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1830                 int i;
1831                 for (i = 0; i < adapter->num_msix_vectors; i++)
1832                         synchronize_irq(adapter->msix_entries[i].vector);
1833         } else {
1834                 synchronize_irq(adapter->pdev->irq);
1835         }
1836 }
1837
1838 /**
1839  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1840  *
1841  **/
1842 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1843 {
1844         struct ixgbe_hw *hw = &adapter->hw;
1845
1846         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1847                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1848
1849         ixgbe_set_ivar(adapter, 0, 0, 0);
1850         ixgbe_set_ivar(adapter, 1, 0, 0);
1851
1852         map_vector_to_rxq(adapter, 0, 0);
1853         map_vector_to_txq(adapter, 0, 0);
1854
1855         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1856 }
1857
1858 /**
1859  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1860  * @adapter: board private structure
1861  *
1862  * Configure the Tx unit of the MAC after a reset.
1863  **/
1864 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1865 {
1866         u64 tdba;
1867         struct ixgbe_hw *hw = &adapter->hw;
1868         u32 i, j, tdlen, txctrl;
1869
1870         /* Setup the HW Tx Head and Tail descriptor pointers */
1871         for (i = 0; i < adapter->num_tx_queues; i++) {
1872                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1873                 j = ring->reg_idx;
1874                 tdba = ring->dma;
1875                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1876                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1877                                 (tdba & DMA_BIT_MASK(32)));
1878                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1879                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1880                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1881                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1882                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1883                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1884                 /* Disable Tx Head Writeback RO bit, since this hoses
1885                  * bookkeeping if things aren't delivered in order.
1886                  */
1887                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1888                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1889                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1890         }
1891         if (hw->mac.type == ixgbe_mac_82599EB) {
1892                 /* We enable 8 traffic classes, DCB only */
1893                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1894                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1895                                         IXGBE_MTQC_8TC_8TQ));
1896         }
1897 }
1898
1899 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1900
1901 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1902 {
1903         struct ixgbe_ring *rx_ring;
1904         u32 srrctl;
1905         int queue0 = 0;
1906         unsigned long mask;
1907         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1908
1909         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1910                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1911                         int dcb_i = feature[RING_F_DCB].indices;
1912                         if (dcb_i == 8)
1913                                 queue0 = index >> 4;
1914                         else if (dcb_i == 4)
1915                                 queue0 = index >> 5;
1916                         else
1917                                 dev_err(&adapter->pdev->dev, "Invalid DCB "
1918                                         "configuration\n");
1919 #ifdef IXGBE_FCOE
1920                         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1921                                 struct ixgbe_ring_feature *f;
1922
1923                                 rx_ring = &adapter->rx_ring[queue0];
1924                                 f = &adapter->ring_feature[RING_F_FCOE];
1925                                 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1926                                         queue0 = f->mask + index -
1927                                                  rx_ring->reg_idx - 1;
1928                         }
1929 #endif /* IXGBE_FCOE */
1930                 } else {
1931                         queue0 = index;
1932                 }
1933         } else {
1934                 mask = (unsigned long) feature[RING_F_RSS].mask;
1935                 queue0 = index & mask;
1936                 index = index & mask;
1937         }
1938
1939         rx_ring = &adapter->rx_ring[queue0];
1940
1941         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1942
1943         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1944         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1945
1946         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1947                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1948
1949         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1950 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1951                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1952 #else
1953                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1954 #endif
1955                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1956         } else {
1957                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1958                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1959                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1960         }
1961
1962         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1963 }
1964
1965 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1966 {
1967         u32 mrqc = 0;
1968         int mask;
1969
1970         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1971                 return mrqc;
1972
1973         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1974 #ifdef CONFIG_IXGBE_DCB
1975                                  | IXGBE_FLAG_DCB_ENABLED
1976 #endif
1977                                 );
1978
1979         switch (mask) {
1980         case (IXGBE_FLAG_RSS_ENABLED):
1981                 mrqc = IXGBE_MRQC_RSSEN;
1982                 break;
1983 #ifdef CONFIG_IXGBE_DCB
1984         case (IXGBE_FLAG_DCB_ENABLED):
1985                 mrqc = IXGBE_MRQC_RT8TCEN;
1986                 break;
1987 #endif /* CONFIG_IXGBE_DCB */
1988         default:
1989                 break;
1990         }
1991
1992         return mrqc;
1993 }
1994
1995 /**
1996  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1997  * @adapter: board private structure
1998  *
1999  * Configure the Rx unit of the MAC after a reset.
2000  **/
2001 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2002 {
2003         u64 rdba;
2004         struct ixgbe_hw *hw = &adapter->hw;
2005         struct net_device *netdev = adapter->netdev;
2006         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2007         int i, j;
2008         u32 rdlen, rxctrl, rxcsum;
2009         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2010                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2011                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2012         u32 fctrl, hlreg0;
2013         u32 reta = 0, mrqc = 0;
2014         u32 rdrxctl;
2015         u32 rscctrl;
2016         int rx_buf_len;
2017
2018         /* Decide whether to use packet split mode or not */
2019         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2020
2021 #ifdef IXGBE_FCOE
2022         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2023                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2024 #endif /* IXGBE_FCOE */
2025
2026         /* Set the RX buffer length according to the mode */
2027         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2028                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2029                 if (hw->mac.type == ixgbe_mac_82599EB) {
2030                         /* PSRTYPE must be initialized in 82599 */
2031                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2032                                       IXGBE_PSRTYPE_UDPHDR |
2033                                       IXGBE_PSRTYPE_IPV4HDR |
2034                                       IXGBE_PSRTYPE_IPV6HDR |
2035                                       IXGBE_PSRTYPE_L2HDR;
2036                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2037                 }
2038         } else {
2039                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2040                     (netdev->mtu <= ETH_DATA_LEN))
2041                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2042                 else
2043                         rx_buf_len = ALIGN(max_frame, 1024);
2044         }
2045
2046         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2047         fctrl |= IXGBE_FCTRL_BAM;
2048         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2049         fctrl |= IXGBE_FCTRL_PMCF;
2050         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2051
2052         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2053         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2054                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2055         else
2056                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2057 #ifdef IXGBE_FCOE
2058         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2059                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2060 #endif
2061         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2062
2063         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2064         /* disable receives while setting up the descriptors */
2065         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2066         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2067
2068         /*
2069          * Setup the HW Rx Head and Tail Descriptor Pointers and
2070          * the Base and Length of the Rx Descriptor Ring
2071          */
2072         for (i = 0; i < adapter->num_rx_queues; i++) {
2073                 rdba = adapter->rx_ring[i].dma;
2074                 j = adapter->rx_ring[i].reg_idx;
2075                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2076                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2077                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2078                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2079                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2080                 adapter->rx_ring[i].head = IXGBE_RDH(j);
2081                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
2082                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
2083
2084 #ifdef IXGBE_FCOE
2085                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2086                         struct ixgbe_ring_feature *f;
2087                         f = &adapter->ring_feature[RING_F_FCOE];
2088                         if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2089                             (i >= f->mask) && (i < f->mask + f->indices))
2090                                 adapter->rx_ring[i].rx_buf_len =
2091                                         IXGBE_FCOE_JUMBO_FRAME_SIZE;
2092                 }
2093
2094 #endif /* IXGBE_FCOE */
2095                 ixgbe_configure_srrctl(adapter, j);
2096         }
2097
2098         if (hw->mac.type == ixgbe_mac_82598EB) {
2099                 /*
2100                  * For VMDq support of different descriptor types or
2101                  * buffer sizes through the use of multiple SRRCTL
2102                  * registers, RDRXCTL.MVMEN must be set to 1
2103                  *
2104                  * also, the manual doesn't mention it clearly but DCA hints
2105                  * will only use queue 0's tags unless this bit is set.  Side
2106                  * effects of setting this bit are only that SRRCTL must be
2107                  * fully programmed [0..15]
2108                  */
2109                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2110                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2111                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2112         }
2113
2114         /* Program MRQC for the distribution of queues */
2115         mrqc = ixgbe_setup_mrqc(adapter);
2116
2117         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2118                 /* Fill out redirection table */
2119                 for (i = 0, j = 0; i < 128; i++, j++) {
2120                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2121                                 j = 0;
2122                         /* reta = 4-byte sliding window of
2123                          * 0x00..(indices-1)(indices-1)00..etc. */
2124                         reta = (reta << 8) | (j * 0x11);
2125                         if ((i & 3) == 3)
2126                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2127                 }
2128
2129                 /* Fill out hash function seeds */
2130                 for (i = 0; i < 10; i++)
2131                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2132
2133                 if (hw->mac.type == ixgbe_mac_82598EB)
2134                         mrqc |= IXGBE_MRQC_RSSEN;
2135                     /* Perform hash on these packet types */
2136                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2137                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2138                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2139                       | IXGBE_MRQC_RSS_FIELD_IPV6
2140                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2141                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2142         }
2143         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2144
2145         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2146
2147         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2148             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2149                 /* Disable indicating checksum in descriptor, enables
2150                  * RSS hash */
2151                 rxcsum |= IXGBE_RXCSUM_PCSD;
2152         }
2153         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2154                 /* Enable IPv4 payload checksum for UDP fragments
2155                  * if PCSD is not set */
2156                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2157         }
2158
2159         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2160
2161         if (hw->mac.type == ixgbe_mac_82599EB) {
2162                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2163                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2164                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2165                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2166         }
2167
2168         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2169                 /* Enable 82599 HW-RSC */
2170                 for (i = 0; i < adapter->num_rx_queues; i++) {
2171                         j = adapter->rx_ring[i].reg_idx;
2172                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2173                         rscctrl |= IXGBE_RSCCTL_RSCEN;
2174                         /*
2175                          * we must limit the number of descriptors so that the
2176                          * total size of max desc * buf_len is not greater
2177                          * than 65535
2178                          */
2179                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2180 #if (MAX_SKB_FRAGS > 16)
2181                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2182 #elif (MAX_SKB_FRAGS > 8)
2183                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2184 #elif (MAX_SKB_FRAGS > 4)
2185                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2186 #else
2187                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2188 #endif
2189                         } else {
2190                                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2191                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2192                                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2193                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2194                                 else
2195                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2196                         }
2197                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2198                 }
2199                 /* Disable RSC for ACK packets */
2200                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2201                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2202         }
2203 }
2204
2205 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2206 {
2207         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2208         struct ixgbe_hw *hw = &adapter->hw;
2209
2210         /* add VID to filter table */
2211         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2212 }
2213
2214 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2215 {
2216         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2217         struct ixgbe_hw *hw = &adapter->hw;
2218
2219         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2220                 ixgbe_irq_disable(adapter);
2221
2222         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2223
2224         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2225                 ixgbe_irq_enable(adapter);
2226
2227         /* remove VID from filter table */
2228         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2229 }
2230
2231 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2232                                    struct vlan_group *grp)
2233 {
2234         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2235         u32 ctrl;
2236         int i, j;
2237
2238         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2239                 ixgbe_irq_disable(adapter);
2240         adapter->vlgrp = grp;
2241
2242         /*
2243          * For a DCB driver, always enable VLAN tag stripping so we can
2244          * still receive traffic from a DCB-enabled host even if we're
2245          * not in DCB mode.
2246          */
2247         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2248         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2249                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2250                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2251                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2252         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2253                 ctrl |= IXGBE_VLNCTRL_VFE;
2254                 /* enable VLAN tag insert/strip */
2255                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2256                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2257                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2258                 for (i = 0; i < adapter->num_rx_queues; i++) {
2259                         j = adapter->rx_ring[i].reg_idx;
2260                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2261                         ctrl |= IXGBE_RXDCTL_VME;
2262                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2263                 }
2264         }
2265         ixgbe_vlan_rx_add_vid(netdev, 0);
2266
2267         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2268                 ixgbe_irq_enable(adapter);
2269 }
2270
2271 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2272 {
2273         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2274
2275         if (adapter->vlgrp) {
2276                 u16 vid;
2277                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2278                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2279                                 continue;
2280                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2281                 }
2282         }
2283 }
2284
2285 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2286 {
2287         struct dev_mc_list *mc_ptr;
2288         u8 *addr = *mc_addr_ptr;
2289         *vmdq = 0;
2290
2291         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2292         if (mc_ptr->next)
2293                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2294         else
2295                 *mc_addr_ptr = NULL;
2296
2297         return addr;
2298 }
2299
2300 /**
2301  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2302  * @netdev: network interface device structure
2303  *
2304  * The set_rx_method entry point is called whenever the unicast/multicast
2305  * address list or the network interface flags are updated.  This routine is
2306  * responsible for configuring the hardware for proper unicast, multicast and
2307  * promiscuous mode.
2308  **/
2309 static void ixgbe_set_rx_mode(struct net_device *netdev)
2310 {
2311         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2312         struct ixgbe_hw *hw = &adapter->hw;
2313         u32 fctrl, vlnctrl;
2314         u8 *addr_list = NULL;
2315         int addr_count = 0;
2316
2317         /* Check for Promiscuous and All Multicast modes */
2318
2319         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2320         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2321
2322         if (netdev->flags & IFF_PROMISC) {
2323                 hw->addr_ctrl.user_set_promisc = 1;
2324                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2325                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2326         } else {
2327                 if (netdev->flags & IFF_ALLMULTI) {
2328                         fctrl |= IXGBE_FCTRL_MPE;
2329                         fctrl &= ~IXGBE_FCTRL_UPE;
2330                 } else {
2331                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2332                 }
2333                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2334                 hw->addr_ctrl.user_set_promisc = 0;
2335         }
2336
2337         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2338         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2339
2340         /* reprogram secondary unicast list */
2341         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2342
2343         /* reprogram multicast list */
2344         addr_count = netdev->mc_count;
2345         if (addr_count)
2346                 addr_list = netdev->mc_list->dmi_addr;
2347         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2348                                         ixgbe_addr_list_itr);
2349 }
2350
2351 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2352 {
2353         int q_idx;
2354         struct ixgbe_q_vector *q_vector;
2355         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2356
2357         /* legacy and MSI only use one vector */
2358         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2359                 q_vectors = 1;
2360
2361         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2362                 struct napi_struct *napi;
2363                 q_vector = adapter->q_vector[q_idx];
2364                 napi = &q_vector->napi;
2365                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2366                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2367                                 if (q_vector->txr_count == 1)
2368                                         napi->poll = &ixgbe_clean_txonly;
2369                                 else if (q_vector->rxr_count == 1)
2370                                         napi->poll = &ixgbe_clean_rxonly;
2371                         }
2372                 }
2373
2374                 napi_enable(napi);
2375         }
2376 }
2377
2378 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2379 {
2380         int q_idx;
2381         struct ixgbe_q_vector *q_vector;
2382         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2383
2384         /* legacy and MSI only use one vector */
2385         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2386                 q_vectors = 1;
2387
2388         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2389                 q_vector = adapter->q_vector[q_idx];
2390                 napi_disable(&q_vector->napi);
2391         }
2392 }
2393
2394 #ifdef CONFIG_IXGBE_DCB
2395 /*
2396  * ixgbe_configure_dcb - Configure DCB hardware
2397  * @adapter: ixgbe adapter struct
2398  *
2399  * This is called by the driver on open to configure the DCB hardware.
2400  * This is also called by the gennetlink interface when reconfiguring
2401  * the DCB state.
2402  */
2403 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2404 {
2405         struct ixgbe_hw *hw = &adapter->hw;
2406         u32 txdctl, vlnctrl;
2407         int i, j;
2408
2409         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2410         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2411         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2412
2413         /* reconfigure the hardware */
2414         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2415
2416         for (i = 0; i < adapter->num_tx_queues; i++) {
2417                 j = adapter->tx_ring[i].reg_idx;
2418                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2419                 /* PThresh workaround for Tx hang with DFP enabled. */
2420                 txdctl |= 32;
2421                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2422         }
2423         /* Enable VLAN tag insert/strip */
2424         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2425         if (hw->mac.type == ixgbe_mac_82598EB) {
2426                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2427                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2428                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2429         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2430                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2431                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2432                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2433                 for (i = 0; i < adapter->num_rx_queues; i++) {
2434                         j = adapter->rx_ring[i].reg_idx;
2435                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2436                         vlnctrl |= IXGBE_RXDCTL_VME;
2437                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2438                 }
2439         }
2440         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2441 }
2442
2443 #endif
2444 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2445 {
2446         struct net_device *netdev = adapter->netdev;
2447         struct ixgbe_hw *hw = &adapter->hw;
2448         int i;
2449
2450         ixgbe_set_rx_mode(netdev);
2451
2452         ixgbe_restore_vlan(adapter);
2453 #ifdef CONFIG_IXGBE_DCB
2454         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2455                 netif_set_gso_max_size(netdev, 32768);
2456                 ixgbe_configure_dcb(adapter);
2457         } else {
2458                 netif_set_gso_max_size(netdev, 65536);
2459         }
2460 #else
2461         netif_set_gso_max_size(netdev, 65536);
2462 #endif
2463
2464 #ifdef IXGBE_FCOE
2465         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2466                 ixgbe_configure_fcoe(adapter);
2467
2468 #endif /* IXGBE_FCOE */
2469         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2470                 for (i = 0; i < adapter->num_tx_queues; i++)
2471                         adapter->tx_ring[i].atr_sample_rate =
2472                                                        adapter->atr_sample_rate;
2473                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2474         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2475                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2476         }
2477
2478         ixgbe_configure_tx(adapter);
2479         ixgbe_configure_rx(adapter);
2480         for (i = 0; i < adapter->num_rx_queues; i++)
2481                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2482                                        (adapter->rx_ring[i].count - 1));
2483 }
2484
2485 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2486 {
2487         switch (hw->phy.type) {
2488         case ixgbe_phy_sfp_avago:
2489         case ixgbe_phy_sfp_ftl:
2490         case ixgbe_phy_sfp_intel:
2491         case ixgbe_phy_sfp_unknown:
2492         case ixgbe_phy_tw_tyco:
2493         case ixgbe_phy_tw_unknown:
2494                 return true;
2495         default:
2496                 return false;
2497         }
2498 }
2499
2500 /**
2501  * ixgbe_sfp_link_config - set up SFP+ link
2502  * @adapter: pointer to private adapter struct
2503  **/
2504 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2505 {
2506         struct ixgbe_hw *hw = &adapter->hw;
2507
2508                 if (hw->phy.multispeed_fiber) {
2509                         /*
2510                          * In multispeed fiber setups, the device may not have
2511                          * had a physical connection when the driver loaded.
2512                          * If that's the case, the initial link configuration
2513                          * couldn't get the MAC into 10G or 1G mode, so we'll
2514                          * never have a link status change interrupt fire.
2515                          * We need to try and force an autonegotiation
2516                          * session, then bring up link.
2517                          */
2518                         hw->mac.ops.setup_sfp(hw);
2519                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2520                                 schedule_work(&adapter->multispeed_fiber_task);
2521                 } else {
2522                         /*
2523                          * Direct Attach Cu and non-multispeed fiber modules
2524                          * still need to be configured properly prior to
2525                          * attempting link.
2526                          */
2527                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2528                                 schedule_work(&adapter->sfp_config_module_task);
2529                 }
2530 }
2531
2532 /**
2533  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2534  * @hw: pointer to private hardware struct
2535  *
2536  * Returns 0 on success, negative on failure
2537  **/
2538 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2539 {
2540         u32 autoneg;
2541         bool link_up = false;
2542         u32 ret = IXGBE_ERR_LINK_SETUP;
2543
2544         if (hw->mac.ops.check_link)
2545                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2546
2547         if (ret)
2548                 goto link_cfg_out;
2549
2550         if (hw->mac.ops.get_link_capabilities)
2551                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2552                                                         &hw->mac.autoneg);
2553         if (ret)
2554                 goto link_cfg_out;
2555
2556         if (hw->mac.ops.setup_link_speed)
2557                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2558 link_cfg_out:
2559         return ret;
2560 }
2561
2562 #define IXGBE_MAX_RX_DESC_POLL 10
2563 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2564                                               int rxr)
2565 {
2566         int j = adapter->rx_ring[rxr].reg_idx;
2567         int k;
2568
2569         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2570                 if (IXGBE_READ_REG(&adapter->hw,
2571                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2572                         break;
2573                 else
2574                         msleep(1);
2575         }
2576         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2577                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2578                         "not set within the polling period\n", rxr);
2579         }
2580         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2581                               (adapter->rx_ring[rxr].count - 1));
2582 }
2583
2584 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2585 {
2586         struct net_device *netdev = adapter->netdev;
2587         struct ixgbe_hw *hw = &adapter->hw;
2588         int i, j = 0;
2589         int num_rx_rings = adapter->num_rx_queues;
2590         int err;
2591         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2592         u32 txdctl, rxdctl, mhadd;
2593         u32 dmatxctl;
2594         u32 gpie;
2595
2596         ixgbe_get_hw_control(adapter);
2597
2598         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2599             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2600                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2601                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2602                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2603                 } else {
2604                         /* MSI only */
2605                         gpie = 0;
2606                 }
2607                 /* XXX: to interrupt immediately for EICS writes, enable this */
2608                 /* gpie |= IXGBE_GPIE_EIMEN; */
2609                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2610         }
2611
2612         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2613                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2614                  * specifically only auto mask tx and rx interrupts */
2615                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2616         }
2617
2618         /* Enable fan failure interrupt if media type is copper */
2619         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2620                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2621                 gpie |= IXGBE_SDP1_GPIEN;
2622                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2623         }
2624
2625         if (hw->mac.type == ixgbe_mac_82599EB) {
2626                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2627                 gpie |= IXGBE_SDP1_GPIEN;
2628                 gpie |= IXGBE_SDP2_GPIEN;
2629                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2630         }
2631
2632 #ifdef IXGBE_FCOE
2633         /* adjust max frame to be able to do baby jumbo for FCoE */
2634         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2635             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2636                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2637
2638 #endif /* IXGBE_FCOE */
2639         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2640         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2641                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2642                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2643
2644                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2645         }
2646
2647         for (i = 0; i < adapter->num_tx_queues; i++) {
2648                 j = adapter->tx_ring[i].reg_idx;
2649                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2650                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2651                 txdctl |= (8 << 16);
2652                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2653         }
2654
2655         if (hw->mac.type == ixgbe_mac_82599EB) {
2656                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2657                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2658                 dmatxctl |= IXGBE_DMATXCTL_TE;
2659                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2660         }
2661         for (i = 0; i < adapter->num_tx_queues; i++) {
2662                 j = adapter->tx_ring[i].reg_idx;
2663                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2664                 txdctl |= IXGBE_TXDCTL_ENABLE;
2665                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2666         }
2667
2668         for (i = 0; i < num_rx_rings; i++) {
2669                 j = adapter->rx_ring[i].reg_idx;
2670                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2671                 /* enable PTHRESH=32 descriptors (half the internal cache)
2672                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2673                  * this also removes a pesky rx_no_buffer_count increment */
2674                 rxdctl |= 0x0020;
2675                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2676                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2677                 if (hw->mac.type == ixgbe_mac_82599EB)
2678                         ixgbe_rx_desc_queue_enable(adapter, i);
2679         }
2680         /* enable all receives */
2681         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2682         if (hw->mac.type == ixgbe_mac_82598EB)
2683                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2684         else
2685                 rxdctl |= IXGBE_RXCTRL_RXEN;
2686         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2687
2688         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2689                 ixgbe_configure_msix(adapter);
2690         else
2691                 ixgbe_configure_msi_and_legacy(adapter);
2692
2693         clear_bit(__IXGBE_DOWN, &adapter->state);
2694         ixgbe_napi_enable_all(adapter);
2695
2696         /* clear any pending interrupts, may auto mask */
2697         IXGBE_READ_REG(hw, IXGBE_EICR);
2698
2699         ixgbe_irq_enable(adapter);
2700
2701         /*
2702          * If this adapter has a fan, check to see if we had a failure
2703          * before we enabled the interrupt.
2704          */
2705         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2706                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2707                 if (esdp & IXGBE_ESDP_SDP1)
2708                         DPRINTK(DRV, CRIT,
2709                                 "Fan has stopped, replace the adapter\n");
2710         }
2711
2712         /*
2713          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2714          * arrived before interrupts were enabled but after probe.  Such
2715          * devices wouldn't have their type identified yet. We need to
2716          * kick off the SFP+ module setup first, then try to bring up link.
2717          * If we're not hot-pluggable SFP+, we just need to configure link
2718          * and bring it up.
2719          */
2720         if (hw->phy.type == ixgbe_phy_unknown) {
2721                 err = hw->phy.ops.identify(hw);
2722                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2723                         /*
2724                          * Take the device down and schedule the sfp tasklet
2725                          * which will unregister_netdev and log it.
2726                          */
2727                         ixgbe_down(adapter);
2728                         schedule_work(&adapter->sfp_config_module_task);
2729                         return err;
2730                 }
2731         }
2732
2733         if (ixgbe_is_sfp(hw)) {
2734                 ixgbe_sfp_link_config(adapter);
2735         } else {
2736                 err = ixgbe_non_sfp_link_config(hw);
2737                 if (err)
2738                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2739         }
2740
2741         for (i = 0; i < adapter->num_tx_queues; i++)
2742                 set_bit(__IXGBE_FDIR_INIT_DONE,
2743                         &(adapter->tx_ring[i].reinit_state));
2744
2745         /* enable transmits */
2746         netif_tx_start_all_queues(netdev);
2747
2748         /* bring the link up in the watchdog, this could race with our first
2749          * link up interrupt but shouldn't be a problem */
2750         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2751         adapter->link_check_timeout = jiffies;
2752         mod_timer(&adapter->watchdog_timer, jiffies);
2753         return 0;
2754 }
2755
2756 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2757 {
2758         WARN_ON(in_interrupt());
2759         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2760                 msleep(1);
2761         ixgbe_down(adapter);
2762         ixgbe_up(adapter);
2763         clear_bit(__IXGBE_RESETTING, &adapter->state);
2764 }
2765
2766 int ixgbe_up(struct ixgbe_adapter *adapter)
2767 {
2768         /* hardware has been reset, we need to reload some things */
2769         ixgbe_configure(adapter);
2770
2771         return ixgbe_up_complete(adapter);
2772 }
2773
2774 void ixgbe_reset(struct ixgbe_adapter *adapter)
2775 {
2776         struct ixgbe_hw *hw = &adapter->hw;
2777         int err;
2778
2779         err = hw->mac.ops.init_hw(hw);
2780         switch (err) {
2781         case 0:
2782         case IXGBE_ERR_SFP_NOT_PRESENT:
2783                 break;
2784         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2785                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2786                 break;
2787         case IXGBE_ERR_EEPROM_VERSION:
2788                 /* We are running on a pre-production device, log a warning */
2789                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2790                          "adapter/LOM.  Please be aware there may be issues "
2791                          "associated with your hardware.  If you are "
2792                          "experiencing problems please contact your Intel or "
2793                          "hardware representative who provided you with this "
2794                          "hardware.\n");
2795                 break;
2796         default:
2797                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2798         }
2799
2800         /* reprogram the RAR[0] in case user changed it. */
2801         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2802 }
2803
2804 /**
2805  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2806  * @adapter: board private structure
2807  * @rx_ring: ring to free buffers from
2808  **/
2809 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2810                                 struct ixgbe_ring *rx_ring)
2811 {
2812         struct pci_dev *pdev = adapter->pdev;
2813         unsigned long size;
2814         unsigned int i;
2815
2816         /* Free all the Rx ring sk_buffs */
2817
2818         for (i = 0; i < rx_ring->count; i++) {
2819                 struct ixgbe_rx_buffer *rx_buffer_info;
2820
2821                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2822                 if (rx_buffer_info->dma) {
2823                         pci_unmap_single(pdev, rx_buffer_info->dma,
2824                                          rx_ring->rx_buf_len,
2825                                          PCI_DMA_FROMDEVICE);
2826                         rx_buffer_info->dma = 0;
2827                 }
2828                 if (rx_buffer_info->skb) {
2829                         struct sk_buff *skb = rx_buffer_info->skb;
2830                         rx_buffer_info->skb = NULL;
2831                         do {
2832                                 struct sk_buff *this = skb;
2833                                 skb = skb->prev;
2834                                 dev_kfree_skb(this);
2835                         } while (skb);
2836                 }
2837                 if (!rx_buffer_info->page)
2838                         continue;
2839                 if (rx_buffer_info->page_dma) {
2840                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2841                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2842                         rx_buffer_info->page_dma = 0;
2843                 }
2844                 put_page(rx_buffer_info->page);
2845                 rx_buffer_info->page = NULL;
2846                 rx_buffer_info->page_offset = 0;
2847         }
2848
2849         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2850         memset(rx_ring->rx_buffer_info, 0, size);
2851
2852         /* Zero out the descriptor ring */
2853         memset(rx_ring->desc, 0, rx_ring->size);
2854
2855         rx_ring->next_to_clean = 0;
2856         rx_ring->next_to_use = 0;
2857
2858         if (rx_ring->head)
2859                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2860         if (rx_ring->tail)
2861                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2862 }
2863
2864 /**
2865  * ixgbe_clean_tx_ring - Free Tx Buffers
2866  * @adapter: board private structure
2867  * @tx_ring: ring to be cleaned
2868  **/
2869 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2870                                 struct ixgbe_ring *tx_ring)
2871 {
2872         struct ixgbe_tx_buffer *tx_buffer_info;
2873         unsigned long size;
2874         unsigned int i;
2875
2876         /* Free all the Tx ring sk_buffs */
2877
2878         for (i = 0; i < tx_ring->count; i++) {
2879                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2880                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2881         }
2882
2883         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2884         memset(tx_ring->tx_buffer_info, 0, size);
2885
2886         /* Zero out the descriptor ring */
2887         memset(tx_ring->desc, 0, tx_ring->size);
2888
2889         tx_ring->next_to_use = 0;
2890         tx_ring->next_to_clean = 0;
2891
2892         if (tx_ring->head)
2893                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2894         if (tx_ring->tail)
2895                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2896 }
2897
2898 /**
2899  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2900  * @adapter: board private structure
2901  **/
2902 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2903 {
2904         int i;
2905
2906         for (i = 0; i < adapter->num_rx_queues; i++)
2907                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2908 }
2909
2910 /**
2911  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2912  * @adapter: board private structure
2913  **/
2914 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2915 {
2916         int i;
2917
2918         for (i = 0; i < adapter->num_tx_queues; i++)
2919                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2920 }
2921
2922 void ixgbe_down(struct ixgbe_adapter *adapter)
2923 {
2924         struct net_device *netdev = adapter->netdev;
2925         struct ixgbe_hw *hw = &adapter->hw;
2926         u32 rxctrl;
2927         u32 txdctl;
2928         int i, j;
2929
2930         /* signal that we are down to the interrupt handler */
2931         set_bit(__IXGBE_DOWN, &adapter->state);
2932
2933         /* disable receives */
2934         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2935         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2936
2937         netif_tx_disable(netdev);
2938
2939         IXGBE_WRITE_FLUSH(hw);
2940         msleep(10);
2941
2942         netif_tx_stop_all_queues(netdev);
2943
2944         ixgbe_irq_disable(adapter);
2945
2946         ixgbe_napi_disable_all(adapter);
2947
2948         del_timer_sync(&adapter->watchdog_timer);
2949         cancel_work_sync(&adapter->watchdog_task);
2950
2951         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2952             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2953                 cancel_work_sync(&adapter->fdir_reinit_task);
2954
2955         /* disable transmits in the hardware now that interrupts are off */
2956         for (i = 0; i < adapter->num_tx_queues; i++) {
2957                 j = adapter->tx_ring[i].reg_idx;
2958                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2959                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2960                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2961         }
2962         /* Disable the Tx DMA engine on 82599 */
2963         if (hw->mac.type == ixgbe_mac_82599EB)
2964                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2965                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2966                                  ~IXGBE_DMATXCTL_TE));
2967
2968         netif_carrier_off(netdev);
2969
2970         if (!pci_channel_offline(adapter->pdev))
2971                 ixgbe_reset(adapter);
2972         ixgbe_clean_all_tx_rings(adapter);
2973         ixgbe_clean_all_rx_rings(adapter);
2974
2975 #ifdef CONFIG_IXGBE_DCA
2976         /* since we reset the hardware DCA settings were cleared */
2977         ixgbe_setup_dca(adapter);
2978 #endif
2979 }
2980
2981 /**
2982  * ixgbe_poll - NAPI Rx polling callback
2983  * @napi: structure for representing this polling device
2984  * @budget: how many packets driver is allowed to clean
2985  *
2986  * This function is used for legacy and MSI, NAPI mode
2987  **/
2988 static int ixgbe_poll(struct napi_struct *napi, int budget)
2989 {
2990         struct ixgbe_q_vector *q_vector =
2991                                 container_of(napi, struct ixgbe_q_vector, napi);
2992         struct ixgbe_adapter *adapter = q_vector->adapter;
2993         int tx_clean_complete, work_done = 0;
2994
2995 #ifdef CONFIG_IXGBE_DCA
2996         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2997                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2998                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2999         }
3000 #endif
3001
3002         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3003         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3004
3005         if (!tx_clean_complete)
3006                 work_done = budget;
3007
3008         /* If budget not fully consumed, exit the polling mode */
3009         if (work_done < budget) {
3010                 napi_complete(napi);
3011                 if (adapter->itr_setting & 1)
3012                         ixgbe_set_itr(adapter);
3013                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3014                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3015         }
3016         return work_done;
3017 }
3018
3019 /**
3020  * ixgbe_tx_timeout - Respond to a Tx Hang
3021  * @netdev: network interface device structure
3022  **/
3023 static void ixgbe_tx_timeout(struct net_device *netdev)
3024 {
3025         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3026
3027         /* Do the reset outside of interrupt context */
3028         schedule_work(&adapter->reset_task);
3029 }
3030
3031 static void ixgbe_reset_task(struct work_struct *work)
3032 {
3033         struct ixgbe_adapter *adapter;
3034         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3035
3036         /* If we're already down or resetting, just bail */
3037         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3038             test_bit(__IXGBE_RESETTING, &adapter->state))
3039                 return;
3040
3041         adapter->tx_timeout_count++;
3042
3043         ixgbe_reinit_locked(adapter);
3044 }
3045
3046 #ifdef CONFIG_IXGBE_DCB
3047 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3048 {
3049         bool ret = false;
3050         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3051
3052         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3053                 return ret;
3054
3055         f->mask = 0x7 << 3;
3056         adapter->num_rx_queues = f->indices;
3057         adapter->num_tx_queues = f->indices;
3058         ret = true;
3059
3060         return ret;
3061 }
3062 #endif
3063
3064 /**
3065  * ixgbe_set_rss_queues: Allocate queues for RSS
3066  * @adapter: board private structure to initialize
3067  *
3068  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3069  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3070  *
3071  **/
3072 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3073 {
3074         bool ret = false;
3075         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3076
3077         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3078                 f->mask = 0xF;
3079                 adapter->num_rx_queues = f->indices;
3080                 adapter->num_tx_queues = f->indices;
3081                 ret = true;
3082         } else {
3083                 ret = false;
3084         }
3085
3086         return ret;
3087 }
3088
3089 /**
3090  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3091  * @adapter: board private structure to initialize
3092  *
3093  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3094  * to the original CPU that initiated the Tx session.  This runs in addition
3095  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3096  * Rx load across CPUs using RSS.
3097  *
3098  **/
3099 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3100 {
3101         bool ret = false;
3102         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3103
3104         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3105         f_fdir->mask = 0;
3106
3107         /* Flow Director must have RSS enabled */
3108         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3109             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3110              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3111                 adapter->num_tx_queues = f_fdir->indices;
3112                 adapter->num_rx_queues = f_fdir->indices;
3113                 ret = true;
3114         } else {
3115                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3116                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3117         }
3118         return ret;
3119 }
3120
3121 #ifdef IXGBE_FCOE
3122 /**
3123  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3124  * @adapter: board private structure to initialize
3125  *
3126  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3127  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3128  * rx queues out of the max number of rx queues, instead, it is used as the
3129  * index of the first rx queue used by FCoE.
3130  *
3131  **/
3132 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3133 {
3134         bool ret = false;
3135         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3136
3137         f->indices = min((int)num_online_cpus(), f->indices);
3138         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3139 #ifdef CONFIG_IXGBE_DCB
3140                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3141                         DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3142                         ixgbe_set_dcb_queues(adapter);
3143                 }
3144 #endif
3145                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3146                         DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3147                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3148                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3149                                 ixgbe_set_fdir_queues(adapter);
3150                         else
3151                                 ixgbe_set_rss_queues(adapter);
3152                 }
3153                 /* adding FCoE rx rings to the end */
3154                 f->mask = adapter->num_rx_queues;
3155                 adapter->num_rx_queues += f->indices;
3156                 if (adapter->num_tx_queues == 0)
3157                         adapter->num_tx_queues = f->indices;
3158
3159                 ret = true;
3160         }
3161
3162         return ret;
3163 }
3164
3165 #endif /* IXGBE_FCOE */
3166 /*
3167  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3168  * @adapter: board private structure to initialize
3169  *
3170  * This is the top level queue allocation routine.  The order here is very