drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 604                                       struct ixgbe_tx_buffer
 605                                       *tx_buffer_info)
 606 {
 607         if (tx_buffer_info->dma) {
 608                 if (tx_buffer_info->mapped_as_page)
 609                         dma_unmap_page(&adapter->pdev->dev,
 610                                        tx_buffer_info->dma,
 611                                        tx_buffer_info->length,
 612                                        DMA_TO_DEVICE);
 613                 else
 614                         dma_unmap_single(&adapter->pdev->dev,
 615                                          tx_buffer_info->dma,
 616                                          tx_buffer_info->length,
 617                                          DMA_TO_DEVICE);
 618                 tx_buffer_info->dma = 0;
 619         }
 620         if (tx_buffer_info->skb) {
 621                 dev_kfree_skb_any(tx_buffer_info->skb);
 622                 tx_buffer_info->skb = NULL;
 623         }
 624         tx_buffer_info->time_stamp = 0;
 625         /* tx_buffer_info must be completely set up in the transmit path */
 626 }
 627
 628 /**
 629  * ixgbe_tx_xon_state - check the tx ring xon state
 630  * @adapter: the ixgbe adapter
 631  * @tx_ring: the corresponding tx_ring
 632  *
 633  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 634  * corresponding TC of this tx_ring when checking TFCS.
 635  *
 636  * Returns : true if in xon state (currently not paused)
 637  */
 638 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 639                                       struct ixgbe_ring *tx_ring)
 640 {
 641         u32 txoff = IXGBE_TFCS_TXOFF;
 642
 643 #ifdef CONFIG_IXGBE_DCB
 644         if (adapter->dcb_cfg.pfc_mode_enable) {
 645                 int tc;
 646                 int reg_idx = tx_ring->reg_idx;
 647                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 648
 649                 switch (adapter->hw.mac.type) {
 650                 case ixgbe_mac_82598EB:
 651                         tc = reg_idx >> 2;
 652                         txoff = IXGBE_TFCS_TXOFF0;
 653                         break;
 654                 case ixgbe_mac_82599EB:
 655                         tc = 0;
 656                         txoff = IXGBE_TFCS_TXOFF;
 657                         if (dcb_i == 8) {
 658                                 /* TC0, TC1 */
 659                                 tc = reg_idx >> 5;
 660                                 if (tc == 2) /* TC2, TC3 */
 661                                         tc += (reg_idx - 64) >> 4;
 662                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 663                                         tc += 1 + ((reg_idx - 96) >> 3);
 664                         } else if (dcb_i == 4) {
 665                                 /* TC0, TC1 */
 666                                 tc = reg_idx >> 6;
 667                                 if (tc == 1) {
 668                                         tc += (reg_idx - 64) >> 5;
 669                                         if (tc == 2) /* TC2, TC3 */
 670                                                 tc += (reg_idx - 96) >> 4;
 671                                 }
 672                         }
 673                         break;
 674                 default:
 675                         tc = 0;
 676                 }
 677                 txoff <<= tc;
 678         }
 679 #endif
 680         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 681 }
 682
 683 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 684                                        struct ixgbe_ring *tx_ring,
 685                                        unsigned int eop)
 686 {
 687         struct ixgbe_hw *hw = &adapter->hw;
 688
 689         /* Detect a transmit hang in hardware, this serializes the
 690          * check with the clearing of time_stamp and movement of eop */
 691         adapter->detect_tx_hung = false;
 692         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 693             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 694             ixgbe_tx_xon_state(adapter, tx_ring)) {
 695                 /* detected Tx unit hang */
 696                 union ixgbe_adv_tx_desc *tx_desc;
 697                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 698                 e_err(drv, "Detected Tx Unit Hang\n"
 699                       "  Tx Queue             <%d>\n"
 700                       "  TDH, TDT             <%x>, <%x>\n"
 701                       "  next_to_use          <%x>\n"
 702                       "  next_to_clean        <%x>\n"
 703                       "tx_buffer_info[next_to_clean]\n"
 704                       "  time_stamp           <%lx>\n"
 705                       "  jiffies              <%lx>\n",
 706                       tx_ring->queue_index,
 707                       IXGBE_READ_REG(hw, tx_ring->head),
 708                       IXGBE_READ_REG(hw, tx_ring->tail),
 709                       tx_ring->next_to_use, eop,
 710                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 711                 return true;
 712         }
 713
 714         return false;
 715 }
 716
 717 #define IXGBE_MAX_TXD_PWR       14
 718 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 719
 720 /* Tx Descriptors needed, worst case */
 721 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 722                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 723 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 724         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 725
 726 static void ixgbe_tx_timeout(struct net_device *netdev);
 727
 728 /**
 729  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 730  * @q_vector: structure containing interrupt and ring information
 731  * @tx_ring: tx ring to clean
 732  **/
 733 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 734                                struct ixgbe_ring *tx_ring)
 735 {
 736         struct ixgbe_adapter *adapter = q_vector->adapter;
 737         struct net_device *netdev = adapter->netdev;
 738         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 739         struct ixgbe_tx_buffer *tx_buffer_info;
 740         unsigned int i, eop, count = 0;
 741         unsigned int total_bytes = 0, total_packets = 0;
 742
 743         i = tx_ring->next_to_clean;
 744         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 745         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 746
 747         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 748                (count < tx_ring->work_limit)) {
 749                 bool cleaned = false;
 750                 rmb(); /* read buffer_info after eop_desc */
 751                 for ( ; !cleaned; count++) {
 752                         struct sk_buff *skb;
 753                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 754                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 755                         cleaned = (i == eop);
 756                         skb = tx_buffer_info->skb;
 757
 758                         if (cleaned && skb) {
 759                                 unsigned int segs, bytecount;
 760                                 unsigned int hlen = skb_headlen(skb);
 761
 762                                 /* gso_segs is currently only valid for tcp */
 763                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 764 #ifdef IXGBE_FCOE
 765                                 /* adjust for FCoE Sequence Offload */
 766                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 767                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 768                                     skb_is_gso(skb)) {
 769                                         hlen = skb_transport_offset(skb) +
 770                                                 sizeof(struct fc_frame_header) +
 771                                                 sizeof(struct fcoe_crc_eof);
 772                                         segs = DIV_ROUND_UP(skb->len - hlen,
 773                                                 skb_shinfo(skb)->gso_size);
 774                                 }
 775 #endif /* IXGBE_FCOE */
 776                                 /* multiply data chunks by size of headers */
 777                                 bytecount = ((segs - 1) * hlen) + skb->len;
 778                                 total_packets += segs;
 779                                 total_bytes += bytecount;
 780                         }
 781
 782                         ixgbe_unmap_and_free_tx_resource(adapter,
 783                                                          tx_buffer_info);
 784
 785                         tx_desc->wb.status = 0;
 786
 787                         i++;
 788                         if (i == tx_ring->count)
 789                                 i = 0;
 790                 }
 791
 792                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 793                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 794         }
 795
 796         tx_ring->next_to_clean = i;
 797
 798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 799         if (unlikely(count && netif_carrier_ok(netdev) &&
 800                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 801                 /* Make sure that anybody stopping the queue after this
 802                  * sees the new next_to_clean.
 803                  */
 804                 smp_mb();
 805                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 806                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 807                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 808                         ++tx_ring->restart_queue;
 809                 }
 810         }
 811
 812         if (adapter->detect_tx_hung) {
 813                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 814                         /* schedule immediate reset if we believe we hung */
 815                         e_info(probe, "tx hang %d detected, resetting "
 816                                "adapter\n", adapter->tx_timeout_count + 1);
 817                         ixgbe_tx_timeout(adapter->netdev);
 818                 }
 819         }
 820
 821         /* re-arm the interrupt */
 822         if (count >= tx_ring->work_limit)
 823                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 824
 825         tx_ring->total_bytes += total_bytes;
 826         tx_ring->total_packets += total_packets;
 827         u64_stats_update_begin(&tx_ring->syncp);
 828         tx_ring->stats.packets += total_packets;
 829         tx_ring->stats.bytes += total_bytes;
 830         u64_stats_update_end(&tx_ring->syncp);
 831         return count < tx_ring->work_limit;
 832 }
 833
 834 #ifdef CONFIG_IXGBE_DCA
 835 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 836                                 struct ixgbe_ring *rx_ring)
 837 {
 838         u32 rxctrl;
 839         int cpu = get_cpu();
 840         int q = rx_ring->reg_idx;
 841
 842         if (rx_ring->cpu != cpu) {
 843                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 844                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 845                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 846                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 847                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 848                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 849                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 850                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 851                 }
 852                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 853                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 854                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 855                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 856                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 857                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 858                 rx_ring->cpu = cpu;
 859         }
 860         put_cpu();
 861 }
 862
 863 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 864                                 struct ixgbe_ring *tx_ring)
 865 {
 866         u32 txctrl;
 867         int cpu = get_cpu();
 868         int q = tx_ring->reg_idx;
 869         struct ixgbe_hw *hw = &adapter->hw;
 870
 871         if (tx_ring->cpu != cpu) {
 872                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 873                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 874                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 875                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 876                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 877                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 878                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 879                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 880                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 881                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 882                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 883                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 884                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 885                 }
 886                 tx_ring->cpu = cpu;
 887         }
 888         put_cpu();
 889 }
 890
 891 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 892 {
 893         int i;
 894
 895         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 896                 return;
 897
 898         /* always use CB2 mode, difference is masked in the CB driver */
 899         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 900
 901         for (i = 0; i < adapter->num_tx_queues; i++) {
 902                 adapter->tx_ring[i]->cpu = -1;
 903                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 904         }
 905         for (i = 0; i < adapter->num_rx_queues; i++) {
 906                 adapter->rx_ring[i]->cpu = -1;
 907                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 908         }
 909 }
 910
 911 static int __ixgbe_notify_dca(struct device *dev, void *data)
 912 {
 913         struct net_device *netdev = dev_get_drvdata(dev);
 914         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 915         unsigned long event = *(unsigned long *)data;
 916
 917         switch (event) {
 918         case DCA_PROVIDER_ADD:
 919                 /* if we're already enabled, don't do it again */
 920                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 921                         break;
 922                 if (dca_add_requester(dev) == 0) {
 923                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 924                         ixgbe_setup_dca(adapter);
 925                         break;
 926                 }
 927                 /* Fall Through since DCA is disabled. */
 928         case DCA_PROVIDER_REMOVE:
 929                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 930                         dca_remove_requester(dev);
 931                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 932                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 933                 }
 934                 break;
 935         }
 936
 937         return 0;
 938 }
 939
 940 #endif /* CONFIG_IXGBE_DCA */
 941 /**
 942  * ixgbe_receive_skb - Send a completed packet up the stack
 943  * @adapter: board private structure
 944  * @skb: packet to send up
 945  * @status: hardware indication of status of receive
 946  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 947  * @rx_desc: rx descriptor
 948  **/
 949 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 950                               struct sk_buff *skb, u8 status,
 951                               struct ixgbe_ring *ring,
 952                               union ixgbe_adv_rx_desc *rx_desc)
 953 {
 954         struct ixgbe_adapter *adapter = q_vector->adapter;
 955         struct napi_struct *napi = &q_vector->napi;
 956         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 957         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 958
 959         if (is_vlan && (tag & VLAN_VID_MASK))
 960                 __vlan_hwaccel_put_tag(skb, tag);
 961
 962         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 963                 napi_gro_receive(napi, skb);
 964         else
 965                 netif_rx(skb);
 966 }
 967
 968 /**
 969  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 970  * @adapter: address of board private structure
 971  * @status_err: hardware indication of status of receive
 972  * @skb: skb currently being received and modified
 973  **/
 974 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 975                                      union ixgbe_adv_rx_desc *rx_desc,
 976                                      struct sk_buff *skb)
 977 {
 978         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 979
 980         skb_checksum_none_assert(skb);
 981
 982         /* Rx csum disabled */
 983         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 984                 return;
 985
 986         /* if IP and error */
 987         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 988             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 989                 adapter->hw_csum_rx_error++;
 990                 return;
 991         }
 992
 993         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 994                 return;
 995
 996         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 997                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 998
 999                 /*
1000                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1001                  * checksum errors.
1002                  */
1003                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1004                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1005                         return;
1006
1007                 adapter->hw_csum_rx_error++;
1008                 return;
1009         }
1010
1011         /* It must be a TCP or UDP packet with a valid checksum */
1012         skb->ip_summed = CHECKSUM_UNNECESSARY;
1013 }
1014
1015 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1016                                          struct ixgbe_ring *rx_ring, u32 val)
1017 {
1018         /*
1019          * Force memory writes to complete before letting h/w
1020          * know there are new descriptors to fetch.  (Only
1021          * applicable for weak-ordered memory model archs,
1022          * such as IA-64).
1023          */
1024         wmb();
1025         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1026 }
1027
1028 /**
1029  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1030  * @adapter: address of board private structure
1031  **/
1032 void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1033                             struct ixgbe_ring *rx_ring,
1034                             int cleaned_count)
1035 {
1036         struct net_device *netdev = adapter->netdev;
1037         struct pci_dev *pdev = adapter->pdev;
1038         union ixgbe_adv_rx_desc *rx_desc;
1039         struct ixgbe_rx_buffer *bi;
1040         unsigned int i;
1041         unsigned int bufsz = rx_ring->rx_buf_len;
1042
1043         i = rx_ring->next_to_use;
1044         bi = &rx_ring->rx_buffer_info[i];
1045
1046         while (cleaned_count--) {
1047                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1048
1049                 if (!bi->page_dma &&
1050                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1051                         if (!bi->page) {
1052                                 bi->page = netdev_alloc_page(netdev);
1053                                 if (!bi->page) {
1054                                         adapter->alloc_rx_page_failed++;
1055                                         goto no_buffers;
1056                                 }
1057                                 bi->page_offset = 0;
1058                         } else {
1059                                 /* use a half page if we're re-using */
1060                                 bi->page_offset ^= (PAGE_SIZE / 2);
1061                         }
1062
1063                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1064                                                     bi->page_offset,
1065                                                     (PAGE_SIZE / 2),
1066                                                     DMA_FROM_DEVICE);
1067                 }
1068
1069                 if (!bi->skb) {
1070                         struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1071                                                                         bufsz);
1072                         bi->skb = skb;
1073
1074                         if (!skb) {
1075                                 adapter->alloc_rx_buff_failed++;
1076                                 goto no_buffers;
1077                         }
1078                         /* initialize queue mapping */
1079                         skb_record_rx_queue(skb, rx_ring->queue_index);
1080                 }
1081
1082                 if (!bi->dma) {
1083                         bi->dma = dma_map_single(&pdev->dev,
1084                                                  bi->skb->data,
1085                                                  rx_ring->rx_buf_len,
1086                                                  DMA_FROM_DEVICE);
1087                 }
1088                 /* Refresh the desc even if buffer_addrs didn't change because
1089                  * each write-back erases this info. */
1090                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1091                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1092                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1093                 } else {
1094                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1095                         rx_desc->read.hdr_addr = 0;
1096                 }
1097
1098                 i++;
1099                 if (i == rx_ring->count)
1100                         i = 0;
1101                 bi = &rx_ring->rx_buffer_info[i];
1102         }
1103
1104 no_buffers:
1105         if (rx_ring->next_to_use != i) {
1106                 rx_ring->next_to_use = i;
1107                 if (i-- == 0)
1108                         i = (rx_ring->count - 1);
1109
1110                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1111         }
1112 }
1113
1114 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1115 {
1116         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1117 }
1118
1119 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1120 {
1121         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122 }
1123
1124 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1125 {
1126         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1127                 IXGBE_RXDADV_RSCCNT_MASK) >>
1128                 IXGBE_RXDADV_RSCCNT_SHIFT;
1129 }
1130
1131 /**
1132  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1133  * @skb: pointer to the last skb in the rsc queue
1134  * @count: pointer to number of packets coalesced in this context
1135  *
1136  * This function changes a queue full of hw rsc buffers into a completed
1137  * packet.  It uses the ->prev pointers to find the first packet and then
1138  * turns it into the frag list owner.
1139  **/
1140 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1141                                                         u64 *count)
1142 {
1143         unsigned int frag_list_size = 0;
1144
1145         while (skb->prev) {
1146                 struct sk_buff *prev = skb->prev;
1147                 frag_list_size += skb->len;
1148                 skb->prev = NULL;
1149                 skb = prev;
1150                 *count += 1;
1151         }
1152
1153         skb_shinfo(skb)->frag_list = skb->next;
1154         skb->next = NULL;
1155         skb->len += frag_list_size;
1156         skb->data_len += frag_list_size;
1157         skb->truesize += frag_list_size;
1158         return skb;
1159 }
1160
1161 struct ixgbe_rsc_cb {
1162         dma_addr_t dma;
1163         bool delay_unmap;
1164 };
1165
1166 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1167
1168 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1169                                struct ixgbe_ring *rx_ring,
1170                                int *work_done, int work_to_do)
1171 {
1172         struct ixgbe_adapter *adapter = q_vector->adapter;
1173         struct pci_dev *pdev = adapter->pdev;
1174         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1175         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1176         struct sk_buff *skb;
1177         unsigned int i, rsc_count = 0;
1178         u32 len, staterr;
1179         u16 hdr_info;
1180         bool cleaned = false;
1181         int cleaned_count = 0;
1182         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1183 #ifdef IXGBE_FCOE
1184         int ddp_bytes = 0;
1185 #endif /* IXGBE_FCOE */
1186
1187         i = rx_ring->next_to_clean;
1188         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1189         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1190         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1191
1192         while (staterr & IXGBE_RXD_STAT_DD) {
1193                 u32 upper_len = 0;
1194                 if (*work_done >= work_to_do)
1195                         break;
1196                 (*work_done)++;
1197
1198                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1199                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1200                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1201                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1202                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1203                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1204                         if ((len > IXGBE_RX_HDR_SIZE) ||
1205                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1206                                 len = IXGBE_RX_HDR_SIZE;
1207                 } else {
1208                         len = le16_to_cpu(rx_desc->wb.upper.length);
1209                 }
1210
1211                 cleaned = true;
1212                 skb = rx_buffer_info->skb;
1213                 prefetch(skb->data);
1214                 rx_buffer_info->skb = NULL;
1215
1216                 if (rx_buffer_info->dma) {
1217                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1218                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1219                                  (!(skb->prev))) {
1220                                 /*
1221                                  * When HWRSC is enabled, delay unmapping
1222                                  * of the first packet. It carries the
1223                                  * header information, HW may still
1224                                  * access the header after the writeback.
1225                                  * Only unmap it when EOP is reached
1226                                  */
1227                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1228                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1229                         } else {
1230                                 dma_unmap_single(&pdev->dev,
1231                                                  rx_buffer_info->dma,
1232                                                  rx_ring->rx_buf_len,
1233                                                  DMA_FROM_DEVICE);
1234                         }
1235                         rx_buffer_info->dma = 0;
1236                         skb_put(skb, len);
1237                 }
1238
1239                 if (upper_len) {
1240                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1241                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1242                         rx_buffer_info->page_dma = 0;
1243                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1244                                            rx_buffer_info->page,
1245                                            rx_buffer_info->page_offset,
1246                                            upper_len);
1247
1248                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1249                             (page_count(rx_buffer_info->page) != 1))
1250                                 rx_buffer_info->page = NULL;
1251                         else
1252                                 get_page(rx_buffer_info->page);
1253
1254                         skb->len += upper_len;
1255                         skb->data_len += upper_len;
1256                         skb->truesize += upper_len;
1257                 }
1258
1259                 i++;
1260                 if (i == rx_ring->count)
1261                         i = 0;
1262
1263                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1264                 prefetch(next_rxd);
1265                 cleaned_count++;
1266
1267                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1268                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1269
1270                 if (rsc_count) {
1271                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1272                                      IXGBE_RXDADV_NEXTP_SHIFT;
1273                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1274                 } else {
1275                         next_buffer = &rx_ring->rx_buffer_info[i];
1276                 }
1277
1278                 if (staterr & IXGBE_RXD_STAT_EOP) {
1279                         if (skb->prev)
1280                                 skb = ixgbe_transform_rsc_queue(skb,
1281                                                                 &(rx_ring->rsc_count));
1282                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1283                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1284                                         dma_unmap_single(&pdev->dev,
1285                                                          IXGBE_RSC_CB(skb)->dma,
1286                                                          rx_ring->rx_buf_len,
1287                                                          DMA_FROM_DEVICE);
1288                                         IXGBE_RSC_CB(skb)->dma = 0;
1289                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1290                                 }
1291                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1292                                         rx_ring->rsc_count +=
1293                                                 skb_shinfo(skb)->nr_frags;
1294                                 else
1295                                         rx_ring->rsc_count++;
1296                                 rx_ring->rsc_flush++;
1297                         }
1298                         u64_stats_update_begin(&rx_ring->syncp);
1299                         rx_ring->stats.packets++;
1300                         rx_ring->stats.bytes += skb->len;
1301                         u64_stats_update_end(&rx_ring->syncp);
1302                 } else {
1303                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1304                                 rx_buffer_info->skb = next_buffer->skb;
1305                                 rx_buffer_info->dma = next_buffer->dma;
1306                                 next_buffer->skb = skb;
1307                                 next_buffer->dma = 0;
1308                         } else {
1309                                 skb->next = next_buffer->skb;
1310                                 skb->next->prev = skb;
1311                         }
1312                         rx_ring->non_eop_descs++;
1313                         goto next_desc;
1314                 }
1315
1316                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1317                         dev_kfree_skb_irq(skb);
1318                         goto next_desc;
1319                 }
1320
1321                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1322
1323                 /* probably a little skewed due to removing CRC */
1324                 total_rx_bytes += skb->len;
1325                 total_rx_packets++;
1326
1327                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1328 #ifdef IXGBE_FCOE
1329                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1330                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1331                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1332                         if (!ddp_bytes)
1333                                 goto next_desc;
1334                 }
1335 #endif /* IXGBE_FCOE */
1336                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1337
1338 next_desc:
1339                 rx_desc->wb.upper.status_error = 0;
1340
1341                 /* return some buffers to hardware, one at a time is too slow */
1342                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1343                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1344                         cleaned_count = 0;
1345                 }
1346
1347                 /* use prefetched values */
1348                 rx_desc = next_rxd;
1349                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1350
1351                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1352         }
1353
1354         rx_ring->next_to_clean = i;
1355         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1356
1357         if (cleaned_count)
1358                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1359
1360 #ifdef IXGBE_FCOE
1361         /* include DDPed FCoE data */
1362         if (ddp_bytes > 0) {
1363                 unsigned int mss;
1364
1365                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1366                         sizeof(struct fc_frame_header) -
1367                         sizeof(struct fcoe_crc_eof);
1368                 if (mss > 512)
1369                         mss &= ~511;
1370                 total_rx_bytes += ddp_bytes;
1371                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1372         }
1373 #endif /* IXGBE_FCOE */
1374
1375         rx_ring->total_packets += total_rx_packets;
1376         rx_ring->total_bytes += total_rx_bytes;
1377
1378         return cleaned;
1379 }
1380
1381 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1382 /**
1383  * ixgbe_configure_msix - Configure MSI-X hardware
1384  * @adapter: board private structure
1385  *
1386  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1387  * interrupts.
1388  **/
1389 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1390 {
1391         struct ixgbe_q_vector *q_vector;
1392         int i, j, q_vectors, v_idx, r_idx;
1393         u32 mask;
1394
1395         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1396
1397         /*
1398          * Populate the IVAR table and set the ITR values to the
1399          * corresponding register.
1400          */
1401         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1402                 q_vector = adapter->q_vector[v_idx];
1403                 /* XXX for_each_set_bit(...) */
1404                 r_idx = find_first_bit(q_vector->rxr_idx,
1405                                        adapter->num_rx_queues);
1406
1407                 for (i = 0; i < q_vector->rxr_count; i++) {
1408                         j = adapter->rx_ring[r_idx]->reg_idx;
1409                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1410                         r_idx = find_next_bit(q_vector->rxr_idx,
1411                                               adapter->num_rx_queues,
1412                                               r_idx + 1);
1413                 }
1414                 r_idx = find_first_bit(q_vector->txr_idx,
1415                                        adapter->num_tx_queues);
1416
1417                 for (i = 0; i < q_vector->txr_count; i++) {
1418                         j = adapter->tx_ring[r_idx]->reg_idx;
1419                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1420                         r_idx = find_next_bit(q_vector->txr_idx,
1421                                               adapter->num_tx_queues,
1422                                               r_idx + 1);
1423                 }
1424
1425                 if (q_vector->txr_count && !q_vector->rxr_count)
1426                         /* tx only */
1427                         q_vector->eitr = adapter->tx_eitr_param;
1428                 else if (q_vector->rxr_count)
1429                         /* rx or mixed */
1430                         q_vector->eitr = adapter->rx_eitr_param;
1431
1432                 ixgbe_write_eitr(q_vector);
1433                 /* If Flow Director is enabled, set interrupt affinity */
1434                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1435                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1436                         /*
1437                          * Allocate the affinity_hint cpumask, assign the mask
1438                          * for this vector, and set our affinity_hint for
1439                          * this irq.
1440                          */
1441                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1442                                                GFP_KERNEL))
1443                                 return;
1444                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1445                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1446                                               q_vector->affinity_mask);
1447                 }
1448         }
1449
1450         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1451                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1452                                v_idx);
1453         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1454                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1455         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1456
1457         /* set up to autoclear timer, and the vectors */
1458         mask = IXGBE_EIMS_ENABLE_MASK;
1459         if (adapter->num_vfs)
1460                 mask &= ~(IXGBE_EIMS_OTHER |
1461                           IXGBE_EIMS_MAILBOX |
1462                           IXGBE_EIMS_LSC);
1463         else
1464                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1465         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1466 }
1467
1468 enum latency_range {
1469         lowest_latency = 0,
1470         low_latency = 1,
1471         bulk_latency = 2,
1472         latency_invalid = 255
1473 };
1474
1475 /**
1476  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1477  * @adapter: pointer to adapter
1478  * @eitr: eitr setting (ints per sec) to give last timeslice
1479  * @itr_setting: current throttle rate in ints/second
1480  * @packets: the number of packets during this measurement interval
1481  * @bytes: the number of bytes during this measurement interval
1482  *
1483  *      Stores a new ITR value based on packets and byte
1484  *      counts during the last interrupt.  The advantage of per interrupt
1485  *      computation is faster updates and more accurate ITR for the current
1486  *      traffic pattern.  Constants in this function were computed
1487  *      based on theoretical maximum wire speed and thresholds were set based
1488  *      on testing data as well as attempting to minimize response time
1489  *      while increasing bulk throughput.
1490  *      this functionality is controlled by the InterruptThrottleRate module
1491  *      parameter (see ixgbe_param.c)
1492  **/
1493 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1494                            u32 eitr, u8 itr_setting,
1495                            int packets, int bytes)
1496 {
1497         unsigned int retval = itr_setting;
1498         u32 timepassed_us;
1499         u64 bytes_perint;
1500
1501         if (packets == 0)
1502                 goto update_itr_done;
1503
1504
1505         /* simple throttlerate management
1506          *    0-20MB/s lowest (100000 ints/s)
1507          *   20-100MB/s low   (20000 ints/s)
1508          *  100-1249MB/s bulk (8000 ints/s)
1509          */
1510         /* what was last interrupt timeslice? */
1511         timepassed_us = 1000000/eitr;
1512         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1513
1514         switch (itr_setting) {
1515         case lowest_latency:
1516                 if (bytes_perint > adapter->eitr_low)
1517                         retval = low_latency;
1518                 break;
1519         case low_latency:
1520                 if (bytes_perint > adapter->eitr_high)
1521                         retval = bulk_latency;
1522                 else if (bytes_perint <= adapter->eitr_low)
1523                         retval = lowest_latency;
1524                 break;
1525         case bulk_latency:
1526                 if (bytes_perint <= adapter->eitr_high)
1527                         retval = low_latency;
1528                 break;
1529         }
1530
1531 update_itr_done:
1532         return retval;
1533 }
1534
1535 /**
1536  * ixgbe_write_eitr - write EITR register in hardware specific way
1537  * @q_vector: structure containing interrupt and ring information
1538  *
1539  * This function is made to be called by ethtool and by the driver
1540  * when it needs to update EITR registers at runtime.  Hardware
1541  * specific quirks/differences are taken care of here.
1542  */
1543 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1544 {
1545         struct ixgbe_adapter *adapter = q_vector->adapter;
1546         struct ixgbe_hw *hw = &adapter->hw;
1547         int v_idx = q_vector->v_idx;
1548         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1549
1550         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1551                 /* must write high and low 16 bits to reset counter */
1552                 itr_reg |= (itr_reg << 16);
1553         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1554                 /*
1555                  * 82599 can support a value of zero, so allow it for
1556                  * max interrupt rate, but there is an errata where it can
1557                  * not be zero with RSC
1558                  */
1559                 if (itr_reg == 8 &&
1560                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1561                         itr_reg = 0;
1562
1563                 /*
1564                  * set the WDIS bit to not clear the timer bits and cause an
1565                  * immediate assertion of the interrupt
1566                  */
1567                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1568         }
1569         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1570 }
1571
1572 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1573 {
1574         struct ixgbe_adapter *adapter = q_vector->adapter;
1575         u32 new_itr;
1576         u8 current_itr, ret_itr;
1577         int i, r_idx;
1578         struct ixgbe_ring *rx_ring, *tx_ring;
1579
1580         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1581         for (i = 0; i < q_vector->txr_count; i++) {
1582                 tx_ring = adapter->tx_ring[r_idx];
1583                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1584                                            q_vector->tx_itr,
1585                                            tx_ring->total_packets,
1586                                            tx_ring->total_bytes);
1587                 /* if the result for this queue would decrease interrupt
1588                  * rate for this vector then use that result */
1589                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1590                                     q_vector->tx_itr - 1 : ret_itr);
1591                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1592                                       r_idx + 1);
1593         }
1594
1595         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1596         for (i = 0; i < q_vector->rxr_count; i++) {
1597                 rx_ring = adapter->rx_ring[r_idx];
1598                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1599                                            q_vector->rx_itr,
1600                                            rx_ring->total_packets,
1601                                            rx_ring->total_bytes);
1602                 /* if the result for this queue would decrease interrupt
1603                  * rate for this vector then use that result */
1604                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1605                                     q_vector->rx_itr - 1 : ret_itr);
1606                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1607                                       r_idx + 1);
1608         }
1609
1610         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1611
1612         switch (current_itr) {
1613         /* counts and packets in update_itr are dependent on these numbers */
1614         case lowest_latency:
1615                 new_itr = 100000;
1616                 break;
1617         case low_latency:
1618                 new_itr = 20000; /* aka hwitr = ~200 */
1619                 break;
1620         case bulk_latency:
1621         default:
1622                 new_itr = 8000;
1623                 break;
1624         }
1625
1626         if (new_itr != q_vector->eitr) {
1627                 /* do an exponential smoothing */
1628                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1629
1630                 /* save the algorithm value here, not the smoothed one */
1631                 q_vector->eitr = new_itr;
1632
1633                 ixgbe_write_eitr(q_vector);
1634         }
1635 }
1636
1637 /**
1638  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1639  * @work: pointer to work_struct containing our data
1640  **/
1641 static void ixgbe_check_overtemp_task(struct work_struct *work)
1642 {
1643         struct ixgbe_adapter *adapter = container_of(work,
1644                                                      struct ixgbe_adapter,
1645                                                      check_overtemp_task);
1646         struct ixgbe_hw *hw = &adapter->hw;
1647         u32 eicr = adapter->interrupt_event;
1648
1649         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1650                 return;
1651
1652         switch (hw->device_id) {
1653         case IXGBE_DEV_ID_82599_T3_LOM: {
1654                 u32 autoneg;
1655                 bool link_up = false;
1656
1657                 if (hw->mac.ops.check_link)
1658                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1659
1660                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1661                     (eicr & IXGBE_EICR_LSC))
1662                         /* Check if this is due to overtemp */
1663                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1664                                 break;
1665                 return;
1666         }
1667         default:
1668                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1669                         return;
1670                 break;
1671         }
1672         e_crit(drv,
1673                "Network adapter has been stopped because it has over heated. "
1674                "Restart the computer. If the problem persists, "
1675                "power off the system and replace the adapter\n");
1676         /* write to clear the interrupt */
1677         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1678 }
1679
1680 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1681 {
1682         struct ixgbe_hw *hw = &adapter->hw;
1683
1684         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1685             (eicr & IXGBE_EICR_GPI_SDP1)) {
1686                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1687                 /* write to clear the interrupt */
1688                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1689         }
1690 }
1691
1692 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1693 {
1694         struct ixgbe_hw *hw = &adapter->hw;
1695
1696         if (eicr & IXGBE_EICR_GPI_SDP1) {
1697                 /* Clear the interrupt */
1698                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1699                 schedule_work(&adapter->multispeed_fiber_task);
1700         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1701                 /* Clear the interrupt */
1702                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1703                 schedule_work(&adapter->sfp_config_module_task);
1704         } else {
1705                 /* Interrupt isn't for us... */
1706                 return;
1707         }
1708 }
1709
1710 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1711 {
1712         struct ixgbe_hw *hw = &adapter->hw;
1713
1714         adapter->lsc_int++;
1715         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1716         adapter->link_check_timeout = jiffies;
1717         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1718                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1719                 IXGBE_WRITE_FLUSH(hw);
1720                 schedule_work(&adapter->watchdog_task);
1721         }
1722 }
1723
1724 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1725 {
1726         struct net_device *netdev = data;
1727         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1728         struct ixgbe_hw *hw = &adapter->hw;
1729         u32 eicr;
1730
1731         /*
1732          * Workaround for Silicon errata.  Use clear-by-write instead
1733          * of clear-by-read.  Reading with EICS will return the
1734          * interrupt causes without clearing, which later be done
1735          * with the write to EICR.
1736          */
1737         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1738         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1739
1740         if (eicr & IXGBE_EICR_LSC)
1741                 ixgbe_check_lsc(adapter);
1742
1743         if (eicr & IXGBE_EICR_MAILBOX)
1744                 ixgbe_msg_task(adapter);
1745
1746         if (hw->mac.type == ixgbe_mac_82598EB)
1747                 ixgbe_check_fan_failure(adapter, eicr);
1748
1749         if (hw->mac.type == ixgbe_mac_82599EB) {
1750                 ixgbe_check_sfp_event(adapter, eicr);
1751                 adapter->interrupt_event = eicr;
1752                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1753                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1754                         schedule_work(&adapter->check_overtemp_task);
1755
1756                 /* Handle Flow Director Full threshold interrupt */
1757                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1758                         int i;
1759                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1760                         /* Disable transmits before FDIR Re-initialization */
1761                         netif_tx_stop_all_queues(netdev);
1762                         for (i = 0; i < adapter->num_tx_queues; i++) {
1763                                 struct ixgbe_ring *tx_ring =
1764                                                             adapter->tx_ring[i];
1765                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1766                                                        &tx_ring->reinit_state))
1767                                         schedule_work(&adapter->fdir_reinit_task);
1768                         }
1769                 }
1770         }
1771         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1772                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1773
1774         return IRQ_HANDLED;
1775 }
1776
1777 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1778                                            u64 qmask)
1779 {
1780         u32 mask;
1781
1782         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1783                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1784                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1785         } else {
1786                 mask = (qmask & 0xFFFFFFFF);
1787                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1788                 mask = (qmask >> 32);
1789                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1790         }
1791         /* skip the flush */
1792 }
1793
1794 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1795                                             u64 qmask)
1796 {
1797         u32 mask;
1798
1799         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1800                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1801                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1802         } else {
1803                 mask = (qmask & 0xFFFFFFFF);
1804                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1805                 mask = (qmask >> 32);
1806                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1807         }
1808         /* skip the flush */
1809 }
1810
1811 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1812 {
1813         struct ixgbe_q_vector *q_vector = data;
1814         struct ixgbe_adapter  *adapter = q_vector->adapter;
1815         struct ixgbe_ring     *tx_ring;
1816         int i, r_idx;
1817
1818         if (!q_vector->txr_count)
1819                 return IRQ_HANDLED;
1820
1821         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1822         for (i = 0; i < q_vector->txr_count; i++) {
1823                 tx_ring = adapter->tx_ring[r_idx];
1824                 tx_ring->total_bytes = 0;
1825                 tx_ring->total_packets = 0;
1826                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1827                                       r_idx + 1);
1828         }
1829
1830         /* EIAM disabled interrupts (on this vector) for us */
1831         napi_schedule(&q_vector->napi);
1832
1833         return IRQ_HANDLED;
1834 }
1835
1836 /**
1837  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1838  * @irq: unused
1839  * @data: pointer to our q_vector struct for this interrupt vector
1840  **/
1841 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1842 {
1843         struct ixgbe_q_vector *q_vector = data;
1844         struct ixgbe_adapter  *adapter = q_vector->adapter;
1845         struct ixgbe_ring  *rx_ring;
1846         int r_idx;
1847         int i;
1848
1849         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1850         for (i = 0;  i < q_vector->rxr_count; i++) {
1851                 rx_ring = adapter->rx_ring[r_idx];
1852                 rx_ring->total_bytes = 0;
1853                 rx_ring->total_packets = 0;
1854                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1855                                       r_idx + 1);
1856         }
1857
1858         if (!q_vector->rxr_count)
1859                 return IRQ_HANDLED;
1860
1861         /* disable interrupts on this vector only */
1862         /* EIAM disabled interrupts (on this vector) for us */
1863         napi_schedule(&q_vector->napi);
1864
1865         return IRQ_HANDLED;
1866 }
1867
1868 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1869 {
1870         struct ixgbe_q_vector *q_vector = data;
1871         struct ixgbe_adapter  *adapter = q_vector->adapter;
1872         struct ixgbe_ring  *ring;
1873         int r_idx;
1874         int i;
1875
1876         if (!q_vector->txr_count && !q_vector->rxr_count)
1877                 return IRQ_HANDLED;
1878
1879         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1880         for (i = 0; i < q_vector->txr_count; i++) {
1881                 ring = adapter->tx_ring[r_idx];
1882                 ring->total_bytes = 0;
1883                 ring->total_packets = 0;
1884                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1885                                       r_idx + 1);
1886         }
1887
1888         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1889         for (i = 0; i < q_vector->rxr_count; i++) {
1890                 ring = adapter->rx_ring[r_idx];
1891                 ring->total_bytes = 0;
1892                 ring->total_packets = 0;
1893                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1894                                       r_idx + 1);
1895         }
1896
1897         /* EIAM disabled interrupts (on this vector) for us */
1898         napi_schedule(&q_vector->napi);
1899
1900         return IRQ_HANDLED;
1901 }
1902
1903 /**
1904  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1905  * @napi: napi struct with our devices info in it
1906  * @budget: amount of work driver is allowed to do this pass, in packets
1907  *
1908  * This function is optimized for cleaning one queue only on a single
1909  * q_vector!!!
1910  **/
1911 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1912 {
1913         struct ixgbe_q_vector *q_vector =
1914                                container_of(napi, struct ixgbe_q_vector, napi);
1915         struct ixgbe_adapter *adapter = q_vector->adapter;
1916         struct ixgbe_ring *rx_ring = NULL;
1917         int work_done = 0;
1918         long r_idx;
1919
1920         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1921         rx_ring = adapter->rx_ring[r_idx];
1922 #ifdef CONFIG_IXGBE_DCA
1923         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1924                 ixgbe_update_rx_dca(adapter, rx_ring);
1925 #endif
1926
1927         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1928
1929         /* If all Rx work done, exit the polling mode */
1930         if (work_done < budget) {
1931                 napi_complete(napi);
1932                 if (adapter->rx_itr_setting & 1)
1933                         ixgbe_set_itr_msix(q_vector);
1934                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1935                         ixgbe_irq_enable_queues(adapter,
1936                                                 ((u64)1 << q_vector->v_idx));
1937         }
1938
1939         return work_done;
1940 }
1941
1942 /**
1943  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1944  * @napi: napi struct with our devices info in it
1945  * @budget: amount of work driver is allowed to do this pass, in packets
1946  *
1947  * This function will clean more than one rx queue associated with a
1948  * q_vector.
1949  **/
1950 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1951 {
1952         struct ixgbe_q_vector *q_vector =
1953                                container_of(napi, struct ixgbe_q_vector, napi);
1954         struct ixgbe_adapter *adapter = q_vector->adapter;
1955         struct ixgbe_ring *ring = NULL;
1956         int work_done = 0, i;
1957         long r_idx;
1958         bool tx_clean_complete = true;
1959
1960         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1961         for (i = 0; i < q_vector->txr_count; i++) {
1962                 ring = adapter->tx_ring[r_idx];
1963 #ifdef CONFIG_IXGBE_DCA
1964                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1965                         ixgbe_update_tx_dca(adapter, ring);
1966 #endif
1967                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1968                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1969                                       r_idx + 1);
1970         }
1971
1972         /* attempt to distribute budget to each queue fairly, but don't allow
1973          * the budget to go below 1 because we'll exit polling */
1974         budget /= (q_vector->rxr_count ?: 1);
1975         budget = max(budget, 1);
1976         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1977         for (i = 0; i < q_vector->rxr_count; i++) {
1978                 ring = adapter->rx_ring[r_idx];
1979 #ifdef CONFIG_IXGBE_DCA
1980                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1981                         ixgbe_update_rx_dca(adapter, ring);
1982 #endif
1983                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1984                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1985                                       r_idx + 1);
1986         }
1987
1988         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1989         ring = adapter->rx_ring[r_idx];
1990         /* If all Rx work done, exit the polling mode */
1991         if (work_done < budget) {
1992                 napi_complete(napi);
1993                 if (adapter->rx_itr_setting & 1)
1994                         ixgbe_set_itr_msix(q_vector);
1995                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1996                         ixgbe_irq_enable_queues(adapter,
1997                                                 ((u64)1 << q_vector->v_idx));
1998                 return 0;
1999         }
2000
2001         return work_done;
2002 }
2003
2004 /**
2005  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2006  * @napi: napi struct with our devices info in it
2007  * @budget: amount of work driver is allowed to do this pass, in packets
2008  *
2009  * This function is optimized for cleaning one queue only on a single
2010  * q_vector!!!
2011  **/
2012 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2013 {
2014         struct ixgbe_q_vector *q_vector =
2015                                container_of(napi, struct ixgbe_q_vector, napi);
2016         struct ixgbe_adapter *adapter = q_vector->adapter;
2017         struct ixgbe_ring *tx_ring = NULL;
2018         int work_done = 0;
2019         long r_idx;
2020
2021         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2022         tx_ring = adapter->tx_ring[r_idx];
2023 #ifdef CONFIG_IXGBE_DCA
2024         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2025                 ixgbe_update_tx_dca(adapter, tx_ring);
2026 #endif
2027
2028         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2029                 work_done = budget;
2030
2031         /* If all Tx work done, exit the polling mode */
2032         if (work_done < budget) {
2033                 napi_complete(napi);
2034                 if (adapter->tx_itr_setting & 1)
2035                         ixgbe_set_itr_msix(q_vector);
2036                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2037                         ixgbe_irq_enable_queues(adapter,
2038                                                 ((u64)1 << q_vector->v_idx));
2039         }
2040
2041         return work_done;
2042 }
2043
2044 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2045                                      int r_idx)
2046 {
2047         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2048
2049         set_bit(r_idx, q_vector->rxr_idx);
2050         q_vector->rxr_count++;
2051 }
2052
2053 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2054                                      int t_idx)
2055 {
2056         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2057
2058         set_bit(t_idx, q_vector->txr_idx);
2059         q_vector->txr_count++;
2060 }
2061
2062 /**
2063  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2064  * @adapter: board private structure to initialize
2065  * @vectors: allotted vector count for descriptor rings
2066  *
2067  * This function maps descriptor rings to the queue-specific vectors
2068  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2069  * one vector per ring/queue, but on a constrained vector budget, we
2070  * group the rings as "efficiently" as possible.  You would add new
2071  * mapping configurations in here.
2072  **/
2073 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2074                                       int vectors)
2075 {
2076         int v_start = 0;
2077         int rxr_idx = 0, txr_idx = 0;
2078         int rxr_remaining = adapter->num_rx_queues;
2079         int txr_remaining = adapter->num_tx_queues;
2080         int i, j;
2081         int rqpv, tqpv;
2082         int err = 0;
2083
2084         /* No mapping required if MSI-X is disabled. */
2085         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2086                 goto out;
2087
2088         /*
2089          * The ideal configuration...
2090          * We have enough vectors to map one per queue.
2091          */
2092         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2093                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2094                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2095
2096                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2097                         map_vector_to_txq(adapter, v_start, txr_idx);
2098
2099                 goto out;
2100         }
2101
2102         /*
2103          * If we don't have enough vectors for a 1-to-1
2104          * mapping, we'll have to group them so there are
2105          * multiple queues per vector.
2106          */
2107         /* Re-adjusting *qpv takes care of the remainder. */
2108         for (i = v_start; i < vectors; i++) {
2109                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2110                 for (j = 0; j < rqpv; j++) {
2111                         map_vector_to_rxq(adapter, i, rxr_idx);
2112                         rxr_idx++;
2113                         rxr_remaining--;
2114                 }
2115         }
2116         for (i = v_start; i < vectors; i++) {
2117                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2118                 for (j = 0; j < tqpv; j++) {
2119                         map_vector_to_txq(adapter, i, txr_idx);
2120                         txr_idx++;
2121                         txr_remaining--;
2122                 }
2123         }
2124
2125 out:
2126         return err;
2127 }
2128
2129 /**
2130  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2131  * @adapter: board private structure
2132  *
2133  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2134  * interrupts from the kernel.
2135  **/
2136 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2137 {
2138         struct net_device *netdev = adapter->netdev;
2139         irqreturn_t (*handler)(int, void *);
2140         int i, vector, q_vectors, err;
2141         int ri = 0, ti = 0;
2142
2143         /* Decrement for Other and TCP Timer vectors */
2144         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2145
2146         /* Map the Tx/Rx rings to the vectors we were allotted. */
2147         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2148         if (err)
2149                 goto out;
2150
2151 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2152                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2153                          &ixgbe_msix_clean_many)
2154         for (vector = 0; vector < q_vectors; vector++) {
2155                 handler = SET_HANDLER(adapter->q_vector[vector]);
2156
2157                 if (handler == &ixgbe_msix_clean_rx) {
2158                         sprintf(adapter->name[vector], "%s-%s-%d",
2159                                 netdev->name, "rx", ri++);
2160                 } else if (handler == &ixgbe_msix_clean_tx) {
2161                         sprintf(adapter->name[vector], "%s-%s-%d",
2162                                 netdev->name, "tx", ti++);
2163                 } else
2164                         sprintf(adapter->name[vector], "%s-%s-%d",
2165                                 netdev->name, "TxRx", vector);
2166
2167                 err = request_irq(adapter->msix_entries[vector].vector,
2168                                   handler, 0, adapter->name[vector],
2169                                   adapter->q_vector[vector]);
2170                 if (err) {
2171                         e_err(probe, "request_irq failed for MSIX interrupt "
2172                               "Error: %d\n", err);
2173                         goto free_queue_irqs;
2174                 }
2175         }
2176
2177         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2178         err = request_irq(adapter->msix_entries[vector].vector,
2179                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2180         if (err) {
2181                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2182                 goto free_queue_irqs;
2183         }
2184
2185         return 0;
2186
2187 free_queue_irqs:
2188         for (i = vector - 1; i >= 0; i--)
2189                 free_irq(adapter->msix_entries[--vector].vector,
2190                          adapter->q_vector[i]);
2191         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2192         pci_disable_msix(adapter->pdev);
2193         kfree(adapter->msix_entries);
2194         adapter->msix_entries = NULL;
2195 out:
2196         return err;
2197 }
2198
2199 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2200 {
2201         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2202         u8 current_itr;
2203         u32 new_itr = q_vector->eitr;
2204         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2205         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2206
2207         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2208                                             q_vector->tx_itr,
2209                                             tx_ring->total_packets,
2210                                             tx_ring->total_bytes);
2211         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2212                                             q_vector->rx_itr,
2213                                             rx_ring->total_packets,
2214                                             rx_ring->total_bytes);
2215
2216         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2217
2218         switch (current_itr) {
2219         /* counts and packets in update_itr are dependent on these numbers */
2220         case lowest_latency:
2221                 new_itr = 100000;
2222                 break;
2223         case low_latency:
2224                 new_itr = 20000; /* aka hwitr = ~200 */
2225                 break;
2226         case bulk_latency:
2227                 new_itr = 8000;
2228                 break;
2229         default:
2230                 break;
2231         }
2232
2233         if (new_itr != q_vector->eitr) {
2234                 /* do an exponential smoothing */
2235                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2236
2237                 /* save the algorithm value here, not the smoothed one */
2238                 q_vector->eitr = new_itr;
2239
2240                 ixgbe_write_eitr(q_vector);
2241         }
2242 }
2243
2244 /**
2245  * ixgbe_irq_enable - Enable default interrupt generation settings
2246  * @adapter: board private structure
2247  **/
2248 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2249                                     bool flush)
2250 {
2251         u32 mask;
2252
2253         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2254         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2255                 mask |= IXGBE_EIMS_GPI_SDP0;
2256         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2257                 mask |= IXGBE_EIMS_GPI_SDP1;
2258         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2259                 mask |= IXGBE_EIMS_ECC;
2260                 mask |= IXGBE_EIMS_GPI_SDP1;
2261                 mask |= IXGBE_EIMS_GPI_SDP2;
2262                 if (adapter->num_vfs)
2263                         mask |= IXGBE_EIMS_MAILBOX;
2264         }
2265         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2266             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2267                 mask |= IXGBE_EIMS_FLOW_DIR;
2268
2269         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2270         if (queues)
2271                 ixgbe_irq_enable_queues(adapter, ~0);
2272         if (flush)
2273                 IXGBE_WRITE_FLUSH(&adapter->hw);
2274
2275         if (adapter->num_vfs > 32) {
2276                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2277                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2278         }
2279 }
2280
2281 /**
2282  * ixgbe_intr - legacy mode Interrupt Handler
2283  * @irq: interrupt number
2284  * @data: pointer to a network interface device structure
2285  **/
2286 static irqreturn_t ixgbe_intr(int irq, void *data)
2287 {
2288         struct net_device *netdev = data;
2289         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2290         struct ixgbe_hw *hw = &adapter->hw;
2291         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2292         u32 eicr;
2293
2294         /*
2295          * Workaround for silicon errata on 82598.  Mask the interrupts
2296          * before the read of EICR.
2297          */
2298         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2299
2300         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2301          * therefore no explict interrupt disable is necessary */
2302         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2303         if (!eicr) {
2304                 /*
2305                  * shared interrupt alert!
2306                  * make sure interrupts are enabled because the read will
2307                  * have disabled interrupts due to EIAM
2308                  * finish the workaround of silicon errata on 82598.  Unmask
2309                  * the interrupt that we masked before the EICR read.
2310                  */
2311                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2312                         ixgbe_irq_enable(adapter, true, true);
2313                 return IRQ_NONE;        /* Not our interrupt */
2314         }
2315
2316         if (eicr & IXGBE_EICR_LSC)
2317                 ixgbe_check_lsc(adapter);
2318
2319         if (hw->mac.type == ixgbe_mac_82599EB)
2320                 ixgbe_check_sfp_event(adapter, eicr);
2321
2322         ixgbe_check_fan_failure(adapter, eicr);
2323         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2324             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2325                 schedule_work(&adapter->check_overtemp_task);
2326
2327         if (napi_schedule_prep(&(q_vector->napi))) {
2328                 adapter->tx_ring[0]->total_packets = 0;
2329                 adapter->tx_ring[0]->total_bytes = 0;
2330                 adapter->rx_ring[0]->total_packets = 0;
2331                 adapter->rx_ring[0]->total_bytes = 0;
2332                 /* would disable interrupts here but EIAM disabled it */
2333                 __napi_schedule(&(q_vector->napi));
2334         }
2335
2336         /*
2337          * re-enable link(maybe) and non-queue interrupts, no flush.
2338          * ixgbe_poll will re-enable the queue interrupts
2339          */
2340
2341         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2342                 ixgbe_irq_enable(adapter, false, false);
2343
2344         return IRQ_HANDLED;
2345 }
2346
2347 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2348 {
2349         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2350
2351         for (i = 0; i < q_vectors; i++) {
2352                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2353                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2354                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2355                 q_vector->rxr_count = 0;
2356                 q_vector->txr_count = 0;
2357         }
2358 }
2359
2360 /**
2361  * ixgbe_request_irq - initialize interrupts
2362  * @adapter: board private structure
2363  *
2364  * Attempts to configure interrupts using the best available
2365  * capabilities of the hardware and kernel.
2366  **/
2367 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2368 {
2369         struct net_device *netdev = adapter->netdev;
2370         int err;
2371
2372         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2373                 err = ixgbe_request_msix_irqs(adapter);
2374         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2375                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2376                                   netdev->name, netdev);
2377         } else {
2378                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2379                                   netdev->name, netdev);
2380         }
2381
2382         if (err)
2383                 e_err(probe, "request_irq failed, Error %d\n", err);
2384
2385         return err;
2386 }
2387
2388 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2389 {
2390         struct net_device *netdev = adapter->netdev;
2391
2392         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2393                 int i, q_vectors;
2394
2395                 q_vectors = adapter->num_msix_vectors;
2396
2397                 i = q_vectors - 1;
2398                 free_irq(adapter->msix_entries[i].vector, netdev);
2399
2400                 i--;
2401                 for (; i >= 0; i--) {
2402                         free_irq(adapter->msix_entries[i].vector,
2403                                  adapter->q_vector[i]);
2404                 }
2405
2406                 ixgbe_reset_q_vectors(adapter);
2407         } else {
2408                 free_irq(adapter->pdev->irq, netdev);
2409         }
2410 }
2411
2412 /**
2413  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2414  * @adapter: board private structure
2415  **/
2416 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2417 {
2418         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2419                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2420         } else {
2421                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2422                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2423                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2424                 if (adapter->num_vfs > 32)
2425                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2426         }
2427         IXGBE_WRITE_FLUSH(&adapter->hw);
2428         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2429                 int i;
2430                 for (i = 0; i < adapter->num_msix_vectors; i++)
2431                         synchronize_irq(adapter->msix_entries[i].vector);
2432         } else {
2433                 synchronize_irq(adapter->pdev->irq);
2434         }
2435 }
2436
2437 /**
2438  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2439  *
2440  **/
2441 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2442 {
2443         struct ixgbe_hw *hw = &adapter->hw;
2444
2445         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2446                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2447
2448         ixgbe_set_ivar(adapter, 0, 0, 0);
2449         ixgbe_set_ivar(adapter, 1, 0, 0);
2450
2451         map_vector_to_rxq(adapter, 0, 0);
2452         map_vector_to_txq(adapter, 0, 0);
2453
2454         e_info(hw, "Legacy interrupt IVAR setup done\n");
2455 }
2456
2457 /**
2458  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2459  * @adapter: board private structure
2460  * @ring: structure containing ring specific data
2461  *
2462  * Configure the Tx descriptor ring after a reset.
2463  **/
2464 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2465                              struct ixgbe_ring *ring)
2466 {
2467         struct ixgbe_hw *hw = &adapter->hw;
2468         u64 tdba = ring->dma;
2469         int wait_loop = 10;
2470         u32 txdctl;
2471         u16 reg_idx = ring->reg_idx;
2472
2473         /* disable queue to avoid issues while updating state */
2474         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2475         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2476                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2477         IXGBE_WRITE_FLUSH(hw);
2478
2479         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2480                         (tdba & DMA_BIT_MASK(32)));
2481         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2482         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2483                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2484         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2485         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2486         ring->head = IXGBE_TDH(reg_idx);
2487         ring->tail = IXGBE_TDT(reg_idx);
2488
2489         /* configure fetching thresholds */
2490         if (adapter->rx_itr_setting == 0) {
2491                 /* cannot set wthresh when itr==0 */
2492                 txdctl &= ~0x007F0000;
2493         } else {
2494                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2495                 txdctl |= (8 << 16);
2496         }
2497         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2498                 /* PThresh workaround for Tx hang with DFP enabled. */
2499                 txdctl |= 32;
2500         }
2501
2502         /* reinitialize flowdirector state */
2503         set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2504
2505         /* enable queue */
2506         txdctl |= IXGBE_TXDCTL_ENABLE;
2507         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2508
2509         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2510         if (hw->mac.type == ixgbe_mac_82598EB &&
2511             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2512                 return;
2513
2514         /* poll to verify queue is enabled */
2515         do {
2516                 msleep(1);
2517                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2518         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2519         if (!wait_loop)
2520                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2521 }
2522
2523 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2524 {
2525         struct ixgbe_hw *hw = &adapter->hw;
2526         u32 rttdcs;
2527         u32 mask;
2528
2529         if (hw->mac.type == ixgbe_mac_82598EB)
2530                 return;
2531
2532         /* disable the arbiter while setting MTQC */
2533         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2534         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2535         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2536
2537         /* set transmit pool layout */
2538         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2539         switch (adapter->flags & mask) {
2540
2541         case (IXGBE_FLAG_SRIOV_ENABLED):
2542                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2543                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2544                 break;
2545
2546         case (IXGBE_FLAG_DCB_ENABLED):
2547                 /* We enable 8 traffic classes, DCB only */
2548                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2549                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2550                 break;
2551
2552         default:
2553                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2554                 break;
2555         }
2556
2557         /* re-enable the arbiter */
2558         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2559         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2560 }
2561
2562 /**
2563  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2564  * @adapter: board private structure
2565  *
2566  * Configure the Tx unit of the MAC after a reset.
2567  **/
2568 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2569 {
2570         struct ixgbe_hw *hw = &adapter->hw;
2571         u32 dmatxctl;
2572         u32 i;
2573
2574         ixgbe_setup_mtqc(adapter);
2575
2576         if (hw->mac.type != ixgbe_mac_82598EB) {
2577                 /* DMATXCTL.EN must be before Tx queues are enabled */
2578                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2579                 dmatxctl |= IXGBE_DMATXCTL_TE;
2580                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2581         }
2582
2583         /* Setup the HW Tx Head and Tail descriptor pointers */
2584         for (i = 0; i < adapter->num_tx_queues; i++)
2585                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2586 }
2587
2588 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2589
2590 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2591                                    struct ixgbe_ring *rx_ring)
2592 {
2593         u32 srrctl;
2594         int index;
2595         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2596
2597         index = rx_ring->reg_idx;
2598         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2599                 unsigned long mask;
2600                 mask = (unsigned long) feature[RING_F_RSS].mask;
2601                 index = index & mask;
2602         }
2603         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2604
2605         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2606         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2607         if (adapter->num_vfs)
2608                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2609
2610         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2611                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2612
2613         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2614 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2615                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2616 #else
2617                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2618 #endif
2619                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2620         } else {
2621                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2622                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2623                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2624         }
2625
2626         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2627 }
2628
2629 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2630 {
2631         struct ixgbe_hw *hw = &adapter->hw;
2632         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2633                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2634                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2635         u32 mrqc = 0, reta = 0;
2636         u32 rxcsum;
2637         int i, j;
2638         int mask;
2639
2640         /* Fill out hash function seeds */
2641         for (i = 0; i < 10; i++)
2642                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2643
2644         /* Fill out redirection table */
2645         for (i = 0, j = 0; i < 128; i++, j++) {
2646                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2647                         j = 0;
2648                 /* reta = 4-byte sliding window of
2649                  * 0x00..(indices-1)(indices-1)00..etc. */
2650                 reta = (reta << 8) | (j * 0x11);
2651                 if ((i & 3) == 3)
2652                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2653         }
2654
2655         /* Disable indicating checksum in descriptor, enables RSS hash */
2656         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2657         rxcsum |= IXGBE_RXCSUM_PCSD;
2658         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2659
2660         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2661                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2662         else
2663                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2664 #ifdef CONFIG_IXGBE_DCB
2665                                          | IXGBE_FLAG_DCB_ENABLED
2666 #endif
2667                                          | IXGBE_FLAG_SRIOV_ENABLED
2668                                         );
2669
2670         switch (mask) {
2671         case (IXGBE_FLAG_RSS_ENABLED):
2672                 mrqc = IXGBE_MRQC_RSSEN;
2673                 break;
2674         case (IXGBE_FLAG_SRIOV_ENABLED):
2675                 mrqc = IXGBE_MRQC_VMDQEN;
2676                 break;
2677 #ifdef CONFIG_IXGBE_DCB
2678         case (IXGBE_FLAG_DCB_ENABLED):
2679                 mrqc = IXGBE_MRQC_RT8TCEN;
2680                 break;
2681 #endif /* CONFIG_IXGBE_DCB */
2682         default:
2683                 break;
2684         }
2685
2686         /* Perform hash on these packet types */
2687         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2688               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2689               | IXGBE_MRQC_RSS_FIELD_IPV6
2690               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2691
2692         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2693 }
2694
2695 /**
2696  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2697  * @adapter:    address of board private structure
2698  * @index:      index of ring to set
2699  **/
2700 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2701                                    struct ixgbe_ring *ring)
2702 {
2703         struct ixgbe_hw *hw = &adapter->hw;
2704         u32 rscctrl;
2705         int rx_buf_len;
2706         u16 reg_idx = ring->reg_idx;
2707
2708         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2709                 return;
2710
2711         rx_buf_len = ring->rx_buf_len;
2712         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2713         rscctrl |= IXGBE_RSCCTL_RSCEN;
2714         /*
2715          * we must limit the number of descriptors so that the
2716          * total size of max desc * buf_len is not greater
2717          * than 65535
2718          */
2719         if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2720 #if (MAX_SKB_FRAGS > 16)
2721                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2722 #elif (MAX_SKB_FRAGS > 8)
2723                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2724 #elif (MAX_SKB_FRAGS > 4)
2725                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2726 #else
2727                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2728 #endif
2729         } else {
2730                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2731                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2732                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2733                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2734                 else
2735                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2736         }
2737         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2738 }
2739
2740 /**
2741  *  ixgbe_set_uta - Set unicast filter table address
2742  *  @adapter: board private structure
2743  *
2744  *  The unicast table address is a register array of 32-bit registers.
2745  *  The table is meant to be used in a way similar to how the MTA is used
2746  *  however due to certain limitations in the hardware it is necessary to
2747  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2748  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2749  **/
2750 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2751 {
2752         struct ixgbe_hw *hw = &adapter->hw;
2753         int i;
2754
2755         /* The UTA table only exists on 82599 hardware and newer */
2756         if (hw->mac.type < ixgbe_mac_82599EB)
2757                 return;
2758
2759         /* we only need to do this if VMDq is enabled */
2760         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2761                 return;
2762
2763         for (i = 0; i < 128; i++)
2764                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2765 }
2766
2767 #define IXGBE_MAX_RX_DESC_POLL 10
2768 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2769                                        struct ixgbe_ring *ring)
2770 {
2771         struct ixgbe_hw *hw = &adapter->hw;
2772         int reg_idx = ring->reg_idx;
2773         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2774         u32 rxdctl;
2775
2776         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2777         if (hw->mac.type == ixgbe_mac_82598EB &&
2778             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2779                 return;
2780
2781         do {
2782                 msleep(1);
2783                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2784         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2785
2786         if (!wait_loop) {
2787                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2788                       "the polling period\n", reg_idx);
2789         }
2790 }
2791
2792 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2793                              struct ixgbe_ring *ring)
2794 {
2795         struct ixgbe_hw *hw = &adapter->hw;
2796         u64 rdba = ring->dma;
2797         u32 rxdctl;
2798         u16 reg_idx = ring->reg_idx;
2799
2800         /* disable queue to avoid issues while updating state */
2801         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2802         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2803                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2804         IXGBE_WRITE_FLUSH(hw);
2805
2806         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2807         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2808         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2809                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2810         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2811         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2812         ring->head = IXGBE_RDH(reg_idx);
2813         ring->tail = IXGBE_RDT(reg_idx);
2814
2815         ixgbe_configure_srrctl(adapter, ring);
2816         ixgbe_configure_rscctl(adapter, ring);
2817
2818         if (hw->mac.type == ixgbe_mac_82598EB) {
2819                 /*
2820                  * enable cache line friendly hardware writes:
2821                  * PTHRESH=32 descriptors (half the internal cache),
2822                  * this also removes ugly rx_no_buffer_count increment
2823                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2824                  * WTHRESH=8 burst writeback up to two cache lines
2825                  */
2826                 rxdctl &= ~0x3FFFFF;
2827                 rxdctl |=  0x080420;
2828         }
2829
2830         /* enable receive descriptor ring */
2831         rxdctl |= IXGBE_RXDCTL_ENABLE;
2832         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2833
2834         ixgbe_rx_desc_queue_enable(adapter, ring);
2835         ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
2836 }
2837
2838 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2839 {
2840         struct ixgbe_hw *hw = &adapter->hw;
2841         int p;
2842
2843         /* PSRTYPE must be initialized in non 82598 adapters */
2844         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2845                       IXGBE_PSRTYPE_UDPHDR |
2846                       IXGBE_PSRTYPE_IPV4HDR |
2847                       IXGBE_PSRTYPE_L2HDR |
2848                       IXGBE_PSRTYPE_IPV6HDR;
2849
2850         if (hw->mac.type == ixgbe_mac_82598EB)
2851                 return;
2852
2853         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2854                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2855
2856         for (p = 0; p < adapter->num_rx_pools; p++)
2857                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2858                                 psrtype);
2859 }
2860
2861 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2862 {
2863         struct ixgbe_hw *hw = &adapter->hw;
2864         u32 gcr_ext;
2865         u32 vt_reg_bits;
2866         u32 reg_offset, vf_shift;
2867         u32 vmdctl;
2868
2869         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2870                 return;
2871
2872         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2873         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2874         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2875         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2876
2877         vf_shift = adapter->num_vfs % 32;
2878         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2879
2880         /* Enable only the PF's pool for Tx/Rx */
2881         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2882         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2883         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2884         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2885         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2886
2887         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2888         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2889
2890         /*
2891          * Set up VF register offsets for selected VT Mode,
2892          * i.e. 32 or 64 VFs for SR-IOV
2893          */
2894         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2895         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2896         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2897         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2898
2899         /* enable Tx loopback for VF/PF communication */
2900         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2901 }
2902
2903 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2904 {
2905         struct ixgbe_hw *hw = &adapter->hw;
2906         struct net_device *netdev = adapter->netdev;
2907         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2908         int rx_buf_len;
2909         struct ixgbe_ring *rx_ring;
2910         int i;
2911         u32 mhadd, hlreg0;
2912
2913         /* Decide whether to use packet split mode or not */
2914         /* Do not use packet split if we're in SR-IOV Mode */
2915         if (!adapter->num_vfs)
2916                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2917
2918         /* Set the RX buffer length according to the mode */
2919         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2920                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2921         } else {
2922                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2923                     (netdev->mtu <= ETH_DATA_LEN))
2924                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2925                 else
2926                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2927         }
2928
2929 #ifdef IXGBE_FCOE
2930         /* adjust max frame to be able to do baby jumbo for FCoE */
2931         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2932             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2933                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2934
2935 #endif /* IXGBE_FCOE */
2936         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2937         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2938                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2939                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2940
2941                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2942         }
2943
2944         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2945         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2946         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2947         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2948
2949         /*
2950          * Setup the HW Rx Head and Tail Descriptor Pointers and
2951          * the Base and Length of the Rx Descriptor Ring
2952          */
2953         for (i = 0; i < adapter->num_rx_queues; i++) {
2954                 rx_ring = adapter->rx_ring[i];
2955                 rx_ring->rx_buf_len = rx_buf_len;
2956
2957                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2958                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2959                 else
2960                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2961
2962 #ifdef IXGBE_FCOE
2963                 if (netdev->features & NETIF_F_FCOE_MTU) {
2964                         struct ixgbe_ring_feature *f;
2965                         f = &adapter->ring_feature[RING_F_FCOE];
2966                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2967                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2968                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2969                                         rx_ring->rx_buf_len =
2970                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2971                         }
2972                 }
2973 #endif /* IXGBE_FCOE */
2974         }
2975
2976 }
2977
2978 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2979 {
2980         struct ixgbe_hw *hw = &adapter->hw;
2981         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2982
2983         switch (hw->mac.type) {
2984         case ixgbe_mac_82598EB:
2985                 /*
2986                  * For VMDq support of different descriptor types or
2987                  * buffer sizes through the use of multiple SRRCTL
2988                  * registers, RDRXCTL.MVMEN must be set to 1
2989                  *
2990                  * also, the manual doesn't mention it clearly but DCA hints
2991                  * will only use queue 0's tags unless this bit is set.  Side
2992                  * effects of setting this bit are only that SRRCTL must be
2993                  * fully programmed [0..15]
2994                  */
2995                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2996                 break;
2997         case ixgbe_mac_82599EB:
2998                 /* Disable RSC for ACK packets */
2999                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3000                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3001                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3002                 /* hardware requires some bits to be set by default */
3003                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3004                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3005                 break;
3006         default:
3007                 /* We should do nothing since we don't know this hardware */
3008                 return;
3009         }
3010
3011         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3012 }
3013
3014 /**
3015  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3016  * @adapter: board private structure
3017  *
3018  * Configure the Rx unit of the MAC after a reset.
3019  **/
3020 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3021 {
3022         struct ixgbe_hw *hw = &adapter->hw;
3023         int i;
3024         u32 rxctrl;
3025
3026         /* disable receives while setting up the descriptors */
3027         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3028         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3029
3030         ixgbe_setup_psrtype(adapter);
3031         ixgbe_setup_rdrxctl(adapter);
3032
3033         /* Program registers for the distribution of queues */
3034         ixgbe_setup_mrqc(adapter);
3035
3036         ixgbe_set_uta(adapter);
3037
3038         /* set_rx_buffer_len must be called before ring initialization */
3039         ixgbe_set_rx_buffer_len(adapter);
3040
3041         /*
3042          * Setup the HW Rx Head and Tail Descriptor Pointers and
3043          * the Base and Length of the Rx Descriptor Ring
3044          */
3045         for (i = 0; i < adapter->num_rx_queues; i++)
3046                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3047
3048         /* disable drop enable for 82598 parts */
3049         if (hw->mac.type == ixgbe_mac_82598EB)
3050                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3051
3052         /* enable all receives */
3053         rxctrl |= IXGBE_RXCTRL_RXEN;
3054         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3055 }
3056
3057 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3058 {
3059         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3060         struct ixgbe_hw *hw = &adapter->hw;
3061         int pool_ndx = adapter->num_vfs;
3062
3063         /* add VID to filter table */
3064         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3065         set_bit(vid, adapter->active_vlans);
3066 }
3067
3068 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3069 {
3070         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3071         struct ixgbe_hw *hw = &adapter->hw;
3072         int pool_ndx = adapter->num_vfs;
3073
3074         /* remove VID from filter table */
3075         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3076         clear_bit(vid, adapter->active_vlans);
3077 }
3078
3079 /**
3080  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3081  * @adapter: driver data
3082  */
3083 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3084 {
3085         struct ixgbe_hw *hw = &adapter->hw;
3086         u32 vlnctrl;
3087
3088         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3089         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3090         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3091 }
3092
3093 /**
3094  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3095  * @adapter: driver data
3096  */
3097 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3098 {
3099         struct ixgbe_hw *hw = &adapter->hw;
3100         u32 vlnctrl;
3101
3102         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3103         vlnctrl |= IXGBE_VLNCTRL_VFE;
3104         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3105         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3106 }
3107
3108 /**
3109  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3110  * @adapter: driver data
3111  */
3112 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3113 {
3114         struct ixgbe_hw *hw = &adapter->hw;
3115         u32 vlnctrl;
3116         int i, j;
3117
3118         switch (hw->mac.type) {
3119         case ixgbe_mac_82598EB:
3120                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3121                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3122                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3123                 break;
3124         case ixgbe_mac_82599EB:
3125                 for (i = 0; i < adapter->num_rx_queues; i++) {
3126                         j = adapter->rx_ring[i]->reg_idx;