drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 604                                       struct ixgbe_tx_buffer
 605                                       *tx_buffer_info)
 606 {
 607         if (tx_buffer_info->dma) {
 608                 if (tx_buffer_info->mapped_as_page)
 609                         dma_unmap_page(&adapter->pdev->dev,
 610                                        tx_buffer_info->dma,
 611                                        tx_buffer_info->length,
 612                                        DMA_TO_DEVICE);
 613                 else
 614                         dma_unmap_single(&adapter->pdev->dev,
 615                                          tx_buffer_info->dma,
 616                                          tx_buffer_info->length,
 617                                          DMA_TO_DEVICE);
 618                 tx_buffer_info->dma = 0;
 619         }
 620         if (tx_buffer_info->skb) {
 621                 dev_kfree_skb_any(tx_buffer_info->skb);
 622                 tx_buffer_info->skb = NULL;
 623         }
 624         tx_buffer_info->time_stamp = 0;
 625         /* tx_buffer_info must be completely set up in the transmit path */
 626 }
 627
 628 /**
 629  * ixgbe_tx_xon_state - check the tx ring xon state
 630  * @adapter: the ixgbe adapter
 631  * @tx_ring: the corresponding tx_ring
 632  *
 633  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 634  * corresponding TC of this tx_ring when checking TFCS.
 635  *
 636  * Returns : true if in xon state (currently not paused)
 637  */
 638 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 639                                       struct ixgbe_ring *tx_ring)
 640 {
 641         u32 txoff = IXGBE_TFCS_TXOFF;
 642
 643 #ifdef CONFIG_IXGBE_DCB
 644         if (adapter->dcb_cfg.pfc_mode_enable) {
 645                 int tc;
 646                 int reg_idx = tx_ring->reg_idx;
 647                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 648
 649                 switch (adapter->hw.mac.type) {
 650                 case ixgbe_mac_82598EB:
 651                         tc = reg_idx >> 2;
 652                         txoff = IXGBE_TFCS_TXOFF0;
 653                         break;
 654                 case ixgbe_mac_82599EB:
 655                         tc = 0;
 656                         txoff = IXGBE_TFCS_TXOFF;
 657                         if (dcb_i == 8) {
 658                                 /* TC0, TC1 */
 659                                 tc = reg_idx >> 5;
 660                                 if (tc == 2) /* TC2, TC3 */
 661                                         tc += (reg_idx - 64) >> 4;
 662                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 663                                         tc += 1 + ((reg_idx - 96) >> 3);
 664                         } else if (dcb_i == 4) {
 665                                 /* TC0, TC1 */
 666                                 tc = reg_idx >> 6;
 667                                 if (tc == 1) {
 668                                         tc += (reg_idx - 64) >> 5;
 669                                         if (tc == 2) /* TC2, TC3 */
 670                                                 tc += (reg_idx - 96) >> 4;
 671                                 }
 672                         }
 673                         break;
 674                 default:
 675                         tc = 0;
 676                 }
 677                 txoff <<= tc;
 678         }
 679 #endif
 680         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 681 }
 682
 683 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 684                                        struct ixgbe_ring *tx_ring,
 685                                        unsigned int eop)
 686 {
 687         struct ixgbe_hw *hw = &adapter->hw;
 688
 689         /* Detect a transmit hang in hardware, this serializes the
 690          * check with the clearing of time_stamp and movement of eop */
 691         adapter->detect_tx_hung = false;
 692         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 693             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 694             ixgbe_tx_xon_state(adapter, tx_ring)) {
 695                 /* detected Tx unit hang */
 696                 union ixgbe_adv_tx_desc *tx_desc;
 697                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 698                 e_err(drv, "Detected Tx Unit Hang\n"
 699                       "  Tx Queue             <%d>\n"
 700                       "  TDH, TDT             <%x>, <%x>\n"
 701                       "  next_to_use          <%x>\n"
 702                       "  next_to_clean        <%x>\n"
 703                       "tx_buffer_info[next_to_clean]\n"
 704                       "  time_stamp           <%lx>\n"
 705                       "  jiffies              <%lx>\n",
 706                       tx_ring->queue_index,
 707                       IXGBE_READ_REG(hw, tx_ring->head),
 708                       IXGBE_READ_REG(hw, tx_ring->tail),
 709                       tx_ring->next_to_use, eop,
 710                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 711                 return true;
 712         }
 713
 714         return false;
 715 }
 716
 717 #define IXGBE_MAX_TXD_PWR       14
 718 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 719
 720 /* Tx Descriptors needed, worst case */
 721 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 722                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 723 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 724         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 725
 726 static void ixgbe_tx_timeout(struct net_device *netdev);
 727
 728 /**
 729  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 730  * @q_vector: structure containing interrupt and ring information
 731  * @tx_ring: tx ring to clean
 732  **/
 733 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 734                                struct ixgbe_ring *tx_ring)
 735 {
 736         struct ixgbe_adapter *adapter = q_vector->adapter;
 737         struct net_device *netdev = adapter->netdev;
 738         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 739         struct ixgbe_tx_buffer *tx_buffer_info;
 740         unsigned int i, eop, count = 0;
 741         unsigned int total_bytes = 0, total_packets = 0;
 742
 743         i = tx_ring->next_to_clean;
 744         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 745         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 746
 747         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 748                (count < tx_ring->work_limit)) {
 749                 bool cleaned = false;
 750                 rmb(); /* read buffer_info after eop_desc */
 751                 for ( ; !cleaned; count++) {
 752                         struct sk_buff *skb;
 753                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 754                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 755                         cleaned = (i == eop);
 756                         skb = tx_buffer_info->skb;
 757
 758                         if (cleaned && skb) {
 759                                 unsigned int segs, bytecount;
 760                                 unsigned int hlen = skb_headlen(skb);
 761
 762                                 /* gso_segs is currently only valid for tcp */
 763                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 764 #ifdef IXGBE_FCOE
 765                                 /* adjust for FCoE Sequence Offload */
 766                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 767                                     && skb_is_gso(skb)
 768                                     && vlan_get_protocol(skb) ==
 769                                     htons(ETH_P_FCOE)) {
 770                                         hlen = skb_transport_offset(skb) +
 771                                                 sizeof(struct fc_frame_header) +
 772                                                 sizeof(struct fcoe_crc_eof);
 773                                         segs = DIV_ROUND_UP(skb->len - hlen,
 774                                                 skb_shinfo(skb)->gso_size);
 775                                 }
 776 #endif /* IXGBE_FCOE */
 777                                 /* multiply data chunks by size of headers */
 778                                 bytecount = ((segs - 1) * hlen) + skb->len;
 779                                 total_packets += segs;
 780                                 total_bytes += bytecount;
 781                         }
 782
 783                         ixgbe_unmap_and_free_tx_resource(adapter,
 784                                                          tx_buffer_info);
 785
 786                         tx_desc->wb.status = 0;
 787
 788                         i++;
 789                         if (i == tx_ring->count)
 790                                 i = 0;
 791                 }
 792
 793                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 794                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 795         }
 796
 797         tx_ring->next_to_clean = i;
 798
 799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 800         if (unlikely(count && netif_carrier_ok(netdev) &&
 801                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 802                 /* Make sure that anybody stopping the queue after this
 803                  * sees the new next_to_clean.
 804                  */
 805                 smp_mb();
 806                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 807                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 808                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 809                         ++tx_ring->restart_queue;
 810                 }
 811         }
 812
 813         if (adapter->detect_tx_hung) {
 814                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 815                         /* schedule immediate reset if we believe we hung */
 816                         e_info(probe, "tx hang %d detected, resetting "
 817                                "adapter\n", adapter->tx_timeout_count + 1);
 818                         ixgbe_tx_timeout(adapter->netdev);
 819                 }
 820         }
 821
 822         /* re-arm the interrupt */
 823         if (count >= tx_ring->work_limit)
 824                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 825
 826         tx_ring->total_bytes += total_bytes;
 827         tx_ring->total_packets += total_packets;
 828         u64_stats_update_begin(&tx_ring->syncp);
 829         tx_ring->stats.packets += total_packets;
 830         tx_ring->stats.bytes += total_bytes;
 831         u64_stats_update_end(&tx_ring->syncp);
 832         return count < tx_ring->work_limit;
 833 }
 834
 835 #ifdef CONFIG_IXGBE_DCA
 836 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 837                                 struct ixgbe_ring *rx_ring)
 838 {
 839         u32 rxctrl;
 840         int cpu = get_cpu();
 841         int q = rx_ring->reg_idx;
 842
 843         if (rx_ring->cpu != cpu) {
 844                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 845                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 846                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 847                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 848                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 849                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 850                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 851                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 852                 }
 853                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 854                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 855                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 856                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 857                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 858                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 859                 rx_ring->cpu = cpu;
 860         }
 861         put_cpu();
 862 }
 863
 864 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 865                                 struct ixgbe_ring *tx_ring)
 866 {
 867         u32 txctrl;
 868         int cpu = get_cpu();
 869         int q = tx_ring->reg_idx;
 870         struct ixgbe_hw *hw = &adapter->hw;
 871
 872         if (tx_ring->cpu != cpu) {
 873                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 874                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 875                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 876                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 877                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 878                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 879                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 880                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 881                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 882                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 883                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 884                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 885                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 886                 }
 887                 tx_ring->cpu = cpu;
 888         }
 889         put_cpu();
 890 }
 891
 892 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 893 {
 894         int i;
 895
 896         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 897                 return;
 898
 899         /* always use CB2 mode, difference is masked in the CB driver */
 900         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 901
 902         for (i = 0; i < adapter->num_tx_queues; i++) {
 903                 adapter->tx_ring[i]->cpu = -1;
 904                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 905         }
 906         for (i = 0; i < adapter->num_rx_queues; i++) {
 907                 adapter->rx_ring[i]->cpu = -1;
 908                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 909         }
 910 }
 911
 912 static int __ixgbe_notify_dca(struct device *dev, void *data)
 913 {
 914         struct net_device *netdev = dev_get_drvdata(dev);
 915         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 916         unsigned long event = *(unsigned long *)data;
 917
 918         switch (event) {
 919         case DCA_PROVIDER_ADD:
 920                 /* if we're already enabled, don't do it again */
 921                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 922                         break;
 923                 if (dca_add_requester(dev) == 0) {
 924                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 925                         ixgbe_setup_dca(adapter);
 926                         break;
 927                 }
 928                 /* Fall Through since DCA is disabled. */
 929         case DCA_PROVIDER_REMOVE:
 930                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 931                         dca_remove_requester(dev);
 932                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 933                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 934                 }
 935                 break;
 936         }
 937
 938         return 0;
 939 }
 940
 941 #endif /* CONFIG_IXGBE_DCA */
 942 /**
 943  * ixgbe_receive_skb - Send a completed packet up the stack
 944  * @adapter: board private structure
 945  * @skb: packet to send up
 946  * @status: hardware indication of status of receive
 947  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 948  * @rx_desc: rx descriptor
 949  **/
 950 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 951                               struct sk_buff *skb, u8 status,
 952                               struct ixgbe_ring *ring,
 953                               union ixgbe_adv_rx_desc *rx_desc)
 954 {
 955         struct ixgbe_adapter *adapter = q_vector->adapter;
 956         struct napi_struct *napi = &q_vector->napi;
 957         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 958         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 959
 960         if (is_vlan && (tag & VLAN_VID_MASK))
 961                 __vlan_hwaccel_put_tag(skb, tag);
 962
 963         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 964                 napi_gro_receive(napi, skb);
 965         else
 966                 netif_rx(skb);
 967 }
 968
 969 /**
 970  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 971  * @adapter: address of board private structure
 972  * @status_err: hardware indication of status of receive
 973  * @skb: skb currently being received and modified
 974  **/
 975 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 976                                      union ixgbe_adv_rx_desc *rx_desc,
 977                                      struct sk_buff *skb)
 978 {
 979         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 980
 981         skb_checksum_none_assert(skb);
 982
 983         /* Rx csum disabled */
 984         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 985                 return;
 986
 987         /* if IP and error */
 988         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 989             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 990                 adapter->hw_csum_rx_error++;
 991                 return;
 992         }
 993
 994         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 995                 return;
 996
 997         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 998                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 999
1000                 /*
1001                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1002                  * checksum errors.
1003                  */
1004                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1005                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1006                         return;
1007
1008                 adapter->hw_csum_rx_error++;
1009                 return;
1010         }
1011
1012         /* It must be a TCP or UDP packet with a valid checksum */
1013         skb->ip_summed = CHECKSUM_UNNECESSARY;
1014 }
1015
1016 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1017                                          struct ixgbe_ring *rx_ring, u32 val)
1018 {
1019         /*
1020          * Force memory writes to complete before letting h/w
1021          * know there are new descriptors to fetch.  (Only
1022          * applicable for weak-ordered memory model archs,
1023          * such as IA-64).
1024          */
1025         wmb();
1026         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1027 }
1028
1029 /**
1030  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1031  * @adapter: address of board private structure
1032  **/
1033 void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1034                             struct ixgbe_ring *rx_ring,
1035                             int cleaned_count)
1036 {
1037         struct net_device *netdev = adapter->netdev;
1038         struct pci_dev *pdev = adapter->pdev;
1039         union ixgbe_adv_rx_desc *rx_desc;
1040         struct ixgbe_rx_buffer *bi;
1041         unsigned int i;
1042         unsigned int bufsz = rx_ring->rx_buf_len;
1043
1044         i = rx_ring->next_to_use;
1045         bi = &rx_ring->rx_buffer_info[i];
1046
1047         while (cleaned_count--) {
1048                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1049
1050                 if (!bi->page_dma &&
1051                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1052                         if (!bi->page) {
1053                                 bi->page = netdev_alloc_page(netdev);
1054                                 if (!bi->page) {
1055                                         adapter->alloc_rx_page_failed++;
1056                                         goto no_buffers;
1057                                 }
1058                                 bi->page_offset = 0;
1059                         } else {
1060                                 /* use a half page if we're re-using */
1061                                 bi->page_offset ^= (PAGE_SIZE / 2);
1062                         }
1063
1064                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1065                                                     bi->page_offset,
1066                                                     (PAGE_SIZE / 2),
1067                                                     DMA_FROM_DEVICE);
1068                 }
1069
1070                 if (!bi->skb) {
1071                         struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1072                                                                         bufsz);
1073                         bi->skb = skb;
1074
1075                         if (!skb) {
1076                                 adapter->alloc_rx_buff_failed++;
1077                                 goto no_buffers;
1078                         }
1079                         /* initialize queue mapping */
1080                         skb_record_rx_queue(skb, rx_ring->queue_index);
1081                 }
1082
1083                 if (!bi->dma) {
1084                         bi->dma = dma_map_single(&pdev->dev,
1085                                                  bi->skb->data,
1086                                                  rx_ring->rx_buf_len,
1087                                                  DMA_FROM_DEVICE);
1088                 }
1089                 /* Refresh the desc even if buffer_addrs didn't change because
1090                  * each write-back erases this info. */
1091                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1092                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1093                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1094                 } else {
1095                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1096                         rx_desc->read.hdr_addr = 0;
1097                 }
1098
1099                 i++;
1100                 if (i == rx_ring->count)
1101                         i = 0;
1102                 bi = &rx_ring->rx_buffer_info[i];
1103         }
1104
1105 no_buffers:
1106         if (rx_ring->next_to_use != i) {
1107                 rx_ring->next_to_use = i;
1108                 if (i-- == 0)
1109                         i = (rx_ring->count - 1);
1110
1111                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1112         }
1113 }
1114
1115 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1116 {
1117         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1118 }
1119
1120 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1121 {
1122         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1123 }
1124
1125 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1126 {
1127         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1128                 IXGBE_RXDADV_RSCCNT_MASK) >>
1129                 IXGBE_RXDADV_RSCCNT_SHIFT;
1130 }
1131
1132 /**
1133  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1134  * @skb: pointer to the last skb in the rsc queue
1135  * @count: pointer to number of packets coalesced in this context
1136  *
1137  * This function changes a queue full of hw rsc buffers into a completed
1138  * packet.  It uses the ->prev pointers to find the first packet and then
1139  * turns it into the frag list owner.
1140  **/
1141 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1142                                                         u64 *count)
1143 {
1144         unsigned int frag_list_size = 0;
1145
1146         while (skb->prev) {
1147                 struct sk_buff *prev = skb->prev;
1148                 frag_list_size += skb->len;
1149                 skb->prev = NULL;
1150                 skb = prev;
1151                 *count += 1;
1152         }
1153
1154         skb_shinfo(skb)->frag_list = skb->next;
1155         skb->next = NULL;
1156         skb->len += frag_list_size;
1157         skb->data_len += frag_list_size;
1158         skb->truesize += frag_list_size;
1159         return skb;
1160 }
1161
1162 struct ixgbe_rsc_cb {
1163         dma_addr_t dma;
1164         bool delay_unmap;
1165 };
1166
1167 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1168
1169 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1170                                struct ixgbe_ring *rx_ring,
1171                                int *work_done, int work_to_do)
1172 {
1173         struct ixgbe_adapter *adapter = q_vector->adapter;
1174         struct pci_dev *pdev = adapter->pdev;
1175         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1176         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1177         struct sk_buff *skb;
1178         unsigned int i, rsc_count = 0;
1179         u32 len, staterr;
1180         u16 hdr_info;
1181         bool cleaned = false;
1182         int cleaned_count = 0;
1183         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1184 #ifdef IXGBE_FCOE
1185         int ddp_bytes = 0;
1186 #endif /* IXGBE_FCOE */
1187
1188         i = rx_ring->next_to_clean;
1189         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1190         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1191         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1192
1193         while (staterr & IXGBE_RXD_STAT_DD) {
1194                 u32 upper_len = 0;
1195                 if (*work_done >= work_to_do)
1196                         break;
1197                 (*work_done)++;
1198
1199                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1200                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1201                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1202                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1203                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1204                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1205                         if ((len > IXGBE_RX_HDR_SIZE) ||
1206                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1207                                 len = IXGBE_RX_HDR_SIZE;
1208                 } else {
1209                         len = le16_to_cpu(rx_desc->wb.upper.length);
1210                 }
1211
1212                 cleaned = true;
1213                 skb = rx_buffer_info->skb;
1214                 prefetch(skb->data);
1215                 rx_buffer_info->skb = NULL;
1216
1217                 if (rx_buffer_info->dma) {
1218                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1219                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1220                                  (!(skb->prev))) {
1221                                 /*
1222                                  * When HWRSC is enabled, delay unmapping
1223                                  * of the first packet. It carries the
1224                                  * header information, HW may still
1225                                  * access the header after the writeback.
1226                                  * Only unmap it when EOP is reached
1227                                  */
1228                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1229                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1230                         } else {
1231                                 dma_unmap_single(&pdev->dev,
1232                                                  rx_buffer_info->dma,
1233                                                  rx_ring->rx_buf_len,
1234                                                  DMA_FROM_DEVICE);
1235                         }
1236                         rx_buffer_info->dma = 0;
1237                         skb_put(skb, len);
1238                 }
1239
1240                 if (upper_len) {
1241                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1242                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1243                         rx_buffer_info->page_dma = 0;
1244                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1245                                            rx_buffer_info->page,
1246                                            rx_buffer_info->page_offset,
1247                                            upper_len);
1248
1249                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1250                             (page_count(rx_buffer_info->page) != 1))
1251                                 rx_buffer_info->page = NULL;
1252                         else
1253                                 get_page(rx_buffer_info->page);
1254
1255                         skb->len += upper_len;
1256                         skb->data_len += upper_len;
1257                         skb->truesize += upper_len;
1258                 }
1259
1260                 i++;
1261                 if (i == rx_ring->count)
1262                         i = 0;
1263
1264                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1265                 prefetch(next_rxd);
1266                 cleaned_count++;
1267
1268                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1269                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1270
1271                 if (rsc_count) {
1272                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1273                                      IXGBE_RXDADV_NEXTP_SHIFT;
1274                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1275                 } else {
1276                         next_buffer = &rx_ring->rx_buffer_info[i];
1277                 }
1278
1279                 if (staterr & IXGBE_RXD_STAT_EOP) {
1280                         if (skb->prev)
1281                                 skb = ixgbe_transform_rsc_queue(skb,
1282                                                                 &(rx_ring->rsc_count));
1283                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1284                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1285                                         dma_unmap_single(&pdev->dev,
1286                                                          IXGBE_RSC_CB(skb)->dma,
1287                                                          rx_ring->rx_buf_len,
1288                                                          DMA_FROM_DEVICE);
1289                                         IXGBE_RSC_CB(skb)->dma = 0;
1290                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1291                                 }
1292                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1293                                         rx_ring->rsc_count +=
1294                                                 skb_shinfo(skb)->nr_frags;
1295                                 else
1296                                         rx_ring->rsc_count++;
1297                                 rx_ring->rsc_flush++;
1298                         }
1299                         u64_stats_update_begin(&rx_ring->syncp);
1300                         rx_ring->stats.packets++;
1301                         rx_ring->stats.bytes += skb->len;
1302                         u64_stats_update_end(&rx_ring->syncp);
1303                 } else {
1304                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1305                                 rx_buffer_info->skb = next_buffer->skb;
1306                                 rx_buffer_info->dma = next_buffer->dma;
1307                                 next_buffer->skb = skb;
1308                                 next_buffer->dma = 0;
1309                         } else {
1310                                 skb->next = next_buffer->skb;
1311                                 skb->next->prev = skb;
1312                         }
1313                         rx_ring->non_eop_descs++;
1314                         goto next_desc;
1315                 }
1316
1317                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1318                         dev_kfree_skb_irq(skb);
1319                         goto next_desc;
1320                 }
1321
1322                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1323
1324                 /* probably a little skewed due to removing CRC */
1325                 total_rx_bytes += skb->len;
1326                 total_rx_packets++;
1327
1328                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1329 #ifdef IXGBE_FCOE
1330                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1331                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1332                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1333                         if (!ddp_bytes)
1334                                 goto next_desc;
1335                 }
1336 #endif /* IXGBE_FCOE */
1337                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1338
1339 next_desc:
1340                 rx_desc->wb.upper.status_error = 0;
1341
1342                 /* return some buffers to hardware, one at a time is too slow */
1343                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1344                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1345                         cleaned_count = 0;
1346                 }
1347
1348                 /* use prefetched values */
1349                 rx_desc = next_rxd;
1350                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1351
1352                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1353         }
1354
1355         rx_ring->next_to_clean = i;
1356         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1357
1358         if (cleaned_count)
1359                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1360
1361 #ifdef IXGBE_FCOE
1362         /* include DDPed FCoE data */
1363         if (ddp_bytes > 0) {
1364                 unsigned int mss;
1365
1366                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1367                         sizeof(struct fc_frame_header) -
1368                         sizeof(struct fcoe_crc_eof);
1369                 if (mss > 512)
1370                         mss &= ~511;
1371                 total_rx_bytes += ddp_bytes;
1372                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1373         }
1374 #endif /* IXGBE_FCOE */
1375
1376         rx_ring->total_packets += total_rx_packets;
1377         rx_ring->total_bytes += total_rx_bytes;
1378
1379         return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384  * ixgbe_configure_msix - Configure MSI-X hardware
1385  * @adapter: board private structure
1386  *
1387  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388  * interrupts.
1389  **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392         struct ixgbe_q_vector *q_vector;
1393         int i, j, q_vectors, v_idx, r_idx;
1394         u32 mask;
1395
1396         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398         /*
1399          * Populate the IVAR table and set the ITR values to the
1400          * corresponding register.
1401          */
1402         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403                 q_vector = adapter->q_vector[v_idx];
1404                 /* XXX for_each_set_bit(...) */
1405                 r_idx = find_first_bit(q_vector->rxr_idx,
1406                                        adapter->num_rx_queues);
1407
1408                 for (i = 0; i < q_vector->rxr_count; i++) {
1409                         j = adapter->rx_ring[r_idx]->reg_idx;
1410                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1411                         r_idx = find_next_bit(q_vector->rxr_idx,
1412                                               adapter->num_rx_queues,
1413                                               r_idx + 1);
1414                 }
1415                 r_idx = find_first_bit(q_vector->txr_idx,
1416                                        adapter->num_tx_queues);
1417
1418                 for (i = 0; i < q_vector->txr_count; i++) {
1419                         j = adapter->tx_ring[r_idx]->reg_idx;
1420                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1421                         r_idx = find_next_bit(q_vector->txr_idx,
1422                                               adapter->num_tx_queues,
1423                                               r_idx + 1);
1424                 }
1425
1426                 if (q_vector->txr_count && !q_vector->rxr_count)
1427                         /* tx only */
1428                         q_vector->eitr = adapter->tx_eitr_param;
1429                 else if (q_vector->rxr_count)
1430                         /* rx or mixed */
1431                         q_vector->eitr = adapter->rx_eitr_param;
1432
1433                 ixgbe_write_eitr(q_vector);
1434                 /* If Flow Director is enabled, set interrupt affinity */
1435                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1436                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1437                         /*
1438                          * Allocate the affinity_hint cpumask, assign the mask
1439                          * for this vector, and set our affinity_hint for
1440                          * this irq.
1441                          */
1442                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1443                                                GFP_KERNEL))
1444                                 return;
1445                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1446                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1447                                               q_vector->affinity_mask);
1448                 }
1449         }
1450
1451         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1452                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1453                                v_idx);
1454         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1455                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1456         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1457
1458         /* set up to autoclear timer, and the vectors */
1459         mask = IXGBE_EIMS_ENABLE_MASK;
1460         if (adapter->num_vfs)
1461                 mask &= ~(IXGBE_EIMS_OTHER |
1462                           IXGBE_EIMS_MAILBOX |
1463                           IXGBE_EIMS_LSC);
1464         else
1465                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1466         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1467 }
1468
1469 enum latency_range {
1470         lowest_latency = 0,
1471         low_latency = 1,
1472         bulk_latency = 2,
1473         latency_invalid = 255
1474 };
1475
1476 /**
1477  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1478  * @adapter: pointer to adapter
1479  * @eitr: eitr setting (ints per sec) to give last timeslice
1480  * @itr_setting: current throttle rate in ints/second
1481  * @packets: the number of packets during this measurement interval
1482  * @bytes: the number of bytes during this measurement interval
1483  *
1484  *      Stores a new ITR value based on packets and byte
1485  *      counts during the last interrupt.  The advantage of per interrupt
1486  *      computation is faster updates and more accurate ITR for the current
1487  *      traffic pattern.  Constants in this function were computed
1488  *      based on theoretical maximum wire speed and thresholds were set based
1489  *      on testing data as well as attempting to minimize response time
1490  *      while increasing bulk throughput.
1491  *      this functionality is controlled by the InterruptThrottleRate module
1492  *      parameter (see ixgbe_param.c)
1493  **/
1494 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1495                            u32 eitr, u8 itr_setting,
1496                            int packets, int bytes)
1497 {
1498         unsigned int retval = itr_setting;
1499         u32 timepassed_us;
1500         u64 bytes_perint;
1501
1502         if (packets == 0)
1503                 goto update_itr_done;
1504
1505
1506         /* simple throttlerate management
1507          *    0-20MB/s lowest (100000 ints/s)
1508          *   20-100MB/s low   (20000 ints/s)
1509          *  100-1249MB/s bulk (8000 ints/s)
1510          */
1511         /* what was last interrupt timeslice? */
1512         timepassed_us = 1000000/eitr;
1513         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1514
1515         switch (itr_setting) {
1516         case lowest_latency:
1517                 if (bytes_perint > adapter->eitr_low)
1518                         retval = low_latency;
1519                 break;
1520         case low_latency:
1521                 if (bytes_perint > adapter->eitr_high)
1522                         retval = bulk_latency;
1523                 else if (bytes_perint <= adapter->eitr_low)
1524                         retval = lowest_latency;
1525                 break;
1526         case bulk_latency:
1527                 if (bytes_perint <= adapter->eitr_high)
1528                         retval = low_latency;
1529                 break;
1530         }
1531
1532 update_itr_done:
1533         return retval;
1534 }
1535
1536 /**
1537  * ixgbe_write_eitr - write EITR register in hardware specific way
1538  * @q_vector: structure containing interrupt and ring information
1539  *
1540  * This function is made to be called by ethtool and by the driver
1541  * when it needs to update EITR registers at runtime.  Hardware
1542  * specific quirks/differences are taken care of here.
1543  */
1544 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1545 {
1546         struct ixgbe_adapter *adapter = q_vector->adapter;
1547         struct ixgbe_hw *hw = &adapter->hw;
1548         int v_idx = q_vector->v_idx;
1549         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1550
1551         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1552                 /* must write high and low 16 bits to reset counter */
1553                 itr_reg |= (itr_reg << 16);
1554         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1555                 /*
1556                  * 82599 can support a value of zero, so allow it for
1557                  * max interrupt rate, but there is an errata where it can
1558                  * not be zero with RSC
1559                  */
1560                 if (itr_reg == 8 &&
1561                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1562                         itr_reg = 0;
1563
1564                 /*
1565                  * set the WDIS bit to not clear the timer bits and cause an
1566                  * immediate assertion of the interrupt
1567                  */
1568                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1569         }
1570         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1571 }
1572
1573 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1574 {
1575         struct ixgbe_adapter *adapter = q_vector->adapter;
1576         u32 new_itr;
1577         u8 current_itr, ret_itr;
1578         int i, r_idx;
1579         struct ixgbe_ring *rx_ring, *tx_ring;
1580
1581         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1582         for (i = 0; i < q_vector->txr_count; i++) {
1583                 tx_ring = adapter->tx_ring[r_idx];
1584                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585                                            q_vector->tx_itr,
1586                                            tx_ring->total_packets,
1587                                            tx_ring->total_bytes);
1588                 /* if the result for this queue would decrease interrupt
1589                  * rate for this vector then use that result */
1590                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1591                                     q_vector->tx_itr - 1 : ret_itr);
1592                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1593                                       r_idx + 1);
1594         }
1595
1596         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1597         for (i = 0; i < q_vector->rxr_count; i++) {
1598                 rx_ring = adapter->rx_ring[r_idx];
1599                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1600                                            q_vector->rx_itr,
1601                                            rx_ring->total_packets,
1602                                            rx_ring->total_bytes);
1603                 /* if the result for this queue would decrease interrupt
1604                  * rate for this vector then use that result */
1605                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1606                                     q_vector->rx_itr - 1 : ret_itr);
1607                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1608                                       r_idx + 1);
1609         }
1610
1611         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1612
1613         switch (current_itr) {
1614         /* counts and packets in update_itr are dependent on these numbers */
1615         case lowest_latency:
1616                 new_itr = 100000;
1617                 break;
1618         case low_latency:
1619                 new_itr = 20000; /* aka hwitr = ~200 */
1620                 break;
1621         case bulk_latency:
1622         default:
1623                 new_itr = 8000;
1624                 break;
1625         }
1626
1627         if (new_itr != q_vector->eitr) {
1628                 /* do an exponential smoothing */
1629                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1630
1631                 /* save the algorithm value here, not the smoothed one */
1632                 q_vector->eitr = new_itr;
1633
1634                 ixgbe_write_eitr(q_vector);
1635         }
1636 }
1637
1638 /**
1639  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1640  * @work: pointer to work_struct containing our data
1641  **/
1642 static void ixgbe_check_overtemp_task(struct work_struct *work)
1643 {
1644         struct ixgbe_adapter *adapter = container_of(work,
1645                                                      struct ixgbe_adapter,
1646                                                      check_overtemp_task);
1647         struct ixgbe_hw *hw = &adapter->hw;
1648         u32 eicr = adapter->interrupt_event;
1649
1650         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1651                 return;
1652
1653         switch (hw->device_id) {
1654         case IXGBE_DEV_ID_82599_T3_LOM: {
1655                 u32 autoneg;
1656                 bool link_up = false;
1657
1658                 if (hw->mac.ops.check_link)
1659                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1660
1661                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1662                     (eicr & IXGBE_EICR_LSC))
1663                         /* Check if this is due to overtemp */
1664                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1665                                 break;
1666                 return;
1667         }
1668         default:
1669                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1670                         return;
1671                 break;
1672         }
1673         e_crit(drv,
1674                "Network adapter has been stopped because it has over heated. "
1675                "Restart the computer. If the problem persists, "
1676                "power off the system and replace the adapter\n");
1677         /* write to clear the interrupt */
1678         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1679 }
1680
1681 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1682 {
1683         struct ixgbe_hw *hw = &adapter->hw;
1684
1685         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1686             (eicr & IXGBE_EICR_GPI_SDP1)) {
1687                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1688                 /* write to clear the interrupt */
1689                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1690         }
1691 }
1692
1693 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1694 {
1695         struct ixgbe_hw *hw = &adapter->hw;
1696
1697         if (eicr & IXGBE_EICR_GPI_SDP1) {
1698                 /* Clear the interrupt */
1699                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1700                 schedule_work(&adapter->multispeed_fiber_task);
1701         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1702                 /* Clear the interrupt */
1703                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1704                 schedule_work(&adapter->sfp_config_module_task);
1705         } else {
1706                 /* Interrupt isn't for us... */
1707                 return;
1708         }
1709 }
1710
1711 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1712 {
1713         struct ixgbe_hw *hw = &adapter->hw;
1714
1715         adapter->lsc_int++;
1716         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1717         adapter->link_check_timeout = jiffies;
1718         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1719                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1720                 IXGBE_WRITE_FLUSH(hw);
1721                 schedule_work(&adapter->watchdog_task);
1722         }
1723 }
1724
1725 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1726 {
1727         struct net_device *netdev = data;
1728         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1729         struct ixgbe_hw *hw = &adapter->hw;
1730         u32 eicr;
1731
1732         /*
1733          * Workaround for Silicon errata.  Use clear-by-write instead
1734          * of clear-by-read.  Reading with EICS will return the
1735          * interrupt causes without clearing, which later be done
1736          * with the write to EICR.
1737          */
1738         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1739         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1740
1741         if (eicr & IXGBE_EICR_LSC)
1742                 ixgbe_check_lsc(adapter);
1743
1744         if (eicr & IXGBE_EICR_MAILBOX)
1745                 ixgbe_msg_task(adapter);
1746
1747         if (hw->mac.type == ixgbe_mac_82598EB)
1748                 ixgbe_check_fan_failure(adapter, eicr);
1749
1750         if (hw->mac.type == ixgbe_mac_82599EB) {
1751                 ixgbe_check_sfp_event(adapter, eicr);
1752                 adapter->interrupt_event = eicr;
1753                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1754                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1755                         schedule_work(&adapter->check_overtemp_task);
1756
1757                 /* Handle Flow Director Full threshold interrupt */
1758                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1759                         int i;
1760                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1761                         /* Disable transmits before FDIR Re-initialization */
1762                         netif_tx_stop_all_queues(netdev);
1763                         for (i = 0; i < adapter->num_tx_queues; i++) {
1764                                 struct ixgbe_ring *tx_ring =
1765                                                             adapter->tx_ring[i];
1766                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1767                                                        &tx_ring->reinit_state))
1768                                         schedule_work(&adapter->fdir_reinit_task);
1769                         }
1770                 }
1771         }
1772         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1773                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1774
1775         return IRQ_HANDLED;
1776 }
1777
1778 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1779                                            u64 qmask)
1780 {
1781         u32 mask;
1782
1783         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1784                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1785                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1786         } else {
1787                 mask = (qmask & 0xFFFFFFFF);
1788                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1789                 mask = (qmask >> 32);
1790                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1791         }
1792         /* skip the flush */
1793 }
1794
1795 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1796                                             u64 qmask)
1797 {
1798         u32 mask;
1799
1800         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1801                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1802                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1803         } else {
1804                 mask = (qmask & 0xFFFFFFFF);
1805                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1806                 mask = (qmask >> 32);
1807                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1808         }
1809         /* skip the flush */
1810 }
1811
1812 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1813 {
1814         struct ixgbe_q_vector *q_vector = data;
1815         struct ixgbe_adapter  *adapter = q_vector->adapter;
1816         struct ixgbe_ring     *tx_ring;
1817         int i, r_idx;
1818
1819         if (!q_vector->txr_count)
1820                 return IRQ_HANDLED;
1821
1822         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1823         for (i = 0; i < q_vector->txr_count; i++) {
1824                 tx_ring = adapter->tx_ring[r_idx];
1825                 tx_ring->total_bytes = 0;
1826                 tx_ring->total_packets = 0;
1827                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1828                                       r_idx + 1);
1829         }
1830
1831         /* EIAM disabled interrupts (on this vector) for us */
1832         napi_schedule(&q_vector->napi);
1833
1834         return IRQ_HANDLED;
1835 }
1836
1837 /**
1838  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1839  * @irq: unused
1840  * @data: pointer to our q_vector struct for this interrupt vector
1841  **/
1842 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1843 {
1844         struct ixgbe_q_vector *q_vector = data;
1845         struct ixgbe_adapter  *adapter = q_vector->adapter;
1846         struct ixgbe_ring  *rx_ring;
1847         int r_idx;
1848         int i;
1849
1850         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1851         for (i = 0;  i < q_vector->rxr_count; i++) {
1852                 rx_ring = adapter->rx_ring[r_idx];
1853                 rx_ring->total_bytes = 0;
1854                 rx_ring->total_packets = 0;
1855                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1856                                       r_idx + 1);
1857         }
1858
1859         if (!q_vector->rxr_count)
1860                 return IRQ_HANDLED;
1861
1862         /* disable interrupts on this vector only */
1863         /* EIAM disabled interrupts (on this vector) for us */
1864         napi_schedule(&q_vector->napi);
1865
1866         return IRQ_HANDLED;
1867 }
1868
1869 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1870 {
1871         struct ixgbe_q_vector *q_vector = data;
1872         struct ixgbe_adapter  *adapter = q_vector->adapter;
1873         struct ixgbe_ring  *ring;
1874         int r_idx;
1875         int i;
1876
1877         if (!q_vector->txr_count && !q_vector->rxr_count)
1878                 return IRQ_HANDLED;
1879
1880         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1881         for (i = 0; i < q_vector->txr_count; i++) {
1882                 ring = adapter->tx_ring[r_idx];
1883                 ring->total_bytes = 0;
1884                 ring->total_packets = 0;
1885                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1886                                       r_idx + 1);
1887         }
1888
1889         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1890         for (i = 0; i < q_vector->rxr_count; i++) {
1891                 ring = adapter->rx_ring[r_idx];
1892                 ring->total_bytes = 0;
1893                 ring->total_packets = 0;
1894                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1895                                       r_idx + 1);
1896         }
1897
1898         /* EIAM disabled interrupts (on this vector) for us */
1899         napi_schedule(&q_vector->napi);
1900
1901         return IRQ_HANDLED;
1902 }
1903
1904 /**
1905  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1906  * @napi: napi struct with our devices info in it
1907  * @budget: amount of work driver is allowed to do this pass, in packets
1908  *
1909  * This function is optimized for cleaning one queue only on a single
1910  * q_vector!!!
1911  **/
1912 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1913 {
1914         struct ixgbe_q_vector *q_vector =
1915                                container_of(napi, struct ixgbe_q_vector, napi);
1916         struct ixgbe_adapter *adapter = q_vector->adapter;
1917         struct ixgbe_ring *rx_ring = NULL;
1918         int work_done = 0;
1919         long r_idx;
1920
1921         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1922         rx_ring = adapter->rx_ring[r_idx];
1923 #ifdef CONFIG_IXGBE_DCA
1924         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1925                 ixgbe_update_rx_dca(adapter, rx_ring);
1926 #endif
1927
1928         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1929
1930         /* If all Rx work done, exit the polling mode */
1931         if (work_done < budget) {
1932                 napi_complete(napi);
1933                 if (adapter->rx_itr_setting & 1)
1934                         ixgbe_set_itr_msix(q_vector);
1935                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1936                         ixgbe_irq_enable_queues(adapter,
1937                                                 ((u64)1 << q_vector->v_idx));
1938         }
1939
1940         return work_done;
1941 }
1942
1943 /**
1944  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1945  * @napi: napi struct with our devices info in it
1946  * @budget: amount of work driver is allowed to do this pass, in packets
1947  *
1948  * This function will clean more than one rx queue associated with a
1949  * q_vector.
1950  **/
1951 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1952 {
1953         struct ixgbe_q_vector *q_vector =
1954                                container_of(napi, struct ixgbe_q_vector, napi);
1955         struct ixgbe_adapter *adapter = q_vector->adapter;
1956         struct ixgbe_ring *ring = NULL;
1957         int work_done = 0, i;
1958         long r_idx;
1959         bool tx_clean_complete = true;
1960
1961         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1962         for (i = 0; i < q_vector->txr_count; i++) {
1963                 ring = adapter->tx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966                         ixgbe_update_tx_dca(adapter, ring);
1967 #endif
1968                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1969                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1970                                       r_idx + 1);
1971         }
1972
1973         /* attempt to distribute budget to each queue fairly, but don't allow
1974          * the budget to go below 1 because we'll exit polling */
1975         budget /= (q_vector->rxr_count ?: 1);
1976         budget = max(budget, 1);
1977         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1978         for (i = 0; i < q_vector->rxr_count; i++) {
1979                 ring = adapter->rx_ring[r_idx];
1980 #ifdef CONFIG_IXGBE_DCA
1981                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1982                         ixgbe_update_rx_dca(adapter, ring);
1983 #endif
1984                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1985                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1986                                       r_idx + 1);
1987         }
1988
1989         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1990         ring = adapter->rx_ring[r_idx];
1991         /* If all Rx work done, exit the polling mode */
1992         if (work_done < budget) {
1993                 napi_complete(napi);
1994                 if (adapter->rx_itr_setting & 1)
1995                         ixgbe_set_itr_msix(q_vector);
1996                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1997                         ixgbe_irq_enable_queues(adapter,
1998                                                 ((u64)1 << q_vector->v_idx));
1999                 return 0;
2000         }
2001
2002         return work_done;
2003 }
2004
2005 /**
2006  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2007  * @napi: napi struct with our devices info in it
2008  * @budget: amount of work driver is allowed to do this pass, in packets
2009  *
2010  * This function is optimized for cleaning one queue only on a single
2011  * q_vector!!!
2012  **/
2013 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2014 {
2015         struct ixgbe_q_vector *q_vector =
2016                                container_of(napi, struct ixgbe_q_vector, napi);
2017         struct ixgbe_adapter *adapter = q_vector->adapter;
2018         struct ixgbe_ring *tx_ring = NULL;
2019         int work_done = 0;
2020         long r_idx;
2021
2022         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2023         tx_ring = adapter->tx_ring[r_idx];
2024 #ifdef CONFIG_IXGBE_DCA
2025         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2026                 ixgbe_update_tx_dca(adapter, tx_ring);
2027 #endif
2028
2029         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2030                 work_done = budget;
2031
2032         /* If all Tx work done, exit the polling mode */
2033         if (work_done < budget) {
2034                 napi_complete(napi);
2035                 if (adapter->tx_itr_setting & 1)
2036                         ixgbe_set_itr_msix(q_vector);
2037                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2038                         ixgbe_irq_enable_queues(adapter,
2039                                                 ((u64)1 << q_vector->v_idx));
2040         }
2041
2042         return work_done;
2043 }
2044
2045 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2046                                      int r_idx)
2047 {
2048         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2049
2050         set_bit(r_idx, q_vector->rxr_idx);
2051         q_vector->rxr_count++;
2052 }
2053
2054 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2055                                      int t_idx)
2056 {
2057         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2058
2059         set_bit(t_idx, q_vector->txr_idx);
2060         q_vector->txr_count++;
2061 }
2062
2063 /**
2064  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2065  * @adapter: board private structure to initialize
2066  * @vectors: allotted vector count for descriptor rings
2067  *
2068  * This function maps descriptor rings to the queue-specific vectors
2069  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2070  * one vector per ring/queue, but on a constrained vector budget, we
2071  * group the rings as "efficiently" as possible.  You would add new
2072  * mapping configurations in here.
2073  **/
2074 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2075                                       int vectors)
2076 {
2077         int v_start = 0;
2078         int rxr_idx = 0, txr_idx = 0;
2079         int rxr_remaining = adapter->num_rx_queues;
2080         int txr_remaining = adapter->num_tx_queues;
2081         int i, j;
2082         int rqpv, tqpv;
2083         int err = 0;
2084
2085         /* No mapping required if MSI-X is disabled. */
2086         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2087                 goto out;
2088
2089         /*
2090          * The ideal configuration...
2091          * We have enough vectors to map one per queue.
2092          */
2093         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2094                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2095                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2096
2097                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2098                         map_vector_to_txq(adapter, v_start, txr_idx);
2099
2100                 goto out;
2101         }
2102
2103         /*
2104          * If we don't have enough vectors for a 1-to-1
2105          * mapping, we'll have to group them so there are
2106          * multiple queues per vector.
2107          */
2108         /* Re-adjusting *qpv takes care of the remainder. */
2109         for (i = v_start; i < vectors; i++) {
2110                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2111                 for (j = 0; j < rqpv; j++) {
2112                         map_vector_to_rxq(adapter, i, rxr_idx);
2113                         rxr_idx++;
2114                         rxr_remaining--;
2115                 }
2116         }
2117         for (i = v_start; i < vectors; i++) {
2118                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2119                 for (j = 0; j < tqpv; j++) {
2120                         map_vector_to_txq(adapter, i, txr_idx);
2121                         txr_idx++;
2122                         txr_remaining--;
2123                 }
2124         }
2125
2126 out:
2127         return err;
2128 }
2129
2130 /**
2131  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2132  * @adapter: board private structure
2133  *
2134  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2135  * interrupts from the kernel.
2136  **/
2137 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2138 {
2139         struct net_device *netdev = adapter->netdev;
2140         irqreturn_t (*handler)(int, void *);
2141         int i, vector, q_vectors, err;
2142         int ri = 0, ti = 0;
2143
2144         /* Decrement for Other and TCP Timer vectors */
2145         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2146
2147         /* Map the Tx/Rx rings to the vectors we were allotted. */
2148         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2149         if (err)
2150                 goto out;
2151
2152 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2153                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2154                          &ixgbe_msix_clean_many)
2155         for (vector = 0; vector < q_vectors; vector++) {
2156                 handler = SET_HANDLER(adapter->q_vector[vector]);
2157
2158                 if (handler == &ixgbe_msix_clean_rx) {
2159                         sprintf(adapter->name[vector], "%s-%s-%d",
2160                                 netdev->name, "rx", ri++);
2161                 } else if (handler == &ixgbe_msix_clean_tx) {
2162                         sprintf(adapter->name[vector], "%s-%s-%d",
2163                                 netdev->name, "tx", ti++);
2164                 } else
2165                         sprintf(adapter->name[vector], "%s-%s-%d",
2166                                 netdev->name, "TxRx", vector);
2167
2168                 err = request_irq(adapter->msix_entries[vector].vector,
2169                                   handler, 0, adapter->name[vector],
2170                                   adapter->q_vector[vector]);
2171                 if (err) {
2172                         e_err(probe, "request_irq failed for MSIX interrupt "
2173                               "Error: %d\n", err);
2174                         goto free_queue_irqs;
2175                 }
2176         }
2177
2178         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2179         err = request_irq(adapter->msix_entries[vector].vector,
2180                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2181         if (err) {
2182                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2183                 goto free_queue_irqs;
2184         }
2185
2186         return 0;
2187
2188 free_queue_irqs:
2189         for (i = vector - 1; i >= 0; i--)
2190                 free_irq(adapter->msix_entries[--vector].vector,
2191                          adapter->q_vector[i]);
2192         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2193         pci_disable_msix(adapter->pdev);
2194         kfree(adapter->msix_entries);
2195         adapter->msix_entries = NULL;
2196 out:
2197         return err;
2198 }
2199
2200 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2201 {
2202         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2203         u8 current_itr;
2204         u32 new_itr = q_vector->eitr;
2205         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2206         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2207
2208         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2209                                             q_vector->tx_itr,
2210                                             tx_ring->total_packets,
2211                                             tx_ring->total_bytes);
2212         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2213                                             q_vector->rx_itr,
2214                                             rx_ring->total_packets,
2215                                             rx_ring->total_bytes);
2216
2217         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2218
2219         switch (current_itr) {
2220         /* counts and packets in update_itr are dependent on these numbers */
2221         case lowest_latency:
2222                 new_itr = 100000;
2223                 break;
2224         case low_latency:
2225                 new_itr = 20000; /* aka hwitr = ~200 */
2226                 break;
2227         case bulk_latency:
2228                 new_itr = 8000;
2229                 break;
2230         default:
2231                 break;
2232         }
2233
2234         if (new_itr != q_vector->eitr) {
2235                 /* do an exponential smoothing */
2236                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2237
2238                 /* save the algorithm value here, not the smoothed one */
2239                 q_vector->eitr = new_itr;
2240
2241                 ixgbe_write_eitr(q_vector);
2242         }
2243 }
2244
2245 /**
2246  * ixgbe_irq_enable - Enable default interrupt generation settings
2247  * @adapter: board private structure
2248  **/
2249 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2250                                     bool flush)
2251 {
2252         u32 mask;
2253
2254         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2255         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2256                 mask |= IXGBE_EIMS_GPI_SDP0;
2257         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2258                 mask |= IXGBE_EIMS_GPI_SDP1;
2259         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2260                 mask |= IXGBE_EIMS_ECC;
2261                 mask |= IXGBE_EIMS_GPI_SDP1;
2262                 mask |= IXGBE_EIMS_GPI_SDP2;
2263                 if (adapter->num_vfs)
2264                         mask |= IXGBE_EIMS_MAILBOX;
2265         }
2266         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2267             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2268                 mask |= IXGBE_EIMS_FLOW_DIR;
2269
2270         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2271         if (queues)
2272                 ixgbe_irq_enable_queues(adapter, ~0);
2273         if (flush)
2274                 IXGBE_WRITE_FLUSH(&adapter->hw);
2275
2276         if (adapter->num_vfs > 32) {
2277                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2278                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2279         }
2280 }
2281
2282 /**
2283  * ixgbe_intr - legacy mode Interrupt Handler
2284  * @irq: interrupt number
2285  * @data: pointer to a network interface device structure
2286  **/
2287 static irqreturn_t ixgbe_intr(int irq, void *data)
2288 {
2289         struct net_device *netdev = data;
2290         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2291         struct ixgbe_hw *hw = &adapter->hw;
2292         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2293         u32 eicr;
2294
2295         /*
2296          * Workaround for silicon errata on 82598.  Mask the interrupts
2297          * before the read of EICR.
2298          */
2299         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2300
2301         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2302          * therefore no explict interrupt disable is necessary */
2303         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2304         if (!eicr) {
2305                 /*
2306                  * shared interrupt alert!
2307                  * make sure interrupts are enabled because the read will
2308                  * have disabled interrupts due to EIAM
2309                  * finish the workaround of silicon errata on 82598.  Unmask
2310                  * the interrupt that we masked before the EICR read.
2311                  */
2312                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2313                         ixgbe_irq_enable(adapter, true, true);
2314                 return IRQ_NONE;        /* Not our interrupt */
2315         }
2316
2317         if (eicr & IXGBE_EICR_LSC)
2318                 ixgbe_check_lsc(adapter);
2319
2320         if (hw->mac.type == ixgbe_mac_82599EB)
2321                 ixgbe_check_sfp_event(adapter, eicr);
2322
2323         ixgbe_check_fan_failure(adapter, eicr);
2324         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2325             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2326                 schedule_work(&adapter->check_overtemp_task);
2327
2328         if (napi_schedule_prep(&(q_vector->napi))) {
2329                 adapter->tx_ring[0]->total_packets = 0;
2330                 adapter->tx_ring[0]->total_bytes = 0;
2331                 adapter->rx_ring[0]->total_packets = 0;
2332                 adapter->rx_ring[0]->total_bytes = 0;
2333                 /* would disable interrupts here but EIAM disabled it */
2334                 __napi_schedule(&(q_vector->napi));
2335         }
2336
2337         /*
2338          * re-enable link(maybe) and non-queue interrupts, no flush.
2339          * ixgbe_poll will re-enable the queue interrupts
2340          */
2341
2342         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2343                 ixgbe_irq_enable(adapter, false, false);
2344
2345         return IRQ_HANDLED;
2346 }
2347
2348 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2349 {
2350         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2351
2352         for (i = 0; i < q_vectors; i++) {
2353                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2354                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2355                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2356                 q_vector->rxr_count = 0;
2357                 q_vector->txr_count = 0;
2358         }
2359 }
2360
2361 /**
2362  * ixgbe_request_irq - initialize interrupts
2363  * @adapter: board private structure
2364  *
2365  * Attempts to configure interrupts using the best available
2366  * capabilities of the hardware and kernel.
2367  **/
2368 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2369 {
2370         struct net_device *netdev = adapter->netdev;
2371         int err;
2372
2373         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2374                 err = ixgbe_request_msix_irqs(adapter);
2375         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2376                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2377                                   netdev->name, netdev);
2378         } else {
2379                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2380                                   netdev->name, netdev);
2381         }
2382
2383         if (err)
2384                 e_err(probe, "request_irq failed, Error %d\n", err);
2385
2386         return err;
2387 }
2388
2389 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2390 {
2391         struct net_device *netdev = adapter->netdev;
2392
2393         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2394                 int i, q_vectors;
2395
2396                 q_vectors = adapter->num_msix_vectors;
2397
2398                 i = q_vectors - 1;
2399                 free_irq(adapter->msix_entries[i].vector, netdev);
2400
2401                 i--;
2402                 for (; i >= 0; i--) {
2403                         free_irq(adapter->msix_entries[i].vector,
2404                                  adapter->q_vector[i]);
2405                 }
2406
2407                 ixgbe_reset_q_vectors(adapter);
2408         } else {
2409                 free_irq(adapter->pdev->irq, netdev);
2410         }
2411 }
2412
2413 /**
2414  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2415  * @adapter: board private structure
2416  **/
2417 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2418 {
2419         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2420                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2421         } else {
2422                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2423                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2424                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2425                 if (adapter->num_vfs > 32)
2426                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2427         }
2428         IXGBE_WRITE_FLUSH(&adapter->hw);
2429         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2430                 int i;
2431                 for (i = 0; i < adapter->num_msix_vectors; i++)
2432                         synchronize_irq(adapter->msix_entries[i].vector);
2433         } else {
2434                 synchronize_irq(adapter->pdev->irq);
2435         }
2436 }
2437
2438 /**
2439  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2440  *
2441  **/
2442 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2443 {
2444         struct ixgbe_hw *hw = &adapter->hw;
2445
2446         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2447                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2448
2449         ixgbe_set_ivar(adapter, 0, 0, 0);
2450         ixgbe_set_ivar(adapter, 1, 0, 0);
2451
2452         map_vector_to_rxq(adapter, 0, 0);
2453         map_vector_to_txq(adapter, 0, 0);
2454
2455         e_info(hw, "Legacy interrupt IVAR setup done\n");
2456 }
2457
2458 /**
2459  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2460  * @adapter: board private structure
2461  * @ring: structure containing ring specific data
2462  *
2463  * Configure the Tx descriptor ring after a reset.
2464  **/
2465 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2466                              struct ixgbe_ring *ring)
2467 {
2468         struct ixgbe_hw *hw = &adapter->hw;
2469         u64 tdba = ring->dma;
2470         int wait_loop = 10;
2471         u32 txdctl;
2472         u16 reg_idx = ring->reg_idx;
2473
2474         /* disable queue to avoid issues while updating state */
2475         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2476         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2477                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2478         IXGBE_WRITE_FLUSH(hw);
2479
2480         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2481                         (tdba & DMA_BIT_MASK(32)));
2482         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2483         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2484                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2485         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2486         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2487         ring->head = IXGBE_TDH(reg_idx);
2488         ring->tail = IXGBE_TDT(reg_idx);
2489
2490         /* configure fetching thresholds */
2491         if (adapter->rx_itr_setting == 0) {
2492                 /* cannot set wthresh when itr==0 */
2493                 txdctl &= ~0x007F0000;
2494         } else {
2495                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2496                 txdctl |= (8 << 16);
2497         }
2498         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2499                 /* PThresh workaround for Tx hang with DFP enabled. */
2500                 txdctl |= 32;
2501         }
2502
2503         /* reinitialize flowdirector state */
2504         set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2505
2506         /* enable queue */
2507         txdctl |= IXGBE_TXDCTL_ENABLE;
2508         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2509
2510         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2511         if (hw->mac.type == ixgbe_mac_82598EB &&
2512             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2513                 return;
2514
2515         /* poll to verify queue is enabled */
2516         do {
2517                 msleep(1);
2518                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2519         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2520         if (!wait_loop)
2521                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2522 }
2523
2524 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2525 {
2526         struct ixgbe_hw *hw = &adapter->hw;
2527         u32 rttdcs;
2528         u32 mask;
2529
2530         if (hw->mac.type == ixgbe_mac_82598EB)
2531                 return;
2532
2533         /* disable the arbiter while setting MTQC */
2534         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2535         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2536         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2537
2538         /* set transmit pool layout */
2539         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2540         switch (adapter->flags & mask) {
2541
2542         case (IXGBE_FLAG_SRIOV_ENABLED):
2543                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2544                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2545                 break;
2546
2547         case (IXGBE_FLAG_DCB_ENABLED):
2548                 /* We enable 8 traffic classes, DCB only */
2549                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2550                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2551                 break;
2552
2553         default:
2554                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2555                 break;
2556         }
2557
2558         /* re-enable the arbiter */
2559         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2560         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2561 }
2562
2563 /**
2564  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2565  * @adapter: board private structure
2566  *
2567  * Configure the Tx unit of the MAC after a reset.
2568  **/
2569 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2570 {
2571         struct ixgbe_hw *hw = &adapter->hw;
2572         u32 dmatxctl;
2573         u32 i;
2574
2575         ixgbe_setup_mtqc(adapter);
2576
2577         if (hw->mac.type != ixgbe_mac_82598EB) {
2578                 /* DMATXCTL.EN must be before Tx queues are enabled */
2579                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2580                 dmatxctl |= IXGBE_DMATXCTL_TE;
2581                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2582         }
2583
2584         /* Setup the HW Tx Head and Tail descriptor pointers */
2585         for (i = 0; i < adapter->num_tx_queues; i++)
2586                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2587 }
2588
2589 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2590
2591 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2592                                    struct ixgbe_ring *rx_ring)
2593 {
2594         u32 srrctl;
2595         int index;
2596         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2597
2598         index = rx_ring->reg_idx;
2599         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2600                 unsigned long mask;
2601                 mask = (unsigned long) feature[RING_F_RSS].mask;
2602                 index = index & mask;
2603         }
2604         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2605
2606         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2607         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2608         if (adapter->num_vfs)
2609                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2610
2611         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2612                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2613
2614         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2615 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2616                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2617 #else
2618                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2619 #endif
2620                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2621         } else {
2622                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2623                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2624                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2625         }
2626
2627         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2628 }
2629
2630 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2631 {
2632         struct ixgbe_hw *hw = &adapter->hw;
2633         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2634                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2635                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2636         u32 mrqc = 0, reta = 0;
2637         u32 rxcsum;
2638         int i, j;
2639         int mask;
2640
2641         /* Fill out hash function seeds */
2642         for (i = 0; i < 10; i++)
2643                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2644
2645         /* Fill out redirection table */
2646         for (i = 0, j = 0; i < 128; i++, j++) {
2647                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2648                         j = 0;
2649                 /* reta = 4-byte sliding window of
2650                  * 0x00..(indices-1)(indices-1)00..etc. */
2651                 reta = (reta << 8) | (j * 0x11);
2652                 if ((i & 3) == 3)
2653                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2654         }
2655
2656         /* Disable indicating checksum in descriptor, enables RSS hash */
2657         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2658         rxcsum |= IXGBE_RXCSUM_PCSD;
2659         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2660
2661         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2662                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2663         else
2664                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2665 #ifdef CONFIG_IXGBE_DCB
2666                                          | IXGBE_FLAG_DCB_ENABLED
2667 #endif
2668                                          | IXGBE_FLAG_SRIOV_ENABLED
2669                                         );
2670
2671         switch (mask) {
2672         case (IXGBE_FLAG_RSS_ENABLED):
2673                 mrqc = IXGBE_MRQC_RSSEN;
2674                 break;
2675         case (IXGBE_FLAG_SRIOV_ENABLED):
2676                 mrqc = IXGBE_MRQC_VMDQEN;
2677                 break;
2678 #ifdef CONFIG_IXGBE_DCB
2679         case (IXGBE_FLAG_DCB_ENABLED):
2680                 mrqc = IXGBE_MRQC_RT8TCEN;
2681                 break;
2682 #endif /* CONFIG_IXGBE_DCB */
2683         default:
2684                 break;
2685         }
2686
2687         /* Perform hash on these packet types */
2688         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2689               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2690               | IXGBE_MRQC_RSS_FIELD_IPV6
2691               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2692
2693         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2694 }
2695
2696 /**
2697  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2698  * @adapter:    address of board private structure
2699  * @index:      index of ring to set
2700  **/
2701 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2702                                    struct ixgbe_ring *ring)
2703 {
2704         struct ixgbe_hw *hw = &adapter->hw;
2705         u32 rscctrl;
2706         int rx_buf_len;
2707         u16 reg_idx = ring->reg_idx;
2708
2709         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2710                 return;
2711
2712         rx_buf_len = ring->rx_buf_len;
2713         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2714         rscctrl |= IXGBE_RSCCTL_RSCEN;
2715         /*
2716          * we must limit the number of descriptors so that the
2717          * total size of max desc * buf_len is not greater
2718          * than 65535
2719          */
2720         if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2721 #if (MAX_SKB_FRAGS > 16)
2722                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2723 #elif (MAX_SKB_FRAGS > 8)
2724                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2725 #elif (MAX_SKB_FRAGS > 4)
2726                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2727 #else
2728                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2729 #endif
2730         } else {
2731                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2732                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2733                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2734                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2735                 else
2736                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2737         }
2738         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2739 }
2740
2741 /**
2742  *  ixgbe_set_uta - Set unicast filter table address
2743  *  @adapter: board private structure
2744  *
2745  *  The unicast table address is a register array of 32-bit registers.
2746  *  The table is meant to be used in a way similar to how the MTA is used
2747  *  however due to certain limitations in the hardware it is necessary to
2748  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2749  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2750  **/
2751 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2752 {
2753         struct ixgbe_hw *hw = &adapter->hw;
2754         int i;
2755
2756         /* The UTA table only exists on 82599 hardware and newer */
2757         if (hw->mac.type < ixgbe_mac_82599EB)
2758                 return;
2759
2760         /* we only need to do this if VMDq is enabled */
2761         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2762                 return;
2763
2764         for (i = 0; i < 128; i++)
2765                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2766 }
2767
2768 #define IXGBE_MAX_RX_DESC_POLL 10
2769 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2770                                        struct ixgbe_ring *ring)
2771 {
2772         struct ixgbe_hw *hw = &adapter->hw;
2773         int reg_idx = ring->reg_idx;
2774         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2775         u32 rxdctl;
2776
2777         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2778         if (hw->mac.type == ixgbe_mac_82598EB &&
2779             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2780                 return;
2781
2782         do {
2783                 msleep(1);
2784                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2785         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2786
2787         if (!wait_loop) {
2788                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2789                       "the polling period\n", reg_idx);
2790         }
2791 }
2792
2793 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2794                              struct ixgbe_ring *ring)
2795 {
2796         struct ixgbe_hw *hw = &adapter->hw;
2797         u64 rdba = ring->dma;
2798         u32 rxdctl;
2799         u16 reg_idx = ring->reg_idx;
2800
2801         /* disable queue to avoid issues while updating state */
2802         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2803         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2804                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2805         IXGBE_WRITE_FLUSH(hw);
2806
2807         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2808         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2809         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2810                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2811         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2812         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2813         ring->head = IXGBE_RDH(reg_idx);
2814         ring->tail = IXGBE_RDT(reg_idx);
2815
2816         ixgbe_configure_srrctl(adapter, ring);
2817         ixgbe_configure_rscctl(adapter, ring);
2818
2819         if (hw->mac.type == ixgbe_mac_82598EB) {
2820                 /*
2821                  * enable cache line friendly hardware writes:
2822                  * PTHRESH=32 descriptors (half the internal cache),
2823                  * this also removes ugly rx_no_buffer_count increment
2824                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2825                  * WTHRESH=8 burst writeback up to two cache lines
2826                  */
2827                 rxdctl &= ~0x3FFFFF;
2828                 rxdctl |=  0x080420;
2829         }
2830
2831         /* enable receive descriptor ring */
2832         rxdctl |= IXGBE_RXDCTL_ENABLE;
2833         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2834
2835         ixgbe_rx_desc_queue_enable(adapter, ring);
2836         ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
2837 }
2838
2839 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2840 {
2841         struct ixgbe_hw *hw = &adapter->hw;
2842         int p;
2843
2844         /* PSRTYPE must be initialized in non 82598 adapters */
2845         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2846                       IXGBE_PSRTYPE_UDPHDR |
2847                       IXGBE_PSRTYPE_IPV4HDR |
2848                       IXGBE_PSRTYPE_L2HDR |
2849                       IXGBE_PSRTYPE_IPV6HDR;
2850
2851         if (hw->mac.type == ixgbe_mac_82598EB)
2852                 return;
2853
2854         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2855                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2856
2857         for (p = 0; p < adapter->num_rx_pools; p++)
2858                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2859                                 psrtype);
2860 }
2861
2862 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2863 {
2864         struct ixgbe_hw *hw = &adapter->hw;
2865         u32 gcr_ext;
2866         u32 vt_reg_bits;
2867         u32 reg_offset, vf_shift;
2868         u32 vmdctl;
2869
2870         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2871                 return;
2872
2873         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2874         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2875         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2876         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2877
2878         vf_shift = adapter->num_vfs % 32;
2879         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2880
2881         /* Enable only the PF's pool for Tx/Rx */
2882         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2883         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2884         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2885         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2886         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2887
2888         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2889         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2890
2891         /*
2892          * Set up VF register offsets for selected VT Mode,
2893          * i.e. 32 or 64 VFs for SR-IOV
2894          */
2895         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2896         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2897         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2898         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2899
2900         /* enable Tx loopback for VF/PF communication */
2901         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2902 }
2903
2904 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2905 {
2906         struct ixgbe_hw *hw = &adapter->hw;
2907         struct net_device *netdev = adapter->netdev;
2908         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2909         int rx_buf_len;
2910         struct ixgbe_ring *rx_ring;
2911         int i;
2912         u32 mhadd, hlreg0;
2913
2914         /* Decide whether to use packet split mode or not */
2915         /* Do not use packet split if we're in SR-IOV Mode */
2916         if (!adapter->num_vfs)
2917                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2918
2919         /* Set the RX buffer length according to the mode */
2920         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2921                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2922         } else {
2923                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2924                     (netdev->mtu <= ETH_DATA_LEN))
2925                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2926                 else
2927                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2928         }
2929
2930 #ifdef IXGBE_FCOE
2931         /* adjust max frame to be able to do baby jumbo for FCoE */
2932         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2933             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2934                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2935
2936 #endif /* IXGBE_FCOE */
2937         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2938         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2939                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2940                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2941
2942                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2943         }
2944
2945         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2946         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2947         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2948         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2949
2950         /*
2951          * Setup the HW Rx Head and Tail Descriptor Pointers and
2952          * the Base and Length of the Rx Descriptor Ring
2953          */
2954         for (i = 0; i < adapter->num_rx_queues; i++) {
2955                 rx_ring = adapter->rx_ring[i];
2956                 rx_ring->rx_buf_len = rx_buf_len;
2957
2958                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2959                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2960                 else
2961                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2962
2963 #ifdef IXGBE_FCOE
2964                 if (netdev->features & NETIF_F_FCOE_MTU) {
2965                         struct ixgbe_ring_feature *f;
2966                         f = &adapter->ring_feature[RING_F_FCOE];
2967                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2968                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2969                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2970                                         rx_ring->rx_buf_len =
2971                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2972                         }
2973                 }
2974 #endif /* IXGBE_FCOE */
2975         }
2976
2977 }
2978
2979 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2980 {
2981         struct ixgbe_hw *hw = &adapter->hw;
2982         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2983
2984         switch (hw->mac.type) {
2985         case ixgbe_mac_82598EB:
2986                 /*
2987                  * For VMDq support of different descriptor types or
2988                  * buffer sizes through the use of multiple SRRCTL
2989                  * registers, RDRXCTL.MVMEN must be set to 1
2990                  *
2991                  * also, the manual doesn't mention it clearly but DCA hints
2992                  * will only use queue 0's tags unless this bit is set.  Side
2993                  * effects of setting this bit are only that SRRCTL must be
2994                  * fully programmed [0..15]
2995                  */
2996                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2997                 break;
2998         case ixgbe_mac_82599EB:
2999                 /* Disable RSC for ACK packets */
3000                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3001                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3002                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3003                 /* hardware requires some bits to be set by default */
3004                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3005                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3006                 break;
3007         default:
3008                 /* We should do nothing since we don't know this hardware */
3009                 return;
3010         }
3011
3012         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3013 }
3014
3015 /**
3016  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3017  * @adapter: board private structure
3018  *
3019  * Configure the Rx unit of the MAC after a reset.
3020  **/
3021 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3022 {
3023         struct ixgbe_hw *hw = &adapter->hw;
3024         int i;
3025         u32 rxctrl;
3026
3027         /* disable receives while setting up the descriptors */
3028         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3029         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3030
3031         ixgbe_setup_psrtype(adapter);
3032         ixgbe_setup_rdrxctl(adapter);
3033
3034         /* Program registers for the distribution of queues */
3035         ixgbe_setup_mrqc(adapter);
3036
3037         ixgbe_set_uta(adapter);
3038
3039         /* set_rx_buffer_len must be called before ring initialization */
3040         ixgbe_set_rx_buffer_len(adapter);
3041
3042         /*
3043          * Setup the HW Rx Head and Tail Descriptor Pointers and
3044          * the Base and Length of the Rx Descriptor Ring
3045          */
3046         for (i = 0; i < adapter->num_rx_queues; i++)
3047                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3048
3049         /* disable drop enable for 82598 parts */
3050         if (hw->mac.type == ixgbe_mac_82598EB)
3051                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3052
3053         /* enable all receives */
3054         rxctrl |= IXGBE_RXCTRL_RXEN;
3055         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3056 }
3057
3058 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3059 {
3060         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3061         struct ixgbe_hw *hw = &adapter->hw;
3062         int pool_ndx = adapter->num_vfs;
3063
3064         /* add VID to filter table */
3065         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3066         set_bit(vid, adapter->active_vlans);
3067 }
3068
3069 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3070 {
3071         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3072         struct ixgbe_hw *hw = &adapter->hw;
3073         int pool_ndx = adapter->num_vfs;
3074
3075         /* remove VID from filter table */
3076         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3077         clear_bit(vid, adapter->active_vlans);
3078 }
3079
3080 /**
3081  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3082  * @adapter: driver data
3083  */
3084 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3085 {
3086         struct ixgbe_hw *hw = &adapter->hw;
3087         u32 vlnctrl;
3088
3089         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3090         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3091         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3092 }
3093
3094 /**
3095  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3096  * @adapter: driver data
3097  */
3098 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3099 {
3100         struct ixgbe_hw *hw = &adapter->hw;
3101         u32 vlnctrl;
3102
3103         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3104         vlnctrl |= IXGBE_VLNCTRL_VFE;
3105         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3106         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3107 }
3108
3109 /**
3110  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3111  * @adapter: driver data
3112  */
3113 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3114 {
3115         struct ixgbe_hw *hw = &adapter->hw;
3116         u32 vlnctrl;
3117         int i, j;
3118
3119         switch (hw->mac.type) {
3120         case ixgbe_mac_82598EB:
3121                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3122                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3123                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3124                 break;
3125         case ixgbe_mac_82599EB:
3126                 for (i = 0; i < adapter->num_rx_queues; i++) {
3127                         j = adapter->rx_ring[i]->reg_idx;
3128                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3129                         vlnctrl &=&nb