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1 /*
2  * Copyright (C) 1999 - 2010 Intel Corporation.
3  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
4  *
5  * This code was derived from the Intel e1000e Linux driver.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
19  */
20
21 #include "pch_gbe.h"
22 #include "pch_gbe_api.h"
23
24 #define DRV_VERSION     "1.00"
25 const char pch_driver_version[] = DRV_VERSION;
26
27 #define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
28 #define PCH_GBE_MAR_ENTRIES             16
29 #define PCH_GBE_SHORT_PKT               64
30 #define DSC_INIT16                      0xC000
31 #define PCH_GBE_DMA_ALIGN               0
32 #define PCH_GBE_WATCHDOG_PERIOD         (1 * HZ)        /* watchdog time */
33 #define PCH_GBE_COPYBREAK_DEFAULT       256
34 #define PCH_GBE_PCI_BAR                 1
35
36 #define PCH_GBE_TX_WEIGHT         64
37 #define PCH_GBE_RX_WEIGHT         64
38 #define PCH_GBE_RX_BUFFER_WRITE   16
39
40 /* Initialize the wake-on-LAN settings */
41 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
42
43 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
44         PCH_GBE_CHIP_TYPE_INTERNAL | \
45         PCH_GBE_RGMII_MODE_RGMII   | \
46         PCH_GBE_CRS_SEL              \
47         )
48
49 /* Ethertype field values */
50 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
51 #define PCH_GBE_FRAME_SIZE_2048         2048
52 #define PCH_GBE_FRAME_SIZE_4096         4096
53 #define PCH_GBE_FRAME_SIZE_8192         8192
54
55 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
56 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
57 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
58 #define PCH_GBE_DESC_UNUSED(R) \
59         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60         (R)->next_to_clean - (R)->next_to_use - 1)
61
62 /* Pause packet value */
63 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
64 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
65 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
66 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
67
68 #define PCH_GBE_ETH_ALEN            6
69
70 /* This defines the bits that are set in the Interrupt Mask
71  * Set/Read Register.  Each bit is documented below:
72  *   o RXT0   = Receiver Timer Interrupt (ring 0)
73  *   o TXDW   = Transmit Descriptor Written Back
74  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
75  *   o RXSEQ  = Receive Sequence Error
76  *   o LSC    = Link Status Change
77  */
78 #define PCH_GBE_INT_ENABLE_MASK ( \
79         PCH_GBE_INT_RX_DMA_CMPLT |    \
80         PCH_GBE_INT_RX_DSC_EMP   |    \
81         PCH_GBE_INT_WOL_DET      |    \
82         PCH_GBE_INT_TX_CMPLT          \
83         )
84
85
86 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
87
88 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
89 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
90                                int data);
91 /**
92  * pch_gbe_mac_read_mac_addr - Read MAC address
93  * @hw:             Pointer to the HW structure
94  * Returns
95  *      0:                      Successful.
96  */
97 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
98 {
99         u32  adr1a, adr1b;
100
101         adr1a = ioread32(&hw->reg->mac_adr[0].high);
102         adr1b = ioread32(&hw->reg->mac_adr[0].low);
103
104         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
105         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
106         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
107         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
108         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
109         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
110
111         pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
112         return 0;
113 }
114
115 /**
116  * pch_gbe_wait_clr_bit - Wait to clear a bit
117  * @reg:        Pointer of register
118  * @busy:       Busy bit
119  */
120 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
121 {
122         u32 tmp;
123         /* wait busy */
124         tmp = 1000;
125         while ((ioread32(reg) & bit) && --tmp)
126                 cpu_relax();
127         if (!tmp)
128                 pr_err("Error: busy bit is not cleared\n");
129 }
130 /**
131  * pch_gbe_mac_mar_set - Set MAC address register
132  * @hw:     Pointer to the HW structure
133  * @addr:   Pointer to the MAC address
134  * @index:  MAC address array register
135  */
136 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
137 {
138         u32 mar_low, mar_high, adrmask;
139
140         pr_debug("index : 0x%x\n", index);
141
142         /*
143          * HW expects these in little endian so we reverse the byte order
144          * from network order (big endian) to little endian
145          */
146         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
147                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
148         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
149         /* Stop the MAC Address of index. */
150         adrmask = ioread32(&hw->reg->ADDR_MASK);
151         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
152         /* wait busy */
153         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
154         /* Set the MAC address to the MAC address 1A/1B register */
155         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
156         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
157         /* Start the MAC address of index */
158         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
159         /* wait busy */
160         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
161 }
162
163 /**
164  * pch_gbe_mac_reset_hw - Reset hardware
165  * @hw: Pointer to the HW structure
166  */
167 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
168 {
169         /* Read the MAC address. and store to the private data */
170         pch_gbe_mac_read_mac_addr(hw);
171         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
172 #ifdef PCH_GBE_MAC_IFOP_RGMII
173         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
174 #endif
175         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
176         /* Setup the receive address */
177         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
178         return;
179 }
180
181 /**
182  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
183  * @hw: Pointer to the HW structure
184  * @mar_count: Receive address registers
185  */
186 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
187 {
188         u32 i;
189
190         /* Setup the receive address */
191         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
192
193         /* Zero out the other receive addresses */
194         for (i = 1; i < mar_count; i++) {
195                 iowrite32(0, &hw->reg->mac_adr[i].high);
196                 iowrite32(0, &hw->reg->mac_adr[i].low);
197         }
198         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
199         /* wait busy */
200         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
201 }
202
203
204 /**
205  * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
206  * @hw:             Pointer to the HW structure
207  * @mc_addr_list:   Array of multicast addresses to program
208  * @mc_addr_count:  Number of multicast addresses to program
209  * @mar_used_count: The first MAC Address register free to program
210  * @mar_total_num:  Total number of supported MAC Address Registers
211  */
212 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
213                                             u8 *mc_addr_list, u32 mc_addr_count,
214                                             u32 mar_used_count, u32 mar_total_num)
215 {
216         u32 i, adrmask;
217
218         /* Load the first set of multicast addresses into the exact
219          * filters (RAR).  If there are not enough to fill the RAR
220          * array, clear the filters.
221          */
222         for (i = mar_used_count; i < mar_total_num; i++) {
223                 if (mc_addr_count) {
224                         pch_gbe_mac_mar_set(hw, mc_addr_list, i);
225                         mc_addr_count--;
226                         mc_addr_list += PCH_GBE_ETH_ALEN;
227                 } else {
228                         /* Clear MAC address mask */
229                         adrmask = ioread32(&hw->reg->ADDR_MASK);
230                         iowrite32((adrmask | (0x0001 << i)),
231                                         &hw->reg->ADDR_MASK);
232                         /* wait busy */
233                         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
234                         /* Clear MAC address */
235                         iowrite32(0, &hw->reg->mac_adr[i].high);
236                         iowrite32(0, &hw->reg->mac_adr[i].low);
237                 }
238         }
239 }
240
241 /**
242  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
243  * @hw:             Pointer to the HW structure
244  * Returns
245  *      0:                      Successful.
246  *      Negative value:         Failed.
247  */
248 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
249 {
250         struct pch_gbe_mac_info *mac = &hw->mac;
251         u32 rx_fctrl;
252
253         pr_debug("mac->fc = %u\n", mac->fc);
254
255         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
256
257         switch (mac->fc) {
258         case PCH_GBE_FC_NONE:
259                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
260                 mac->tx_fc_enable = false;
261                 break;
262         case PCH_GBE_FC_RX_PAUSE:
263                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
264                 mac->tx_fc_enable = false;
265                 break;
266         case PCH_GBE_FC_TX_PAUSE:
267                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
268                 mac->tx_fc_enable = true;
269                 break;
270         case PCH_GBE_FC_FULL:
271                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
272                 mac->tx_fc_enable = true;
273                 break;
274         default:
275                 pr_err("Flow control param set incorrectly\n");
276                 return -EINVAL;
277         }
278         if (mac->link_duplex == DUPLEX_HALF)
279                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
280         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
281         pr_debug("RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
282                  ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
283         return 0;
284 }
285
286 /**
287  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
288  * @hw:     Pointer to the HW structure
289  * @wu_evt: Wake up event
290  */
291 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
292 {
293         u32 addr_mask;
294
295         pr_debug("wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
296                  wu_evt, ioread32(&hw->reg->ADDR_MASK));
297
298         if (wu_evt) {
299                 /* Set Wake-On-Lan address mask */
300                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
301                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
302                 /* wait busy */
303                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
304                 iowrite32(0, &hw->reg->WOL_ST);
305                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
306                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
307                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
308         } else {
309                 iowrite32(0, &hw->reg->WOL_CTRL);
310                 iowrite32(0, &hw->reg->WOL_ST);
311         }
312         return;
313 }
314
315 /**
316  * pch_gbe_mac_ctrl_miim - Control MIIM interface
317  * @hw:   Pointer to the HW structure
318  * @addr: Address of PHY
319  * @dir:  Operetion. (Write or Read)
320  * @reg:  Access register of PHY
321  * @data: Write data.
322  *
323  * Returns: Read date.
324  */
325 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
326                         u16 data)
327 {
328         u32 data_out = 0;
329         unsigned int i;
330         unsigned long flags;
331
332         spin_lock_irqsave(&hw->miim_lock, flags);
333
334         for (i = 100; i; --i) {
335                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
336                         break;
337                 udelay(20);
338         }
339         if (i == 0) {
340                 pr_err("pch-gbe.miim won't go Ready\n");
341                 spin_unlock_irqrestore(&hw->miim_lock, flags);
342                 return 0;       /* No way to indicate timeout error */
343         }
344         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
345                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
346                   dir | data), &hw->reg->MIIM);
347         for (i = 0; i < 100; i++) {
348                 udelay(20);
349                 data_out = ioread32(&hw->reg->MIIM);
350                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
351                         break;
352         }
353         spin_unlock_irqrestore(&hw->miim_lock, flags);
354
355         pr_debug("PHY %s: reg=%d, data=0x%04X\n",
356                  dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
357                  dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
358         return (u16) data_out;
359 }
360
361 /**
362  * pch_gbe_mac_set_pause_packet - Set pause packet
363  * @hw:   Pointer to the HW structure
364  */
365 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
366 {
367         unsigned long tmp2, tmp3;
368
369         /* Set Pause packet */
370         tmp2 = hw->mac.addr[1];
371         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
372         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
373
374         tmp3 = hw->mac.addr[5];
375         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
376         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
377         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
378
379         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
380         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
381         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
382         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
383         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
384
385         /* Transmit Pause Packet */
386         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
387
388         pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
389                  ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
390                  ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
391                  ioread32(&hw->reg->PAUSE_PKT5));
392
393         return;
394 }
395
396
397 /**
398  * pch_gbe_alloc_queues - Allocate memory for all rings
399  * @adapter:  Board private structure to initialize
400  * Returns
401  *      0:      Successfully
402  *      Negative value: Failed
403  */
404 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
405 {
406         int size;
407
408         size = (int)sizeof(struct pch_gbe_tx_ring);
409         adapter->tx_ring = kzalloc(size, GFP_KERNEL);
410         if (!adapter->tx_ring)
411                 return -ENOMEM;
412         size = (int)sizeof(struct pch_gbe_rx_ring);
413         adapter->rx_ring = kzalloc(size, GFP_KERNEL);
414         if (!adapter->rx_ring) {
415                 kfree(adapter->tx_ring);
416                 return -ENOMEM;
417         }
418         return 0;
419 }
420
421 /**
422  * pch_gbe_init_stats - Initialize status
423  * @adapter:  Board private structure to initialize
424  */
425 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
426 {
427         memset(&adapter->stats, 0, sizeof(adapter->stats));
428         return;
429 }
430
431 /**
432  * pch_gbe_init_phy - Initialize PHY
433  * @adapter:  Board private structure to initialize
434  * Returns
435  *      0:      Successfully
436  *      Negative value: Failed
437  */
438 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
439 {
440         struct net_device *netdev = adapter->netdev;
441         u32 addr;
442         u16 bmcr, stat;
443
444         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
445         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
446                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
447                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
448                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
449                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
450                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
451                         break;
452         }
453         adapter->hw.phy.addr = adapter->mii.phy_id;
454         pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
455         if (addr == 32)
456                 return -EAGAIN;
457         /* Selected the phy and isolate the rest */
458         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
459                 if (addr != adapter->mii.phy_id) {
460                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
461                                            BMCR_ISOLATE);
462                 } else {
463                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
464                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
465                                            bmcr & ~BMCR_ISOLATE);
466                 }
467         }
468
469         /* MII setup */
470         adapter->mii.phy_id_mask = 0x1F;
471         adapter->mii.reg_num_mask = 0x1F;
472         adapter->mii.dev = adapter->netdev;
473         adapter->mii.mdio_read = pch_gbe_mdio_read;
474         adapter->mii.mdio_write = pch_gbe_mdio_write;
475         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
476         return 0;
477 }
478
479 /**
480  * pch_gbe_mdio_read - The read function for mii
481  * @netdev: Network interface device structure
482  * @addr:   Phy ID
483  * @reg:    Access location
484  * Returns
485  *      0:      Successfully
486  *      Negative value: Failed
487  */
488 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
489 {
490         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
491         struct pch_gbe_hw *hw = &adapter->hw;
492
493         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
494                                      (u16) 0);
495 }
496
497 /**
498  * pch_gbe_mdio_write - The write function for mii
499  * @netdev: Network interface device structure
500  * @addr:   Phy ID (not used)
501  * @reg:    Access location
502  * @data:   Write data
503  */
504 static void pch_gbe_mdio_write(struct net_device *netdev,
505                                int addr, int reg, int data)
506 {
507         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
508         struct pch_gbe_hw *hw = &adapter->hw;
509
510         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
511 }
512
513 /**
514  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
515  * @work:  Pointer of board private structure
516  */
517 static void pch_gbe_reset_task(struct work_struct *work)
518 {
519         struct pch_gbe_adapter *adapter;
520         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
521
522         pch_gbe_reinit_locked(adapter);
523 }
524
525 /**
526  * pch_gbe_reinit_locked- Re-initialization
527  * @adapter:  Board private structure
528  */
529 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
530 {
531         struct net_device *netdev = adapter->netdev;
532
533         rtnl_lock();
534         if (netif_running(netdev)) {
535                 pch_gbe_down(adapter);
536                 pch_gbe_up(adapter);
537         }
538         rtnl_unlock();
539 }
540
541 /**
542  * pch_gbe_reset - Reset GbE
543  * @adapter:  Board private structure
544  */
545 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
546 {
547         pch_gbe_mac_reset_hw(&adapter->hw);
548         /* Setup the receive address. */
549         pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
550         if (pch_gbe_hal_init_hw(&adapter->hw))
551                 pr_err("Hardware Error\n");
552 }
553
554 /**
555  * pch_gbe_free_irq - Free an interrupt
556  * @adapter:  Board private structure
557  */
558 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
559 {
560         struct net_device *netdev = adapter->netdev;
561
562         free_irq(adapter->pdev->irq, netdev);
563         if (adapter->have_msi) {
564                 pci_disable_msi(adapter->pdev);
565                 pr_debug("call pci_disable_msi\n");
566         }
567 }
568
569 /**
570  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
571  * @adapter:  Board private structure
572  */
573 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
574 {
575         struct pch_gbe_hw *hw = &adapter->hw;
576
577         atomic_inc(&adapter->irq_sem);
578         iowrite32(0, &hw->reg->INT_EN);
579         ioread32(&hw->reg->INT_ST);
580         synchronize_irq(adapter->pdev->irq);
581
582         pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
583 }
584
585 /**
586  * pch_gbe_irq_enable - Enable default interrupt generation settings
587  * @adapter:  Board private structure
588  */
589 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
590 {
591         struct pch_gbe_hw *hw = &adapter->hw;
592
593         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
594                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
595         ioread32(&hw->reg->INT_ST);
596         pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
597 }
598
599
600
601 /**
602  * pch_gbe_setup_tctl - configure the Transmit control registers
603  * @adapter:  Board private structure
604  */
605 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
606 {
607         struct pch_gbe_hw *hw = &adapter->hw;
608         u32 tx_mode, tcpip;
609
610         tx_mode = PCH_GBE_TM_LONG_PKT |
611                 PCH_GBE_TM_ST_AND_FD |
612                 PCH_GBE_TM_SHORT_PKT |
613                 PCH_GBE_TM_TH_TX_STRT_8 |
614                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
615
616         iowrite32(tx_mode, &hw->reg->TX_MODE);
617
618         tcpip = ioread32(&hw->reg->TCPIP_ACC);
619         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
620         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
621         return;
622 }
623
624 /**
625  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
626  * @adapter:  Board private structure
627  */
628 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
629 {
630         struct pch_gbe_hw *hw = &adapter->hw;
631         u32 tdba, tdlen, dctrl;
632
633         pr_debug("dma addr = 0x%08llx  size = 0x%08x\n",
634                  (unsigned long long)adapter->tx_ring->dma,
635                  adapter->tx_ring->size);
636
637         /* Setup the HW Tx Head and Tail descriptor pointers */
638         tdba = adapter->tx_ring->dma;
639         tdlen = adapter->tx_ring->size - 0x10;
640         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
641         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
642         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
643
644         /* Enables Transmission DMA */
645         dctrl = ioread32(&hw->reg->DMA_CTRL);
646         dctrl |= PCH_GBE_TX_DMA_EN;
647         iowrite32(dctrl, &hw->reg->DMA_CTRL);
648 }
649
650 /**
651  * pch_gbe_setup_rctl - Configure the receive control registers
652  * @adapter:  Board private structure
653  */
654 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
655 {
656         struct pch_gbe_hw *hw = &adapter->hw;
657         u32 rx_mode, tcpip;
658
659         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
660         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
661
662         iowrite32(rx_mode, &hw->reg->RX_MODE);
663
664         tcpip = ioread32(&hw->reg->TCPIP_ACC);
665
666         if (adapter->rx_csum) {
667                 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
668                 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
669         } else {
670                 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
671                 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
672         }
673         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
674         return;
675 }
676
677 /**
678  * pch_gbe_configure_rx - Configure Receive Unit after Reset
679  * @adapter:  Board private structure
680  */
681 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
682 {
683         struct pch_gbe_hw *hw = &adapter->hw;
684         u32 rdba, rdlen, rctl, rxdma;
685
686         pr_debug("dma adr = 0x%08llx  size = 0x%08x\n",
687                  (unsigned long long)adapter->rx_ring->dma,
688                  adapter->rx_ring->size);
689
690         pch_gbe_mac_force_mac_fc(hw);
691
692         /* Disables Receive MAC */
693         rctl = ioread32(&hw->reg->MAC_RX_EN);
694         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
695
696         /* Disables Receive DMA */
697         rxdma = ioread32(&hw->reg->DMA_CTRL);
698         rxdma &= ~PCH_GBE_RX_DMA_EN;
699         iowrite32(rxdma, &hw->reg->DMA_CTRL);
700
701         pr_debug("MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
702                  ioread32(&hw->reg->MAC_RX_EN),
703                  ioread32(&hw->reg->DMA_CTRL));
704
705         /* Setup the HW Rx Head and Tail Descriptor Pointers and
706          * the Base and Length of the Rx Descriptor Ring */
707         rdba = adapter->rx_ring->dma;
708         rdlen = adapter->rx_ring->size - 0x10;
709         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
710         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
711         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
712
713         /* Enables Receive DMA */
714         rxdma = ioread32(&hw->reg->DMA_CTRL);
715         rxdma |= PCH_GBE_RX_DMA_EN;
716         iowrite32(rxdma, &hw->reg->DMA_CTRL);
717         /* Enables Receive */
718         iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
719 }
720
721 /**
722  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
723  * @adapter:     Board private structure
724  * @buffer_info: Buffer information structure
725  */
726 static void pch_gbe_unmap_and_free_tx_resource(
727         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
728 {
729         if (buffer_info->mapped) {
730                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
731                                  buffer_info->length, DMA_TO_DEVICE);
732                 buffer_info->mapped = false;
733         }
734         if (buffer_info->skb) {
735                 dev_kfree_skb_any(buffer_info->skb);
736                 buffer_info->skb = NULL;
737         }
738 }
739
740 /**
741  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
742  * @adapter:      Board private structure
743  * @buffer_info:  Buffer information structure
744  */
745 static void pch_gbe_unmap_and_free_rx_resource(
746                                         struct pch_gbe_adapter *adapter,
747                                         struct pch_gbe_buffer *buffer_info)
748 {
749         if (buffer_info->mapped) {
750                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
751                                  buffer_info->length, DMA_FROM_DEVICE);
752                 buffer_info->mapped = false;
753         }
754         if (buffer_info->skb) {
755                 dev_kfree_skb_any(buffer_info->skb);
756                 buffer_info->skb = NULL;
757         }
758 }
759
760 /**
761  * pch_gbe_clean_tx_ring - Free Tx Buffers
762  * @adapter:  Board private structure
763  * @tx_ring:  Ring to be cleaned
764  */
765 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
766                                    struct pch_gbe_tx_ring *tx_ring)
767 {
768         struct pch_gbe_hw *hw = &adapter->hw;
769         struct pch_gbe_buffer *buffer_info;
770         unsigned long size;
771         unsigned int i;
772
773         /* Free all the Tx ring sk_buffs */
774         for (i = 0; i < tx_ring->count; i++) {
775                 buffer_info = &tx_ring->buffer_info[i];
776                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
777         }
778         pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
779
780         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
781         memset(tx_ring->buffer_info, 0, size);
782
783         /* Zero out the descriptor ring */
784         memset(tx_ring->desc, 0, tx_ring->size);
785         tx_ring->next_to_use = 0;
786         tx_ring->next_to_clean = 0;
787         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
788         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
789 }
790
791 /**
792  * pch_gbe_clean_rx_ring - Free Rx Buffers
793  * @adapter:  Board private structure
794  * @rx_ring:  Ring to free buffers from
795  */
796 static void
797 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
798                       struct pch_gbe_rx_ring *rx_ring)
799 {
800         struct pch_gbe_hw *hw = &adapter->hw;
801         struct pch_gbe_buffer *buffer_info;
802         unsigned long size;
803         unsigned int i;
804
805         /* Free all the Rx ring sk_buffs */
806         for (i = 0; i < rx_ring->count; i++) {
807                 buffer_info = &rx_ring->buffer_info[i];
808                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
809         }
810         pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
811         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
812         memset(rx_ring->buffer_info, 0, size);
813
814         /* Zero out the descriptor ring */
815         memset(rx_ring->desc, 0, rx_ring->size);
816         rx_ring->next_to_clean = 0;
817         rx_ring->next_to_use = 0;
818         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
819         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
820 }
821
822 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
823                                     u16 duplex)
824 {
825         struct pch_gbe_hw *hw = &adapter->hw;
826         unsigned long rgmii = 0;
827
828         /* Set the RGMII control. */
829 #ifdef PCH_GBE_MAC_IFOP_RGMII
830         switch (speed) {
831         case SPEED_10:
832                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
833                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
834                 break;
835         case SPEED_100:
836                 rgmii = (PCH_GBE_RGMII_RATE_25M |
837                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
838                 break;
839         case SPEED_1000:
840                 rgmii = (PCH_GBE_RGMII_RATE_125M |
841                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
842                 break;
843         }
844         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
845 #else   /* GMII */
846         rgmii = 0;
847         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
848 #endif
849 }
850 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
851                               u16 duplex)
852 {
853         struct net_device *netdev = adapter->netdev;
854         struct pch_gbe_hw *hw = &adapter->hw;
855         unsigned long mode = 0;
856
857         /* Set the communication mode */
858         switch (speed) {
859         case SPEED_10:
860                 mode = PCH_GBE_MODE_MII_ETHER;
861                 netdev->tx_queue_len = 10;
862                 break;
863         case SPEED_100:
864                 mode = PCH_GBE_MODE_MII_ETHER;
865                 netdev->tx_queue_len = 100;
866                 break;
867         case SPEED_1000:
868                 mode = PCH_GBE_MODE_GMII_ETHER;
869                 break;
870         }
871         if (duplex == DUPLEX_FULL)
872                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
873         else
874                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
875         iowrite32(mode, &hw->reg->MODE);
876 }
877
878 /**
879  * pch_gbe_watchdog - Watchdog process
880  * @data:  Board private structure
881  */
882 static void pch_gbe_watchdog(unsigned long data)
883 {
884         struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
885         struct net_device *netdev = adapter->netdev;
886         struct pch_gbe_hw *hw = &adapter->hw;
887         struct ethtool_cmd cmd;
888
889         pr_debug("right now = %ld\n", jiffies);
890
891         pch_gbe_update_stats(adapter);
892         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
893                 netdev->tx_queue_len = adapter->tx_queue_len;
894                 /* mii library handles link maintenance tasks */
895                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
896                         pr_err("ethtool get setting Error\n");
897                         mod_timer(&adapter->watchdog_timer,
898                                   round_jiffies(jiffies +
899                                                 PCH_GBE_WATCHDOG_PERIOD));
900                         return;
901                 }
902                 hw->mac.link_speed = cmd.speed;
903                 hw->mac.link_duplex = cmd.duplex;
904                 /* Set the RGMII control. */
905                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
906                                                 hw->mac.link_duplex);
907                 /* Set the communication mode */
908                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
909                                  hw->mac.link_duplex);
910                 netdev_dbg(netdev,
911                            "Link is Up %d Mbps %s-Duplex\n",
912                            cmd.speed,
913                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
914                 netif_carrier_on(netdev);
915                 netif_wake_queue(netdev);
916         } else if ((!mii_link_ok(&adapter->mii)) &&
917                    (netif_carrier_ok(netdev))) {
918                 netdev_dbg(netdev, "NIC Link is Down\n");
919                 hw->mac.link_speed = SPEED_10;
920                 hw->mac.link_duplex = DUPLEX_HALF;
921                 netif_carrier_off(netdev);
922                 netif_stop_queue(netdev);
923         }
924         mod_timer(&adapter->watchdog_timer,
925                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
926 }
927
928 /**
929  * pch_gbe_tx_queue - Carry out queuing of the transmission data
930  * @adapter:  Board private structure
931  * @tx_ring:  Tx descriptor ring structure
932  * @skb:      Sockt buffer structure
933  */
934 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
935                               struct pch_gbe_tx_ring *tx_ring,
936                               struct sk_buff *skb)
937 {
938         struct pch_gbe_hw *hw = &adapter->hw;
939         struct pch_gbe_tx_desc *tx_desc;
940         struct pch_gbe_buffer *buffer_info;
941         struct sk_buff *tmp_skb;
942         unsigned int frame_ctrl;
943         unsigned int ring_num;
944         unsigned long flags;
945
946         /*-- Set frame control --*/
947         frame_ctrl = 0;
948         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
949                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
950         if (unlikely(!adapter->tx_csum))
951                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
952
953         /* Performs checksum processing */
954         /*
955          * It is because the hardware accelerator does not support a checksum,
956          * when the received data size is less than 64 bytes.
957          */
958         if ((skb->len < PCH_GBE_SHORT_PKT) && (adapter->tx_csum)) {
959                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
960                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
961                 if (skb->protocol == htons(ETH_P_IP)) {
962                         struct iphdr *iph = ip_hdr(skb);
963                         unsigned int offset;
964                         iph->check = 0;
965                         iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
966                         offset = skb_transport_offset(skb);
967                         if (iph->protocol == IPPROTO_TCP) {
968                                 skb->csum = 0;
969                                 tcp_hdr(skb)->check = 0;
970                                 skb->csum = skb_checksum(skb, offset,
971                                                          skb->len - offset, 0);
972                                 tcp_hdr(skb)->check =
973                                         csum_tcpudp_magic(iph->saddr,
974                                                           iph->daddr,
975                                                           skb->len - offset,
976                                                           IPPROTO_TCP,
977                                                           skb->csum);
978                         } else if (iph->protocol == IPPROTO_UDP) {
979                                 skb->csum = 0;
980                                 udp_hdr(skb)->check = 0;
981                                 skb->csum =
982                                         skb_checksum(skb, offset,
983                                                      skb->len - offset, 0);
984                                 udp_hdr(skb)->check =
985                                         csum_tcpudp_magic(iph->saddr,
986                                                           iph->daddr,
987                                                           skb->len - offset,
988                                                           IPPROTO_UDP,
989                                                           skb->csum);
990                         }
991                 }
992         }
993         spin_lock_irqsave(&tx_ring->tx_lock, flags);
994         ring_num = tx_ring->next_to_use;
995         if (unlikely((ring_num + 1) == tx_ring->count))
996                 tx_ring->next_to_use = 0;
997         else
998                 tx_ring->next_to_use = ring_num + 1;
999
1000         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1001         buffer_info = &tx_ring->buffer_info[ring_num];
1002         tmp_skb = buffer_info->skb;
1003
1004         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1005         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1006         tmp_skb->data[ETH_HLEN] = 0x00;
1007         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1008         tmp_skb->len = skb->len;
1009         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1010                (skb->len - ETH_HLEN));
1011         /*-- Set Buffer infomation --*/
1012         buffer_info->length = tmp_skb->len;
1013         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1014                                           buffer_info->length,
1015                                           DMA_TO_DEVICE);
1016         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1017                 pr_err("TX DMA map failed\n");
1018                 buffer_info->dma = 0;
1019                 buffer_info->time_stamp = 0;
1020                 tx_ring->next_to_use = ring_num;
1021                 return;
1022         }
1023         buffer_info->mapped = true;
1024         buffer_info->time_stamp = jiffies;
1025
1026         /*-- Set Tx descriptor --*/
1027         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1028         tx_desc->buffer_addr = (buffer_info->dma);
1029         tx_desc->length = (tmp_skb->len);
1030         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1031         tx_desc->tx_frame_ctrl = (frame_ctrl);
1032         tx_desc->gbec_status = (DSC_INIT16);
1033
1034         if (unlikely(++ring_num == tx_ring->count))
1035                 ring_num = 0;
1036
1037         /* Update software pointer of TX descriptor */
1038         iowrite32(tx_ring->dma +
1039                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1040                   &hw->reg->TX_DSC_SW_P);
1041         dev_kfree_skb_any(skb);
1042 }
1043
1044 /**
1045  * pch_gbe_update_stats - Update the board statistics counters
1046  * @adapter:  Board private structure
1047  */
1048 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1049 {
1050         struct net_device *netdev = adapter->netdev;
1051         struct pci_dev *pdev = adapter->pdev;
1052         struct pch_gbe_hw_stats *stats = &adapter->stats;
1053         unsigned long flags;
1054
1055         /*
1056          * Prevent stats update while adapter is being reset, or if the pci
1057          * connection is down.
1058          */
1059         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1060                 return;
1061
1062         spin_lock_irqsave(&adapter->stats_lock, flags);
1063
1064         /* Update device status "adapter->stats" */
1065         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1066         stats->tx_errors = stats->tx_length_errors +
1067             stats->tx_aborted_errors +
1068             stats->tx_carrier_errors + stats->tx_timeout_count;
1069
1070         /* Update network device status "adapter->net_stats" */
1071         netdev->stats.rx_packets = stats->rx_packets;
1072         netdev->stats.rx_bytes = stats->rx_bytes;
1073         netdev->stats.rx_dropped = stats->rx_dropped;
1074         netdev->stats.tx_packets = stats->tx_packets;
1075         netdev->stats.tx_bytes = stats->tx_bytes;
1076         netdev->stats.tx_dropped = stats->tx_dropped;
1077         /* Fill out the OS statistics structure */
1078         netdev->stats.multicast = stats->multicast;
1079         netdev->stats.collisions = stats->collisions;
1080         /* Rx Errors */
1081         netdev->stats.rx_errors = stats->rx_errors;
1082         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1083         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1084         /* Tx Errors */
1085         netdev->stats.tx_errors = stats->tx_errors;
1086         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1087         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1088
1089         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1090 }
1091
1092 /**
1093  * pch_gbe_intr - Interrupt Handler
1094  * @irq:   Interrupt number
1095  * @data:  Pointer to a network interface device structure
1096  * Returns
1097  *      - IRQ_HANDLED:  Our interrupt
1098  *      - IRQ_NONE:     Not our interrupt
1099  */
1100 static irqreturn_t pch_gbe_intr(int irq, void *data)
1101 {
1102         struct net_device *netdev = data;
1103         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1104         struct pch_gbe_hw *hw = &adapter->hw;
1105         u32 int_st;
1106         u32 int_en;
1107
1108         /* Check request status */
1109         int_st = ioread32(&hw->reg->INT_ST);
1110         int_st = int_st & ioread32(&hw->reg->INT_EN);
1111         /* When request status is no interruption factor */
1112         if (unlikely(!int_st))
1113                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1114         pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1115         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1116                 adapter->stats.intr_rx_frame_err_count++;
1117         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1118                 adapter->stats.intr_rx_fifo_err_count++;
1119         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1120                 adapter->stats.intr_rx_dma_err_count++;
1121         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1122                 adapter->stats.intr_tx_fifo_err_count++;
1123         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1124                 adapter->stats.intr_tx_dma_err_count++;
1125         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1126                 adapter->stats.intr_tcpip_err_count++;
1127         /* When Rx descriptor is empty  */
1128         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1129                 adapter->stats.intr_rx_dsc_empty_count++;
1130                 pr_err("Rx descriptor is empty\n");
1131                 int_en = ioread32(&hw->reg->INT_EN);
1132                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1133                 if (hw->mac.tx_fc_enable) {
1134                         /* Set Pause packet */
1135                         pch_gbe_mac_set_pause_packet(hw);
1136                 }
1137                 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1138                     == 0) {
1139                         return IRQ_HANDLED;
1140                 }
1141         }
1142
1143         /* When request status is Receive interruption */
1144         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1145                 if (likely(napi_schedule_prep(&adapter->napi))) {
1146                         /* Enable only Rx Descriptor empty */
1147                         atomic_inc(&adapter->irq_sem);
1148                         int_en = ioread32(&hw->reg->INT_EN);
1149                         int_en &=
1150                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1151                         iowrite32(int_en, &hw->reg->INT_EN);
1152                         /* Start polling for NAPI */
1153                         __napi_schedule(&adapter->napi);
1154                 }
1155         }
1156         pr_debug("return = 0x%08x  INT_EN reg = 0x%08x\n",
1157                  IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1158         return IRQ_HANDLED;
1159 }
1160
1161 /**
1162  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1163  * @adapter:       Board private structure
1164  * @rx_ring:       Rx descriptor ring
1165  * @cleaned_count: Cleaned count
1166  */
1167 static void
1168 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1169                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1170 {
1171         struct net_device *netdev = adapter->netdev;
1172         struct pci_dev *pdev = adapter->pdev;
1173         struct pch_gbe_hw *hw = &adapter->hw;
1174         struct pch_gbe_rx_desc *rx_desc;
1175         struct pch_gbe_buffer *buffer_info;
1176         struct sk_buff *skb;
1177         unsigned int i;
1178         unsigned int bufsz;
1179
1180         bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1181         i = rx_ring->next_to_use;
1182
1183         while ((cleaned_count--)) {
1184                 buffer_info = &rx_ring->buffer_info[i];
1185                 skb = buffer_info->skb;
1186                 if (skb) {
1187                         skb_trim(skb, 0);
1188                 } else {
1189                         skb = netdev_alloc_skb(netdev, bufsz);
1190                         if (unlikely(!skb)) {
1191                                 /* Better luck next round */
1192                                 adapter->stats.rx_alloc_buff_failed++;
1193                                 break;
1194                         }
1195                         /* 64byte align */
1196                         skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1197
1198                         buffer_info->skb = skb;
1199                         buffer_info->length = adapter->rx_buffer_len;
1200                 }
1201                 buffer_info->dma = dma_map_single(&pdev->dev,
1202                                                   skb->data,
1203                                                   buffer_info->length,
1204                                                   DMA_FROM_DEVICE);
1205                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1206                         dev_kfree_skb(skb);
1207                         buffer_info->skb = NULL;
1208                         buffer_info->dma = 0;
1209                         adapter->stats.rx_alloc_buff_failed++;
1210                         break; /* while !buffer_info->skb */
1211                 }
1212                 buffer_info->mapped = true;
1213                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1214                 rx_desc->buffer_addr = (buffer_info->dma);
1215                 rx_desc->gbec_status = DSC_INIT16;
1216
1217                 pr_debug("i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1218                          i, (unsigned long long)buffer_info->dma,
1219                          buffer_info->length);
1220
1221                 if (unlikely(++i == rx_ring->count))
1222                         i = 0;
1223         }
1224         if (likely(rx_ring->next_to_use != i)) {
1225                 rx_ring->next_to_use = i;
1226                 if (unlikely(i-- == 0))
1227                         i = (rx_ring->count - 1);
1228                 iowrite32(rx_ring->dma +
1229                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1230                           &hw->reg->RX_DSC_SW_P);
1231         }
1232         return;
1233 }
1234
1235 /**
1236  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1237  * @adapter:   Board private structure
1238  * @tx_ring:   Tx descriptor ring
1239  */
1240 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1241                                         struct pch_gbe_tx_ring *tx_ring)
1242 {
1243         struct pch_gbe_buffer *buffer_info;
1244         struct sk_buff *skb;
1245         unsigned int i;
1246         unsigned int bufsz;
1247         struct pch_gbe_tx_desc *tx_desc;
1248
1249         bufsz =
1250             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1251
1252         for (i = 0; i < tx_ring->count; i++) {
1253                 buffer_info = &tx_ring->buffer_info[i];
1254                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1255                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1256                 buffer_info->skb = skb;
1257                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1258                 tx_desc->gbec_status = (DSC_INIT16);
1259         }
1260         return;
1261 }
1262
1263 /**
1264  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1265  * @adapter:   Board private structure
1266  * @tx_ring:   Tx descriptor ring
1267  * Returns
1268  *      true:  Cleaned the descriptor
1269  *      false: Not cleaned the descriptor
1270  */
1271 static bool
1272 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1273                  struct pch_gbe_tx_ring *tx_ring)
1274 {
1275         struct pch_gbe_tx_desc *tx_desc;
1276         struct pch_gbe_buffer *buffer_info;
1277         struct sk_buff *skb;
1278         unsigned int i;
1279         unsigned int cleaned_count = 0;
1280         bool cleaned = false;
1281
1282         pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1283
1284         i = tx_ring->next_to_clean;
1285         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1286         pr_debug("gbec_status:0x%04x  dma_status:0x%04x\n",
1287                  tx_desc->gbec_status, tx_desc->dma_status);
1288
1289         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1290                 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1291                 cleaned = true;
1292                 buffer_info = &tx_ring->buffer_info[i];
1293                 skb = buffer_info->skb;
1294
1295                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1296                         adapter->stats.tx_aborted_errors++;
1297                         pr_err("Transfer Abort Error\n");
1298                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1299                           ) {
1300                         adapter->stats.tx_carrier_errors++;
1301                         pr_err("Transfer Carrier Sense Error\n");
1302                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1303                           ) {
1304                         adapter->stats.tx_aborted_errors++;
1305                         pr_err("Transfer Collision Abort Error\n");
1306                 } else if ((tx_desc->gbec_status &
1307                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1308                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1309                         adapter->stats.collisions++;
1310                         adapter->stats.tx_packets++;
1311                         adapter->stats.tx_bytes += skb->len;
1312                         pr_debug("Transfer Collision\n");
1313                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1314                           ) {
1315                         adapter->stats.tx_packets++;
1316                         adapter->stats.tx_bytes += skb->len;
1317                 }
1318                 if (buffer_info->mapped) {
1319                         pr_debug("unmap buffer_info->dma : %d\n", i);
1320                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1321                                          buffer_info->length, DMA_TO_DEVICE);
1322                         buffer_info->mapped = false;
1323                 }
1324                 if (buffer_info->skb) {
1325                         pr_debug("trim buffer_info->skb : %d\n", i);
1326                         skb_trim(buffer_info->skb, 0);
1327                 }
1328                 tx_desc->gbec_status = DSC_INIT16;
1329                 if (unlikely(++i == tx_ring->count))
1330                         i = 0;
1331                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1332
1333                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1334                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1335                         break;
1336         }
1337         pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1338                  cleaned_count);
1339         /* Recover from running out of Tx resources in xmit_frame */
1340         if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1341                 netif_wake_queue(adapter->netdev);
1342                 adapter->stats.tx_restart_count++;
1343                 pr_debug("Tx wake queue\n");
1344         }
1345         spin_lock(&adapter->tx_queue_lock);
1346         tx_ring->next_to_clean = i;
1347         spin_unlock(&adapter->tx_queue_lock);
1348         pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1349         return cleaned;
1350 }
1351
1352 /**
1353  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1354  * @adapter:     Board private structure
1355  * @rx_ring:     Rx descriptor ring
1356  * @work_done:   Completed count
1357  * @work_to_do:  Request count
1358  * Returns
1359  *      true:  Cleaned the descriptor
1360  *      false: Not cleaned the descriptor
1361  */
1362 static bool
1363 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1364                  struct pch_gbe_rx_ring *rx_ring,
1365                  int *work_done, int work_to_do)
1366 {
1367         struct net_device *netdev = adapter->netdev;
1368         struct pci_dev *pdev = adapter->pdev;
1369         struct pch_gbe_buffer *buffer_info;
1370         struct pch_gbe_rx_desc *rx_desc;
1371         u32 length;
1372         unsigned char tmp_packet[ETH_HLEN];
1373         unsigned int i;
1374         unsigned int cleaned_count = 0;
1375         bool cleaned = false;
1376         struct sk_buff *skb;
1377         u8 dma_status;
1378         u16 gbec_status;
1379         u32 tcp_ip_status;
1380         u8 skb_copy_flag = 0;
1381         u8 skb_padding_flag = 0;
1382
1383         i = rx_ring->next_to_clean;
1384
1385         while (*work_done < work_to_do) {
1386                 /* Check Rx descriptor status */
1387                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1388                 if (rx_desc->gbec_status == DSC_INIT16)
1389                         break;
1390                 cleaned = true;
1391                 cleaned_count++;
1392
1393                 dma_status = rx_desc->dma_status;
1394                 gbec_status = rx_desc->gbec_status;
1395                 tcp_ip_status = rx_desc->tcp_ip_status;
1396                 rx_desc->gbec_status = DSC_INIT16;
1397                 buffer_info = &rx_ring->buffer_info[i];
1398                 skb = buffer_info->skb;
1399
1400                 /* unmap dma */
1401                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1402                                    buffer_info->length, DMA_FROM_DEVICE);
1403                 buffer_info->mapped = false;
1404                 /* Prefetch the packet */
1405                 prefetch(skb->data);
1406
1407                 pr_debug("RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x "
1408                          "TCP:0x%08x]  BufInf = 0x%p\n",
1409                          i, dma_status, gbec_status, tcp_ip_status,
1410                          buffer_info);
1411                 /* Error check */
1412                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1413                         adapter->stats.rx_frame_errors++;
1414                         pr_err("Receive Not Octal Error\n");
1415                 } else if (unlikely(gbec_status &
1416                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1417                         adapter->stats.rx_frame_errors++;
1418                         pr_err("Receive Nibble Error\n");
1419                 } else if (unlikely(gbec_status &
1420                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1421                         adapter->stats.rx_crc_errors++;
1422                         pr_err("Receive CRC Error\n");
1423                 } else {
1424                         /* get receive length */
1425                         /* length convert[-3], padding[-2] */
1426                         length = (rx_desc->rx_words_eob) - 3 - 2;
1427
1428                         /* Decide the data conversion method */
1429                         if (!adapter->rx_csum) {
1430                                 /* [Header:14][payload] */
1431                                 skb_padding_flag = 0;
1432                                 skb_copy_flag = 1;
1433                         } else {
1434                                 /* [Header:14][padding:2][payload] */
1435                                 skb_padding_flag = 1;
1436                                 if (length < copybreak)
1437                                         skb_copy_flag = 1;
1438                                 else
1439                                         skb_copy_flag = 0;
1440                         }
1441
1442                         /* Data conversion */
1443                         if (skb_copy_flag) {    /* recycle  skb */
1444                                 struct sk_buff *new_skb;
1445                                 new_skb =
1446                                     netdev_alloc_skb(netdev,
1447                                                      length + NET_IP_ALIGN);
1448                                 if (new_skb) {
1449                                         if (!skb_padding_flag) {
1450                                                 skb_reserve(new_skb,
1451                                                                 NET_IP_ALIGN);
1452                                         }
1453                                         memcpy(new_skb->data, skb->data,
1454                                                 length);
1455                                         /* save the skb
1456                                          * in buffer_info as good */
1457                                         skb = new_skb;
1458                                 } else if (!skb_padding_flag) {
1459                                         /* dorrop error */
1460                                         pr_err("New skb allocation Error\n");
1461                                         goto dorrop;
1462                                 }
1463                         } else {
1464                                 buffer_info->skb = NULL;
1465                         }
1466                         if (skb_padding_flag) {
1467                                 memcpy(&tmp_packet[0], &skb->data[0], ETH_HLEN);
1468                                 memcpy(&skb->data[NET_IP_ALIGN], &tmp_packet[0],
1469                                         ETH_HLEN);
1470                                 skb_reserve(skb, NET_IP_ALIGN);
1471
1472                         }
1473
1474                         /* update status of driver */
1475                         adapter->stats.rx_bytes += length;
1476                         adapter->stats.rx_packets++;
1477                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1478                                 adapter->stats.multicast++;
1479                         /* Write meta date of skb */
1480                         skb_put(skb, length);
1481                         skb->protocol = eth_type_trans(skb, netdev);
1482                         if ((tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) ==
1483                             PCH_GBE_RXD_ACC_STAT_TCPIPOK) {
1484                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1485                         } else {
1486                                 skb->ip_summed = CHECKSUM_NONE;
1487                         }
1488                         napi_gro_receive(&adapter->napi, skb);
1489                         (*work_done)++;
1490                         pr_debug("Receive skb->ip_summed: %d length: %d\n",
1491                                  skb->ip_summed, length);
1492                 }
1493 dorrop:
1494                 /* return some buffers to hardware, one at a time is too slow */
1495                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1496                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1497                                                  cleaned_count);
1498                         cleaned_count = 0;
1499                 }
1500                 if (++i == rx_ring->count)
1501                         i = 0;
1502         }
1503         rx_ring->next_to_clean = i;
1504         if (cleaned_count)
1505                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1506         return cleaned;
1507 }
1508
1509 /**
1510  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1511  * @adapter:  Board private structure
1512  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1513  * Returns
1514  *      0:              Successfully
1515  *      Negative value: Failed
1516  */
1517 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1518                                 struct pch_gbe_tx_ring *tx_ring)
1519 {
1520         struct pci_dev *pdev = adapter->pdev;
1521         struct pch_gbe_tx_desc *tx_desc;
1522         int size;
1523         int desNo;
1524
1525         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1526         tx_ring->buffer_info = vmalloc(size);
1527         if (!tx_ring->buffer_info) {
1528                 pr_err("Unable to allocate memory for the buffer infomation\n");
1529                 return -ENOMEM;
1530         }
1531         memset(tx_ring->buffer_info, 0, size);
1532
1533         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1534
1535         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1536                                            &tx_ring->dma, GFP_KERNEL);
1537         if (!tx_ring->desc) {
1538                 vfree(tx_ring->buffer_info);
1539                 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1540                 return -ENOMEM;
1541         }
1542         memset(tx_ring->desc, 0, tx_ring->size);
1543
1544         tx_ring->next_to_use = 0;
1545         tx_ring->next_to_clean = 0;
1546         spin_lock_init(&tx_ring->tx_lock);
1547
1548         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1549                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1550                 tx_desc->gbec_status = DSC_INIT16;
1551         }
1552         pr_debug("tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx\n"
1553                  "next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1554                  tx_ring->desc, (unsigned long long)tx_ring->dma,
1555                  tx_ring->next_to_clean, tx_ring->next_to_use);
1556         return 0;
1557 }
1558
1559 /**
1560  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1561  * @adapter:  Board private structure
1562  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1563  * Returns
1564  *      0:              Successfully
1565  *      Negative value: Failed
1566  */
1567 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1568                                 struct pch_gbe_rx_ring *rx_ring)
1569 {
1570         struct pci_dev *pdev = adapter->pdev;
1571         struct pch_gbe_rx_desc *rx_desc;
1572         int size;
1573         int desNo;
1574
1575         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1576         rx_ring->buffer_info = vmalloc(size);
1577         if (!rx_ring->buffer_info) {
1578                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1579                 return -ENOMEM;
1580         }
1581         memset(rx_ring->buffer_info, 0, size);
1582         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1583         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1584                                            &rx_ring->dma, GFP_KERNEL);
1585
1586         if (!rx_ring->desc) {
1587                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1588                 vfree(rx_ring->buffer_info);
1589                 return -ENOMEM;
1590         }
1591         memset(rx_ring->desc, 0, rx_ring->size);
1592         rx_ring->next_to_clean = 0;
1593         rx_ring->next_to_use = 0;
1594         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1595                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1596                 rx_desc->gbec_status = DSC_INIT16;
1597         }
1598         pr_debug("rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx "
1599                  "next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1600                  rx_ring->desc, (unsigned long long)rx_ring->dma,
1601                  rx_ring->next_to_clean, rx_ring->next_to_use);
1602         return 0;
1603 }
1604
1605 /**
1606  * pch_gbe_free_tx_resources - Free Tx Resources
1607  * @adapter:  Board private structure
1608  * @tx_ring:  Tx descriptor ring for a specific queue
1609  */
1610 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1611                                 struct pch_gbe_tx_ring *tx_ring)
1612 {
1613         struct pci_dev *pdev = adapter->pdev;
1614
1615         pch_gbe_clean_tx_ring(adapter, tx_ring);
1616         vfree(tx_ring->buffer_info);
1617         tx_ring->buffer_info = NULL;
1618         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1619         tx_ring->desc = NULL;
1620 }
1621
1622 /**
1623  * pch_gbe_free_rx_resources - Free Rx Resources
1624  * @adapter:  Board private structure
1625  * @rx_ring:  Ring to clean the resources from
1626  */
1627 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1628                                 struct pch_gbe_rx_ring *rx_ring)
1629 {
1630         struct pci_dev *pdev = adapter->pdev;
1631
1632         pch_gbe_clean_rx_ring(adapter, rx_ring);
1633         vfree(rx_ring->buffer_info);
1634         rx_ring->buffer_info = NULL;
1635         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1636         rx_ring->desc = NULL;
1637 }
1638
1639 /**
1640  * pch_gbe_request_irq - Allocate an interrupt line
1641  * @adapter:  Board private structure
1642  * Returns
1643  *      0:              Successfully
1644  *      Negative value: Failed
1645  */
1646 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1647 {
1648         struct net_device *netdev = adapter->netdev;
1649         int err;
1650         int flags;
1651
1652         flags = IRQF_SHARED;
1653         adapter->have_msi = false;
1654         err = pci_enable_msi(adapter->pdev);
1655         pr_debug("call pci_enable_msi\n");
1656         if (err) {
1657                 pr_debug("call pci_enable_msi - Error: %d\n", err);
1658         } else {
1659                 flags = 0;
1660                 adapter->have_msi = true;
1661         }
1662         err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1663                           flags, netdev->name, netdev);
1664         if (err)
1665                 pr_err("Unable to allocate interrupt Error: %d\n", err);
1666         pr_debug("adapter->have_msi : %d  flags : 0x%04x  return : 0x%04x\n",
1667                  adapter->have_msi, flags, err);
1668         return err;
1669 }
1670
1671
1672 static void pch_gbe_set_multi(struct net_device *netdev);
1673 /**
1674  * pch_gbe_up - Up GbE network device
1675  * @adapter:  Board private structure
1676  * Returns
1677  *      0:              Successfully
1678  *      Negative value: Failed
1679  */
1680 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1681 {
1682         struct net_device *netdev = adapter->netdev;
1683         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1684         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1685         int err;
1686
1687         /* hardware has been reset, we need to reload some things */
1688         pch_gbe_set_multi(netdev);
1689
1690         pch_gbe_setup_tctl(adapter);
1691         pch_gbe_configure_tx(adapter);
1692         pch_gbe_setup_rctl(adapter);
1693         pch_gbe_configure_rx(adapter);
1694
1695         err = pch_gbe_request_irq(adapter);
1696         if (err) {
1697                 pr_err("Error: can't bring device up\n");
1698                 return err;
1699         }
1700         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1701         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1702         adapter->tx_queue_len = netdev->tx_queue_len;
1703
1704         mod_timer(&adapter->watchdog_timer, jiffies);
1705
1706         napi_enable(&adapter->napi);
1707         pch_gbe_irq_enable(adapter);
1708         netif_start_queue(adapter->netdev);
1709
1710         return 0;
1711 }
1712
1713 /**
1714  * pch_gbe_down - Down GbE network device
1715  * @adapter:  Board private structure
1716  */
1717 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1718 {
1719         struct net_device *netdev = adapter->netdev;
1720
1721         /* signal that we're down so the interrupt handler does not
1722          * reschedule our watchdog timer */
1723         napi_disable(&adapter->napi);
1724         atomic_set(&adapter->irq_sem, 0);
1725
1726         pch_gbe_irq_disable(adapter);
1727         pch_gbe_free_irq(adapter);
1728
1729         del_timer_sync(&adapter->watchdog_timer);
1730
1731         netdev->tx_queue_len = adapter->tx_queue_len;
1732         netif_carrier_off(netdev);
1733         netif_stop_queue(netdev);
1734
1735         pch_gbe_reset(adapter);
1736         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1737         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1738 }
1739
1740 /**
1741  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1742  * @adapter:  Board private structure to initialize
1743  * Returns
1744  *      0:              Successfully
1745  *      Negative value: Failed
1746  */
1747 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1748 {
1749         struct pch_gbe_hw *hw = &adapter->hw;
1750         struct net_device *netdev = adapter->netdev;
1751
1752         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1753         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1754         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1755
1756         /* Initialize the hardware-specific values */
1757         if (pch_gbe_hal_setup_init_funcs(hw)) {
1758                 pr_err("Hardware Initialization Failure\n");
1759                 return -EIO;
1760         }
1761         if (pch_gbe_alloc_queues(adapter)) {
1762                 pr_err("Unable to allocate memory for queues\n");
1763                 return -ENOMEM;
1764         }
1765         spin_lock_init(&adapter->hw.miim_lock);
1766         spin_lock_init(&adapter->tx_queue_lock);
1767         spin_lock_init(&adapter->stats_lock);
1768         spin_lock_init(&adapter->ethtool_lock);
1769         atomic_set(&adapter->irq_sem, 0);
1770         pch_gbe_irq_disable(adapter);
1771
1772         pch_gbe_init_stats(adapter);
1773
1774         pr_debug("rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
1775                  (u32) adapter->rx_buffer_len,
1776                  hw->mac.min_frame_size, hw->mac.max_frame_size);
1777         return 0;
1778 }
1779
1780 /**
1781  * pch_gbe_open - Called when a network interface is made active
1782  * @netdev:     Network interface device structure
1783  * Returns
1784  *      0:              Successfully
1785  *      Negative value: Failed
1786  */
1787 static int pch_gbe_open(struct net_device *netdev)
1788 {
1789         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1790         struct pch_gbe_hw *hw = &adapter->hw;
1791         int err;
1792
1793         /* allocate transmit descriptors */
1794         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1795         if (err)
1796                 goto err_setup_tx;
1797         /* allocate receive descriptors */
1798         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1799         if (err)
1800                 goto err_setup_rx;
1801         pch_gbe_hal_power_up_phy(hw);
1802         err = pch_gbe_up(adapter);
1803         if (err)
1804                 goto err_up;
1805         pr_debug("Success End\n");
1806         return 0;
1807
1808 err_up:
1809         if (!adapter->wake_up_evt)
1810                 pch_gbe_hal_power_down_phy(hw);
1811         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1812 err_setup_rx:
1813         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1814 err_setup_tx:
1815         pch_gbe_reset(adapter);
1816         pr_err("Error End\n");
1817         return err;
1818 }
1819
1820 /**
1821  * pch_gbe_stop - Disables a network interface
1822  * @netdev:  Network interface device structure
1823  * Returns
1824  *      0: Successfully
1825  */
1826 static int pch_gbe_stop(struct net_device *netdev)
1827 {
1828         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1829         struct pch_gbe_hw *hw = &adapter->hw;
1830
1831         pch_gbe_down(adapter);
1832         if (!adapter->wake_up_evt)
1833                 pch_gbe_hal_power_down_phy(hw);
1834         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1835         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1836         return 0;
1837 }
1838
1839 /**
1840  * pch_gbe_xmit_frame - Packet transmitting start
1841  * @skb:     Socket buffer structure
1842  * @netdev:  Network interface device structure
1843  * Returns
1844  *      - NETDEV_TX_OK:   Normal end
1845  *      - NETDEV_TX_BUSY: Error end
1846  */
1847 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1848 {
1849         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1850         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1851         unsigned long flags;
1852
1853         if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
1854                 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1855                        skb->len, adapter->hw.mac.max_frame_size);
1856                 dev_kfree_skb_any(skb);
1857                 adapter->stats.tx_length_errors++;
1858                 return NETDEV_TX_OK;
1859         }
1860         if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1861                 /* Collision - tell upper layer to requeue */
1862                 return NETDEV_TX_LOCKED;
1863         }
1864         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1865                 netif_stop_queue(netdev);
1866                 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1867                 pr_debug("Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
1868                          tx_ring->next_to_use, tx_ring->next_to_clean);
1869                 return NETDEV_TX_BUSY;
1870         }
1871         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1872
1873         /* CRC,ITAG no support */
1874         pch_gbe_tx_queue(adapter, tx_ring, skb);
1875         return NETDEV_TX_OK;
1876 }
1877
1878 /**
1879  * pch_gbe_get_stats - Get System Network Statistics
1880  * @netdev:  Network interface device structure
1881  * Returns:  The current stats
1882  */
1883 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1884 {
1885         /* only return the current stats */
1886         return &netdev->stats;
1887 }
1888
1889 /**
1890  * pch_gbe_set_multi - Multicast and Promiscuous mode set
1891  * @netdev:   Network interface device structure
1892  */
1893 static void pch_gbe_set_multi(struct net_device *netdev)
1894 {
1895         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1896         struct pch_gbe_hw *hw = &adapter->hw;
1897         struct netdev_hw_addr *ha;
1898         u8 *mta_list;
1899         u32 rctl;
1900         int i;
1901         int mc_count;
1902
1903         pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1904
1905         /* Check for Promiscuous and All Multicast modes */
1906         rctl = ioread32(&hw->reg->RX_MODE);
1907         mc_count = netdev_mc_count(netdev);
1908         if ((netdev->flags & IFF_PROMISC)) {
1909                 rctl &= ~PCH_GBE_ADD_FIL_EN;
1910                 rctl &= ~PCH_GBE_MLT_FIL_EN;
1911         } else if ((netdev->flags & IFF_ALLMULTI)) {
1912                 /* all the multicasting receive permissions */
1913                 rctl |= PCH_GBE_ADD_FIL_EN;
1914                 rctl &= ~PCH_GBE_MLT_FIL_EN;
1915         } else {
1916                 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1917                         /* all the multicasting receive permissions */
1918                         rctl |= PCH_GBE_ADD_FIL_EN;
1919                         rctl &= ~PCH_GBE_MLT_FIL_EN;
1920                 } else {
1921                         rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1922                 }
1923         }
1924         iowrite32(rctl, &hw->reg->RX_MODE);
1925
1926         if (mc_count >= PCH_GBE_MAR_ENTRIES)
1927                 return;
1928         mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1929         if (!mta_list)
1930                 return;
1931
1932         /* The shared function expects a packed array of only addresses. */
1933         i = 0;
1934         netdev_for_each_mc_addr(ha, netdev) {
1935                 if (i == mc_count)
1936                         break;
1937                 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1938         }
1939         pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1940                                         PCH_GBE_MAR_ENTRIES);
1941         kfree(mta_list);
1942
1943         pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
1944                  ioread32(&hw->reg->RX_MODE), mc_count);
1945 }
1946
1947 /**
1948  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1949  * @netdev: Network interface device structure
1950  * @addr:   Pointer to an address structure
1951  * Returns
1952  *      0:              Successfully
1953  *      -EADDRNOTAVAIL: Failed
1954  */
1955 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1956 {
1957         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1958         struct sockaddr *skaddr = addr;
1959         int ret_val;
1960
1961         if (!is_valid_ether_addr(skaddr->sa_data)) {
1962                 ret_val = -EADDRNOTAVAIL;
1963         } else {
1964                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1965                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1966                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1967                 ret_val = 0;
1968         }
1969         pr_debug("ret_val : 0x%08x\n", ret_val);
1970         pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1971         pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1972         pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1973                  ioread32(&adapter->hw.reg->mac_adr[0].high),
1974                  ioread32(&adapter->hw.reg->mac_adr[0].low));
1975         return ret_val;
1976 }
1977
1978 /**
1979  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1980  * @netdev:   Network interface device structure
1981  * @new_mtu:  New value for maximum frame size
1982  * Returns
1983  *      0:              Successfully
1984  *      -EINVAL:        Failed
1985  */
1986 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
1987 {
1988         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1989         int max_frame;
1990
1991         max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1992         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
1993                 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
1994                 pr_err("Invalid MTU setting\n");
1995                 return -EINVAL;
1996         }
1997         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
1998                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1999         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2000                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2001         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2002                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2003         else
2004                 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
2005         netdev->mtu = new_mtu;
2006         adapter->hw.mac.max_frame_size = max_frame;
2007
2008         if (netif_running(netdev))
2009                 pch_gbe_reinit_locked(adapter);
2010         else
2011                 pch_gbe_reset(adapter);
2012
2013         pr_debug("max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2014                  max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2015                  adapter->hw.mac.max_frame_size);
2016         return 0;
2017 }
2018
2019 /**
2020  * pch_gbe_ioctl - Controls register through a MII interface
2021  * @netdev:   Network interface device structure
2022  * @ifr:      Pointer to ifr structure
2023  * @cmd:      Control command
2024  * Returns
2025  *      0:      Successfully
2026  *      Negative value: Failed
2027  */
2028 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2029 {
2030         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2031
2032         pr_debug("cmd : 0x%04x\n", cmd);
2033
2034         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2035 }
2036
2037 /**
2038  * pch_gbe_tx_timeout - Respond to a Tx Hang
2039  * @netdev:   Network interface device structure
2040  */
2041 static void pch_gbe_tx_timeout(struct net_device *netdev)
2042 {
2043         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2044
2045         /* Do the reset outside of interrupt context */
2046         adapter->stats.tx_timeout_count++;
2047         schedule_work(&adapter->reset_task);
2048 }
2049
2050 /**
2051  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2052  * @napi:    Pointer of polling device struct
2053  * @budget:  The maximum number of a packet
2054  * Returns
2055  *      false:  Exit the polling mode
2056  *      true:   Continue the polling mode
2057  */
2058 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2059 {
2060         struct pch_gbe_adapter *adapter =
2061             container_of(napi, struct pch_gbe_adapter, napi);
2062         struct net_device *netdev = adapter->netdev;
2063         int work_done = 0;
2064         bool poll_end_flag = false;
2065         bool cleaned = false;
2066
2067         pr_debug("budget : %d\n", budget);
2068
2069         /* Keep link state information with original netdev */
2070         if (!netif_carrier_ok(netdev)) {
2071                 poll_end_flag = true;
2072         } else {
2073                 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2074                 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2075
2076                 if (cleaned)
2077                         work_done = budget;
2078                 /* If no Tx and not enough Rx work done,
2079                  * exit the polling mode
2080                  */
2081                 if ((work_done < budget) || !netif_running(netdev))
2082                         poll_end_flag = true;
2083         }
2084
2085         if (poll_end_flag) {
2086                 napi_complete(napi);
2087                 pch_gbe_irq_enable(adapter);
2088         }
2089
2090         pr_debug("poll_end_flag : %d  work_done : %d  budget : %d\n",
2091                  poll_end_flag, work_done, budget);
2092
2093         return work_done;
2094 }
2095
2096 #ifdef CONFIG_NET_POLL_CONTROLLER
2097 /**
2098  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2099  * @netdev:  Network interface device structure
2100  */
2101 static void pch_gbe_netpoll(struct net_device *netdev)
2102 {
2103         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2104
2105         disable_irq(adapter->pdev->irq);
2106         pch_gbe_intr(adapter->pdev->irq, netdev);
2107         enable_irq(adapter->pdev->irq);
2108 }
2109 #endif
2110
2111 static const struct net_device_ops pch_gbe_netdev_ops = {
2112         .ndo_open = pch_gbe_open,
2113         .ndo_stop = pch_gbe_stop,
2114         .ndo_start_xmit = pch_gbe_xmit_frame,
2115         .ndo_get_stats = pch_gbe_get_stats,
2116         .ndo_set_mac_address = pch_gbe_set_mac,
2117         .ndo_tx_timeout = pch_gbe_tx_timeout,
2118         .ndo_change_mtu = pch_gbe_change_mtu,
2119         .ndo_do_ioctl = pch_gbe_ioctl,
2120         .ndo_set_multicast_list = &pch_gbe_set_multi,
2121 #ifdef CONFIG_NET_POLL_CONTROLLER
2122         .ndo_poll_controller = pch_gbe_netpoll,
2123 #endif
2124 };
2125
2126 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2127                                                 pci_channel_state_t state)
2128 {
2129         struct net_device *netdev = pci_get_drvdata(pdev);
2130         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2131
2132         netif_device_detach(netdev);
2133         if (netif_running(netdev))
2134                 pch_gbe_down(adapter);
2135         pci_disable_device(pdev);
2136         /* Request a slot slot reset. */
2137         return PCI_ERS_RESULT_NEED_RESET;
2138 }
2139
2140 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2141 {
2142         struct net_device *netdev = pci_get_drvdata(pdev);
2143         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2144         struct pch_gbe_hw *hw = &adapter->hw;
2145
2146         if (pci_enable_device(pdev)) {
2147                 pr_err("Cannot re-enable PCI device after reset\n");
2148                 return PCI_ERS_RESULT_DISCONNECT;
2149         }
2150         pci_set_master(pdev);
2151         pci_enable_wake(pdev, PCI_D0, 0);
2152         pch_gbe_hal_power_up_phy(hw);
2153         pch_gbe_reset(adapter);
2154         /* Clear wake up status */
2155         pch_gbe_mac_set_wol_event(hw, 0);
2156
2157         return PCI_ERS_RESULT_RECOVERED;
2158 }
2159
2160 static void pch_gbe_io_resume(struct pci_dev *pdev)
2161 {
2162         struct net_device *netdev = pci_get_drvdata(pdev);
2163         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2164
2165         if (netif_running(netdev)) {
2166                 if (pch_gbe_up(adapter)) {
2167                         pr_debug("can't bring device back up after reset\n");
2168                         return;
2169                 }
2170         }
2171         netif_device_attach(netdev);
2172 }
2173
2174 static int __pch_gbe_suspend(struct pci_dev *pdev)
2175 {
2176         struct net_device *netdev = pci_get_drvdata(pdev);
2177         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2178         struct pch_gbe_hw *hw = &adapter->hw;
2179         u32 wufc = adapter->wake_up_evt;
2180         int retval = 0;
2181
2182         netif_device_detach(netdev);
2183         if (netif_running(netdev))
2184                 pch_gbe_down(adapter);
2185         if (wufc) {
2186                 pch_gbe_set_multi(netdev);
2187                 pch_gbe_setup_rctl(adapter);
2188                 pch_gbe_configure_rx(adapter);
2189                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2190                                         hw->mac.link_duplex);
2191                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2192                                         hw->mac.link_duplex);
2193                 pch_gbe_mac_set_wol_event(hw, wufc);
2194                 pci_disable_device(pdev);
2195         } else {
2196                 pch_gbe_hal_power_down_phy(hw);
2197                 pch_gbe_mac_set_wol_event(hw, wufc);
2198                 pci_disable_device(pdev);
2199         }
2200         return retval;
2201 }
2202
2203 #ifdef CONFIG_PM
2204 static int pch_gbe_suspend(struct device *device)
2205 {
2206         struct pci_dev *pdev = to_pci_dev(device);
2207
2208         return __pch_gbe_suspend(pdev);
2209 }
2210
2211 static int pch_gbe_resume(struct device *device)
2212 {
2213         struct pci_dev *pdev = to_pci_dev(device);
2214         struct net_device *netdev = pci_get_drvdata(pdev);
2215         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2216         struct pch_gbe_hw *hw = &adapter->hw;
2217         u32 err;
2218
2219         err = pci_enable_device(pdev);
2220         if (err) {
2221                 pr_err("Cannot enable PCI device from suspend\n");
2222                 return err;
2223         }
2224         pci_set_master(pdev);
2225         pch_gbe_hal_power_up_phy(hw);
2226         pch_gbe_reset(adapter);
2227         /* Clear wake on lan control and status */
2228         pch_gbe_mac_set_wol_event(hw, 0);
2229
2230         if (netif_running(netdev))
2231                 pch_gbe_up(adapter);
2232         netif_device_attach(netdev);
2233
2234         return 0;
2235 }
2236 #endif /* CONFIG_PM */
2237
2238 static void pch_gbe_shutdown(struct pci_dev *pdev)
2239 {
2240         __pch_gbe_suspend(pdev);
2241         if (system_state == SYSTEM_POWER_OFF) {
2242                 pci_wake_from_d3(pdev, true);
2243                 pci_set_power_state(pdev, PCI_D3hot);
2244         }
2245 }
2246
2247 static void pch_gbe_remove(struct pci_dev *pdev)
2248 {
2249         struct net_device *netdev = pci_get_drvdata(pdev);
2250         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2251
2252         flush_scheduled_work();
2253         unregister_netdev(netdev);
2254
2255         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2256
2257         kfree(adapter->tx_ring);
2258         kfree(adapter->rx_ring);
2259
2260         iounmap(adapter->hw.reg);
2261         pci_release_regions(pdev);
2262         free_netdev(netdev);
2263         pci_disable_device(pdev);
2264 }
2265
2266 static int pch_gbe_probe(struct pci_dev *pdev,
2267                           const struct pci_device_id *pci_id)
2268 {
2269         struct net_device *netdev;
2270         struct pch_gbe_adapter *adapter;
2271         int ret;
2272
2273         ret = pci_enable_device(pdev);
2274         if (ret)
2275                 return ret;
2276
2277         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2278                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2279                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2280                 if (ret) {
2281                         ret = pci_set_consistent_dma_mask(pdev,
2282                                                           DMA_BIT_MASK(32));
2283                         if (ret) {
2284                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2285                                         "configuration, aborting\n");
2286                                 goto err_disable_device;
2287                         }
2288                 }
2289         }
2290
2291         ret = pci_request_regions(pdev, KBUILD_MODNAME);
2292         if (ret) {
2293                 dev_err(&pdev->dev,
2294                         "ERR: Can't reserve PCI I/O and memory resources\n");
2295                 goto err_disable_device;
2296         }
2297         pci_set_master(pdev);
2298
2299         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2300         if (!netdev) {
2301                 ret = -ENOMEM;
2302                 dev_err(&pdev->dev,
2303                         "ERR: Can't allocate and set up an Ethernet device\n");
2304                 goto err_release_pci;
2305         }
2306         SET_NETDEV_DEV(netdev, &pdev->dev);
2307
2308         pci_set_drvdata(pdev, netdev);
2309         adapter = netdev_priv(netdev);
2310         adapter->netdev = netdev;
2311         adapter->pdev = pdev;
2312         adapter->hw.back = adapter;
2313         adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2314         if (!adapter->hw.reg) {
2315                 ret = -EIO;
2316                 dev_err(&pdev->dev, "Can't ioremap\n");
2317                 goto err_free_netdev;
2318         }
2319
2320         netdev->netdev_ops = &pch_gbe_netdev_ops;
2321         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2322         netif_napi_add(netdev, &adapter->napi,
2323                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2324         netdev->features = NETIF_F_HW_CSUM | NETIF_F_GRO;
2325         pch_gbe_set_ethtool_ops(netdev);
2326
2327         pch_gbe_mac_reset_hw(&adapter->hw);
2328
2329         /* setup the private structure */
2330         ret = pch_gbe_sw_init(adapter);
2331         if (ret)
2332                 goto err_iounmap;
2333
2334         /* Initialize PHY */
2335         ret = pch_gbe_init_phy(adapter);
2336         if (ret) {
2337                 dev_err(&pdev->dev, "PHY initialize error\n");
2338                 goto err_free_adapter;
2339         }
2340         pch_gbe_hal_get_bus_info(&adapter->hw);
2341
2342         /* Read the MAC address. and store to the private data */
2343         ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2344         if (ret) {
2345                 dev_err(&pdev->dev, "MAC address Read Error\n");
2346                 goto err_free_adapter;
2347         }
2348
2349         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2350         if (!is_valid_ether_addr(netdev->dev_addr)) {
2351                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2352                 ret = -EIO;
2353                 goto err_free_adapter;
2354         }
2355         setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2356                     (unsigned long)adapter);
2357
2358         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2359
2360         pch_gbe_check_options(adapter);
2361
2362         if (adapter->tx_csum)
2363                 netdev->features |= NETIF_F_HW_CSUM;
2364         else
2365                 netdev->features &= ~NETIF_F_HW_CSUM;
2366
2367         /* initialize the wol settings based on the eeprom settings */
2368         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2369         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2370
2371         /* reset the hardware with the new settings */
2372         pch_gbe_reset(adapter);
2373
2374         ret = register_netdev(netdev);
2375         if (ret)
2376                 goto err_free_adapter;
2377         /* tell the stack to leave us alone until pch_gbe_open() is called */
2378         netif_carrier_off(netdev);
2379         netif_stop_queue(netdev);
2380
2381         dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2382
2383         device_set_wakeup_enable(&pdev->dev, 1);
2384         return 0;
2385
2386 err_free_adapter:
2387         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2388         kfree(adapter->tx_ring);
2389         kfree(adapter->rx_ring);
2390 err_iounmap:
2391         iounmap(adapter->hw.reg);
2392 err_free_netdev:
2393         free_netdev(netdev);
2394 err_release_pci:
2395         pci_release_regions(pdev);
2396 err_disable_device:
2397         pci_disable_device(pdev);
2398         return ret;
2399 }
2400
2401 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2402         {.vendor = PCI_VENDOR_ID_INTEL,
2403          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2404          .subvendor = PCI_ANY_ID,
2405          .subdevice = PCI_ANY_ID,
2406          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2407          .class_mask = (0xFFFF00)
2408          },
2409         /* required last entry */
2410         {0}
2411 };
2412
2413 #ifdef CONFIG_PM
2414 static const struct dev_pm_ops pch_gbe_pm_ops = {
2415         .suspend = pch_gbe_suspend,
2416         .resume = pch_gbe_resume,
2417         .freeze = pch_gbe_suspend,
2418         .thaw = pch_gbe_resume,
2419         .poweroff = pch_gbe_suspend,
2420         .restore = pch_gbe_resume,
2421 };
2422 #endif
2423
2424 static struct pci_error_handlers pch_gbe_err_handler = {
2425         .error_detected = pch_gbe_io_error_detected,
2426         .slot_reset = pch_gbe_io_slot_reset,
2427         .resume = pch_gbe_io_resume
2428 };
2429
2430 static struct pci_driver pch_gbe_pcidev = {
2431         .name = KBUILD_MODNAME,
2432         .id_table = pch_gbe_pcidev_id,
2433         .probe = pch_gbe_probe,
2434         .remove = pch_gbe_remove,
2435 #ifdef CONFIG_PM_OPS
2436         .driver.pm = &pch_gbe_pm_ops,
2437 #endif
2438         .shutdown = pch_gbe_shutdown,
2439         .err_handler = &pch_gbe_err_handler
2440 };
2441
2442
2443 static int __init pch_gbe_init_module(void)
2444 {
2445         int ret;
2446
2447         ret = pci_register_driver(&pch_gbe_pcidev);
2448         if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2449                 if (copybreak == 0) {
2450                         pr_info("copybreak disabled\n");
2451                 } else {
2452                         pr_info("copybreak enabled for packets <= %u bytes\n",
2453                                 copybreak);
2454                 }
2455         }
2456         return ret;
2457 }
2458
2459 static void __exit pch_gbe_exit_module(void)
2460 {
2461         pci_unregister_driver(&pch_gbe_pcidev);
2462 }
2463
2464 module_init(pch_gbe_init_module);
2465 module_exit(pch_gbe_exit_module);
2466
2467 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2468 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2469 MODULE_LICENSE("GPL");
2470 MODULE_VERSION(DRV_VERSION);
2471 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2472
2473 module_param(copybreak, uint, 0644);
2474 MODULE_PARM_DESC(copybreak,
2475         "Maximum size of packet that is copied to a new buffer on receive");
2476
2477 /* pch_gbe_main.c */