4c9a7d4f3fcabc0e63047e73ceaaaa18bc15b128
[~shefty/rdma-dev.git] / drivers / net / pch_gbe / pch_gbe_main.c
1 /*
2  * Copyright (C) 1999 - 2010 Intel Corporation.
3  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
4  *
5  * This code was derived from the Intel e1000e Linux driver.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
19  */
20
21 #include "pch_gbe.h"
22 #include "pch_gbe_api.h"
23
24 #define DRV_VERSION     "1.00"
25 const char pch_driver_version[] = DRV_VERSION;
26
27 #define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
28 #define PCH_GBE_MAR_ENTRIES             16
29 #define PCH_GBE_SHORT_PKT               64
30 #define DSC_INIT16                      0xC000
31 #define PCH_GBE_DMA_ALIGN               0
32 #define PCH_GBE_WATCHDOG_PERIOD         (1 * HZ)        /* watchdog time */
33 #define PCH_GBE_COPYBREAK_DEFAULT       256
34 #define PCH_GBE_PCI_BAR                 1
35
36 #define PCH_GBE_TX_WEIGHT         64
37 #define PCH_GBE_RX_WEIGHT         64
38 #define PCH_GBE_RX_BUFFER_WRITE   16
39
40 /* Initialize the wake-on-LAN settings */
41 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
42
43 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
44         PCH_GBE_CHIP_TYPE_INTERNAL | \
45         PCH_GBE_RGMII_MODE_RGMII   | \
46         PCH_GBE_CRS_SEL              \
47         )
48
49 /* Ethertype field values */
50 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
51 #define PCH_GBE_FRAME_SIZE_2048         2048
52 #define PCH_GBE_FRAME_SIZE_4096         4096
53 #define PCH_GBE_FRAME_SIZE_8192         8192
54
55 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
56 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
57 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
58 #define PCH_GBE_DESC_UNUSED(R) \
59         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60         (R)->next_to_clean - (R)->next_to_use - 1)
61
62 /* Pause packet value */
63 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
64 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
65 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
66 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
67
68 #define PCH_GBE_ETH_ALEN            6
69
70 /* This defines the bits that are set in the Interrupt Mask
71  * Set/Read Register.  Each bit is documented below:
72  *   o RXT0   = Receiver Timer Interrupt (ring 0)
73  *   o TXDW   = Transmit Descriptor Written Back
74  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
75  *   o RXSEQ  = Receive Sequence Error
76  *   o LSC    = Link Status Change
77  */
78 #define PCH_GBE_INT_ENABLE_MASK ( \
79         PCH_GBE_INT_RX_DMA_CMPLT |    \
80         PCH_GBE_INT_RX_DSC_EMP   |    \
81         PCH_GBE_INT_WOL_DET      |    \
82         PCH_GBE_INT_TX_CMPLT          \
83         )
84
85
86 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
87
88 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
89 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
90                                int data);
91 /**
92  * pch_gbe_mac_read_mac_addr - Read MAC address
93  * @hw:             Pointer to the HW structure
94  * Returns
95  *      0:                      Successful.
96  */
97 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
98 {
99         u32  adr1a, adr1b;
100
101         adr1a = ioread32(&hw->reg->mac_adr[0].high);
102         adr1b = ioread32(&hw->reg->mac_adr[0].low);
103
104         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
105         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
106         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
107         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
108         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
109         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
110
111         pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
112         return 0;
113 }
114
115 /**
116  * pch_gbe_wait_clr_bit - Wait to clear a bit
117  * @reg:        Pointer of register
118  * @busy:       Busy bit
119  */
120 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
121 {
122         u32 tmp;
123         /* wait busy */
124         tmp = 1000;
125         while ((ioread32(reg) & bit) && --tmp)
126                 cpu_relax();
127         if (!tmp)
128                 pr_err("Error: busy bit is not cleared\n");
129 }
130 /**
131  * pch_gbe_mac_mar_set - Set MAC address register
132  * @hw:     Pointer to the HW structure
133  * @addr:   Pointer to the MAC address
134  * @index:  MAC address array register
135  */
136 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
137 {
138         u32 mar_low, mar_high, adrmask;
139
140         pr_debug("index : 0x%x\n", index);
141
142         /*
143          * HW expects these in little endian so we reverse the byte order
144          * from network order (big endian) to little endian
145          */
146         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
147                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
148         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
149         /* Stop the MAC Address of index. */
150         adrmask = ioread32(&hw->reg->ADDR_MASK);
151         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
152         /* wait busy */
153         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
154         /* Set the MAC address to the MAC address 1A/1B register */
155         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
156         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
157         /* Start the MAC address of index */
158         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
159         /* wait busy */
160         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
161 }
162
163 /**
164  * pch_gbe_mac_reset_hw - Reset hardware
165  * @hw: Pointer to the HW structure
166  */
167 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
168 {
169         /* Read the MAC address. and store to the private data */
170         pch_gbe_mac_read_mac_addr(hw);
171         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
172 #ifdef PCH_GBE_MAC_IFOP_RGMII
173         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
174 #endif
175         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
176         /* Setup the receive address */
177         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
178         return;
179 }
180
181 /**
182  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
183  * @hw: Pointer to the HW structure
184  * @mar_count: Receive address registers
185  */
186 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
187 {
188         u32 i;
189
190         /* Setup the receive address */
191         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
192
193         /* Zero out the other receive addresses */
194         for (i = 1; i < mar_count; i++) {
195                 iowrite32(0, &hw->reg->mac_adr[i].high);
196                 iowrite32(0, &hw->reg->mac_adr[i].low);
197         }
198         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
199         /* wait busy */
200         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
201 }
202
203
204 /**
205  * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
206  * @hw:             Pointer to the HW structure
207  * @mc_addr_list:   Array of multicast addresses to program
208  * @mc_addr_count:  Number of multicast addresses to program
209  * @mar_used_count: The first MAC Address register free to program
210  * @mar_total_num:  Total number of supported MAC Address Registers
211  */
212 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
213                                             u8 *mc_addr_list, u32 mc_addr_count,
214                                             u32 mar_used_count, u32 mar_total_num)
215 {
216         u32 i, adrmask;
217
218         /* Load the first set of multicast addresses into the exact
219          * filters (RAR).  If there are not enough to fill the RAR
220          * array, clear the filters.
221          */
222         for (i = mar_used_count; i < mar_total_num; i++) {
223                 if (mc_addr_count) {
224                         pch_gbe_mac_mar_set(hw, mc_addr_list, i);
225                         mc_addr_count--;
226                         mc_addr_list += PCH_GBE_ETH_ALEN;
227                 } else {
228                         /* Clear MAC address mask */
229                         adrmask = ioread32(&hw->reg->ADDR_MASK);
230                         iowrite32((adrmask | (0x0001 << i)),
231                                         &hw->reg->ADDR_MASK);
232                         /* wait busy */
233                         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
234                         /* Clear MAC address */
235                         iowrite32(0, &hw->reg->mac_adr[i].high);
236                         iowrite32(0, &hw->reg->mac_adr[i].low);
237                 }
238         }
239 }
240
241 /**
242  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
243  * @hw:             Pointer to the HW structure
244  * Returns
245  *      0:                      Successful.
246  *      Negative value:         Failed.
247  */
248 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
249 {
250         struct pch_gbe_mac_info *mac = &hw->mac;
251         u32 rx_fctrl;
252
253         pr_debug("mac->fc = %u\n", mac->fc);
254
255         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
256
257         switch (mac->fc) {
258         case PCH_GBE_FC_NONE:
259                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
260                 mac->tx_fc_enable = false;
261                 break;
262         case PCH_GBE_FC_RX_PAUSE:
263                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
264                 mac->tx_fc_enable = false;
265                 break;
266         case PCH_GBE_FC_TX_PAUSE:
267                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
268                 mac->tx_fc_enable = true;
269                 break;
270         case PCH_GBE_FC_FULL:
271                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
272                 mac->tx_fc_enable = true;
273                 break;
274         default:
275                 pr_err("Flow control param set incorrectly\n");
276                 return -EINVAL;
277         }
278         if (mac->link_duplex == DUPLEX_HALF)
279                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
280         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
281         pr_debug("RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
282                  ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
283         return 0;
284 }
285
286 /**
287  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
288  * @hw:     Pointer to the HW structure
289  * @wu_evt: Wake up event
290  */
291 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
292 {
293         u32 addr_mask;
294
295         pr_debug("wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
296                  wu_evt, ioread32(&hw->reg->ADDR_MASK));
297
298         if (wu_evt) {
299                 /* Set Wake-On-Lan address mask */
300                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
301                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
302                 /* wait busy */
303                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
304                 iowrite32(0, &hw->reg->WOL_ST);
305                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
306                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
307                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
308         } else {
309                 iowrite32(0, &hw->reg->WOL_CTRL);
310                 iowrite32(0, &hw->reg->WOL_ST);
311         }
312         return;
313 }
314
315 /**
316  * pch_gbe_mac_ctrl_miim - Control MIIM interface
317  * @hw:   Pointer to the HW structure
318  * @addr: Address of PHY
319  * @dir:  Operetion. (Write or Read)
320  * @reg:  Access register of PHY
321  * @data: Write data.
322  *
323  * Returns: Read date.
324  */
325 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
326                         u16 data)
327 {
328         u32 data_out = 0;
329         unsigned int i;
330         unsigned long flags;
331
332         spin_lock_irqsave(&hw->miim_lock, flags);
333
334         for (i = 100; i; --i) {
335                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
336                         break;
337                 udelay(20);
338         }
339         if (i == 0) {
340                 pr_err("pch-gbe.miim won't go Ready\n");
341                 spin_unlock_irqrestore(&hw->miim_lock, flags);
342                 return 0;       /* No way to indicate timeout error */
343         }
344         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
345                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
346                   dir | data), &hw->reg->MIIM);
347         for (i = 0; i < 100; i++) {
348                 udelay(20);
349                 data_out = ioread32(&hw->reg->MIIM);
350                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
351                         break;
352         }
353         spin_unlock_irqrestore(&hw->miim_lock, flags);
354
355         pr_debug("PHY %s: reg=%d, data=0x%04X\n",
356                  dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
357                  dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
358         return (u16) data_out;
359 }
360
361 /**
362  * pch_gbe_mac_set_pause_packet - Set pause packet
363  * @hw:   Pointer to the HW structure
364  */
365 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
366 {
367         unsigned long tmp2, tmp3;
368
369         /* Set Pause packet */
370         tmp2 = hw->mac.addr[1];
371         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
372         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
373
374         tmp3 = hw->mac.addr[5];
375         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
376         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
377         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
378
379         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
380         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
381         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
382         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
383         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
384
385         /* Transmit Pause Packet */
386         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
387
388         pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
389                  ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
390                  ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
391                  ioread32(&hw->reg->PAUSE_PKT5));
392
393         return;
394 }
395
396
397 /**
398  * pch_gbe_alloc_queues - Allocate memory for all rings
399  * @adapter:  Board private structure to initialize
400  * Returns
401  *      0:      Successfully
402  *      Negative value: Failed
403  */
404 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
405 {
406         int size;
407
408         size = (int)sizeof(struct pch_gbe_tx_ring);
409         adapter->tx_ring = kzalloc(size, GFP_KERNEL);
410         if (!adapter->tx_ring)
411                 return -ENOMEM;
412         size = (int)sizeof(struct pch_gbe_rx_ring);
413         adapter->rx_ring = kzalloc(size, GFP_KERNEL);
414         if (!adapter->rx_ring) {
415                 kfree(adapter->tx_ring);
416                 return -ENOMEM;
417         }
418         return 0;
419 }
420
421 /**
422  * pch_gbe_init_stats - Initialize status
423  * @adapter:  Board private structure to initialize
424  */
425 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
426 {
427         memset(&adapter->stats, 0, sizeof(adapter->stats));
428         return;
429 }
430
431 /**
432  * pch_gbe_init_phy - Initialize PHY
433  * @adapter:  Board private structure to initialize
434  * Returns
435  *      0:      Successfully
436  *      Negative value: Failed
437  */
438 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
439 {
440         struct net_device *netdev = adapter->netdev;
441         u32 addr;
442         u16 bmcr, stat;
443
444         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
445         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
446                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
447                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
448                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
449                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
450                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
451                         break;
452         }
453         adapter->hw.phy.addr = adapter->mii.phy_id;
454         pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
455         if (addr == 32)
456                 return -EAGAIN;
457         /* Selected the phy and isolate the rest */
458         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
459                 if (addr != adapter->mii.phy_id) {
460                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
461                                            BMCR_ISOLATE);
462                 } else {
463                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
464                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
465                                            bmcr & ~BMCR_ISOLATE);
466                 }
467         }
468
469         /* MII setup */
470         adapter->mii.phy_id_mask = 0x1F;
471         adapter->mii.reg_num_mask = 0x1F;
472         adapter->mii.dev = adapter->netdev;
473         adapter->mii.mdio_read = pch_gbe_mdio_read;
474         adapter->mii.mdio_write = pch_gbe_mdio_write;
475         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
476         return 0;
477 }
478
479 /**
480  * pch_gbe_mdio_read - The read function for mii
481  * @netdev: Network interface device structure
482  * @addr:   Phy ID
483  * @reg:    Access location
484  * Returns
485  *      0:      Successfully
486  *      Negative value: Failed
487  */
488 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
489 {
490         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
491         struct pch_gbe_hw *hw = &adapter->hw;
492
493         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
494                                      (u16) 0);
495 }
496
497 /**
498  * pch_gbe_mdio_write - The write function for mii
499  * @netdev: Network interface device structure
500  * @addr:   Phy ID (not used)
501  * @reg:    Access location
502  * @data:   Write data
503  */
504 static void pch_gbe_mdio_write(struct net_device *netdev,
505                                int addr, int reg, int data)
506 {
507         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
508         struct pch_gbe_hw *hw = &adapter->hw;
509
510         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
511 }
512
513 /**
514  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
515  * @work:  Pointer of board private structure
516  */
517 static void pch_gbe_reset_task(struct work_struct *work)
518 {
519         struct pch_gbe_adapter *adapter;
520         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
521
522         rtnl_lock();
523         pch_gbe_reinit_locked(adapter);
524         rtnl_unlock();
525 }
526
527 /**
528  * pch_gbe_reinit_locked- Re-initialization
529  * @adapter:  Board private structure
530  */
531 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
532 {
533         pch_gbe_down(adapter);
534         pch_gbe_up(adapter);
535 }
536
537 /**
538  * pch_gbe_reset - Reset GbE
539  * @adapter:  Board private structure
540  */
541 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
542 {
543         pch_gbe_mac_reset_hw(&adapter->hw);
544         /* Setup the receive address. */
545         pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
546         if (pch_gbe_hal_init_hw(&adapter->hw))
547                 pr_err("Hardware Error\n");
548 }
549
550 /**
551  * pch_gbe_free_irq - Free an interrupt
552  * @adapter:  Board private structure
553  */
554 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
555 {
556         struct net_device *netdev = adapter->netdev;
557
558         free_irq(adapter->pdev->irq, netdev);
559         if (adapter->have_msi) {
560                 pci_disable_msi(adapter->pdev);
561                 pr_debug("call pci_disable_msi\n");
562         }
563 }
564
565 /**
566  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
567  * @adapter:  Board private structure
568  */
569 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
570 {
571         struct pch_gbe_hw *hw = &adapter->hw;
572
573         atomic_inc(&adapter->irq_sem);
574         iowrite32(0, &hw->reg->INT_EN);
575         ioread32(&hw->reg->INT_ST);
576         synchronize_irq(adapter->pdev->irq);
577
578         pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
579 }
580
581 /**
582  * pch_gbe_irq_enable - Enable default interrupt generation settings
583  * @adapter:  Board private structure
584  */
585 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
586 {
587         struct pch_gbe_hw *hw = &adapter->hw;
588
589         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
590                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
591         ioread32(&hw->reg->INT_ST);
592         pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
593 }
594
595
596
597 /**
598  * pch_gbe_setup_tctl - configure the Transmit control registers
599  * @adapter:  Board private structure
600  */
601 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
602 {
603         struct pch_gbe_hw *hw = &adapter->hw;
604         u32 tx_mode, tcpip;
605
606         tx_mode = PCH_GBE_TM_LONG_PKT |
607                 PCH_GBE_TM_ST_AND_FD |
608                 PCH_GBE_TM_SHORT_PKT |
609                 PCH_GBE_TM_TH_TX_STRT_8 |
610                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
611
612         iowrite32(tx_mode, &hw->reg->TX_MODE);
613
614         tcpip = ioread32(&hw->reg->TCPIP_ACC);
615         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
616         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
617         return;
618 }
619
620 /**
621  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
622  * @adapter:  Board private structure
623  */
624 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
625 {
626         struct pch_gbe_hw *hw = &adapter->hw;
627         u32 tdba, tdlen, dctrl;
628
629         pr_debug("dma addr = 0x%08llx  size = 0x%08x\n",
630                  (unsigned long long)adapter->tx_ring->dma,
631                  adapter->tx_ring->size);
632
633         /* Setup the HW Tx Head and Tail descriptor pointers */
634         tdba = adapter->tx_ring->dma;
635         tdlen = adapter->tx_ring->size - 0x10;
636         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
637         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
638         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
639
640         /* Enables Transmission DMA */
641         dctrl = ioread32(&hw->reg->DMA_CTRL);
642         dctrl |= PCH_GBE_TX_DMA_EN;
643         iowrite32(dctrl, &hw->reg->DMA_CTRL);
644 }
645
646 /**
647  * pch_gbe_setup_rctl - Configure the receive control registers
648  * @adapter:  Board private structure
649  */
650 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
651 {
652         struct pch_gbe_hw *hw = &adapter->hw;
653         u32 rx_mode, tcpip;
654
655         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
656         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
657
658         iowrite32(rx_mode, &hw->reg->RX_MODE);
659
660         tcpip = ioread32(&hw->reg->TCPIP_ACC);
661
662         if (adapter->rx_csum) {
663                 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
664                 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
665         } else {
666                 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
667                 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
668         }
669         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
670         return;
671 }
672
673 /**
674  * pch_gbe_configure_rx - Configure Receive Unit after Reset
675  * @adapter:  Board private structure
676  */
677 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
678 {
679         struct pch_gbe_hw *hw = &adapter->hw;
680         u32 rdba, rdlen, rctl, rxdma;
681
682         pr_debug("dma adr = 0x%08llx  size = 0x%08x\n",
683                  (unsigned long long)adapter->rx_ring->dma,
684                  adapter->rx_ring->size);
685
686         pch_gbe_mac_force_mac_fc(hw);
687
688         /* Disables Receive MAC */
689         rctl = ioread32(&hw->reg->MAC_RX_EN);
690         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
691
692         /* Disables Receive DMA */
693         rxdma = ioread32(&hw->reg->DMA_CTRL);
694         rxdma &= ~PCH_GBE_RX_DMA_EN;
695         iowrite32(rxdma, &hw->reg->DMA_CTRL);
696
697         pr_debug("MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
698                  ioread32(&hw->reg->MAC_RX_EN),
699                  ioread32(&hw->reg->DMA_CTRL));
700
701         /* Setup the HW Rx Head and Tail Descriptor Pointers and
702          * the Base and Length of the Rx Descriptor Ring */
703         rdba = adapter->rx_ring->dma;
704         rdlen = adapter->rx_ring->size - 0x10;
705         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
706         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
707         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
708
709         /* Enables Receive DMA */
710         rxdma = ioread32(&hw->reg->DMA_CTRL);
711         rxdma |= PCH_GBE_RX_DMA_EN;
712         iowrite32(rxdma, &hw->reg->DMA_CTRL);
713         /* Enables Receive */
714         iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
715 }
716
717 /**
718  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
719  * @adapter:     Board private structure
720  * @buffer_info: Buffer information structure
721  */
722 static void pch_gbe_unmap_and_free_tx_resource(
723         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
724 {
725         if (buffer_info->mapped) {
726                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
727                                  buffer_info->length, DMA_TO_DEVICE);
728                 buffer_info->mapped = false;
729         }
730         if (buffer_info->skb) {
731                 dev_kfree_skb_any(buffer_info->skb);
732                 buffer_info->skb = NULL;
733         }
734 }
735
736 /**
737  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
738  * @adapter:      Board private structure
739  * @buffer_info:  Buffer information structure
740  */
741 static void pch_gbe_unmap_and_free_rx_resource(
742                                         struct pch_gbe_adapter *adapter,
743                                         struct pch_gbe_buffer *buffer_info)
744 {
745         if (buffer_info->mapped) {
746                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
747                                  buffer_info->length, DMA_FROM_DEVICE);
748                 buffer_info->mapped = false;
749         }
750         if (buffer_info->skb) {
751                 dev_kfree_skb_any(buffer_info->skb);
752                 buffer_info->skb = NULL;
753         }
754 }
755
756 /**
757  * pch_gbe_clean_tx_ring - Free Tx Buffers
758  * @adapter:  Board private structure
759  * @tx_ring:  Ring to be cleaned
760  */
761 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
762                                    struct pch_gbe_tx_ring *tx_ring)
763 {
764         struct pch_gbe_hw *hw = &adapter->hw;
765         struct pch_gbe_buffer *buffer_info;
766         unsigned long size;
767         unsigned int i;
768
769         /* Free all the Tx ring sk_buffs */
770         for (i = 0; i < tx_ring->count; i++) {
771                 buffer_info = &tx_ring->buffer_info[i];
772                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
773         }
774         pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
775
776         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
777         memset(tx_ring->buffer_info, 0, size);
778
779         /* Zero out the descriptor ring */
780         memset(tx_ring->desc, 0, tx_ring->size);
781         tx_ring->next_to_use = 0;
782         tx_ring->next_to_clean = 0;
783         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
784         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
785 }
786
787 /**
788  * pch_gbe_clean_rx_ring - Free Rx Buffers
789  * @adapter:  Board private structure
790  * @rx_ring:  Ring to free buffers from
791  */
792 static void
793 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
794                       struct pch_gbe_rx_ring *rx_ring)
795 {
796         struct pch_gbe_hw *hw = &adapter->hw;
797         struct pch_gbe_buffer *buffer_info;
798         unsigned long size;
799         unsigned int i;
800
801         /* Free all the Rx ring sk_buffs */
802         for (i = 0; i < rx_ring->count; i++) {
803                 buffer_info = &rx_ring->buffer_info[i];
804                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
805         }
806         pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
807         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
808         memset(rx_ring->buffer_info, 0, size);
809
810         /* Zero out the descriptor ring */
811         memset(rx_ring->desc, 0, rx_ring->size);
812         rx_ring->next_to_clean = 0;
813         rx_ring->next_to_use = 0;
814         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
815         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
816 }
817
818 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
819                                     u16 duplex)
820 {
821         struct pch_gbe_hw *hw = &adapter->hw;
822         unsigned long rgmii = 0;
823
824         /* Set the RGMII control. */
825 #ifdef PCH_GBE_MAC_IFOP_RGMII
826         switch (speed) {
827         case SPEED_10:
828                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
829                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
830                 break;
831         case SPEED_100:
832                 rgmii = (PCH_GBE_RGMII_RATE_25M |
833                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
834                 break;
835         case SPEED_1000:
836                 rgmii = (PCH_GBE_RGMII_RATE_125M |
837                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
838                 break;
839         }
840         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
841 #else   /* GMII */
842         rgmii = 0;
843         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
844 #endif
845 }
846 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
847                               u16 duplex)
848 {
849         struct net_device *netdev = adapter->netdev;
850         struct pch_gbe_hw *hw = &adapter->hw;
851         unsigned long mode = 0;
852
853         /* Set the communication mode */
854         switch (speed) {
855         case SPEED_10:
856                 mode = PCH_GBE_MODE_MII_ETHER;
857                 netdev->tx_queue_len = 10;
858                 break;
859         case SPEED_100:
860                 mode = PCH_GBE_MODE_MII_ETHER;
861                 netdev->tx_queue_len = 100;
862                 break;
863         case SPEED_1000:
864                 mode = PCH_GBE_MODE_GMII_ETHER;
865                 break;
866         }
867         if (duplex == DUPLEX_FULL)
868                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
869         else
870                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
871         iowrite32(mode, &hw->reg->MODE);
872 }
873
874 /**
875  * pch_gbe_watchdog - Watchdog process
876  * @data:  Board private structure
877  */
878 static void pch_gbe_watchdog(unsigned long data)
879 {
880         struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
881         struct net_device *netdev = adapter->netdev;
882         struct pch_gbe_hw *hw = &adapter->hw;
883         struct ethtool_cmd cmd;
884
885         pr_debug("right now = %ld\n", jiffies);
886
887         pch_gbe_update_stats(adapter);
888         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
889                 netdev->tx_queue_len = adapter->tx_queue_len;
890                 /* mii library handles link maintenance tasks */
891                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
892                         pr_err("ethtool get setting Error\n");
893                         mod_timer(&adapter->watchdog_timer,
894                                   round_jiffies(jiffies +
895                                                 PCH_GBE_WATCHDOG_PERIOD));
896                         return;
897                 }
898                 hw->mac.link_speed = cmd.speed;
899                 hw->mac.link_duplex = cmd.duplex;
900                 /* Set the RGMII control. */
901                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
902                                                 hw->mac.link_duplex);
903                 /* Set the communication mode */
904                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
905                                  hw->mac.link_duplex);
906                 netdev_dbg(netdev,
907                            "Link is Up %d Mbps %s-Duplex\n",
908                            cmd.speed,
909                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
910                 netif_carrier_on(netdev);
911                 netif_wake_queue(netdev);
912         } else if ((!mii_link_ok(&adapter->mii)) &&
913                    (netif_carrier_ok(netdev))) {
914                 netdev_dbg(netdev, "NIC Link is Down\n");
915                 hw->mac.link_speed = SPEED_10;
916                 hw->mac.link_duplex = DUPLEX_HALF;
917                 netif_carrier_off(netdev);
918                 netif_stop_queue(netdev);
919         }
920         mod_timer(&adapter->watchdog_timer,
921                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
922 }
923
924 /**
925  * pch_gbe_tx_queue - Carry out queuing of the transmission data
926  * @adapter:  Board private structure
927  * @tx_ring:  Tx descriptor ring structure
928  * @skb:      Sockt buffer structure
929  */
930 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
931                               struct pch_gbe_tx_ring *tx_ring,
932                               struct sk_buff *skb)
933 {
934         struct pch_gbe_hw *hw = &adapter->hw;
935         struct pch_gbe_tx_desc *tx_desc;
936         struct pch_gbe_buffer *buffer_info;
937         struct sk_buff *tmp_skb;
938         unsigned int frame_ctrl;
939         unsigned int ring_num;
940         unsigned long flags;
941
942         /*-- Set frame control --*/
943         frame_ctrl = 0;
944         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
945                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
946         if (unlikely(!adapter->tx_csum))
947                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
948
949         /* Performs checksum processing */
950         /*
951          * It is because the hardware accelerator does not support a checksum,
952          * when the received data size is less than 64 bytes.
953          */
954         if ((skb->len < PCH_GBE_SHORT_PKT) && (adapter->tx_csum)) {
955                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
956                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
957                 if (skb->protocol == htons(ETH_P_IP)) {
958                         struct iphdr *iph = ip_hdr(skb);
959                         unsigned int offset;
960                         iph->check = 0;
961                         iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
962                         offset = skb_transport_offset(skb);
963                         if (iph->protocol == IPPROTO_TCP) {
964                                 skb->csum = 0;
965                                 tcp_hdr(skb)->check = 0;
966                                 skb->csum = skb_checksum(skb, offset,
967                                                          skb->len - offset, 0);
968                                 tcp_hdr(skb)->check =
969                                         csum_tcpudp_magic(iph->saddr,
970                                                           iph->daddr,
971                                                           skb->len - offset,
972                                                           IPPROTO_TCP,
973                                                           skb->csum);
974                         } else if (iph->protocol == IPPROTO_UDP) {
975                                 skb->csum = 0;
976                                 udp_hdr(skb)->check = 0;
977                                 skb->csum =
978                                         skb_checksum(skb, offset,
979                                                      skb->len - offset, 0);
980                                 udp_hdr(skb)->check =
981                                         csum_tcpudp_magic(iph->saddr,
982                                                           iph->daddr,
983                                                           skb->len - offset,
984                                                           IPPROTO_UDP,
985                                                           skb->csum);
986                         }
987                 }
988         }
989         spin_lock_irqsave(&tx_ring->tx_lock, flags);
990         ring_num = tx_ring->next_to_use;
991         if (unlikely((ring_num + 1) == tx_ring->count))
992                 tx_ring->next_to_use = 0;
993         else
994                 tx_ring->next_to_use = ring_num + 1;
995
996         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
997         buffer_info = &tx_ring->buffer_info[ring_num];
998         tmp_skb = buffer_info->skb;
999
1000         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1001         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1002         tmp_skb->data[ETH_HLEN] = 0x00;
1003         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1004         tmp_skb->len = skb->len;
1005         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1006                (skb->len - ETH_HLEN));
1007         /*-- Set Buffer infomation --*/
1008         buffer_info->length = tmp_skb->len;
1009         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1010                                           buffer_info->length,
1011                                           DMA_TO_DEVICE);
1012         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1013                 pr_err("TX DMA map failed\n");
1014                 buffer_info->dma = 0;
1015                 buffer_info->time_stamp = 0;
1016                 tx_ring->next_to_use = ring_num;
1017                 return;
1018         }
1019         buffer_info->mapped = true;
1020         buffer_info->time_stamp = jiffies;
1021
1022         /*-- Set Tx descriptor --*/
1023         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1024         tx_desc->buffer_addr = (buffer_info->dma);
1025         tx_desc->length = (tmp_skb->len);
1026         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1027         tx_desc->tx_frame_ctrl = (frame_ctrl);
1028         tx_desc->gbec_status = (DSC_INIT16);
1029
1030         if (unlikely(++ring_num == tx_ring->count))
1031                 ring_num = 0;
1032
1033         /* Update software pointer of TX descriptor */
1034         iowrite32(tx_ring->dma +
1035                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1036                   &hw->reg->TX_DSC_SW_P);
1037         dev_kfree_skb_any(skb);
1038 }
1039
1040 /**
1041  * pch_gbe_update_stats - Update the board statistics counters
1042  * @adapter:  Board private structure
1043  */
1044 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1045 {
1046         struct net_device *netdev = adapter->netdev;
1047         struct pci_dev *pdev = adapter->pdev;
1048         struct pch_gbe_hw_stats *stats = &adapter->stats;
1049         unsigned long flags;
1050
1051         /*
1052          * Prevent stats update while adapter is being reset, or if the pci
1053          * connection is down.
1054          */
1055         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1056                 return;
1057
1058         spin_lock_irqsave(&adapter->stats_lock, flags);
1059
1060         /* Update device status "adapter->stats" */
1061         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1062         stats->tx_errors = stats->tx_length_errors +
1063             stats->tx_aborted_errors +
1064             stats->tx_carrier_errors + stats->tx_timeout_count;
1065
1066         /* Update network device status "adapter->net_stats" */
1067         netdev->stats.rx_packets = stats->rx_packets;
1068         netdev->stats.rx_bytes = stats->rx_bytes;
1069         netdev->stats.rx_dropped = stats->rx_dropped;
1070         netdev->stats.tx_packets = stats->tx_packets;
1071         netdev->stats.tx_bytes = stats->tx_bytes;
1072         netdev->stats.tx_dropped = stats->tx_dropped;
1073         /* Fill out the OS statistics structure */
1074         netdev->stats.multicast = stats->multicast;
1075         netdev->stats.collisions = stats->collisions;
1076         /* Rx Errors */
1077         netdev->stats.rx_errors = stats->rx_errors;
1078         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1079         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1080         /* Tx Errors */
1081         netdev->stats.tx_errors = stats->tx_errors;
1082         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1083         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1084
1085         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1086 }
1087
1088 /**
1089  * pch_gbe_intr - Interrupt Handler
1090  * @irq:   Interrupt number
1091  * @data:  Pointer to a network interface device structure
1092  * Returns
1093  *      - IRQ_HANDLED:  Our interrupt
1094  *      - IRQ_NONE:     Not our interrupt
1095  */
1096 static irqreturn_t pch_gbe_intr(int irq, void *data)
1097 {
1098         struct net_device *netdev = data;
1099         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1100         struct pch_gbe_hw *hw = &adapter->hw;
1101         u32 int_st;
1102         u32 int_en;
1103
1104         /* Check request status */
1105         int_st = ioread32(&hw->reg->INT_ST);
1106         int_st = int_st & ioread32(&hw->reg->INT_EN);
1107         /* When request status is no interruption factor */
1108         if (unlikely(!int_st))
1109                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1110         pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1111         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1112                 adapter->stats.intr_rx_frame_err_count++;
1113         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1114                 adapter->stats.intr_rx_fifo_err_count++;
1115         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1116                 adapter->stats.intr_rx_dma_err_count++;
1117         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1118                 adapter->stats.intr_tx_fifo_err_count++;
1119         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1120                 adapter->stats.intr_tx_dma_err_count++;
1121         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1122                 adapter->stats.intr_tcpip_err_count++;
1123         /* When Rx descriptor is empty  */
1124         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1125                 adapter->stats.intr_rx_dsc_empty_count++;
1126                 pr_err("Rx descriptor is empty\n");
1127                 int_en = ioread32(&hw->reg->INT_EN);
1128                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1129                 if (hw->mac.tx_fc_enable) {
1130                         /* Set Pause packet */
1131                         pch_gbe_mac_set_pause_packet(hw);
1132                 }
1133                 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1134                     == 0) {
1135                         return IRQ_HANDLED;
1136                 }
1137         }
1138
1139         /* When request status is Receive interruption */
1140         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1141                 if (likely(napi_schedule_prep(&adapter->napi))) {
1142                         /* Enable only Rx Descriptor empty */
1143                         atomic_inc(&adapter->irq_sem);
1144                         int_en = ioread32(&hw->reg->INT_EN);
1145                         int_en &=
1146                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1147                         iowrite32(int_en, &hw->reg->INT_EN);
1148                         /* Start polling for NAPI */
1149                         __napi_schedule(&adapter->napi);
1150                 }
1151         }
1152         pr_debug("return = 0x%08x  INT_EN reg = 0x%08x\n",
1153                  IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1154         return IRQ_HANDLED;
1155 }
1156
1157 /**
1158  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1159  * @adapter:       Board private structure
1160  * @rx_ring:       Rx descriptor ring
1161  * @cleaned_count: Cleaned count
1162  */
1163 static void
1164 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1165                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1166 {
1167         struct net_device *netdev = adapter->netdev;
1168         struct pci_dev *pdev = adapter->pdev;
1169         struct pch_gbe_hw *hw = &adapter->hw;
1170         struct pch_gbe_rx_desc *rx_desc;
1171         struct pch_gbe_buffer *buffer_info;
1172         struct sk_buff *skb;
1173         unsigned int i;
1174         unsigned int bufsz;
1175
1176         bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1177         i = rx_ring->next_to_use;
1178
1179         while ((cleaned_count--)) {
1180                 buffer_info = &rx_ring->buffer_info[i];
1181                 skb = buffer_info->skb;
1182                 if (skb) {
1183                         skb_trim(skb, 0);
1184                 } else {
1185                         skb = netdev_alloc_skb(netdev, bufsz);
1186                         if (unlikely(!skb)) {
1187                                 /* Better luck next round */
1188                                 adapter->stats.rx_alloc_buff_failed++;
1189                                 break;
1190                         }
1191                         /* 64byte align */
1192                         skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1193
1194                         buffer_info->skb = skb;
1195                         buffer_info->length = adapter->rx_buffer_len;
1196                 }
1197                 buffer_info->dma = dma_map_single(&pdev->dev,
1198                                                   skb->data,
1199                                                   buffer_info->length,
1200                                                   DMA_FROM_DEVICE);
1201                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1202                         dev_kfree_skb(skb);
1203                         buffer_info->skb = NULL;
1204                         buffer_info->dma = 0;
1205                         adapter->stats.rx_alloc_buff_failed++;
1206                         break; /* while !buffer_info->skb */
1207                 }
1208                 buffer_info->mapped = true;
1209                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1210                 rx_desc->buffer_addr = (buffer_info->dma);
1211                 rx_desc->gbec_status = DSC_INIT16;
1212
1213                 pr_debug("i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1214                          i, (unsigned long long)buffer_info->dma,
1215                          buffer_info->length);
1216
1217                 if (unlikely(++i == rx_ring->count))
1218                         i = 0;
1219         }
1220         if (likely(rx_ring->next_to_use != i)) {
1221                 rx_ring->next_to_use = i;
1222                 if (unlikely(i-- == 0))
1223                         i = (rx_ring->count - 1);
1224                 iowrite32(rx_ring->dma +
1225                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1226                           &hw->reg->RX_DSC_SW_P);
1227         }
1228         return;
1229 }
1230
1231 /**
1232  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1233  * @adapter:   Board private structure
1234  * @tx_ring:   Tx descriptor ring
1235  */
1236 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1237                                         struct pch_gbe_tx_ring *tx_ring)
1238 {
1239         struct pch_gbe_buffer *buffer_info;
1240         struct sk_buff *skb;
1241         unsigned int i;
1242         unsigned int bufsz;
1243         struct pch_gbe_tx_desc *tx_desc;
1244
1245         bufsz =
1246             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1247
1248         for (i = 0; i < tx_ring->count; i++) {
1249                 buffer_info = &tx_ring->buffer_info[i];
1250                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1251                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1252                 buffer_info->skb = skb;
1253                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1254                 tx_desc->gbec_status = (DSC_INIT16);
1255         }
1256         return;
1257 }
1258
1259 /**
1260  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1261  * @adapter:   Board private structure
1262  * @tx_ring:   Tx descriptor ring
1263  * Returns
1264  *      true:  Cleaned the descriptor
1265  *      false: Not cleaned the descriptor
1266  */
1267 static bool
1268 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1269                  struct pch_gbe_tx_ring *tx_ring)
1270 {
1271         struct pch_gbe_tx_desc *tx_desc;
1272         struct pch_gbe_buffer *buffer_info;
1273         struct sk_buff *skb;
1274         unsigned int i;
1275         unsigned int cleaned_count = 0;
1276         bool cleaned = false;
1277
1278         pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1279
1280         i = tx_ring->next_to_clean;
1281         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1282         pr_debug("gbec_status:0x%04x  dma_status:0x%04x\n",
1283                  tx_desc->gbec_status, tx_desc->dma_status);
1284
1285         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1286                 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1287                 cleaned = true;
1288                 buffer_info = &tx_ring->buffer_info[i];
1289                 skb = buffer_info->skb;
1290
1291                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1292                         adapter->stats.tx_aborted_errors++;
1293                         pr_err("Transfer Abort Error\n");
1294                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1295                           ) {
1296                         adapter->stats.tx_carrier_errors++;
1297                         pr_err("Transfer Carrier Sense Error\n");
1298                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1299                           ) {
1300                         adapter->stats.tx_aborted_errors++;
1301                         pr_err("Transfer Collision Abort Error\n");
1302                 } else if ((tx_desc->gbec_status &
1303                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1304                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1305                         adapter->stats.collisions++;
1306                         adapter->stats.tx_packets++;
1307                         adapter->stats.tx_bytes += skb->len;
1308                         pr_debug("Transfer Collision\n");
1309                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1310                           ) {
1311                         adapter->stats.tx_packets++;
1312                         adapter->stats.tx_bytes += skb->len;
1313                 }
1314                 if (buffer_info->mapped) {
1315                         pr_debug("unmap buffer_info->dma : %d\n", i);
1316                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1317                                          buffer_info->length, DMA_TO_DEVICE);
1318                         buffer_info->mapped = false;
1319                 }
1320                 if (buffer_info->skb) {
1321                         pr_debug("trim buffer_info->skb : %d\n", i);
1322                         skb_trim(buffer_info->skb, 0);
1323                 }
1324                 tx_desc->gbec_status = DSC_INIT16;
1325                 if (unlikely(++i == tx_ring->count))
1326                         i = 0;
1327                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1328
1329                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1330                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1331                         break;
1332         }
1333         pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1334                  cleaned_count);
1335         /* Recover from running out of Tx resources in xmit_frame */
1336         if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1337                 netif_wake_queue(adapter->netdev);
1338                 adapter->stats.tx_restart_count++;
1339                 pr_debug("Tx wake queue\n");
1340         }
1341         spin_lock(&adapter->tx_queue_lock);
1342         tx_ring->next_to_clean = i;
1343         spin_unlock(&adapter->tx_queue_lock);
1344         pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1345         return cleaned;
1346 }
1347
1348 /**
1349  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1350  * @adapter:     Board private structure
1351  * @rx_ring:     Rx descriptor ring
1352  * @work_done:   Completed count
1353  * @work_to_do:  Request count
1354  * Returns
1355  *      true:  Cleaned the descriptor
1356  *      false: Not cleaned the descriptor
1357  */
1358 static bool
1359 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1360                  struct pch_gbe_rx_ring *rx_ring,
1361                  int *work_done, int work_to_do)
1362 {
1363         struct net_device *netdev = adapter->netdev;
1364         struct pci_dev *pdev = adapter->pdev;
1365         struct pch_gbe_buffer *buffer_info;
1366         struct pch_gbe_rx_desc *rx_desc;
1367         u32 length;
1368         unsigned char tmp_packet[ETH_HLEN];
1369         unsigned int i;
1370         unsigned int cleaned_count = 0;
1371         bool cleaned = false;
1372         struct sk_buff *skb;
1373         u8 dma_status;
1374         u16 gbec_status;
1375         u32 tcp_ip_status;
1376         u8 skb_copy_flag = 0;
1377         u8 skb_padding_flag = 0;
1378
1379         i = rx_ring->next_to_clean;
1380
1381         while (*work_done < work_to_do) {
1382                 /* Check Rx descriptor status */
1383                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1384                 if (rx_desc->gbec_status == DSC_INIT16)
1385                         break;
1386                 cleaned = true;
1387                 cleaned_count++;
1388
1389                 dma_status = rx_desc->dma_status;
1390                 gbec_status = rx_desc->gbec_status;
1391                 tcp_ip_status = rx_desc->tcp_ip_status;
1392                 rx_desc->gbec_status = DSC_INIT16;
1393                 buffer_info = &rx_ring->buffer_info[i];
1394                 skb = buffer_info->skb;
1395
1396                 /* unmap dma */
1397                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1398                                    buffer_info->length, DMA_FROM_DEVICE);
1399                 buffer_info->mapped = false;
1400                 /* Prefetch the packet */
1401                 prefetch(skb->data);
1402
1403                 pr_debug("RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x "
1404                          "TCP:0x%08x]  BufInf = 0x%p\n",
1405                          i, dma_status, gbec_status, tcp_ip_status,
1406                          buffer_info);
1407                 /* Error check */
1408                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1409                         adapter->stats.rx_frame_errors++;
1410                         pr_err("Receive Not Octal Error\n");
1411                 } else if (unlikely(gbec_status &
1412                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1413                         adapter->stats.rx_frame_errors++;
1414                         pr_err("Receive Nibble Error\n");
1415                 } else if (unlikely(gbec_status &
1416                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1417                         adapter->stats.rx_crc_errors++;
1418                         pr_err("Receive CRC Error\n");
1419                 } else {
1420                         /* get receive length */
1421                         /* length convert[-3], padding[-2] */
1422                         length = (rx_desc->rx_words_eob) - 3 - 2;
1423
1424                         /* Decide the data conversion method */
1425                         if (!adapter->rx_csum) {
1426                                 /* [Header:14][payload] */
1427                                 skb_padding_flag = 0;
1428                                 skb_copy_flag = 1;
1429                         } else {
1430                                 /* [Header:14][padding:2][payload] */
1431                                 skb_padding_flag = 1;
1432                                 if (length < copybreak)
1433                                         skb_copy_flag = 1;
1434                                 else
1435                                         skb_copy_flag = 0;
1436                         }
1437
1438                         /* Data conversion */
1439                         if (skb_copy_flag) {    /* recycle  skb */
1440                                 struct sk_buff *new_skb;
1441                                 new_skb =
1442                                     netdev_alloc_skb(netdev,
1443                                                      length + NET_IP_ALIGN);
1444                                 if (new_skb) {
1445                                         if (!skb_padding_flag) {
1446                                                 skb_reserve(new_skb,
1447                                                                 NET_IP_ALIGN);
1448                                         }
1449                                         memcpy(new_skb->data, skb->data,
1450                                                 length);
1451                                         /* save the skb
1452                                          * in buffer_info as good */
1453                                         skb = new_skb;
1454                                 } else if (!skb_padding_flag) {
1455                                         /* dorrop error */
1456                                         pr_err("New skb allocation Error\n");
1457                                         goto dorrop;
1458                                 }
1459                         } else {
1460                                 buffer_info->skb = NULL;
1461                         }
1462                         if (skb_padding_flag) {
1463                                 memcpy(&tmp_packet[0], &skb->data[0], ETH_HLEN);
1464                                 memcpy(&skb->data[NET_IP_ALIGN], &tmp_packet[0],
1465                                         ETH_HLEN);
1466                                 skb_reserve(skb, NET_IP_ALIGN);
1467
1468                         }
1469
1470                         /* update status of driver */
1471                         adapter->stats.rx_bytes += length;
1472                         adapter->stats.rx_packets++;
1473                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1474                                 adapter->stats.multicast++;
1475                         /* Write meta date of skb */
1476                         skb_put(skb, length);
1477                         skb->protocol = eth_type_trans(skb, netdev);
1478                         if ((tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) ==
1479                             PCH_GBE_RXD_ACC_STAT_TCPIPOK) {
1480                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1481                         } else {
1482                                 skb->ip_summed = CHECKSUM_NONE;
1483                         }
1484                         napi_gro_receive(&adapter->napi, skb);
1485                         (*work_done)++;
1486                         pr_debug("Receive skb->ip_summed: %d length: %d\n",
1487                                  skb->ip_summed, length);
1488                 }
1489 dorrop:
1490                 /* return some buffers to hardware, one at a time is too slow */
1491                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1492                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1493                                                  cleaned_count);
1494                         cleaned_count = 0;
1495                 }
1496                 if (++i == rx_ring->count)
1497                         i = 0;
1498         }
1499         rx_ring->next_to_clean = i;
1500         if (cleaned_count)
1501                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1502         return cleaned;
1503 }
1504
1505 /**
1506  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1507  * @adapter:  Board private structure
1508  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1509  * Returns
1510  *      0:              Successfully
1511  *      Negative value: Failed
1512  */
1513 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1514                                 struct pch_gbe_tx_ring *tx_ring)
1515 {
1516         struct pci_dev *pdev = adapter->pdev;
1517         struct pch_gbe_tx_desc *tx_desc;
1518         int size;
1519         int desNo;
1520
1521         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1522         tx_ring->buffer_info = vzalloc(size);
1523         if (!tx_ring->buffer_info) {
1524                 pr_err("Unable to allocate memory for the buffer infomation\n");
1525                 return -ENOMEM;
1526         }
1527
1528         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1529
1530         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1531                                            &tx_ring->dma, GFP_KERNEL);
1532         if (!tx_ring->desc) {
1533                 vfree(tx_ring->buffer_info);
1534                 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1535                 return -ENOMEM;
1536         }
1537         memset(tx_ring->desc, 0, tx_ring->size);
1538
1539         tx_ring->next_to_use = 0;
1540         tx_ring->next_to_clean = 0;
1541         spin_lock_init(&tx_ring->tx_lock);
1542
1543         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1544                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1545                 tx_desc->gbec_status = DSC_INIT16;
1546         }
1547         pr_debug("tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx\n"
1548                  "next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1549                  tx_ring->desc, (unsigned long long)tx_ring->dma,
1550                  tx_ring->next_to_clean, tx_ring->next_to_use);
1551         return 0;
1552 }
1553
1554 /**
1555  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1556  * @adapter:  Board private structure
1557  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1558  * Returns
1559  *      0:              Successfully
1560  *      Negative value: Failed
1561  */
1562 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1563                                 struct pch_gbe_rx_ring *rx_ring)
1564 {
1565         struct pci_dev *pdev = adapter->pdev;
1566         struct pch_gbe_rx_desc *rx_desc;
1567         int size;
1568         int desNo;
1569
1570         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1571         rx_ring->buffer_info = vzalloc(size);
1572         if (!rx_ring->buffer_info) {
1573                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1574                 return -ENOMEM;
1575         }
1576         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1577         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1578                                            &rx_ring->dma, GFP_KERNEL);
1579
1580         if (!rx_ring->desc) {
1581                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1582                 vfree(rx_ring->buffer_info);
1583                 return -ENOMEM;
1584         }
1585         memset(rx_ring->desc, 0, rx_ring->size);
1586         rx_ring->next_to_clean = 0;
1587         rx_ring->next_to_use = 0;
1588         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1589                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1590                 rx_desc->gbec_status = DSC_INIT16;
1591         }
1592         pr_debug("rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx "
1593                  "next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1594                  rx_ring->desc, (unsigned long long)rx_ring->dma,
1595                  rx_ring->next_to_clean, rx_ring->next_to_use);
1596         return 0;
1597 }
1598
1599 /**
1600  * pch_gbe_free_tx_resources - Free Tx Resources
1601  * @adapter:  Board private structure
1602  * @tx_ring:  Tx descriptor ring for a specific queue
1603  */
1604 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1605                                 struct pch_gbe_tx_ring *tx_ring)
1606 {
1607         struct pci_dev *pdev = adapter->pdev;
1608
1609         pch_gbe_clean_tx_ring(adapter, tx_ring);
1610         vfree(tx_ring->buffer_info);
1611         tx_ring->buffer_info = NULL;
1612         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1613         tx_ring->desc = NULL;
1614 }
1615
1616 /**
1617  * pch_gbe_free_rx_resources - Free Rx Resources
1618  * @adapter:  Board private structure
1619  * @rx_ring:  Ring to clean the resources from
1620  */
1621 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1622                                 struct pch_gbe_rx_ring *rx_ring)
1623 {
1624         struct pci_dev *pdev = adapter->pdev;
1625
1626         pch_gbe_clean_rx_ring(adapter, rx_ring);
1627         vfree(rx_ring->buffer_info);
1628         rx_ring->buffer_info = NULL;
1629         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1630         rx_ring->desc = NULL;
1631 }
1632
1633 /**
1634  * pch_gbe_request_irq - Allocate an interrupt line
1635  * @adapter:  Board private structure
1636  * Returns
1637  *      0:              Successfully
1638  *      Negative value: Failed
1639  */
1640 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1641 {
1642         struct net_device *netdev = adapter->netdev;
1643         int err;
1644         int flags;
1645
1646         flags = IRQF_SHARED;
1647         adapter->have_msi = false;
1648         err = pci_enable_msi(adapter->pdev);
1649         pr_debug("call pci_enable_msi\n");
1650         if (err) {
1651                 pr_debug("call pci_enable_msi - Error: %d\n", err);
1652         } else {
1653                 flags = 0;
1654                 adapter->have_msi = true;
1655         }
1656         err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1657                           flags, netdev->name, netdev);
1658         if (err)
1659                 pr_err("Unable to allocate interrupt Error: %d\n", err);
1660         pr_debug("adapter->have_msi : %d  flags : 0x%04x  return : 0x%04x\n",
1661                  adapter->have_msi, flags, err);
1662         return err;
1663 }
1664
1665
1666 static void pch_gbe_set_multi(struct net_device *netdev);
1667 /**
1668  * pch_gbe_up - Up GbE network device
1669  * @adapter:  Board private structure
1670  * Returns
1671  *      0:              Successfully
1672  *      Negative value: Failed
1673  */
1674 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1675 {
1676         struct net_device *netdev = adapter->netdev;
1677         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1678         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1679         int err;
1680
1681         /* hardware has been reset, we need to reload some things */
1682         pch_gbe_set_multi(netdev);
1683
1684         pch_gbe_setup_tctl(adapter);
1685         pch_gbe_configure_tx(adapter);
1686         pch_gbe_setup_rctl(adapter);
1687         pch_gbe_configure_rx(adapter);
1688
1689         err = pch_gbe_request_irq(adapter);
1690         if (err) {
1691                 pr_err("Error: can't bring device up\n");
1692                 return err;
1693         }
1694         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1695         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1696         adapter->tx_queue_len = netdev->tx_queue_len;
1697
1698         mod_timer(&adapter->watchdog_timer, jiffies);
1699
1700         napi_enable(&adapter->napi);
1701         pch_gbe_irq_enable(adapter);
1702         netif_start_queue(adapter->netdev);
1703
1704         return 0;
1705 }
1706
1707 /**
1708  * pch_gbe_down - Down GbE network device
1709  * @adapter:  Board private structure
1710  */
1711 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1712 {
1713         struct net_device *netdev = adapter->netdev;
1714
1715         /* signal that we're down so the interrupt handler does not
1716          * reschedule our watchdog timer */
1717         napi_disable(&adapter->napi);
1718         atomic_set(&adapter->irq_sem, 0);
1719
1720         pch_gbe_irq_disable(adapter);
1721         pch_gbe_free_irq(adapter);
1722
1723         del_timer_sync(&adapter->watchdog_timer);
1724
1725         netdev->tx_queue_len = adapter->tx_queue_len;
1726         netif_carrier_off(netdev);
1727         netif_stop_queue(netdev);
1728
1729         pch_gbe_reset(adapter);
1730         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1731         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1732 }
1733
1734 /**
1735  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1736  * @adapter:  Board private structure to initialize
1737  * Returns
1738  *      0:              Successfully
1739  *      Negative value: Failed
1740  */
1741 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1742 {
1743         struct pch_gbe_hw *hw = &adapter->hw;
1744         struct net_device *netdev = adapter->netdev;
1745
1746         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1747         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1748         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1749
1750         /* Initialize the hardware-specific values */
1751         if (pch_gbe_hal_setup_init_funcs(hw)) {
1752                 pr_err("Hardware Initialization Failure\n");
1753                 return -EIO;
1754         }
1755         if (pch_gbe_alloc_queues(adapter)) {
1756                 pr_err("Unable to allocate memory for queues\n");
1757                 return -ENOMEM;
1758         }
1759         spin_lock_init(&adapter->hw.miim_lock);
1760         spin_lock_init(&adapter->tx_queue_lock);
1761         spin_lock_init(&adapter->stats_lock);
1762         spin_lock_init(&adapter->ethtool_lock);
1763         atomic_set(&adapter->irq_sem, 0);
1764         pch_gbe_irq_disable(adapter);
1765
1766         pch_gbe_init_stats(adapter);
1767
1768         pr_debug("rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
1769                  (u32) adapter->rx_buffer_len,
1770                  hw->mac.min_frame_size, hw->mac.max_frame_size);
1771         return 0;
1772 }
1773
1774 /**
1775  * pch_gbe_open - Called when a network interface is made active
1776  * @netdev:     Network interface device structure
1777  * Returns
1778  *      0:              Successfully
1779  *      Negative value: Failed
1780  */
1781 static int pch_gbe_open(struct net_device *netdev)
1782 {
1783         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1784         struct pch_gbe_hw *hw = &adapter->hw;
1785         int err;
1786
1787         /* allocate transmit descriptors */
1788         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1789         if (err)
1790                 goto err_setup_tx;
1791         /* allocate receive descriptors */
1792         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1793         if (err)
1794                 goto err_setup_rx;
1795         pch_gbe_hal_power_up_phy(hw);
1796         err = pch_gbe_up(adapter);
1797         if (err)
1798                 goto err_up;
1799         pr_debug("Success End\n");
1800         return 0;
1801
1802 err_up:
1803         if (!adapter->wake_up_evt)
1804                 pch_gbe_hal_power_down_phy(hw);
1805         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1806 err_setup_rx:
1807         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1808 err_setup_tx:
1809         pch_gbe_reset(adapter);
1810         pr_err("Error End\n");
1811         return err;
1812 }
1813
1814 /**
1815  * pch_gbe_stop - Disables a network interface
1816  * @netdev:  Network interface device structure
1817  * Returns
1818  *      0: Successfully
1819  */
1820 static int pch_gbe_stop(struct net_device *netdev)
1821 {
1822         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1823         struct pch_gbe_hw *hw = &adapter->hw;
1824
1825         pch_gbe_down(adapter);
1826         if (!adapter->wake_up_evt)
1827                 pch_gbe_hal_power_down_phy(hw);
1828         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1829         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1830         return 0;
1831 }
1832
1833 /**
1834  * pch_gbe_xmit_frame - Packet transmitting start
1835  * @skb:     Socket buffer structure
1836  * @netdev:  Network interface device structure
1837  * Returns
1838  *      - NETDEV_TX_OK:   Normal end
1839  *      - NETDEV_TX_BUSY: Error end
1840  */
1841 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1842 {
1843         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1844         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1845         unsigned long flags;
1846
1847         if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
1848                 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1849                        skb->len, adapter->hw.mac.max_frame_size);
1850                 dev_kfree_skb_any(skb);
1851                 adapter->stats.tx_length_errors++;
1852                 return NETDEV_TX_OK;
1853         }
1854         if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1855                 /* Collision - tell upper layer to requeue */
1856                 return NETDEV_TX_LOCKED;
1857         }
1858         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1859                 netif_stop_queue(netdev);
1860                 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1861                 pr_debug("Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
1862                          tx_ring->next_to_use, tx_ring->next_to_clean);
1863                 return NETDEV_TX_BUSY;
1864         }
1865         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1866
1867         /* CRC,ITAG no support */
1868         pch_gbe_tx_queue(adapter, tx_ring, skb);
1869         return NETDEV_TX_OK;
1870 }
1871
1872 /**
1873  * pch_gbe_get_stats - Get System Network Statistics
1874  * @netdev:  Network interface device structure
1875  * Returns:  The current stats
1876  */
1877 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1878 {
1879         /* only return the current stats */
1880         return &netdev->stats;
1881 }
1882
1883 /**
1884  * pch_gbe_set_multi - Multicast and Promiscuous mode set
1885  * @netdev:   Network interface device structure
1886  */
1887 static void pch_gbe_set_multi(struct net_device *netdev)
1888 {
1889         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1890         struct pch_gbe_hw *hw = &adapter->hw;
1891         struct netdev_hw_addr *ha;
1892         u8 *mta_list;
1893         u32 rctl;
1894         int i;
1895         int mc_count;
1896
1897         pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1898
1899         /* Check for Promiscuous and All Multicast modes */
1900         rctl = ioread32(&hw->reg->RX_MODE);
1901         mc_count = netdev_mc_count(netdev);
1902         if ((netdev->flags & IFF_PROMISC)) {
1903                 rctl &= ~PCH_GBE_ADD_FIL_EN;
1904                 rctl &= ~PCH_GBE_MLT_FIL_EN;
1905         } else if ((netdev->flags & IFF_ALLMULTI)) {
1906                 /* all the multicasting receive permissions */
1907                 rctl |= PCH_GBE_ADD_FIL_EN;
1908                 rctl &= ~PCH_GBE_MLT_FIL_EN;
1909         } else {
1910                 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1911                         /* all the multicasting receive permissions */
1912                         rctl |= PCH_GBE_ADD_FIL_EN;
1913                         rctl &= ~PCH_GBE_MLT_FIL_EN;
1914                 } else {
1915                         rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1916                 }
1917         }
1918         iowrite32(rctl, &hw->reg->RX_MODE);
1919
1920         if (mc_count >= PCH_GBE_MAR_ENTRIES)
1921                 return;
1922         mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1923         if (!mta_list)
1924                 return;
1925
1926         /* The shared function expects a packed array of only addresses. */
1927         i = 0;
1928         netdev_for_each_mc_addr(ha, netdev) {
1929                 if (i == mc_count)
1930                         break;
1931                 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1932         }
1933         pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1934                                         PCH_GBE_MAR_ENTRIES);
1935         kfree(mta_list);
1936
1937         pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
1938                  ioread32(&hw->reg->RX_MODE), mc_count);
1939 }
1940
1941 /**
1942  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1943  * @netdev: Network interface device structure
1944  * @addr:   Pointer to an address structure
1945  * Returns
1946  *      0:              Successfully
1947  *      -EADDRNOTAVAIL: Failed
1948  */
1949 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1950 {
1951         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1952         struct sockaddr *skaddr = addr;
1953         int ret_val;
1954
1955         if (!is_valid_ether_addr(skaddr->sa_data)) {
1956                 ret_val = -EADDRNOTAVAIL;
1957         } else {
1958                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1959                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1960                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1961                 ret_val = 0;
1962         }
1963         pr_debug("ret_val : 0x%08x\n", ret_val);
1964         pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1965         pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1966         pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1967                  ioread32(&adapter->hw.reg->mac_adr[0].high),
1968                  ioread32(&adapter->hw.reg->mac_adr[0].low));
1969         return ret_val;
1970 }
1971
1972 /**
1973  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1974  * @netdev:   Network interface device structure
1975  * @new_mtu:  New value for maximum frame size
1976  * Returns
1977  *      0:              Successfully
1978  *      -EINVAL:        Failed
1979  */
1980 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
1981 {
1982         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1983         int max_frame;
1984
1985         max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1986         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
1987                 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
1988                 pr_err("Invalid MTU setting\n");
1989                 return -EINVAL;
1990         }
1991         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
1992                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1993         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
1994                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
1995         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
1996                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
1997         else
1998                 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
1999         netdev->mtu = new_mtu;
2000         adapter->hw.mac.max_frame_size = max_frame;
2001
2002         if (netif_running(netdev))
2003                 pch_gbe_reinit_locked(adapter);
2004         else
2005                 pch_gbe_reset(adapter);
2006
2007         pr_debug("max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2008                  max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2009                  adapter->hw.mac.max_frame_size);
2010         return 0;
2011 }
2012
2013 /**
2014  * pch_gbe_ioctl - Controls register through a MII interface
2015  * @netdev:   Network interface device structure
2016  * @ifr:      Pointer to ifr structure
2017  * @cmd:      Control command
2018  * Returns
2019  *      0:      Successfully
2020  *      Negative value: Failed
2021  */
2022 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2023 {
2024         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2025
2026         pr_debug("cmd : 0x%04x\n", cmd);
2027
2028         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2029 }
2030
2031 /**
2032  * pch_gbe_tx_timeout - Respond to a Tx Hang
2033  * @netdev:   Network interface device structure
2034  */
2035 static void pch_gbe_tx_timeout(struct net_device *netdev)
2036 {
2037         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2038
2039         /* Do the reset outside of interrupt context */
2040         adapter->stats.tx_timeout_count++;
2041         schedule_work(&adapter->reset_task);
2042 }
2043
2044 /**
2045  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2046  * @napi:    Pointer of polling device struct
2047  * @budget:  The maximum number of a packet
2048  * Returns
2049  *      false:  Exit the polling mode
2050  *      true:   Continue the polling mode
2051  */
2052 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2053 {
2054         struct pch_gbe_adapter *adapter =
2055             container_of(napi, struct pch_gbe_adapter, napi);
2056         struct net_device *netdev = adapter->netdev;
2057         int work_done = 0;
2058         bool poll_end_flag = false;
2059         bool cleaned = false;
2060
2061         pr_debug("budget : %d\n", budget);
2062
2063         /* Keep link state information with original netdev */
2064         if (!netif_carrier_ok(netdev)) {
2065                 poll_end_flag = true;
2066         } else {
2067                 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2068                 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2069
2070                 if (cleaned)
2071                         work_done = budget;
2072                 /* If no Tx and not enough Rx work done,
2073                  * exit the polling mode
2074                  */
2075                 if ((work_done < budget) || !netif_running(netdev))
2076                         poll_end_flag = true;
2077         }
2078
2079         if (poll_end_flag) {
2080                 napi_complete(napi);
2081                 pch_gbe_irq_enable(adapter);
2082         }
2083
2084         pr_debug("poll_end_flag : %d  work_done : %d  budget : %d\n",
2085                  poll_end_flag, work_done, budget);
2086
2087         return work_done;
2088 }
2089
2090 #ifdef CONFIG_NET_POLL_CONTROLLER
2091 /**
2092  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2093  * @netdev:  Network interface device structure
2094  */
2095 static void pch_gbe_netpoll(struct net_device *netdev)
2096 {
2097         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2098
2099         disable_irq(adapter->pdev->irq);
2100         pch_gbe_intr(adapter->pdev->irq, netdev);
2101         enable_irq(adapter->pdev->irq);
2102 }
2103 #endif
2104
2105 static const struct net_device_ops pch_gbe_netdev_ops = {
2106         .ndo_open = pch_gbe_open,
2107         .ndo_stop = pch_gbe_stop,
2108         .ndo_start_xmit = pch_gbe_xmit_frame,
2109         .ndo_get_stats = pch_gbe_get_stats,
2110         .ndo_set_mac_address = pch_gbe_set_mac,
2111         .ndo_tx_timeout = pch_gbe_tx_timeout,
2112         .ndo_change_mtu = pch_gbe_change_mtu,
2113         .ndo_do_ioctl = pch_gbe_ioctl,
2114         .ndo_set_multicast_list = &pch_gbe_set_multi,
2115 #ifdef CONFIG_NET_POLL_CONTROLLER
2116         .ndo_poll_controller = pch_gbe_netpoll,
2117 #endif
2118 };
2119
2120 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2121                                                 pci_channel_state_t state)
2122 {
2123         struct net_device *netdev = pci_get_drvdata(pdev);
2124         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2125
2126         netif_device_detach(netdev);
2127         if (netif_running(netdev))
2128                 pch_gbe_down(adapter);
2129         pci_disable_device(pdev);
2130         /* Request a slot slot reset. */
2131         return PCI_ERS_RESULT_NEED_RESET;
2132 }
2133
2134 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2135 {
2136         struct net_device *netdev = pci_get_drvdata(pdev);
2137         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2138         struct pch_gbe_hw *hw = &adapter->hw;
2139
2140         if (pci_enable_device(pdev)) {
2141                 pr_err("Cannot re-enable PCI device after reset\n");
2142                 return PCI_ERS_RESULT_DISCONNECT;
2143         }
2144         pci_set_master(pdev);
2145         pci_enable_wake(pdev, PCI_D0, 0);
2146         pch_gbe_hal_power_up_phy(hw);
2147         pch_gbe_reset(adapter);
2148         /* Clear wake up status */
2149         pch_gbe_mac_set_wol_event(hw, 0);
2150
2151         return PCI_ERS_RESULT_RECOVERED;
2152 }
2153
2154 static void pch_gbe_io_resume(struct pci_dev *pdev)
2155 {
2156         struct net_device *netdev = pci_get_drvdata(pdev);
2157         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2158
2159         if (netif_running(netdev)) {
2160                 if (pch_gbe_up(adapter)) {
2161                         pr_debug("can't bring device back up after reset\n");
2162                         return;
2163                 }
2164         }
2165         netif_device_attach(netdev);
2166 }
2167
2168 static int __pch_gbe_suspend(struct pci_dev *pdev)
2169 {
2170         struct net_device *netdev = pci_get_drvdata(pdev);
2171         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2172         struct pch_gbe_hw *hw = &adapter->hw;
2173         u32 wufc = adapter->wake_up_evt;
2174         int retval = 0;
2175
2176         netif_device_detach(netdev);
2177         if (netif_running(netdev))
2178                 pch_gbe_down(adapter);
2179         if (wufc) {
2180                 pch_gbe_set_multi(netdev);
2181                 pch_gbe_setup_rctl(adapter);
2182                 pch_gbe_configure_rx(adapter);
2183                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2184                                         hw->mac.link_duplex);
2185                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2186                                         hw->mac.link_duplex);
2187                 pch_gbe_mac_set_wol_event(hw, wufc);
2188                 pci_disable_device(pdev);
2189         } else {
2190                 pch_gbe_hal_power_down_phy(hw);
2191                 pch_gbe_mac_set_wol_event(hw, wufc);
2192                 pci_disable_device(pdev);
2193         }
2194         return retval;
2195 }
2196
2197 #ifdef CONFIG_PM
2198 static int pch_gbe_suspend(struct device *device)
2199 {
2200         struct pci_dev *pdev = to_pci_dev(device);
2201
2202         return __pch_gbe_suspend(pdev);
2203 }
2204
2205 static int pch_gbe_resume(struct device *device)
2206 {
2207         struct pci_dev *pdev = to_pci_dev(device);
2208         struct net_device *netdev = pci_get_drvdata(pdev);
2209         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2210         struct pch_gbe_hw *hw = &adapter->hw;
2211         u32 err;
2212
2213         err = pci_enable_device(pdev);
2214         if (err) {
2215                 pr_err("Cannot enable PCI device from suspend\n");
2216                 return err;
2217         }
2218         pci_set_master(pdev);
2219         pch_gbe_hal_power_up_phy(hw);
2220         pch_gbe_reset(adapter);
2221         /* Clear wake on lan control and status */
2222         pch_gbe_mac_set_wol_event(hw, 0);
2223
2224         if (netif_running(netdev))
2225                 pch_gbe_up(adapter);
2226         netif_device_attach(netdev);
2227
2228         return 0;
2229 }
2230 #endif /* CONFIG_PM */
2231
2232 static void pch_gbe_shutdown(struct pci_dev *pdev)
2233 {
2234         __pch_gbe_suspend(pdev);
2235         if (system_state == SYSTEM_POWER_OFF) {
2236                 pci_wake_from_d3(pdev, true);
2237                 pci_set_power_state(pdev, PCI_D3hot);
2238         }
2239 }
2240
2241 static void pch_gbe_remove(struct pci_dev *pdev)
2242 {
2243         struct net_device *netdev = pci_get_drvdata(pdev);
2244         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2245
2246         cancel_work_sync(&adapter->reset_task);
2247         unregister_netdev(netdev);
2248
2249         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2250
2251         kfree(adapter->tx_ring);
2252         kfree(adapter->rx_ring);
2253
2254         iounmap(adapter->hw.reg);
2255         pci_release_regions(pdev);
2256         free_netdev(netdev);
2257         pci_disable_device(pdev);
2258 }
2259
2260 static int pch_gbe_probe(struct pci_dev *pdev,
2261                           const struct pci_device_id *pci_id)
2262 {
2263         struct net_device *netdev;
2264         struct pch_gbe_adapter *adapter;
2265         int ret;
2266
2267         ret = pci_enable_device(pdev);
2268         if (ret)
2269                 return ret;
2270
2271         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2272                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2273                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2274                 if (ret) {
2275                         ret = pci_set_consistent_dma_mask(pdev,
2276                                                           DMA_BIT_MASK(32));
2277                         if (ret) {
2278                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2279                                         "configuration, aborting\n");
2280                                 goto err_disable_device;
2281                         }
2282                 }
2283         }
2284
2285         ret = pci_request_regions(pdev, KBUILD_MODNAME);
2286         if (ret) {
2287                 dev_err(&pdev->dev,
2288                         "ERR: Can't reserve PCI I/O and memory resources\n");
2289                 goto err_disable_device;
2290         }
2291         pci_set_master(pdev);
2292
2293         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2294         if (!netdev) {
2295                 ret = -ENOMEM;
2296                 dev_err(&pdev->dev,
2297                         "ERR: Can't allocate and set up an Ethernet device\n");
2298                 goto err_release_pci;
2299         }
2300         SET_NETDEV_DEV(netdev, &pdev->dev);
2301
2302         pci_set_drvdata(pdev, netdev);
2303         adapter = netdev_priv(netdev);
2304         adapter->netdev = netdev;
2305         adapter->pdev = pdev;
2306         adapter->hw.back = adapter;
2307         adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2308         if (!adapter->hw.reg) {
2309                 ret = -EIO;
2310                 dev_err(&pdev->dev, "Can't ioremap\n");
2311                 goto err_free_netdev;
2312         }
2313
2314         netdev->netdev_ops = &pch_gbe_netdev_ops;
2315         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2316         netif_napi_add(netdev, &adapter->napi,
2317                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2318         netdev->features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_GRO;
2319         pch_gbe_set_ethtool_ops(netdev);
2320
2321         pch_gbe_mac_reset_hw(&adapter->hw);
2322
2323         /* setup the private structure */
2324         ret = pch_gbe_sw_init(adapter);
2325         if (ret)
2326                 goto err_iounmap;
2327
2328         /* Initialize PHY */
2329         ret = pch_gbe_init_phy(adapter);
2330         if (ret) {
2331                 dev_err(&pdev->dev, "PHY initialize error\n");
2332                 goto err_free_adapter;
2333         }
2334         pch_gbe_hal_get_bus_info(&adapter->hw);
2335
2336         /* Read the MAC address. and store to the private data */
2337         ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2338         if (ret) {
2339                 dev_err(&pdev->dev, "MAC address Read Error\n");
2340                 goto err_free_adapter;
2341         }
2342
2343         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2344         if (!is_valid_ether_addr(netdev->dev_addr)) {
2345                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2346                 ret = -EIO;
2347                 goto err_free_adapter;
2348         }
2349         setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2350                     (unsigned long)adapter);
2351
2352         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2353
2354         pch_gbe_check_options(adapter);
2355
2356         if (adapter->tx_csum)
2357                 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2358         else
2359                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2360
2361         /* initialize the wol settings based on the eeprom settings */
2362         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2363         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2364
2365         /* reset the hardware with the new settings */
2366         pch_gbe_reset(adapter);
2367
2368         ret = register_netdev(netdev);
2369         if (ret)
2370                 goto err_free_adapter;
2371         /* tell the stack to leave us alone until pch_gbe_open() is called */
2372         netif_carrier_off(netdev);
2373         netif_stop_queue(netdev);
2374
2375         dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2376
2377         device_set_wakeup_enable(&pdev->dev, 1);
2378         return 0;
2379
2380 err_free_adapter:
2381         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2382         kfree(adapter->tx_ring);
2383         kfree(adapter->rx_ring);
2384 err_iounmap:
2385         iounmap(adapter->hw.reg);
2386 err_free_netdev:
2387         free_netdev(netdev);
2388 err_release_pci:
2389         pci_release_regions(pdev);
2390 err_disable_device:
2391         pci_disable_device(pdev);
2392         return ret;
2393 }
2394
2395 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2396         {.vendor = PCI_VENDOR_ID_INTEL,
2397          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2398          .subvendor = PCI_ANY_ID,
2399          .subdevice = PCI_ANY_ID,
2400          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2401          .class_mask = (0xFFFF00)
2402          },
2403         /* required last entry */
2404         {0}
2405 };
2406
2407 #ifdef CONFIG_PM
2408 static const struct dev_pm_ops pch_gbe_pm_ops = {
2409         .suspend = pch_gbe_suspend,
2410         .resume = pch_gbe_resume,
2411         .freeze = pch_gbe_suspend,
2412         .thaw = pch_gbe_resume,
2413         .poweroff = pch_gbe_suspend,
2414         .restore = pch_gbe_resume,
2415 };
2416 #endif
2417
2418 static struct pci_error_handlers pch_gbe_err_handler = {
2419         .error_detected = pch_gbe_io_error_detected,
2420         .slot_reset = pch_gbe_io_slot_reset,
2421         .resume = pch_gbe_io_resume
2422 };
2423
2424 static struct pci_driver pch_gbe_pcidev = {
2425         .name = KBUILD_MODNAME,
2426         .id_table = pch_gbe_pcidev_id,
2427         .probe = pch_gbe_probe,
2428         .remove = pch_gbe_remove,
2429 #ifdef CONFIG_PM_OPS
2430         .driver.pm = &pch_gbe_pm_ops,
2431 #endif
2432         .shutdown = pch_gbe_shutdown,
2433         .err_handler = &pch_gbe_err_handler
2434 };
2435
2436
2437 static int __init pch_gbe_init_module(void)
2438 {
2439         int ret;
2440
2441         ret = pci_register_driver(&pch_gbe_pcidev);
2442         if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2443                 if (copybreak == 0) {
2444                         pr_info("copybreak disabled\n");
2445                 } else {
2446                         pr_info("copybreak enabled for packets <= %u bytes\n",
2447                                 copybreak);
2448                 }
2449         }
2450         return ret;
2451 }
2452
2453 static void __exit pch_gbe_exit_module(void)
2454 {
2455         pci_unregister_driver(&pch_gbe_pcidev);
2456 }
2457
2458 module_init(pch_gbe_init_module);
2459 module_exit(pch_gbe_exit_module);
2460
2461 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2462 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2463 MODULE_LICENSE("GPL");
2464 MODULE_VERSION(DRV_VERSION);
2465 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2466
2467 module_param(copybreak, uint, 0644);
2468 MODULE_PARM_DESC(copybreak,
2469         "Maximum size of packet that is copied to a new buffer on receive");
2470
2471 /* pch_gbe_main.c */