Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[~shefty/rdma-dev.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
1 /*
2  * Copyright (c) 2010-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20
21 static const int firstep_table[] =
22 /* level:  0   1   2   3   4   5   6   7   8  */
23         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
24
25 static const int cycpwrThr1_table[] =
26 /* level:  0   1   2   3   4   5   6   7   8  */
27         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
28
29 /*
30  * register values to turn OFDM weak signal detection OFF
31  */
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off =  31;
37 static const int m2CountThrLow_off =  63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
42
43 /**
44  * ar9003_hw_set_channel - set channel on single-chip device
45  * @ah: atheros hardware structure
46  * @chan:
47  *
48  * This is the function to change channel on single-chip devices, that is
49  * for AR9300 family of chipsets.
50  *
51  * This function takes the channel value in MHz and sets
52  * hardware channel value. Assumes writes have been enabled to analog bus.
53  *
54  * Actual Expression,
55  *
56  * For 2GHz channel,
57  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58  * (freq_ref = 40MHz)
59  *
60  * For 5GHz channel,
61  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62  * (freq_ref = 40MHz/(24>>amodeRefSel))
63  *
64  * For 5GHz channels which are 5MHz spaced,
65  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66  * (freq_ref = 40MHz)
67  */
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69 {
70         u16 bMode, fracMode = 0, aModeRefSel = 0;
71         u32 freq, channelSel = 0, reg32 = 0;
72         struct chan_centers centers;
73         int loadSynthChannel;
74
75         ath9k_hw_get_channel_centers(ah, chan, &centers);
76         freq = centers.synth_center;
77
78         if (freq < 4800) {     /* 2 GHz, fractional mode */
79                 if (AR_SREV_9330(ah)) {
80                         u32 chan_frac;
81                         u32 div;
82
83                         if (ah->is_clk_25mhz)
84                                 div = 75;
85                         else
86                                 div = 120;
87
88                         channelSel = (freq * 4) / div;
89                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
90                         channelSel = (channelSel << 17) | chan_frac;
91                 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
92                         u32 chan_frac;
93
94                         /*
95                          * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
96                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
97                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
98                          */
99                         channelSel = (freq * 4) / 120;
100                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
101                         channelSel = (channelSel << 17) | chan_frac;
102                 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
103                         if (ah->is_clk_25mhz) {
104                                 u32 chan_frac;
105
106                                 channelSel = (freq * 2) / 75;
107                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
108                                 channelSel = (channelSel << 17) | chan_frac;
109                         } else
110                                 channelSel = CHANSEL_2G(freq) >> 1;
111                 } else
112                         channelSel = CHANSEL_2G(freq);
113                 /* Set to 2G mode */
114                 bMode = 1;
115         } else {
116                 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
117                     ah->is_clk_25mhz) {
118                         u32 chan_frac;
119
120                         channelSel = freq / 75;
121                         chan_frac = ((freq % 75) * 0x20000) / 75;
122                         channelSel = (channelSel << 17) | chan_frac;
123                 } else {
124                         channelSel = CHANSEL_5G(freq);
125                         /* Doubler is ON, so, divide channelSel by 2. */
126                         channelSel >>= 1;
127                 }
128                 /* Set to 5G mode */
129                 bMode = 0;
130         }
131
132         /* Enable fractional mode for all channels */
133         fracMode = 1;
134         aModeRefSel = 0;
135         loadSynthChannel = 0;
136
137         reg32 = (bMode << 29);
138         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
139
140         /* Enable Long shift Select for Synthesizer */
141         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
142                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
143
144         /* Program Synth. setting */
145         reg32 = (channelSel << 2) | (fracMode << 30) |
146                 (aModeRefSel << 28) | (loadSynthChannel << 31);
147         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
148
149         /* Toggle Load Synth channel bit */
150         loadSynthChannel = 1;
151         reg32 = (channelSel << 2) | (fracMode << 30) |
152                 (aModeRefSel << 28) | (loadSynthChannel << 31);
153         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
154
155         ah->curchan = chan;
156
157         return 0;
158 }
159
160 /**
161  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
162  * @ah: atheros hardware structure
163  * @chan:
164  *
165  * For single-chip solutions. Converts to baseband spur frequency given the
166  * input channel frequency and compute register settings below.
167  *
168  * Spur mitigation for MRC CCK
169  */
170 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
171                                             struct ath9k_channel *chan)
172 {
173         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
174         int cur_bb_spur, negative = 0, cck_spur_freq;
175         int i;
176         int range, max_spur_cnts, synth_freq;
177         u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
178
179         /*
180          * Need to verify range +/- 10 MHz in control channel, otherwise spur
181          * is out-of-band and can be ignored.
182          */
183
184         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
185             AR_SREV_9550(ah)) {
186                 if (spur_fbin_ptr[0] == 0) /* No spur */
187                         return;
188                 max_spur_cnts = 5;
189                 if (IS_CHAN_HT40(chan)) {
190                         range = 19;
191                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
192                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
193                                 synth_freq = chan->channel + 10;
194                         else
195                                 synth_freq = chan->channel - 10;
196                 } else {
197                         range = 10;
198                         synth_freq = chan->channel;
199                 }
200         } else {
201                 range = AR_SREV_9462(ah) ? 5 : 10;
202                 max_spur_cnts = 4;
203                 synth_freq = chan->channel;
204         }
205
206         for (i = 0; i < max_spur_cnts; i++) {
207                 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
208                         continue;
209
210                 negative = 0;
211                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
212                     AR_SREV_9550(ah))
213                         cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
214                                                          IS_CHAN_2GHZ(chan));
215                 else
216                         cur_bb_spur = spur_freq[i];
217
218                 cur_bb_spur -= synth_freq;
219                 if (cur_bb_spur < 0) {
220                         negative = 1;
221                         cur_bb_spur = -cur_bb_spur;
222                 }
223                 if (cur_bb_spur < range) {
224                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
225
226                         if (negative == 1)
227                                 cck_spur_freq = -cck_spur_freq;
228
229                         cck_spur_freq = cck_spur_freq & 0xfffff;
230
231                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
232                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
233                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
234                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
235                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
236                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
237                                       0x2);
238                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
240                                       0x1);
241                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
243                                       cck_spur_freq);
244
245                         return;
246                 }
247         }
248
249         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
250                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
251         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
252                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
253         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
254                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
255 }
256
257 /* Clean all spur register fields */
258 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
259 {
260         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
261                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
262         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
263                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
264         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
265                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
266         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
267                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
268         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
269                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
270         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
271                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
272         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
273                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
274         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
275                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
276         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
277                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
278
279         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
281         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
282                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
283         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
284                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
285         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
286                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
287         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
288                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
289         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
290                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
291         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
292                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
293         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
294                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
295         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
296                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
297         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
298                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
299 }
300
301 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
302                                 int freq_offset,
303                                 int spur_freq_sd,
304                                 int spur_delta_phase,
305                                 int spur_subchannel_sd,
306                                 int range,
307                                 int synth_freq)
308 {
309         int mask_index = 0;
310
311         /* OFDM Spur mitigation */
312         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
313                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
314         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
315                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
316         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
317                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
318         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
319                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
320         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
321                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
322
323         if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
324                 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
325                               AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
326
327         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
328                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
329         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
330                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
331         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
332                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
333
334         if (REG_READ_FIELD(ah, AR_PHY_MODE,
335                            AR_PHY_MODE_DYNAMIC) == 0x1)
336                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
337                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
338
339         mask_index = (freq_offset << 4) / 5;
340         if (mask_index < 0)
341                 mask_index = mask_index - 1;
342
343         mask_index = mask_index & 0x7f;
344
345         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
346                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
347         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
348                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
349         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
350                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
351         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
352                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
353         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
354                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
355         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
356                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
357         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
358                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
359         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
361         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
362                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
363         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
364                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
365 }
366
367 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
368                                      int freq_offset)
369 {
370         int mask_index = 0;
371
372         mask_index = (freq_offset << 4) / 5;
373         if (mask_index < 0)
374                 mask_index = mask_index - 1;
375
376         mask_index = mask_index & 0x7f;
377
378         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
379                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
380                       mask_index);
381
382         /* A == B */
383         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
384                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
385                       mask_index);
386
387         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
388                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
389                       mask_index);
390         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
391                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
392         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
393                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
394
395         /* A == B */
396         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
397                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
398 }
399
400 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
401                                      struct ath9k_channel *chan,
402                                      int freq_offset,
403                                      int range,
404                                      int synth_freq)
405 {
406         int spur_freq_sd = 0;
407         int spur_subchannel_sd = 0;
408         int spur_delta_phase = 0;
409
410         if (IS_CHAN_HT40(chan)) {
411                 if (freq_offset < 0) {
412                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
413                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
414                                 spur_subchannel_sd = 1;
415                         else
416                                 spur_subchannel_sd = 0;
417
418                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
419
420                 } else {
421                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
422                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
423                                 spur_subchannel_sd = 0;
424                         else
425                                 spur_subchannel_sd = 1;
426
427                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
428
429                 }
430
431                 spur_delta_phase = (freq_offset << 17) / 5;
432
433         } else {
434                 spur_subchannel_sd = 0;
435                 spur_freq_sd = (freq_offset << 9) /11;
436                 spur_delta_phase = (freq_offset << 18) / 5;
437         }
438
439         spur_freq_sd = spur_freq_sd & 0x3ff;
440         spur_delta_phase = spur_delta_phase & 0xfffff;
441
442         ar9003_hw_spur_ofdm(ah,
443                             freq_offset,
444                             spur_freq_sd,
445                             spur_delta_phase,
446                             spur_subchannel_sd,
447                             range, synth_freq);
448 }
449
450 /* Spur mitigation for OFDM */
451 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
452                                          struct ath9k_channel *chan)
453 {
454         int synth_freq;
455         int range = 10;
456         int freq_offset = 0;
457         int mode;
458         u8* spurChansPtr;
459         unsigned int i;
460         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
461
462         if (IS_CHAN_5GHZ(chan)) {
463                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
464                 mode = 0;
465         }
466         else {
467                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
468                 mode = 1;
469         }
470
471         if (spurChansPtr[0] == 0)
472                 return; /* No spur in the mode */
473
474         if (IS_CHAN_HT40(chan)) {
475                 range = 19;
476                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
477                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
478                         synth_freq = chan->channel - 10;
479                 else
480                         synth_freq = chan->channel + 10;
481         } else {
482                 range = 10;
483                 synth_freq = chan->channel;
484         }
485
486         ar9003_hw_spur_ofdm_clear(ah);
487
488         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
489                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
490                 freq_offset -= synth_freq;
491                 if (abs(freq_offset) < range) {
492                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
493                                                  range, synth_freq);
494
495                         if (AR_SREV_9565(ah) && (i < 4)) {
496                                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
497                                                                  mode);
498                                 freq_offset -= synth_freq;
499                                 if (abs(freq_offset) < range)
500                                         ar9003_hw_spur_ofdm_9565(ah, freq_offset);
501                         }
502
503                         break;
504                 }
505         }
506 }
507
508 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
509                                     struct ath9k_channel *chan)
510 {
511         if (!AR_SREV_9565(ah))
512                 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
513         ar9003_hw_spur_mitigate_ofdm(ah, chan);
514 }
515
516 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
517                                          struct ath9k_channel *chan)
518 {
519         u32 pll;
520
521         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
522
523         if (chan && IS_CHAN_HALF_RATE(chan))
524                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
525         else if (chan && IS_CHAN_QUARTER_RATE(chan))
526                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
527
528         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
529
530         return pll;
531 }
532
533 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
534                                        struct ath9k_channel *chan)
535 {
536         u32 phymode;
537         u32 enableDacFifo = 0;
538
539         enableDacFifo =
540                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
541
542         /* Enable 11n HT, 20 MHz */
543         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
544                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
545
546         /* Configure baseband for dynamic 20/40 operation */
547         if (IS_CHAN_HT40(chan)) {
548                 phymode |= AR_PHY_GC_DYN2040_EN;
549                 /* Configure control (primary) channel at +-10MHz */
550                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
551                     (chan->chanmode == CHANNEL_G_HT40PLUS))
552                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
553
554         }
555
556         /* make sure we preserve INI settings */
557         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
558         /* turn off Green Field detection for STA for now */
559         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
560
561         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
562
563         /* Configure MAC for 20/40 operation */
564         ath9k_hw_set11nmac2040(ah);
565
566         /* global transmit timeout (25 TUs default)*/
567         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
568         /* carrier sense timeout */
569         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
570 }
571
572 static void ar9003_hw_init_bb(struct ath_hw *ah,
573                               struct ath9k_channel *chan)
574 {
575         u32 synthDelay;
576
577         /*
578          * Wait for the frequency synth to settle (synth goes on
579          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
580          * Value is in 100ns increments.
581          */
582         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
583
584         /* Activate the PHY (includes baseband activate + synthesizer on) */
585         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
586         ath9k_hw_synth_delay(ah, chan, synthDelay);
587 }
588
589 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
590 {
591         if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
592                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
593                             AR_PHY_SWAP_ALT_CHAIN);
594
595         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
596         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
597
598         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
599                 tx = 3;
600
601         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
602 }
603
604 /*
605  * Override INI values with chip specific configuration.
606  */
607 static void ar9003_hw_override_ini(struct ath_hw *ah)
608 {
609         u32 val;
610
611         /*
612          * Set the RX_ABORT and RX_DIS and clear it only after
613          * RXE is set for MAC. This prevents frames with
614          * corrupted descriptor status.
615          */
616         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
617
618         /*
619          * For AR9280 and above, there is a new feature that allows
620          * Multicast search based on both MAC Address and Key ID. By default,
621          * this feature is enabled. But since the driver is not using this
622          * feature, we switch it off; otherwise multicast search based on
623          * MAC addr only will fail.
624          */
625         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
626         REG_WRITE(ah, AR_PCU_MISC_MODE2,
627                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
628
629         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
630                     AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
631 }
632
633 static void ar9003_hw_prog_ini(struct ath_hw *ah,
634                                struct ar5416IniArray *iniArr,
635                                int column)
636 {
637         unsigned int i, regWrites = 0;
638
639         /* New INI format: Array may be undefined (pre, core, post arrays) */
640         if (!iniArr->ia_array)
641                 return;
642
643         /*
644          * New INI format: Pre, core, and post arrays for a given subsystem
645          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
646          * the array is non-modal and force the column to 1.
647          */
648         if (column >= iniArr->ia_columns)
649                 column = 1;
650
651         for (i = 0; i < iniArr->ia_rows; i++) {
652                 u32 reg = INI_RA(iniArr, i, 0);
653                 u32 val = INI_RA(iniArr, i, column);
654
655                 REG_WRITE(ah, reg, val);
656
657                 DO_DELAY(regWrites);
658         }
659 }
660
661 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
662                                             struct ath9k_channel *chan)
663 {
664         int ret;
665
666         switch (chan->chanmode) {
667         case CHANNEL_A:
668         case CHANNEL_A_HT20:
669                 if (chan->channel <= 5350)
670                         ret = 1;
671                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
672                         ret = 3;
673                 else
674                         ret = 5;
675                 break;
676
677         case CHANNEL_A_HT40PLUS:
678         case CHANNEL_A_HT40MINUS:
679                 if (chan->channel <= 5350)
680                         ret = 2;
681                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
682                         ret = 4;
683                 else
684                         ret = 6;
685                 break;
686
687         case CHANNEL_G:
688         case CHANNEL_G_HT20:
689         case CHANNEL_B:
690                 ret = 8;
691                 break;
692
693         case CHANNEL_G_HT40PLUS:
694         case CHANNEL_G_HT40MINUS:
695                 ret = 7;
696                 break;
697
698         default:
699                 ret = -EINVAL;
700         }
701
702         return ret;
703 }
704
705 static int ar9003_hw_process_ini(struct ath_hw *ah,
706                                  struct ath9k_channel *chan)
707 {
708         unsigned int regWrites = 0, i;
709         u32 modesIndex;
710
711         switch (chan->chanmode) {
712         case CHANNEL_A:
713         case CHANNEL_A_HT20:
714                 modesIndex = 1;
715                 break;
716         case CHANNEL_A_HT40PLUS:
717         case CHANNEL_A_HT40MINUS:
718                 modesIndex = 2;
719                 break;
720         case CHANNEL_G:
721         case CHANNEL_G_HT20:
722         case CHANNEL_B:
723                 modesIndex = 4;
724                 break;
725         case CHANNEL_G_HT40PLUS:
726         case CHANNEL_G_HT40MINUS:
727                 modesIndex = 3;
728                 break;
729
730         default:
731                 return -EINVAL;
732         }
733
734         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
735                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
736                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
737                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
738                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
739                 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
740                         ar9003_hw_prog_ini(ah,
741                                            &ah->ini_radio_post_sys2ant,
742                                            modesIndex);
743         }
744
745         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
746         if (AR_SREV_9550(ah))
747                 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
748                                 regWrites);
749
750         if (AR_SREV_9550(ah)) {
751                 int modes_txgain_index;
752
753                 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
754                 if (modes_txgain_index < 0)
755                         return -EINVAL;
756
757                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
758                                 regWrites);
759         } else {
760                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
761         }
762
763         /*
764          * For 5GHz channels requiring Fast Clock, apply
765          * different modal values.
766          */
767         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
768                 REG_WRITE_ARRAY(&ah->iniModesFastClock,
769                                 modesIndex, regWrites);
770
771         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
772
773         if (chan->channel == 2484)
774                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
775
776         if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
777                 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
778                           AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
779
780         ah->modes_index = modesIndex;
781         ar9003_hw_override_ini(ah);
782         ar9003_hw_set_channel_regs(ah, chan);
783         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
784         ath9k_hw_apply_txpower(ah, chan, false);
785
786         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
787                 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
788                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
789                         ah->enabled_cals |= TX_IQ_CAL;
790                 else
791                         ah->enabled_cals &= ~TX_IQ_CAL;
792
793                 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
794                         ah->enabled_cals |= TX_CL_CAL;
795                 else
796                         ah->enabled_cals &= ~TX_CL_CAL;
797         }
798
799         return 0;
800 }
801
802 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
803                                  struct ath9k_channel *chan)
804 {
805         u32 rfMode = 0;
806
807         if (chan == NULL)
808                 return;
809
810         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
811                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
812
813         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
814                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
815         if (IS_CHAN_QUARTER_RATE(chan))
816                 rfMode |= AR_PHY_MODE_QUARTER;
817         if (IS_CHAN_HALF_RATE(chan))
818                 rfMode |= AR_PHY_MODE_HALF;
819
820         if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
821                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
822                               AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
823
824         REG_WRITE(ah, AR_PHY_MODE, rfMode);
825 }
826
827 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
828 {
829         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
830 }
831
832 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
833                                       struct ath9k_channel *chan)
834 {
835         u32 coef_scaled, ds_coef_exp, ds_coef_man;
836         u32 clockMhzScaled = 0x64000000;
837         struct chan_centers centers;
838
839         /*
840          * half and quarter rate can divide the scaled clock by 2 or 4
841          * scale for selected channel bandwidth
842          */
843         if (IS_CHAN_HALF_RATE(chan))
844                 clockMhzScaled = clockMhzScaled >> 1;
845         else if (IS_CHAN_QUARTER_RATE(chan))
846                 clockMhzScaled = clockMhzScaled >> 2;
847
848         /*
849          * ALGO -> coef = 1e8/fcarrier*fclock/40;
850          * scaled coef to provide precision for this floating calculation
851          */
852         ath9k_hw_get_channel_centers(ah, chan, &centers);
853         coef_scaled = clockMhzScaled / centers.synth_center;
854
855         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
856                                       &ds_coef_exp);
857
858         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
859                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
860         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
861                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
862
863         /*
864          * For Short GI,
865          * scaled coeff is 9/10 that of normal coeff
866          */
867         coef_scaled = (9 * coef_scaled) / 10;
868
869         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
870                                       &ds_coef_exp);
871
872         /* for short gi */
873         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
874                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
875         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
876                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
877 }
878
879 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
880 {
881         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
882         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
883                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
884 }
885
886 /*
887  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
888  * Read the phy active delay register. Value is in 100ns increments.
889  */
890 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
891 {
892         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
893
894         ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
895
896         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
897 }
898
899 static bool ar9003_hw_ani_control(struct ath_hw *ah,
900                                   enum ath9k_ani_cmd cmd, int param)
901 {
902         struct ath_common *common = ath9k_hw_common(ah);
903         struct ath9k_channel *chan = ah->curchan;
904         struct ar5416AniState *aniState = &chan->ani;
905         s32 value, value2;
906
907         switch (cmd & ah->ani_function) {
908         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
909                 /*
910                  * on == 1 means ofdm weak signal detection is ON
911                  * on == 1 is the default, for less noise immunity
912                  *
913                  * on == 0 means ofdm weak signal detection is OFF
914                  * on == 0 means more noise imm
915                  */
916                 u32 on = param ? 1 : 0;
917
918                 if (on)
919                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
920                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
921                 else
922                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
923                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
924
925                 if (on != aniState->ofdmWeakSigDetect) {
926                         ath_dbg(common, ANI,
927                                 "** ch %d: ofdm weak signal: %s=>%s\n",
928                                 chan->channel,
929                                 aniState->ofdmWeakSigDetect ?
930                                 "on" : "off",
931                                 on ? "on" : "off");
932                         if (on)
933                                 ah->stats.ast_ani_ofdmon++;
934                         else
935                                 ah->stats.ast_ani_ofdmoff++;
936                         aniState->ofdmWeakSigDetect = on;
937                 }
938                 break;
939         }
940         case ATH9K_ANI_FIRSTEP_LEVEL:{
941                 u32 level = param;
942
943                 if (level >= ARRAY_SIZE(firstep_table)) {
944                         ath_dbg(common, ANI,
945                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
946                                 level, ARRAY_SIZE(firstep_table));
947                         return false;
948                 }
949
950                 /*
951                  * make register setting relative to default
952                  * from INI file & cap value
953                  */
954                 value = firstep_table[level] -
955                         firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
956                         aniState->iniDef.firstep;
957                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
958                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
959                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
960                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
961                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
962                               AR_PHY_FIND_SIG_FIRSTEP,
963                               value);
964                 /*
965                  * we need to set first step low register too
966                  * make register setting relative to default
967                  * from INI file & cap value
968                  */
969                 value2 = firstep_table[level] -
970                          firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
971                          aniState->iniDef.firstepLow;
972                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
973                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
974                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
975                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
976
977                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
978                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
979
980                 if (level != aniState->firstepLevel) {
981                         ath_dbg(common, ANI,
982                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
983                                 chan->channel,
984                                 aniState->firstepLevel,
985                                 level,
986                                 ATH9K_ANI_FIRSTEP_LVL,
987                                 value,
988                                 aniState->iniDef.firstep);
989                         ath_dbg(common, ANI,
990                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
991                                 chan->channel,
992                                 aniState->firstepLevel,
993                                 level,
994                                 ATH9K_ANI_FIRSTEP_LVL,
995                                 value2,
996                                 aniState->iniDef.firstepLow);
997                         if (level > aniState->firstepLevel)
998                                 ah->stats.ast_ani_stepup++;
999                         else if (level < aniState->firstepLevel)
1000                                 ah->stats.ast_ani_stepdown++;
1001                         aniState->firstepLevel = level;
1002                 }
1003                 break;
1004         }
1005         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1006                 u32 level = param;
1007
1008                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1009                         ath_dbg(common, ANI,
1010                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1011                                 level, ARRAY_SIZE(cycpwrThr1_table));
1012                         return false;
1013                 }
1014                 /*
1015                  * make register setting relative to default
1016                  * from INI file & cap value
1017                  */
1018                 value = cycpwrThr1_table[level] -
1019                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1020                         aniState->iniDef.cycpwrThr1;
1021                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1022                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1023                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1024                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1025                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1026                               AR_PHY_TIMING5_CYCPWR_THR1,
1027                               value);
1028
1029                 /*
1030                  * set AR_PHY_EXT_CCA for extension channel
1031                  * make register setting relative to default
1032                  * from INI file & cap value
1033                  */
1034                 value2 = cycpwrThr1_table[level] -
1035                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1036                          aniState->iniDef.cycpwrThr1Ext;
1037                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1038                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1039                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1040                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1041                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1042                               AR_PHY_EXT_CYCPWR_THR1, value2);
1043
1044                 if (level != aniState->spurImmunityLevel) {
1045                         ath_dbg(common, ANI,
1046                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1047                                 chan->channel,
1048                                 aniState->spurImmunityLevel,
1049                                 level,
1050                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1051                                 value,
1052                                 aniState->iniDef.cycpwrThr1);
1053                         ath_dbg(common, ANI,
1054                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1055                                 chan->channel,
1056                                 aniState->spurImmunityLevel,
1057                                 level,
1058                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1059                                 value2,
1060                                 aniState->iniDef.cycpwrThr1Ext);
1061                         if (level > aniState->spurImmunityLevel)
1062                                 ah->stats.ast_ani_spurup++;
1063                         else if (level < aniState->spurImmunityLevel)
1064                                 ah->stats.ast_ani_spurdown++;
1065                         aniState->spurImmunityLevel = level;
1066                 }
1067                 break;
1068         }
1069         case ATH9K_ANI_MRC_CCK:{
1070                 /*
1071                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1072                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1073                  */
1074                 bool is_on = param ? 1 : 0;
1075                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1076                               AR_PHY_MRC_CCK_ENABLE, is_on);
1077                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1078                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1079                 if (is_on != aniState->mrcCCK) {
1080                         ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1081                                 chan->channel,
1082                                 aniState->mrcCCK ? "on" : "off",
1083                                 is_on ? "on" : "off");
1084                 if (is_on)
1085                         ah->stats.ast_ani_ccklow++;
1086                 else
1087                         ah->stats.ast_ani_cckhigh++;
1088                 aniState->mrcCCK = is_on;
1089                 }
1090         break;
1091         }
1092         case ATH9K_ANI_PRESENT:
1093                 break;
1094         default:
1095                 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1096                 return false;
1097         }
1098
1099         ath_dbg(common, ANI,
1100                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1101                 aniState->spurImmunityLevel,
1102                 aniState->ofdmWeakSigDetect ? "on" : "off",
1103                 aniState->firstepLevel,
1104                 aniState->mrcCCK ? "on" : "off",
1105                 aniState->listenTime,
1106                 aniState->ofdmPhyErrCount,
1107                 aniState->cckPhyErrCount);
1108         return true;
1109 }
1110
1111 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1112                               int16_t nfarray[NUM_NF_READINGS])
1113 {
1114 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1115 #define AR_PHY_CH_MINCCA_PWR_S  20
1116 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1117 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1118
1119         int16_t nf;
1120         int i;
1121
1122         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1123                 if (ah->rxchainmask & BIT(i)) {
1124                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1125                                          AR_PHY_CH_MINCCA_PWR);
1126                         nfarray[i] = sign_extend32(nf, 8);
1127
1128                         if (IS_CHAN_HT40(ah->curchan)) {
1129                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1130
1131                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1132                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1133                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1134                         }
1135                 }
1136         }
1137 }
1138
1139 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1140 {
1141         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1142         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1143         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1144         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1145         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1146         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1147
1148         if (AR_SREV_9330(ah))
1149                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1150
1151         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1152                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1153                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1154                 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1155                 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1156         }
1157 }
1158
1159 /*
1160  * Initialize the ANI register values with default (ini) values.
1161  * This routine is called during a (full) hardware reset after
1162  * all the registers are initialised from the INI.
1163  */
1164 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1165 {
1166         struct ar5416AniState *aniState;
1167         struct ath_common *common = ath9k_hw_common(ah);
1168         struct ath9k_channel *chan = ah->curchan;
1169         struct ath9k_ani_default *iniDef;
1170         u32 val;
1171
1172         aniState = &ah->curchan->ani;
1173         iniDef = &aniState->iniDef;
1174
1175         ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1176                 ah->hw_version.macVersion,
1177                 ah->hw_version.macRev,
1178                 ah->opmode,
1179                 chan->channel,
1180                 chan->channelFlags);
1181
1182         val = REG_READ(ah, AR_PHY_SFCORR);
1183         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1184         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1185         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1186
1187         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1188         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1189         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1190         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1191
1192         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1193         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1194         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1195         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1196         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1197         iniDef->firstep = REG_READ_FIELD(ah,
1198                                          AR_PHY_FIND_SIG,
1199                                          AR_PHY_FIND_SIG_FIRSTEP);
1200         iniDef->firstepLow = REG_READ_FIELD(ah,
1201                                             AR_PHY_FIND_SIG_LOW,
1202                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1203         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1204                                             AR_PHY_TIMING5,
1205                                             AR_PHY_TIMING5_CYCPWR_THR1);
1206         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1207                                                AR_PHY_EXT_CCA,
1208                                                AR_PHY_EXT_CYCPWR_THR1);
1209
1210         /* these levels just got reset to defaults by the INI */
1211         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1212         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1213         aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1214         aniState->mrcCCK = true;
1215 }
1216
1217 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1218                                        struct ath_hw_radar_conf *conf)
1219 {
1220         u32 radar_0 = 0, radar_1 = 0;
1221
1222         if (!conf) {
1223                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1224                 return;
1225         }
1226
1227         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1228         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1229         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1230         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1231         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1232         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1233
1234         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1235         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1236         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1237         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1238         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1239
1240         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1241         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1242         if (conf->ext_channel)
1243                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1244         else
1245                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1246 }
1247
1248 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1249 {
1250         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1251
1252         conf->fir_power = -28;
1253         conf->radar_rssi = 0;
1254         conf->pulse_height = 10;
1255         conf->pulse_rssi = 24;
1256         conf->pulse_inband = 8;
1257         conf->pulse_maxlen = 255;
1258         conf->pulse_inband_step = 12;
1259         conf->radar_inband = 8;
1260 }
1261
1262 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1263                                            struct ath_hw_antcomb_conf *antconf)
1264 {
1265         u32 regval;
1266
1267         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1268         antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1269                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1270         antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1271                                  AR_PHY_ANT_DIV_ALT_LNACONF_S;
1272         antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1273                                   AR_PHY_ANT_FAST_DIV_BIAS_S;
1274
1275         if (AR_SREV_9330_11(ah)) {
1276                 antconf->lna1_lna2_delta = -9;
1277                 antconf->div_group = 1;
1278         } else if (AR_SREV_9485(ah)) {
1279                 antconf->lna1_lna2_delta = -9;
1280                 antconf->div_group = 2;
1281         } else if (AR_SREV_9565(ah)) {
1282                 antconf->lna1_lna2_delta = -3;
1283                 antconf->div_group = 3;
1284         } else {
1285                 antconf->lna1_lna2_delta = -3;
1286                 antconf->div_group = 0;
1287         }
1288 }
1289
1290 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1291                                    struct ath_hw_antcomb_conf *antconf)
1292 {
1293         u32 regval;
1294
1295         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1296         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1297                     AR_PHY_ANT_DIV_ALT_LNACONF |
1298                     AR_PHY_ANT_FAST_DIV_BIAS |
1299                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1300                     AR_PHY_ANT_DIV_ALT_GAINTB);
1301         regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1302                    & AR_PHY_ANT_DIV_MAIN_LNACONF);
1303         regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1304                    & AR_PHY_ANT_DIV_ALT_LNACONF);
1305         regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1306                    & AR_PHY_ANT_FAST_DIV_BIAS);
1307         regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1308                    & AR_PHY_ANT_DIV_MAIN_GAINTB);
1309         regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1310                    & AR_PHY_ANT_DIV_ALT_GAINTB);
1311
1312         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1313 }
1314
1315 static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1316                                                   bool enable)
1317 {
1318         u8 ant_div_ctl1;
1319         u32 regval;
1320
1321         if (!AR_SREV_9565(ah))
1322                 return;
1323
1324         ah->shared_chain_lnadiv = enable;
1325         ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1326
1327         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1328         regval &= (~AR_ANT_DIV_CTRL_ALL);
1329         regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1330         regval &= ~AR_PHY_ANT_DIV_LNADIV;
1331         regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1332
1333         if (enable)
1334                 regval |= AR_ANT_DIV_ENABLE;
1335
1336         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1337
1338         regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1339         regval &= ~AR_FAST_DIV_ENABLE;
1340         regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1341
1342         if (enable)
1343                 regval |= AR_FAST_DIV_ENABLE;
1344
1345         REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1346
1347         if (enable) {
1348                 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1349                             (1 << AR_PHY_ANT_SW_RX_PROT_S));
1350                 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
1351                         REG_SET_BIT(ah, AR_PHY_RESTART,
1352                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1353                 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1354                             AR_BTCOEX_WL_LNADIV_FORCE_ON);
1355         } else {
1356                 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1357                 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1358                             (1 << AR_PHY_ANT_SW_RX_PROT_S));
1359                 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1360                 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1361                             AR_BTCOEX_WL_LNADIV_FORCE_ON);
1362
1363                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1364                 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1365                         AR_PHY_ANT_DIV_ALT_LNACONF |
1366                         AR_PHY_ANT_DIV_MAIN_GAINTB |
1367                         AR_PHY_ANT_DIV_ALT_GAINTB);
1368                 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1369                 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1370                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1371         }
1372 }
1373
1374 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1375                                       struct ath9k_channel *chan,
1376                                       u8 *ini_reloaded)
1377 {
1378         unsigned int regWrites = 0;
1379         u32 modesIndex;
1380
1381         switch (chan->chanmode) {
1382         case CHANNEL_A:
1383         case CHANNEL_A_HT20:
1384                 modesIndex = 1;
1385                 break;
1386         case CHANNEL_A_HT40PLUS:
1387         case CHANNEL_A_HT40MINUS:
1388                 modesIndex = 2;
1389                 break;
1390         case CHANNEL_G:
1391         case CHANNEL_G_HT20:
1392         case CHANNEL_B:
1393                 modesIndex = 4;
1394                 break;
1395         case CHANNEL_G_HT40PLUS:
1396         case CHANNEL_G_HT40MINUS:
1397                 modesIndex = 3;
1398                 break;
1399
1400         default:
1401                 return -EINVAL;
1402         }
1403
1404         if (modesIndex == ah->modes_index) {
1405                 *ini_reloaded = false;
1406                 goto set_rfmode;
1407         }
1408
1409         ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1410         ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1411         ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1412         ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1413
1414         if (AR_SREV_9462_20(ah))
1415                 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1416                                    modesIndex);
1417
1418         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1419
1420         /*
1421          * For 5GHz channels requiring Fast Clock, apply
1422          * different modal values.
1423          */
1424         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1425                 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1426
1427         if (AR_SREV_9565(ah))
1428                 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1429
1430         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1431
1432         ah->modes_index = modesIndex;
1433         *ini_reloaded = true;
1434
1435 set_rfmode:
1436         ar9003_hw_set_rfmode(ah, chan);
1437         return 0;
1438 }
1439
1440 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1441 {
1442         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1443         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1444         static const u32 ar9300_cca_regs[6] = {
1445                 AR_PHY_CCA_0,
1446                 AR_PHY_CCA_1,
1447                 AR_PHY_CCA_2,
1448                 AR_PHY_EXT_CCA,
1449                 AR_PHY_EXT_CCA_1,
1450                 AR_PHY_EXT_CCA_2,
1451         };
1452
1453         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1454         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1455         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1456         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1457         priv_ops->init_bb = ar9003_hw_init_bb;
1458         priv_ops->process_ini = ar9003_hw_process_ini;
1459         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1460         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1461         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1462         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1463         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1464         priv_ops->ani_control = ar9003_hw_ani_control;
1465         priv_ops->do_getnf = ar9003_hw_do_getnf;
1466         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1467         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1468         priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1469
1470         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1471         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1472         ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
1473
1474         ar9003_hw_set_nf_limits(ah);
1475         ar9003_hw_set_radar_conf(ah);
1476         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1477 }
1478
1479 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1480 {
1481         struct ath_common *common = ath9k_hw_common(ah);
1482         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1483         u32 val, idle_count;
1484
1485         if (!idle_tmo_ms) {
1486                 /* disable IRQ, disable chip-reset for BB panic */
1487                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1488                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1489                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1490                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1491
1492                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1493                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1494                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1495                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1496                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1497
1498                 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1499                 return;
1500         }
1501
1502         /* enable IRQ, disable chip-reset for BB watchdog */
1503         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1504         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1505                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1506                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1507
1508         /* bound limit to 10 secs */
1509         if (idle_tmo_ms > 10000)
1510                 idle_tmo_ms = 10000;
1511
1512         /*
1513          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1514          *
1515          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1516          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1517          *
1518          * Given we use fast clock now in 5 GHz, these time units should
1519          * be common for both 2 GHz and 5 GHz.
1520          */
1521         idle_count = (100 * idle_tmo_ms) / 74;
1522         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1523                 idle_count = (100 * idle_tmo_ms) / 37;
1524
1525         /*
1526          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1527          * set idle time-out.
1528          */
1529         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1530                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1531                   AR_PHY_WATCHDOG_IDLE_MASK |
1532                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1533
1534         ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1535                 idle_tmo_ms);
1536 }
1537
1538 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1539 {
1540         /*
1541          * we want to avoid printing in ISR context so we save the
1542          * watchdog status to be printed later in bottom half context.
1543          */
1544         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1545
1546         /*
1547          * the watchdog timer should reset on status read but to be sure
1548          * sure we write 0 to the watchdog status bit.
1549          */
1550         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1551                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1552 }
1553
1554 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1555 {
1556         struct ath_common *common = ath9k_hw_common(ah);
1557         u32 status;
1558
1559         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1560                 return;
1561
1562         status = ah->bb_watchdog_last_status;
1563         ath_dbg(common, RESET,
1564                 "\n==== BB update: BB status=0x%08x ====\n", status);
1565         ath_dbg(common, RESET,
1566                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1567                 MS(status, AR_PHY_WATCHDOG_INFO),
1568                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1569                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1570                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1571                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1572                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1573                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1574                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1575                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1576
1577         ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1578                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1579                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1580         ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1581                 REG_READ(ah, AR_PHY_GEN_CTRL));
1582
1583 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1584         if (common->cc_survey.cycles)
1585                 ath_dbg(common, RESET,
1586                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1587                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1588
1589         ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1590 }
1591 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1592
1593 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1594 {
1595         u32 val;
1596
1597         /* While receiving unsupported rate frame rx state machine
1598          * gets into a state 0xb and if phy_restart happens in that
1599          * state, BB would go hang. If RXSM is in 0xb state after
1600          * first bb panic, ensure to disable the phy_restart.
1601          */
1602         if (!((MS(ah->bb_watchdog_last_status,
1603                   AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1604             ah->bb_hang_rx_ofdm))
1605                 return;
1606
1607         ah->bb_hang_rx_ofdm = true;
1608         val = REG_READ(ah, AR_PHY_RESTART);
1609         val &= ~AR_PHY_RESTART_ENA;
1610
1611         REG_WRITE(ah, AR_PHY_RESTART, val);
1612 }
1613 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);