tcp: detect SYN/data drop when F-RTO is disabled
[~shefty/rdma-dev.git] / drivers / net / wireless / brcm80211 / brcmsmac / main.c
1 /*
2  * Copyright (c) 2010 Broadcom Corporation
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
24 #include <aiutils.h>
25 #include <chipcommon.h>
26 #include "rate.h"
27 #include "scb.h"
28 #include "phy/phy_hal.h"
29 #include "channel.h"
30 #include "antsel.h"
31 #include "stf.h"
32 #include "ampdu.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
35 #include "main.h"
36 #include "soc.h"
37 #include "dma.h"
38 #include "debug.h"
39 #include "brcms_trace_events.h"
40
41 /* watchdog timer, in unit of ms */
42 #define TIMER_INTERVAL_WATCHDOG         1000
43 /* radio monitor timer, in unit of ms */
44 #define TIMER_INTERVAL_RADIOCHK         800
45
46 /* beacon interval, in unit of 1024TU */
47 #define BEACON_INTERVAL_DEFAULT         100
48
49 /* n-mode support capability */
50 /* 2x2 includes both 1x1 & 2x2 devices
51  * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
52  * control it independently
53  */
54 #define WL_11N_2x2                      1
55 #define WL_11N_3x3                      3
56 #define WL_11N_4x4                      4
57
58 #define EDCF_ACI_MASK                   0x60
59 #define EDCF_ACI_SHIFT                  5
60 #define EDCF_ECWMIN_MASK                0x0f
61 #define EDCF_ECWMAX_SHIFT               4
62 #define EDCF_AIFSN_MASK                 0x0f
63 #define EDCF_AIFSN_MAX                  15
64 #define EDCF_ECWMAX_MASK                0xf0
65
66 #define EDCF_AC_BE_TXOP_STA             0x0000
67 #define EDCF_AC_BK_TXOP_STA             0x0000
68 #define EDCF_AC_VO_ACI_STA              0x62
69 #define EDCF_AC_VO_ECW_STA              0x32
70 #define EDCF_AC_VI_ACI_STA              0x42
71 #define EDCF_AC_VI_ECW_STA              0x43
72 #define EDCF_AC_BK_ECW_STA              0xA4
73 #define EDCF_AC_VI_TXOP_STA             0x005e
74 #define EDCF_AC_VO_TXOP_STA             0x002f
75 #define EDCF_AC_BE_ACI_STA              0x03
76 #define EDCF_AC_BE_ECW_STA              0xA4
77 #define EDCF_AC_BK_ACI_STA              0x27
78 #define EDCF_AC_VO_TXOP_AP              0x002f
79
80 #define EDCF_TXOP2USEC(txop)            ((txop) << 5)
81 #define EDCF_ECW2CW(exp)                ((1 << (exp)) - 1)
82
83 #define APHY_SYMBOL_TIME                4
84 #define APHY_PREAMBLE_TIME              16
85 #define APHY_SIGNAL_TIME                4
86 #define APHY_SIFS_TIME                  16
87 #define APHY_SERVICE_NBITS              16
88 #define APHY_TAIL_NBITS                 6
89 #define BPHY_SIFS_TIME                  10
90 #define BPHY_PLCP_SHORT_TIME            96
91
92 #define PREN_PREAMBLE                   24
93 #define PREN_MM_EXT                     12
94 #define PREN_PREAMBLE_EXT               4
95
96 #define DOT11_MAC_HDR_LEN               24
97 #define DOT11_ACK_LEN                   10
98 #define DOT11_BA_LEN                    4
99 #define DOT11_OFDM_SIGNAL_EXTENSION     6
100 #define DOT11_MIN_FRAG_LEN              256
101 #define DOT11_RTS_LEN                   16
102 #define DOT11_CTS_LEN                   10
103 #define DOT11_BA_BITMAP_LEN             128
104 #define DOT11_MIN_BEACON_PERIOD         1
105 #define DOT11_MAX_BEACON_PERIOD         0xFFFF
106 #define DOT11_MAXNUMFRAGS               16
107 #define DOT11_MAX_FRAG_LEN              2346
108
109 #define BPHY_PLCP_TIME                  192
110 #define RIFS_11N_TIME                   2
111
112 /* length of the BCN template area */
113 #define BCN_TMPL_LEN                    512
114
115 /* brcms_bss_info flag bit values */
116 #define BRCMS_BSS_HT                    0x0020  /* BSS is HT (MIMO) capable */
117
118 /* chip rx buffer offset */
119 #define BRCMS_HWRXOFF                   38
120
121 /* rfdisable delay timer 500 ms, runs of ALP clock */
122 #define RFDISABLE_DEFAULT               10000000
123
124 #define BRCMS_TEMPSENSE_PERIOD          10      /* 10 second timeout */
125
126 /* synthpu_dly times in us */
127 #define SYNTHPU_DLY_APHY_US             3700
128 #define SYNTHPU_DLY_BPHY_US             1050
129 #define SYNTHPU_DLY_NPHY_US             2048
130 #define SYNTHPU_DLY_LPPHY_US            300
131
132 #define ANTCNT                          10      /* vanilla M_MAX_ANTCNT val */
133
134 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
135 #define EDCF_SHORT_S                    0
136 #define EDCF_SFB_S                      4
137 #define EDCF_LONG_S                     8
138 #define EDCF_LFB_S                      12
139 #define EDCF_SHORT_M                    BITFIELD_MASK(4)
140 #define EDCF_SFB_M                      BITFIELD_MASK(4)
141 #define EDCF_LONG_M                     BITFIELD_MASK(4)
142 #define EDCF_LFB_M                      BITFIELD_MASK(4)
143
144 #define RETRY_SHORT_DEF                 7       /* Default Short retry Limit */
145 #define RETRY_SHORT_MAX                 255     /* Maximum Short retry Limit */
146 #define RETRY_LONG_DEF                  4       /* Default Long retry count */
147 #define RETRY_SHORT_FB                  3       /* Short count for fb rate */
148 #define RETRY_LONG_FB                   2       /* Long count for fb rate */
149
150 #define APHY_CWMIN                      15
151 #define PHY_CWMAX                       1023
152
153 #define EDCF_AIFSN_MIN                  1
154
155 #define FRAGNUM_MASK                    0xF
156
157 #define APHY_SLOT_TIME                  9
158 #define BPHY_SLOT_TIME                  20
159
160 #define WL_SPURAVOID_OFF                0
161 #define WL_SPURAVOID_ON1                1
162 #define WL_SPURAVOID_ON2                2
163
164 /* invalid core flags, use the saved coreflags */
165 #define BRCMS_USE_COREFLAGS             0xffffffff
166
167 /* values for PLCPHdr_override */
168 #define BRCMS_PLCP_AUTO                 -1
169 #define BRCMS_PLCP_SHORT                0
170 #define BRCMS_PLCP_LONG                 1
171
172 /* values for g_protection_override and n_protection_override */
173 #define BRCMS_PROTECTION_AUTO           -1
174 #define BRCMS_PROTECTION_OFF            0
175 #define BRCMS_PROTECTION_ON             1
176 #define BRCMS_PROTECTION_MMHDR_ONLY     2
177 #define BRCMS_PROTECTION_CTS_ONLY       3
178
179 /* values for g_protection_control and n_protection_control */
180 #define BRCMS_PROTECTION_CTL_OFF        0
181 #define BRCMS_PROTECTION_CTL_LOCAL      1
182 #define BRCMS_PROTECTION_CTL_OVERLAP    2
183
184 /* values for n_protection */
185 #define BRCMS_N_PROTECTION_OFF          0
186 #define BRCMS_N_PROTECTION_OPTIONAL     1
187 #define BRCMS_N_PROTECTION_20IN40       2
188 #define BRCMS_N_PROTECTION_MIXEDMODE    3
189
190 /* values for band specific 40MHz capabilities */
191 #define BRCMS_N_BW_20ALL                0
192 #define BRCMS_N_BW_40ALL                1
193 #define BRCMS_N_BW_20IN2G_40IN5G        2
194
195 /* bitflags for SGI support (sgi_rx iovar) */
196 #define BRCMS_N_SGI_20                  0x01
197 #define BRCMS_N_SGI_40                  0x02
198
199 /* defines used by the nrate iovar */
200 /* MSC in use,indicates b0-6 holds an mcs */
201 #define NRATE_MCS_INUSE                 0x00000080
202 /* rate/mcs value */
203 #define NRATE_RATE_MASK                 0x0000007f
204 /* stf mode mask: siso, cdd, stbc, sdm */
205 #define NRATE_STF_MASK                  0x0000ff00
206 /* stf mode shift */
207 #define NRATE_STF_SHIFT                 8
208 /* bit indicate to override mcs only */
209 #define NRATE_OVERRIDE_MCS_ONLY         0x40000000
210 #define NRATE_SGI_MASK                  0x00800000      /* sgi mode */
211 #define NRATE_SGI_SHIFT                 23              /* sgi mode */
212 #define NRATE_LDPC_CODING               0x00400000      /* adv coding in use */
213 #define NRATE_LDPC_SHIFT                22              /* ldpc shift */
214
215 #define NRATE_STF_SISO                  0               /* stf mode SISO */
216 #define NRATE_STF_CDD                   1               /* stf mode CDD */
217 #define NRATE_STF_STBC                  2               /* stf mode STBC */
218 #define NRATE_STF_SDM                   3               /* stf mode SDM */
219
220 #define MAX_DMA_SEGS                    4
221
222 /* # of entries in Tx FIFO */
223 #define NTXD                            64
224 /* Max # of entries in Rx FIFO based on 4kb page size */
225 #define NRXD                            256
226
227 /* Amount of headroom to leave in Tx FIFO */
228 #define TX_HEADROOM                     4
229
230 /* try to keep this # rbufs posted to the chip */
231 #define NRXBUFPOST                      32
232
233 /* max # frames to process in brcms_c_recv() */
234 #define RXBND                           8
235 /* max # tx status to process in wlc_txstatus() */
236 #define TXSBND                          8
237
238 /* brcmu_format_flags() bit description structure */
239 struct brcms_c_bit_desc {
240         u32 bit;
241         const char *name;
242 };
243
244 /*
245  * The following table lists the buffer memory allocated to xmt fifos in HW.
246  * the size is in units of 256bytes(one block), total size is HW dependent
247  * ucode has default fifo partition, sw can overwrite if necessary
248  *
249  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
250  * the twiki is updated before making changes.
251  */
252
253 /* Starting corerev for the fifo size table */
254 #define XMTFIFOTBL_STARTREV     17
255
256 struct d11init {
257         __le16 addr;
258         __le16 size;
259         __le32 value;
260 };
261
262 struct edcf_acparam {
263         u8 ACI;
264         u8 ECW;
265         u16 TXOP;
266 } __packed;
267
268 /* debug/trace */
269 uint brcm_msg_level;
270
271 /* TX FIFO number to WME/802.1E Access Category */
272 static const u8 wme_fifo2ac[] = {
273         IEEE80211_AC_BK,
274         IEEE80211_AC_BE,
275         IEEE80211_AC_VI,
276         IEEE80211_AC_VO,
277         IEEE80211_AC_BE,
278         IEEE80211_AC_BE
279 };
280
281 /* ieee80211 Access Category to TX FIFO number */
282 static const u8 wme_ac2fifo[] = {
283         TX_AC_VO_FIFO,
284         TX_AC_VI_FIFO,
285         TX_AC_BE_FIFO,
286         TX_AC_BK_FIFO
287 };
288
289 static const u16 xmtfifo_sz[][NFIFO] = {
290         /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
291         {20, 192, 192, 21, 17, 5},
292         /* corerev 18: */
293         {0, 0, 0, 0, 0, 0},
294         /* corerev 19: */
295         {0, 0, 0, 0, 0, 0},
296         /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
297         {20, 192, 192, 21, 17, 5},
298         /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
299         {9, 58, 22, 14, 14, 5},
300         /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
301         {20, 192, 192, 21, 17, 5},
302         /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
303         {20, 192, 192, 21, 17, 5},
304         /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
305         {9, 58, 22, 14, 14, 5},
306         /* corerev 25: */
307         {0, 0, 0, 0, 0, 0},
308         /* corerev 26: */
309         {0, 0, 0, 0, 0, 0},
310         /* corerev 27: */
311         {0, 0, 0, 0, 0, 0},
312         /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
313         {9, 58, 22, 14, 14, 5},
314 };
315
316 #ifdef DEBUG
317 static const char * const fifo_names[] = {
318         "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
319 #else
320 static const char fifo_names[6][0];
321 #endif
322
323 #ifdef DEBUG
324 /* pointer to most recently allocated wl/wlc */
325 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
326 #endif
327
328 /* Mapping of ieee80211 AC numbers to tx fifos */
329 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
330         [IEEE80211_AC_VO]       = TX_AC_VO_FIFO,
331         [IEEE80211_AC_VI]       = TX_AC_VI_FIFO,
332         [IEEE80211_AC_BE]       = TX_AC_BE_FIFO,
333         [IEEE80211_AC_BK]       = TX_AC_BK_FIFO,
334 };
335
336 /* Mapping of tx fifos to ieee80211 AC numbers */
337 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
338         [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
339         [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
340         [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
341         [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
342 };
343
344 static u8 brcms_ac_to_fifo(u8 ac)
345 {
346         if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
347                 return TX_AC_BE_FIFO;
348         return ac_to_fifo_mapping[ac];
349 }
350
351 static u8 brcms_fifo_to_ac(u8 fifo)
352 {
353         if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
354                 return IEEE80211_AC_BE;
355         return fifo_to_ac_mapping[fifo];
356 }
357
358 /* Find basic rate for a given rate */
359 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
360 {
361         if (is_mcs_rate(rspec))
362                 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
363                        .leg_ofdm];
364         return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
365 }
366
367 static u16 frametype(u32 rspec, u8 mimoframe)
368 {
369         if (is_mcs_rate(rspec))
370                 return mimoframe;
371         return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
372 }
373
374 /* currently the best mechanism for determining SIFS is the band in use */
375 static u16 get_sifs(struct brcms_band *band)
376 {
377         return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
378                                  BPHY_SIFS_TIME;
379 }
380
381 /*
382  * Detect Card removed.
383  * Even checking an sbconfig register read will not false trigger when the core
384  * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
385  * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
386  * reg with fixed 0/1 pattern (some platforms return all 0).
387  * If clocks are present, call the sb routine which will figure out if the
388  * device is removed.
389  */
390 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
391 {
392         u32 macctrl;
393
394         if (!wlc->hw->clk)
395                 return ai_deviceremoved(wlc->hw->sih);
396         macctrl = bcma_read32(wlc->hw->d11core,
397                               D11REGOFFS(maccontrol));
398         return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
399 }
400
401 /* sum the individual fifo tx pending packet counts */
402 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
403 {
404         int i;
405         int pending = 0;
406
407         for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
408                 if (wlc->hw->di[i])
409                         pending += dma_txpending(wlc->hw->di[i]);
410         return pending;
411 }
412
413 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
414 {
415         return wlc->pub->_nbands > 1 && !wlc->bandlocked;
416 }
417
418 static int brcms_chspec_bw(u16 chanspec)
419 {
420         if (CHSPEC_IS40(chanspec))
421                 return BRCMS_40_MHZ;
422         if (CHSPEC_IS20(chanspec))
423                 return BRCMS_20_MHZ;
424
425         return BRCMS_10_MHZ;
426 }
427
428 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
429 {
430         if (cfg == NULL)
431                 return;
432
433         kfree(cfg->current_bss);
434         kfree(cfg);
435 }
436
437 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
438 {
439         if (wlc == NULL)
440                 return;
441
442         brcms_c_bsscfg_mfree(wlc->bsscfg);
443         kfree(wlc->pub);
444         kfree(wlc->modulecb);
445         kfree(wlc->default_bss);
446         kfree(wlc->protection);
447         kfree(wlc->stf);
448         kfree(wlc->bandstate[0]);
449         kfree(wlc->corestate->macstat_snapshot);
450         kfree(wlc->corestate);
451         kfree(wlc->hw->bandstate[0]);
452         kfree(wlc->hw);
453
454         /* free the wlc */
455         kfree(wlc);
456         wlc = NULL;
457 }
458
459 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
460 {
461         struct brcms_bss_cfg *cfg;
462
463         cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
464         if (cfg == NULL)
465                 goto fail;
466
467         cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
468         if (cfg->current_bss == NULL)
469                 goto fail;
470
471         return cfg;
472
473  fail:
474         brcms_c_bsscfg_mfree(cfg);
475         return NULL;
476 }
477
478 static struct brcms_c_info *
479 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
480 {
481         struct brcms_c_info *wlc;
482
483         wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
484         if (wlc == NULL) {
485                 *err = 1002;
486                 goto fail;
487         }
488
489         /* allocate struct brcms_c_pub state structure */
490         wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
491         if (wlc->pub == NULL) {
492                 *err = 1003;
493                 goto fail;
494         }
495         wlc->pub->wlc = wlc;
496
497         /* allocate struct brcms_hardware state structure */
498
499         wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
500         if (wlc->hw == NULL) {
501                 *err = 1005;
502                 goto fail;
503         }
504         wlc->hw->wlc = wlc;
505
506         wlc->hw->bandstate[0] =
507                 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
508         if (wlc->hw->bandstate[0] == NULL) {
509                 *err = 1006;
510                 goto fail;
511         } else {
512                 int i;
513
514                 for (i = 1; i < MAXBANDS; i++)
515                         wlc->hw->bandstate[i] = (struct brcms_hw_band *)
516                             ((unsigned long)wlc->hw->bandstate[0] +
517                              (sizeof(struct brcms_hw_band) * i));
518         }
519
520         wlc->modulecb =
521                 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
522         if (wlc->modulecb == NULL) {
523                 *err = 1009;
524                 goto fail;
525         }
526
527         wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
528         if (wlc->default_bss == NULL) {
529                 *err = 1010;
530                 goto fail;
531         }
532
533         wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
534         if (wlc->bsscfg == NULL) {
535                 *err = 1011;
536                 goto fail;
537         }
538
539         wlc->protection = kzalloc(sizeof(struct brcms_protection),
540                                   GFP_ATOMIC);
541         if (wlc->protection == NULL) {
542                 *err = 1016;
543                 goto fail;
544         }
545
546         wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
547         if (wlc->stf == NULL) {
548                 *err = 1017;
549                 goto fail;
550         }
551
552         wlc->bandstate[0] =
553                 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
554         if (wlc->bandstate[0] == NULL) {
555                 *err = 1025;
556                 goto fail;
557         } else {
558                 int i;
559
560                 for (i = 1; i < MAXBANDS; i++)
561                         wlc->bandstate[i] = (struct brcms_band *)
562                                 ((unsigned long)wlc->bandstate[0]
563                                 + (sizeof(struct brcms_band)*i));
564         }
565
566         wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
567         if (wlc->corestate == NULL) {
568                 *err = 1026;
569                 goto fail;
570         }
571
572         wlc->corestate->macstat_snapshot =
573                 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
574         if (wlc->corestate->macstat_snapshot == NULL) {
575                 *err = 1027;
576                 goto fail;
577         }
578
579         return wlc;
580
581  fail:
582         brcms_c_detach_mfree(wlc);
583         return NULL;
584 }
585
586 /*
587  * Update the slot timing for standard 11b/g (20us slots)
588  * or shortslot 11g (9us slots)
589  * The PSM needs to be suspended for this call.
590  */
591 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
592                                         bool shortslot)
593 {
594         struct bcma_device *core = wlc_hw->d11core;
595
596         if (shortslot) {
597                 /* 11g short slot: 11a timing */
598                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
599                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
600         } else {
601                 /* 11g long slot: 11b timing */
602                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
603                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
604         }
605 }
606
607 /*
608  * calculate frame duration of a given rate and length, return
609  * time in usec unit
610  */
611 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
612                                     u8 preamble_type, uint mac_len)
613 {
614         uint nsyms, dur = 0, Ndps, kNdps;
615         uint rate = rspec2rate(ratespec);
616
617         if (rate == 0) {
618                 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
619                           wlc->pub->unit);
620                 rate = BRCM_RATE_1M;
621         }
622
623         if (is_mcs_rate(ratespec)) {
624                 uint mcs = ratespec & RSPEC_RATE_MASK;
625                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
626
627                 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
628                 if (preamble_type == BRCMS_MM_PREAMBLE)
629                         dur += PREN_MM_EXT;
630                 /* 1000Ndbps = kbps * 4 */
631                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
632                                    rspec_issgi(ratespec)) * 4;
633
634                 if (rspec_stc(ratespec) == 0)
635                         nsyms =
636                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
637                                   APHY_TAIL_NBITS) * 1000, kNdps);
638                 else
639                         /* STBC needs to have even number of symbols */
640                         nsyms =
641                             2 *
642                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
643                                   APHY_TAIL_NBITS) * 1000, 2 * kNdps);
644
645                 dur += APHY_SYMBOL_TIME * nsyms;
646                 if (wlc->band->bandtype == BRCM_BAND_2G)
647                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
648         } else if (is_ofdm_rate(rate)) {
649                 dur = APHY_PREAMBLE_TIME;
650                 dur += APHY_SIGNAL_TIME;
651                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
652                 Ndps = rate * 2;
653                 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
654                 nsyms =
655                     CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
656                          Ndps);
657                 dur += APHY_SYMBOL_TIME * nsyms;
658                 if (wlc->band->bandtype == BRCM_BAND_2G)
659                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
660         } else {
661                 /*
662                  * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
663                  * will divide out
664                  */
665                 mac_len = mac_len * 8 * 2;
666                 /* calc ceiling of bits/rate = microseconds of air time */
667                 dur = (mac_len + rate - 1) / rate;
668                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
669                         dur += BPHY_PLCP_SHORT_TIME;
670                 else
671                         dur += BPHY_PLCP_TIME;
672         }
673         return dur;
674 }
675
676 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
677                                 const struct d11init *inits)
678 {
679         struct bcma_device *core = wlc_hw->d11core;
680         int i;
681         uint offset;
682         u16 size;
683         u32 value;
684
685         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
686
687         for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
688                 size = le16_to_cpu(inits[i].size);
689                 offset = le16_to_cpu(inits[i].addr);
690                 value = le32_to_cpu(inits[i].value);
691                 if (size == 2)
692                         bcma_write16(core, offset, value);
693                 else if (size == 4)
694                         bcma_write32(core, offset, value);
695                 else
696                         break;
697         }
698 }
699
700 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
701 {
702         u8 idx;
703         u16 addr[] = {
704                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
705                 M_HOST_FLAGS5
706         };
707
708         for (idx = 0; idx < MHFMAX; idx++)
709                 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
710 }
711
712 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
713 {
714         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
715
716         /* init microcode host flags */
717         brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
718
719         /* do band-specific ucode IHR, SHM, and SCR inits */
720         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
721                 if (BRCMS_ISNPHY(wlc_hw->band))
722                         brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
723                 else
724                         brcms_err(wlc_hw->d11core,
725                                   "%s: wl%d: unsupported phy in corerev %d\n",
726                                   __func__, wlc_hw->unit,
727                                   wlc_hw->corerev);
728         } else {
729                 if (D11REV_IS(wlc_hw->corerev, 24)) {
730                         if (BRCMS_ISLCNPHY(wlc_hw->band))
731                                 brcms_c_write_inits(wlc_hw,
732                                                     ucode->d11lcn0bsinitvals24);
733                         else
734                                 brcms_err(wlc_hw->d11core,
735                                           "%s: wl%d: unsupported phy in core rev %d\n",
736                                           __func__, wlc_hw->unit,
737                                           wlc_hw->corerev);
738                 } else {
739                         brcms_err(wlc_hw->d11core,
740                                   "%s: wl%d: unsupported corerev %d\n",
741                                   __func__, wlc_hw->unit, wlc_hw->corerev);
742                 }
743         }
744 }
745
746 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
747 {
748         struct bcma_device *core = wlc_hw->d11core;
749         u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
750
751         bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
752 }
753
754 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
755 {
756         brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
757
758         wlc_hw->phyclk = clk;
759
760         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
761
762                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
763                                    (SICF_PRST | SICF_FGC));
764                 udelay(1);
765                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
766                 udelay(1);
767
768         } else {                /* take phy out of reset */
769
770                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
771                 udelay(1);
772                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
773                 udelay(1);
774
775         }
776 }
777
778 /* low-level band switch utility routine */
779 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
780 {
781         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
782                            bandunit);
783
784         wlc_hw->band = wlc_hw->bandstate[bandunit];
785
786         /*
787          * BMAC_NOTE:
788          *   until we eliminate need for wlc->band refs in low level code
789          */
790         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
791
792         /* set gmode core flag */
793         if (wlc_hw->sbclk && !wlc_hw->noreset) {
794                 u32 gmode = 0;
795
796                 if (bandunit == 0)
797                         gmode = SICF_GMODE;
798
799                 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
800         }
801 }
802
803 /* switch to new band but leave it inactive */
804 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
805 {
806         struct brcms_hardware *wlc_hw = wlc->hw;
807         u32 macintmask;
808         u32 macctrl;
809
810         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
811         macctrl = bcma_read32(wlc_hw->d11core,
812                               D11REGOFFS(maccontrol));
813         WARN_ON((macctrl & MCTL_EN_MAC) != 0);
814
815         /* disable interrupts */
816         macintmask = brcms_intrsoff(wlc->wl);
817
818         /* radio off */
819         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
820
821         brcms_b_core_phy_clk(wlc_hw, OFF);
822
823         brcms_c_setxband(wlc_hw, bandunit);
824
825         return macintmask;
826 }
827
828 /* process an individual struct tx_status */
829 static bool
830 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
831 {
832         struct sk_buff *p = NULL;
833         uint queue = NFIFO;
834         struct dma_pub *dma = NULL;
835         struct d11txh *txh = NULL;
836         struct scb *scb = NULL;
837         bool free_pdu;
838         int tx_rts, tx_frame_count, tx_rts_count;
839         uint totlen, supr_status;
840         bool lastframe;
841         struct ieee80211_hdr *h;
842         u16 mcl;
843         struct ieee80211_tx_info *tx_info;
844         struct ieee80211_tx_rate *txrate;
845         int i;
846         bool fatal = true;
847
848         trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
849                              txs->frameid, txs->status, txs->lasttxtime,
850                              txs->sequence, txs->phyerr, txs->ackphyrxsh);
851
852         /* discard intermediate indications for ucode with one legitimate case:
853          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
854          *   but the subsequent tx of DATA failed. so it will start rts/cts
855          *   from the beginning (resetting the rts transmission count)
856          */
857         if (!(txs->status & TX_STATUS_AMPDU)
858             && (txs->status & TX_STATUS_INTERMEDIATE)) {
859                 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
860                 fatal = false;
861                 goto out;
862         }
863
864         queue = txs->frameid & TXFID_QUEUE_MASK;
865         if (queue >= NFIFO) {
866                 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
867                 goto out;
868         }
869
870         dma = wlc->hw->di[queue];
871
872         p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
873         if (p == NULL) {
874                 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
875                 goto out;
876         }
877
878         txh = (struct d11txh *) (p->data);
879         mcl = le16_to_cpu(txh->MacTxControlLow);
880
881         if (txs->phyerr)
882                 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
883                           txs->phyerr, txh->MainRates);
884
885         if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
886                 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
887                 goto out;
888         }
889         tx_info = IEEE80211_SKB_CB(p);
890         h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
891
892         if (tx_info->rate_driver_data[0])
893                 scb = &wlc->pri_scb;
894
895         if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
896                 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
897                 fatal = false;
898                 goto out;
899         }
900
901         /*
902          * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
903          * frames; this traces them for the rest.
904          */
905         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
906
907         supr_status = txs->status & TX_STATUS_SUPR_MASK;
908         if (supr_status == TX_STATUS_SUPR_BADCH) {
909                 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
910                 brcms_dbg_tx(wlc->hw->d11core,
911                              "Pkt tx suppressed, dest chan %u, current %d\n",
912                              (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
913                              CHSPEC_CHANNEL(wlc->default_bss->chanspec));
914         }
915
916         tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
917         tx_frame_count =
918             (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
919         tx_rts_count =
920             (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
921
922         lastframe = !ieee80211_has_morefrags(h->frame_control);
923
924         if (!lastframe) {
925                 brcms_err(wlc->hw->d11core, "Not last frame!\n");
926         } else {
927                 /*
928                  * Set information to be consumed by Minstrel ht.
929                  *
930                  * The "fallback limit" is the number of tx attempts a given
931                  * MPDU is sent at the "primary" rate. Tx attempts beyond that
932                  * limit are sent at the "secondary" rate.
933                  * A 'short frame' does not exceed RTS treshold.
934                  */
935                 u16 sfbl,       /* Short Frame Rate Fallback Limit */
936                     lfbl,       /* Long Frame Rate Fallback Limit */
937                     fbl;
938
939                 if (queue < IEEE80211_NUM_ACS) {
940                         sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
941                                       EDCF_SFB);
942                         lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
943                                       EDCF_LFB);
944                 } else {
945                         sfbl = wlc->SFBL;
946                         lfbl = wlc->LFBL;
947                 }
948
949                 txrate = tx_info->status.rates;
950                 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
951                         fbl = lfbl;
952                 else
953                         fbl = sfbl;
954
955                 ieee80211_tx_info_clear_status(tx_info);
956
957                 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
958                         /*
959                          * rate selection requested a fallback rate
960                          * and we used it
961                          */
962                         txrate[0].count = fbl;
963                         txrate[1].count = tx_frame_count - fbl;
964                 } else {
965                         /*
966                          * rate selection did not request fallback rate, or
967                          * we didn't need it
968                          */
969                         txrate[0].count = tx_frame_count;
970                         /*
971                          * rc80211_minstrel.c:minstrel_tx_status() expects
972                          * unused rates to be marked with idx = -1
973                          */
974                         txrate[1].idx = -1;
975                         txrate[1].count = 0;
976                 }
977
978                 /* clear the rest of the rates */
979                 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
980                         txrate[i].idx = -1;
981                         txrate[i].count = 0;
982                 }
983
984                 if (txs->status & TX_STATUS_ACK_RCV)
985                         tx_info->flags |= IEEE80211_TX_STAT_ACK;
986         }
987
988         totlen = p->len;
989         free_pdu = true;
990
991         if (lastframe) {
992                 /* remove PLCP & Broadcom tx descriptor header */
993                 skb_pull(p, D11_PHY_HDR_LEN);
994                 skb_pull(p, D11_TXH_LEN);
995                 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
996         } else {
997                 brcms_err(wlc->hw->d11core,
998                           "%s: Not last frame => not calling tx_status\n",
999                           __func__);
1000         }
1001
1002         fatal = false;
1003
1004  out:
1005         if (fatal) {
1006                 if (txh)
1007                         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1008                                            sizeof(*txh));
1009                 if (p)
1010                         brcmu_pkt_buf_free_skb(p);
1011         }
1012
1013         if (dma && queue < NFIFO) {
1014                 u16 ac_queue = brcms_fifo_to_ac(queue);
1015                 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1016                     ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1017                         ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1018                 dma_kick_tx(dma);
1019         }
1020
1021         return fatal;
1022 }
1023
1024 /* process tx completion events in BMAC
1025  * Return true if more tx status need to be processed. false otherwise.
1026  */
1027 static bool
1028 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1029 {
1030         bool morepending = false;
1031         struct bcma_device *core;
1032         struct tx_status txstatus, *txs;
1033         u32 s1, s2;
1034         uint n = 0;
1035         /*
1036          * Param 'max_tx_num' indicates max. # tx status to process before
1037          * break out.
1038          */
1039         uint max_tx_num = bound ? TXSBND : -1;
1040
1041         txs = &txstatus;
1042         core = wlc_hw->d11core;
1043         *fatal = false;
1044         s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1045         while (!(*fatal)
1046                && (s1 & TXS_V)) {
1047                 /* !give others some time to run! */
1048                 if (n >= max_tx_num) {
1049                         morepending = true;
1050                         break;
1051                 }
1052
1053                 if (s1 == 0xffffffff) {
1054                         brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1055                                   __func__);
1056                         *fatal = true;
1057                         return false;
1058                 }
1059                 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1060
1061                 txs->status = s1 & TXS_STATUS_MASK;
1062                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1063                 txs->sequence = s2 & TXS_SEQ_MASK;
1064                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1065                 txs->lasttxtime = 0;
1066
1067                 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1068
1069                 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1070                 n++;
1071         }
1072
1073         if (*fatal)
1074                 return false;
1075
1076         return morepending;
1077 }
1078
1079 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1080 {
1081         if (!wlc->bsscfg->BSS)
1082                 /*
1083                  * DirFrmQ is now valid...defer setting until end
1084                  * of ATIM window
1085                  */
1086                 wlc->qvalid |= MCMD_DIRFRMQVAL;
1087 }
1088
1089 /* set initial host flags value */
1090 static void
1091 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1092 {
1093         struct brcms_hardware *wlc_hw = wlc->hw;
1094
1095         memset(mhfs, 0, MHFMAX * sizeof(u16));
1096
1097         mhfs[MHF2] |= mhf2_init;
1098
1099         /* prohibit use of slowclock on multifunction boards */
1100         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1101                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1102
1103         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1104                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1105                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1106         }
1107 }
1108
1109 static uint
1110 dmareg(uint direction, uint fifonum)
1111 {
1112         if (direction == DMA_TX)
1113                 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1114         return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1115 }
1116
1117 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1118 {
1119         uint i;
1120         char name[8];
1121         /*
1122          * ucode host flag 2 needed for pio mode, independent of band and fifo
1123          */
1124         u16 pio_mhf2 = 0;
1125         struct brcms_hardware *wlc_hw = wlc->hw;
1126         uint unit = wlc_hw->unit;
1127
1128         /* name and offsets for dma_attach */
1129         snprintf(name, sizeof(name), "wl%d", unit);
1130
1131         if (wlc_hw->di[0] == NULL) {    /* Init FIFOs */
1132                 int dma_attach_err = 0;
1133
1134                 /*
1135                  * FIFO 0
1136                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1137                  * RX: RX_FIFO (RX data packets)
1138                  */
1139                 wlc_hw->di[0] = dma_attach(name, wlc,
1140                                            (wme ? dmareg(DMA_TX, 0) : 0),
1141                                            dmareg(DMA_RX, 0),
1142                                            (wme ? NTXD : 0), NRXD,
1143                                            RXBUFSZ, -1, NRXBUFPOST,
1144                                            BRCMS_HWRXOFF);
1145                 dma_attach_err |= (NULL == wlc_hw->di[0]);
1146
1147                 /*
1148                  * FIFO 1
1149                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1150                  *   (legacy) TX_DATA_FIFO (TX data packets)
1151                  * RX: UNUSED
1152                  */
1153                 wlc_hw->di[1] = dma_attach(name, wlc,
1154                                            dmareg(DMA_TX, 1), 0,
1155                                            NTXD, 0, 0, -1, 0, 0);
1156                 dma_attach_err |= (NULL == wlc_hw->di[1]);
1157
1158                 /*
1159                  * FIFO 2
1160                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1161                  * RX: UNUSED
1162                  */
1163                 wlc_hw->di[2] = dma_attach(name, wlc,
1164                                            dmareg(DMA_TX, 2), 0,
1165                                            NTXD, 0, 0, -1, 0, 0);
1166                 dma_attach_err |= (NULL == wlc_hw->di[2]);
1167                 /*
1168                  * FIFO 3
1169                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1170                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1171                  */
1172                 wlc_hw->di[3] = dma_attach(name, wlc,
1173                                            dmareg(DMA_TX, 3),
1174                                            0, NTXD, 0, 0, -1,
1175                                            0, 0);
1176                 dma_attach_err |= (NULL == wlc_hw->di[3]);
1177 /* Cleaner to leave this as if with AP defined */
1178
1179                 if (dma_attach_err) {
1180                         brcms_err(wlc_hw->d11core,
1181                                   "wl%d: wlc_attach: dma_attach failed\n",
1182                                   unit);
1183                         return false;
1184                 }
1185
1186                 /* get pointer to dma engine tx flow control variable */
1187                 for (i = 0; i < NFIFO; i++)
1188                         if (wlc_hw->di[i])
1189                                 wlc_hw->txavail[i] =
1190                                     (uint *) dma_getvar(wlc_hw->di[i],
1191                                                         "&txavail");
1192         }
1193
1194         /* initial ucode host flags */
1195         brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1196
1197         return true;
1198 }
1199
1200 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1201 {
1202         uint j;
1203
1204         for (j = 0; j < NFIFO; j++) {
1205                 if (wlc_hw->di[j]) {
1206                         dma_detach(wlc_hw->di[j]);
1207                         wlc_hw->di[j] = NULL;
1208                 }
1209         }
1210 }
1211
1212 /*
1213  * Initialize brcms_c_info default values ...
1214  * may get overrides later in this function
1215  *  BMAC_NOTES, move low out and resolve the dangling ones
1216  */
1217 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1218 {
1219         struct brcms_c_info *wlc = wlc_hw->wlc;
1220
1221         /* set default sw macintmask value */
1222         wlc->defmacintmask = DEF_MACINTMASK;
1223
1224         /* various 802.11g modes */
1225         wlc_hw->shortslot = false;
1226
1227         wlc_hw->SFBL = RETRY_SHORT_FB;
1228         wlc_hw->LFBL = RETRY_LONG_FB;
1229
1230         /* default mac retry limits */
1231         wlc_hw->SRL = RETRY_SHORT_DEF;
1232         wlc_hw->LRL = RETRY_LONG_DEF;
1233         wlc_hw->chanspec = ch20mhz_chspec(1);
1234 }
1235
1236 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1237 {
1238         /* delay before first read of ucode state */
1239         udelay(40);
1240
1241         /* wait until ucode is no longer asleep */
1242         SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1243                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1244 }
1245
1246 /* control chip clock to save power, enable dynamic clock or force fast clock */
1247 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1248 {
1249         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1250                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1251                  * on backplane, but mac core will still run on ALP(not HT) when
1252                  * it enters powersave mode, which means the FCA bit may not be
1253                  * set. Should wakeup mac if driver wants it to run on HT.
1254                  */
1255
1256                 if (wlc_hw->clk) {
1257                         if (mode == BCMA_CLKMODE_FAST) {
1258                                 bcma_set32(wlc_hw->d11core,
1259                                            D11REGOFFS(clk_ctl_st),
1260                                            CCS_FORCEHT);
1261
1262                                 udelay(64);
1263
1264                                 SPINWAIT(
1265                                     ((bcma_read32(wlc_hw->d11core,
1266                                       D11REGOFFS(clk_ctl_st)) &
1267                                       CCS_HTAVAIL) == 0),
1268                                       PMU_MAX_TRANSITION_DLY);
1269                                 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1270                                         D11REGOFFS(clk_ctl_st)) &
1271                                         CCS_HTAVAIL));
1272                         } else {
1273                                 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1274                                     (bcma_read32(wlc_hw->d11core,
1275                                         D11REGOFFS(clk_ctl_st)) &
1276                                         (CCS_FORCEHT | CCS_HTAREQ)))
1277                                         SPINWAIT(
1278                                             ((bcma_read32(wlc_hw->d11core,
1279                                               offsetof(struct d11regs,
1280                                                        clk_ctl_st)) &
1281                                               CCS_HTAVAIL) == 0),
1282                                               PMU_MAX_TRANSITION_DLY);
1283                                 bcma_mask32(wlc_hw->d11core,
1284                                         D11REGOFFS(clk_ctl_st),
1285                                         ~CCS_FORCEHT);
1286                         }
1287                 }
1288                 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1289         } else {
1290
1291                 /* old chips w/o PMU, force HT through cc,
1292                  * then use FCA to verify mac is running fast clock
1293                  */
1294
1295                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1296
1297                 /* check fast clock is available (if core is not in reset) */
1298                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1299                         WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1300                                   SISF_FCLKA));
1301
1302                 /*
1303                  * keep the ucode wake bit on if forcefastclk is on since we
1304                  * do not want ucode to put us back to slow clock when it dozes
1305                  * for PM mode. Code below matches the wake override bit with
1306                  * current forcefastclk state. Only setting bit in wake_override
1307                  * instead of waking ucode immediately since old code had this
1308                  * behavior. Older code set wlc->forcefastclk but only had the
1309                  * wake happen if the wakup_ucode work (protected by an up
1310                  * check) was executed just below.
1311                  */
1312                 if (wlc_hw->forcefastclk)
1313                         mboolset(wlc_hw->wake_override,
1314                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1315                 else
1316                         mboolclr(wlc_hw->wake_override,
1317                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1318         }
1319 }
1320
1321 /* set or clear ucode host flag bits
1322  * it has an optimization for no-change write
1323  * it only writes through shared memory when the core has clock;
1324  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1325  *
1326  *
1327  * bands values are: BRCM_BAND_AUTO <--- Current band only
1328  *                   BRCM_BAND_5G   <--- 5G band only
1329  *                   BRCM_BAND_2G   <--- 2G band only
1330  *                   BRCM_BAND_ALL  <--- All bands
1331  */
1332 void
1333 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1334              int bands)
1335 {
1336         u16 save;
1337         u16 addr[MHFMAX] = {
1338                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1339                 M_HOST_FLAGS5
1340         };
1341         struct brcms_hw_band *band;
1342
1343         if ((val & ~mask) || idx >= MHFMAX)
1344                 return; /* error condition */
1345
1346         switch (bands) {
1347                 /* Current band only or all bands,
1348                  * then set the band to current band
1349                  */
1350         case BRCM_BAND_AUTO:
1351         case BRCM_BAND_ALL:
1352                 band = wlc_hw->band;
1353                 break;
1354         case BRCM_BAND_5G:
1355                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1356                 break;
1357         case BRCM_BAND_2G:
1358                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1359                 break;
1360         default:
1361                 band = NULL;    /* error condition */
1362         }
1363
1364         if (band) {
1365                 save = band->mhfs[idx];
1366                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1367
1368                 /* optimization: only write through if changed, and
1369                  * changed band is the current band
1370                  */
1371                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1372                     && (band == wlc_hw->band))
1373                         brcms_b_write_shm(wlc_hw, addr[idx],
1374                                            (u16) band->mhfs[idx]);
1375         }
1376
1377         if (bands == BRCM_BAND_ALL) {
1378                 wlc_hw->bandstate[0]->mhfs[idx] =
1379                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1380                 wlc_hw->bandstate[1]->mhfs[idx] =
1381                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1382         }
1383 }
1384
1385 /* set the maccontrol register to desired reset state and
1386  * initialize the sw cache of the register
1387  */
1388 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1389 {
1390         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1391         wlc_hw->maccontrol = 0;
1392         wlc_hw->suspended_fifos = 0;
1393         wlc_hw->wake_override = 0;
1394         wlc_hw->mute_override = 0;
1395         brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1396 }
1397
1398 /*
1399  * write the software state of maccontrol and
1400  * overrides to the maccontrol register
1401  */
1402 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1403 {
1404         u32 maccontrol = wlc_hw->maccontrol;
1405
1406         /* OR in the wake bit if overridden */
1407         if (wlc_hw->wake_override)
1408                 maccontrol |= MCTL_WAKE;
1409
1410         /* set AP and INFRA bits for mute if needed */
1411         if (wlc_hw->mute_override) {
1412                 maccontrol &= ~(MCTL_AP);
1413                 maccontrol |= MCTL_INFRA;
1414         }
1415
1416         bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1417                      maccontrol);
1418 }
1419
1420 /* set or clear maccontrol bits */
1421 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1422 {
1423         u32 maccontrol;
1424         u32 new_maccontrol;
1425
1426         if (val & ~mask)
1427                 return; /* error condition */
1428         maccontrol = wlc_hw->maccontrol;
1429         new_maccontrol = (maccontrol & ~mask) | val;
1430
1431         /* if the new maccontrol value is the same as the old, nothing to do */
1432         if (new_maccontrol == maccontrol)
1433                 return;
1434
1435         /* something changed, cache the new value */
1436         wlc_hw->maccontrol = new_maccontrol;
1437
1438         /* write the new values with overrides applied */
1439         brcms_c_mctrl_write(wlc_hw);
1440 }
1441
1442 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1443                                  u32 override_bit)
1444 {
1445         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1446                 mboolset(wlc_hw->wake_override, override_bit);
1447                 return;
1448         }
1449
1450         mboolset(wlc_hw->wake_override, override_bit);
1451
1452         brcms_c_mctrl_write(wlc_hw);
1453         brcms_b_wait_for_wake(wlc_hw);
1454 }
1455
1456 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1457                                    u32 override_bit)
1458 {
1459         mboolclr(wlc_hw->wake_override, override_bit);
1460
1461         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1462                 return;
1463
1464         brcms_c_mctrl_write(wlc_hw);
1465 }
1466
1467 /* When driver needs ucode to stop beaconing, it has to make sure that
1468  * MCTL_AP is clear and MCTL_INFRA is set
1469  * Mode           MCTL_AP        MCTL_INFRA
1470  * AP                1              1
1471  * STA               0              1 <--- This will ensure no beacons
1472  * IBSS              0              0
1473  */
1474 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1475 {
1476         wlc_hw->mute_override = 1;
1477
1478         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1479          * override, then there is no change to write
1480          */
1481         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1482                 return;
1483
1484         brcms_c_mctrl_write(wlc_hw);
1485 }
1486
1487 /* Clear the override on AP and INFRA bits */
1488 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1489 {
1490         if (wlc_hw->mute_override == 0)
1491                 return;
1492
1493         wlc_hw->mute_override = 0;
1494
1495         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1496          * override, then there is no change to write
1497          */
1498         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1499                 return;
1500
1501         brcms_c_mctrl_write(wlc_hw);
1502 }
1503
1504 /*
1505  * Write a MAC address to the given match reg offset in the RXE match engine.
1506  */
1507 static void
1508 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1509                        const u8 *addr)
1510 {
1511         struct bcma_device *core = wlc_hw->d11core;
1512         u16 mac_l;
1513         u16 mac_m;
1514         u16 mac_h;
1515
1516         brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1517
1518         mac_l = addr[0] | (addr[1] << 8);
1519         mac_m = addr[2] | (addr[3] << 8);
1520         mac_h = addr[4] | (addr[5] << 8);
1521
1522         /* enter the MAC addr into the RXE match registers */
1523         bcma_write16(core, D11REGOFFS(rcm_ctl),
1524                      RCM_INC_DATA | match_reg_offset);
1525         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1526         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1527         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1528 }
1529
1530 void
1531 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1532                             void *buf)
1533 {
1534         struct bcma_device *core = wlc_hw->d11core;
1535         u32 word;
1536         __le32 word_le;
1537         __be32 word_be;
1538         bool be_bit;
1539         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1540
1541         bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1542
1543         /* if MCTL_BIGEND bit set in mac control register,
1544          * the chip swaps data in fifo, as well as data in
1545          * template ram
1546          */
1547         be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1548
1549         while (len > 0) {
1550                 memcpy(&word, buf, sizeof(u32));
1551
1552                 if (be_bit) {
1553                         word_be = cpu_to_be32(word);
1554                         word = *(u32 *)&word_be;
1555                 } else {
1556                         word_le = cpu_to_le32(word);
1557                         word = *(u32 *)&word_le;
1558                 }
1559
1560                 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1561
1562                 buf = (u8 *) buf + sizeof(u32);
1563                 len -= sizeof(u32);
1564         }
1565 }
1566
1567 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1568 {
1569         wlc_hw->band->CWmin = newmin;
1570
1571         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1572                      OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1573         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1574         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1575 }
1576
1577 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1578 {
1579         wlc_hw->band->CWmax = newmax;
1580
1581         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1582                      OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1583         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1584         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1585 }
1586
1587 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1588 {
1589         bool fastclk;
1590
1591         /* request FAST clock if not on */
1592         fastclk = wlc_hw->forcefastclk;
1593         if (!fastclk)
1594                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1595
1596         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1597
1598         brcms_b_phy_reset(wlc_hw);
1599         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1600
1601         /* restore the clk */
1602         if (!fastclk)
1603                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1604 }
1605
1606 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1607 {
1608         u16 v;
1609         struct brcms_c_info *wlc = wlc_hw->wlc;
1610         /* update SYNTHPU_DLY */
1611
1612         if (BRCMS_ISLCNPHY(wlc->band))
1613                 v = SYNTHPU_DLY_LPPHY_US;
1614         else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1615                 v = SYNTHPU_DLY_NPHY_US;
1616         else
1617                 v = SYNTHPU_DLY_BPHY_US;
1618
1619         brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1620 }
1621
1622 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1623 {
1624         u16 phyctl;
1625         u16 phytxant = wlc_hw->bmac_phytxant;
1626         u16 mask = PHY_TXC_ANT_MASK;
1627
1628         /* set the Probe Response frame phy control word */
1629         phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1630         phyctl = (phyctl & ~mask) | phytxant;
1631         brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1632
1633         /* set the Response (ACK/CTS) frame phy control word */
1634         phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1635         phyctl = (phyctl & ~mask) | phytxant;
1636         brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1637 }
1638
1639 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1640                                          u8 rate)
1641 {
1642         uint i;
1643         u8 plcp_rate = 0;
1644         struct plcp_signal_rate_lookup {
1645                 u8 rate;
1646                 u8 signal_rate;
1647         };
1648         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1649         const struct plcp_signal_rate_lookup rate_lookup[] = {
1650                 {BRCM_RATE_6M, 0xB},
1651                 {BRCM_RATE_9M, 0xF},
1652                 {BRCM_RATE_12M, 0xA},
1653                 {BRCM_RATE_18M, 0xE},
1654                 {BRCM_RATE_24M, 0x9},
1655                 {BRCM_RATE_36M, 0xD},
1656                 {BRCM_RATE_48M, 0x8},
1657                 {BRCM_RATE_54M, 0xC}
1658         };
1659
1660         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1661                 if (rate == rate_lookup[i].rate) {
1662                         plcp_rate = rate_lookup[i].signal_rate;
1663                         break;
1664                 }
1665         }
1666
1667         /* Find the SHM pointer to the rate table entry by looking in the
1668          * Direct-map Table
1669          */
1670         return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1671 }
1672
1673 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1674 {
1675         u8 rate;
1676         u8 rates[8] = {
1677                 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1678                 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1679         };
1680         u16 entry_ptr;
1681         u16 pctl1;
1682         uint i;
1683
1684         if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1685                 return;
1686
1687         /* walk the phy rate table and update the entries */
1688         for (i = 0; i < ARRAY_SIZE(rates); i++) {
1689                 rate = rates[i];
1690
1691                 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1692
1693                 /* read the SHM Rate Table entry OFDM PCTL1 values */
1694                 pctl1 =
1695                     brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1696
1697                 /* modify the value */
1698                 pctl1 &= ~PHY_TXC1_MODE_MASK;
1699                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1700
1701                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1702                 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1703                                    pctl1);
1704         }
1705 }
1706
1707 /* band-specific init */
1708 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1709 {
1710         struct brcms_hardware *wlc_hw = wlc->hw;
1711
1712         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1713                            wlc_hw->band->bandunit);
1714
1715         brcms_c_ucode_bsinit(wlc_hw);
1716
1717         wlc_phy_init(wlc_hw->band->pi, chanspec);
1718
1719         brcms_c_ucode_txant_set(wlc_hw);
1720
1721         /*
1722          * cwmin is band-specific, update hardware
1723          * with value for current band
1724          */
1725         brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1726         brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1727
1728         brcms_b_update_slot_timing(wlc_hw,
1729                                    wlc_hw->band->bandtype == BRCM_BAND_5G ?
1730                                    true : wlc_hw->shortslot);
1731
1732         /* write phytype and phyvers */
1733         brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1734         brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1735
1736         /*
1737          * initialize the txphyctl1 rate table since
1738          * shmem is shared between bands
1739          */
1740         brcms_upd_ofdm_pctl1_table(wlc_hw);
1741
1742         brcms_b_upd_synthpu(wlc_hw);
1743 }
1744
1745 /* Perform a soft reset of the PHY PLL */
1746 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1747 {
1748         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1749                   ~0, 0);
1750         udelay(1);
1751         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1752                   0x4, 0);
1753         udelay(1);
1754         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1755                   0x4, 4);
1756         udelay(1);
1757         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1758                   0x4, 0);
1759         udelay(1);
1760 }
1761
1762 /* light way to turn on phy clock without reset for NPHY only
1763  *  refer to brcms_b_core_phy_clk for full version
1764  */
1765 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1766 {
1767         /* support(necessary for NPHY and HYPHY) only */
1768         if (!BRCMS_ISNPHY(wlc_hw->band))
1769                 return;
1770
1771         if (ON == clk)
1772                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1773         else
1774                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1775
1776 }
1777
1778 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1779 {
1780         if (ON == clk)
1781                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1782         else
1783                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1784 }
1785
1786 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1787 {
1788         struct brcms_phy_pub *pih = wlc_hw->band->pi;
1789         u32 phy_bw_clkbits;
1790         bool phy_in_reset = false;
1791
1792         brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1793
1794         if (pih == NULL)
1795                 return;
1796
1797         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1798
1799         /* Specific reset sequence required for NPHY rev 3 and 4 */
1800         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1801             NREV_LE(wlc_hw->band->phyrev, 4)) {
1802                 /* Set the PHY bandwidth */
1803                 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1804
1805                 udelay(1);
1806
1807                 /* Perform a soft reset of the PHY PLL */
1808                 brcms_b_core_phypll_reset(wlc_hw);
1809
1810                 /* reset the PHY */
1811                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1812                                    (SICF_PRST | SICF_PCLKE));
1813                 phy_in_reset = true;
1814         } else {
1815                 brcms_b_core_ioctl(wlc_hw,
1816                                    (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1817                                    (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1818         }
1819
1820         udelay(2);
1821         brcms_b_core_phy_clk(wlc_hw, ON);
1822
1823         if (pih)
1824                 wlc_phy_anacore(pih, ON);
1825 }
1826
1827 /* switch to and initialize new band */
1828 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1829                             u16 chanspec) {
1830         struct brcms_c_info *wlc = wlc_hw->wlc;
1831         u32 macintmask;
1832
1833         /* Enable the d11 core before accessing it */
1834         if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1835                 bcma_core_enable(wlc_hw->d11core, 0);
1836                 brcms_c_mctrl_reset(wlc_hw);
1837         }
1838
1839         macintmask = brcms_c_setband_inact(wlc, bandunit);
1840
1841         if (!wlc_hw->up)
1842                 return;
1843
1844         brcms_b_core_phy_clk(wlc_hw, ON);
1845
1846         /* band-specific initializations */
1847         brcms_b_bsinit(wlc, chanspec);
1848
1849         /*
1850          * If there are any pending software interrupt bits,
1851          * then replace these with a harmless nonzero value
1852          * so brcms_c_dpc() will re-enable interrupts when done.
1853          */
1854         if (wlc->macintstatus)
1855                 wlc->macintstatus = MI_DMAINT;
1856
1857         /* restore macintmask */
1858         brcms_intrsrestore(wlc->wl, macintmask);
1859
1860         /* ucode should still be suspended.. */
1861         WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1862                  MCTL_EN_MAC) != 0);
1863 }
1864
1865 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1866 {
1867
1868         /* reject unsupported corerev */
1869         if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1870                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1871                           wlc_hw->corerev);
1872                 return false;
1873         }
1874
1875         return true;
1876 }
1877
1878 /* Validate some board info parameters */
1879 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1880 {
1881         uint boardrev = wlc_hw->boardrev;
1882
1883         /* 4 bits each for board type, major, minor, and tiny version */
1884         uint brt = (boardrev & 0xf000) >> 12;
1885         uint b0 = (boardrev & 0xf00) >> 8;
1886         uint b1 = (boardrev & 0xf0) >> 4;
1887         uint b2 = boardrev & 0xf;
1888
1889         /* voards from other vendors are always considered valid */
1890         if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1891                 return true;
1892
1893         /* do some boardrev sanity checks when boardvendor is Broadcom */
1894         if (boardrev == 0)
1895                 return false;
1896
1897         if (boardrev <= 0xff)
1898                 return true;
1899
1900         if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1901                 || (b2 > 9))
1902                 return false;
1903
1904         return true;
1905 }
1906
1907 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1908 {
1909         struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1910
1911         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1912         if (!is_zero_ether_addr(sprom->il0mac)) {
1913                 memcpy(etheraddr, sprom->il0mac, 6);
1914                 return;
1915         }
1916
1917         if (wlc_hw->_nbands > 1)
1918                 memcpy(etheraddr, sprom->et1mac, 6);
1919         else
1920                 memcpy(etheraddr, sprom->il0mac, 6);
1921 }
1922
1923 /* power both the pll and external oscillator on/off */
1924 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1925 {
1926         brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1927
1928         /*
1929          * dont power down if plldown is false or
1930          * we must poll hw radio disable
1931          */
1932         if (!want && wlc_hw->pllreq)
1933                 return;
1934
1935         wlc_hw->sbclk = want;
1936         if (!wlc_hw->sbclk) {
1937                 wlc_hw->clk = false;
1938                 if (wlc_hw->band && wlc_hw->band->pi)
1939                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1940         }
1941 }
1942
1943 /*
1944  * Return true if radio is disabled, otherwise false.
1945  * hw radio disable signal is an external pin, users activate it asynchronously
1946  * this function could be called when driver is down and w/o clock
1947  * it operates on different registers depending on corerev and boardflag.
1948  */
1949 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1950 {
1951         bool v, clk, xtal;
1952         u32 flags = 0;
1953
1954         xtal = wlc_hw->sbclk;
1955         if (!xtal)
1956                 brcms_b_xtal(wlc_hw, ON);
1957
1958         /* may need to take core out of reset first */
1959         clk = wlc_hw->clk;
1960         if (!clk) {
1961                 /*
1962                  * mac no longer enables phyclk automatically when driver
1963                  * accesses phyreg throughput mac. This can be skipped since
1964                  * only mac reg is accessed below
1965                  */
1966                 if (D11REV_GE(wlc_hw->corerev, 18))
1967                         flags |= SICF_PCLKE;
1968
1969                 /*
1970                  * TODO: test suspend/resume
1971                  *
1972                  * AI chip doesn't restore bar0win2 on
1973                  * hibernation/resume, need sw fixup
1974                  */
1975
1976                 bcma_core_enable(wlc_hw->d11core, flags);
1977                 brcms_c_mctrl_reset(wlc_hw);
1978         }
1979
1980         v = ((bcma_read32(wlc_hw->d11core,
1981                           D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1982
1983         /* put core back into reset */
1984         if (!clk)
1985                 bcma_core_disable(wlc_hw->d11core, 0);
1986
1987         if (!xtal)
1988                 brcms_b_xtal(wlc_hw, OFF);
1989
1990         return v;
1991 }
1992
1993 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1994 {
1995         struct dma_pub *di = wlc_hw->di[fifo];
1996         return dma_rxreset(di);
1997 }
1998
1999 /* d11 core reset
2000  *   ensure fask clock during reset
2001  *   reset dma
2002  *   reset d11(out of reset)
2003  *   reset phy(out of reset)
2004  *   clear software macintstatus for fresh new start
2005  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2006  */
2007 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2008 {
2009         uint i;
2010         bool fastclk;
2011
2012         if (flags == BRCMS_USE_COREFLAGS)
2013                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2014
2015         brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2016
2017         /* request FAST clock if not on  */
2018         fastclk = wlc_hw->forcefastclk;
2019         if (!fastclk)
2020                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2021
2022         /* reset the dma engines except first time thru */
2023         if (bcma_core_is_enabled(wlc_hw->d11core)) {
2024                 for (i = 0; i < NFIFO; i++)
2025                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2026                                 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2027                                           "dma_txreset[%d]: cannot stop dma\n",
2028                                            wlc_hw->unit, __func__, i);
2029
2030                 if ((wlc_hw->di[RX_FIFO])
2031                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2032                         brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2033                                   "[%d]: cannot stop dma\n",
2034                                   wlc_hw->unit, __func__, RX_FIFO);
2035         }
2036         /* if noreset, just stop the psm and return */
2037         if (wlc_hw->noreset) {
2038                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2039                 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2040                 return;
2041         }
2042
2043         /*
2044          * mac no longer enables phyclk automatically when driver accesses
2045          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2046          * band->pi is invalid. need to enable PHY CLK
2047          */
2048         if (D11REV_GE(wlc_hw->corerev, 18))
2049                 flags |= SICF_PCLKE;
2050
2051         /*
2052          * reset the core
2053          * In chips with PMU, the fastclk request goes through d11 core
2054          * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2055          *
2056          * This adds some delay and we can optimize it by also requesting
2057          * fastclk through chipcommon during this period if necessary. But
2058          * that has to work coordinate with other driver like mips/arm since
2059          * they may touch chipcommon as well.
2060          */
2061         wlc_hw->clk = false;
2062         bcma_core_enable(wlc_hw->d11core, flags);
2063         wlc_hw->clk = true;
2064         if (wlc_hw->band && wlc_hw->band->pi)
2065                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2066
2067         brcms_c_mctrl_reset(wlc_hw);
2068
2069         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2070                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2071
2072         brcms_b_phy_reset(wlc_hw);
2073
2074         /* turn on PHY_PLL */
2075         brcms_b_core_phypll_ctl(wlc_hw, true);
2076
2077         /* clear sw intstatus */
2078         wlc_hw->wlc->macintstatus = 0;
2079
2080         /* restore the clk setting */
2081         if (!fastclk)
2082                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2083 }
2084
2085 /* txfifo sizes needs to be modified(increased) since the newer cores
2086  * have more memory.
2087  */
2088 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2089 {
2090         struct bcma_device *core = wlc_hw->d11core;
2091         u16 fifo_nu;
2092         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2093         u16 txfifo_def, txfifo_def1;
2094         u16 txfifo_cmd;
2095
2096         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2097         txfifo_startblk = TXFIFO_START_BLK;
2098
2099         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2100         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2101
2102                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2103                 txfifo_def = (txfifo_startblk & 0xff) |
2104                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2105                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2106                     ((((txfifo_endblk -
2107                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2108                 txfifo_cmd =
2109                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2110
2111                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2112                 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2113                 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2114
2115                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2116
2117                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2118         }
2119         /*
2120          * need to propagate to shm location to be in sync since ucode/hw won't
2121          * do this
2122          */
2123         brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2124                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2125         brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2126                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2127         brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2128                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2129                             xmtfifo_sz[TX_AC_BK_FIFO]));
2130         brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2131                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2132                             xmtfifo_sz[TX_BCMC_FIFO]));
2133 }
2134
2135 /* This function is used for changing the tsf frac register
2136  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2137  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2138  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2139  * HTPHY Formula is 2^26/freq(MHz) e.g.
2140  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2141  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2142  * For spuron: 123MHz -> 2^26/123    = 545600.5
2143  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2144  * For spur off: 120MHz -> 2^26/120    = 559240.5
2145  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2146  */
2147
2148 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2149 {
2150         struct bcma_device *core = wlc_hw->d11core;
2151
2152         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2153             (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2154                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2155                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2156                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2157                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2158                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2159                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2160                 } else {        /* 120Mhz */
2161                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2162                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2163                 }
2164         } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2165                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2166                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2167                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2168                 } else {        /* 80Mhz */
2169                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2170                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2171                 }
2172         }
2173 }
2174
2175 /* Initialize GPIOs that are controlled by D11 core */
2176 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2177 {
2178         struct brcms_hardware *wlc_hw = wlc->hw;
2179         u32 gc, gm;
2180
2181         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2182         brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2183
2184         /*
2185          * Common GPIO setup:
2186          *      G0 = LED 0 = WLAN Activity
2187          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2188          *      G2 = LED 2 = WLAN 5 GHz Radio State
2189          *      G4 = radio disable input (HI enabled, LO disabled)
2190          */
2191
2192         gc = gm = 0;
2193
2194         /* Allocate GPIOs for mimo antenna diversity feature */
2195         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2196                 /* Enable antenna diversity, use 2x3 mode */
2197                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2198                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2199                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2200                              MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2201
2202                 /* init superswitch control */
2203                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2204
2205         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2206                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2207                 /*
2208                  * The board itself is powered by these GPIOs
2209                  * (when not sending pattern) so set them high
2210                  */
2211                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2212                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2213                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2214                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2215
2216                 /* Enable antenna diversity, use 2x4 mode */
2217                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2218                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2219                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2220                              BRCM_BAND_ALL);
2221
2222                 /* Configure the desired clock to be 4Mhz */
2223                 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2224                                    ANTSEL_CLKDIV_4MHZ);
2225         }
2226
2227         /*
2228          * gpio 9 controls the PA. ucode is responsible
2229          * for wiggling out and oe
2230          */
2231         if (wlc_hw->boardflags & BFL_PACTRL)
2232                 gm |= gc |= BOARD_GPIO_PACTRL;
2233
2234         /* apply to gpiocontrol register */
2235         bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2236 }
2237
2238 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2239                               const __le32 ucode[], const size_t nbytes)
2240 {
2241         struct bcma_device *core = wlc_hw->d11core;
2242         uint i;
2243         uint count;
2244
2245         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2246
2247         count = (nbytes / sizeof(u32));
2248
2249         bcma_write32(core, D11REGOFFS(objaddr),
2250                      OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2251         (void)bcma_read32(core, D11REGOFFS(objaddr));
2252         for (i = 0; i < count; i++)
2253                 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2254
2255 }
2256
2257 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2258 {
2259         struct brcms_c_info *wlc;
2260         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2261
2262         wlc = wlc_hw->wlc;
2263
2264         if (wlc_hw->ucode_loaded)
2265                 return;
2266
2267         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2268                 if (BRCMS_ISNPHY(wlc_hw->band)) {
2269                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2270                                           ucode->bcm43xx_16_mimosz);
2271                         wlc_hw->ucode_loaded = true;
2272                 } else
2273                         brcms_err(wlc_hw->d11core,
2274                                   "%s: wl%d: unsupported phy in corerev %d\n",
2275                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2276         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2277                 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2278                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2279                                           ucode->bcm43xx_24_lcnsz);
2280                         wlc_hw->ucode_loaded = true;
2281                 } else {
2282                         brcms_err(wlc_hw->d11core,
2283                                   "%s: wl%d: unsupported phy in corerev %d\n",
2284                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2285                 }
2286         }
2287 }
2288
2289 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2290 {
2291         /* update sw state */
2292         wlc_hw->bmac_phytxant = phytxant;
2293
2294         /* push to ucode if up */
2295         if (!wlc_hw->up)
2296                 return;
2297         brcms_c_ucode_txant_set(wlc_hw);
2298
2299 }
2300
2301 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2302 {
2303         return (u16) wlc_hw->wlc->stf->txant;
2304 }
2305
2306 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2307 {
2308         wlc_hw->antsel_type = antsel_type;
2309
2310         /* Update the antsel type for phy module to use */
2311         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2312 }
2313
2314 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2315 {
2316         bool fatal = false;
2317         uint unit;
2318         uint intstatus, idx;
2319         struct bcma_device *core = wlc_hw->d11core;
2320
2321         unit = wlc_hw->unit;
2322
2323         for (idx = 0; idx < NFIFO; idx++) {
2324                 /* read intstatus register and ignore any non-error bits */
2325                 intstatus =
2326                         bcma_read32(core,
2327                                     D11REGOFFS(intctrlregs[idx].intstatus)) &
2328                         I_ERRORS;
2329                 if (!intstatus)
2330                         continue;
2331
2332                 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2333                               unit, idx, intstatus);
2334
2335                 if (intstatus & I_RO) {
2336                         brcms_err(core, "wl%d: fifo %d: receive fifo "
2337                                   "overflow\n", unit, idx);
2338                         fatal = true;
2339                 }
2340
2341                 if (intstatus & I_PC) {
2342                         brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2343                                   unit, idx);
2344                         fatal = true;
2345                 }
2346
2347                 if (intstatus & I_PD) {
2348                         brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2349                                   idx);
2350                         fatal = true;
2351                 }
2352
2353                 if (intstatus & I_DE) {
2354                         brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2355                                   "error\n", unit, idx);
2356                         fatal = true;
2357                 }
2358
2359                 if (intstatus & I_RU)
2360                         brcms_err(core, "wl%d: fifo %d: receive descriptor "
2361                                   "underflow\n", idx, unit);
2362
2363                 if (intstatus & I_XU) {
2364                         brcms_err(core, "wl%d: fifo %d: transmit fifo "
2365                                   "underflow\n", idx, unit);
2366                         fatal = true;
2367                 }
2368
2369                 if (fatal) {
2370                         brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2371                         break;
2372                 } else
2373                         bcma_write32(core,
2374                                      D11REGOFFS(intctrlregs[idx].intstatus),
2375                                      intstatus);
2376         }
2377 }
2378
2379 void brcms_c_intrson(struct brcms_c_info *wlc)
2380 {
2381         struct brcms_hardware *wlc_hw = wlc->hw;
2382         wlc->macintmask = wlc->defmacintmask;
2383         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2384 }
2385
2386 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2387 {
2388         struct brcms_hardware *wlc_hw = wlc->hw;
2389         u32 macintmask;
2390
2391         if (!wlc_hw->clk)
2392                 return 0;
2393
2394         macintmask = wlc->macintmask;   /* isr can still happen */
2395
2396         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2397         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2398         udelay(1);              /* ensure int line is no longer driven */
2399         wlc->macintmask = 0;
2400
2401         /* return previous macintmask; resolve race between us and our isr */
2402         return wlc->macintstatus ? 0 : macintmask;
2403 }
2404
2405 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2406 {
2407         struct brcms_hardware *wlc_hw = wlc->hw;
2408         if (!wlc_hw->clk)
2409                 return;
2410
2411         wlc->macintmask = macintmask;
2412         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2413 }
2414
2415 /* assumes that the d11 MAC is enabled */
2416 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2417                                     uint tx_fifo)
2418 {
2419         u8 fifo = 1 << tx_fifo;
2420
2421         /* Two clients of this code, 11h Quiet period and scanning. */
2422
2423         /* only suspend if not already suspended */
2424         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2425                 return;
2426
2427         /* force the core awake only if not already */
2428         if (wlc_hw->suspended_fifos == 0)
2429                 brcms_c_ucode_wake_override_set(wlc_hw,
2430                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2431
2432         wlc_hw->suspended_fifos |= fifo;
2433
2434         if (wlc_hw->di[tx_fifo]) {
2435                 /*
2436                  * Suspending AMPDU transmissions in the middle can cause
2437                  * underflow which may result in mismatch between ucode and
2438                  * driver so suspend the mac before suspending the FIFO
2439                  */
2440                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2441                         brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2442
2443                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2444
2445                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2446                         brcms_c_enable_mac(wlc_hw->wlc);
2447         }
2448 }
2449
2450 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2451                                    uint tx_fifo)
2452 {
2453         /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2454          * but need to be done here for PIO otherwise the watchdog will catch
2455          * the inconsistency and fire
2456          */
2457         /* Two clients of this code, 11h Quiet period and scanning. */
2458         if (wlc_hw->di[tx_fifo])
2459                 dma_txresume(wlc_hw->di[tx_fifo]);
2460
2461         /* allow core to sleep again */
2462         if (wlc_hw->suspended_fifos == 0)
2463                 return;
2464         else {
2465                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2466                 if (wlc_hw->suspended_fifos == 0)
2467                         brcms_c_ucode_wake_override_clear(wlc_hw,
2468                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2469         }
2470 }
2471
2472 /* precondition: requires the mac core to be enabled */
2473 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2474 {
2475         static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2476
2477         if (mute_tx) {
2478                 /* suspend tx fifos */
2479                 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2480                 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2481                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2482                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2483
2484                 /* zero the address match register so we do not send ACKs */
2485                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2486                                        null_ether_addr);
2487         } else {
2488                 /* resume tx fifos */
2489                 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2490                 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2491                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2492                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2493
2494                 /* Restore address */
2495                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2496                                        wlc_hw->etheraddr);
2497         }
2498
2499         wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2500
2501         if (mute_tx)
2502                 brcms_c_ucode_mute_override_set(wlc_hw);
2503         else
2504                 brcms_c_ucode_mute_override_clear(wlc_hw);
2505 }
2506
2507 void
2508 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2509 {
2510         brcms_b_mute(wlc->hw, mute_tx);
2511 }
2512
2513 /*
2514  * Read and clear macintmask and macintstatus and intstatus registers.
2515  * This routine should be called with interrupts off
2516  * Return:
2517  *   -1 if brcms_deviceremoved(wlc) evaluates to true;
2518  *   0 if the interrupt is not for us, or we are in some special cases;
2519  *   device interrupt status bits otherwise.
2520  */
2521 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2522 {
2523         struct brcms_hardware *wlc_hw = wlc->hw;
2524         struct bcma_device *core = wlc_hw->d11core;
2525         u32 macintstatus, mask;
2526
2527         /* macintstatus includes a DMA interrupt summary bit */
2528         macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2529         mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2530
2531         trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2532
2533         /* detect cardbus removed, in power down(suspend) and in reset */
2534         if (brcms_deviceremoved(wlc))
2535                 return -1;
2536
2537         /* brcms_deviceremoved() succeeds even when the core is still resetting,
2538          * handle that case here.
2539          */
2540         if (macintstatus == 0xffffffff)
2541                 return 0;
2542
2543         /* defer unsolicited interrupts */
2544         macintstatus &= mask;
2545
2546         /* if not for us */
2547         if (macintstatus == 0)
2548                 return 0;
2549
2550         /* turn off the interrupts */
2551         bcma_write32(core, D11REGOFFS(macintmask), 0);
2552         (void)bcma_read32(core, D11REGOFFS(macintmask));
2553         wlc->macintmask = 0;
2554
2555         /* clear device interrupts */
2556         bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2557
2558         /* MI_DMAINT is indication of non-zero intstatus */
2559         if (macintstatus & MI_DMAINT)
2560                 /*
2561                  * only fifo interrupt enabled is I_RI in
2562                  * RX_FIFO. If MI_DMAINT is set, assume it
2563                  * is set and clear the interrupt.
2564                  */
2565                 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2566                              DEF_RXINTMASK);
2567
2568         return macintstatus;
2569 }
2570
2571 /* Update wlc->macintstatus and wlc->intstatus[]. */
2572 /* Return true if they are updated successfully. false otherwise */
2573 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2574 {
2575         u32 macintstatus;
2576
2577         /* read and clear macintstatus and intstatus registers */
2578         macintstatus = wlc_intstatus(wlc, false);
2579
2580         /* device is removed */
2581         if (macintstatus == 0xffffffff)
2582                 return false;
2583
2584         /* update interrupt status in software */
2585         wlc->macintstatus |= macintstatus;
2586
2587         return true;
2588 }
2589
2590 /*
2591  * First-level interrupt processing.
2592  * Return true if this was our interrupt
2593  * and if further brcms_c_dpc() processing is required,
2594  * false otherwise.
2595  */
2596 bool brcms_c_isr(struct brcms_c_info *wlc)
2597 {
2598         struct brcms_hardware *wlc_hw = wlc->hw;
2599         u32 macintstatus;
2600
2601         if (!wlc_hw->up || !wlc->macintmask)
2602                 return false;
2603
2604         /* read and clear macintstatus and intstatus registers */
2605         macintstatus = wlc_intstatus(wlc, true);
2606
2607         if (macintstatus == 0xffffffff) {
2608                 brcms_err(wlc_hw->d11core,
2609                           "DEVICEREMOVED detected in the ISR code path\n");
2610                 return false;
2611         }
2612
2613         /* it is not for us */
2614         if (macintstatus == 0)
2615                 return false;
2616
2617         /* save interrupt status bits */
2618         wlc->macintstatus = macintstatus;
2619
2620         return true;
2621
2622 }
2623
2624 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2625 {
2626         struct brcms_hardware *wlc_hw = wlc->hw;
2627         struct bcma_device *core = wlc_hw->d11core;
2628         u32 mc, mi;
2629
2630         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2631                            wlc_hw->band->bandunit);
2632
2633         /*
2634          * Track overlapping suspend requests
2635          */
2636         wlc_hw->mac_suspend_depth++;
2637         if (wlc_hw->mac_suspend_depth > 1)
2638                 return;
2639
2640         /* force the core awake */
2641         brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2642
2643         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2644
2645         if (mc == 0xffffffff) {
2646                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2647                           __func__);
2648                 brcms_down(wlc->wl);
2649                 return;
2650         }
2651         WARN_ON(mc & MCTL_PSM_JMP_0);
2652         WARN_ON(!(mc & MCTL_PSM_RUN));
2653         WARN_ON(!(mc & MCTL_EN_MAC));
2654
2655         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2656         if (mi == 0xffffffff) {
2657                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2658                           __func__);
2659                 brcms_down(wlc->wl);
2660                 return;
2661         }
2662         WARN_ON(mi & MI_MACSSPNDD);
2663
2664         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2665
2666         SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2667                  BRCMS_MAX_MAC_SUSPEND);
2668
2669         if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2670                 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2671                           " and MI_MACSSPNDD is still not on.\n",
2672                           wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2673                 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2674                           "psm_brc 0x%04x\n", wlc_hw->unit,
2675                           bcma_read32(core, D11REGOFFS(psmdebug)),
2676                           bcma_read32(core, D11REGOFFS(phydebug)),
2677                           bcma_read16(core, D11REGOFFS(psm_brc)));
2678         }
2679
2680         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2681         if (mc == 0xffffffff) {
2682                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2683                           __func__);
2684                 brcms_down(wlc->wl);
2685                 return;
2686         }
2687         WARN_ON(mc & MCTL_PSM_JMP_0);
2688         WARN_ON(!(mc & MCTL_PSM_RUN));
2689         WARN_ON(mc & MCTL_EN_MAC);
2690 }
2691
2692 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2693 {
2694         struct brcms_hardware *wlc_hw = wlc->hw;
2695         struct bcma_device *core = wlc_hw->d11core;
2696         u32 mc, mi;
2697
2698         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2699                            wlc->band->bandunit);
2700
2701         /*
2702          * Track overlapping suspend requests
2703          */
2704         wlc_hw->mac_suspend_depth--;
2705         if (wlc_hw->mac_suspend_depth > 0)
2706                 return;
2707
2708         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2709         WARN_ON(mc & MCTL_PSM_JMP_0);
2710         WARN_ON(mc & MCTL_EN_MAC);
2711         WARN_ON(!(mc & MCTL_PSM_RUN));
2712
2713         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2714         bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2715
2716         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2717         WARN_ON(mc & MCTL_PSM_JMP_0);
2718         WARN_ON(!(mc & MCTL_EN_MAC));
2719         WARN_ON(!(mc & MCTL_PSM_RUN));
2720
2721         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2722         WARN_ON(mi & MI_MACSSPNDD);
2723
2724         brcms_c_ucode_wake_override_clear(wlc_hw,
2725                                           BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2726 }
2727
2728 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2729 {
2730         wlc_hw->hw_stf_ss_opmode = stf_mode;
2731
2732         if (wlc_hw->clk)
2733                 brcms_upd_ofdm_pctl1_table(wlc_hw);
2734 }
2735
2736 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2737 {
2738         struct bcma_device *core = wlc_hw->d11core;
2739         u32 w, val;
2740         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2741
2742         /* Validate dchip register access */
2743
2744         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2745         (void)bcma_read32(core, D11REGOFFS(objaddr));
2746         w = bcma_read32(core, D11REGOFFS(objdata));
2747
2748         /* Can we write and read back a 32bit register? */
2749         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2750         (void)bcma_read32(core, D11REGOFFS(objaddr));
2751         bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2752
2753         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2754         (void)bcma_read32(core, D11REGOFFS(objaddr));
2755         val = bcma_read32(core, D11REGOFFS(objdata));
2756         if (val != (u32) 0xaa5555aa) {
2757                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2758                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
2759                 return false;
2760         }
2761
2762         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2763         (void)bcma_read32(core, D11REGOFFS(objaddr));
2764         bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2765
2766         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2767         (void)bcma_read32(core, D11REGOFFS(objaddr));
2768         val = bcma_read32(core, D11REGOFFS(objdata));
2769         if (val != (u32) 0x55aaaa55) {
2770                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2771                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
2772                 return false;
2773         }
2774
2775         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2776         (void)bcma_read32(core, D11REGOFFS(objaddr));
2777         bcma_write32(core, D11REGOFFS(objdata), w);
2778
2779         /* clear CFPStart */
2780         bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2781
2782         w = bcma_read32(core, D11REGOFFS(maccontrol));
2783         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2784             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2785                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2786                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2787                           (MCTL_IHR_EN | MCTL_WAKE),
2788                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2789                 return false;
2790         }
2791
2792         return true;
2793 }
2794
2795 #define PHYPLL_WAIT_US  100000
2796
2797 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2798 {
2799         struct bcma_device *core = wlc_hw->d11core;
2800         u32 tmp;
2801
2802         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2803
2804         tmp = 0;
2805
2806         if (on) {
2807                 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2808                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2809                                    CCS_ERSRC_REQ_HT |
2810                                    CCS_ERSRC_REQ_D11PLL |
2811                                    CCS_ERSRC_REQ_PHYPLL);
2812                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2813                                   CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2814                                  PHYPLL_WAIT_US);
2815
2816                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2817                         if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2818                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2819                                           __func__);
2820                 } else {
2821                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2822                                    tmp | CCS_ERSRC_REQ_D11PLL |
2823                                    CCS_ERSRC_REQ_PHYPLL);
2824                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2825                                   (CCS_ERSRC_AVAIL_D11PLL |
2826                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
2827                                  (CCS_ERSRC_AVAIL_D11PLL |
2828                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2829
2830                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2831                         if ((tmp &
2832                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2833                             !=
2834                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2835                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2836                                           __func__);
2837                 }
2838         } else {
2839                 /*
2840                  * Since the PLL may be shared, other cores can still
2841                  * be requesting it; so we'll deassert the request but
2842                  * not wait for status to comply.
2843                  */
2844                 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2845                             ~CCS_ERSRC_REQ_PHYPLL);
2846                 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2847         }
2848 }
2849
2850 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2851 {
2852         bool dev_gone;
2853
2854         brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2855
2856         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2857
2858         if (dev_gone)
2859                 return;
2860
2861         if (wlc_hw->noreset)
2862                 return;
2863
2864         /* radio off */
2865         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2866
2867         /* turn off analog core */
2868         wlc_phy_anacore(wlc_hw->band->pi, OFF);
2869
2870         /* turn off PHYPLL to save power */
2871         brcms_b_core_phypll_ctl(wlc_hw, false);
2872
2873         wlc_hw->clk = false;
2874         bcma_core_disable(wlc_hw->d11core, 0);
2875         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2876 }
2877
2878 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2879 {
2880         struct brcms_hardware *wlc_hw = wlc->hw;
2881         uint i;
2882
2883         /* free any posted tx packets */
2884         for (i = 0; i < NFIFO; i++) {
2885                 if (wlc_hw->di[i]) {
2886                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2887                         if (i < TX_BCMC_FIFO)
2888                                 ieee80211_wake_queue(wlc->pub->ieee_hw,
2889                                                      brcms_fifo_to_ac(i));
2890                 }
2891         }
2892
2893         /* free any posted rx packets */
2894         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2895 }
2896
2897 static u16
2898 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2899 {
2900         struct bcma_device *core = wlc_hw->d11core;
2901         u16 objoff = D11REGOFFS(objdata);
2902
2903         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2904         (void)bcma_read32(core, D11REGOFFS(objaddr));
2905         if (offset & 2)
2906                 objoff += 2;
2907
2908         return bcma_read16(core, objoff);
2909 }
2910
2911 static void
2912 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2913                      u32 sel)
2914 {
2915         struct bcma_device *core = wlc_hw->d11core;
2916         u16 objoff = D11REGOFFS(objdata);
2917
2918         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2919         (void)bcma_read32(core, D11REGOFFS(objaddr));
2920         if (offset & 2)
2921                 objoff += 2;
2922
2923         bcma_wflush16(core, objoff, v);
2924 }
2925
2926 /*
2927  * Read a single u16 from shared memory.
2928  * SHM 'offset' needs to be an even address
2929  */
2930 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2931 {
2932         return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2933 }
2934
2935 /*
2936  * Write a single u16 to shared memory.
2937  * SHM 'offset' needs to be an even address
2938  */
2939 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2940 {
2941         brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2942 }
2943
2944 /*
2945  * Copy a buffer to shared memory of specified type .
2946  * SHM 'offset' needs to be an even address and
2947  * Buffer length 'len' must be an even number of bytes
2948  * 'sel' selects the type of memory
2949  */
2950 void
2951 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2952                       const void *buf, int len, u32 sel)
2953 {
2954         u16 v;
2955         const u8 *p = (const u8 *)buf;
2956         int i;
2957
2958         if (len <= 0 || (offset & 1) || (len & 1))
2959                 return;
2960
2961         for (i = 0; i < len; i += 2) {
2962                 v = p[i] | (p[i + 1] << 8);
2963                 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2964         }
2965 }
2966
2967 /*
2968  * Copy a piece of shared memory of specified type to a buffer .
2969  * SHM 'offset' needs to be an even address and
2970  * Buffer length 'len' must be an even number of bytes
2971  * 'sel' selects the type of memory
2972  */
2973 void
2974 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2975                          int len, u32 sel)
2976 {
2977         u16 v;
2978         u8 *p = (u8 *) buf;
2979         int i;
2980
2981         if (len <= 0 || (offset & 1) || (len & 1))
2982                 return;
2983
2984         for (i = 0; i < len; i += 2) {
2985                 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2986                 p[i] = v & 0xFF;
2987                 p[i + 1] = (v >> 8) & 0xFF;
2988         }
2989 }
2990
2991 /* Copy a buffer to shared memory.
2992  * SHM 'offset' needs to be an even address and
2993  * Buffer length 'len' must be an even number of bytes
2994  */
2995 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2996                         const void *buf, int len)
2997 {
2998         brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2999 }
3000
3001 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3002                                    u16 SRL, u16 LRL)
3003 {
3004         wlc_hw->SRL = SRL;
3005         wlc_hw->LRL = LRL;
3006
3007         /* write retry limit to SCR, shouldn't need to suspend */
3008         if (wlc_hw->up) {
3009                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3010                              OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3011                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3012                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3013                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3014                              OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3015                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3016                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3017         }
3018 }
3019
3020 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3021 {
3022         if (set) {
3023                 if (mboolisset(wlc_hw->pllreq, req_bit))
3024                         return;
3025
3026                 mboolset(wlc_hw->pllreq, req_bit);
3027
3028                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3029                         if (!wlc_hw->sbclk)
3030                                 brcms_b_xtal(wlc_hw, ON);
3031                 }
3032         } else {
3033                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3034                         return;
3035
3036                 mboolclr(wlc_hw->pllreq, req_bit);
3037
3038                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3039                         if (wlc_hw->sbclk)
3040                                 brcms_b_xtal(wlc_hw, OFF);
3041                 }
3042         }
3043 }
3044
3045 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3046 {
3047         wlc_hw->antsel_avail = antsel_avail;
3048 }
3049
3050 /*
3051  * conditions under which the PM bit should be set in outgoing frames
3052  * and STAY_AWAKE is meaningful
3053  */
3054 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3055 {
3056         struct brcms_bss_cfg *cfg = wlc->bsscfg;
3057
3058         /* disallow PS when one of the following global conditions meets */
3059         if (!wlc->pub->associated)
3060                 return false;
3061
3062         /* disallow PS when one of these meets when not scanning */
3063         if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3064                 return false;
3065
3066         if (cfg->associated) {
3067                 /*
3068                  * disallow PS when one of the following
3069                  * bsscfg specific conditions meets
3070                  */
3071                 if (!cfg->BSS)
3072                         return false;
3073
3074                 return false;
3075         }
3076
3077         return true;
3078 }
3079
3080 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3081 {
3082         int i;
3083         struct macstat macstats;
3084 #ifdef DEBUG
3085         u16 delta;
3086         u16 rxf0ovfl;
3087         u16 txfunfl[NFIFO];
3088 #endif                          /* DEBUG */
3089
3090         /* if driver down, make no sense to update stats */
3091         if (!wlc->pub->up)
3092                 return;
3093
3094 #ifdef DEBUG
3095         /* save last rx fifo 0 overflow count */
3096         rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3097
3098         /* save last tx fifo  underflow count */
3099         for (i = 0; i < NFIFO; i++)