Merge branch 'fixes-for-3.8' of git://gitorious.org/linux-can/linux-can
[~shefty/rdma-dev.git] / drivers / net / wireless / brcm80211 / brcmsmac / main.c
1 /*
2  * Copyright (c) 2010 Broadcom Corporation
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
24 #include <aiutils.h>
25 #include <chipcommon.h>
26 #include "rate.h"
27 #include "scb.h"
28 #include "phy/phy_hal.h"
29 #include "channel.h"
30 #include "antsel.h"
31 #include "stf.h"
32 #include "ampdu.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
35 #include "main.h"
36 #include "soc.h"
37 #include "dma.h"
38 #include "debug.h"
39 #include "brcms_trace_events.h"
40
41 /* watchdog timer, in unit of ms */
42 #define TIMER_INTERVAL_WATCHDOG         1000
43 /* radio monitor timer, in unit of ms */
44 #define TIMER_INTERVAL_RADIOCHK         800
45
46 /* beacon interval, in unit of 1024TU */
47 #define BEACON_INTERVAL_DEFAULT         100
48
49 /* n-mode support capability */
50 /* 2x2 includes both 1x1 & 2x2 devices
51  * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
52  * control it independently
53  */
54 #define WL_11N_2x2                      1
55 #define WL_11N_3x3                      3
56 #define WL_11N_4x4                      4
57
58 #define EDCF_ACI_MASK                   0x60
59 #define EDCF_ACI_SHIFT                  5
60 #define EDCF_ECWMIN_MASK                0x0f
61 #define EDCF_ECWMAX_SHIFT               4
62 #define EDCF_AIFSN_MASK                 0x0f
63 #define EDCF_AIFSN_MAX                  15
64 #define EDCF_ECWMAX_MASK                0xf0
65
66 #define EDCF_AC_BE_TXOP_STA             0x0000
67 #define EDCF_AC_BK_TXOP_STA             0x0000
68 #define EDCF_AC_VO_ACI_STA              0x62
69 #define EDCF_AC_VO_ECW_STA              0x32
70 #define EDCF_AC_VI_ACI_STA              0x42
71 #define EDCF_AC_VI_ECW_STA              0x43
72 #define EDCF_AC_BK_ECW_STA              0xA4
73 #define EDCF_AC_VI_TXOP_STA             0x005e
74 #define EDCF_AC_VO_TXOP_STA             0x002f
75 #define EDCF_AC_BE_ACI_STA              0x03
76 #define EDCF_AC_BE_ECW_STA              0xA4
77 #define EDCF_AC_BK_ACI_STA              0x27
78 #define EDCF_AC_VO_TXOP_AP              0x002f
79
80 #define EDCF_TXOP2USEC(txop)            ((txop) << 5)
81 #define EDCF_ECW2CW(exp)                ((1 << (exp)) - 1)
82
83 #define APHY_SYMBOL_TIME                4
84 #define APHY_PREAMBLE_TIME              16
85 #define APHY_SIGNAL_TIME                4
86 #define APHY_SIFS_TIME                  16
87 #define APHY_SERVICE_NBITS              16
88 #define APHY_TAIL_NBITS                 6
89 #define BPHY_SIFS_TIME                  10
90 #define BPHY_PLCP_SHORT_TIME            96
91
92 #define PREN_PREAMBLE                   24
93 #define PREN_MM_EXT                     12
94 #define PREN_PREAMBLE_EXT               4
95
96 #define DOT11_MAC_HDR_LEN               24
97 #define DOT11_ACK_LEN                   10
98 #define DOT11_BA_LEN                    4
99 #define DOT11_OFDM_SIGNAL_EXTENSION     6
100 #define DOT11_MIN_FRAG_LEN              256
101 #define DOT11_RTS_LEN                   16
102 #define DOT11_CTS_LEN                   10
103 #define DOT11_BA_BITMAP_LEN             128
104 #define DOT11_MIN_BEACON_PERIOD         1
105 #define DOT11_MAX_BEACON_PERIOD         0xFFFF
106 #define DOT11_MAXNUMFRAGS               16
107 #define DOT11_MAX_FRAG_LEN              2346
108
109 #define BPHY_PLCP_TIME                  192
110 #define RIFS_11N_TIME                   2
111
112 /* length of the BCN template area */
113 #define BCN_TMPL_LEN                    512
114
115 /* brcms_bss_info flag bit values */
116 #define BRCMS_BSS_HT                    0x0020  /* BSS is HT (MIMO) capable */
117
118 /* chip rx buffer offset */
119 #define BRCMS_HWRXOFF                   38
120
121 /* rfdisable delay timer 500 ms, runs of ALP clock */
122 #define RFDISABLE_DEFAULT               10000000
123
124 #define BRCMS_TEMPSENSE_PERIOD          10      /* 10 second timeout */
125
126 /* synthpu_dly times in us */
127 #define SYNTHPU_DLY_APHY_US             3700
128 #define SYNTHPU_DLY_BPHY_US             1050
129 #define SYNTHPU_DLY_NPHY_US             2048
130 #define SYNTHPU_DLY_LPPHY_US            300
131
132 #define ANTCNT                          10      /* vanilla M_MAX_ANTCNT val */
133
134 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
135 #define EDCF_SHORT_S                    0
136 #define EDCF_SFB_S                      4
137 #define EDCF_LONG_S                     8
138 #define EDCF_LFB_S                      12
139 #define EDCF_SHORT_M                    BITFIELD_MASK(4)
140 #define EDCF_SFB_M                      BITFIELD_MASK(4)
141 #define EDCF_LONG_M                     BITFIELD_MASK(4)
142 #define EDCF_LFB_M                      BITFIELD_MASK(4)
143
144 #define RETRY_SHORT_DEF                 7       /* Default Short retry Limit */
145 #define RETRY_SHORT_MAX                 255     /* Maximum Short retry Limit */
146 #define RETRY_LONG_DEF                  4       /* Default Long retry count */
147 #define RETRY_SHORT_FB                  3       /* Short count for fb rate */
148 #define RETRY_LONG_FB                   2       /* Long count for fb rate */
149
150 #define APHY_CWMIN                      15
151 #define PHY_CWMAX                       1023
152
153 #define EDCF_AIFSN_MIN                  1
154
155 #define FRAGNUM_MASK                    0xF
156
157 #define APHY_SLOT_TIME                  9
158 #define BPHY_SLOT_TIME                  20
159
160 #define WL_SPURAVOID_OFF                0
161 #define WL_SPURAVOID_ON1                1
162 #define WL_SPURAVOID_ON2                2
163
164 /* invalid core flags, use the saved coreflags */
165 #define BRCMS_USE_COREFLAGS             0xffffffff
166
167 /* values for PLCPHdr_override */
168 #define BRCMS_PLCP_AUTO                 -1
169 #define BRCMS_PLCP_SHORT                0
170 #define BRCMS_PLCP_LONG                 1
171
172 /* values for g_protection_override and n_protection_override */
173 #define BRCMS_PROTECTION_AUTO           -1
174 #define BRCMS_PROTECTION_OFF            0
175 #define BRCMS_PROTECTION_ON             1
176 #define BRCMS_PROTECTION_MMHDR_ONLY     2
177 #define BRCMS_PROTECTION_CTS_ONLY       3
178
179 /* values for g_protection_control and n_protection_control */
180 #define BRCMS_PROTECTION_CTL_OFF        0
181 #define BRCMS_PROTECTION_CTL_LOCAL      1
182 #define BRCMS_PROTECTION_CTL_OVERLAP    2
183
184 /* values for n_protection */
185 #define BRCMS_N_PROTECTION_OFF          0
186 #define BRCMS_N_PROTECTION_OPTIONAL     1
187 #define BRCMS_N_PROTECTION_20IN40       2
188 #define BRCMS_N_PROTECTION_MIXEDMODE    3
189
190 /* values for band specific 40MHz capabilities */
191 #define BRCMS_N_BW_20ALL                0
192 #define BRCMS_N_BW_40ALL                1
193 #define BRCMS_N_BW_20IN2G_40IN5G        2
194
195 /* bitflags for SGI support (sgi_rx iovar) */
196 #define BRCMS_N_SGI_20                  0x01
197 #define BRCMS_N_SGI_40                  0x02
198
199 /* defines used by the nrate iovar */
200 /* MSC in use,indicates b0-6 holds an mcs */
201 #define NRATE_MCS_INUSE                 0x00000080
202 /* rate/mcs value */
203 #define NRATE_RATE_MASK                 0x0000007f
204 /* stf mode mask: siso, cdd, stbc, sdm */
205 #define NRATE_STF_MASK                  0x0000ff00
206 /* stf mode shift */
207 #define NRATE_STF_SHIFT                 8
208 /* bit indicate to override mcs only */
209 #define NRATE_OVERRIDE_MCS_ONLY         0x40000000
210 #define NRATE_SGI_MASK                  0x00800000      /* sgi mode */
211 #define NRATE_SGI_SHIFT                 23              /* sgi mode */
212 #define NRATE_LDPC_CODING               0x00400000      /* adv coding in use */
213 #define NRATE_LDPC_SHIFT                22              /* ldpc shift */
214
215 #define NRATE_STF_SISO                  0               /* stf mode SISO */
216 #define NRATE_STF_CDD                   1               /* stf mode CDD */
217 #define NRATE_STF_STBC                  2               /* stf mode STBC */
218 #define NRATE_STF_SDM                   3               /* stf mode SDM */
219
220 #define MAX_DMA_SEGS                    4
221
222 /* # of entries in Tx FIFO */
223 #define NTXD                            64
224 /* Max # of entries in Rx FIFO based on 4kb page size */
225 #define NRXD                            256
226
227 /* Amount of headroom to leave in Tx FIFO */
228 #define TX_HEADROOM                     4
229
230 /* try to keep this # rbufs posted to the chip */
231 #define NRXBUFPOST                      32
232
233 /* max # frames to process in brcms_c_recv() */
234 #define RXBND                           8
235 /* max # tx status to process in wlc_txstatus() */
236 #define TXSBND                          8
237
238 /* brcmu_format_flags() bit description structure */
239 struct brcms_c_bit_desc {
240         u32 bit;
241         const char *name;
242 };
243
244 /*
245  * The following table lists the buffer memory allocated to xmt fifos in HW.
246  * the size is in units of 256bytes(one block), total size is HW dependent
247  * ucode has default fifo partition, sw can overwrite if necessary
248  *
249  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
250  * the twiki is updated before making changes.
251  */
252
253 /* Starting corerev for the fifo size table */
254 #define XMTFIFOTBL_STARTREV     17
255
256 struct d11init {
257         __le16 addr;
258         __le16 size;
259         __le32 value;
260 };
261
262 struct edcf_acparam {
263         u8 ACI;
264         u8 ECW;
265         u16 TXOP;
266 } __packed;
267
268 /* debug/trace */
269 uint brcm_msg_level;
270
271 /* TX FIFO number to WME/802.1E Access Category */
272 static const u8 wme_fifo2ac[] = {
273         IEEE80211_AC_BK,
274         IEEE80211_AC_BE,
275         IEEE80211_AC_VI,
276         IEEE80211_AC_VO,
277         IEEE80211_AC_BE,
278         IEEE80211_AC_BE
279 };
280
281 /* ieee80211 Access Category to TX FIFO number */
282 static const u8 wme_ac2fifo[] = {
283         TX_AC_VO_FIFO,
284         TX_AC_VI_FIFO,
285         TX_AC_BE_FIFO,
286         TX_AC_BK_FIFO
287 };
288
289 static const u16 xmtfifo_sz[][NFIFO] = {
290         /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
291         {20, 192, 192, 21, 17, 5},
292         /* corerev 18: */
293         {0, 0, 0, 0, 0, 0},
294         /* corerev 19: */
295         {0, 0, 0, 0, 0, 0},
296         /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
297         {20, 192, 192, 21, 17, 5},
298         /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
299         {9, 58, 22, 14, 14, 5},
300         /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
301         {20, 192, 192, 21, 17, 5},
302         /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
303         {20, 192, 192, 21, 17, 5},
304         /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
305         {9, 58, 22, 14, 14, 5},
306         /* corerev 25: */
307         {0, 0, 0, 0, 0, 0},
308         /* corerev 26: */
309         {0, 0, 0, 0, 0, 0},
310         /* corerev 27: */
311         {0, 0, 0, 0, 0, 0},
312         /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
313         {9, 58, 22, 14, 14, 5},
314 };
315
316 #ifdef DEBUG
317 static const char * const fifo_names[] = {
318         "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
319 #else
320 static const char fifo_names[6][0];
321 #endif
322
323 #ifdef DEBUG
324 /* pointer to most recently allocated wl/wlc */
325 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
326 #endif
327
328 /* Mapping of ieee80211 AC numbers to tx fifos */
329 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
330         [IEEE80211_AC_VO]       = TX_AC_VO_FIFO,
331         [IEEE80211_AC_VI]       = TX_AC_VI_FIFO,
332         [IEEE80211_AC_BE]       = TX_AC_BE_FIFO,
333         [IEEE80211_AC_BK]       = TX_AC_BK_FIFO,
334 };
335
336 /* Mapping of tx fifos to ieee80211 AC numbers */
337 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
338         [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
339         [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
340         [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
341         [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
342 };
343
344 static u8 brcms_ac_to_fifo(u8 ac)
345 {
346         if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
347                 return TX_AC_BE_FIFO;
348         return ac_to_fifo_mapping[ac];
349 }
350
351 static u8 brcms_fifo_to_ac(u8 fifo)
352 {
353         if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
354                 return IEEE80211_AC_BE;
355         return fifo_to_ac_mapping[fifo];
356 }
357
358 /* Find basic rate for a given rate */
359 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
360 {
361         if (is_mcs_rate(rspec))
362                 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
363                        .leg_ofdm];
364         return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
365 }
366
367 static u16 frametype(u32 rspec, u8 mimoframe)
368 {
369         if (is_mcs_rate(rspec))
370                 return mimoframe;
371         return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
372 }
373
374 /* currently the best mechanism for determining SIFS is the band in use */
375 static u16 get_sifs(struct brcms_band *band)
376 {
377         return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
378                                  BPHY_SIFS_TIME;
379 }
380
381 /*
382  * Detect Card removed.
383  * Even checking an sbconfig register read will not false trigger when the core
384  * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
385  * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
386  * reg with fixed 0/1 pattern (some platforms return all 0).
387  * If clocks are present, call the sb routine which will figure out if the
388  * device is removed.
389  */
390 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
391 {
392         u32 macctrl;
393
394         if (!wlc->hw->clk)
395                 return ai_deviceremoved(wlc->hw->sih);
396         macctrl = bcma_read32(wlc->hw->d11core,
397                               D11REGOFFS(maccontrol));
398         return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
399 }
400
401 /* sum the individual fifo tx pending packet counts */
402 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
403 {
404         int i;
405         int pending = 0;
406
407         for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
408                 if (wlc->hw->di[i])
409                         pending += dma_txpending(wlc->hw->di[i]);
410         return pending;
411 }
412
413 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
414 {
415         return wlc->pub->_nbands > 1 && !wlc->bandlocked;
416 }
417
418 static int brcms_chspec_bw(u16 chanspec)
419 {
420         if (CHSPEC_IS40(chanspec))
421                 return BRCMS_40_MHZ;
422         if (CHSPEC_IS20(chanspec))
423                 return BRCMS_20_MHZ;
424
425         return BRCMS_10_MHZ;
426 }
427
428 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
429 {
430         if (cfg == NULL)
431                 return;
432
433         kfree(cfg->current_bss);
434         kfree(cfg);
435 }
436
437 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
438 {
439         if (wlc == NULL)
440                 return;
441
442         brcms_c_bsscfg_mfree(wlc->bsscfg);
443         kfree(wlc->pub);
444         kfree(wlc->modulecb);
445         kfree(wlc->default_bss);
446         kfree(wlc->protection);
447         kfree(wlc->stf);
448         kfree(wlc->bandstate[0]);
449         kfree(wlc->corestate->macstat_snapshot);
450         kfree(wlc->corestate);
451         kfree(wlc->hw->bandstate[0]);
452         kfree(wlc->hw);
453
454         /* free the wlc */
455         kfree(wlc);
456         wlc = NULL;
457 }
458
459 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
460 {
461         struct brcms_bss_cfg *cfg;
462
463         cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
464         if (cfg == NULL)
465                 goto fail;
466
467         cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
468         if (cfg->current_bss == NULL)
469                 goto fail;
470
471         return cfg;
472
473  fail:
474         brcms_c_bsscfg_mfree(cfg);
475         return NULL;
476 }
477
478 static struct brcms_c_info *
479 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
480 {
481         struct brcms_c_info *wlc;
482
483         wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
484         if (wlc == NULL) {
485                 *err = 1002;
486                 goto fail;
487         }
488
489         /* allocate struct brcms_c_pub state structure */
490         wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
491         if (wlc->pub == NULL) {
492                 *err = 1003;
493                 goto fail;
494         }
495         wlc->pub->wlc = wlc;
496
497         /* allocate struct brcms_hardware state structure */
498
499         wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
500         if (wlc->hw == NULL) {
501                 *err = 1005;
502                 goto fail;
503         }
504         wlc->hw->wlc = wlc;
505
506         wlc->hw->bandstate[0] =
507                 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
508         if (wlc->hw->bandstate[0] == NULL) {
509                 *err = 1006;
510                 goto fail;
511         } else {
512                 int i;
513
514                 for (i = 1; i < MAXBANDS; i++)
515                         wlc->hw->bandstate[i] = (struct brcms_hw_band *)
516                             ((unsigned long)wlc->hw->bandstate[0] +
517                              (sizeof(struct brcms_hw_band) * i));
518         }
519
520         wlc->modulecb =
521                 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
522         if (wlc->modulecb == NULL) {
523                 *err = 1009;
524                 goto fail;
525         }
526
527         wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
528         if (wlc->default_bss == NULL) {
529                 *err = 1010;
530                 goto fail;
531         }
532
533         wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
534         if (wlc->bsscfg == NULL) {
535                 *err = 1011;
536                 goto fail;
537         }
538
539         wlc->protection = kzalloc(sizeof(struct brcms_protection),
540                                   GFP_ATOMIC);
541         if (wlc->protection == NULL) {
542                 *err = 1016;
543                 goto fail;
544         }
545
546         wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
547         if (wlc->stf == NULL) {
548                 *err = 1017;
549                 goto fail;
550         }
551
552         wlc->bandstate[0] =
553                 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
554         if (wlc->bandstate[0] == NULL) {
555                 *err = 1025;
556                 goto fail;
557         } else {
558                 int i;
559
560                 for (i = 1; i < MAXBANDS; i++)
561                         wlc->bandstate[i] = (struct brcms_band *)
562                                 ((unsigned long)wlc->bandstate[0]
563                                 + (sizeof(struct brcms_band)*i));
564         }
565
566         wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
567         if (wlc->corestate == NULL) {
568                 *err = 1026;
569                 goto fail;
570         }
571
572         wlc->corestate->macstat_snapshot =
573                 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
574         if (wlc->corestate->macstat_snapshot == NULL) {
575                 *err = 1027;
576                 goto fail;
577         }
578
579         return wlc;
580
581  fail:
582         brcms_c_detach_mfree(wlc);
583         return NULL;
584 }
585
586 /*
587  * Update the slot timing for standard 11b/g (20us slots)
588  * or shortslot 11g (9us slots)
589  * The PSM needs to be suspended for this call.
590  */
591 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
592                                         bool shortslot)
593 {
594         struct bcma_device *core = wlc_hw->d11core;
595
596         if (shortslot) {
597                 /* 11g short slot: 11a timing */
598                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
599                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
600         } else {
601                 /* 11g long slot: 11b timing */
602                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
603                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
604         }
605 }
606
607 /*
608  * calculate frame duration of a given rate and length, return
609  * time in usec unit
610  */
611 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
612                                     u8 preamble_type, uint mac_len)
613 {
614         uint nsyms, dur = 0, Ndps, kNdps;
615         uint rate = rspec2rate(ratespec);
616
617         if (rate == 0) {
618                 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
619                           wlc->pub->unit);
620                 rate = BRCM_RATE_1M;
621         }
622
623         if (is_mcs_rate(ratespec)) {
624                 uint mcs = ratespec & RSPEC_RATE_MASK;
625                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
626
627                 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
628                 if (preamble_type == BRCMS_MM_PREAMBLE)
629                         dur += PREN_MM_EXT;
630                 /* 1000Ndbps = kbps * 4 */
631                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
632                                    rspec_issgi(ratespec)) * 4;
633
634                 if (rspec_stc(ratespec) == 0)
635                         nsyms =
636                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
637                                   APHY_TAIL_NBITS) * 1000, kNdps);
638                 else
639                         /* STBC needs to have even number of symbols */
640                         nsyms =
641                             2 *
642                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
643                                   APHY_TAIL_NBITS) * 1000, 2 * kNdps);
644
645                 dur += APHY_SYMBOL_TIME * nsyms;
646                 if (wlc->band->bandtype == BRCM_BAND_2G)
647                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
648         } else if (is_ofdm_rate(rate)) {
649                 dur = APHY_PREAMBLE_TIME;
650                 dur += APHY_SIGNAL_TIME;
651                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
652                 Ndps = rate * 2;
653                 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
654                 nsyms =
655                     CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
656                          Ndps);
657                 dur += APHY_SYMBOL_TIME * nsyms;
658                 if (wlc->band->bandtype == BRCM_BAND_2G)
659                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
660         } else {
661                 /*
662                  * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
663                  * will divide out
664                  */
665                 mac_len = mac_len * 8 * 2;
666                 /* calc ceiling of bits/rate = microseconds of air time */
667                 dur = (mac_len + rate - 1) / rate;
668                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
669                         dur += BPHY_PLCP_SHORT_TIME;
670                 else
671                         dur += BPHY_PLCP_TIME;
672         }
673         return dur;
674 }
675
676 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
677                                 const struct d11init *inits)
678 {
679         struct bcma_device *core = wlc_hw->d11core;
680         int i;
681         uint offset;
682         u16 size;
683         u32 value;
684
685         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
686
687         for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
688                 size = le16_to_cpu(inits[i].size);
689                 offset = le16_to_cpu(inits[i].addr);
690                 value = le32_to_cpu(inits[i].value);
691                 if (size == 2)
692                         bcma_write16(core, offset, value);
693                 else if (size == 4)
694                         bcma_write32(core, offset, value);
695                 else
696                         break;
697         }
698 }
699
700 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
701 {
702         u8 idx;
703         u16 addr[] = {
704                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
705                 M_HOST_FLAGS5
706         };
707
708         for (idx = 0; idx < MHFMAX; idx++)
709                 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
710 }
711
712 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
713 {
714         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
715
716         /* init microcode host flags */
717         brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
718
719         /* do band-specific ucode IHR, SHM, and SCR inits */
720         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
721                 if (BRCMS_ISNPHY(wlc_hw->band))
722                         brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
723                 else
724                         brcms_err(wlc_hw->d11core,
725                                   "%s: wl%d: unsupported phy in corerev %d\n",
726                                   __func__, wlc_hw->unit,
727                                   wlc_hw->corerev);
728         } else {
729                 if (D11REV_IS(wlc_hw->corerev, 24)) {
730                         if (BRCMS_ISLCNPHY(wlc_hw->band))
731                                 brcms_c_write_inits(wlc_hw,
732                                                     ucode->d11lcn0bsinitvals24);
733                         else
734                                 brcms_err(wlc_hw->d11core,
735                                           "%s: wl%d: unsupported phy in core rev %d\n",
736                                           __func__, wlc_hw->unit,
737                                           wlc_hw->corerev);
738                 } else {
739                         brcms_err(wlc_hw->d11core,
740                                   "%s: wl%d: unsupported corerev %d\n",
741                                   __func__, wlc_hw->unit, wlc_hw->corerev);
742                 }
743         }
744 }
745
746 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
747 {
748         struct bcma_device *core = wlc_hw->d11core;
749         u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
750
751         bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
752 }
753
754 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
755 {
756         brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
757
758         wlc_hw->phyclk = clk;
759
760         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
761
762                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
763                                    (SICF_PRST | SICF_FGC));
764                 udelay(1);
765                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
766                 udelay(1);
767
768         } else {                /* take phy out of reset */
769
770                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
771                 udelay(1);
772                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
773                 udelay(1);
774
775         }
776 }
777
778 /* low-level band switch utility routine */
779 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
780 {
781         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
782                            bandunit);
783
784         wlc_hw->band = wlc_hw->bandstate[bandunit];
785
786         /*
787          * BMAC_NOTE:
788          *   until we eliminate need for wlc->band refs in low level code
789          */
790         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
791
792         /* set gmode core flag */
793         if (wlc_hw->sbclk && !wlc_hw->noreset) {
794                 u32 gmode = 0;
795
796                 if (bandunit == 0)
797                         gmode = SICF_GMODE;
798
799                 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
800         }
801 }
802
803 /* switch to new band but leave it inactive */
804 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
805 {
806         struct brcms_hardware *wlc_hw = wlc->hw;
807         u32 macintmask;
808         u32 macctrl;
809
810         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
811         macctrl = bcma_read32(wlc_hw->d11core,
812                               D11REGOFFS(maccontrol));
813         WARN_ON((macctrl & MCTL_EN_MAC) != 0);
814
815         /* disable interrupts */
816         macintmask = brcms_intrsoff(wlc->wl);
817
818         /* radio off */
819         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
820
821         brcms_b_core_phy_clk(wlc_hw, OFF);
822
823         brcms_c_setxband(wlc_hw, bandunit);
824
825         return macintmask;
826 }
827
828 /* process an individual struct tx_status */
829 static bool
830 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
831 {
832         struct sk_buff *p = NULL;
833         uint queue = NFIFO;
834         struct dma_pub *dma = NULL;
835         struct d11txh *txh = NULL;
836         struct scb *scb = NULL;
837         bool free_pdu;
838         int tx_rts, tx_frame_count, tx_rts_count;
839         uint totlen, supr_status;
840         bool lastframe;
841         struct ieee80211_hdr *h;
842         u16 mcl;
843         struct ieee80211_tx_info *tx_info;
844         struct ieee80211_tx_rate *txrate;
845         int i;
846         bool fatal = true;
847
848         trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
849                              txs->frameid, txs->status, txs->lasttxtime,
850                              txs->sequence, txs->phyerr, txs->ackphyrxsh);
851
852         /* discard intermediate indications for ucode with one legitimate case:
853          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
854          *   but the subsequent tx of DATA failed. so it will start rts/cts
855          *   from the beginning (resetting the rts transmission count)
856          */
857         if (!(txs->status & TX_STATUS_AMPDU)
858             && (txs->status & TX_STATUS_INTERMEDIATE)) {
859                 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
860                 fatal = false;
861                 goto out;
862         }
863
864         queue = txs->frameid & TXFID_QUEUE_MASK;
865         if (queue >= NFIFO) {
866                 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
867                 goto out;
868         }
869
870         dma = wlc->hw->di[queue];
871
872         p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
873         if (p == NULL) {
874                 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
875                 goto out;
876         }
877
878         txh = (struct d11txh *) (p->data);
879         mcl = le16_to_cpu(txh->MacTxControlLow);
880
881         if (txs->phyerr)
882                 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
883                           txs->phyerr, txh->MainRates);
884
885         if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
886                 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
887                 goto out;
888         }
889         tx_info = IEEE80211_SKB_CB(p);
890         h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
891
892         if (tx_info->rate_driver_data[0])
893                 scb = &wlc->pri_scb;
894
895         if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
896                 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
897                 fatal = false;
898                 goto out;
899         }
900
901         /*
902          * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
903          * frames; this traces them for the rest.
904          */
905         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
906
907         supr_status = txs->status & TX_STATUS_SUPR_MASK;
908         if (supr_status == TX_STATUS_SUPR_BADCH) {
909                 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
910                 brcms_dbg_tx(wlc->hw->d11core,
911                              "Pkt tx suppressed, dest chan %u, current %d\n",
912                              (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
913                              CHSPEC_CHANNEL(wlc->default_bss->chanspec));
914         }
915
916         tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
917         tx_frame_count =
918             (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
919         tx_rts_count =
920             (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
921
922         lastframe = !ieee80211_has_morefrags(h->frame_control);
923
924         if (!lastframe) {
925                 brcms_err(wlc->hw->d11core, "Not last frame!\n");
926         } else {
927                 /*
928                  * Set information to be consumed by Minstrel ht.
929                  *
930                  * The "fallback limit" is the number of tx attempts a given
931                  * MPDU is sent at the "primary" rate. Tx attempts beyond that
932                  * limit are sent at the "secondary" rate.
933                  * A 'short frame' does not exceed RTS treshold.
934                  */
935                 u16 sfbl,       /* Short Frame Rate Fallback Limit */
936                     lfbl,       /* Long Frame Rate Fallback Limit */
937                     fbl;
938
939                 if (queue < IEEE80211_NUM_ACS) {
940                         sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
941                                       EDCF_SFB);
942                         lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
943                                       EDCF_LFB);
944                 } else {
945                         sfbl = wlc->SFBL;
946                         lfbl = wlc->LFBL;
947                 }
948
949                 txrate = tx_info->status.rates;
950                 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
951                         fbl = lfbl;
952                 else
953                         fbl = sfbl;
954
955                 ieee80211_tx_info_clear_status(tx_info);
956
957                 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
958                         /*
959                          * rate selection requested a fallback rate
960                          * and we used it
961                          */
962                         txrate[0].count = fbl;
963                         txrate[1].count = tx_frame_count - fbl;
964                 } else {
965                         /*
966                          * rate selection did not request fallback rate, or
967                          * we didn't need it
968                          */
969                         txrate[0].count = tx_frame_count;
970                         /*
971                          * rc80211_minstrel.c:minstrel_tx_status() expects
972                          * unused rates to be marked with idx = -1
973                          */
974                         txrate[1].idx = -1;
975                         txrate[1].count = 0;
976                 }
977
978                 /* clear the rest of the rates */
979                 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
980                         txrate[i].idx = -1;
981                         txrate[i].count = 0;
982                 }
983
984                 if (txs->status & TX_STATUS_ACK_RCV)
985                         tx_info->flags |= IEEE80211_TX_STAT_ACK;
986         }
987
988         totlen = p->len;
989         free_pdu = true;
990
991         if (lastframe) {
992                 /* remove PLCP & Broadcom tx descriptor header */
993                 skb_pull(p, D11_PHY_HDR_LEN);
994                 skb_pull(p, D11_TXH_LEN);
995                 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
996         } else {
997                 brcms_err(wlc->hw->d11core,
998                           "%s: Not last frame => not calling tx_status\n",
999                           __func__);
1000         }
1001
1002         fatal = false;
1003
1004  out:
1005         if (fatal) {
1006                 if (txh)
1007                         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1008                                            sizeof(*txh));
1009                 if (p)
1010                         brcmu_pkt_buf_free_skb(p);
1011         }
1012
1013         if (dma && queue < NFIFO) {
1014                 u16 ac_queue = brcms_fifo_to_ac(queue);
1015                 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1016                     ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1017                         ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1018                 dma_kick_tx(dma);
1019         }
1020
1021         return fatal;
1022 }
1023
1024 /* process tx completion events in BMAC
1025  * Return true if more tx status need to be processed. false otherwise.
1026  */
1027 static bool
1028 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1029 {
1030         struct bcma_device *core;
1031         struct tx_status txstatus, *txs;
1032         u32 s1, s2;
1033         uint n = 0;
1034         /*
1035          * Param 'max_tx_num' indicates max. # tx status to process before
1036          * break out.
1037          */
1038         uint max_tx_num = bound ? TXSBND : -1;
1039
1040         txs = &txstatus;
1041         core = wlc_hw->d11core;
1042         *fatal = false;
1043
1044         while (n < max_tx_num) {
1045                 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1046                 if (s1 == 0xffffffff) {
1047                         brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1048                                   __func__);
1049                         *fatal = true;
1050                         return false;
1051                 }
1052                 /* only process when valid */
1053                 if (!(s1 & TXS_V))
1054                         break;
1055
1056                 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1057                 txs->status = s1 & TXS_STATUS_MASK;
1058                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1059                 txs->sequence = s2 & TXS_SEQ_MASK;
1060                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1061                 txs->lasttxtime = 0;
1062
1063                 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1064                 if (*fatal == true)
1065                         return false;
1066                 n++;
1067         }
1068
1069         return n >= max_tx_num;
1070 }
1071
1072 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1073 {
1074         if (!wlc->bsscfg->BSS)
1075                 /*
1076                  * DirFrmQ is now valid...defer setting until end
1077                  * of ATIM window
1078                  */
1079                 wlc->qvalid |= MCMD_DIRFRMQVAL;
1080 }
1081
1082 /* set initial host flags value */
1083 static void
1084 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1085 {
1086         struct brcms_hardware *wlc_hw = wlc->hw;
1087
1088         memset(mhfs, 0, MHFMAX * sizeof(u16));
1089
1090         mhfs[MHF2] |= mhf2_init;
1091
1092         /* prohibit use of slowclock on multifunction boards */
1093         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1094                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1095
1096         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1097                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1098                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1099         }
1100 }
1101
1102 static uint
1103 dmareg(uint direction, uint fifonum)
1104 {
1105         if (direction == DMA_TX)
1106                 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1107         return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1108 }
1109
1110 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1111 {
1112         uint i;
1113         char name[8];
1114         /*
1115          * ucode host flag 2 needed for pio mode, independent of band and fifo
1116          */
1117         u16 pio_mhf2 = 0;
1118         struct brcms_hardware *wlc_hw = wlc->hw;
1119         uint unit = wlc_hw->unit;
1120
1121         /* name and offsets for dma_attach */
1122         snprintf(name, sizeof(name), "wl%d", unit);
1123
1124         if (wlc_hw->di[0] == NULL) {    /* Init FIFOs */
1125                 int dma_attach_err = 0;
1126
1127                 /*
1128                  * FIFO 0
1129                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1130                  * RX: RX_FIFO (RX data packets)
1131                  */
1132                 wlc_hw->di[0] = dma_attach(name, wlc,
1133                                            (wme ? dmareg(DMA_TX, 0) : 0),
1134                                            dmareg(DMA_RX, 0),
1135                                            (wme ? NTXD : 0), NRXD,
1136                                            RXBUFSZ, -1, NRXBUFPOST,
1137                                            BRCMS_HWRXOFF);
1138                 dma_attach_err |= (NULL == wlc_hw->di[0]);
1139
1140                 /*
1141                  * FIFO 1
1142                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1143                  *   (legacy) TX_DATA_FIFO (TX data packets)
1144                  * RX: UNUSED
1145                  */
1146                 wlc_hw->di[1] = dma_attach(name, wlc,
1147                                            dmareg(DMA_TX, 1), 0,
1148                                            NTXD, 0, 0, -1, 0, 0);
1149                 dma_attach_err |= (NULL == wlc_hw->di[1]);
1150
1151                 /*
1152                  * FIFO 2
1153                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1154                  * RX: UNUSED
1155                  */
1156                 wlc_hw->di[2] = dma_attach(name, wlc,
1157                                            dmareg(DMA_TX, 2), 0,
1158                                            NTXD, 0, 0, -1, 0, 0);
1159                 dma_attach_err |= (NULL == wlc_hw->di[2]);
1160                 /*
1161                  * FIFO 3
1162                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1163                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1164                  */
1165                 wlc_hw->di[3] = dma_attach(name, wlc,
1166                                            dmareg(DMA_TX, 3),
1167                                            0, NTXD, 0, 0, -1,
1168                                            0, 0);
1169                 dma_attach_err |= (NULL == wlc_hw->di[3]);
1170 /* Cleaner to leave this as if with AP defined */
1171
1172                 if (dma_attach_err) {
1173                         brcms_err(wlc_hw->d11core,
1174                                   "wl%d: wlc_attach: dma_attach failed\n",
1175                                   unit);
1176                         return false;
1177                 }
1178
1179                 /* get pointer to dma engine tx flow control variable */
1180                 for (i = 0; i < NFIFO; i++)
1181                         if (wlc_hw->di[i])
1182                                 wlc_hw->txavail[i] =
1183                                     (uint *) dma_getvar(wlc_hw->di[i],
1184                                                         "&txavail");
1185         }
1186
1187         /* initial ucode host flags */
1188         brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1189
1190         return true;
1191 }
1192
1193 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1194 {
1195         uint j;
1196
1197         for (j = 0; j < NFIFO; j++) {
1198                 if (wlc_hw->di[j]) {
1199                         dma_detach(wlc_hw->di[j]);
1200                         wlc_hw->di[j] = NULL;
1201                 }
1202         }
1203 }
1204
1205 /*
1206  * Initialize brcms_c_info default values ...
1207  * may get overrides later in this function
1208  *  BMAC_NOTES, move low out and resolve the dangling ones
1209  */
1210 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1211 {
1212         struct brcms_c_info *wlc = wlc_hw->wlc;
1213
1214         /* set default sw macintmask value */
1215         wlc->defmacintmask = DEF_MACINTMASK;
1216
1217         /* various 802.11g modes */
1218         wlc_hw->shortslot = false;
1219
1220         wlc_hw->SFBL = RETRY_SHORT_FB;
1221         wlc_hw->LFBL = RETRY_LONG_FB;
1222
1223         /* default mac retry limits */
1224         wlc_hw->SRL = RETRY_SHORT_DEF;
1225         wlc_hw->LRL = RETRY_LONG_DEF;
1226         wlc_hw->chanspec = ch20mhz_chspec(1);
1227 }
1228
1229 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1230 {
1231         /* delay before first read of ucode state */
1232         udelay(40);
1233
1234         /* wait until ucode is no longer asleep */
1235         SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1236                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1237 }
1238
1239 /* control chip clock to save power, enable dynamic clock or force fast clock */
1240 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1241 {
1242         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1243                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1244                  * on backplane, but mac core will still run on ALP(not HT) when
1245                  * it enters powersave mode, which means the FCA bit may not be
1246                  * set. Should wakeup mac if driver wants it to run on HT.
1247                  */
1248
1249                 if (wlc_hw->clk) {
1250                         if (mode == BCMA_CLKMODE_FAST) {
1251                                 bcma_set32(wlc_hw->d11core,
1252                                            D11REGOFFS(clk_ctl_st),
1253                                            CCS_FORCEHT);
1254
1255                                 udelay(64);
1256
1257                                 SPINWAIT(
1258                                     ((bcma_read32(wlc_hw->d11core,
1259                                       D11REGOFFS(clk_ctl_st)) &
1260                                       CCS_HTAVAIL) == 0),
1261                                       PMU_MAX_TRANSITION_DLY);
1262                                 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1263                                         D11REGOFFS(clk_ctl_st)) &
1264                                         CCS_HTAVAIL));
1265                         } else {
1266                                 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1267                                     (bcma_read32(wlc_hw->d11core,
1268                                         D11REGOFFS(clk_ctl_st)) &
1269                                         (CCS_FORCEHT | CCS_HTAREQ)))
1270                                         SPINWAIT(
1271                                             ((bcma_read32(wlc_hw->d11core,
1272                                               offsetof(struct d11regs,
1273                                                        clk_ctl_st)) &
1274                                               CCS_HTAVAIL) == 0),
1275                                               PMU_MAX_TRANSITION_DLY);
1276                                 bcma_mask32(wlc_hw->d11core,
1277                                         D11REGOFFS(clk_ctl_st),
1278                                         ~CCS_FORCEHT);
1279                         }
1280                 }
1281                 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1282         } else {
1283
1284                 /* old chips w/o PMU, force HT through cc,
1285                  * then use FCA to verify mac is running fast clock
1286                  */
1287
1288                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1289
1290                 /* check fast clock is available (if core is not in reset) */
1291                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1292                         WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1293                                   SISF_FCLKA));
1294
1295                 /*
1296                  * keep the ucode wake bit on if forcefastclk is on since we
1297                  * do not want ucode to put us back to slow clock when it dozes
1298                  * for PM mode. Code below matches the wake override bit with
1299                  * current forcefastclk state. Only setting bit in wake_override
1300                  * instead of waking ucode immediately since old code had this
1301                  * behavior. Older code set wlc->forcefastclk but only had the
1302                  * wake happen if the wakup_ucode work (protected by an up
1303                  * check) was executed just below.
1304                  */
1305                 if (wlc_hw->forcefastclk)
1306                         mboolset(wlc_hw->wake_override,
1307                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1308                 else
1309                         mboolclr(wlc_hw->wake_override,
1310                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1311         }
1312 }
1313
1314 /* set or clear ucode host flag bits
1315  * it has an optimization for no-change write
1316  * it only writes through shared memory when the core has clock;
1317  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1318  *
1319  *
1320  * bands values are: BRCM_BAND_AUTO <--- Current band only
1321  *                   BRCM_BAND_5G   <--- 5G band only
1322  *                   BRCM_BAND_2G   <--- 2G band only
1323  *                   BRCM_BAND_ALL  <--- All bands
1324  */
1325 void
1326 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1327              int bands)
1328 {
1329         u16 save;
1330         u16 addr[MHFMAX] = {
1331                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1332                 M_HOST_FLAGS5
1333         };
1334         struct brcms_hw_band *band;
1335
1336         if ((val & ~mask) || idx >= MHFMAX)
1337                 return; /* error condition */
1338
1339         switch (bands) {
1340                 /* Current band only or all bands,
1341                  * then set the band to current band
1342                  */
1343         case BRCM_BAND_AUTO:
1344         case BRCM_BAND_ALL:
1345                 band = wlc_hw->band;
1346                 break;
1347         case BRCM_BAND_5G:
1348                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1349                 break;
1350         case BRCM_BAND_2G:
1351                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1352                 break;
1353         default:
1354                 band = NULL;    /* error condition */
1355         }
1356
1357         if (band) {
1358                 save = band->mhfs[idx];
1359                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1360
1361                 /* optimization: only write through if changed, and
1362                  * changed band is the current band
1363                  */
1364                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1365                     && (band == wlc_hw->band))
1366                         brcms_b_write_shm(wlc_hw, addr[idx],
1367                                            (u16) band->mhfs[idx]);
1368         }
1369
1370         if (bands == BRCM_BAND_ALL) {
1371                 wlc_hw->bandstate[0]->mhfs[idx] =
1372                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1373                 wlc_hw->bandstate[1]->mhfs[idx] =
1374                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1375         }
1376 }
1377
1378 /* set the maccontrol register to desired reset state and
1379  * initialize the sw cache of the register
1380  */
1381 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1382 {
1383         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1384         wlc_hw->maccontrol = 0;
1385         wlc_hw->suspended_fifos = 0;
1386         wlc_hw->wake_override = 0;
1387         wlc_hw->mute_override = 0;
1388         brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1389 }
1390
1391 /*
1392  * write the software state of maccontrol and
1393  * overrides to the maccontrol register
1394  */
1395 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1396 {
1397         u32 maccontrol = wlc_hw->maccontrol;
1398
1399         /* OR in the wake bit if overridden */
1400         if (wlc_hw->wake_override)
1401                 maccontrol |= MCTL_WAKE;
1402
1403         /* set AP and INFRA bits for mute if needed */
1404         if (wlc_hw->mute_override) {
1405                 maccontrol &= ~(MCTL_AP);
1406                 maccontrol |= MCTL_INFRA;
1407         }
1408
1409         bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1410                      maccontrol);
1411 }
1412
1413 /* set or clear maccontrol bits */
1414 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1415 {
1416         u32 maccontrol;
1417         u32 new_maccontrol;
1418
1419         if (val & ~mask)
1420                 return; /* error condition */
1421         maccontrol = wlc_hw->maccontrol;
1422         new_maccontrol = (maccontrol & ~mask) | val;
1423
1424         /* if the new maccontrol value is the same as the old, nothing to do */
1425         if (new_maccontrol == maccontrol)
1426                 return;
1427
1428         /* something changed, cache the new value */
1429         wlc_hw->maccontrol = new_maccontrol;
1430
1431         /* write the new values with overrides applied */
1432         brcms_c_mctrl_write(wlc_hw);
1433 }
1434
1435 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1436                                  u32 override_bit)
1437 {
1438         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1439                 mboolset(wlc_hw->wake_override, override_bit);
1440                 return;
1441         }
1442
1443         mboolset(wlc_hw->wake_override, override_bit);
1444
1445         brcms_c_mctrl_write(wlc_hw);
1446         brcms_b_wait_for_wake(wlc_hw);
1447 }
1448
1449 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1450                                    u32 override_bit)
1451 {
1452         mboolclr(wlc_hw->wake_override, override_bit);
1453
1454         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1455                 return;
1456
1457         brcms_c_mctrl_write(wlc_hw);
1458 }
1459
1460 /* When driver needs ucode to stop beaconing, it has to make sure that
1461  * MCTL_AP is clear and MCTL_INFRA is set
1462  * Mode           MCTL_AP        MCTL_INFRA
1463  * AP                1              1
1464  * STA               0              1 <--- This will ensure no beacons
1465  * IBSS              0              0
1466  */
1467 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1468 {
1469         wlc_hw->mute_override = 1;
1470
1471         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1472          * override, then there is no change to write
1473          */
1474         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1475                 return;
1476
1477         brcms_c_mctrl_write(wlc_hw);
1478 }
1479
1480 /* Clear the override on AP and INFRA bits */
1481 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1482 {
1483         if (wlc_hw->mute_override == 0)
1484                 return;
1485
1486         wlc_hw->mute_override = 0;
1487
1488         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1489          * override, then there is no change to write
1490          */
1491         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1492                 return;
1493
1494         brcms_c_mctrl_write(wlc_hw);
1495 }
1496
1497 /*
1498  * Write a MAC address to the given match reg offset in the RXE match engine.
1499  */
1500 static void
1501 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1502                        const u8 *addr)
1503 {
1504         struct bcma_device *core = wlc_hw->d11core;
1505         u16 mac_l;
1506         u16 mac_m;
1507         u16 mac_h;
1508
1509         brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1510
1511         mac_l = addr[0] | (addr[1] << 8);
1512         mac_m = addr[2] | (addr[3] << 8);
1513         mac_h = addr[4] | (addr[5] << 8);
1514
1515         /* enter the MAC addr into the RXE match registers */
1516         bcma_write16(core, D11REGOFFS(rcm_ctl),
1517                      RCM_INC_DATA | match_reg_offset);
1518         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1519         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1520         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1521 }
1522
1523 void
1524 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1525                             void *buf)
1526 {
1527         struct bcma_device *core = wlc_hw->d11core;
1528         u32 word;
1529         __le32 word_le;
1530         __be32 word_be;
1531         bool be_bit;
1532         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1533
1534         bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1535
1536         /* if MCTL_BIGEND bit set in mac control register,
1537          * the chip swaps data in fifo, as well as data in
1538          * template ram
1539          */
1540         be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1541
1542         while (len > 0) {
1543                 memcpy(&word, buf, sizeof(u32));
1544
1545                 if (be_bit) {
1546                         word_be = cpu_to_be32(word);
1547                         word = *(u32 *)&word_be;
1548                 } else {
1549                         word_le = cpu_to_le32(word);
1550                         word = *(u32 *)&word_le;
1551                 }
1552
1553                 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1554
1555                 buf = (u8 *) buf + sizeof(u32);
1556                 len -= sizeof(u32);
1557         }
1558 }
1559
1560 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1561 {
1562         wlc_hw->band->CWmin = newmin;
1563
1564         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1565                      OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1566         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1567         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1568 }
1569
1570 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1571 {
1572         wlc_hw->band->CWmax = newmax;
1573
1574         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1575                      OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1576         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1577         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1578 }
1579
1580 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1581 {
1582         bool fastclk;
1583
1584         /* request FAST clock if not on */
1585         fastclk = wlc_hw->forcefastclk;
1586         if (!fastclk)
1587                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1588
1589         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1590
1591         brcms_b_phy_reset(wlc_hw);
1592         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1593
1594         /* restore the clk */
1595         if (!fastclk)
1596                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1597 }
1598
1599 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1600 {
1601         u16 v;
1602         struct brcms_c_info *wlc = wlc_hw->wlc;
1603         /* update SYNTHPU_DLY */
1604
1605         if (BRCMS_ISLCNPHY(wlc->band))
1606                 v = SYNTHPU_DLY_LPPHY_US;
1607         else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1608                 v = SYNTHPU_DLY_NPHY_US;
1609         else
1610                 v = SYNTHPU_DLY_BPHY_US;
1611
1612         brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1613 }
1614
1615 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1616 {
1617         u16 phyctl;
1618         u16 phytxant = wlc_hw->bmac_phytxant;
1619         u16 mask = PHY_TXC_ANT_MASK;
1620
1621         /* set the Probe Response frame phy control word */
1622         phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1623         phyctl = (phyctl & ~mask) | phytxant;
1624         brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1625
1626         /* set the Response (ACK/CTS) frame phy control word */
1627         phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1628         phyctl = (phyctl & ~mask) | phytxant;
1629         brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1630 }
1631
1632 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1633                                          u8 rate)
1634 {
1635         uint i;
1636         u8 plcp_rate = 0;
1637         struct plcp_signal_rate_lookup {
1638                 u8 rate;
1639                 u8 signal_rate;
1640         };
1641         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1642         const struct plcp_signal_rate_lookup rate_lookup[] = {
1643                 {BRCM_RATE_6M, 0xB},
1644                 {BRCM_RATE_9M, 0xF},
1645                 {BRCM_RATE_12M, 0xA},
1646                 {BRCM_RATE_18M, 0xE},
1647                 {BRCM_RATE_24M, 0x9},
1648                 {BRCM_RATE_36M, 0xD},
1649                 {BRCM_RATE_48M, 0x8},
1650                 {BRCM_RATE_54M, 0xC}
1651         };
1652
1653         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1654                 if (rate == rate_lookup[i].rate) {
1655                         plcp_rate = rate_lookup[i].signal_rate;
1656                         break;
1657                 }
1658         }
1659
1660         /* Find the SHM pointer to the rate table entry by looking in the
1661          * Direct-map Table
1662          */
1663         return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1664 }
1665
1666 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1667 {
1668         u8 rate;
1669         u8 rates[8] = {
1670                 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1671                 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1672         };
1673         u16 entry_ptr;
1674         u16 pctl1;
1675         uint i;
1676
1677         if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1678                 return;
1679
1680         /* walk the phy rate table and update the entries */
1681         for (i = 0; i < ARRAY_SIZE(rates); i++) {
1682                 rate = rates[i];
1683
1684                 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1685
1686                 /* read the SHM Rate Table entry OFDM PCTL1 values */
1687                 pctl1 =
1688                     brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1689
1690                 /* modify the value */
1691                 pctl1 &= ~PHY_TXC1_MODE_MASK;
1692                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1693
1694                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1695                 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1696                                    pctl1);
1697         }
1698 }
1699
1700 /* band-specific init */
1701 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1702 {
1703         struct brcms_hardware *wlc_hw = wlc->hw;
1704
1705         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1706                            wlc_hw->band->bandunit);
1707
1708         brcms_c_ucode_bsinit(wlc_hw);
1709
1710         wlc_phy_init(wlc_hw->band->pi, chanspec);
1711
1712         brcms_c_ucode_txant_set(wlc_hw);
1713
1714         /*
1715          * cwmin is band-specific, update hardware
1716          * with value for current band
1717          */
1718         brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1719         brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1720
1721         brcms_b_update_slot_timing(wlc_hw,
1722                                    wlc_hw->band->bandtype == BRCM_BAND_5G ?
1723                                    true : wlc_hw->shortslot);
1724
1725         /* write phytype and phyvers */
1726         brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1727         brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1728
1729         /*
1730          * initialize the txphyctl1 rate table since
1731          * shmem is shared between bands
1732          */
1733         brcms_upd_ofdm_pctl1_table(wlc_hw);
1734
1735         brcms_b_upd_synthpu(wlc_hw);
1736 }
1737
1738 /* Perform a soft reset of the PHY PLL */
1739 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1740 {
1741         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1742                   ~0, 0);
1743         udelay(1);
1744         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1745                   0x4, 0);
1746         udelay(1);
1747         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1748                   0x4, 4);
1749         udelay(1);
1750         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1751                   0x4, 0);
1752         udelay(1);
1753 }
1754
1755 /* light way to turn on phy clock without reset for NPHY only
1756  *  refer to brcms_b_core_phy_clk for full version
1757  */
1758 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1759 {
1760         /* support(necessary for NPHY and HYPHY) only */
1761         if (!BRCMS_ISNPHY(wlc_hw->band))
1762                 return;
1763
1764         if (ON == clk)
1765                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1766         else
1767                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1768
1769 }
1770
1771 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1772 {
1773         if (ON == clk)
1774                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1775         else
1776                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1777 }
1778
1779 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1780 {
1781         struct brcms_phy_pub *pih = wlc_hw->band->pi;
1782         u32 phy_bw_clkbits;
1783         bool phy_in_reset = false;
1784
1785         brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1786
1787         if (pih == NULL)
1788                 return;
1789
1790         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1791
1792         /* Specific reset sequence required for NPHY rev 3 and 4 */
1793         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1794             NREV_LE(wlc_hw->band->phyrev, 4)) {
1795                 /* Set the PHY bandwidth */
1796                 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1797
1798                 udelay(1);
1799
1800                 /* Perform a soft reset of the PHY PLL */
1801                 brcms_b_core_phypll_reset(wlc_hw);
1802
1803                 /* reset the PHY */
1804                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1805                                    (SICF_PRST | SICF_PCLKE));
1806                 phy_in_reset = true;
1807         } else {
1808                 brcms_b_core_ioctl(wlc_hw,
1809                                    (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1810                                    (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1811         }
1812
1813         udelay(2);
1814         brcms_b_core_phy_clk(wlc_hw, ON);
1815
1816         if (pih)
1817                 wlc_phy_anacore(pih, ON);
1818 }
1819
1820 /* switch to and initialize new band */
1821 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1822                             u16 chanspec) {
1823         struct brcms_c_info *wlc = wlc_hw->wlc;
1824         u32 macintmask;
1825
1826         /* Enable the d11 core before accessing it */
1827         if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1828                 bcma_core_enable(wlc_hw->d11core, 0);
1829                 brcms_c_mctrl_reset(wlc_hw);
1830         }
1831
1832         macintmask = brcms_c_setband_inact(wlc, bandunit);
1833
1834         if (!wlc_hw->up)
1835                 return;
1836
1837         brcms_b_core_phy_clk(wlc_hw, ON);
1838
1839         /* band-specific initializations */
1840         brcms_b_bsinit(wlc, chanspec);
1841
1842         /*
1843          * If there are any pending software interrupt bits,
1844          * then replace these with a harmless nonzero value
1845          * so brcms_c_dpc() will re-enable interrupts when done.
1846          */
1847         if (wlc->macintstatus)
1848                 wlc->macintstatus = MI_DMAINT;
1849
1850         /* restore macintmask */
1851         brcms_intrsrestore(wlc->wl, macintmask);
1852
1853         /* ucode should still be suspended.. */
1854         WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1855                  MCTL_EN_MAC) != 0);
1856 }
1857
1858 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1859 {
1860
1861         /* reject unsupported corerev */
1862         if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1863                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1864                           wlc_hw->corerev);
1865                 return false;
1866         }
1867
1868         return true;
1869 }
1870
1871 /* Validate some board info parameters */
1872 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1873 {
1874         uint boardrev = wlc_hw->boardrev;
1875
1876         /* 4 bits each for board type, major, minor, and tiny version */
1877         uint brt = (boardrev & 0xf000) >> 12;
1878         uint b0 = (boardrev & 0xf00) >> 8;
1879         uint b1 = (boardrev & 0xf0) >> 4;
1880         uint b2 = boardrev & 0xf;
1881
1882         /* voards from other vendors are always considered valid */
1883         if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1884                 return true;
1885
1886         /* do some boardrev sanity checks when boardvendor is Broadcom */
1887         if (boardrev == 0)
1888                 return false;
1889
1890         if (boardrev <= 0xff)
1891                 return true;
1892
1893         if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1894                 || (b2 > 9))
1895                 return false;
1896
1897         return true;
1898 }
1899
1900 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1901 {
1902         struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1903
1904         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1905         if (!is_zero_ether_addr(sprom->il0mac)) {
1906                 memcpy(etheraddr, sprom->il0mac, 6);
1907                 return;
1908         }
1909
1910         if (wlc_hw->_nbands > 1)
1911                 memcpy(etheraddr, sprom->et1mac, 6);
1912         else
1913                 memcpy(etheraddr, sprom->il0mac, 6);
1914 }
1915
1916 /* power both the pll and external oscillator on/off */
1917 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1918 {
1919         brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1920
1921         /*
1922          * dont power down if plldown is false or
1923          * we must poll hw radio disable
1924          */
1925         if (!want && wlc_hw->pllreq)
1926                 return;
1927
1928         wlc_hw->sbclk = want;
1929         if (!wlc_hw->sbclk) {
1930                 wlc_hw->clk = false;
1931                 if (wlc_hw->band && wlc_hw->band->pi)
1932                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1933         }
1934 }
1935
1936 /*
1937  * Return true if radio is disabled, otherwise false.
1938  * hw radio disable signal is an external pin, users activate it asynchronously
1939  * this function could be called when driver is down and w/o clock
1940  * it operates on different registers depending on corerev and boardflag.
1941  */
1942 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1943 {
1944         bool v, clk, xtal;
1945         u32 flags = 0;
1946
1947         xtal = wlc_hw->sbclk;
1948         if (!xtal)
1949                 brcms_b_xtal(wlc_hw, ON);
1950
1951         /* may need to take core out of reset first */
1952         clk = wlc_hw->clk;
1953         if (!clk) {
1954                 /*
1955                  * mac no longer enables phyclk automatically when driver
1956                  * accesses phyreg throughput mac. This can be skipped since
1957                  * only mac reg is accessed below
1958                  */
1959                 if (D11REV_GE(wlc_hw->corerev, 18))
1960                         flags |= SICF_PCLKE;
1961
1962                 /*
1963                  * TODO: test suspend/resume
1964                  *
1965                  * AI chip doesn't restore bar0win2 on
1966                  * hibernation/resume, need sw fixup
1967                  */
1968
1969                 bcma_core_enable(wlc_hw->d11core, flags);
1970                 brcms_c_mctrl_reset(wlc_hw);
1971         }
1972
1973         v = ((bcma_read32(wlc_hw->d11core,
1974                           D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1975
1976         /* put core back into reset */
1977         if (!clk)
1978                 bcma_core_disable(wlc_hw->d11core, 0);
1979
1980         if (!xtal)
1981                 brcms_b_xtal(wlc_hw, OFF);
1982
1983         return v;
1984 }
1985
1986 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1987 {
1988         struct dma_pub *di = wlc_hw->di[fifo];
1989         return dma_rxreset(di);
1990 }
1991
1992 /* d11 core reset
1993  *   ensure fask clock during reset
1994  *   reset dma
1995  *   reset d11(out of reset)
1996  *   reset phy(out of reset)
1997  *   clear software macintstatus for fresh new start
1998  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1999  */
2000 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2001 {
2002         uint i;
2003         bool fastclk;
2004
2005         if (flags == BRCMS_USE_COREFLAGS)
2006                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2007
2008         brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2009
2010         /* request FAST clock if not on  */
2011         fastclk = wlc_hw->forcefastclk;
2012         if (!fastclk)
2013                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2014
2015         /* reset the dma engines except first time thru */
2016         if (bcma_core_is_enabled(wlc_hw->d11core)) {
2017                 for (i = 0; i < NFIFO; i++)
2018                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2019                                 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2020                                           "dma_txreset[%d]: cannot stop dma\n",
2021                                            wlc_hw->unit, __func__, i);
2022
2023                 if ((wlc_hw->di[RX_FIFO])
2024                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2025                         brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2026                                   "[%d]: cannot stop dma\n",
2027                                   wlc_hw->unit, __func__, RX_FIFO);
2028         }
2029         /* if noreset, just stop the psm and return */
2030         if (wlc_hw->noreset) {
2031                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2032                 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2033                 return;
2034         }
2035
2036         /*
2037          * mac no longer enables phyclk automatically when driver accesses
2038          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2039          * band->pi is invalid. need to enable PHY CLK
2040          */
2041         if (D11REV_GE(wlc_hw->corerev, 18))
2042                 flags |= SICF_PCLKE;
2043
2044         /*
2045          * reset the core
2046          * In chips with PMU, the fastclk request goes through d11 core
2047          * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2048          *
2049          * This adds some delay and we can optimize it by also requesting
2050          * fastclk through chipcommon during this period if necessary. But
2051          * that has to work coordinate with other driver like mips/arm since
2052          * they may touch chipcommon as well.
2053          */
2054         wlc_hw->clk = false;
2055         bcma_core_enable(wlc_hw->d11core, flags);
2056         wlc_hw->clk = true;
2057         if (wlc_hw->band && wlc_hw->band->pi)
2058                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2059
2060         brcms_c_mctrl_reset(wlc_hw);
2061
2062         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2063                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2064
2065         brcms_b_phy_reset(wlc_hw);
2066
2067         /* turn on PHY_PLL */
2068         brcms_b_core_phypll_ctl(wlc_hw, true);
2069
2070         /* clear sw intstatus */
2071         wlc_hw->wlc->macintstatus = 0;
2072
2073         /* restore the clk setting */
2074         if (!fastclk)
2075                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2076 }
2077
2078 /* txfifo sizes needs to be modified(increased) since the newer cores
2079  * have more memory.
2080  */
2081 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2082 {
2083         struct bcma_device *core = wlc_hw->d11core;
2084         u16 fifo_nu;
2085         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2086         u16 txfifo_def, txfifo_def1;
2087         u16 txfifo_cmd;
2088
2089         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2090         txfifo_startblk = TXFIFO_START_BLK;
2091
2092         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2093         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2094
2095                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2096                 txfifo_def = (txfifo_startblk & 0xff) |
2097                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2098                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2099                     ((((txfifo_endblk -
2100                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2101                 txfifo_cmd =
2102                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2103
2104                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2105                 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2106                 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2107
2108                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2109
2110                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2111         }
2112         /*
2113          * need to propagate to shm location to be in sync since ucode/hw won't
2114          * do this
2115          */
2116         brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2117                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2118         brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2119                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2120         brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2121                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2122                             xmtfifo_sz[TX_AC_BK_FIFO]));
2123         brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2124                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2125                             xmtfifo_sz[TX_BCMC_FIFO]));
2126 }
2127
2128 /* This function is used for changing the tsf frac register
2129  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2130  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2131  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2132  * HTPHY Formula is 2^26/freq(MHz) e.g.
2133  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2134  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2135  * For spuron: 123MHz -> 2^26/123    = 545600.5
2136  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2137  * For spur off: 120MHz -> 2^26/120    = 559240.5
2138  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2139  */
2140
2141 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2142 {
2143         struct bcma_device *core = wlc_hw->d11core;
2144
2145         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2146             (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2147                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2148                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2149                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2150                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2151                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2152                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2153                 } else {        /* 120Mhz */
2154                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2155                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2156                 }
2157         } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2158                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2159                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2160                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2161                 } else {        /* 80Mhz */
2162                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2163                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2164                 }
2165         }
2166 }
2167
2168 /* Initialize GPIOs that are controlled by D11 core */
2169 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2170 {
2171         struct brcms_hardware *wlc_hw = wlc->hw;
2172         u32 gc, gm;
2173
2174         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2175         brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2176
2177         /*
2178          * Common GPIO setup:
2179          *      G0 = LED 0 = WLAN Activity
2180          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2181          *      G2 = LED 2 = WLAN 5 GHz Radio State
2182          *      G4 = radio disable input (HI enabled, LO disabled)
2183          */
2184
2185         gc = gm = 0;
2186
2187         /* Allocate GPIOs for mimo antenna diversity feature */
2188         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2189                 /* Enable antenna diversity, use 2x3 mode */
2190                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2191                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2192                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2193                              MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2194
2195                 /* init superswitch control */
2196                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2197
2198         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2199                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2200                 /*
2201                  * The board itself is powered by these GPIOs
2202                  * (when not sending pattern) so set them high
2203                  */
2204                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2205                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2206                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2207                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2208
2209                 /* Enable antenna diversity, use 2x4 mode */
2210                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2211                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2212                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2213                              BRCM_BAND_ALL);
2214
2215                 /* Configure the desired clock to be 4Mhz */
2216                 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2217                                    ANTSEL_CLKDIV_4MHZ);
2218         }
2219
2220         /*
2221          * gpio 9 controls the PA. ucode is responsible
2222          * for wiggling out and oe
2223          */
2224         if (wlc_hw->boardflags & BFL_PACTRL)
2225                 gm |= gc |= BOARD_GPIO_PACTRL;
2226
2227         /* apply to gpiocontrol register */
2228         bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2229 }
2230
2231 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2232                               const __le32 ucode[], const size_t nbytes)
2233 {
2234         struct bcma_device *core = wlc_hw->d11core;
2235         uint i;
2236         uint count;
2237
2238         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2239
2240         count = (nbytes / sizeof(u32));
2241
2242         bcma_write32(core, D11REGOFFS(objaddr),
2243                      OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2244         (void)bcma_read32(core, D11REGOFFS(objaddr));
2245         for (i = 0; i < count; i++)
2246                 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2247
2248 }
2249
2250 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2251 {
2252         struct brcms_c_info *wlc;
2253         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2254
2255         wlc = wlc_hw->wlc;
2256
2257         if (wlc_hw->ucode_loaded)
2258                 return;
2259
2260         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2261                 if (BRCMS_ISNPHY(wlc_hw->band)) {
2262                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2263                                           ucode->bcm43xx_16_mimosz);
2264                         wlc_hw->ucode_loaded = true;
2265                 } else
2266                         brcms_err(wlc_hw->d11core,
2267                                   "%s: wl%d: unsupported phy in corerev %d\n",
2268                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2269         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2270                 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2271                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2272                                           ucode->bcm43xx_24_lcnsz);
2273                         wlc_hw->ucode_loaded = true;
2274                 } else {
2275                         brcms_err(wlc_hw->d11core,
2276                                   "%s: wl%d: unsupported phy in corerev %d\n",
2277                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2278                 }
2279         }
2280 }
2281
2282 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2283 {
2284         /* update sw state */
2285         wlc_hw->bmac_phytxant = phytxant;
2286
2287         /* push to ucode if up */
2288         if (!wlc_hw->up)
2289                 return;
2290         brcms_c_ucode_txant_set(wlc_hw);
2291
2292 }
2293
2294 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2295 {
2296         return (u16) wlc_hw->wlc->stf->txant;
2297 }
2298
2299 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2300 {
2301         wlc_hw->antsel_type = antsel_type;
2302
2303         /* Update the antsel type for phy module to use */
2304         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2305 }
2306
2307 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2308 {
2309         bool fatal = false;
2310         uint unit;
2311         uint intstatus, idx;
2312         struct bcma_device *core = wlc_hw->d11core;
2313
2314         unit = wlc_hw->unit;
2315
2316         for (idx = 0; idx < NFIFO; idx++) {
2317                 /* read intstatus register and ignore any non-error bits */
2318                 intstatus =
2319                         bcma_read32(core,
2320                                     D11REGOFFS(intctrlregs[idx].intstatus)) &
2321                         I_ERRORS;
2322                 if (!intstatus)
2323                         continue;
2324
2325                 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2326                               unit, idx, intstatus);
2327
2328                 if (intstatus & I_RO) {
2329                         brcms_err(core, "wl%d: fifo %d: receive fifo "
2330                                   "overflow\n", unit, idx);
2331                         fatal = true;
2332                 }
2333
2334                 if (intstatus & I_PC) {
2335                         brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2336                                   unit, idx);
2337                         fatal = true;
2338                 }
2339
2340                 if (intstatus & I_PD) {
2341                         brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2342                                   idx);
2343                         fatal = true;
2344                 }
2345
2346                 if (intstatus & I_DE) {
2347                         brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2348                                   "error\n", unit, idx);
2349                         fatal = true;
2350                 }
2351
2352                 if (intstatus & I_RU)
2353                         brcms_err(core, "wl%d: fifo %d: receive descriptor "
2354                                   "underflow\n", idx, unit);
2355
2356                 if (intstatus & I_XU) {
2357                         brcms_err(core, "wl%d: fifo %d: transmit fifo "
2358                                   "underflow\n", idx, unit);
2359                         fatal = true;
2360                 }
2361
2362                 if (fatal) {
2363                         brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2364                         break;
2365                 } else
2366                         bcma_write32(core,
2367                                      D11REGOFFS(intctrlregs[idx].intstatus),
2368                                      intstatus);
2369         }
2370 }
2371
2372 void brcms_c_intrson(struct brcms_c_info *wlc)
2373 {
2374         struct brcms_hardware *wlc_hw = wlc->hw;
2375         wlc->macintmask = wlc->defmacintmask;
2376         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2377 }
2378
2379 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2380 {
2381         struct brcms_hardware *wlc_hw = wlc->hw;
2382         u32 macintmask;
2383
2384         if (!wlc_hw->clk)
2385                 return 0;
2386
2387         macintmask = wlc->macintmask;   /* isr can still happen */
2388
2389         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2390         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2391         udelay(1);              /* ensure int line is no longer driven */
2392         wlc->macintmask = 0;
2393
2394         /* return previous macintmask; resolve race between us and our isr */
2395         return wlc->macintstatus ? 0 : macintmask;
2396 }
2397
2398 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2399 {
2400         struct brcms_hardware *wlc_hw = wlc->hw;
2401         if (!wlc_hw->clk)
2402                 return;
2403
2404         wlc->macintmask = macintmask;
2405         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2406 }
2407
2408 /* assumes that the d11 MAC is enabled */
2409 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2410                                     uint tx_fifo)
2411 {
2412         u8 fifo = 1 << tx_fifo;
2413
2414         /* Two clients of this code, 11h Quiet period and scanning. */
2415
2416         /* only suspend if not already suspended */
2417         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2418                 return;
2419
2420         /* force the core awake only if not already */
2421         if (wlc_hw->suspended_fifos == 0)
2422                 brcms_c_ucode_wake_override_set(wlc_hw,
2423                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2424
2425         wlc_hw->suspended_fifos |= fifo;
2426
2427         if (wlc_hw->di[tx_fifo]) {
2428                 /*
2429                  * Suspending AMPDU transmissions in the middle can cause
2430                  * underflow which may result in mismatch between ucode and
2431                  * driver so suspend the mac before suspending the FIFO
2432                  */
2433                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2434                         brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2435
2436                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2437
2438                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2439                         brcms_c_enable_mac(wlc_hw->wlc);
2440         }
2441 }
2442
2443 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2444                                    uint tx_fifo)
2445 {
2446         /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2447          * but need to be done here for PIO otherwise the watchdog will catch
2448          * the inconsistency and fire
2449          */
2450         /* Two clients of this code, 11h Quiet period and scanning. */
2451         if (wlc_hw->di[tx_fifo])
2452                 dma_txresume(wlc_hw->di[tx_fifo]);
2453
2454         /* allow core to sleep again */
2455         if (wlc_hw->suspended_fifos == 0)
2456                 return;
2457         else {
2458                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2459                 if (wlc_hw->suspended_fifos == 0)
2460                         brcms_c_ucode_wake_override_clear(wlc_hw,
2461                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2462         }
2463 }
2464
2465 /* precondition: requires the mac core to be enabled */
2466 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2467 {
2468         static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2469
2470         if (mute_tx) {
2471                 /* suspend tx fifos */
2472                 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2473                 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2474                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2475                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2476
2477                 /* zero the address match register so we do not send ACKs */
2478                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2479                                        null_ether_addr);
2480         } else {
2481                 /* resume tx fifos */
2482                 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2483                 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2484                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2485                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2486
2487                 /* Restore address */
2488                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2489                                        wlc_hw->etheraddr);
2490         }
2491
2492         wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2493
2494         if (mute_tx)
2495                 brcms_c_ucode_mute_override_set(wlc_hw);
2496         else
2497                 brcms_c_ucode_mute_override_clear(wlc_hw);
2498 }
2499
2500 void
2501 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2502 {
2503         brcms_b_mute(wlc->hw, mute_tx);
2504 }
2505
2506 /*
2507  * Read and clear macintmask and macintstatus and intstatus registers.
2508  * This routine should be called with interrupts off
2509  * Return:
2510  *   -1 if brcms_deviceremoved(wlc) evaluates to true;
2511  *   0 if the interrupt is not for us, or we are in some special cases;
2512  *   device interrupt status bits otherwise.
2513  */
2514 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2515 {
2516         struct brcms_hardware *wlc_hw = wlc->hw;
2517         struct bcma_device *core = wlc_hw->d11core;
2518         u32 macintstatus, mask;
2519
2520         /* macintstatus includes a DMA interrupt summary bit */
2521         macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2522         mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2523
2524         trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2525
2526         /* detect cardbus removed, in power down(suspend) and in reset */
2527         if (brcms_deviceremoved(wlc))
2528                 return -1;
2529
2530         /* brcms_deviceremoved() succeeds even when the core is still resetting,
2531          * handle that case here.
2532          */
2533         if (macintstatus == 0xffffffff)
2534                 return 0;
2535
2536         /* defer unsolicited interrupts */
2537         macintstatus &= mask;
2538
2539         /* if not for us */
2540         if (macintstatus == 0)
2541                 return 0;
2542
2543         /* turn off the interrupts */
2544         bcma_write32(core, D11REGOFFS(macintmask), 0);
2545         (void)bcma_read32(core, D11REGOFFS(macintmask));
2546         wlc->macintmask = 0;
2547
2548         /* clear device interrupts */
2549         bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2550
2551         /* MI_DMAINT is indication of non-zero intstatus */
2552         if (macintstatus & MI_DMAINT)
2553                 /*
2554                  * only fifo interrupt enabled is I_RI in
2555                  * RX_FIFO. If MI_DMAINT is set, assume it
2556                  * is set and clear the interrupt.
2557                  */
2558                 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2559                              DEF_RXINTMASK);
2560
2561         return macintstatus;
2562 }
2563
2564 /* Update wlc->macintstatus and wlc->intstatus[]. */
2565 /* Return true if they are updated successfully. false otherwise */
2566 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2567 {
2568         u32 macintstatus;
2569
2570         /* read and clear macintstatus and intstatus registers */
2571         macintstatus = wlc_intstatus(wlc, false);
2572
2573         /* device is removed */
2574         if (macintstatus == 0xffffffff)
2575                 return false;
2576
2577         /* update interrupt status in software */
2578         wlc->macintstatus |= macintstatus;
2579
2580         return true;
2581 }
2582
2583 /*
2584  * First-level interrupt processing.
2585  * Return true if this was our interrupt
2586  * and if further brcms_c_dpc() processing is required,
2587  * false otherwise.
2588  */
2589 bool brcms_c_isr(struct brcms_c_info *wlc)
2590 {
2591         struct brcms_hardware *wlc_hw = wlc->hw;
2592         u32 macintstatus;
2593
2594         if (!wlc_hw->up || !wlc->macintmask)
2595                 return false;
2596
2597         /* read and clear macintstatus and intstatus registers */
2598         macintstatus = wlc_intstatus(wlc, true);
2599
2600         if (macintstatus == 0xffffffff) {
2601                 brcms_err(wlc_hw->d11core,
2602                           "DEVICEREMOVED detected in the ISR code path\n");
2603                 return false;
2604         }
2605
2606         /* it is not for us */
2607         if (macintstatus == 0)
2608                 return false;
2609
2610         /* save interrupt status bits */
2611         wlc->macintstatus = macintstatus;
2612
2613         return true;
2614
2615 }
2616
2617 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2618 {
2619         struct brcms_hardware *wlc_hw = wlc->hw;
2620         struct bcma_device *core = wlc_hw->d11core;
2621         u32 mc, mi;
2622
2623         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2624                            wlc_hw->band->bandunit);
2625
2626         /*
2627          * Track overlapping suspend requests
2628          */
2629         wlc_hw->mac_suspend_depth++;
2630         if (wlc_hw->mac_suspend_depth > 1)
2631                 return;
2632
2633         /* force the core awake */
2634         brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2635
2636         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2637
2638         if (mc == 0xffffffff) {
2639                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2640                           __func__);
2641                 brcms_down(wlc->wl);
2642                 return;
2643         }
2644         WARN_ON(mc & MCTL_PSM_JMP_0);
2645         WARN_ON(!(mc & MCTL_PSM_RUN));
2646         WARN_ON(!(mc & MCTL_EN_MAC));
2647
2648         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2649         if (mi == 0xffffffff) {
2650                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2651                           __func__);
2652                 brcms_down(wlc->wl);
2653                 return;
2654         }
2655         WARN_ON(mi & MI_MACSSPNDD);
2656
2657         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2658
2659         SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2660                  BRCMS_MAX_MAC_SUSPEND);
2661
2662         if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2663                 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2664                           " and MI_MACSSPNDD is still not on.\n",
2665                           wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2666                 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2667                           "psm_brc 0x%04x\n", wlc_hw->unit,
2668                           bcma_read32(core, D11REGOFFS(psmdebug)),
2669                           bcma_read32(core, D11REGOFFS(phydebug)),
2670                           bcma_read16(core, D11REGOFFS(psm_brc)));
2671         }
2672
2673         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2674         if (mc == 0xffffffff) {
2675                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2676                           __func__);
2677                 brcms_down(wlc->wl);
2678                 return;
2679         }
2680         WARN_ON(mc & MCTL_PSM_JMP_0);
2681         WARN_ON(!(mc & MCTL_PSM_RUN));
2682         WARN_ON(mc & MCTL_EN_MAC);
2683 }
2684
2685 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2686 {
2687         struct brcms_hardware *wlc_hw = wlc->hw;
2688         struct bcma_device *core = wlc_hw->d11core;
2689         u32 mc, mi;
2690
2691         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2692                            wlc->band->bandunit);
2693
2694         /*
2695          * Track overlapping suspend requests
2696          */
2697         wlc_hw->mac_suspend_depth--;
2698         if (wlc_hw->mac_suspend_depth > 0)
2699                 return;
2700
2701         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2702         WARN_ON(mc & MCTL_PSM_JMP_0);
2703         WARN_ON(mc & MCTL_EN_MAC);
2704         WARN_ON(!(mc & MCTL_PSM_RUN));
2705
2706         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2707         bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2708
2709         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2710         WARN_ON(mc & MCTL_PSM_JMP_0);
2711         WARN_ON(!(mc & MCTL_EN_MAC));
2712         WARN_ON(!(mc & MCTL_PSM_RUN));
2713
2714         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2715         WARN_ON(mi & MI_MACSSPNDD);
2716
2717         brcms_c_ucode_wake_override_clear(wlc_hw,
2718                                           BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2719 }
2720
2721 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2722 {
2723         wlc_hw->hw_stf_ss_opmode = stf_mode;
2724
2725         if (wlc_hw->clk)
2726                 brcms_upd_ofdm_pctl1_table(wlc_hw);
2727 }
2728
2729 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2730 {
2731         struct bcma_device *core = wlc_hw->d11core;
2732         u32 w, val;
2733         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2734
2735         /* Validate dchip register access */
2736
2737         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2738         (void)bcma_read32(core, D11REGOFFS(objaddr));
2739         w = bcma_read32(core, D11REGOFFS(objdata));
2740
2741         /* Can we write and read back a 32bit register? */
2742         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2743         (void)bcma_read32(core, D11REGOFFS(objaddr));
2744         bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2745
2746         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2747         (void)bcma_read32(core, D11REGOFFS(objaddr));
2748         val = bcma_read32(core, D11REGOFFS(objdata));
2749         if (val != (u32) 0xaa5555aa) {
2750                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2751                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
2752                 return false;
2753         }
2754
2755         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2756         (void)bcma_read32(core, D11REGOFFS(objaddr));
2757         bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2758
2759         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2760         (void)bcma_read32(core, D11REGOFFS(objaddr));
2761         val = bcma_read32(core, D11REGOFFS(objdata));
2762         if (val != (u32) 0x55aaaa55) {
2763                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2764                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
2765                 return false;
2766         }
2767
2768         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2769         (void)bcma_read32(core, D11REGOFFS(objaddr));
2770         bcma_write32(core, D11REGOFFS(objdata), w);
2771
2772         /* clear CFPStart */
2773         bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2774
2775         w = bcma_read32(core, D11REGOFFS(maccontrol));
2776         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2777             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2778                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2779                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2780                           (MCTL_IHR_EN | MCTL_WAKE),
2781                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2782                 return false;
2783         }
2784
2785         return true;
2786 }
2787
2788 #define PHYPLL_WAIT_US  100000
2789
2790 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2791 {
2792         struct bcma_device *core = wlc_hw->d11core;
2793         u32 tmp;
2794
2795         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2796
2797         tmp = 0;
2798
2799         if (on) {
2800                 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2801                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2802                                    CCS_ERSRC_REQ_HT |
2803                                    CCS_ERSRC_REQ_D11PLL |
2804                                    CCS_ERSRC_REQ_PHYPLL);
2805                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2806                                   CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2807                                  PHYPLL_WAIT_US);
2808
2809                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2810                         if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2811                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2812                                           __func__);
2813                 } else {
2814                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2815                                    tmp | CCS_ERSRC_REQ_D11PLL |
2816                                    CCS_ERSRC_REQ_PHYPLL);
2817                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2818                                   (CCS_ERSRC_AVAIL_D11PLL |
2819                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
2820                                  (CCS_ERSRC_AVAIL_D11PLL |
2821                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2822
2823                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2824                         if ((tmp &
2825                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2826                             !=
2827                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2828                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2829                                           __func__);
2830                 }
2831         } else {
2832                 /*
2833                  * Since the PLL may be shared, other cores can still
2834                  * be requesting it; so we'll deassert the request but
2835                  * not wait for status to comply.
2836                  */
2837                 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2838                             ~CCS_ERSRC_REQ_PHYPLL);
2839                 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2840         }
2841 }
2842
2843 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2844 {
2845         bool dev_gone;
2846
2847         brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2848
2849         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2850
2851         if (dev_gone)
2852                 return;
2853
2854         if (wlc_hw->noreset)
2855                 return;
2856
2857         /* radio off */
2858         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2859
2860         /* turn off analog core */
2861         wlc_phy_anacore(wlc_hw->band->pi, OFF);
2862
2863         /* turn off PHYPLL to save power */
2864         brcms_b_core_phypll_ctl(wlc_hw, false);
2865
2866         wlc_hw->clk = false;
2867         bcma_core_disable(wlc_hw->d11core, 0);
2868         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2869 }
2870
2871 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2872 {
2873         struct brcms_hardware *wlc_hw = wlc->hw;
2874         uint i;
2875
2876         /* free any posted tx packets */
2877         for (i = 0; i < NFIFO; i++) {
2878                 if (wlc_hw->di[i]) {
2879                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2880                         if (i < TX_BCMC_FIFO)
2881                                 ieee80211_wake_queue(wlc->pub->ieee_hw,
2882                                                      brcms_fifo_to_ac(i));
2883                 }
2884         }
2885
2886         /* free any posted rx packets */
2887         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2888 }
2889
2890 static u16
2891 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2892 {
2893         struct bcma_device *core = wlc_hw->d11core;
2894         u16 objoff = D11REGOFFS(objdata);
2895
2896         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2897         (void)bcma_read32(core, D11REGOFFS(objaddr));
2898         if (offset & 2)
2899                 objoff += 2;
2900
2901         return bcma_read16(core, objoff);
2902 }
2903
2904 static void
2905 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2906                      u32 sel)
2907 {
2908         struct bcma_device *core = wlc_hw->d11core;
2909         u16 objoff = D11REGOFFS(objdata);
2910
2911         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2912         (void)bcma_read32(core, D11REGOFFS(objaddr));
2913         if (offset & 2)
2914                 objoff += 2;
2915
2916         bcma_wflush16(core, objoff, v);
2917 }
2918
2919 /*
2920  * Read a single u16 from shared memory.
2921  * SHM 'offset' needs to be an even address
2922  */
2923 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2924 {
2925         return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2926 }
2927
2928 /*
2929  * Write a single u16 to shared memory.
2930  * SHM 'offset' needs to be an even address
2931  */
2932 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2933 {
2934         brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2935 }
2936
2937 /*
2938  * Copy a buffer to shared memory of specified type .
2939  * SHM 'offset' needs to be an even address and
2940  * Buffer length 'len' must be an even number of bytes
2941  * 'sel' selects the type of memory
2942  */
2943 void
2944 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2945                       const void *buf, int len, u32 sel)
2946 {
2947         u16 v;
2948         const u8 *p = (const u8 *)buf;
2949         int i;
2950
2951         if (len <= 0 || (offset & 1) || (len & 1))
2952                 return;
2953
2954         for (i = 0; i < len; i += 2) {
2955                 v = p[i] | (p[i + 1] << 8);
2956                 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2957         }
2958 }
2959
2960 /*
2961  * Copy a piece of shared memory of specified type to a buffer .
2962  * SHM 'offset' needs to be an even address and
2963  * Buffer length 'len' must be an even number of bytes
2964  * 'sel' selects the type of memory
2965  */
2966 void
2967 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2968                          int len, u32 sel)
2969 {
2970         u16 v;
2971         u8 *p = (u8 *) buf;
2972         int i;
2973
2974         if (len <= 0 || (offset & 1) || (len & 1))
2975                 return;
2976
2977         for (i = 0; i < len; i += 2) {
2978                 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2979                 p[i] = v & 0xFF;
2980                 p[i + 1] = (v >> 8) & 0xFF;
2981         }
2982 }
2983
2984 /* Copy a buffer to shared memory.
2985  * SHM 'offset' needs to be an even address and
2986  * Buffer length 'len' must be an even number of bytes
2987  */
2988 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2989                         const void *buf, int len)
2990 {
2991         brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2992 }
2993
2994 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
2995                                    u16 SRL, u16 LRL)
2996 {
2997         wlc_hw->SRL = SRL;
2998         wlc_hw->LRL = LRL;
2999
3000         /* write retry limit to SCR, shouldn't need to suspend */
3001         if (wlc_hw->up) {
3002                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3003                              OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3004                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3005                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3006                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3007                              OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3008                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3009                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3010         }
3011 }
3012
3013 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3014 {
3015         if (set) {
3016                 if (mboolisset(wlc_hw->pllreq, req_bit))
3017                         return;
3018
3019                 mboolset(wlc_hw->pllreq, req_bit);
3020
3021                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3022                         if (!wlc_hw->sbclk)
3023                                 brcms_b_xtal(wlc_hw, ON);
3024                 }
3025         } else {
3026                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3027                         return;
3028
3029                 mboolclr(wlc_hw->pllreq, req_bit);
3030
3031                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3032                         if (wlc_hw->sbclk)
3033                                 brcms_b_xtal(wlc_hw, OFF);
3034                 }
3035         }
3036 }
3037
3038 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3039 {
3040         wlc_hw->antsel_avail = antsel_avail;
3041 }
3042
3043 /*
3044  * conditions under which the PM bit should be set in outgoing frames
3045  * and STAY_AWAKE is meaningful
3046  */
3047 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3048 {
3049         struct brcms_bss_cfg *cfg = wlc->bsscfg;
3050
3051         /* disallow PS when one of the following global conditions meets */
3052         if (!wlc->pub->associated)
3053                 return false;
3054
3055         /* disallow PS when one of these meets when not scanning */
3056         if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3057                 return false;
3058
3059         if (cfg->associated) {
3060                 /*
3061                  * disallow PS when one of the following
3062                  * bsscfg specific conditions meets
3063                  */
3064                 if (!cfg->BSS)
3065                         return false;
3066
3067                 return false;
3068         }
3069
3070         return true;
3071 }
3072
3073 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3074 {
3075         int i;
3076         struct macstat macstats;
3077 #ifdef DEBUG
3078         u16 delta;
3079         u16 rxf0ovfl;
3080         u16 txfunfl[NFIFO];
3081 #endif                          /* DEBUG */
3082
3083         /* if driver down, make no sense to update stats */
3084         if (!wlc->pub->up)
3085                 return;
3086
3087 #ifdef DEBUG
3088         /* save last rx fifo 0 overflow count */
3089         rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3090
3091         /* save last tx fifo  underflow count */
3092         for (i = 0; i < NFIFO; i++)
3093                 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3094 #endif                          /* DEBUG */
3095
3096         /* Read mac stats from contiguous shared memory */
3097         brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3098           &