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1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  *  Intel Linux Wireless <ilw@linux.intel.com>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
41
42 #include "common.h"
43 #include "3945.h"
44
45 /* Send led command */
46 static int
47 il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd)
48 {
49         struct il_host_cmd cmd = {
50                 .id = C_LEDS,
51                 .len = sizeof(struct il_led_cmd),
52                 .data = led_cmd,
53                 .flags = CMD_ASYNC,
54                 .callback = NULL,
55         };
56
57         return il_send_cmd(il, &cmd);
58 }
59
60 const struct il_led_ops il3945_led_ops = {
61         .cmd = il3945_send_led_cmd,
62 };
63
64 #define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
65         [RATE_##r##M_IDX] = { RATE_##r##M_PLCP,   \
66                                     RATE_##r##M_IEEE,   \
67                                     RATE_##ip##M_IDX, \
68                                     RATE_##in##M_IDX, \
69                                     RATE_##rp##M_IDX, \
70                                     RATE_##rn##M_IDX, \
71                                     RATE_##pp##M_IDX, \
72                                     RATE_##np##M_IDX, \
73                                     RATE_##r##M_IDX_TBL, \
74                                     RATE_##ip##M_IDX_TBL }
75
76 /*
77  * Parameter order:
78  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
79  *
80  * If there isn't a valid next or previous rate then INV is used which
81  * maps to RATE_INVALID
82  *
83  */
84 const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = {
85         IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),        /*  1mbps */
86         IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),      /*  2mbps */
87         IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),    /*5.5mbps */
88         IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),  /* 11mbps */
89         IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),    /*  6mbps */
90         IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),   /*  9mbps */
91         IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),       /* 12mbps */
92         IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),       /* 18mbps */
93         IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),       /* 24mbps */
94         IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),       /* 36mbps */
95         IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),       /* 48mbps */
96         IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),    /* 54mbps */
97 };
98
99 static inline u8
100 il3945_get_prev_ieee_rate(u8 rate_idx)
101 {
102         u8 rate = il3945_rates[rate_idx].prev_ieee;
103
104         if (rate == RATE_INVALID)
105                 rate = rate_idx;
106         return rate;
107 }
108
109 /* 1 = enable the il3945_disable_events() function */
110 #define IL_EVT_DISABLE (0)
111 #define IL_EVT_DISABLE_SIZE (1532/32)
112
113 /**
114  * il3945_disable_events - Disable selected events in uCode event log
115  *
116  * Disable an event by writing "1"s into "disable"
117  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
118  *   Default values of 0 enable uCode events to be logged.
119  * Use for only special debugging.  This function is just a placeholder as-is,
120  *   you'll need to provide the special bits! ...
121  *   ... and set IL_EVT_DISABLE to 1. */
122 void
123 il3945_disable_events(struct il_priv *il)
124 {
125         int i;
126         u32 base;               /* SRAM address of event log header */
127         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
128         u32 array_size;         /* # of u32 entries in array */
129         static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = {
130                 0x00000000,     /*   31 -    0  Event id numbers */
131                 0x00000000,     /*   63 -   32 */
132                 0x00000000,     /*   95 -   64 */
133                 0x00000000,     /*  127 -   96 */
134                 0x00000000,     /*  159 -  128 */
135                 0x00000000,     /*  191 -  160 */
136                 0x00000000,     /*  223 -  192 */
137                 0x00000000,     /*  255 -  224 */
138                 0x00000000,     /*  287 -  256 */
139                 0x00000000,     /*  319 -  288 */
140                 0x00000000,     /*  351 -  320 */
141                 0x00000000,     /*  383 -  352 */
142                 0x00000000,     /*  415 -  384 */
143                 0x00000000,     /*  447 -  416 */
144                 0x00000000,     /*  479 -  448 */
145                 0x00000000,     /*  511 -  480 */
146                 0x00000000,     /*  543 -  512 */
147                 0x00000000,     /*  575 -  544 */
148                 0x00000000,     /*  607 -  576 */
149                 0x00000000,     /*  639 -  608 */
150                 0x00000000,     /*  671 -  640 */
151                 0x00000000,     /*  703 -  672 */
152                 0x00000000,     /*  735 -  704 */
153                 0x00000000,     /*  767 -  736 */
154                 0x00000000,     /*  799 -  768 */
155                 0x00000000,     /*  831 -  800 */
156                 0x00000000,     /*  863 -  832 */
157                 0x00000000,     /*  895 -  864 */
158                 0x00000000,     /*  927 -  896 */
159                 0x00000000,     /*  959 -  928 */
160                 0x00000000,     /*  991 -  960 */
161                 0x00000000,     /* 1023 -  992 */
162                 0x00000000,     /* 1055 - 1024 */
163                 0x00000000,     /* 1087 - 1056 */
164                 0x00000000,     /* 1119 - 1088 */
165                 0x00000000,     /* 1151 - 1120 */
166                 0x00000000,     /* 1183 - 1152 */
167                 0x00000000,     /* 1215 - 1184 */
168                 0x00000000,     /* 1247 - 1216 */
169                 0x00000000,     /* 1279 - 1248 */
170                 0x00000000,     /* 1311 - 1280 */
171                 0x00000000,     /* 1343 - 1312 */
172                 0x00000000,     /* 1375 - 1344 */
173                 0x00000000,     /* 1407 - 1376 */
174                 0x00000000,     /* 1439 - 1408 */
175                 0x00000000,     /* 1471 - 1440 */
176                 0x00000000,     /* 1503 - 1472 */
177         };
178
179         base = le32_to_cpu(il->card_alive.log_event_table_ptr);
180         if (!il3945_hw_valid_rtc_data_addr(base)) {
181                 IL_ERR("Invalid event log pointer 0x%08X\n", base);
182                 return;
183         }
184
185         disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32)));
186         array_size = il_read_targ_mem(il, base + (5 * sizeof(u32)));
187
188         if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) {
189                 D_INFO("Disabling selected uCode log events at 0x%x\n",
190                        disable_ptr);
191                 for (i = 0; i < IL_EVT_DISABLE_SIZE; i++)
192                         il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)),
193                                           evt_disable[i]);
194
195         } else {
196                 D_INFO("Selected uCode log events may be disabled\n");
197                 D_INFO("  by writing \"1\"s into disable bitmap\n");
198                 D_INFO("  in SRAM at 0x%x, size %d u32s\n", disable_ptr,
199                        array_size);
200         }
201
202 }
203
204 static int
205 il3945_hwrate_to_plcp_idx(u8 plcp)
206 {
207         int idx;
208
209         for (idx = 0; idx < RATE_COUNT_3945; idx++)
210                 if (il3945_rates[idx].plcp == plcp)
211                         return idx;
212         return -1;
213 }
214
215 #ifdef CONFIG_IWLEGACY_DEBUG
216 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
217
218 static const char *
219 il3945_get_tx_fail_reason(u32 status)
220 {
221         switch (status & TX_STATUS_MSK) {
222         case TX_3945_STATUS_SUCCESS:
223                 return "SUCCESS";
224                 TX_STATUS_ENTRY(SHORT_LIMIT);
225                 TX_STATUS_ENTRY(LONG_LIMIT);
226                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
227                 TX_STATUS_ENTRY(MGMNT_ABORT);
228                 TX_STATUS_ENTRY(NEXT_FRAG);
229                 TX_STATUS_ENTRY(LIFE_EXPIRE);
230                 TX_STATUS_ENTRY(DEST_PS);
231                 TX_STATUS_ENTRY(ABORTED);
232                 TX_STATUS_ENTRY(BT_RETRY);
233                 TX_STATUS_ENTRY(STA_INVALID);
234                 TX_STATUS_ENTRY(FRAG_DROPPED);
235                 TX_STATUS_ENTRY(TID_DISABLE);
236                 TX_STATUS_ENTRY(FRAME_FLUSHED);
237                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
238                 TX_STATUS_ENTRY(TX_LOCKED);
239                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
240         }
241
242         return "UNKNOWN";
243 }
244 #else
245 static inline const char *
246 il3945_get_tx_fail_reason(u32 status)
247 {
248         return "";
249 }
250 #endif
251
252 /*
253  * get ieee prev rate from rate scale table.
254  * for A and B mode we need to overright prev
255  * value
256  */
257 int
258 il3945_rs_next_rate(struct il_priv *il, int rate)
259 {
260         int next_rate = il3945_get_prev_ieee_rate(rate);
261
262         switch (il->band) {
263         case IEEE80211_BAND_5GHZ:
264                 if (rate == RATE_12M_IDX)
265                         next_rate = RATE_9M_IDX;
266                 else if (rate == RATE_6M_IDX)
267                         next_rate = RATE_6M_IDX;
268                 break;
269         case IEEE80211_BAND_2GHZ:
270                 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
271                     il_is_associated(il)) {
272                         if (rate == RATE_11M_IDX)
273                                 next_rate = RATE_5M_IDX;
274                 }
275                 break;
276
277         default:
278                 break;
279         }
280
281         return next_rate;
282 }
283
284 /**
285  * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
286  *
287  * When FW advances 'R' idx, all entries between old and new 'R' idx
288  * need to be reclaimed. As result, some free space forms. If there is
289  * enough free space (> low mark), wake the stack that feeds us.
290  */
291 static void
292 il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
293 {
294         struct il_tx_queue *txq = &il->txq[txq_id];
295         struct il_queue *q = &txq->q;
296         struct il_tx_info *tx_info;
297
298         BUG_ON(txq_id == IL39_CMD_QUEUE_NUM);
299
300         for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
301              q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
302
303                 tx_info = &txq->txb[txq->q.read_ptr];
304                 ieee80211_tx_status_irqsafe(il->hw, tx_info->skb);
305                 tx_info->skb = NULL;
306                 il->cfg->ops->lib->txq_free_tfd(il, txq);
307         }
308
309         if (il_queue_space(q) > q->low_mark && txq_id >= 0 &&
310             txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
311                 il_wake_queue(il, txq);
312 }
313
314 /**
315  * il3945_hdl_tx - Handle Tx response
316  */
317 static void
318 il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
319 {
320         struct il_rx_pkt *pkt = rxb_addr(rxb);
321         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
322         int txq_id = SEQ_TO_QUEUE(sequence);
323         int idx = SEQ_TO_IDX(sequence);
324         struct il_tx_queue *txq = &il->txq[txq_id];
325         struct ieee80211_tx_info *info;
326         struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
327         u32 status = le32_to_cpu(tx_resp->status);
328         int rate_idx;
329         int fail;
330
331         if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
332                 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
333                        "is out of range [0-%d] %d %d\n", txq_id, idx,
334                        txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
335                 return;
336         }
337
338         txq->time_stamp = jiffies;
339         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
340         ieee80211_tx_info_clear_status(info);
341
342         /* Fill the MRR chain with some info about on-chip retransmissions */
343         rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate);
344         if (info->band == IEEE80211_BAND_5GHZ)
345                 rate_idx -= IL_FIRST_OFDM_RATE;
346
347         fail = tx_resp->failure_frame;
348
349         info->status.rates[0].idx = rate_idx;
350         info->status.rates[0].count = fail + 1; /* add final attempt */
351
352         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
353         info->flags |=
354             ((status & TX_STATUS_MSK) ==
355              TX_STATUS_SUCCESS) ? IEEE80211_TX_STAT_ACK : 0;
356
357         D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id,
358              il3945_get_tx_fail_reason(status), status, tx_resp->rate,
359              tx_resp->failure_frame);
360
361         D_TX_REPLY("Tx queue reclaim %d\n", idx);
362         il3945_tx_queue_reclaim(il, txq_id, idx);
363
364         if (status & TX_ABORT_REQUIRED_MSK)
365                 IL_ERR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
366 }
367
368 /*****************************************************************************
369  *
370  * Intel PRO/Wireless 3945ABG/BG Network Connection
371  *
372  *  RX handler implementations
373  *
374  *****************************************************************************/
375 #ifdef CONFIG_IWLEGACY_DEBUGFS
376 static void
377 il3945_accumulative_stats(struct il_priv *il, __le32 * stats)
378 {
379         int i;
380         __le32 *prev_stats;
381         u32 *accum_stats;
382         u32 *delta, *max_delta;
383
384         prev_stats = (__le32 *) &il->_3945.stats;
385         accum_stats = (u32 *) &il->_3945.accum_stats;
386         delta = (u32 *) &il->_3945.delta_stats;
387         max_delta = (u32 *) &il->_3945.max_delta;
388
389         for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats);
390              i +=
391              sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
392              accum_stats++) {
393                 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
394                         *delta =
395                             (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
396                         *accum_stats += *delta;
397                         if (*delta > *max_delta)
398                                 *max_delta = *delta;
399                 }
400         }
401
402         /* reset accumulative stats for "no-counter" type stats */
403         il->_3945.accum_stats.general.temperature =
404             il->_3945.stats.general.temperature;
405         il->_3945.accum_stats.general.ttl_timestamp =
406             il->_3945.stats.general.ttl_timestamp;
407 }
408 #endif
409
410 void
411 il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
412 {
413         struct il_rx_pkt *pkt = rxb_addr(rxb);
414
415         D_RX("Statistics notification received (%d vs %d).\n",
416              (int)sizeof(struct il3945_notif_stats),
417              le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
418 #ifdef CONFIG_IWLEGACY_DEBUGFS
419         il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw);
420 #endif
421
422         memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats));
423 }
424
425 void
426 il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
427 {
428         struct il_rx_pkt *pkt = rxb_addr(rxb);
429         __le32 *flag = (__le32 *) &pkt->u.raw;
430
431         if (le32_to_cpu(*flag) & UCODE_STATS_CLEAR_MSK) {
432 #ifdef CONFIG_IWLEGACY_DEBUGFS
433                 memset(&il->_3945.accum_stats, 0,
434                        sizeof(struct il3945_notif_stats));
435                 memset(&il->_3945.delta_stats, 0,
436                        sizeof(struct il3945_notif_stats));
437                 memset(&il->_3945.max_delta, 0,
438                        sizeof(struct il3945_notif_stats));
439 #endif
440                 D_RX("Statistics have been cleared\n");
441         }
442         il3945_hdl_stats(il, rxb);
443 }
444
445 /******************************************************************************
446  *
447  * Misc. internal state and helper functions
448  *
449  ******************************************************************************/
450
451 /* This is necessary only for a number of stats, see the caller. */
452 static int
453 il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header)
454 {
455         /* Filter incoming packets to determine if they are targeted toward
456          * this network, discarding packets coming from ourselves */
457         switch (il->iw_mode) {
458         case NL80211_IFTYPE_ADHOC:      /* Header: Dest. | Source    | BSSID */
459                 /* packets to our IBSS update information */
460                 return !compare_ether_addr(header->addr3, il->bssid);
461         case NL80211_IFTYPE_STATION:    /* Header: Dest. | AP{BSSID} | Source */
462                 /* packets to our IBSS update information */
463                 return !compare_ether_addr(header->addr2, il->bssid);
464         default:
465                 return 1;
466         }
467 }
468
469 static void
470 il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb,
471                                struct ieee80211_rx_status *stats)
472 {
473         struct il_rx_pkt *pkt = rxb_addr(rxb);
474         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
475         struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
476         struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
477         u16 len = le16_to_cpu(rx_hdr->len);
478         struct sk_buff *skb;
479         __le16 fc = hdr->frame_control;
480
481         /* We received data from the HW, so stop the watchdog */
482         if (unlikely
483             (len + IL39_RX_FRAME_SIZE >
484              PAGE_SIZE << il->hw_params.rx_page_order)) {
485                 D_DROP("Corruption detected!\n");
486                 return;
487         }
488
489         /* We only process data packets if the interface is open */
490         if (unlikely(!il->is_open)) {
491                 D_DROP("Dropping packet while interface is not open.\n");
492                 return;
493         }
494
495         skb = dev_alloc_skb(128);
496         if (!skb) {
497                 IL_ERR("dev_alloc_skb failed\n");
498                 return;
499         }
500
501         if (!il3945_mod_params.sw_crypto)
502                 il_set_decrypted_flag(il, (struct ieee80211_hdr *)rxb_addr(rxb),
503                                       le32_to_cpu(rx_end->status), stats);
504
505         skb_add_rx_frag(skb, 0, rxb->page,
506                         (void *)rx_hdr->payload - (void *)pkt, len);
507
508         il_update_stats(il, false, fc, len);
509         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
510
511         ieee80211_rx(il->hw, skb);
512         il->alloc_rxb_page--;
513         rxb->page = NULL;
514 }
515
516 #define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
517
518 static void
519 il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
520 {
521         struct ieee80211_hdr *header;
522         struct ieee80211_rx_status rx_status;
523         struct il_rx_pkt *pkt = rxb_addr(rxb);
524         struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt);
525         struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
526         struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
527         u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
528         u16 rx_stats_noise_diff __maybe_unused =
529             le16_to_cpu(rx_stats->noise_diff);
530         u8 network_packet;
531
532         rx_status.flag = 0;
533         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
534         rx_status.band =
535             (rx_hdr->
536              phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
537             IEEE80211_BAND_5GHZ;
538         rx_status.freq =
539             ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
540                                            rx_status.band);
541
542         rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate);
543         if (rx_status.band == IEEE80211_BAND_5GHZ)
544                 rx_status.rate_idx -= IL_FIRST_OFDM_RATE;
545
546         rx_status.antenna =
547             (le16_to_cpu(rx_hdr->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
548             4;
549
550         /* set the preamble flag if appropriate */
551         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
552                 rx_status.flag |= RX_FLAG_SHORTPRE;
553
554         if ((unlikely(rx_stats->phy_count > 20))) {
555                 D_DROP("dsp size out of range [0,20]: %d/n",
556                        rx_stats->phy_count);
557                 return;
558         }
559
560         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) ||
561             !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
562                 D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
563                 return;
564         }
565
566         /* Convert 3945's rssi indicator to dBm */
567         rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET;
568
569         D_STATS("Rssi %d sig_avg %d noise_diff %d\n", rx_status.signal,
570                 rx_stats_sig_avg, rx_stats_noise_diff);
571
572         header = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
573
574         network_packet = il3945_is_network_packet(il, header);
575
576         D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
577                 network_packet ? '*' : ' ', le16_to_cpu(rx_hdr->channel),
578                 rx_status.signal, rx_status.signal, rx_status.rate_idx);
579
580         il_dbg_log_rx_data_frame(il, le16_to_cpu(rx_hdr->len), header);
581
582         if (network_packet) {
583                 il->_3945.last_beacon_time =
584                     le32_to_cpu(rx_end->beacon_timestamp);
585                 il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
586                 il->_3945.last_rx_rssi = rx_status.signal;
587         }
588
589         il3945_pass_packet_to_mac80211(il, rxb, &rx_status);
590 }
591
592 int
593 il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
594                                 dma_addr_t addr, u16 len, u8 reset, u8 pad)
595 {
596         int count;
597         struct il_queue *q;
598         struct il3945_tfd *tfd, *tfd_tmp;
599
600         q = &txq->q;
601         tfd_tmp = (struct il3945_tfd *)txq->tfds;
602         tfd = &tfd_tmp[q->write_ptr];
603
604         if (reset)
605                 memset(tfd, 0, sizeof(*tfd));
606
607         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
608
609         if (count >= NUM_TFD_CHUNKS || count < 0) {
610                 IL_ERR("Error can not send more than %d chunks\n",
611                        NUM_TFD_CHUNKS);
612                 return -EINVAL;
613         }
614
615         tfd->tbs[count].addr = cpu_to_le32(addr);
616         tfd->tbs[count].len = cpu_to_le32(len);
617
618         count++;
619
620         tfd->control_flags =
621             cpu_to_le32(TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad));
622
623         return 0;
624 }
625
626 /**
627  * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr]
628  *
629  * Does NOT advance any idxes
630  */
631 void
632 il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
633 {
634         struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds;
635         int idx = txq->q.read_ptr;
636         struct il3945_tfd *tfd = &tfd_tmp[idx];
637         struct pci_dev *dev = il->pci_dev;
638         int i;
639         int counter;
640
641         /* sanity check */
642         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
643         if (counter > NUM_TFD_CHUNKS) {
644                 IL_ERR("Too many chunks: %i\n", counter);
645                 /* @todo issue fatal error, it is quite serious situation */
646                 return;
647         }
648
649         /* Unmap tx_cmd */
650         if (counter)
651                 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
652                                  dma_unmap_len(&txq->meta[idx], len),
653                                  PCI_DMA_TODEVICE);
654
655         /* unmap chunks if any */
656
657         for (i = 1; i < counter; i++)
658                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
659                                  le32_to_cpu(tfd->tbs[i].len),
660                                  PCI_DMA_TODEVICE);
661
662         /* free SKB */
663         if (txq->txb) {
664                 struct sk_buff *skb;
665
666                 skb = txq->txb[txq->q.read_ptr].skb;
667
668                 /* can be called from irqs-disabled context */
669                 if (skb) {
670                         dev_kfree_skb_any(skb);
671                         txq->txb[txq->q.read_ptr].skb = NULL;
672                 }
673         }
674 }
675
676 /**
677  * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
678  *
679 */
680 void
681 il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
682                             struct ieee80211_tx_info *info,
683                             struct ieee80211_hdr *hdr, int sta_id, int tx_id)
684 {
685         u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value;
686         u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945);
687         u16 rate_mask;
688         int rate;
689         u8 rts_retry_limit;
690         u8 data_retry_limit;
691         __le32 tx_flags;
692         __le16 fc = hdr->frame_control;
693         struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
694
695         rate = il3945_rates[rate_idx].plcp;
696         tx_flags = tx_cmd->tx_flags;
697
698         /* We need to figure out how to get the sta->supp_rates while
699          * in this running context */
700         rate_mask = RATES_MASK_3945;
701
702         /* Set retry limit on DATA packets and Probe Responses */
703         if (ieee80211_is_probe_resp(fc))
704                 data_retry_limit = 3;
705         else
706                 data_retry_limit = IL_DEFAULT_TX_RETRY;
707         tx_cmd->data_retry_limit = data_retry_limit;
708
709         if (tx_id >= IL39_CMD_QUEUE_NUM)
710                 rts_retry_limit = 3;
711         else
712                 rts_retry_limit = 7;
713
714         if (data_retry_limit < rts_retry_limit)
715                 rts_retry_limit = data_retry_limit;
716         tx_cmd->rts_retry_limit = rts_retry_limit;
717
718         tx_cmd->rate = rate;
719         tx_cmd->tx_flags = tx_flags;
720
721         /* OFDM */
722         tx_cmd->supp_rates[0] =
723             ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF;
724
725         /* CCK */
726         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
727
728         D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
729                "cck/ofdm mask: 0x%x/0x%x\n", sta_id, tx_cmd->rate,
730                le32_to_cpu(tx_cmd->tx_flags), tx_cmd->supp_rates[1],
731                tx_cmd->supp_rates[0]);
732 }
733
734 static u8
735 il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate)
736 {
737         unsigned long flags_spin;
738         struct il_station_entry *station;
739
740         if (sta_id == IL_INVALID_STATION)
741                 return IL_INVALID_STATION;
742
743         spin_lock_irqsave(&il->sta_lock, flags_spin);
744         station = &il->stations[sta_id];
745
746         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
747         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
748         station->sta.mode = STA_CONTROL_MODIFY_MSK;
749         il_send_add_sta(il, &station->sta, CMD_ASYNC);
750         spin_unlock_irqrestore(&il->sta_lock, flags_spin);
751
752         D_RATE("SCALE sync station %d to rate %d\n", sta_id, tx_rate);
753         return sta_id;
754 }
755
756 static void
757 il3945_set_pwr_vmain(struct il_priv *il)
758 {
759 /*
760  * (for documentation purposes)
761  * to set power to V_AUX, do
762
763                 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) {
764                         il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
765                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
766                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
767
768                         _il_poll_bit(il, CSR_GPIO_IN,
769                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
770                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
771                 }
772  */
773
774         il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
775                               APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
776                               ~APMG_PS_CTRL_MSK_PWR_SRC);
777
778         _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
779                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
780 }
781
782 static int
783 il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
784 {
785         il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
786         il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
787         il_wr(il, FH39_RCSR_WPTR(0), 0);
788         il_wr(il, FH39_RCSR_CONFIG(0),
789               FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
790               FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
791               FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
792               FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | (RX_QUEUE_SIZE_LOG
793                                                                <<
794                                                                FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE)
795               | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | (1 <<
796                                                                  FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH)
797               | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
798
799         /* fake read to flush all prev I/O */
800         il_rd(il, FH39_RSSR_CTRL);
801
802         return 0;
803 }
804
805 static int
806 il3945_tx_reset(struct il_priv *il)
807 {
808
809         /* bypass mode */
810         il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
811
812         /* RA 0 is active */
813         il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
814
815         /* all 6 fifo are active */
816         il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
817
818         il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
819         il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
820         il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
821         il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
822
823         il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys);
824
825         il_wr(il, FH39_TSSR_MSG_CONFIG,
826               FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
827               FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
828               FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
829               FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
830               FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
831               FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
832               FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
833
834         return 0;
835 }
836
837 /**
838  * il3945_txq_ctx_reset - Reset TX queue context
839  *
840  * Destroys all DMA structures and initialize them again
841  */
842 static int
843 il3945_txq_ctx_reset(struct il_priv *il)
844 {
845         int rc;
846         int txq_id, slots_num;
847
848         il3945_hw_txq_ctx_free(il);
849
850         /* allocate tx queue structure */
851         rc = il_alloc_txq_mem(il);
852         if (rc)
853                 return rc;
854
855         /* Tx CMD queue */
856         rc = il3945_tx_reset(il);
857         if (rc)
858                 goto error;
859
860         /* Tx queue(s) */
861         for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
862                 slots_num =
863                     (txq_id ==
864                      IL39_CMD_QUEUE_NUM) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
865                 rc = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id);
866                 if (rc) {
867                         IL_ERR("Tx %d queue init failed\n", txq_id);
868                         goto error;
869                 }
870         }
871
872         return rc;
873
874 error:
875         il3945_hw_txq_ctx_free(il);
876         return rc;
877 }
878
879 /*
880  * Start up 3945's basic functionality after it has been reset
881  * (e.g. after platform boot, or shutdown via il_apm_stop())
882  * NOTE:  This does not load uCode nor start the embedded processor
883  */
884 static int
885 il3945_apm_init(struct il_priv *il)
886 {
887         int ret = il_apm_init(il);
888
889         /* Clear APMG (NIC's internal power management) interrupts */
890         il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
891         il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
892
893         /* Reset radio chip */
894         il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
895         udelay(5);
896         il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
897
898         return ret;
899 }
900
901 static void
902 il3945_nic_config(struct il_priv *il)
903 {
904         struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
905         unsigned long flags;
906         u8 rev_id = il->pci_dev->revision;
907
908         spin_lock_irqsave(&il->lock, flags);
909
910         /* Determine HW type */
911         D_INFO("HW Revision ID = 0x%X\n", rev_id);
912
913         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
914                 D_INFO("RTP type\n");
915         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
916                 D_INFO("3945 RADIO-MB type\n");
917                 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
918                            CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
919         } else {
920                 D_INFO("3945 RADIO-MM type\n");
921                 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
922                            CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
923         }
924
925         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
926                 D_INFO("SKU OP mode is mrc\n");
927                 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
928                            CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
929         } else
930                 D_INFO("SKU OP mode is basic\n");
931
932         if ((eeprom->board_revision & 0xF0) == 0xD0) {
933                 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
934                 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
935                            CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
936         } else {
937                 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
938                 il_clear_bit(il, CSR_HW_IF_CONFIG_REG,
939                              CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
940         }
941
942         if (eeprom->almgor_m_version <= 1) {
943                 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
944                            CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
945                 D_INFO("Card M type A version is 0x%X\n",
946                        eeprom->almgor_m_version);
947         } else {
948                 D_INFO("Card M type B version is 0x%X\n",
949                        eeprom->almgor_m_version);
950                 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
951                            CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
952         }
953         spin_unlock_irqrestore(&il->lock, flags);
954
955         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
956                 D_RF_KILL("SW RF KILL supported in EEPROM.\n");
957
958         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
959                 D_RF_KILL("HW RF KILL supported in EEPROM.\n");
960 }
961
962 int
963 il3945_hw_nic_init(struct il_priv *il)
964 {
965         int rc;
966         unsigned long flags;
967         struct il_rx_queue *rxq = &il->rxq;
968
969         spin_lock_irqsave(&il->lock, flags);
970         il->cfg->ops->lib->apm_ops.init(il);
971         spin_unlock_irqrestore(&il->lock, flags);
972
973         il3945_set_pwr_vmain(il);
974
975         il->cfg->ops->lib->apm_ops.config(il);
976
977         /* Allocate the RX queue, or reset if it is already allocated */
978         if (!rxq->bd) {
979                 rc = il_rx_queue_alloc(il);
980                 if (rc) {
981                         IL_ERR("Unable to initialize Rx queue\n");
982                         return -ENOMEM;
983                 }
984         } else
985                 il3945_rx_queue_reset(il, rxq);
986
987         il3945_rx_replenish(il);
988
989         il3945_rx_init(il, rxq);
990
991         /* Look at using this instead:
992            rxq->need_update = 1;
993            il_rx_queue_update_write_ptr(il, rxq);
994          */
995
996         il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
997
998         rc = il3945_txq_ctx_reset(il);
999         if (rc)
1000                 return rc;
1001
1002         set_bit(S_INIT, &il->status);
1003
1004         return 0;
1005 }
1006
1007 /**
1008  * il3945_hw_txq_ctx_free - Free TXQ Context
1009  *
1010  * Destroy all TX DMA queues and structures
1011  */
1012 void
1013 il3945_hw_txq_ctx_free(struct il_priv *il)
1014 {
1015         int txq_id;
1016
1017         /* Tx queues */
1018         if (il->txq)
1019                 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1020                         if (txq_id == IL39_CMD_QUEUE_NUM)
1021                                 il_cmd_queue_free(il);
1022                         else
1023                                 il_tx_queue_free(il, txq_id);
1024
1025         /* free tx queue structure */
1026         il_txq_mem(il);
1027 }
1028
1029 void
1030 il3945_hw_txq_ctx_stop(struct il_priv *il)
1031 {
1032         int txq_id;
1033
1034         /* stop SCD */
1035         il_wr_prph(il, ALM_SCD_MODE_REG, 0);
1036         il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
1037
1038         /* reset TFD queues */
1039         for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1040                 il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
1041                 il_poll_bit(il, FH39_TSSR_TX_STATUS,
1042                             FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1043                             1000);
1044         }
1045
1046         il3945_hw_txq_ctx_free(il);
1047 }
1048
1049 /**
1050  * il3945_hw_reg_adjust_power_by_temp
1051  * return idx delta into power gain settings table
1052 */
1053 static int
1054 il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1055 {
1056         return (new_reading - old_reading) * (-11) / 100;
1057 }
1058
1059 /**
1060  * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1061  */
1062 static inline int
1063 il3945_hw_reg_temp_out_of_range(int temperature)
1064 {
1065         return (temperature < -260 || temperature > 25) ? 1 : 0;
1066 }
1067
1068 int
1069 il3945_hw_get_temperature(struct il_priv *il)
1070 {
1071         return _il_rd(il, CSR_UCODE_DRV_GP2);
1072 }
1073
1074 /**
1075  * il3945_hw_reg_txpower_get_temperature
1076  * get the current temperature by reading from NIC
1077 */
1078 static int
1079 il3945_hw_reg_txpower_get_temperature(struct il_priv *il)
1080 {
1081         struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1082         int temperature;
1083
1084         temperature = il3945_hw_get_temperature(il);
1085
1086         /* driver's okay range is -260 to +25.
1087          *   human readable okay range is 0 to +285 */
1088         D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT);
1089
1090         /* handle insane temp reading */
1091         if (il3945_hw_reg_temp_out_of_range(temperature)) {
1092                 IL_ERR("Error bad temperature value  %d\n", temperature);
1093
1094                 /* if really really hot(?),
1095                  *   substitute the 3rd band/group's temp measured at factory */
1096                 if (il->last_temperature > 100)
1097                         temperature = eeprom->groups[2].temperature;
1098                 else            /* else use most recent "sane" value from driver */
1099                         temperature = il->last_temperature;
1100         }
1101
1102         return temperature;     /* raw, not "human readable" */
1103 }
1104
1105 /* Adjust Txpower only if temperature variance is greater than threshold.
1106  *
1107  * Both are lower than older versions' 9 degrees */
1108 #define IL_TEMPERATURE_LIMIT_TIMER   6
1109
1110 /**
1111  * il3945_is_temp_calib_needed - determines if new calibration is needed
1112  *
1113  * records new temperature in tx_mgr->temperature.
1114  * replaces tx_mgr->last_temperature *only* if calib needed
1115  *    (assumes caller will actually do the calibration!). */
1116 static int
1117 il3945_is_temp_calib_needed(struct il_priv *il)
1118 {
1119         int temp_diff;
1120
1121         il->temperature = il3945_hw_reg_txpower_get_temperature(il);
1122         temp_diff = il->temperature - il->last_temperature;
1123
1124         /* get absolute value */
1125         if (temp_diff < 0) {
1126                 D_POWER("Getting cooler, delta %d,\n", temp_diff);
1127                 temp_diff = -temp_diff;
1128         } else if (temp_diff == 0)
1129                 D_POWER("Same temp,\n");
1130         else
1131                 D_POWER("Getting warmer, delta %d,\n", temp_diff);
1132
1133         /* if we don't need calibration, *don't* update last_temperature */
1134         if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) {
1135                 D_POWER("Timed thermal calib not needed\n");
1136                 return 0;
1137         }
1138
1139         D_POWER("Timed thermal calib needed\n");
1140
1141         /* assume that caller will actually do calib ...
1142          *   update the "last temperature" value */
1143         il->last_temperature = il->temperature;
1144         return 1;
1145 }
1146
1147 #define IL_MAX_GAIN_ENTRIES 78
1148 #define IL_CCK_FROM_OFDM_POWER_DIFF  -5
1149 #define IL_CCK_FROM_OFDM_IDX_DIFF (10)
1150
1151 /* radio and DSP power table, each step is 1/2 dB.
1152  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1153 static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = {
1154         {
1155          {251, 127},            /* 2.4 GHz, highest power */
1156          {251, 127},
1157          {251, 127},
1158          {251, 127},
1159          {251, 125},
1160          {251, 110},
1161          {251, 105},
1162          {251, 98},
1163          {187, 125},
1164          {187, 115},
1165          {187, 108},
1166          {187, 99},
1167          {243, 119},
1168          {243, 111},
1169          {243, 105},
1170          {243, 97},
1171          {243, 92},
1172          {211, 106},
1173          {211, 100},
1174          {179, 120},
1175          {179, 113},
1176          {179, 107},
1177          {147, 125},
1178          {147, 119},
1179          {147, 112},
1180          {147, 106},
1181          {147, 101},
1182          {147, 97},
1183          {147, 91},
1184          {115, 107},
1185          {235, 121},
1186          {235, 115},
1187          {235, 109},
1188          {203, 127},
1189          {203, 121},
1190          {203, 115},
1191          {203, 108},
1192          {203, 102},
1193          {203, 96},
1194          {203, 92},
1195          {171, 110},
1196          {171, 104},
1197          {171, 98},
1198          {139, 116},
1199          {227, 125},
1200          {227, 119},
1201          {227, 113},
1202          {227, 107},
1203          {227, 101},
1204          {227, 96},
1205          {195, 113},
1206          {195, 106},
1207          {195, 102},
1208          {195, 95},
1209          {163, 113},
1210          {163, 106},
1211          {163, 102},
1212          {163, 95},
1213          {131, 113},
1214          {131, 106},
1215          {131, 102},
1216          {131, 95},
1217          {99, 113},
1218          {99, 106},
1219          {99, 102},
1220          {99, 95},
1221          {67, 113},
1222          {67, 106},
1223          {67, 102},
1224          {67, 95},
1225          {35, 113},
1226          {35, 106},
1227          {35, 102},
1228          {35, 95},
1229          {3, 113},
1230          {3, 106},
1231          {3, 102},
1232          {3, 95}                /* 2.4 GHz, lowest power */
1233         },
1234         {
1235          {251, 127},            /* 5.x GHz, highest power */
1236          {251, 120},
1237          {251, 114},
1238          {219, 119},
1239          {219, 101},
1240          {187, 113},
1241          {187, 102},
1242          {155, 114},
1243          {155, 103},
1244          {123, 117},
1245          {123, 107},
1246          {123, 99},
1247          {123, 92},
1248          {91, 108},
1249          {59, 125},
1250          {59, 118},
1251          {59, 109},
1252          {59, 102},
1253          {59, 96},
1254          {59, 90},
1255          {27, 104},
1256          {27, 98},
1257          {27, 92},
1258          {115, 118},
1259          {115, 111},
1260          {115, 104},
1261          {83, 126},
1262          {83, 121},
1263          {83, 113},
1264          {83, 105},
1265          {83, 99},
1266          {51, 118},
1267          {51, 111},
1268          {51, 104},
1269          {51, 98},
1270          {19, 116},
1271          {19, 109},
1272          {19, 102},
1273          {19, 98},
1274          {19, 93},
1275          {171, 113},
1276          {171, 107},
1277          {171, 99},
1278          {139, 120},
1279          {139, 113},
1280          {139, 107},
1281          {139, 99},
1282          {107, 120},
1283          {107, 113},
1284          {107, 107},
1285          {107, 99},
1286          {75, 120},
1287          {75, 113},
1288          {75, 107},
1289          {75, 99},
1290          {43, 120},
1291          {43, 113},
1292          {43, 107},
1293          {43, 99},
1294          {11, 120},
1295          {11, 113},
1296          {11, 107},
1297          {11, 99},
1298          {131, 107},
1299          {131, 99},
1300          {99, 120},
1301          {99, 113},
1302          {99, 107},
1303          {99, 99},
1304          {67, 120},
1305          {67, 113},
1306          {67, 107},
1307          {67, 99},
1308          {35, 120},
1309          {35, 113},
1310          {35, 107},
1311          {35, 99},
1312          {3, 120}               /* 5.x GHz, lowest power */
1313         }
1314 };
1315
1316 static inline u8
1317 il3945_hw_reg_fix_power_idx(int idx)
1318 {
1319         if (idx < 0)
1320                 return 0;
1321         if (idx >= IL_MAX_GAIN_ENTRIES)
1322                 return IL_MAX_GAIN_ENTRIES - 1;
1323         return (u8) idx;
1324 }
1325
1326 /* Kick off thermal recalibration check every 60 seconds */
1327 #define REG_RECALIB_PERIOD (60)
1328
1329 /**
1330  * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1331  *
1332  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1333  * or 6 Mbit (OFDM) rates.
1334  */
1335 static void
1336 il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx,
1337                              const s8 *clip_pwrs,
1338                              struct il_channel_info *ch_info, int band_idx)
1339 {
1340         struct il3945_scan_power_info *scan_power_info;
1341         s8 power;
1342         u8 power_idx;
1343
1344         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx];
1345
1346         /* use this channel group's 6Mbit clipping/saturation pwr,
1347          *   but cap at regulatory scan power restriction (set during init
1348          *   based on eeprom channel data) for this channel.  */
1349         power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]);
1350
1351         power = min(power, il->tx_power_user_lmt);
1352         scan_power_info->requested_power = power;
1353
1354         /* find difference between new scan *power* and current "normal"
1355          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1356          *   current "normal" temperature-compensated Tx power *idx* for
1357          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1358          *   *idx*. */
1359         power_idx =
1360             ch_info->power_info[rate_idx].power_table_idx - (power -
1361                                                              ch_info->
1362                                                              power_info
1363                                                              [RATE_6M_IDX_TBL].
1364                                                              requested_power) *
1365             2;
1366
1367         /* store reference idx that we use when adjusting *all* scan
1368          *   powers.  So we can accommodate user (all channel) or spectrum
1369          *   management (single channel) power changes "between" temperature
1370          *   feedback compensation procedures.
1371          * don't force fit this reference idx into gain table; it may be a
1372          *   negative number.  This will help avoid errors when we're at
1373          *   the lower bounds (highest gains, for warmest temperatures)
1374          *   of the table. */
1375
1376         /* don't exceed table bounds for "real" setting */
1377         power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1378
1379         scan_power_info->power_table_idx = power_idx;
1380         scan_power_info->tpc.tx_gain =
1381             power_gain_table[band_idx][power_idx].tx_gain;
1382         scan_power_info->tpc.dsp_atten =
1383             power_gain_table[band_idx][power_idx].dsp_atten;
1384 }
1385
1386 /**
1387  * il3945_send_tx_power - fill in Tx Power command with gain settings
1388  *
1389  * Configures power settings for all rates for the current channel,
1390  * using values from channel info struct, and send to NIC
1391  */
1392 static int
1393 il3945_send_tx_power(struct il_priv *il)
1394 {
1395         int rate_idx, i;
1396         const struct il_channel_info *ch_info = NULL;
1397         struct il3945_txpowertable_cmd txpower = {
1398                 .channel = il->ctx.active.channel,
1399         };
1400         u16 chan;
1401
1402         if (WARN_ONCE
1403             (test_bit(S_SCAN_HW, &il->status),
1404              "TX Power requested while scanning!\n"))
1405                 return -EAGAIN;
1406
1407         chan = le16_to_cpu(il->ctx.active.channel);
1408
1409         txpower.band = (il->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1410         ch_info = il_get_channel_info(il, il->band, chan);
1411         if (!ch_info) {
1412                 IL_ERR("Failed to get channel info for channel %d [%d]\n", chan,
1413                        il->band);
1414                 return -EINVAL;
1415         }
1416
1417         if (!il_is_channel_valid(ch_info)) {
1418                 D_POWER("Not calling TX_PWR_TBL_CMD on " "non-Tx channel.\n");
1419                 return 0;
1420         }
1421
1422         /* fill cmd with power settings for all rates for current channel */
1423         /* Fill OFDM rate */
1424         for (rate_idx = IL_FIRST_OFDM_RATE, i = 0;
1425              rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) {
1426
1427                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1428                 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1429
1430                 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1431                         le16_to_cpu(txpower.channel), txpower.band,
1432                         txpower.power[i].tpc.tx_gain,
1433                         txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1434         }
1435         /* Fill CCK rates */
1436         for (rate_idx = IL_FIRST_CCK_RATE; rate_idx <= IL_LAST_CCK_RATE;
1437              rate_idx++, i++) {
1438                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1439                 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1440
1441                 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1442                         le16_to_cpu(txpower.channel), txpower.band,
1443                         txpower.power[i].tpc.tx_gain,
1444                         txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1445         }
1446
1447         return il_send_cmd_pdu(il, C_TX_PWR_TBL,
1448                                sizeof(struct il3945_txpowertable_cmd),
1449                                &txpower);
1450
1451 }
1452
1453 /**
1454  * il3945_hw_reg_set_new_power - Configures power tables at new levels
1455  * @ch_info: Channel to update.  Uses power_info.requested_power.
1456  *
1457  * Replace requested_power and base_power_idx ch_info fields for
1458  * one channel.
1459  *
1460  * Called if user or spectrum management changes power preferences.
1461  * Takes into account h/w and modulation limitations (clip power).
1462  *
1463  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1464  *
1465  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1466  *       properly fill out the scan powers, and actual h/w gain settings,
1467  *       and send changes to NIC
1468  */
1469 static int
1470 il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info)
1471 {
1472         struct il3945_channel_power_info *power_info;
1473         int power_changed = 0;
1474         int i;
1475         const s8 *clip_pwrs;
1476         int power;
1477
1478         /* Get this chnlgrp's rate-to-max/clip-powers table */
1479         clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1480
1481         /* Get this channel's rate-to-current-power settings table */
1482         power_info = ch_info->power_info;
1483
1484         /* update OFDM Txpower settings */
1485         for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++, ++power_info) {
1486                 int delta_idx;
1487
1488                 /* limit new power to be no more than h/w capability */
1489                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1490                 if (power == power_info->requested_power)
1491                         continue;
1492
1493                 /* find difference between old and new requested powers,
1494                  *    update base (non-temp-compensated) power idx */
1495                 delta_idx = (power - power_info->requested_power) * 2;
1496                 power_info->base_power_idx -= delta_idx;
1497
1498                 /* save new requested power value */
1499                 power_info->requested_power = power;
1500
1501                 power_changed = 1;
1502         }
1503
1504         /* update CCK Txpower settings, based on OFDM 12M setting ...
1505          *    ... all CCK power settings for a given channel are the *same*. */
1506         if (power_changed) {
1507                 power =
1508                     ch_info->power_info[RATE_12M_IDX_TBL].requested_power +
1509                     IL_CCK_FROM_OFDM_POWER_DIFF;
1510
1511                 /* do all CCK rates' il3945_channel_power_info structures */
1512                 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) {
1513                         power_info->requested_power = power;
1514                         power_info->base_power_idx =
1515                             ch_info->power_info[RATE_12M_IDX_TBL].
1516                             base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
1517                         ++power_info;
1518                 }
1519         }
1520
1521         return 0;
1522 }
1523
1524 /**
1525  * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1526  *
1527  * NOTE: Returned power limit may be less (but not more) than requested,
1528  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1529  *       (no consideration for h/w clipping limitations).
1530  */
1531 static int
1532 il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info)
1533 {
1534         s8 max_power;
1535
1536 #if 0
1537         /* if we're using TGd limits, use lower of TGd or EEPROM */
1538         if (ch_info->tgd_data.max_power != 0)
1539                 max_power =
1540                     min(ch_info->tgd_data.max_power,
1541                         ch_info->eeprom.max_power_avg);
1542
1543         /* else just use EEPROM limits */
1544         else
1545 #endif
1546                 max_power = ch_info->eeprom.max_power_avg;
1547
1548         return min(max_power, ch_info->max_power_avg);
1549 }
1550
1551 /**
1552  * il3945_hw_reg_comp_txpower_temp - Compensate for temperature
1553  *
1554  * Compensate txpower settings of *all* channels for temperature.
1555  * This only accounts for the difference between current temperature
1556  *   and the factory calibration temperatures, and bases the new settings
1557  *   on the channel's base_power_idx.
1558  *
1559  * If RxOn is "associated", this sends the new Txpower to NIC!
1560  */
1561 static int
1562 il3945_hw_reg_comp_txpower_temp(struct il_priv *il)
1563 {
1564         struct il_channel_info *ch_info = NULL;
1565         struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1566         int delta_idx;
1567         const s8 *clip_pwrs;    /* array of h/w max power levels for each rate */
1568         u8 a_band;
1569         u8 rate_idx;
1570         u8 scan_tbl_idx;
1571         u8 i;
1572         int ref_temp;
1573         int temperature = il->temperature;
1574
1575         if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) {
1576                 /* do not perform tx power calibration */
1577                 return 0;
1578         }
1579         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1580         for (i = 0; i < il->channel_count; i++) {
1581                 ch_info = &il->channel_info[i];
1582                 a_band = il_is_channel_a_band(ch_info);
1583
1584                 /* Get this chnlgrp's factory calibration temperature */
1585                 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature;
1586
1587                 /* get power idx adjustment based on current and factory
1588                  * temps */
1589                 delta_idx =
1590                     il3945_hw_reg_adjust_power_by_temp(temperature, ref_temp);
1591
1592                 /* set tx power value for all rates, OFDM and CCK */
1593                 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; rate_idx++) {
1594                         int power_idx =
1595                             ch_info->power_info[rate_idx].base_power_idx;
1596
1597                         /* temperature compensate */
1598                         power_idx += delta_idx;
1599
1600                         /* stay within table range */
1601                         power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1602                         ch_info->power_info[rate_idx].power_table_idx =
1603                             (u8) power_idx;
1604                         ch_info->power_info[rate_idx].tpc =
1605                             power_gain_table[a_band][power_idx];
1606                 }
1607
1608                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1609                 clip_pwrs =
1610                     il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1611
1612                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1613                 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
1614                      scan_tbl_idx++) {
1615                         s32 actual_idx =
1616                             (scan_tbl_idx ==
1617                              0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
1618                         il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
1619                                                      actual_idx, clip_pwrs,
1620                                                      ch_info, a_band);
1621                 }
1622         }
1623
1624         /* send Txpower command for current channel to ucode */
1625         return il->cfg->ops->lib->send_tx_power(il);
1626 }
1627
1628 int
1629 il3945_hw_reg_set_txpower(struct il_priv *il, s8 power)
1630 {
1631         struct il_channel_info *ch_info;
1632         s8 max_power;
1633         u8 a_band;
1634         u8 i;
1635
1636         if (il->tx_power_user_lmt == power) {
1637                 D_POWER("Requested Tx power same as current " "limit: %ddBm.\n",
1638                         power);
1639                 return 0;
1640         }
1641
1642         D_POWER("Setting upper limit clamp to %ddBm.\n", power);
1643         il->tx_power_user_lmt = power;
1644
1645         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1646
1647         for (i = 0; i < il->channel_count; i++) {
1648                 ch_info = &il->channel_info[i];
1649                 a_band = il_is_channel_a_band(ch_info);
1650
1651                 /* find minimum power of all user and regulatory constraints
1652                  *    (does not consider h/w clipping limitations) */
1653                 max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info);
1654                 max_power = min(power, max_power);
1655                 if (max_power != ch_info->curr_txpow) {
1656                         ch_info->curr_txpow = max_power;
1657
1658                         /* this considers the h/w clipping limitations */
1659                         il3945_hw_reg_set_new_power(il, ch_info);
1660                 }
1661         }
1662
1663         /* update txpower settings for all channels,
1664          *   send to NIC if associated. */
1665         il3945_is_temp_calib_needed(il);
1666         il3945_hw_reg_comp_txpower_temp(il);
1667
1668         return 0;
1669 }
1670
1671 static int
1672 il3945_send_rxon_assoc(struct il_priv *il, struct il_rxon_context *ctx)
1673 {
1674         int rc = 0;
1675         struct il_rx_pkt *pkt;
1676         struct il3945_rxon_assoc_cmd rxon_assoc;
1677         struct il_host_cmd cmd = {
1678                 .id = C_RXON_ASSOC,
1679                 .len = sizeof(rxon_assoc),
1680                 .flags = CMD_WANT_SKB,
1681                 .data = &rxon_assoc,
1682         };
1683         const struct il_rxon_cmd *rxon1 = &ctx->staging;
1684         const struct il_rxon_cmd *rxon2 = &ctx->active;
1685
1686         if (rxon1->flags == rxon2->flags &&
1687             rxon1->filter_flags == rxon2->filter_flags &&
1688             rxon1->cck_basic_rates == rxon2->cck_basic_rates &&
1689             rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) {
1690                 D_INFO("Using current RXON_ASSOC.  Not resending.\n");
1691                 return 0;
1692         }
1693
1694         rxon_assoc.flags = ctx->staging.flags;
1695         rxon_assoc.filter_flags = ctx->staging.filter_flags;
1696         rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1697         rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1698         rxon_assoc.reserved = 0;
1699
1700         rc = il_send_cmd_sync(il, &cmd);
1701         if (rc)
1702                 return rc;
1703
1704         pkt = (struct il_rx_pkt *)cmd.reply_page;
1705         if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
1706                 IL_ERR("Bad return from C_RXON_ASSOC command\n");
1707                 rc = -EIO;
1708         }
1709
1710         il_free_pages(il, cmd.reply_page);
1711
1712         return rc;
1713 }
1714
1715 /**
1716  * il3945_commit_rxon - commit staging_rxon to hardware
1717  *
1718  * The RXON command in staging_rxon is committed to the hardware and
1719  * the active_rxon structure is updated with the new data.  This
1720  * function correctly transitions out of the RXON_ASSOC_MSK state if
1721  * a HW tune is required based on the RXON structure changes.
1722  */
1723 int
1724 il3945_commit_rxon(struct il_priv *il, struct il_rxon_context *ctx)
1725 {
1726         /* cast away the const for active_rxon in this function */
1727         struct il3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1728         struct il3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1729         int rc = 0;
1730         bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1731
1732         if (test_bit(S_EXIT_PENDING, &il->status))
1733                 return -EINVAL;
1734
1735         if (!il_is_alive(il))
1736                 return -1;
1737
1738         /* always get timestamp with Rx frame */
1739         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1740
1741         /* select antenna */
1742         staging_rxon->flags &= ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1743         staging_rxon->flags |= il3945_get_antenna_flags(il);
1744
1745         rc = il_check_rxon_cmd(il, ctx);
1746         if (rc) {
1747                 IL_ERR("Invalid RXON configuration.  Not committing.\n");
1748                 return -EINVAL;
1749         }
1750
1751         /* If we don't need to send a full RXON, we can use
1752          * il3945_rxon_assoc_cmd which is used to reconfigure filter
1753          * and other flags for the current radio configuration. */
1754         if (!il_full_rxon_required(il, &il->ctx)) {
1755                 rc = il_send_rxon_assoc(il, &il->ctx);
1756                 if (rc) {
1757                         IL_ERR("Error setting RXON_ASSOC "
1758                                "configuration (%d).\n", rc);
1759                         return rc;
1760                 }
1761
1762                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1763                 /*
1764                  * We do not commit tx power settings while channel changing,
1765                  * do it now if tx power changed.
1766                  */
1767                 il_set_tx_power(il, il->tx_power_next, false);
1768                 return 0;
1769         }
1770
1771         /* If we are currently associated and the new config requires
1772          * an RXON_ASSOC and the new config wants the associated mask enabled,
1773          * we must clear the associated from the active configuration
1774          * before we apply the new config */
1775         if (il_is_associated(il) && new_assoc) {
1776                 D_INFO("Toggling associated bit on current RXON\n");
1777                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1778
1779                 /*
1780                  * reserved4 and 5 could have been filled by the iwlcore code.
1781                  * Let's clear them before pushing to the 3945.
1782                  */
1783                 active_rxon->reserved4 = 0;
1784                 active_rxon->reserved5 = 0;
1785                 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1786                                      &il->ctx.active);
1787
1788                 /* If the mask clearing failed then we set
1789                  * active_rxon back to what it was previously */
1790                 if (rc) {
1791                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1792                         IL_ERR("Error clearing ASSOC_MSK on current "
1793                                "configuration (%d).\n", rc);
1794                         return rc;
1795                 }
1796                 il_clear_ucode_stations(il, &il->ctx);
1797                 il_restore_stations(il, &il->ctx);
1798         }
1799
1800         D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n"
1801                "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"),
1802                le16_to_cpu(staging_rxon->channel), staging_rxon->bssid_addr);
1803
1804         /*
1805          * reserved4 and 5 could have been filled by the iwlcore code.
1806          * Let's clear them before pushing to the 3945.
1807          */
1808         staging_rxon->reserved4 = 0;
1809         staging_rxon->reserved5 = 0;
1810
1811         il_set_rxon_hwcrypto(il, ctx, !il3945_mod_params.sw_crypto);
1812
1813         /* Apply the new configuration */
1814         rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1815                              staging_rxon);
1816         if (rc) {
1817                 IL_ERR("Error setting new configuration (%d).\n", rc);
1818                 return rc;
1819         }
1820
1821         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1822
1823         if (!new_assoc) {
1824                 il_clear_ucode_stations(il, &il->ctx);
1825                 il_restore_stations(il, &il->ctx);
1826         }
1827
1828         /* If we issue a new RXON command which required a tune then we must
1829          * send a new TXPOWER command or we won't be able to Tx any frames */
1830         rc = il_set_tx_power(il, il->tx_power_next, true);
1831         if (rc) {
1832                 IL_ERR("Error setting Tx power (%d).\n", rc);
1833                 return rc;
1834         }
1835
1836         /* Init the hardware's rate fallback order based on the band */
1837         rc = il3945_init_hw_rate_table(il);
1838         if (rc) {
1839                 IL_ERR("Error setting HW rate table: %02X\n", rc);
1840                 return -EIO;
1841         }
1842
1843         return 0;
1844 }
1845
1846 /**
1847  * il3945_reg_txpower_periodic -  called when time to check our temperature.
1848  *
1849  * -- reset periodic timer
1850  * -- see if temp has changed enough to warrant re-calibration ... if so:
1851  *     -- correct coeffs for temp (can reset temp timer)
1852  *     -- save this temp as "last",
1853  *     -- send new set of gain settings to NIC
1854  * NOTE:  This should continue working, even when we're not associated,
1855  *   so we can keep our internal table of scan powers current. */
1856 void
1857 il3945_reg_txpower_periodic(struct il_priv *il)
1858 {
1859         /* This will kick in the "brute force"
1860          * il3945_hw_reg_comp_txpower_temp() below */
1861         if (!il3945_is_temp_calib_needed(il))
1862                 goto reschedule;
1863
1864         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1865          * This is based *only* on current temperature,
1866          * ignoring any previous power measurements */
1867         il3945_hw_reg_comp_txpower_temp(il);
1868
1869 reschedule:
1870         queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic,
1871                            REG_RECALIB_PERIOD * HZ);
1872 }
1873
1874 static void
1875 il3945_bg_reg_txpower_periodic(struct work_struct *work)
1876 {
1877         struct il_priv *il = container_of(work, struct il_priv,
1878                                           _3945.thermal_periodic.work);
1879
1880         if (test_bit(S_EXIT_PENDING, &il->status))
1881                 return;
1882
1883         mutex_lock(&il->mutex);
1884         il3945_reg_txpower_periodic(il);
1885         mutex_unlock(&il->mutex);
1886 }
1887
1888 /**
1889  * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4) for channel.
1890  *
1891  * This function is used when initializing channel-info structs.
1892  *
1893  * NOTE: These channel groups do *NOT* match the bands above!
1894  *       These channel groups are based on factory-tested channels;
1895  *       on A-band, EEPROM's "group frequency" entries represent the top
1896  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1897  */
1898 static u16
1899 il3945_hw_reg_get_ch_grp_idx(struct il_priv *il,
1900                              const struct il_channel_info *ch_info)
1901 {
1902         struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1903         struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1904         u8 group;
1905         u16 group_idx = 0;      /* based on factory calib frequencies */
1906         u8 grp_channel;
1907
1908         /* Find the group idx for the channel ... don't use idx 1(?) */
1909         if (il_is_channel_a_band(ch_info)) {
1910                 for (group = 1; group < 5; group++) {
1911                         grp_channel = ch_grp[group].group_channel;
1912                         if (ch_info->channel <= grp_channel) {
1913                                 group_idx = group;
1914                                 break;
1915                         }
1916                 }
1917                 /* group 4 has a few channels *above* its factory cal freq */
1918                 if (group == 5)
1919                         group_idx = 4;
1920         } else
1921                 group_idx = 0;  /* 2.4 GHz, group 0 */
1922
1923         D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx);
1924         return group_idx;
1925 }
1926
1927 /**
1928  * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx
1929  *
1930  * Interpolate to get nominal (i.e. at factory calibration temperature) idx
1931  *   into radio/DSP gain settings table for requested power.
1932  */
1933 static int
1934 il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power,
1935                                     s32 setting_idx, s32 *new_idx)
1936 {
1937         const struct il3945_eeprom_txpower_group *chnl_grp = NULL;
1938         struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1939         s32 idx0, idx1;
1940         s32 power = 2 * requested_power;
1941         s32 i;
1942         const struct il3945_eeprom_txpower_sample *samples;
1943         s32 gains0, gains1;
1944         s32 res;
1945         s32 denominator;
1946
1947         chnl_grp = &eeprom->groups[setting_idx];
1948         samples = chnl_grp->samples;
1949         for (i = 0; i < 5; i++) {
1950                 if (power == samples[i].power) {
1951                         *new_idx = samples[i].gain_idx;
1952                         return 0;
1953                 }
1954         }
1955
1956         if (power > samples[1].power) {
1957                 idx0 = 0;
1958                 idx1 = 1;
1959         } else if (power > samples[2].power) {
1960                 idx0 = 1;
1961                 idx1 = 2;
1962         } else if (power > samples[3].power) {
1963                 idx0 = 2;
1964                 idx1 = 3;
1965         } else {
1966                 idx0 = 3;
1967                 idx1 = 4;
1968         }
1969
1970         denominator = (s32) samples[idx1].power - (s32) samples[idx0].power;
1971         if (denominator == 0)
1972                 return -EINVAL;
1973         gains0 = (s32) samples[idx0].gain_idx * (1 << 19);
1974         gains1 = (s32) samples[idx1].gain_idx * (1 << 19);
1975         res =
1976             gains0 + (gains1 - gains0) * ((s32) power -
1977                                           (s32) samples[idx0].power) /
1978             denominator + (1 << 18);
1979         *new_idx = res >> 19;
1980         return 0;
1981 }
1982
1983 static void
1984 il3945_hw_reg_init_channel_groups(struct il_priv *il)
1985 {
1986         u32 i;
1987         s32 rate_idx;
1988         struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1989         const struct il3945_eeprom_txpower_group *group;
1990
1991         D_POWER("Initializing factory calib info from EEPROM\n");
1992
1993         for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) {
1994                 s8 *clip_pwrs;  /* table of power levels for each rate */
1995                 s8 satur_pwr;   /* saturation power for each chnl group */
1996                 group = &eeprom->groups[i];
1997
1998                 /* sanity check on factory saturation power value */
1999                 if (group->saturation_power < 40) {
2000                         IL_WARN("Error: saturation power is %d, "
2001                                 "less than minimum expected 40\n",
2002                                 group->saturation_power);
2003                         return;
2004                 }
2005
2006                 /*
2007                  * Derive requested power levels for each rate, based on
2008                  *   hardware capabilities (saturation power for band).
2009                  * Basic value is 3dB down from saturation, with further
2010                  *   power reductions for highest 3 data rates.  These
2011                  *   backoffs provide headroom for high rate modulation
2012                  *   power peaks, without too much distortion (clipping).
2013                  */
2014                 /* we'll fill in this array with h/w max power levels */
2015                 clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers;
2016
2017                 /* divide factory saturation power by 2 to find -3dB level */
2018                 satur_pwr = (s8) (group->saturation_power >> 1);
2019
2020                 /* fill in channel group's nominal powers for each rate */
2021                 for (rate_idx = 0; rate_idx < RATE_COUNT_3945;
2022                      rate_idx++, clip_pwrs++) {
2023                         switch (rate_idx) {
2024                         case RATE_36M_IDX_TBL:
2025                                 if (i == 0)     /* B/G */
2026                                         *clip_pwrs = satur_pwr;
2027                                 else    /* A */
2028                                         *clip_pwrs = satur_pwr - 5;
2029                                 break;
2030                         case RATE_48M_IDX_TBL:
2031                                 if (i == 0)
2032                                         *clip_pwrs = satur_pwr - 7;
2033                                 else
2034                                         *clip_pwrs = satur_pwr - 10;
2035                                 break;
2036                         case RATE_54M_IDX_TBL:
2037                                 if (i == 0)
2038                                         *clip_pwrs = satur_pwr - 9;
2039                                 else
2040                                         *clip_pwrs = satur_pwr - 12;
2041                                 break;
2042                         default:
2043                                 *clip_pwrs = satur_pwr;
2044                                 break;
2045                         }
2046                 }
2047         }
2048 }
2049
2050 /**
2051  * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2052  *
2053  * Second pass (during init) to set up il->channel_info
2054  *
2055  * Set up Tx-power settings in our channel info database for each VALID
2056  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2057  * and current temperature.
2058  *
2059  * Since this is based on current temperature (at init time), these values may
2060  * not be valid for very long, but it gives us a starting/default point,
2061  * and allows us to active (i.e. using Tx) scan.
2062  *
2063  * This does *not* write values to NIC, just sets up our internal table.
2064  */
2065 int
2066 il3945_txpower_set_from_eeprom(struct il_priv *il)
2067 {
2068         struct il_channel_info *ch_info = NULL;
2069         struct il3945_channel_power_info *pwr_info;
2070         struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
2071         int delta_idx;
2072         u8 rate_idx;
2073         u8 scan_tbl_idx;
2074         const s8 *clip_pwrs;    /* array of power levels for each rate */
2075         u8 gain, dsp_atten;
2076         s8 power;
2077         u8 pwr_idx, base_pwr_idx, a_band;
2078         u8 i;
2079         int temperature;
2080
2081         /* save temperature reference,
2082          *   so we can determine next time to calibrate */
2083         temperature = il3945_hw_reg_txpower_get_temperature(il);
2084         il->last_temperature = temperature;
2085
2086         il3945_hw_reg_init_channel_groups(il);
2087
2088         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2089         for (i = 0, ch_info = il->channel_info; i < il->channel_count;
2090              i++, ch_info++) {
2091                 a_band = il_is_channel_a_band(ch_info);
2092                 if (!il_is_channel_valid(ch_info))
2093                         continue;
2094
2095                 /* find this channel's channel group (*not* "band") idx */
2096                 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info);
2097
2098                 /* Get this chnlgrp's rate->max/clip-powers table */
2099                 clip_pwrs =
2100                     il->_3945.clip_groups[ch_info->group_idx].clip_powers;
2101
2102                 /* calculate power idx *adjustment* value according to
2103                  *  diff between current temperature and factory temperature */
2104                 delta_idx =
2105                     il3945_hw_reg_adjust_power_by_temp(temperature,
2106                                                        eeprom->groups[ch_info->
2107                                                                       group_idx].
2108                                                        temperature);
2109
2110                 D_POWER("Delta idx for channel %d: %d [%d]\n", ch_info->channel,
2111                         delta_idx, temperature + IL_TEMP_CONVERT);
2112
2113                 /* set tx power value for all OFDM rates */
2114                 for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) {
2115                         s32 uninitialized_var(power_idx);
2116                         int rc;
2117
2118                         /* use channel group's clip-power table,
2119                          *   but don't exceed channel's max power */
2120                         s8 pwr = min(ch_info->max_power_avg,
2121                                      clip_pwrs[rate_idx]);
2122
2123                         pwr_info = &ch_info->power_info[rate_idx];
2124
2125                         /* get base (i.e. at factory-measured temperature)
2126                          *    power table idx for this rate's power */
2127                         rc = il3945_hw_reg_get_matched_power_idx(il, pwr,
2128                                                                  ch_info->
2129                                                                  group_idx,
2130                                                                  &power_idx);
2131                         if (rc) {
2132                                 IL_ERR("Invalid power idx\n");
2133                                 return rc;
2134                         }
2135                         pwr_info->base_power_idx = (u8) power_idx;
2136
2137                         /* temperature compensate */
2138                         power_idx += delta_idx;
2139
2140                         /* stay within range of gain table */
2141                         power_idx = il3945_hw_reg_fix_power_idx(power_idx);
2142
2143                         /* fill 1 OFDM rate's il3945_channel_power_info struct */
2144                         pwr_info->requested_power = pwr;
2145                         pwr_info->power_table_idx = (u8) power_idx;
2146                         pwr_info->tpc.tx_gain =
2147                             power_gain_table[a_band][power_idx].tx_gain;
2148                         pwr_info->tpc.dsp_atten =
2149                             power_gain_table[a_band][power_idx].dsp_atten;
2150                 }
2151
2152                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings */
2153                 pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL];
2154                 power = pwr_info->requested_power + IL_CCK_FROM_OFDM_POWER_DIFF;
2155                 pwr_idx = pwr_info->power_table_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2156                 base_pwr_idx =
2157                     pwr_info->base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2158
2159                 /* stay within table range */
2160                 pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx);
2161                 gain = power_gain_table[a_band][pwr_idx].tx_gain;
2162                 dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten;
2163
2164                 /* fill each CCK rate's il3945_channel_power_info structure
2165                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2166                  * NOTE:  CCK rates start at end of OFDM rates! */
2167                 for (rate_idx = 0; rate_idx < IL_CCK_RATES; rate_idx++) {
2168                         pwr_info =
2169                             &ch_info->power_info[rate_idx + IL_OFDM_RATES];
2170                         pwr_info->requested_power = power;
2171                         pwr_info->power_table_idx = pwr_idx;
2172                         pwr_info->base_power_idx = base_pwr_idx;
2173                         pwr_info->tpc.tx_gain = gain;
2174                         pwr_info->tpc.dsp_atten = dsp_atten;
2175                 }
2176
2177                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2178                 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
2179                      scan_tbl_idx++) {
2180                         s32 actual_idx =
2181                             (scan_tbl_idx ==
2182                              0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
2183                         il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
2184                                                      actual_idx, clip_pwrs,
2185                                                      ch_info, a_band);
2186                 }
2187         }
2188
2189         return 0;
2190 }
2191
2192 int
2193 il3945_hw_rxq_stop(struct il_priv *il)
2194 {
2195         int rc;
2196
2197         il_wr(il, FH39_RCSR_CONFIG(0), 0);
2198         rc = il_poll_bit(il, FH39_RSSR_STATUS,
2199                          FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2200         if (rc < 0)
2201                 IL_ERR("Can't stop Rx DMA.\n");
2202
2203         return 0;
2204 }
2205
2206 int
2207 il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
2208 {
2209         int txq_id = txq->q.id;
2210
2211         struct il3945_shared *shared_data = il->_3945.shared_virt;
2212
2213         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr);
2214
2215         il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
2216         il_wr(il, FH39_CBCC_BASE(txq_id), 0);
2217
2218         il_wr(il, FH39_TCSR_CONFIG(txq_id),
2219               FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2220               FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2221               FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2222               FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2223               FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2224
2225         /* fake read to flush all prev. writes */
2226         _il_rd(il, FH39_TSSR_CBB_BASE);
2227
2228         return 0;
2229 }
2230
2231 /*
2232  * HCMD utils
2233  */
2234 static u16
2235 il3945_get_hcmd_size(u8 cmd_id, u16 len)
2236 {
2237         switch (cmd_id) {
2238         case C_RXON:
2239                 return sizeof(struct il3945_rxon_cmd);
2240         case C_POWER_TBL:
2241                 return sizeof(struct il3945_powertable_cmd);
2242         default:
2243                 return len;
2244         }
2245 }
2246
2247 static u16
2248 il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data)
2249 {
2250         struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data;
2251         addsta->mode = cmd->mode;
2252         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2253         memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo));
2254         addsta->station_flags = cmd->station_flags;
2255         addsta->station_flags_msk = cmd->station_flags_msk;
2256         addsta->tid_disable_tx = cpu_to_le16(0);
2257         addsta->rate_n_flags = cmd->rate_n_flags;
2258         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2259         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2260         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2261
2262         return (u16) sizeof(struct il3945_addsta_cmd);
2263 }
2264
2265 static int
2266 il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r)
2267 {
2268         struct il_rxon_context *ctx = &il->ctx;
2269         int ret;
2270         u8 sta_id;
2271         unsigned long flags;
2272
2273         if (sta_id_r)
2274                 *sta_id_r = IL_INVALID_STATION;
2275
2276         ret = il_add_station_common(il, ctx, addr, 0, NULL, &sta_id);
2277         if (ret) {
2278                 IL_ERR("Unable to add station %pM\n", addr);
2279                 return ret;
2280         }
2281
2282         if (sta_id_r)
2283                 *sta_id_r = sta_id;
2284
2285         spin_lock_irqsave(&il->sta_lock, flags);
2286         il->stations[sta_id].used |= IL_STA_LOCAL;
2287         spin_unlock_irqrestore(&il->sta_lock, flags);
2288
2289         return 0;
2290 }
2291
2292 static int
2293 il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
2294                            bool add)
2295 {
2296         struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
2297         int ret;
2298
2299         if (add) {
2300                 ret =
2301                     il3945_add_bssid_station(il, vif->bss_conf.bssid,
2302                                              &vif_priv->ibss_bssid_sta_id);
2303                 if (ret)
2304                         return ret;
2305
2306                 il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id,
2307                                 (il->band ==
2308                                  IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP :
2309                                 RATE_1M_PLCP);
2310                 il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id);
2311
2312                 return 0;
2313         }
2314
2315         return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
2316                                  vif->bss_conf.bssid);
2317 }
2318
2319 /**
2320  * il3945_init_hw_rate_table - Initialize the hardware rate fallback table
2321  */
2322 int
2323 il3945_init_hw_rate_table(struct il_priv *il)
2324 {
2325         int rc, i, idx, prev_idx;
2326         struct il3945_rate_scaling_cmd rate_cmd = {
2327                 .reserved = {0, 0, 0},
2328         };
2329         struct il3945_rate_scaling_info *table = rate_cmd.table;
2330
2331         for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) {
2332                 idx = il3945_rates[i].table_rs_idx;
2333
2334                 table[idx].rate_n_flags =
2335                     il3945_hw_set_rate_n_flags(il3945_rates[i].plcp, 0);
2336                 table[idx].try_cnt = il->retry_rate;
2337                 prev_idx = il3945_get_prev_ieee_rate(i);
2338                 table[idx].next_rate_idx = il3945_rates[prev_idx].table_rs_idx;
2339         }
2340
2341         switch (il->band) {
2342         case IEEE80211_BAND_5GHZ:
2343                 D_RATE("Select A mode rate scale\n");
2344                 /* If one of the following CCK rates is used,
2345                  * have it fall back to the 6M OFDM rate */
2346                 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++)
2347                         table[i].next_rate_idx =
2348                             il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2349
2350                 /* Don't fall back to CCK rates */
2351                 table[RATE_12M_IDX_TBL].next_rate_idx = RATE_9M_IDX_TBL;
2352
2353                 /* Don't drop out of OFDM rates */
2354                 table[RATE_6M_IDX_TBL].next_rate_idx =
2355                     il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2356                 break;
2357
2358         case IEEE80211_BAND_2GHZ:
2359                 D_RATE("Select B/G mode rate scale\n");
2360                 /* If an OFDM rate is used, have it fall back to the
2361                  * 1M CCK rates */
2362
2363                 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
2364                     il_is_associated(il)) {
2365
2366                         idx = IL_FIRST_CCK_RATE;
2367                         for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++)
2368                                 table[i].next_rate_idx =
2369                                     il3945_rates[idx].table_rs_idx;
2370
2371                         idx = RATE_11M_IDX_TBL;
2372                         /* CCK shouldn't fall back to OFDM... */
2373                         table[idx].next_rate_idx = RATE_5M_IDX_TBL;
2374                 }
2375                 break;
2376
2377         default:
2378                 WARN_ON(1);
2379                 break;
2380         }
2381
2382         /* Update the rate scaling for control frame Tx */
2383         rate_cmd.table_id = 0;
2384         rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2385         if (rc)
2386                 return rc;
2387
2388         /* Update the rate scaling for data frame Tx */
2389         rate_cmd.table_id = 1;
2390         return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2391 }
2392
2393 /* Called when initializing driver */
2394 int
2395 il3945_hw_set_hw_params(struct il_priv *il)
2396 {
2397         memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params));
2398
2399         il->_3945.shared_virt =
2400             dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared),
2401                                &il->_3945.shared_phys, GFP_KERNEL);
2402         if (!il->_3945.shared_virt) {
2403                 IL_ERR("failed to allocate pci memory\n");
2404                 return -ENOMEM;
2405         }
2406
2407         /* Assign number of Usable TX queues */
2408         il->hw_params.max_txq_num = il->cfg->base_params->num_of_queues;
2409
2410         il->hw_params.tfd_size = sizeof(struct il3945_tfd);
2411         il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K);
2412         il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2413         il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2414         il->hw_params.max_stations = IL3945_STATION_COUNT;
2415         il->ctx.bcast_sta_id = IL3945_BROADCAST_ID;
2416
2417         il->sta_key_max_num = STA_KEY_MAX_NUM;
2418
2419         il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2420         il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL;
2421         il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS;
2422
2423         return 0;
2424 }
2425
2426 unsigned int
2427 il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame,
2428                          u8 rate)
2429 {
2430         struct il3945_tx_beacon_cmd *tx_beacon_cmd;
2431         unsigned int frame_size;
2432
2433         tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u;
2434         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2435
2436         tx_beacon_cmd->tx.sta_id = il->ctx.bcast_sta_id;
2437         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2438
2439         frame_size =
2440             il3945_fill_beacon_frame(il, tx_beacon_cmd->frame,
2441                                      sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2442
2443         BUG_ON(frame_size > MAX_MPDU_SIZE);
2444         tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
2445
2446         tx_beacon_cmd->tx.rate = rate;
2447         tx_beacon_cmd->tx.tx_flags =
2448             (TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK);
2449
2450         /* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE */
2451         tx_beacon_cmd->tx.supp_rates[0] =
2452             (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
2453
2454         tx_beacon_cmd->tx.supp_rates[1] = (IL_CCK_BASIC_RATES_MASK & 0xF);
2455
2456         return sizeof(struct il3945_tx_beacon_cmd) + frame_size;
2457 }
2458
2459 void
2460 il3945_hw_handler_setup(struct il_priv *il)
2461 {
2462         il->handlers[C_TX] = il3945_hdl_tx;
2463         il->handlers[N_3945_RX] = il3945_hdl_rx;
2464 }
2465
2466 void
2467 il3945_hw_setup_deferred_work(struct il_priv *il)
2468 {
2469         INIT_DELAYED_WORK(&il->_3945.thermal_periodic,
2470                           il3945_bg_reg_txpower_periodic);
2471 }
2472
2473 void
2474 il3945_hw_cancel_deferred_work(struct il_priv *il)
2475 {
2476         cancel_delayed_work(&il->_3945.thermal_periodic);
2477 }
2478
2479 /* check contents of special bootstrap uCode SRAM */
2480 static int
2481 il3945_verify_bsm(struct il_priv *il)
2482 {
2483         __le32 *image = il->ucode_boot.v_addr;
2484         u32 len = il->ucode_boot.len;
2485         u32 reg;
2486         u32 val;
2487
2488         D_INFO("Begin verify bsm\n");
2489
2490         /* verify BSM SRAM contents */
2491         val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
2492         for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len;
2493              reg += sizeof(u32), image++) {
2494                 val = il_rd_prph(il, reg);
2495                 if (val != le32_to_cpu(*image)) {
2496                         IL_ERR("BSM uCode verification failed at "
2497                                "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2498                                BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND,
2499                                len, val, le32_to_cpu(*image));
2500                         return -EIO;
2501                 }
2502         }
2503
2504         D_INFO("BSM bootstrap uCode image OK\n");
2505
2506         return 0;
2507 }
2508
2509 /******************************************************************************
2510  *
2511  * EEPROM related functions
2512  *
2513  ******************************************************************************/
2514
2515 /*
2516  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2517  * embedded controller) as EEPROM reader; each read is a series of pulses
2518  * to/from the EEPROM chip, not a single event, so even reads could conflict
2519  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2520  * simply claims ownership, which should be safe when this function is called
2521  * (i.e. before loading uCode!).
2522  */
2523 static int
2524 il3945_eeprom_acquire_semaphore(struct il_priv *il)
2525 {
2526         _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2527         return 0;
2528 }
2529
2530 static void
2531 il3945_eeprom_release_semaphore(struct il_priv *il)
2532 {
2533         return;
2534 }
2535
2536  /**
2537   * il3945_load_bsm - Load bootstrap instructions
2538   *
2539   * BSM operation:
2540   *
2541   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2542   * in special SRAM that does not power down during RFKILL.  When powering back
2543   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2544   * the bootstrap program into the on-board processor, and starts it.
2545   *
2546   * The bootstrap program loads (via DMA) instructions and data for a new
2547   * program from host DRAM locations indicated by the host driver in the
2548   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2549   * automatically.
2550   *
2551   * When initializing the NIC, the host driver points the BSM to the
2552   * "initialize" uCode image.  This uCode sets up some internal data, then
2553   * notifies host via "initialize alive" that it is complete.
2554   *
2555   * The host then replaces the BSM_DRAM_* pointer values to point to the
2556   * normal runtime uCode instructions and a backup uCode data cache buffer
2557   * (filled initially with starting data values for the on-board processor),
2558   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2559   * which begins normal operation.
2560   *
2561   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2562   * the backup data cache in DRAM before SRAM is powered down.
2563   *
2564   * When powering back up, the BSM loads the bootstrap program.  This reloads
2565   * the runtime uCode instructions and the backup data cache into SRAM,
2566   * and re-launches the runtime uCode from where it left off.
2567   */
2568 static int
2569 il3945_load_bsm(struct il_priv *il)
2570 {
2571         __le32 *image = il->ucode_boot.v_addr;
2572         u32 len = il->ucode_boot.len;
2573         dma_addr_t pinst;
2574         dma_addr_t pdata;
2575         u32 inst_len;
2576         u32 data_len;
2577         int rc;
2578         int i;
2579         u32 done;
2580         u32 reg_offset;
2581
2582         D_INFO("Begin load bsm\n");
2583
2584         /* make sure bootstrap program is no larger than BSM's SRAM size */
2585         if (len > IL39_MAX_BSM_SIZE)
2586                 return -EINVAL;
2587
2588         /* Tell bootstrap uCode where to find the "Initialize" uCode
2589          *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2590          * NOTE:  il3945_initialize_alive_start() will replace these values,
2591          *        after the "initialize" uCode has run, to point to
2592          *        runtime/protocol instructions and backup data cache. */
2593         pinst = il->ucode_init.p_addr;
2594         pdata = il->ucode_init_data.p_addr;
2595         inst_len = il->ucode_init.len;
2596         data_len = il->ucode_init_data.len;
2597
2598         il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2599         il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2600         il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2601         il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2602
2603         /* Fill BSM memory with bootstrap instructions */
2604         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2605              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2606              reg_offset += sizeof(u32), image++)
2607                 _il_wr_prph(il, reg_offset, le32_to_cpu(*image));
2608
2609         rc = il3945_verify_bsm(il);
2610         if (rc)
2611                 return rc;
2612
2613         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2614         il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
2615         il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND);
2616         il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2617
2618         /* Load bootstrap code into instruction SRAM now,
2619          *   to prepare to load "initialize" uCode */
2620         il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
2621
2622         /* Wait for load of bootstrap uCode to finish */
2623         for (i = 0; i < 100; i++) {
2624                 done = il_rd_prph(il, BSM_WR_CTRL_REG);
2625                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2626                         break;
2627                 udelay(10);
2628         }
2629         if (i < 100)
2630                 D_INFO("BSM write complete, poll %d iterations\n", i);
2631         else {
2632                 IL_ERR("BSM write did not complete!\n");
2633                 return -EIO;
2634         }
2635
2636         /* Enable future boot loads whenever power management unit triggers it
2637          *   (e.g. when powering back up after power-save shutdown) */
2638         il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
2639
2640         return 0;
2641 }
2642
2643 static struct il_hcmd_ops il3945_hcmd = {
2644         .rxon_assoc = il3945_send_rxon_assoc,
2645         .commit_rxon = il3945_commit_rxon,
2646 };
2647
2648 static struct il_lib_ops il3945_lib = {
2649         .txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd,
2650         .txq_free_tfd = il3945_hw_txq_free_tfd,
2651         .txq_init = il3945_hw_tx_queue_init,
2652         .load_ucode = il3945_load_bsm,
2653         .dump_nic_error_log = il3945_dump_nic_error_log,
2654         .apm_ops = {
2655                     .init = il3945_apm_init,
2656                     .config = il3945_nic_config,
2657                     },
2658         .eeprom_ops = {
2659                        .regulatory_bands = {
2660                                             EEPROM_REGULATORY_BAND_1_CHANNELS,
2661                                             EEPROM_REGULATORY_BAND_2_CHANNELS,
2662                                             EEPROM_REGULATORY_BAND_3_CHANNELS,
2663                                             EEPROM_REGULATORY_BAND_4_CHANNELS,
2664                                             EEPROM_REGULATORY_BAND_5_CHANNELS,
2665                                             EEPROM_REGULATORY_BAND_NO_HT40,
2666                                             EEPROM_REGULATORY_BAND_NO_HT40,
2667                                             },
2668                        .acquire_semaphore = il3945_eeprom_acquire_semaphore,
2669                        .release_semaphore = il3945_eeprom_release_semaphore,
2670                        },
2671         .send_tx_power = il3945_send_tx_power,
2672         .is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr,
2673
2674         .debugfs_ops = {
2675                         .rx_stats_read = il3945_ucode_rx_stats_read,
2676                         .tx_stats_read = il3945_ucode_tx_stats_read,
2677                         .general_stats_read = il3945_ucode_general_stats_read,
2678                         },
2679 };
2680
2681 static const struct il_legacy_ops il3945_legacy_ops = {
2682         .post_associate = il3945_post_associate,
2683         .config_ap = il3945_config_ap,
2684         .manage_ibss_station = il3945_manage_ibss_station,
2685 };
2686
2687 static struct il_hcmd_utils_ops il3945_hcmd_utils = {
2688         .get_hcmd_size = il3945_get_hcmd_size,
2689         .build_addsta_hcmd = il3945_build_addsta_hcmd,
2690         .request_scan = il3945_request_scan,
2691         .post_scan = il3945_post_scan,
2692 };
2693
2694 static const struct il_ops il3945_ops = {
2695         .lib = &il3945_lib,
2696         .hcmd = &il3945_hcmd,
2697         .utils = &il3945_hcmd_utils,
2698         .led = &il3945_led_ops,
2699         .legacy = &il3945_legacy_ops,
2700         .ieee80211_ops = &il3945_hw_ops,
2701 };
2702
2703 static struct il_base_params il3945_base_params = {
2704         .eeprom_size = IL3945_EEPROM_IMG_SIZE,
2705         .num_of_queues = IL39_NUM_QUEUES,
2706         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2707         .set_l0s = false,
2708         .use_bsm = true,
2709         .led_compensation = 64,
2710         .wd_timeout = IL_DEF_WD_TIMEOUT,
2711 };
2712
2713 static struct il_cfg il3945_bg_cfg = {
2714         .name = "3945BG",
2715         .fw_name_pre = IL3945_FW_PRE,
2716         .ucode_api_max = IL3945_UCODE_API_MAX,
2717         .ucode_api_min = IL3945_UCODE_API_MIN,
2718         .sku = IL_SKU_G,
2719         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2720         .ops = &il3945_ops,
2721         .mod_params = &il3945_mod_params,
2722         .base_params = &il3945_base_params,
2723         .led_mode = IL_LED_BLINK,
2724 };
2725
2726 static struct il_cfg il3945_abg_cfg = {
2727         .name = "3945ABG",
2728         .fw_name_pre = IL3945_FW_PRE,
2729         .ucode_api_max = IL3945_UCODE_API_MAX,
2730         .ucode_api_min = IL3945_UCODE_API_MIN,
2731         .sku = IL_SKU_A | IL_SKU_G,
2732         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2733         .ops = &il3945_ops,
2734         .mod_params = &il3945_mod_params,
2735         .base_params = &il3945_base_params,
2736         .led_mode = IL_LED_BLINK,
2737 };
2738
2739 DEFINE_PCI_DEVICE_TABLE(il3945_hw_card_ids) = {
2740         {IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)},
2741         {IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)},
2742         {IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)},
2743         {IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)},
2744         {IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)},
2745         {IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)},
2746         {0}
2747 };
2748
2749 MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids);