net: explicitly add jump_label.h header to sock.h
[~shefty/rdma-dev.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie-rx.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
32
33 /*TODO: Remove include to iwl-core.h*/
34 #include "iwl-core.h"
35 #include "iwl-io.h"
36 #include "iwl-trans-pcie-int.h"
37
38 /******************************************************************************
39  *
40  * RX path functions
41  *
42  ******************************************************************************/
43
44 /*
45  * Rx theory of operation
46  *
47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
48  * each of which point to Receive Buffers to be filled by the NIC.  These get
49  * used not only for Rx frames, but for any command response or notification
50  * from the NIC.  The driver and NIC manage the Rx buffers by means
51  * of indexes into the circular buffer.
52  *
53  * Rx Queue Indexes
54  * The host/firmware share two index registers for managing the Rx buffers.
55  *
56  * The READ index maps to the first position that the firmware may be writing
57  * to -- the driver can read up to (but not including) this position and get
58  * good data.
59  * The READ index is managed by the firmware once the card is enabled.
60  *
61  * The WRITE index maps to the last position the driver has read from -- the
62  * position preceding WRITE is the last slot the firmware can place a packet.
63  *
64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
65  * WRITE = READ.
66  *
67  * During initialization, the host sets up the READ queue position to the first
68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
69  *
70  * When the firmware places a packet in a buffer, it will advance the READ index
71  * and fire the RX interrupt.  The driver can then query the READ index and
72  * process as many packets as possible, moving the WRITE index forward as it
73  * resets the Rx queue buffers with new memory.
74  *
75  * The management in the driver is as follows:
76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
78  *   to replenish the iwl->rxq->rx_free.
79  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
81  *   'processed' and 'read' driver indexes as well)
82  * + A received packet is processed and handed to the kernel network stack,
83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
84  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
85  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
86  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
87  *   were enough free buffers and RX_STALLED is set it is cleared.
88  *
89  *
90  * Driver sequence:
91  *
92  * iwl_rx_queue_alloc()   Allocates rx_free
93  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
94  *                            iwl_rx_queue_restock
95  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
96  *                            queue, updates firmware pointers, and updates
97  *                            the WRITE index.  If insufficient rx_free buffers
98  *                            are available, schedules iwl_rx_replenish
99  *
100  * -- enable interrupts --
101  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
102  *                            READ INDEX, detaching the SKB from the pool.
103  *                            Moves the packet buffer from queue to rx_used.
104  *                            Calls iwl_rx_queue_restock to refill any empty
105  *                            slots.
106  * ...
107  *
108  */
109
110 /**
111  * iwl_rx_queue_space - Return number of free slots available in queue.
112  */
113 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
114 {
115         int s = q->read - q->write;
116         if (s <= 0)
117                 s += RX_QUEUE_SIZE;
118         /* keep some buffer to not confuse full and empty queue */
119         s -= 2;
120         if (s < 0)
121                 s = 0;
122         return s;
123 }
124
125 /**
126  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
127  */
128 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
129                         struct iwl_rx_queue *q)
130 {
131         unsigned long flags;
132         u32 reg;
133
134         spin_lock_irqsave(&q->lock, flags);
135
136         if (q->need_update == 0)
137                 goto exit_unlock;
138
139         if (hw_params(trans).shadow_reg_enable) {
140                 /* shadow register enabled */
141                 /* Device expects a multiple of 8 */
142                 q->write_actual = (q->write & ~0x7);
143                 iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
144         } else {
145                 /* If power-saving is in use, make sure device is awake */
146                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
147                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
148
149                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
150                                 IWL_DEBUG_INFO(trans,
151                                         "Rx queue requesting wakeup,"
152                                         " GP1 = 0x%x\n", reg);
153                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
154                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
155                                 goto exit_unlock;
156                         }
157
158                         q->write_actual = (q->write & ~0x7);
159                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
160                                         q->write_actual);
161
162                 /* Else device is assumed to be awake */
163                 } else {
164                         /* Device expects a multiple of 8 */
165                         q->write_actual = (q->write & ~0x7);
166                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
167                                 q->write_actual);
168                 }
169         }
170         q->need_update = 0;
171
172  exit_unlock:
173         spin_unlock_irqrestore(&q->lock, flags);
174 }
175
176 /**
177  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
178  */
179 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
180 {
181         return cpu_to_le32((u32)(dma_addr >> 8));
182 }
183
184 /**
185  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
186  *
187  * If there are slots in the RX queue that need to be restocked,
188  * and we have free pre-allocated buffers, fill the ranks as much
189  * as we can, pulling from rx_free.
190  *
191  * This moves the 'write' index forward to catch up with 'processed', and
192  * also updates the memory address in the firmware to reference the new
193  * target buffer.
194  */
195 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
196 {
197         struct iwl_trans_pcie *trans_pcie =
198                 IWL_TRANS_GET_PCIE_TRANS(trans);
199
200         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
201         struct list_head *element;
202         struct iwl_rx_mem_buffer *rxb;
203         unsigned long flags;
204
205         spin_lock_irqsave(&rxq->lock, flags);
206         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
207                 /* The overwritten rxb must be a used one */
208                 rxb = rxq->queue[rxq->write];
209                 BUG_ON(rxb && rxb->page);
210
211                 /* Get next free Rx buffer, remove from free list */
212                 element = rxq->rx_free.next;
213                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
214                 list_del(element);
215
216                 /* Point to Rx buffer via next RBD in circular buffer */
217                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
218                 rxq->queue[rxq->write] = rxb;
219                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
220                 rxq->free_count--;
221         }
222         spin_unlock_irqrestore(&rxq->lock, flags);
223         /* If the pre-allocated buffer pool is dropping low, schedule to
224          * refill it */
225         if (rxq->free_count <= RX_LOW_WATERMARK)
226                 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
227
228
229         /* If we've added more space for the firmware to place data, tell it.
230          * Increment device's write pointer in multiples of 8. */
231         if (rxq->write_actual != (rxq->write & ~0x7)) {
232                 spin_lock_irqsave(&rxq->lock, flags);
233                 rxq->need_update = 1;
234                 spin_unlock_irqrestore(&rxq->lock, flags);
235                 iwl_rx_queue_update_write_ptr(trans, rxq);
236         }
237 }
238
239 /**
240  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
241  *
242  * When moving to rx_free an SKB is allocated for the slot.
243  *
244  * Also restock the Rx queue via iwl_rx_queue_restock.
245  * This is called as a scheduled work item (except for during initialization)
246  */
247 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
248 {
249         struct iwl_trans_pcie *trans_pcie =
250                 IWL_TRANS_GET_PCIE_TRANS(trans);
251
252         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
253         struct list_head *element;
254         struct iwl_rx_mem_buffer *rxb;
255         struct page *page;
256         unsigned long flags;
257         gfp_t gfp_mask = priority;
258
259         while (1) {
260                 spin_lock_irqsave(&rxq->lock, flags);
261                 if (list_empty(&rxq->rx_used)) {
262                         spin_unlock_irqrestore(&rxq->lock, flags);
263                         return;
264                 }
265                 spin_unlock_irqrestore(&rxq->lock, flags);
266
267                 if (rxq->free_count > RX_LOW_WATERMARK)
268                         gfp_mask |= __GFP_NOWARN;
269
270                 if (hw_params(trans).rx_page_order > 0)
271                         gfp_mask |= __GFP_COMP;
272
273                 /* Alloc a new receive buffer */
274                 page = alloc_pages(gfp_mask,
275                                   hw_params(trans).rx_page_order);
276                 if (!page) {
277                         if (net_ratelimit())
278                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
279                                            "order: %d\n",
280                                            hw_params(trans).rx_page_order);
281
282                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
283                             net_ratelimit())
284                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
285                                          "Only %u free buffers remaining.\n",
286                                          priority == GFP_ATOMIC ?
287                                          "GFP_ATOMIC" : "GFP_KERNEL",
288                                          rxq->free_count);
289                         /* We don't reschedule replenish work here -- we will
290                          * call the restock method and if it still needs
291                          * more buffers it will schedule replenish */
292                         return;
293                 }
294
295                 spin_lock_irqsave(&rxq->lock, flags);
296
297                 if (list_empty(&rxq->rx_used)) {
298                         spin_unlock_irqrestore(&rxq->lock, flags);
299                         __free_pages(page, hw_params(trans).rx_page_order);
300                         return;
301                 }
302                 element = rxq->rx_used.next;
303                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
304                 list_del(element);
305
306                 spin_unlock_irqrestore(&rxq->lock, flags);
307
308                 BUG_ON(rxb->page);
309                 rxb->page = page;
310                 /* Get physical address of the RB */
311                 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
312                                 PAGE_SIZE << hw_params(trans).rx_page_order,
313                                 DMA_FROM_DEVICE);
314                 /* dma address must be no more than 36 bits */
315                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
316                 /* and also 256 byte aligned! */
317                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
318
319                 spin_lock_irqsave(&rxq->lock, flags);
320
321                 list_add_tail(&rxb->list, &rxq->rx_free);
322                 rxq->free_count++;
323
324                 spin_unlock_irqrestore(&rxq->lock, flags);
325         }
326 }
327
328 void iwlagn_rx_replenish(struct iwl_trans *trans)
329 {
330         unsigned long flags;
331
332         iwlagn_rx_allocate(trans, GFP_KERNEL);
333
334         spin_lock_irqsave(&trans->shrd->lock, flags);
335         iwlagn_rx_queue_restock(trans);
336         spin_unlock_irqrestore(&trans->shrd->lock, flags);
337 }
338
339 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
340 {
341         iwlagn_rx_allocate(trans, GFP_ATOMIC);
342
343         iwlagn_rx_queue_restock(trans);
344 }
345
346 void iwl_bg_rx_replenish(struct work_struct *data)
347 {
348         struct iwl_trans_pcie *trans_pcie =
349             container_of(data, struct iwl_trans_pcie, rx_replenish);
350         struct iwl_trans *trans = trans_pcie->trans;
351
352         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
353                 return;
354
355         mutex_lock(&trans->shrd->mutex);
356         iwlagn_rx_replenish(trans);
357         mutex_unlock(&trans->shrd->mutex);
358 }
359
360 /**
361  * iwl_rx_handle - Main entry function for receiving responses from uCode
362  *
363  * Uses the priv->rx_handlers callback function array to invoke
364  * the appropriate handlers, including command responses,
365  * frame-received notifications, and other notifications.
366  */
367 static void iwl_rx_handle(struct iwl_trans *trans)
368 {
369         struct iwl_rx_mem_buffer *rxb;
370         struct iwl_rx_packet *pkt;
371         struct iwl_trans_pcie *trans_pcie =
372                 IWL_TRANS_GET_PCIE_TRANS(trans);
373         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
374         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
375         struct iwl_device_cmd *cmd;
376         u32 r, i;
377         int reclaim;
378         unsigned long flags;
379         u8 fill_rx = 0;
380         u32 count = 8;
381         int total_empty;
382         int index, cmd_index;
383
384         /* uCode's read index (stored in shared DRAM) indicates the last Rx
385          * buffer that the driver may process (last buffer filled by ucode). */
386         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
387         i = rxq->read;
388
389         /* Rx interrupt, but nothing sent from uCode */
390         if (i == r)
391                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
392
393         /* calculate total frames need to be restock after handling RX */
394         total_empty = r - rxq->write_actual;
395         if (total_empty < 0)
396                 total_empty += RX_QUEUE_SIZE;
397
398         if (total_empty > (RX_QUEUE_SIZE / 2))
399                 fill_rx = 1;
400
401         while (i != r) {
402                 int len, err;
403                 u16 sequence;
404
405                 rxb = rxq->queue[i];
406
407                 /* If an RXB doesn't have a Rx queue slot associated with it,
408                  * then a bug has been introduced in the queue refilling
409                  * routines -- catch it here */
410                 if (WARN_ON(rxb == NULL)) {
411                         i = (i + 1) & RX_QUEUE_MASK;
412                         continue;
413                 }
414
415                 rxq->queue[i] = NULL;
416
417                 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
418                                PAGE_SIZE << hw_params(trans).rx_page_order,
419                                DMA_FROM_DEVICE);
420                 pkt = rxb_addr(rxb);
421
422                 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
423                         i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
424
425                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
426                 len += sizeof(u32); /* account for status word */
427                 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
428
429                 /* Reclaim a command buffer only if this packet is a response
430                  *   to a (driver-originated) command.
431                  * If the packet (e.g. Rx frame) originated from uCode,
432                  *   there is no command buffer to reclaim.
433                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
434                  *   but apparently a few don't get set; catch them here. */
435                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
436                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
437                         (pkt->hdr.cmd != REPLY_RX) &&
438                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
439                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
440                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
441                         (pkt->hdr.cmd != REPLY_TX);
442
443                 sequence = le16_to_cpu(pkt->hdr.sequence);
444                 index = SEQ_TO_INDEX(sequence);
445                 cmd_index = get_cmd_index(&txq->q, index);
446
447                 if (reclaim)
448                         cmd = txq->cmd[cmd_index];
449                 else
450                         cmd = NULL;
451
452                 /* warn if this is cmd response / notification and the uCode
453                  * didn't set the SEQ_RX_FRAME for a frame that is
454                  * uCode-originated
455                  * If you saw this code after the second half of 2012, then
456                  * please remove it
457                  */
458                 WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false &&
459                      (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
460                      "reclaim is false, SEQ_RX_FRAME unset: %s\n",
461                      get_cmd_string(pkt->hdr.cmd));
462
463                 err = iwl_rx_dispatch(priv(trans), rxb, cmd);
464
465                 /*
466                  * XXX: After here, we should always check rxb->page
467                  * against NULL before touching it or its virtual
468                  * memory (pkt). Because some rx_handler might have
469                  * already taken or freed the pages.
470                  */
471
472                 if (reclaim) {
473                         /* Invoke any callbacks, transfer the buffer to caller,
474                          * and fire off the (possibly) blocking
475                          * iwl_trans_send_cmd()
476                          * as we reclaim the driver command queue */
477                         if (rxb->page)
478                                 iwl_tx_cmd_complete(trans, rxb, err);
479                         else
480                                 IWL_WARN(trans, "Claim null rxb?\n");
481                 }
482
483                 /* Reuse the page if possible. For notification packets and
484                  * SKBs that fail to Rx correctly, add them back into the
485                  * rx_free list for reuse later. */
486                 spin_lock_irqsave(&rxq->lock, flags);
487                 if (rxb->page != NULL) {
488                         rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
489                                 0, PAGE_SIZE <<
490                                     hw_params(trans).rx_page_order,
491                                 DMA_FROM_DEVICE);
492                         list_add_tail(&rxb->list, &rxq->rx_free);
493                         rxq->free_count++;
494                 } else
495                         list_add_tail(&rxb->list, &rxq->rx_used);
496
497                 spin_unlock_irqrestore(&rxq->lock, flags);
498
499                 i = (i + 1) & RX_QUEUE_MASK;
500                 /* If there are a lot of unused frames,
501                  * restock the Rx queue so ucode wont assert. */
502                 if (fill_rx) {
503                         count++;
504                         if (count >= 8) {
505                                 rxq->read = i;
506                                 iwlagn_rx_replenish_now(trans);
507                                 count = 0;
508                         }
509                 }
510         }
511
512         /* Backtrack one entry */
513         rxq->read = i;
514         if (fill_rx)
515                 iwlagn_rx_replenish_now(trans);
516         else
517                 iwlagn_rx_queue_restock(trans);
518 }
519
520 static const char * const desc_lookup_text[] = {
521         "OK",
522         "FAIL",
523         "BAD_PARAM",
524         "BAD_CHECKSUM",
525         "NMI_INTERRUPT_WDG",
526         "SYSASSERT",
527         "FATAL_ERROR",
528         "BAD_COMMAND",
529         "HW_ERROR_TUNE_LOCK",
530         "HW_ERROR_TEMPERATURE",
531         "ILLEGAL_CHAN_FREQ",
532         "VCC_NOT_STABLE",
533         "FH_ERROR",
534         "NMI_INTERRUPT_HOST",
535         "NMI_INTERRUPT_ACTION_PT",
536         "NMI_INTERRUPT_UNKNOWN",
537         "UCODE_VERSION_MISMATCH",
538         "HW_ERROR_ABS_LOCK",
539         "HW_ERROR_CAL_LOCK_FAIL",
540         "NMI_INTERRUPT_INST_ACTION_PT",
541         "NMI_INTERRUPT_DATA_ACTION_PT",
542         "NMI_TRM_HW_ER",
543         "NMI_INTERRUPT_TRM",
544         "NMI_INTERRUPT_BREAK_POINT",
545         "DEBUG_0",
546         "DEBUG_1",
547         "DEBUG_2",
548         "DEBUG_3",
549 };
550
551 static struct { char *name; u8 num; } advanced_lookup[] = {
552         { "NMI_INTERRUPT_WDG", 0x34 },
553         { "SYSASSERT", 0x35 },
554         { "UCODE_VERSION_MISMATCH", 0x37 },
555         { "BAD_COMMAND", 0x38 },
556         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
557         { "FATAL_ERROR", 0x3D },
558         { "NMI_TRM_HW_ERR", 0x46 },
559         { "NMI_INTERRUPT_TRM", 0x4C },
560         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
561         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
562         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
563         { "NMI_INTERRUPT_HOST", 0x66 },
564         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
565         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
566         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
567         { "ADVANCED_SYSASSERT", 0 },
568 };
569
570 static const char *desc_lookup(u32 num)
571 {
572         int i;
573         int max = ARRAY_SIZE(desc_lookup_text);
574
575         if (num < max)
576                 return desc_lookup_text[num];
577
578         max = ARRAY_SIZE(advanced_lookup) - 1;
579         for (i = 0; i < max; i++) {
580                 if (advanced_lookup[i].num == num)
581                         break;
582         }
583         return advanced_lookup[i].name;
584 }
585
586 #define ERROR_START_OFFSET  (1 * sizeof(u32))
587 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
588
589 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
590 {
591         u32 base;
592         struct iwl_error_event_table table;
593         struct iwl_priv *priv = priv(trans);
594         struct iwl_trans_pcie *trans_pcie =
595                 IWL_TRANS_GET_PCIE_TRANS(trans);
596
597         base = trans->shrd->device_pointers.error_event_table;
598         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
599                 if (!base)
600                         base = priv->init_errlog_ptr;
601         } else {
602                 if (!base)
603                         base = priv->inst_errlog_ptr;
604         }
605
606         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
607                 IWL_ERR(trans,
608                         "Not valid error log pointer 0x%08X for %s uCode\n",
609                         base,
610                         (trans->shrd->ucode_type == IWL_UCODE_INIT)
611                                         ? "Init" : "RT");
612                 return;
613         }
614
615         iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table));
616
617         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
618                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
619                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
620                         trans->shrd->status, table.valid);
621         }
622
623         trans_pcie->isr_stats.err_code = table.error_id;
624
625         trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
626                                       table.data1, table.data2, table.line,
627                                       table.blink1, table.blink2, table.ilink1,
628                                       table.ilink2, table.bcon_time, table.gp1,
629                                       table.gp2, table.gp3, table.ucode_ver,
630                                       table.hw_ver, table.brd_ver);
631         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
632                 desc_lookup(table.error_id));
633         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
634         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
635         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
636         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
637         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
638         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
639         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
640         IWL_ERR(trans, "0x%08X | line\n", table.line);
641         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
642         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
643         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
644         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
645         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
646         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
647         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
648         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
649         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
650         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
651
652         IWL_ERR(trans, "0x%08X | isr0\n", table.isr0);
653         IWL_ERR(trans, "0x%08X | isr1\n", table.isr1);
654         IWL_ERR(trans, "0x%08X | isr2\n", table.isr2);
655         IWL_ERR(trans, "0x%08X | isr3\n", table.isr3);
656         IWL_ERR(trans, "0x%08X | isr4\n", table.isr4);
657         IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref);
658         IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event);
659         IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control);
660         IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration);
661         IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
662         IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
663         IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
664         IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp);
665         IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler);
666 }
667
668 /**
669  * iwl_irq_handle_error - called for HW or SW error interrupt from card
670  */
671 static void iwl_irq_handle_error(struct iwl_trans *trans)
672 {
673         struct iwl_priv *priv = priv(trans);
674         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
675         if (cfg(priv)->internal_wimax_coex &&
676             (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
677                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
678              (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
679                         APMG_PS_CTRL_VAL_RESET_REQ))) {
680                 /*
681                  * Keep the restart process from trying to send host
682                  * commands by clearing the ready bit.
683                  */
684                 clear_bit(STATUS_READY, &trans->shrd->status);
685                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
686                 wake_up(&priv->shrd->wait_command_queue);
687                 IWL_ERR(trans, "RF is used by WiMAX\n");
688                 return;
689         }
690
691         IWL_ERR(trans, "Loaded firmware version: %s\n",
692                 priv->hw->wiphy->fw_version);
693
694         iwl_dump_nic_error_log(trans);
695         iwl_dump_csr(trans);
696         iwl_dump_fh(trans, NULL, false);
697         iwl_dump_nic_event_log(trans, false, NULL, false);
698 #ifdef CONFIG_IWLWIFI_DEBUG
699         if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
700                 iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS);
701 #endif
702
703         iwlagn_fw_error(priv, false);
704 }
705
706 #define EVENT_START_OFFSET  (4 * sizeof(u32))
707
708 /**
709  * iwl_print_event_log - Dump error event log to syslog
710  *
711  */
712 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
713                                u32 num_events, u32 mode,
714                                int pos, char **buf, size_t bufsz)
715 {
716         u32 i;
717         u32 base;       /* SRAM byte address of event log header */
718         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
719         u32 ptr;        /* SRAM byte address of log data */
720         u32 ev, time, data; /* event log data */
721         unsigned long reg_flags;
722         struct iwl_priv *priv = priv(trans);
723
724         if (num_events == 0)
725                 return pos;
726
727         base = trans->shrd->device_pointers.log_event_table;
728         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
729                 if (!base)
730                         base = priv->init_evtlog_ptr;
731         } else {
732                 if (!base)
733                         base = priv->inst_evtlog_ptr;
734         }
735
736         if (mode == 0)
737                 event_size = 2 * sizeof(u32);
738         else
739                 event_size = 3 * sizeof(u32);
740
741         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
742
743         /* Make sure device is powered up for SRAM reads */
744         spin_lock_irqsave(&bus(trans)->reg_lock, reg_flags);
745         iwl_grab_nic_access(bus(trans));
746
747         /* Set starting address; reads will auto-increment */
748         iwl_write32(bus(trans), HBUS_TARG_MEM_RADDR, ptr);
749         rmb();
750
751         /* "time" is actually "data" for mode 0 (no timestamp).
752         * place event id # at far right for easier visual parsing. */
753         for (i = 0; i < num_events; i++) {
754                 ev = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
755                 time = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
756                 if (mode == 0) {
757                         /* data, ev */
758                         if (bufsz) {
759                                 pos += scnprintf(*buf + pos, bufsz - pos,
760                                                 "EVT_LOG:0x%08x:%04u\n",
761                                                 time, ev);
762                         } else {
763                                 trace_iwlwifi_dev_ucode_event(priv, 0,
764                                         time, ev);
765                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
766                                         time, ev);
767                         }
768                 } else {
769                         data = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
770                         if (bufsz) {
771                                 pos += scnprintf(*buf + pos, bufsz - pos,
772                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
773                                                  time, data, ev);
774                         } else {
775                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
776                                         time, data, ev);
777                                 trace_iwlwifi_dev_ucode_event(priv, time,
778                                         data, ev);
779                         }
780                 }
781         }
782
783         /* Allow device to power down */
784         iwl_release_nic_access(bus(trans));
785         spin_unlock_irqrestore(&bus(trans)->reg_lock, reg_flags);
786         return pos;
787 }
788
789 /**
790  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
791  */
792 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
793                                     u32 num_wraps, u32 next_entry,
794                                     u32 size, u32 mode,
795                                     int pos, char **buf, size_t bufsz)
796 {
797         /*
798          * display the newest DEFAULT_LOG_ENTRIES entries
799          * i.e the entries just before the next ont that uCode would fill.
800          */
801         if (num_wraps) {
802                 if (next_entry < size) {
803                         pos = iwl_print_event_log(trans,
804                                                 capacity - (size - next_entry),
805                                                 size - next_entry, mode,
806                                                 pos, buf, bufsz);
807                         pos = iwl_print_event_log(trans, 0,
808                                                   next_entry, mode,
809                                                   pos, buf, bufsz);
810                 } else
811                         pos = iwl_print_event_log(trans, next_entry - size,
812                                                   size, mode, pos, buf, bufsz);
813         } else {
814                 if (next_entry < size) {
815                         pos = iwl_print_event_log(trans, 0, next_entry,
816                                                   mode, pos, buf, bufsz);
817                 } else {
818                         pos = iwl_print_event_log(trans, next_entry - size,
819                                                   size, mode, pos, buf, bufsz);
820                 }
821         }
822         return pos;
823 }
824
825 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
826
827 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
828                             char **buf, bool display)
829 {
830         u32 base;       /* SRAM byte address of event log header */
831         u32 capacity;   /* event log capacity in # entries */
832         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
833         u32 num_wraps;  /* # times uCode wrapped to top of log */
834         u32 next_entry; /* index of next entry to be written by uCode */
835         u32 size;       /* # entries that we'll print */
836         u32 logsize;
837         int pos = 0;
838         size_t bufsz = 0;
839         struct iwl_priv *priv = priv(trans);
840
841         base = trans->shrd->device_pointers.log_event_table;
842         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
843                 logsize = priv->init_evtlog_size;
844                 if (!base)
845                         base = priv->init_evtlog_ptr;
846         } else {
847                 logsize = priv->inst_evtlog_size;
848                 if (!base)
849                         base = priv->inst_evtlog_ptr;
850         }
851
852         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
853                 IWL_ERR(trans,
854                         "Invalid event log pointer 0x%08X for %s uCode\n",
855                         base,
856                         (trans->shrd->ucode_type == IWL_UCODE_INIT)
857                                         ? "Init" : "RT");
858                 return -EINVAL;
859         }
860
861         /* event log header */
862         capacity = iwl_read_targ_mem(bus(trans), base);
863         mode = iwl_read_targ_mem(bus(trans), base + (1 * sizeof(u32)));
864         num_wraps = iwl_read_targ_mem(bus(trans), base + (2 * sizeof(u32)));
865         next_entry = iwl_read_targ_mem(bus(trans), base + (3 * sizeof(u32)));
866
867         if (capacity > logsize) {
868                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
869                         "entries\n", capacity, logsize);
870                 capacity = logsize;
871         }
872
873         if (next_entry > logsize) {
874                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
875                         next_entry, logsize);
876                 next_entry = logsize;
877         }
878
879         size = num_wraps ? capacity : next_entry;
880
881         /* bail out if nothing in log */
882         if (size == 0) {
883                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
884                 return pos;
885         }
886
887 #ifdef CONFIG_IWLWIFI_DEBUG
888         if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
889                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
890                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
891 #else
892         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
893                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
894 #endif
895         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
896                 size);
897
898 #ifdef CONFIG_IWLWIFI_DEBUG
899         if (display) {
900                 if (full_log)
901                         bufsz = capacity * 48;
902                 else
903                         bufsz = size * 48;
904                 *buf = kmalloc(bufsz, GFP_KERNEL);
905                 if (!*buf)
906                         return -ENOMEM;
907         }
908         if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
909                 /*
910                  * if uCode has wrapped back to top of log,
911                  * start at the oldest entry,
912                  * i.e the next one that uCode would fill.
913                  */
914                 if (num_wraps)
915                         pos = iwl_print_event_log(trans, next_entry,
916                                                 capacity - next_entry, mode,
917                                                 pos, buf, bufsz);
918                 /* (then/else) start at top of log */
919                 pos = iwl_print_event_log(trans, 0,
920                                           next_entry, mode, pos, buf, bufsz);
921         } else
922                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
923                                                 next_entry, size, mode,
924                                                 pos, buf, bufsz);
925 #else
926         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
927                                         next_entry, size, mode,
928                                         pos, buf, bufsz);
929 #endif
930         return pos;
931 }
932
933 /* tasklet for iwlagn interrupt */
934 void iwl_irq_tasklet(struct iwl_trans *trans)
935 {
936         u32 inta = 0;
937         u32 handled = 0;
938         unsigned long flags;
939         u32 i;
940 #ifdef CONFIG_IWLWIFI_DEBUG
941         u32 inta_mask;
942 #endif
943
944         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
945         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
946
947
948         spin_lock_irqsave(&trans->shrd->lock, flags);
949
950         /* Ack/clear/reset pending uCode interrupts.
951          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
952          */
953         /* There is a hardware bug in the interrupt mask function that some
954          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
955          * they are disabled in the CSR_INT_MASK register. Furthermore the
956          * ICT interrupt handling mechanism has another bug that might cause
957          * these unmasked interrupts fail to be detected. We workaround the
958          * hardware bugs here by ACKing all the possible interrupts so that
959          * interrupt coalescing can still be achieved.
960          */
961         iwl_write32(bus(trans), CSR_INT,
962                 trans_pcie->inta | ~trans_pcie->inta_mask);
963
964         inta = trans_pcie->inta;
965
966 #ifdef CONFIG_IWLWIFI_DEBUG
967         if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
968                 /* just for debug */
969                 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
970                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
971                                 inta, inta_mask);
972         }
973 #endif
974
975         spin_unlock_irqrestore(&trans->shrd->lock, flags);
976
977         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
978         trans_pcie->inta = 0;
979
980         /* Now service all interrupt bits discovered above. */
981         if (inta & CSR_INT_BIT_HW_ERR) {
982                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
983
984                 /* Tell the device to stop sending interrupts */
985                 iwl_disable_interrupts(trans);
986
987                 isr_stats->hw++;
988                 iwl_irq_handle_error(trans);
989
990                 handled |= CSR_INT_BIT_HW_ERR;
991
992                 return;
993         }
994
995 #ifdef CONFIG_IWLWIFI_DEBUG
996         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
997                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
998                 if (inta & CSR_INT_BIT_SCD) {
999                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
1000                                       "the frame/frames.\n");
1001                         isr_stats->sch++;
1002                 }
1003
1004                 /* Alive notification via Rx interrupt will do the real work */
1005                 if (inta & CSR_INT_BIT_ALIVE) {
1006                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1007                         isr_stats->alive++;
1008                 }
1009         }
1010 #endif
1011         /* Safely ignore these bits for debug checks below */
1012         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1013
1014         /* HW RF KILL switch toggled */
1015         if (inta & CSR_INT_BIT_RF_KILL) {
1016                 int hw_rf_kill = 0;
1017                 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1018                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1019                         hw_rf_kill = 1;
1020
1021                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1022                                 hw_rf_kill ? "disable radio" : "enable radio");
1023
1024                 isr_stats->rfkill++;
1025
1026                 /* driver only loads ucode once setting the interface up.
1027                  * the driver allows loading the ucode even if the radio
1028                  * is killed. Hence update the killswitch state here. The
1029                  * rfkill handler will care about restarting if needed.
1030                  */
1031                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1032                         if (hw_rf_kill)
1033                                 set_bit(STATUS_RF_KILL_HW,
1034                                         &trans->shrd->status);
1035                         else
1036                                 clear_bit(STATUS_RF_KILL_HW,
1037                                           &trans->shrd->status);
1038                         iwl_set_hw_rfkill_state(priv(trans), hw_rf_kill);
1039                 }
1040
1041                 handled |= CSR_INT_BIT_RF_KILL;
1042         }
1043
1044         /* Chip got too hot and stopped itself */
1045         if (inta & CSR_INT_BIT_CT_KILL) {
1046                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1047                 isr_stats->ctkill++;
1048                 handled |= CSR_INT_BIT_CT_KILL;
1049         }
1050
1051         /* Error detected by uCode */
1052         if (inta & CSR_INT_BIT_SW_ERR) {
1053                 IWL_ERR(trans, "Microcode SW error detected. "
1054                         " Restarting 0x%X.\n", inta);
1055                 isr_stats->sw++;
1056                 iwl_irq_handle_error(trans);
1057                 handled |= CSR_INT_BIT_SW_ERR;
1058         }
1059
1060         /* uCode wakes up after power-down sleep */
1061         if (inta & CSR_INT_BIT_WAKEUP) {
1062                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1063                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1064                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1065                         iwl_txq_update_write_ptr(trans,
1066                                                  &trans_pcie->txq[i]);
1067
1068                 isr_stats->wakeup++;
1069
1070                 handled |= CSR_INT_BIT_WAKEUP;
1071         }
1072
1073         /* All uCode command responses, including Tx command responses,
1074          * Rx "responses" (frame-received notification), and other
1075          * notifications from uCode come through here*/
1076         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1077                         CSR_INT_BIT_RX_PERIODIC)) {
1078                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1079                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1080                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1081                         iwl_write32(bus(trans), CSR_FH_INT_STATUS,
1082                                         CSR_FH_INT_RX_MASK);
1083                 }
1084                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1085                         handled |= CSR_INT_BIT_RX_PERIODIC;
1086                         iwl_write32(bus(trans),
1087                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1088                 }
1089                 /* Sending RX interrupt require many steps to be done in the
1090                  * the device:
1091                  * 1- write interrupt to current index in ICT table.
1092                  * 2- dma RX frame.
1093                  * 3- update RX shared data to indicate last write index.
1094                  * 4- send interrupt.
1095                  * This could lead to RX race, driver could receive RX interrupt
1096                  * but the shared data changes does not reflect this;
1097                  * periodic interrupt will detect any dangling Rx activity.
1098                  */
1099
1100                 /* Disable periodic interrupt; we use it as just a one-shot. */
1101                 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1102                             CSR_INT_PERIODIC_DIS);
1103                 iwl_rx_handle(trans);
1104
1105                 /*
1106                  * Enable periodic interrupt in 8 msec only if we received
1107                  * real RX interrupt (instead of just periodic int), to catch
1108                  * any dangling Rx interrupt.  If it was just the periodic
1109                  * interrupt, there was no dangling Rx activity, and no need
1110                  * to extend the periodic interrupt; one-shot is enough.
1111                  */
1112                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1113                         iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1114                                     CSR_INT_PERIODIC_ENA);
1115
1116                 isr_stats->rx++;
1117         }
1118
1119         /* This "Tx" DMA channel is used only for loading uCode */
1120         if (inta & CSR_INT_BIT_FH_TX) {
1121                 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1122                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1123                 isr_stats->tx++;
1124                 handled |= CSR_INT_BIT_FH_TX;
1125                 /* Wake up uCode load routine, now that load is complete */
1126                 trans->ucode_write_complete = 1;
1127                 wake_up(&trans->shrd->wait_command_queue);
1128         }
1129
1130         if (inta & ~handled) {
1131                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1132                 isr_stats->unhandled++;
1133         }
1134
1135         if (inta & ~(trans_pcie->inta_mask)) {
1136                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1137                          inta & ~trans_pcie->inta_mask);
1138         }
1139
1140         /* Re-enable all interrupts */
1141         /* only Re-enable if disabled by irq */
1142         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1143                 iwl_enable_interrupts(trans);
1144         /* Re-enable RF_KILL if it occurred */
1145         else if (handled & CSR_INT_BIT_RF_KILL)
1146                 iwl_enable_rfkill_int(priv(trans));
1147 }
1148
1149 /******************************************************************************
1150  *
1151  * ICT functions
1152  *
1153  ******************************************************************************/
1154
1155 /* a device (PCI-E) page is 4096 bytes long */
1156 #define ICT_SHIFT       12
1157 #define ICT_SIZE        (1 << ICT_SHIFT)
1158 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1159
1160 /* Free dram table */
1161 void iwl_free_isr_ict(struct iwl_trans *trans)
1162 {
1163         struct iwl_trans_pcie *trans_pcie =
1164                 IWL_TRANS_GET_PCIE_TRANS(trans);
1165
1166         if (trans_pcie->ict_tbl) {
1167                 dma_free_coherent(bus(trans)->dev, ICT_SIZE,
1168                                   trans_pcie->ict_tbl,
1169                                   trans_pcie->ict_tbl_dma);
1170                 trans_pcie->ict_tbl = NULL;
1171                 trans_pcie->ict_tbl_dma = 0;
1172         }
1173 }
1174
1175
1176 /*
1177  * allocate dram shared table, it is an aligned memory
1178  * block of ICT_SIZE.
1179  * also reset all data related to ICT table interrupt.
1180  */
1181 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1182 {
1183         struct iwl_trans_pcie *trans_pcie =
1184                 IWL_TRANS_GET_PCIE_TRANS(trans);
1185
1186         trans_pcie->ict_tbl =
1187                 dma_alloc_coherent(bus(trans)->dev, ICT_SIZE,
1188                                    &trans_pcie->ict_tbl_dma,
1189                                    GFP_KERNEL);
1190         if (!trans_pcie->ict_tbl)
1191                 return -ENOMEM;
1192
1193         /* just an API sanity check ... it is guaranteed to be aligned */
1194         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1195                 iwl_free_isr_ict(trans);
1196                 return -EINVAL;
1197         }
1198
1199         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1200                       (unsigned long long)trans_pcie->ict_tbl_dma);
1201
1202         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1203
1204         /* reset table and index to all 0 */
1205         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1206         trans_pcie->ict_index = 0;
1207
1208         /* add periodic RX interrupt */
1209         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1210         return 0;
1211 }
1212
1213 /* Device is going up inform it about using ICT interrupt table,
1214  * also we need to tell the driver to start using ICT interrupt.
1215  */
1216 int iwl_reset_ict(struct iwl_trans *trans)
1217 {
1218         u32 val;
1219         unsigned long flags;
1220         struct iwl_trans_pcie *trans_pcie =
1221                 IWL_TRANS_GET_PCIE_TRANS(trans);
1222
1223         if (!trans_pcie->ict_tbl)
1224                 return 0;
1225
1226         spin_lock_irqsave(&trans->shrd->lock, flags);
1227         iwl_disable_interrupts(trans);
1228
1229         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1230
1231         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1232
1233         val |= CSR_DRAM_INT_TBL_ENABLE;
1234         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1235
1236         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1237
1238         iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
1239         trans_pcie->use_ict = true;
1240         trans_pcie->ict_index = 0;
1241         iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
1242         iwl_enable_interrupts(trans);
1243         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1244
1245         return 0;
1246 }
1247
1248 /* Device is going down disable ict interrupt usage */
1249 void iwl_disable_ict(struct iwl_trans *trans)
1250 {
1251         struct iwl_trans_pcie *trans_pcie =
1252                 IWL_TRANS_GET_PCIE_TRANS(trans);
1253
1254         unsigned long flags;
1255
1256         spin_lock_irqsave(&trans->shrd->lock, flags);
1257         trans_pcie->use_ict = false;
1258         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1259 }
1260
1261 static irqreturn_t iwl_isr(int irq, void *data)
1262 {
1263         struct iwl_trans *trans = data;
1264         struct iwl_trans_pcie *trans_pcie;
1265         u32 inta, inta_mask;
1266         unsigned long flags;
1267 #ifdef CONFIG_IWLWIFI_DEBUG
1268         u32 inta_fh;
1269 #endif
1270         if (!trans)
1271                 return IRQ_NONE;
1272
1273         trace_iwlwifi_dev_irq(priv(trans));
1274
1275         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1276
1277         spin_lock_irqsave(&trans->shrd->lock, flags);
1278
1279         /* Disable (but don't clear!) interrupts here to avoid
1280          *    back-to-back ISRs and sporadic interrupts from our NIC.
1281          * If we have something to service, the tasklet will re-enable ints.
1282          * If we *don't* have something, we'll re-enable before leaving here. */
1283         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);  /* just for debug */
1284         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1285
1286         /* Discover which interrupts are active/pending */
1287         inta = iwl_read32(bus(trans), CSR_INT);
1288
1289         /* Ignore interrupt if there's nothing in NIC to service.
1290          * This may be due to IRQ shared with another device,
1291          * or due to sporadic interrupts thrown from our NIC. */
1292         if (!inta) {
1293                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1294                 goto none;
1295         }
1296
1297         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1298                 /* Hardware disappeared. It might have already raised
1299                  * an interrupt */
1300                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1301                 goto unplugged;
1302         }
1303
1304 #ifdef CONFIG_IWLWIFI_DEBUG
1305         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1306                 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS);
1307                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1308                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1309         }
1310 #endif
1311
1312         trans_pcie->inta |= inta;
1313         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1314         if (likely(inta))
1315                 tasklet_schedule(&trans_pcie->irq_tasklet);
1316         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1317                         !trans_pcie->inta)
1318                 iwl_enable_interrupts(trans);
1319
1320  unplugged:
1321         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1322         return IRQ_HANDLED;
1323
1324  none:
1325         /* re-enable interrupts here since we don't have anything to service. */
1326         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1327         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1328                 !trans_pcie->inta)
1329                 iwl_enable_interrupts(trans);
1330
1331         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1332         return IRQ_NONE;
1333 }
1334
1335 /* interrupt handler using ict table, with this interrupt driver will
1336  * stop using INTA register to get device's interrupt, reading this register
1337  * is expensive, device will write interrupts in ICT dram table, increment
1338  * index then will fire interrupt to driver, driver will OR all ICT table
1339  * entries from current index up to table entry with 0 value. the result is
1340  * the interrupt we need to service, driver will set the entries back to 0 and
1341  * set index.
1342  */
1343 irqreturn_t iwl_isr_ict(int irq, void *data)
1344 {
1345         struct iwl_trans *trans = data;
1346         struct iwl_trans_pcie *trans_pcie;
1347         u32 inta, inta_mask;
1348         u32 val = 0;
1349         u32 read;
1350         unsigned long flags;
1351
1352         if (!trans)
1353                 return IRQ_NONE;
1354
1355         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1356
1357         /* dram interrupt table not set yet,
1358          * use legacy interrupt.
1359          */
1360         if (!trans_pcie->use_ict)
1361                 return iwl_isr(irq, data);
1362
1363         trace_iwlwifi_dev_irq(priv(trans));
1364
1365         spin_lock_irqsave(&trans->shrd->lock, flags);
1366
1367         /* Disable (but don't clear!) interrupts here to avoid
1368          * back-to-back ISRs and sporadic interrupts from our NIC.
1369          * If we have something to service, the tasklet will re-enable ints.
1370          * If we *don't* have something, we'll re-enable before leaving here.
1371          */
1372         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);  /* just for debug */
1373         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1374
1375
1376         /* Ignore interrupt if there's nothing in NIC to service.
1377          * This may be due to IRQ shared with another device,
1378          * or due to sporadic interrupts thrown from our NIC. */
1379         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1380         trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index, read);
1381         if (!read) {
1382                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1383                 goto none;
1384         }
1385
1386         /*
1387          * Collect all entries up to the first 0, starting from ict_index;
1388          * note we already read at ict_index.
1389          */
1390         do {
1391                 val |= read;
1392                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1393                                 trans_pcie->ict_index, read);
1394                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1395                 trans_pcie->ict_index =
1396                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1397
1398                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1399                 trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index,
1400                                            read);
1401         } while (read);
1402
1403         /* We should not get this value, just ignore it. */
1404         if (val == 0xffffffff)
1405                 val = 0;
1406
1407         /*
1408          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1409          * (bit 15 before shifting it to 31) to clear when using interrupt
1410          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1411          * so we use them to decide on the real state of the Rx bit.
1412          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1413          */
1414         if (val & 0xC0000)
1415                 val |= 0x8000;
1416
1417         inta = (0xff & val) | ((0xff00 & val) << 16);
1418         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1419                         inta, inta_mask, val);
1420
1421         inta &= trans_pcie->inta_mask;
1422         trans_pcie->inta |= inta;
1423
1424         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1425         if (likely(inta))
1426                 tasklet_schedule(&trans_pcie->irq_tasklet);
1427         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1428                  !trans_pcie->inta) {
1429                 /* Allow interrupt if was disabled by this handler and
1430                  * no tasklet was schedules, We should not enable interrupt,
1431                  * tasklet will enable it.
1432                  */
1433                 iwl_enable_interrupts(trans);
1434         }
1435
1436         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1437         return IRQ_HANDLED;
1438
1439  none:
1440         /* re-enable interrupts here since we don't have anything to service.
1441          * only Re-enable if disabled by irq.
1442          */
1443         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1444             !trans_pcie->inta)
1445                 iwl_enable_interrupts(trans);
1446
1447         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1448         return IRQ_NONE;
1449 }