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[~shefty/rdma-dev.git] / drivers / pinctrl / pinctrl-sirf.c
1 /*
2  * pinmux driver for CSR SiRFprimaII
3  *
4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5  *
6  * Licensed under GPLv2 or later.
7  */
8
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/irq.h>
12 #include <linux/platform_device.h>
13 #include <linux/io.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
16 #include <linux/irqdomain.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_platform.h>
25 #include <linux/bitops.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
28 #include <asm/mach/irq.h>
29
30 #define DRIVER_NAME "pinmux-sirf"
31
32 #define SIRFSOC_NUM_PADS    622
33 #define SIRFSOC_RSC_PIN_MUX 0x4
34
35 #define SIRFSOC_GPIO_PAD_EN(g)          ((g)*0x100 + 0x84)
36 #define SIRFSOC_GPIO_PAD_EN_CLR(g)      ((g)*0x100 + 0x90)
37 #define SIRFSOC_GPIO_CTRL(g, i)                 ((g)*0x100 + (i)*4)
38 #define SIRFSOC_GPIO_DSP_EN0                    (0x80)
39 #define SIRFSOC_GPIO_INT_STATUS(g)              ((g)*0x100 + 0x8C)
40
41 #define SIRFSOC_GPIO_CTL_INTR_LOW_MASK          0x1
42 #define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK         0x2
43 #define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK         0x4
44 #define SIRFSOC_GPIO_CTL_INTR_EN_MASK           0x8
45 #define SIRFSOC_GPIO_CTL_INTR_STS_MASK          0x10
46 #define SIRFSOC_GPIO_CTL_OUT_EN_MASK            0x20
47 #define SIRFSOC_GPIO_CTL_DATAOUT_MASK           0x40
48 #define SIRFSOC_GPIO_CTL_DATAIN_MASK            0x80
49 #define SIRFSOC_GPIO_CTL_PULL_MASK              0x100
50 #define SIRFSOC_GPIO_CTL_PULL_HIGH              0x200
51 #define SIRFSOC_GPIO_CTL_DSP_INT                0x400
52
53 #define SIRFSOC_GPIO_NO_OF_BANKS        5
54 #define SIRFSOC_GPIO_BANK_SIZE          32
55 #define SIRFSOC_GPIO_NUM(bank, index)   (((bank)*(32)) + (index))
56
57 struct sirfsoc_gpio_bank {
58         struct of_mm_gpio_chip chip;
59         struct irq_domain *domain;
60         int id;
61         int parent_irq;
62         spinlock_t lock;
63         bool is_marco; /* for marco, some registers are different with prima2 */
64 };
65
66 static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
67 static DEFINE_SPINLOCK(sgpio_lock);
68
69 /*
70  * pad list for the pinmux subsystem
71  * refer to CS-131858-DC-6A.xls
72  */
73 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
74         PINCTRL_PIN(0, "gpio0-0"),
75         PINCTRL_PIN(1, "gpio0-1"),
76         PINCTRL_PIN(2, "gpio0-2"),
77         PINCTRL_PIN(3, "gpio0-3"),
78         PINCTRL_PIN(4, "pwm0"),
79         PINCTRL_PIN(5, "pwm1"),
80         PINCTRL_PIN(6, "pwm2"),
81         PINCTRL_PIN(7, "pwm3"),
82         PINCTRL_PIN(8, "warm_rst_b"),
83         PINCTRL_PIN(9, "odo_0"),
84         PINCTRL_PIN(10, "odo_1"),
85         PINCTRL_PIN(11, "dr_dir"),
86         PINCTRL_PIN(12, "viprom_fa"),
87         PINCTRL_PIN(13, "scl_1"),
88         PINCTRL_PIN(14, "ntrst"),
89         PINCTRL_PIN(15, "sda_1"),
90         PINCTRL_PIN(16, "x_ldd[16]"),
91         PINCTRL_PIN(17, "x_ldd[17]"),
92         PINCTRL_PIN(18, "x_ldd[18]"),
93         PINCTRL_PIN(19, "x_ldd[19]"),
94         PINCTRL_PIN(20, "x_ldd[20]"),
95         PINCTRL_PIN(21, "x_ldd[21]"),
96         PINCTRL_PIN(22, "x_ldd[22]"),
97         PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
98         PINCTRL_PIN(24, "gps_sgn"),
99         PINCTRL_PIN(25, "gps_mag"),
100         PINCTRL_PIN(26, "gps_clk"),
101         PINCTRL_PIN(27, "sd_cd_b_1"),
102         PINCTRL_PIN(28, "sd_vcc_on_1"),
103         PINCTRL_PIN(29, "sd_wp_b_1"),
104         PINCTRL_PIN(30, "sd_clk_3"),
105         PINCTRL_PIN(31, "sd_cmd_3"),
106
107         PINCTRL_PIN(32, "x_sd_dat_3[0]"),
108         PINCTRL_PIN(33, "x_sd_dat_3[1]"),
109         PINCTRL_PIN(34, "x_sd_dat_3[2]"),
110         PINCTRL_PIN(35, "x_sd_dat_3[3]"),
111         PINCTRL_PIN(36, "x_sd_clk_4"),
112         PINCTRL_PIN(37, "x_sd_cmd_4"),
113         PINCTRL_PIN(38, "x_sd_dat_4[0]"),
114         PINCTRL_PIN(39, "x_sd_dat_4[1]"),
115         PINCTRL_PIN(40, "x_sd_dat_4[2]"),
116         PINCTRL_PIN(41, "x_sd_dat_4[3]"),
117         PINCTRL_PIN(42, "x_cko_1"),
118         PINCTRL_PIN(43, "x_ac97_bit_clk"),
119         PINCTRL_PIN(44, "x_ac97_dout"),
120         PINCTRL_PIN(45, "x_ac97_din"),
121         PINCTRL_PIN(46, "x_ac97_sync"),
122         PINCTRL_PIN(47, "x_txd_1"),
123         PINCTRL_PIN(48, "x_txd_2"),
124         PINCTRL_PIN(49, "x_rxd_1"),
125         PINCTRL_PIN(50, "x_rxd_2"),
126         PINCTRL_PIN(51, "x_usclk_0"),
127         PINCTRL_PIN(52, "x_utxd_0"),
128         PINCTRL_PIN(53, "x_urxd_0"),
129         PINCTRL_PIN(54, "x_utfs_0"),
130         PINCTRL_PIN(55, "x_urfs_0"),
131         PINCTRL_PIN(56, "x_usclk_1"),
132         PINCTRL_PIN(57, "x_utxd_1"),
133         PINCTRL_PIN(58, "x_urxd_1"),
134         PINCTRL_PIN(59, "x_utfs_1"),
135         PINCTRL_PIN(60, "x_urfs_1"),
136         PINCTRL_PIN(61, "x_usclk_2"),
137         PINCTRL_PIN(62, "x_utxd_2"),
138         PINCTRL_PIN(63, "x_urxd_2"),
139
140         PINCTRL_PIN(64, "x_utfs_2"),
141         PINCTRL_PIN(65, "x_urfs_2"),
142         PINCTRL_PIN(66, "x_df_we_b"),
143         PINCTRL_PIN(67, "x_df_re_b"),
144         PINCTRL_PIN(68, "x_txd_0"),
145         PINCTRL_PIN(69, "x_rxd_0"),
146         PINCTRL_PIN(78, "x_cko_0"),
147         PINCTRL_PIN(79, "x_vip_pxd[7]"),
148         PINCTRL_PIN(80, "x_vip_pxd[6]"),
149         PINCTRL_PIN(81, "x_vip_pxd[5]"),
150         PINCTRL_PIN(82, "x_vip_pxd[4]"),
151         PINCTRL_PIN(83, "x_vip_pxd[3]"),
152         PINCTRL_PIN(84, "x_vip_pxd[2]"),
153         PINCTRL_PIN(85, "x_vip_pxd[1]"),
154         PINCTRL_PIN(86, "x_vip_pxd[0]"),
155         PINCTRL_PIN(87, "x_vip_vsync"),
156         PINCTRL_PIN(88, "x_vip_hsync"),
157         PINCTRL_PIN(89, "x_vip_pxclk"),
158         PINCTRL_PIN(90, "x_sda_0"),
159         PINCTRL_PIN(91, "x_scl_0"),
160         PINCTRL_PIN(92, "x_df_ry_by"),
161         PINCTRL_PIN(93, "x_df_cs_b[1]"),
162         PINCTRL_PIN(94, "x_df_cs_b[0]"),
163         PINCTRL_PIN(95, "x_l_pclk"),
164
165         PINCTRL_PIN(96, "x_l_lck"),
166         PINCTRL_PIN(97, "x_l_fck"),
167         PINCTRL_PIN(98, "x_l_de"),
168         PINCTRL_PIN(99, "x_ldd[0]"),
169         PINCTRL_PIN(100, "x_ldd[1]"),
170         PINCTRL_PIN(101, "x_ldd[2]"),
171         PINCTRL_PIN(102, "x_ldd[3]"),
172         PINCTRL_PIN(103, "x_ldd[4]"),
173         PINCTRL_PIN(104, "x_ldd[5]"),
174         PINCTRL_PIN(105, "x_ldd[6]"),
175         PINCTRL_PIN(106, "x_ldd[7]"),
176         PINCTRL_PIN(107, "x_ldd[8]"),
177         PINCTRL_PIN(108, "x_ldd[9]"),
178         PINCTRL_PIN(109, "x_ldd[10]"),
179         PINCTRL_PIN(110, "x_ldd[11]"),
180         PINCTRL_PIN(111, "x_ldd[12]"),
181         PINCTRL_PIN(112, "x_ldd[13]"),
182         PINCTRL_PIN(113, "x_ldd[14]"),
183         PINCTRL_PIN(114, "x_ldd[15]"),
184 };
185
186 /**
187  * @dev: a pointer back to containing device
188  * @virtbase: the offset to the controller in virtual memory
189  */
190 struct sirfsoc_pmx {
191         struct device *dev;
192         struct pinctrl_dev *pmx;
193         void __iomem *gpio_virtbase;
194         void __iomem *rsc_virtbase;
195         bool is_marco;
196 };
197
198 /* SIRFSOC_GPIO_PAD_EN set */
199 struct sirfsoc_muxmask {
200         unsigned long group;
201         unsigned long mask;
202 };
203
204 struct sirfsoc_padmux {
205         unsigned long muxmask_counts;
206         const struct sirfsoc_muxmask *muxmask;
207         /* RSC_PIN_MUX set */
208         unsigned long funcmask;
209         unsigned long funcval;
210 };
211
212  /**
213  * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
214  * @name: the name of this specific pin group
215  * @pins: an array of discrete physical pins used in this group, taken
216  *      from the driver-local pin enumeration space
217  * @num_pins: the number of pins in this group array, i.e. the number of
218  *      elements in .pins so we can iterate over that array
219  */
220 struct sirfsoc_pin_group {
221         const char *name;
222         const unsigned int *pins;
223         const unsigned num_pins;
224 };
225
226 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
227         {
228                 .group = 3,
229                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
230                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
231                         BIT(17) | BIT(18),
232         }, {
233                 .group = 2,
234                 .mask = BIT(31),
235         },
236 };
237
238 static const struct sirfsoc_padmux lcd_16bits_padmux = {
239         .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
240         .muxmask = lcd_16bits_sirfsoc_muxmask,
241         .funcmask = BIT(4),
242         .funcval = 0,
243 };
244
245 static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
246         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
247
248 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
249         {
250                 .group = 3,
251                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
252                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
253                         BIT(17) | BIT(18),
254         }, {
255                 .group = 2,
256                 .mask = BIT(31),
257         }, {
258                 .group = 0,
259                 .mask = BIT(16) | BIT(17),
260         },
261 };
262
263 static const struct sirfsoc_padmux lcd_18bits_padmux = {
264         .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
265         .muxmask = lcd_18bits_muxmask,
266         .funcmask = BIT(4),
267         .funcval = 0,
268 };
269
270 static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
271         105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
272
273 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
274         {
275                 .group = 3,
276                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
277                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
278                         BIT(17) | BIT(18),
279         }, {
280                 .group = 2,
281                 .mask = BIT(31),
282         }, {
283                 .group = 0,
284                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
285         },
286 };
287
288 static const struct sirfsoc_padmux lcd_24bits_padmux = {
289         .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
290         .muxmask = lcd_24bits_muxmask,
291         .funcmask = BIT(4),
292         .funcval = 0,
293 };
294
295 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
296         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
297
298 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
299         {
300                 .group = 3,
301                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
302                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
303                         BIT(17) | BIT(18),
304         }, {
305                 .group = 2,
306                 .mask = BIT(31),
307         }, {
308                 .group = 0,
309                 .mask = BIT(23),
310         },
311 };
312
313 static const struct sirfsoc_padmux lcdrom_padmux = {
314         .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
315         .muxmask = lcdrom_muxmask,
316         .funcmask = BIT(4),
317         .funcval = BIT(4),
318 };
319
320 static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
321         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
322
323 static const struct sirfsoc_muxmask uart0_muxmask[] = {
324         {
325                 .group = 2,
326                 .mask = BIT(4) | BIT(5),
327         }, {
328                 .group = 1,
329                 .mask = BIT(23) | BIT(28),
330         },
331 };
332
333 static const struct sirfsoc_padmux uart0_padmux = {
334         .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
335         .muxmask = uart0_muxmask,
336         .funcmask = BIT(9),
337         .funcval = BIT(9),
338 };
339
340 static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
341
342 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
343         {
344                 .group = 2,
345                 .mask = BIT(4) | BIT(5),
346         },
347 };
348
349 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
350         .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
351         .muxmask = uart0_nostreamctrl_muxmask,
352 };
353
354 static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 };
355
356 static const struct sirfsoc_muxmask uart1_muxmask[] = {
357         {
358                 .group = 1,
359                 .mask = BIT(15) | BIT(17),
360         },
361 };
362
363 static const struct sirfsoc_padmux uart1_padmux = {
364         .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
365         .muxmask = uart1_muxmask,
366 };
367
368 static const unsigned uart1_pins[] = { 47, 49 };
369
370 static const struct sirfsoc_muxmask uart2_muxmask[] = {
371         {
372                 .group = 1,
373                 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
374         },
375 };
376
377 static const struct sirfsoc_padmux uart2_padmux = {
378         .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
379         .muxmask = uart2_muxmask,
380         .funcmask = BIT(10),
381         .funcval = BIT(10),
382 };
383
384 static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
385
386 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
387         {
388                 .group = 1,
389                 .mask = BIT(16) | BIT(18),
390         },
391 };
392
393 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
394         .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
395         .muxmask = uart2_nostreamctrl_muxmask,
396 };
397
398 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
399
400 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
401         {
402                 .group = 0,
403                 .mask = BIT(30) | BIT(31),
404         }, {
405                 .group = 1,
406                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
407         },
408 };
409
410 static const struct sirfsoc_padmux sdmmc3_padmux = {
411         .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
412         .muxmask = sdmmc3_muxmask,
413         .funcmask = BIT(7),
414         .funcval = 0,
415 };
416
417 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
418
419 static const struct sirfsoc_muxmask spi0_muxmask[] = {
420         {
421                 .group = 1,
422                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
423         },
424 };
425
426 static const struct sirfsoc_padmux spi0_padmux = {
427         .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
428         .muxmask = spi0_muxmask,
429         .funcmask = BIT(7),
430         .funcval = BIT(7),
431 };
432
433 static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
434
435 static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
436         {
437                 .group = 1,
438                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
439         },
440 };
441
442 static const struct sirfsoc_padmux sdmmc4_padmux = {
443         .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
444         .muxmask = sdmmc4_muxmask,
445 };
446
447 static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
448
449 static const struct sirfsoc_muxmask cko1_muxmask[] = {
450         {
451                 .group = 1,
452                 .mask = BIT(10),
453         },
454 };
455
456 static const struct sirfsoc_padmux cko1_padmux = {
457         .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
458         .muxmask = cko1_muxmask,
459         .funcmask = BIT(3),
460         .funcval = 0,
461 };
462
463 static const unsigned cko1_pins[] = { 42 };
464
465 static const struct sirfsoc_muxmask i2s_muxmask[] = {
466         {
467                 .group = 1,
468                 .mask =
469                         BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
470                                 | BIT(23) | BIT(28),
471         },
472 };
473
474 static const struct sirfsoc_padmux i2s_padmux = {
475         .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
476         .muxmask = i2s_muxmask,
477         .funcmask = BIT(3) | BIT(9),
478         .funcval = BIT(3),
479 };
480
481 static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
482
483 static const struct sirfsoc_muxmask ac97_muxmask[] = {
484         {
485                 .group = 1,
486                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
487         },
488 };
489
490 static const struct sirfsoc_padmux ac97_padmux = {
491         .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
492         .muxmask = ac97_muxmask,
493         .funcmask = BIT(8),
494         .funcval = 0,
495 };
496
497 static const unsigned ac97_pins[] = { 33, 34, 35, 36 };
498
499 static const struct sirfsoc_muxmask spi1_muxmask[] = {
500         {
501                 .group = 1,
502                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
503         },
504 };
505
506 static const struct sirfsoc_padmux spi1_padmux = {
507         .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
508         .muxmask = spi1_muxmask,
509         .funcmask = BIT(8),
510         .funcval = BIT(8),
511 };
512
513 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
514
515 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
516         {
517                 .group = 0,
518                 .mask = BIT(27) | BIT(28) | BIT(29),
519         },
520 };
521
522 static const struct sirfsoc_padmux sdmmc1_padmux = {
523         .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
524         .muxmask = sdmmc1_muxmask,
525 };
526
527 static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
528
529 static const struct sirfsoc_muxmask gps_muxmask[] = {
530         {
531                 .group = 0,
532                 .mask = BIT(24) | BIT(25) | BIT(26),
533         },
534 };
535
536 static const struct sirfsoc_padmux gps_padmux = {
537         .muxmask_counts = ARRAY_SIZE(gps_muxmask),
538         .muxmask = gps_muxmask,
539         .funcmask = BIT(12) | BIT(13) | BIT(14),
540         .funcval = BIT(12),
541 };
542
543 static const unsigned gps_pins[] = { 24, 25, 26 };
544
545 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
546         {
547                 .group = 0,
548                 .mask = BIT(24) | BIT(25) | BIT(26),
549         }, {
550                 .group = 1,
551                 .mask = BIT(29),
552         }, {
553                 .group = 2,
554                 .mask = BIT(0) | BIT(1),
555         },
556 };
557
558 static const struct sirfsoc_padmux sdmmc5_padmux = {
559         .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
560         .muxmask = sdmmc5_muxmask,
561         .funcmask = BIT(13) | BIT(14),
562         .funcval = BIT(13) | BIT(14),
563 };
564
565 static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 };
566
567 static const struct sirfsoc_muxmask usp0_muxmask[] = {
568         {
569                 .group = 1,
570                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
571         },
572 };
573
574 static const struct sirfsoc_padmux usp0_padmux = {
575         .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
576         .muxmask = usp0_muxmask,
577         .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
578         .funcval = 0,
579 };
580
581 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
582
583 static const struct sirfsoc_muxmask usp1_muxmask[] = {
584         {
585                 .group = 1,
586                 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
587         },
588 };
589
590 static const struct sirfsoc_padmux usp1_padmux = {
591         .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
592         .muxmask = usp1_muxmask,
593         .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
594         .funcval = 0,
595 };
596
597 static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
598
599 static const struct sirfsoc_muxmask usp2_muxmask[] = {
600         {
601                 .group = 1,
602                 .mask = BIT(29) | BIT(30) | BIT(31),
603         }, {
604                 .group = 2,
605                 .mask = BIT(0) | BIT(1),
606         },
607 };
608
609 static const struct sirfsoc_padmux usp2_padmux = {
610         .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
611         .muxmask = usp2_muxmask,
612         .funcmask = BIT(13) | BIT(14),
613         .funcval = 0,
614 };
615
616 static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
617
618 static const struct sirfsoc_muxmask nand_muxmask[] = {
619         {
620                 .group = 2,
621                 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
622         },
623 };
624
625 static const struct sirfsoc_padmux nand_padmux = {
626         .muxmask_counts = ARRAY_SIZE(nand_muxmask),
627         .muxmask = nand_muxmask,
628         .funcmask = BIT(5),
629         .funcval = 0,
630 };
631
632 static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
633
634 static const struct sirfsoc_padmux sdmmc0_padmux = {
635         .muxmask_counts = 0,
636         .funcmask = BIT(5),
637         .funcval = 0,
638 };
639
640 static const unsigned sdmmc0_pins[] = { };
641
642 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
643         {
644                 .group = 2,
645                 .mask = BIT(2) | BIT(3),
646         },
647 };
648
649 static const struct sirfsoc_padmux sdmmc2_padmux = {
650         .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
651         .muxmask = sdmmc2_muxmask,
652         .funcmask = BIT(5),
653         .funcval = BIT(5),
654 };
655
656 static const unsigned sdmmc2_pins[] = { 66, 67 };
657
658 static const struct sirfsoc_muxmask cko0_muxmask[] = {
659         {
660                 .group = 2,
661                 .mask = BIT(14),
662         },
663 };
664
665 static const struct sirfsoc_padmux cko0_padmux = {
666         .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
667         .muxmask = cko0_muxmask,
668 };
669
670 static const unsigned cko0_pins[] = { 78 };
671
672 static const struct sirfsoc_muxmask vip_muxmask[] = {
673         {
674                 .group = 2,
675                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
676                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
677                         BIT(25),
678         },
679 };
680
681 static const struct sirfsoc_padmux vip_padmux = {
682         .muxmask_counts = ARRAY_SIZE(vip_muxmask),
683         .muxmask = vip_muxmask,
684         .funcmask = BIT(0),
685         .funcval = 0,
686 };
687
688 static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
689
690 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
691         {
692                 .group = 2,
693                 .mask = BIT(26) | BIT(27),
694         },
695 };
696
697 static const struct sirfsoc_padmux i2c0_padmux = {
698         .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
699         .muxmask = i2c0_muxmask,
700 };
701
702 static const unsigned i2c0_pins[] = { 90, 91 };
703
704 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
705         {
706                 .group = 0,
707                 .mask = BIT(13) | BIT(15),
708         },
709 };
710
711 static const struct sirfsoc_padmux i2c1_padmux = {
712         .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
713         .muxmask = i2c1_muxmask,
714 };
715
716 static const unsigned i2c1_pins[] = { 13, 15 };
717
718 static const struct sirfsoc_muxmask viprom_muxmask[] = {
719         {
720                 .group = 2,
721                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
722                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
723                         BIT(25),
724         }, {
725                 .group = 0,
726                 .mask = BIT(12),
727         },
728 };
729
730 static const struct sirfsoc_padmux viprom_padmux = {
731         .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
732         .muxmask = viprom_muxmask,
733         .funcmask = BIT(0),
734         .funcval = BIT(0),
735 };
736
737 static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
738
739 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
740         {
741                 .group = 0,
742                 .mask = BIT(4),
743         },
744 };
745
746 static const struct sirfsoc_padmux pwm0_padmux = {
747         .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
748         .muxmask = pwm0_muxmask,
749         .funcmask = BIT(12),
750         .funcval = 0,
751 };
752
753 static const unsigned pwm0_pins[] = { 4 };
754
755 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
756         {
757                 .group = 0,
758                 .mask = BIT(5),
759         },
760 };
761
762 static const struct sirfsoc_padmux pwm1_padmux = {
763         .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
764         .muxmask = pwm1_muxmask,
765 };
766
767 static const unsigned pwm1_pins[] = { 5 };
768
769 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
770         {
771                 .group = 0,
772                 .mask = BIT(6),
773         },
774 };
775
776 static const struct sirfsoc_padmux pwm2_padmux = {
777         .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
778         .muxmask = pwm2_muxmask,
779 };
780
781 static const unsigned pwm2_pins[] = { 6 };
782
783 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
784         {
785                 .group = 0,
786                 .mask = BIT(7),
787         },
788 };
789
790 static const struct sirfsoc_padmux pwm3_padmux = {
791         .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
792         .muxmask = pwm3_muxmask,
793 };
794
795 static const unsigned pwm3_pins[] = { 7 };
796
797 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
798         {
799                 .group = 0,
800                 .mask = BIT(8),
801         },
802 };
803
804 static const struct sirfsoc_padmux warm_rst_padmux = {
805         .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
806         .muxmask = warm_rst_muxmask,
807 };
808
809 static const unsigned warm_rst_pins[] = { 8 };
810
811 static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
812         {
813                 .group = 1,
814                 .mask = BIT(22),
815         },
816 };
817 static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
818         .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
819         .muxmask = usb0_utmi_drvbus_muxmask,
820         .funcmask = BIT(6),
821         .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
822 };
823
824 static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
825
826 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
827         {
828                 .group = 1,
829                 .mask = BIT(27),
830         },
831 };
832
833 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
834         .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
835         .muxmask = usb1_utmi_drvbus_muxmask,
836         .funcmask = BIT(11),
837         .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
838 };
839
840 static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
841
842 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
843         {
844                 .group = 0,
845                 .mask = BIT(9) | BIT(10) | BIT(11),
846         },
847 };
848
849 static const struct sirfsoc_padmux pulse_count_padmux = {
850         .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
851         .muxmask = pulse_count_muxmask,
852 };
853
854 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
855
856 #define SIRFSOC_PIN_GROUP(n, p)  \
857         {                       \
858                 .name = n,      \
859                 .pins = p,      \
860                 .num_pins = ARRAY_SIZE(p),      \
861         }
862
863 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
864         SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
865         SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
866         SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
867         SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
868         SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
869         SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
870         SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
871         SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
872         SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
873         SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
874         SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
875         SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
876         SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
877         SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
878         SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
879         SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
880         SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
881         SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
882         SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
883         SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
884         SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins),
885         SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins),
886         SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
887         SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
888         SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
889         SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
890         SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
891         SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
892         SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
893         SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
894         SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
895         SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
896         SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
897         SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
898         SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
899         SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
900         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
901 };
902
903 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
904 {
905         return ARRAY_SIZE(sirfsoc_pin_groups);
906 }
907
908 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
909                                        unsigned selector)
910 {
911         return sirfsoc_pin_groups[selector].name;
912 }
913
914 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
915                                const unsigned **pins,
916                                unsigned *num_pins)
917 {
918         *pins = sirfsoc_pin_groups[selector].pins;
919         *num_pins = sirfsoc_pin_groups[selector].num_pins;
920         return 0;
921 }
922
923 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
924                    unsigned offset)
925 {
926         seq_printf(s, " " DRIVER_NAME);
927 }
928
929 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
930                                  struct device_node *np_config,
931                                  struct pinctrl_map **map, unsigned *num_maps)
932 {
933         struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
934         struct device_node *np;
935         struct property *prop;
936         const char *function, *group;
937         int ret, index = 0, count = 0;
938
939         /* calculate number of maps required */
940         for_each_child_of_node(np_config, np) {
941                 ret = of_property_read_string(np, "sirf,function", &function);
942                 if (ret < 0)
943                         return ret;
944
945                 ret = of_property_count_strings(np, "sirf,pins");
946                 if (ret < 0)
947                         return ret;
948
949                 count += ret;
950         }
951
952         if (!count) {
953                 dev_err(spmx->dev, "No child nodes passed via DT\n");
954                 return -ENODEV;
955         }
956
957         *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
958         if (!*map)
959                 return -ENOMEM;
960
961         for_each_child_of_node(np_config, np) {
962                 of_property_read_string(np, "sirf,function", &function);
963                 of_property_for_each_string(np, "sirf,pins", prop, group) {
964                         (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
965                         (*map)[index].data.mux.group = group;
966                         (*map)[index].data.mux.function = function;
967                         index++;
968                 }
969         }
970
971         *num_maps = count;
972
973         return 0;
974 }
975
976 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
977                 struct pinctrl_map *map, unsigned num_maps)
978 {
979         kfree(map);
980 }
981
982 static struct pinctrl_ops sirfsoc_pctrl_ops = {
983         .get_groups_count = sirfsoc_get_groups_count,
984         .get_group_name = sirfsoc_get_group_name,
985         .get_group_pins = sirfsoc_get_group_pins,
986         .pin_dbg_show = sirfsoc_pin_dbg_show,
987         .dt_node_to_map = sirfsoc_dt_node_to_map,
988         .dt_free_map = sirfsoc_dt_free_map,
989 };
990
991 struct sirfsoc_pmx_func {
992         const char *name;
993         const char * const *groups;
994         const unsigned num_groups;
995         const struct sirfsoc_padmux *padmux;
996 };
997
998 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
999 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
1000 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
1001 static const char * const lcdromgrp[] = { "lcdromgrp" };
1002 static const char * const uart0grp[] = { "uart0grp" };
1003 static const char * const uart1grp[] = { "uart1grp" };
1004 static const char * const uart2grp[] = { "uart2grp" };
1005 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
1006 static const char * const usp0grp[] = { "usp0grp" };
1007 static const char * const usp1grp[] = { "usp1grp" };
1008 static const char * const usp2grp[] = { "usp2grp" };
1009 static const char * const i2c0grp[] = { "i2c0grp" };
1010 static const char * const i2c1grp[] = { "i2c1grp" };
1011 static const char * const pwm0grp[] = { "pwm0grp" };
1012 static const char * const pwm1grp[] = { "pwm1grp" };
1013 static const char * const pwm2grp[] = { "pwm2grp" };
1014 static const char * const pwm3grp[] = { "pwm3grp" };
1015 static const char * const vipgrp[] = { "vipgrp" };
1016 static const char * const vipromgrp[] = { "vipromgrp" };
1017 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
1018 static const char * const cko0grp[] = { "cko0grp" };
1019 static const char * const cko1grp[] = { "cko1grp" };
1020 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
1021 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
1022 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
1023 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
1024 static const char * const sdmmc4grp[] = { "sdmmc4grp" };
1025 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
1026 static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
1027 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1028 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1029 static const char * const i2sgrp[] = { "i2sgrp" };
1030 static const char * const ac97grp[] = { "ac97grp" };
1031 static const char * const nandgrp[] = { "nandgrp" };
1032 static const char * const spi0grp[] = { "spi0grp" };
1033 static const char * const spi1grp[] = { "spi1grp" };
1034 static const char * const gpsgrp[] = { "gpsgrp" };
1035
1036 #define SIRFSOC_PMX_FUNCTION(n, g, m)           \
1037         {                                       \
1038                 .name = n,                      \
1039                 .groups = g,                    \
1040                 .num_groups = ARRAY_SIZE(g),    \
1041                 .padmux = &m,                   \
1042         }
1043
1044 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1045         SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1046         SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
1047         SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
1048         SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
1049         SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
1050         SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1051         SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1052         SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1053         SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1054         SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1055         SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
1056         SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1057         SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1058         SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1059         SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1060         SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1061         SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1062         SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1063         SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
1064         SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1065         SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1066         SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1067         SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1068         SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1069         SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1070         SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1071         SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1072         SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1073         SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1074         SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1075         SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1076         SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1077         SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1078         SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1079         SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1080         SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1081         SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1082 };
1083
1084 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
1085         bool enable)
1086 {
1087         int i;
1088         const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
1089         const struct sirfsoc_muxmask *mask = mux->muxmask;
1090
1091         for (i = 0; i < mux->muxmask_counts; i++) {
1092                 u32 muxval;
1093                 if (!spmx->is_marco) {
1094                         muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1095                         if (enable)
1096                                 muxval = muxval & ~mask[i].mask;
1097                         else
1098                                 muxval = muxval | mask[i].mask;
1099                         writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1100                 } else {
1101                         if (enable)
1102                                 writel(mask[i].mask, spmx->gpio_virtbase +
1103                                         SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
1104                         else
1105                                 writel(mask[i].mask, spmx->gpio_virtbase +
1106                                         SIRFSOC_GPIO_PAD_EN(mask[i].group));
1107                 }
1108         }
1109
1110         if (mux->funcmask && enable) {
1111                 u32 func_en_val;
1112                 func_en_val =
1113                         readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1114                 func_en_val =
1115                         (func_en_val & ~mux->funcmask) | (mux->
1116                                 funcval);
1117                 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1118         }
1119 }
1120
1121 static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
1122         unsigned group)
1123 {
1124         struct sirfsoc_pmx *spmx;
1125
1126         spmx = pinctrl_dev_get_drvdata(pmxdev);
1127         sirfsoc_pinmux_endisable(spmx, selector, true);
1128
1129         return 0;
1130 }
1131
1132 static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
1133         unsigned group)
1134 {
1135         struct sirfsoc_pmx *spmx;
1136
1137         spmx = pinctrl_dev_get_drvdata(pmxdev);
1138         sirfsoc_pinmux_endisable(spmx, selector, false);
1139 }
1140
1141 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1142 {
1143         return ARRAY_SIZE(sirfsoc_pmx_functions);
1144 }
1145
1146 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
1147                                           unsigned selector)
1148 {
1149         return sirfsoc_pmx_functions[selector].name;
1150 }
1151
1152 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1153                                const char * const **groups,
1154                                unsigned * const num_groups)
1155 {
1156         *groups = sirfsoc_pmx_functions[selector].groups;
1157         *num_groups = sirfsoc_pmx_functions[selector].num_groups;
1158         return 0;
1159 }
1160
1161 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1162         struct pinctrl_gpio_range *range, unsigned offset)
1163 {
1164         struct sirfsoc_pmx *spmx;
1165
1166         int group = range->id;
1167
1168         u32 muxval;
1169
1170         spmx = pinctrl_dev_get_drvdata(pmxdev);
1171
1172         if (!spmx->is_marco) {
1173                 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1174                 muxval = muxval | (1 << (offset - range->pin_base));
1175                 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1176         } else {
1177                 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
1178                         SIRFSOC_GPIO_PAD_EN(group));
1179         }
1180
1181         return 0;
1182 }
1183
1184 static struct pinmux_ops sirfsoc_pinmux_ops = {
1185         .enable = sirfsoc_pinmux_enable,
1186         .disable = sirfsoc_pinmux_disable,
1187         .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1188         .get_function_name = sirfsoc_pinmux_get_func_name,
1189         .get_function_groups = sirfsoc_pinmux_get_groups,
1190         .gpio_request_enable = sirfsoc_pinmux_request_gpio,
1191 };
1192
1193 static struct pinctrl_desc sirfsoc_pinmux_desc = {
1194         .name = DRIVER_NAME,
1195         .pins = sirfsoc_pads,
1196         .npins = ARRAY_SIZE(sirfsoc_pads),
1197         .pctlops = &sirfsoc_pctrl_ops,
1198         .pmxops = &sirfsoc_pinmux_ops,
1199         .owner = THIS_MODULE,
1200 };
1201
1202 /*
1203  * Todo: bind irq_chip to every pinctrl_gpio_range
1204  */
1205 static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
1206         {
1207                 .name = "sirfsoc-gpio*",
1208                 .id = 0,
1209                 .base = 0,
1210                 .pin_base = 0,
1211                 .npins = 32,
1212         }, {
1213                 .name = "sirfsoc-gpio*",
1214                 .id = 1,
1215                 .base = 32,
1216                 .pin_base = 32,
1217                 .npins = 32,
1218         }, {
1219                 .name = "sirfsoc-gpio*",
1220                 .id = 2,
1221                 .base = 64,
1222                 .pin_base = 64,
1223                 .npins = 32,
1224         }, {
1225                 .name = "sirfsoc-gpio*",
1226                 .id = 3,
1227                 .base = 96,
1228                 .pin_base = 96,
1229                 .npins = 19,
1230         },
1231 };
1232
1233 static void __iomem *sirfsoc_rsc_of_iomap(void)
1234 {
1235         const struct of_device_id rsc_ids[]  = {
1236                 { .compatible = "sirf,prima2-rsc" },
1237                 { .compatible = "sirf,marco-rsc" },
1238                 {}
1239         };
1240         struct device_node *np;
1241
1242         np = of_find_matching_node(NULL, rsc_ids);
1243         if (!np)
1244                 panic("unable to find compatible rsc node in dtb\n");
1245
1246         return of_iomap(np, 0);
1247 }
1248
1249 static int sirfsoc_pinmux_probe(struct platform_device *pdev)
1250 {
1251         int ret;
1252         struct sirfsoc_pmx *spmx;
1253         struct device_node *np = pdev->dev.of_node;
1254         int i;
1255
1256         /* Create state holders etc for this driver */
1257         spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
1258         if (!spmx)
1259                 return -ENOMEM;
1260
1261         spmx->dev = &pdev->dev;
1262
1263         platform_set_drvdata(pdev, spmx);
1264
1265         spmx->gpio_virtbase = of_iomap(np, 0);
1266         if (!spmx->gpio_virtbase) {
1267                 ret = -ENOMEM;
1268                 dev_err(&pdev->dev, "can't map gpio registers\n");
1269                 goto out_no_gpio_remap;
1270         }
1271
1272         spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
1273         if (!spmx->rsc_virtbase) {
1274                 ret = -ENOMEM;
1275                 dev_err(&pdev->dev, "can't map rsc registers\n");
1276                 goto out_no_rsc_remap;
1277         }
1278
1279         if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
1280                 spmx->is_marco = 1;
1281
1282         /* Now register the pin controller and all pins it handles */
1283         spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
1284         if (!spmx->pmx) {
1285                 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
1286                 ret = -EINVAL;
1287                 goto out_no_pmx;
1288         }
1289
1290         for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
1291                 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
1292                 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
1293         }
1294
1295         dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
1296
1297         return 0;
1298
1299 out_no_pmx:
1300         iounmap(spmx->rsc_virtbase);
1301 out_no_rsc_remap:
1302         iounmap(spmx->gpio_virtbase);
1303 out_no_gpio_remap:
1304         platform_set_drvdata(pdev, NULL);
1305         return ret;
1306 }
1307
1308 static const struct of_device_id pinmux_ids[] = {
1309         { .compatible = "sirf,prima2-pinctrl" },
1310         { .compatible = "sirf,marco-pinctrl" },
1311         {}
1312 };
1313
1314 static struct platform_driver sirfsoc_pinmux_driver = {
1315         .driver = {
1316                 .name = DRIVER_NAME,
1317                 .owner = THIS_MODULE,
1318                 .of_match_table = pinmux_ids,
1319         },
1320         .probe = sirfsoc_pinmux_probe,
1321 };
1322
1323 static int __init sirfsoc_pinmux_init(void)
1324 {
1325         return platform_driver_register(&sirfsoc_pinmux_driver);
1326 }
1327 arch_initcall(sirfsoc_pinmux_init);
1328
1329 static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1330 {
1331         struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
1332                 struct sirfsoc_gpio_bank, chip);
1333
1334         return irq_find_mapping(bank->domain, offset);
1335 }
1336
1337 static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
1338 {
1339         return gpio % SIRFSOC_GPIO_BANK_SIZE;
1340 }
1341
1342 static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1343 {
1344         return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1345 }
1346
1347 static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1348 {
1349         return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
1350 }
1351
1352 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
1353 {
1354         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1355         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1356         u32 val, offset;
1357         unsigned long flags;
1358
1359         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1360
1361         spin_lock_irqsave(&sgpio_lock, flags);
1362
1363         val = readl(bank->chip.regs + offset);
1364
1365         writel(val, bank->chip.regs + offset);
1366
1367         spin_unlock_irqrestore(&sgpio_lock, flags);
1368 }
1369
1370 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
1371 {
1372         u32 val, offset;
1373         unsigned long flags;
1374
1375         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1376
1377         spin_lock_irqsave(&sgpio_lock, flags);
1378
1379         val = readl(bank->chip.regs + offset);
1380         val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1381         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1382         writel(val, bank->chip.regs + offset);
1383
1384         spin_unlock_irqrestore(&sgpio_lock, flags);
1385 }
1386
1387 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
1388 {
1389         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1390
1391         __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
1392 }
1393
1394 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
1395 {
1396         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1397         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1398         u32 val, offset;
1399         unsigned long flags;
1400
1401         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1402
1403         spin_lock_irqsave(&sgpio_lock, flags);
1404
1405         val = readl(bank->chip.regs + offset);
1406         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1407         val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1408         writel(val, bank->chip.regs + offset);
1409
1410         spin_unlock_irqrestore(&sgpio_lock, flags);
1411 }
1412
1413 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
1414 {
1415         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1416         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1417         u32 val, offset;
1418         unsigned long flags;
1419
1420         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1421
1422         spin_lock_irqsave(&sgpio_lock, flags);
1423
1424         val = readl(bank->chip.regs + offset);
1425         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1426
1427         switch (type) {
1428         case IRQ_TYPE_NONE:
1429                 break;
1430         case IRQ_TYPE_EDGE_RISING:
1431                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1432                 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1433                 break;
1434         case IRQ_TYPE_EDGE_FALLING:
1435                 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1436                 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1437                 break;
1438         case IRQ_TYPE_EDGE_BOTH:
1439                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
1440                          SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1441                 break;
1442         case IRQ_TYPE_LEVEL_LOW:
1443                 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1444                 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1445                 break;
1446         case IRQ_TYPE_LEVEL_HIGH:
1447                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1448                 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1449                 break;
1450         }
1451
1452         writel(val, bank->chip.regs + offset);
1453
1454         spin_unlock_irqrestore(&sgpio_lock, flags);
1455
1456         return 0;
1457 }
1458
1459 static struct irq_chip sirfsoc_irq_chip = {
1460         .name = "sirf-gpio-irq",
1461         .irq_ack = sirfsoc_gpio_irq_ack,
1462         .irq_mask = sirfsoc_gpio_irq_mask,
1463         .irq_unmask = sirfsoc_gpio_irq_unmask,
1464         .irq_set_type = sirfsoc_gpio_irq_type,
1465 };
1466
1467 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1468 {
1469         struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
1470         u32 status, ctrl;
1471         int idx = 0;
1472         unsigned int first_irq;
1473         struct irq_chip *chip = irq_get_chip(irq);
1474
1475         chained_irq_enter(chip, desc);
1476
1477         status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1478         if (!status) {
1479                 printk(KERN_WARNING
1480                         "%s: gpio id %d status %#x no interrupt is flaged\n",
1481                         __func__, bank->id, status);
1482                 handle_bad_irq(irq, desc);
1483                 return;
1484         }
1485
1486         first_irq = bank->domain->revmap_data.legacy.first_irq;
1487
1488         while (status) {
1489                 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
1490
1491                 /*
1492                  * Here we must check whether the corresponding GPIO's interrupt
1493                  * has been enabled, otherwise just skip it
1494                  */
1495                 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
1496                         pr_debug("%s: gpio id %d idx %d happens\n",
1497                                 __func__, bank->id, idx);
1498                         generic_handle_irq(first_irq + idx);
1499                 }
1500
1501                 idx++;
1502                 status = status >> 1;
1503         }
1504
1505         chained_irq_exit(chip, desc);
1506 }
1507
1508 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1509 {
1510         u32 val;
1511
1512         val = readl(bank->chip.regs + ctrl_offset);
1513         val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1514         writel(val, bank->chip.regs + ctrl_offset);
1515 }
1516
1517 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
1518 {
1519         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1520         unsigned long flags;
1521
1522         if (pinctrl_request_gpio(chip->base + offset))
1523                 return -ENODEV;
1524
1525         spin_lock_irqsave(&bank->lock, flags);
1526
1527         /*
1528          * default status:
1529          * set direction as input and mask irq
1530          */
1531         sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1532         __sirfsoc_gpio_irq_mask(bank, offset);
1533
1534         spin_unlock_irqrestore(&bank->lock, flags);
1535
1536         return 0;
1537 }
1538
1539 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
1540 {
1541         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1542         unsigned long flags;
1543
1544         spin_lock_irqsave(&bank->lock, flags);
1545
1546         __sirfsoc_gpio_irq_mask(bank, offset);
1547         sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1548
1549         spin_unlock_irqrestore(&bank->lock, flags);
1550
1551         pinctrl_free_gpio(chip->base + offset);
1552 }
1553
1554 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1555 {
1556         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1557         int idx = sirfsoc_gpio_to_offset(gpio);
1558         unsigned long flags;
1559         unsigned offset;
1560
1561         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1562
1563         spin_lock_irqsave(&bank->lock, flags);
1564
1565         sirfsoc_gpio_set_input(bank, offset);
1566
1567         spin_unlock_irqrestore(&bank->lock, flags);
1568
1569         return 0;
1570 }
1571
1572 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
1573         int value)
1574 {
1575         u32 out_ctrl;
1576         unsigned long flags;
1577
1578         spin_lock_irqsave(&bank->lock, flags);
1579
1580         out_ctrl = readl(bank->chip.regs + offset);
1581         if (value)
1582                 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1583         else
1584                 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1585
1586         out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1587         out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1588         writel(out_ctrl, bank->chip.regs + offset);
1589
1590         spin_unlock_irqrestore(&bank->lock, flags);
1591 }
1592
1593 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1594 {
1595         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1596         int idx = sirfsoc_gpio_to_offset(gpio);
1597         u32 offset;
1598         unsigned long flags;
1599
1600         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1601
1602         spin_lock_irqsave(&sgpio_lock, flags);
1603
1604         sirfsoc_gpio_set_output(bank, offset, value);
1605
1606         spin_unlock_irqrestore(&sgpio_lock, flags);
1607
1608         return 0;
1609 }
1610
1611 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
1612 {
1613         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1614         u32 val;
1615         unsigned long flags;
1616
1617         spin_lock_irqsave(&bank->lock, flags);
1618
1619         val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1620
1621         spin_unlock_irqrestore(&bank->lock, flags);
1622
1623         return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
1624 }
1625
1626 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
1627         int value)
1628 {
1629         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1630         u32 ctrl;
1631         unsigned long flags;
1632
1633         spin_lock_irqsave(&bank->lock, flags);
1634
1635         ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1636         if (value)
1637                 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1638         else
1639                 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1640         writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1641
1642         spin_unlock_irqrestore(&bank->lock, flags);
1643 }
1644
1645 static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1646                                 irq_hw_number_t hwirq)
1647 {
1648         struct sirfsoc_gpio_bank *bank = d->host_data;
1649
1650         if (!bank)
1651                 return -EINVAL;
1652
1653         irq_set_chip(irq, &sirfsoc_irq_chip);
1654         irq_set_handler(irq, handle_level_irq);
1655         irq_set_chip_data(irq, bank);
1656         set_irq_flags(irq, IRQF_VALID);
1657
1658         return 0;
1659 }
1660
1661 const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
1662         .map = sirfsoc_gpio_irq_map,
1663         .xlate = irq_domain_xlate_twocell,
1664 };
1665
1666 static void sirfsoc_gpio_set_pullup(const u32 *pullups)
1667 {
1668         int i, n;
1669         const unsigned long *p = (const unsigned long *)pullups;
1670
1671         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1672                 n = find_first_bit(p + i, BITS_PER_LONG);
1673                 while (n < BITS_PER_LONG) {
1674                         u32 offset = SIRFSOC_GPIO_CTRL(i, n);
1675                         u32 val = readl(sgpio_bank[i].chip.regs + offset);
1676                         val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1677                         val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1678                         writel(val, sgpio_bank[i].chip.regs + offset);
1679
1680                         n = find_next_bit(p + i, BITS_PER_LONG, n + 1);
1681                 }
1682         }
1683 }
1684
1685 static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
1686 {
1687         int i, n;
1688         const unsigned long *p = (const unsigned long *)pulldowns;
1689
1690         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1691                 n = find_first_bit(p + i, BITS_PER_LONG);
1692                 while (n < BITS_PER_LONG) {
1693                         u32 offset = SIRFSOC_GPIO_CTRL(i, n);
1694                         u32 val = readl(sgpio_bank[i].chip.regs + offset);
1695                         val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1696                         val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1697                         writel(val, sgpio_bank[i].chip.regs + offset);
1698
1699                         n = find_next_bit(p + i, BITS_PER_LONG, n + 1);
1700                 }
1701         }
1702 }
1703
1704 static int sirfsoc_gpio_probe(struct device_node *np)
1705 {
1706         int i, err = 0;
1707         struct sirfsoc_gpio_bank *bank;
1708         void *regs;
1709         struct platform_device *pdev;
1710         bool is_marco = false;
1711
1712         u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
1713
1714         pdev = of_find_device_by_node(np);
1715         if (!pdev)
1716                 return -ENODEV;
1717
1718         regs = of_iomap(np, 0);
1719         if (!regs)
1720                 return -ENOMEM;
1721
1722         if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
1723                 is_marco = 1;
1724
1725         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1726                 bank = &sgpio_bank[i];
1727                 spin_lock_init(&bank->lock);
1728                 bank->chip.gc.request = sirfsoc_gpio_request;
1729                 bank->chip.gc.free = sirfsoc_gpio_free;
1730                 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
1731                 bank->chip.gc.get = sirfsoc_gpio_get_value;
1732                 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
1733                 bank->chip.gc.set = sirfsoc_gpio_set_value;
1734                 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
1735                 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
1736                 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
1737                 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
1738                 bank->chip.gc.of_node = np;
1739                 bank->chip.regs = regs;
1740                 bank->id = i;
1741                 bank->is_marco = is_marco;
1742                 bank->parent_irq = platform_get_irq(pdev, i);
1743                 if (bank->parent_irq < 0) {
1744                         err = bank->parent_irq;
1745                         goto out;
1746                 }
1747
1748                 err = gpiochip_add(&bank->chip.gc);
1749                 if (err) {
1750                         pr_err("%s: error in probe function with status %d\n",
1751                                 np->full_name, err);
1752                         goto out;
1753                 }
1754
1755                 bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
1756                         SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
1757                         &sirfsoc_gpio_irq_simple_ops, bank);
1758
1759                 if (!bank->domain) {
1760                         pr_err("%s: Failed to create irqdomain\n", np->full_name);
1761                         err = -ENOSYS;
1762                         goto out;
1763                 }
1764
1765                 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
1766                 irq_set_handler_data(bank->parent_irq, bank);
1767         }
1768
1769         if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
1770                 SIRFSOC_GPIO_NO_OF_BANKS))
1771                 sirfsoc_gpio_set_pullup(pullups);
1772
1773         if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
1774                 SIRFSOC_GPIO_NO_OF_BANKS))
1775                 sirfsoc_gpio_set_pulldown(pulldowns);
1776
1777         return 0;
1778
1779 out:
1780         iounmap(regs);
1781         return err;
1782 }
1783
1784 static int __init sirfsoc_gpio_init(void)
1785 {
1786
1787         struct device_node *np;
1788
1789         np = of_find_matching_node(NULL, pinmux_ids);
1790
1791         if (!np)
1792                 return -ENODEV;
1793
1794         return sirfsoc_gpio_probe(np);
1795 }
1796 subsys_initcall(sirfsoc_gpio_init);
1797
1798 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
1799         "Yuping Luo <yuping.luo@csr.com>, "
1800         "Barry Song <baohua.song@csr.com>");
1801 MODULE_DESCRIPTION("SIRFSOC pin control driver");
1802 MODULE_LICENSE("GPL");