spi/s3c64xx: fix checkpatch warnings and error
[~shefty/rdma-dev.git] / drivers / spi / spi-s3c64xx.c
1 /*
2  * Copyright (C) 2009 Samsung Electronics Ltd.
3  *      Jaswinder Singh <jassi.brar@samsung.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18  */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/workqueue.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/spi/spi.h>
30 #include <linux/gpio.h>
31 #include <linux/of.h>
32 #include <linux/of_gpio.h>
33
34 #include <mach/dma.h>
35 #include <linux/platform_data/spi-s3c64xx.h>
36
37 #define MAX_SPI_PORTS           3
38
39 /* Registers and bit-fields */
40
41 #define S3C64XX_SPI_CH_CFG              0x00
42 #define S3C64XX_SPI_CLK_CFG             0x04
43 #define S3C64XX_SPI_MODE_CFG    0x08
44 #define S3C64XX_SPI_SLAVE_SEL   0x0C
45 #define S3C64XX_SPI_INT_EN              0x10
46 #define S3C64XX_SPI_STATUS              0x14
47 #define S3C64XX_SPI_TX_DATA             0x18
48 #define S3C64XX_SPI_RX_DATA             0x1C
49 #define S3C64XX_SPI_PACKET_CNT  0x20
50 #define S3C64XX_SPI_PENDING_CLR 0x24
51 #define S3C64XX_SPI_SWAP_CFG    0x28
52 #define S3C64XX_SPI_FB_CLK              0x2C
53
54 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
55 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
56 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
57 #define S3C64XX_SPI_CPOL_L              (1<<3)
58 #define S3C64XX_SPI_CPHA_B              (1<<2)
59 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
60 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
61
62 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
63 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
64 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
65 #define S3C64XX_SPI_PSR_MASK            0xff
66
67 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
68 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
69 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
70 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
71 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
72 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
73 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
74 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
75 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
76 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
77 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
78
79 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
80 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
81
82 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
83 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
84 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
85 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
86 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
87 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
88 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
89
90 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
91 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
92 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
93 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
94 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
95 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
96
97 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
98
99 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
100 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
101 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
102 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
103 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
104
105 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
106 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
107 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
108 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
109 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
110 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
111 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
112 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
113
114 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
115
116 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
117 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
118                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
121                                         FIFO_LVL_MASK(i))
122
123 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
124 #define S3C64XX_SPI_TRAILCNT_OFF        19
125
126 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
127
128 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
129
130 #define RXBUSY    (1<<2)
131 #define TXBUSY    (1<<3)
132
133 struct s3c64xx_spi_dma_data {
134         unsigned                ch;
135         enum dma_transfer_direction direction;
136         enum dma_ch     dmach;
137         struct property         *dma_prop;
138 };
139
140 /**
141  * struct s3c64xx_spi_info - SPI Controller hardware info
142  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
143  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
144  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
145  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
146  * @clk_from_cmu: True, if the controller does not include a clock mux and
147  *      prescaler unit.
148  *
149  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
150  * differ in some aspects such as the size of the fifo and spi bus clock
151  * setup. Such differences are specified to the driver using this structure
152  * which is provided as driver data to the driver.
153  */
154 struct s3c64xx_spi_port_config {
155         int     fifo_lvl_mask[MAX_SPI_PORTS];
156         int     rx_lvl_offset;
157         int     tx_st_done;
158         bool    high_speed;
159         bool    clk_from_cmu;
160 };
161
162 /**
163  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164  * @clk: Pointer to the spi clock.
165  * @src_clk: Pointer to the clock used to generate SPI signals.
166  * @master: Pointer to the SPI Protocol master.
167  * @cntrlr_info: Platform specific data for the controller this driver manages.
168  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
169  * @queue: To log SPI xfer requests.
170  * @lock: Controller specific lock.
171  * @state: Set of FLAGS to indicate status.
172  * @rx_dmach: Controller's DMA channel for Rx.
173  * @tx_dmach: Controller's DMA channel for Tx.
174  * @sfr_start: BUS address of SPI controller regs.
175  * @regs: Pointer to ioremap'ed controller registers.
176  * @irq: interrupt
177  * @xfer_completion: To indicate completion of xfer task.
178  * @cur_mode: Stores the active configuration of the controller.
179  * @cur_bpw: Stores the active bits per word settings.
180  * @cur_speed: Stores the active xfer clock speed.
181  */
182 struct s3c64xx_spi_driver_data {
183         void __iomem                    *regs;
184         struct clk                      *clk;
185         struct clk                      *src_clk;
186         struct platform_device          *pdev;
187         struct spi_master               *master;
188         struct s3c64xx_spi_info  *cntrlr_info;
189         struct spi_device               *tgl_spi;
190         struct list_head                queue;
191         spinlock_t                      lock;
192         unsigned long                   sfr_start;
193         struct completion               xfer_completion;
194         unsigned                        state;
195         unsigned                        cur_mode, cur_bpw;
196         unsigned                        cur_speed;
197         struct s3c64xx_spi_dma_data     rx_dma;
198         struct s3c64xx_spi_dma_data     tx_dma;
199         struct samsung_dma_ops          *ops;
200         struct s3c64xx_spi_port_config  *port_conf;
201         unsigned int                    port_id;
202         unsigned long                   gpios[4];
203 };
204
205 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
206         .name = "samsung-spi-dma",
207 };
208
209 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
210 {
211         void __iomem *regs = sdd->regs;
212         unsigned long loops;
213         u32 val;
214
215         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
216
217         val = readl(regs + S3C64XX_SPI_CH_CFG);
218         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
219         writel(val, regs + S3C64XX_SPI_CH_CFG);
220
221         val = readl(regs + S3C64XX_SPI_CH_CFG);
222         val |= S3C64XX_SPI_CH_SW_RST;
223         val &= ~S3C64XX_SPI_CH_HS_EN;
224         writel(val, regs + S3C64XX_SPI_CH_CFG);
225
226         /* Flush TxFIFO*/
227         loops = msecs_to_loops(1);
228         do {
229                 val = readl(regs + S3C64XX_SPI_STATUS);
230         } while (TX_FIFO_LVL(val, sdd) && loops--);
231
232         if (loops == 0)
233                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
234
235         /* Flush RxFIFO*/
236         loops = msecs_to_loops(1);
237         do {
238                 val = readl(regs + S3C64XX_SPI_STATUS);
239                 if (RX_FIFO_LVL(val, sdd))
240                         readl(regs + S3C64XX_SPI_RX_DATA);
241                 else
242                         break;
243         } while (loops--);
244
245         if (loops == 0)
246                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
247
248         val = readl(regs + S3C64XX_SPI_CH_CFG);
249         val &= ~S3C64XX_SPI_CH_SW_RST;
250         writel(val, regs + S3C64XX_SPI_CH_CFG);
251
252         val = readl(regs + S3C64XX_SPI_MODE_CFG);
253         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
254         writel(val, regs + S3C64XX_SPI_MODE_CFG);
255 }
256
257 static void s3c64xx_spi_dmacb(void *data)
258 {
259         struct s3c64xx_spi_driver_data *sdd;
260         struct s3c64xx_spi_dma_data *dma = data;
261         unsigned long flags;
262
263         if (dma->direction == DMA_DEV_TO_MEM)
264                 sdd = container_of(data,
265                         struct s3c64xx_spi_driver_data, rx_dma);
266         else
267                 sdd = container_of(data,
268                         struct s3c64xx_spi_driver_data, tx_dma);
269
270         spin_lock_irqsave(&sdd->lock, flags);
271
272         if (dma->direction == DMA_DEV_TO_MEM) {
273                 sdd->state &= ~RXBUSY;
274                 if (!(sdd->state & TXBUSY))
275                         complete(&sdd->xfer_completion);
276         } else {
277                 sdd->state &= ~TXBUSY;
278                 if (!(sdd->state & RXBUSY))
279                         complete(&sdd->xfer_completion);
280         }
281
282         spin_unlock_irqrestore(&sdd->lock, flags);
283 }
284
285 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
286                                         unsigned len, dma_addr_t buf)
287 {
288         struct s3c64xx_spi_driver_data *sdd;
289         struct samsung_dma_prep info;
290         struct samsung_dma_config config;
291
292         if (dma->direction == DMA_DEV_TO_MEM) {
293                 sdd = container_of((void *)dma,
294                         struct s3c64xx_spi_driver_data, rx_dma);
295                 config.direction = sdd->rx_dma.direction;
296                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
297                 config.width = sdd->cur_bpw / 8;
298                 sdd->ops->config(sdd->rx_dma.ch, &config);
299         } else {
300                 sdd = container_of((void *)dma,
301                         struct s3c64xx_spi_driver_data, tx_dma);
302                 config.direction =  sdd->tx_dma.direction;
303                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
304                 config.width = sdd->cur_bpw / 8;
305                 sdd->ops->config(sdd->tx_dma.ch, &config);
306         }
307
308         info.cap = DMA_SLAVE;
309         info.len = len;
310         info.fp = s3c64xx_spi_dmacb;
311         info.fp_param = dma;
312         info.direction = dma->direction;
313         info.buf = buf;
314
315         sdd->ops->prepare(dma->ch, &info);
316         sdd->ops->trigger(dma->ch);
317 }
318
319 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
320 {
321         struct samsung_dma_req req;
322
323         sdd->ops = samsung_dma_get_ops();
324
325         req.cap = DMA_SLAVE;
326         req.client = &s3c64xx_spi_dma_client;
327
328         req.dt_dmach_prop = sdd->rx_dma.dma_prop;
329         sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req);
330         req.dt_dmach_prop = sdd->tx_dma.dma_prop;
331         sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req);
332
333         return 1;
334 }
335
336 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
337                                 struct spi_device *spi,
338                                 struct spi_transfer *xfer, int dma_mode)
339 {
340         void __iomem *regs = sdd->regs;
341         u32 modecfg, chcfg;
342
343         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
344         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
345
346         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
347         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
348
349         if (dma_mode) {
350                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
351         } else {
352                 /* Always shift in data in FIFO, even if xfer is Tx only,
353                  * this helps setting PCKT_CNT value for generating clocks
354                  * as exactly needed.
355                  */
356                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
357                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
358                                         | S3C64XX_SPI_PACKET_CNT_EN,
359                                         regs + S3C64XX_SPI_PACKET_CNT);
360         }
361
362         if (xfer->tx_buf != NULL) {
363                 sdd->state |= TXBUSY;
364                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
365                 if (dma_mode) {
366                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
367                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
368                 } else {
369                         switch (sdd->cur_bpw) {
370                         case 32:
371                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
372                                         xfer->tx_buf, xfer->len / 4);
373                                 break;
374                         case 16:
375                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
376                                         xfer->tx_buf, xfer->len / 2);
377                                 break;
378                         default:
379                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
380                                         xfer->tx_buf, xfer->len);
381                                 break;
382                         }
383                 }
384         }
385
386         if (xfer->rx_buf != NULL) {
387                 sdd->state |= RXBUSY;
388
389                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
390                                         && !(sdd->cur_mode & SPI_CPHA))
391                         chcfg |= S3C64XX_SPI_CH_HS_EN;
392
393                 if (dma_mode) {
394                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
395                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
396                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
397                                         | S3C64XX_SPI_PACKET_CNT_EN,
398                                         regs + S3C64XX_SPI_PACKET_CNT);
399                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
400                 }
401         }
402
403         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
404         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
405 }
406
407 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
408                                                 struct spi_device *spi)
409 {
410         struct s3c64xx_spi_csinfo *cs;
411
412         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
413                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
414                         /* Deselect the last toggled device */
415                         cs = sdd->tgl_spi->controller_data;
416                         gpio_set_value(cs->line,
417                                 spi->mode & SPI_CS_HIGH ? 0 : 1);
418                 }
419                 sdd->tgl_spi = NULL;
420         }
421
422         cs = spi->controller_data;
423         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
424 }
425
426 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
427                                 struct spi_transfer *xfer, int dma_mode)
428 {
429         void __iomem *regs = sdd->regs;
430         unsigned long val;
431         int ms;
432
433         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
434         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
435         ms += 10; /* some tolerance */
436
437         if (dma_mode) {
438                 val = msecs_to_jiffies(ms) + 10;
439                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
440         } else {
441                 u32 status;
442                 val = msecs_to_loops(ms);
443                 do {
444                         status = readl(regs + S3C64XX_SPI_STATUS);
445                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
446         }
447
448         if (!val)
449                 return -EIO;
450
451         if (dma_mode) {
452                 u32 status;
453
454                 /*
455                  * DmaTx returns after simply writing data in the FIFO,
456                  * w/o waiting for real transmission on the bus to finish.
457                  * DmaRx returns only after Dma read data from FIFO which
458                  * needs bus transmission to finish, so we don't worry if
459                  * Xfer involved Rx(with or without Tx).
460                  */
461                 if (xfer->rx_buf == NULL) {
462                         val = msecs_to_loops(10);
463                         status = readl(regs + S3C64XX_SPI_STATUS);
464                         while ((TX_FIFO_LVL(status, sdd)
465                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
466                                         && --val) {
467                                 cpu_relax();
468                                 status = readl(regs + S3C64XX_SPI_STATUS);
469                         }
470
471                         if (!val)
472                                 return -EIO;
473                 }
474         } else {
475                 /* If it was only Tx */
476                 if (xfer->rx_buf == NULL) {
477                         sdd->state &= ~TXBUSY;
478                         return 0;
479                 }
480
481                 switch (sdd->cur_bpw) {
482                 case 32:
483                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
484                                 xfer->rx_buf, xfer->len / 4);
485                         break;
486                 case 16:
487                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
488                                 xfer->rx_buf, xfer->len / 2);
489                         break;
490                 default:
491                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
492                                 xfer->rx_buf, xfer->len);
493                         break;
494                 }
495                 sdd->state &= ~RXBUSY;
496         }
497
498         return 0;
499 }
500
501 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
502                                                 struct spi_device *spi)
503 {
504         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
505
506         if (sdd->tgl_spi == spi)
507                 sdd->tgl_spi = NULL;
508
509         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
510 }
511
512 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
513 {
514         void __iomem *regs = sdd->regs;
515         u32 val;
516
517         /* Disable Clock */
518         if (sdd->port_conf->clk_from_cmu) {
519                 clk_disable_unprepare(sdd->src_clk);
520         } else {
521                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
522                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
523                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
524         }
525
526         /* Set Polarity and Phase */
527         val = readl(regs + S3C64XX_SPI_CH_CFG);
528         val &= ~(S3C64XX_SPI_CH_SLAVE |
529                         S3C64XX_SPI_CPOL_L |
530                         S3C64XX_SPI_CPHA_B);
531
532         if (sdd->cur_mode & SPI_CPOL)
533                 val |= S3C64XX_SPI_CPOL_L;
534
535         if (sdd->cur_mode & SPI_CPHA)
536                 val |= S3C64XX_SPI_CPHA_B;
537
538         writel(val, regs + S3C64XX_SPI_CH_CFG);
539
540         /* Set Channel & DMA Mode */
541         val = readl(regs + S3C64XX_SPI_MODE_CFG);
542         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
543                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
544
545         switch (sdd->cur_bpw) {
546         case 32:
547                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
548                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
549                 break;
550         case 16:
551                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
552                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
553                 break;
554         default:
555                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
556                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
557                 break;
558         }
559
560         writel(val, regs + S3C64XX_SPI_MODE_CFG);
561
562         if (sdd->port_conf->clk_from_cmu) {
563                 /* Configure Clock */
564                 /* There is half-multiplier before the SPI */
565                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
566                 /* Enable Clock */
567                 clk_prepare_enable(sdd->src_clk);
568         } else {
569                 /* Configure Clock */
570                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
571                 val &= ~S3C64XX_SPI_PSR_MASK;
572                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
573                                 & S3C64XX_SPI_PSR_MASK);
574                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
575
576                 /* Enable Clock */
577                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
578                 val |= S3C64XX_SPI_ENCLK_ENABLE;
579                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
580         }
581 }
582
583 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
584
585 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
586                                                 struct spi_message *msg)
587 {
588         struct device *dev = &sdd->pdev->dev;
589         struct spi_transfer *xfer;
590
591         if (msg->is_dma_mapped)
592                 return 0;
593
594         /* First mark all xfer unmapped */
595         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
596                 xfer->rx_dma = XFER_DMAADDR_INVALID;
597                 xfer->tx_dma = XFER_DMAADDR_INVALID;
598         }
599
600         /* Map until end or first fail */
601         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
602
603                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
604                         continue;
605
606                 if (xfer->tx_buf != NULL) {
607                         xfer->tx_dma = dma_map_single(dev,
608                                         (void *)xfer->tx_buf, xfer->len,
609                                         DMA_TO_DEVICE);
610                         if (dma_mapping_error(dev, xfer->tx_dma)) {
611                                 dev_err(dev, "dma_map_single Tx failed\n");
612                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
613                                 return -ENOMEM;
614                         }
615                 }
616
617                 if (xfer->rx_buf != NULL) {
618                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
619                                                 xfer->len, DMA_FROM_DEVICE);
620                         if (dma_mapping_error(dev, xfer->rx_dma)) {
621                                 dev_err(dev, "dma_map_single Rx failed\n");
622                                 dma_unmap_single(dev, xfer->tx_dma,
623                                                 xfer->len, DMA_TO_DEVICE);
624                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
625                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
626                                 return -ENOMEM;
627                         }
628                 }
629         }
630
631         return 0;
632 }
633
634 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
635                                                 struct spi_message *msg)
636 {
637         struct device *dev = &sdd->pdev->dev;
638         struct spi_transfer *xfer;
639
640         if (msg->is_dma_mapped)
641                 return;
642
643         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
644
645                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
646                         continue;
647
648                 if (xfer->rx_buf != NULL
649                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
650                         dma_unmap_single(dev, xfer->rx_dma,
651                                                 xfer->len, DMA_FROM_DEVICE);
652
653                 if (xfer->tx_buf != NULL
654                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
655                         dma_unmap_single(dev, xfer->tx_dma,
656                                                 xfer->len, DMA_TO_DEVICE);
657         }
658 }
659
660 static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
661                                             struct spi_message *msg)
662 {
663         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
664         struct spi_device *spi = msg->spi;
665         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
666         struct spi_transfer *xfer;
667         int status = 0, cs_toggle = 0;
668         u32 speed;
669         u8 bpw;
670
671         /* If Master's(controller) state differs from that needed by Slave */
672         if (sdd->cur_speed != spi->max_speed_hz
673                         || sdd->cur_mode != spi->mode
674                         || sdd->cur_bpw != spi->bits_per_word) {
675                 sdd->cur_bpw = spi->bits_per_word;
676                 sdd->cur_speed = spi->max_speed_hz;
677                 sdd->cur_mode = spi->mode;
678                 s3c64xx_spi_config(sdd);
679         }
680
681         /* Map all the transfers if needed */
682         if (s3c64xx_spi_map_mssg(sdd, msg)) {
683                 dev_err(&spi->dev,
684                         "Xfer: Unable to map message buffers!\n");
685                 status = -ENOMEM;
686                 goto out;
687         }
688
689         /* Configure feedback delay */
690         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
691
692         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
693
694                 unsigned long flags;
695                 int use_dma;
696
697                 INIT_COMPLETION(sdd->xfer_completion);
698
699                 /* Only BPW and Speed may change across transfers */
700                 bpw = xfer->bits_per_word;
701                 speed = xfer->speed_hz ? : spi->max_speed_hz;
702
703                 if (xfer->len % (bpw / 8)) {
704                         dev_err(&spi->dev,
705                                 "Xfer length(%u) not a multiple of word size(%u)\n",
706                                 xfer->len, bpw / 8);
707                         status = -EIO;
708                         goto out;
709                 }
710
711                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
712                         sdd->cur_bpw = bpw;
713                         sdd->cur_speed = speed;
714                         s3c64xx_spi_config(sdd);
715                 }
716
717                 /* Polling method for xfers not bigger than FIFO capacity */
718                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
719                         use_dma = 0;
720                 else
721                         use_dma = 1;
722
723                 spin_lock_irqsave(&sdd->lock, flags);
724
725                 /* Pending only which is to be done */
726                 sdd->state &= ~RXBUSY;
727                 sdd->state &= ~TXBUSY;
728
729                 enable_datapath(sdd, spi, xfer, use_dma);
730
731                 /* Slave Select */
732                 enable_cs(sdd, spi);
733
734                 /* Start the signals */
735                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
736
737                 spin_unlock_irqrestore(&sdd->lock, flags);
738
739                 status = wait_for_xfer(sdd, xfer, use_dma);
740
741                 /* Quiese the signals */
742                 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
743                        sdd->regs + S3C64XX_SPI_SLAVE_SEL);
744
745                 if (status) {
746                         dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
747                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
748                                 (sdd->state & RXBUSY) ? 'f' : 'p',
749                                 (sdd->state & TXBUSY) ? 'f' : 'p',
750                                 xfer->len);
751
752                         if (use_dma) {
753                                 if (xfer->tx_buf != NULL
754                                                 && (sdd->state & TXBUSY))
755                                         sdd->ops->stop(sdd->tx_dma.ch);
756                                 if (xfer->rx_buf != NULL
757                                                 && (sdd->state & RXBUSY))
758                                         sdd->ops->stop(sdd->rx_dma.ch);
759                         }
760
761                         goto out;
762                 }
763
764                 if (xfer->delay_usecs)
765                         udelay(xfer->delay_usecs);
766
767                 if (xfer->cs_change) {
768                         /* Hint that the next mssg is gonna be
769                            for the same device */
770                         if (list_is_last(&xfer->transfer_list,
771                                                 &msg->transfers))
772                                 cs_toggle = 1;
773                 }
774
775                 msg->actual_length += xfer->len;
776
777                 flush_fifo(sdd);
778         }
779
780 out:
781         if (!cs_toggle || status)
782                 disable_cs(sdd, spi);
783         else
784                 sdd->tgl_spi = spi;
785
786         s3c64xx_spi_unmap_mssg(sdd, msg);
787
788         msg->status = status;
789
790         spi_finalize_current_message(master);
791
792         return 0;
793 }
794
795 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
796 {
797         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
798
799         /* Acquire DMA channels */
800         while (!acquire_dma(sdd))
801                 usleep_range(10000, 11000);
802
803         pm_runtime_get_sync(&sdd->pdev->dev);
804
805         return 0;
806 }
807
808 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
809 {
810         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
811
812         /* Free DMA channels */
813         sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
814         sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
815
816         pm_runtime_put(&sdd->pdev->dev);
817
818         return 0;
819 }
820
821 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
822                                 struct s3c64xx_spi_driver_data *sdd,
823                                 struct spi_device *spi)
824 {
825         struct s3c64xx_spi_csinfo *cs;
826         struct device_node *slave_np, *data_np = NULL;
827         u32 fb_delay = 0;
828
829         slave_np = spi->dev.of_node;
830         if (!slave_np) {
831                 dev_err(&spi->dev, "device node not found\n");
832                 return ERR_PTR(-EINVAL);
833         }
834
835         data_np = of_get_child_by_name(slave_np, "controller-data");
836         if (!data_np) {
837                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
838                 return ERR_PTR(-EINVAL);
839         }
840
841         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
842         if (!cs) {
843                 dev_err(&spi->dev, "could not allocate memory for controller data\n");
844                 of_node_put(data_np);
845                 return ERR_PTR(-ENOMEM);
846         }
847
848         cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
849         if (!gpio_is_valid(cs->line)) {
850                 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
851                 kfree(cs);
852                 of_node_put(data_np);
853                 return ERR_PTR(-EINVAL);
854         }
855
856         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
857         cs->fb_delay = fb_delay;
858         of_node_put(data_np);
859         return cs;
860 }
861
862 /*
863  * Here we only check the validity of requested configuration
864  * and save the configuration in a local data-structure.
865  * The controller is actually configured only just before we
866  * get a message to transfer.
867  */
868 static int s3c64xx_spi_setup(struct spi_device *spi)
869 {
870         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
871         struct s3c64xx_spi_driver_data *sdd;
872         struct s3c64xx_spi_info *sci;
873         struct spi_message *msg;
874         unsigned long flags;
875         int err;
876
877         sdd = spi_master_get_devdata(spi->master);
878         if (!cs && spi->dev.of_node) {
879                 cs = s3c64xx_get_slave_ctrldata(sdd, spi);
880                 spi->controller_data = cs;
881         }
882
883         if (IS_ERR_OR_NULL(cs)) {
884                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
885                 return -ENODEV;
886         }
887
888         if (!spi_get_ctldata(spi)) {
889                 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
890                                        dev_name(&spi->dev));
891                 if (err) {
892                         dev_err(&spi->dev,
893                                 "Failed to get /CS gpio [%d]: %d\n",
894                                 cs->line, err);
895                         goto err_gpio_req;
896                 }
897                 spi_set_ctldata(spi, cs);
898         }
899
900         sci = sdd->cntrlr_info;
901
902         spin_lock_irqsave(&sdd->lock, flags);
903
904         list_for_each_entry(msg, &sdd->queue, queue) {
905                 /* Is some mssg is already queued for this device */
906                 if (msg->spi == spi) {
907                         dev_err(&spi->dev,
908                                 "setup: attempt while mssg in queue!\n");
909                         spin_unlock_irqrestore(&sdd->lock, flags);
910                         err = -EBUSY;
911                         goto err_msgq;
912                 }
913         }
914
915         spin_unlock_irqrestore(&sdd->lock, flags);
916
917         if (spi->bits_per_word != 8
918                         && spi->bits_per_word != 16
919                         && spi->bits_per_word != 32) {
920                 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
921                                                         spi->bits_per_word);
922                 err = -EINVAL;
923                 goto setup_exit;
924         }
925
926         pm_runtime_get_sync(&sdd->pdev->dev);
927
928         /* Check if we can provide the requested rate */
929         if (!sdd->port_conf->clk_from_cmu) {
930                 u32 psr, speed;
931
932                 /* Max possible */
933                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
934
935                 if (spi->max_speed_hz > speed)
936                         spi->max_speed_hz = speed;
937
938                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
939                 psr &= S3C64XX_SPI_PSR_MASK;
940                 if (psr == S3C64XX_SPI_PSR_MASK)
941                         psr--;
942
943                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
944                 if (spi->max_speed_hz < speed) {
945                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
946                                 psr++;
947                         } else {
948                                 err = -EINVAL;
949                                 goto setup_exit;
950                         }
951                 }
952
953                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
954                 if (spi->max_speed_hz >= speed) {
955                         spi->max_speed_hz = speed;
956                 } else {
957                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
958                                 spi->max_speed_hz);
959                         err = -EINVAL;
960                         goto setup_exit;
961                 }
962         }
963
964         pm_runtime_put(&sdd->pdev->dev);
965         disable_cs(sdd, spi);
966         return 0;
967
968 setup_exit:
969         /* setup() returns with device de-selected */
970         disable_cs(sdd, spi);
971
972 err_msgq:
973         gpio_free(cs->line);
974         spi_set_ctldata(spi, NULL);
975
976 err_gpio_req:
977         if (spi->dev.of_node)
978                 kfree(cs);
979
980         return err;
981 }
982
983 static void s3c64xx_spi_cleanup(struct spi_device *spi)
984 {
985         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
986
987         if (cs) {
988                 gpio_free(cs->line);
989                 if (spi->dev.of_node)
990                         kfree(cs);
991         }
992         spi_set_ctldata(spi, NULL);
993 }
994
995 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
996 {
997         struct s3c64xx_spi_driver_data *sdd = data;
998         struct spi_master *spi = sdd->master;
999         unsigned int val;
1000
1001         val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
1002
1003         val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1004                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1005                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1006                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1007
1008         writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1009
1010         if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
1011                 dev_err(&spi->dev, "RX overrun\n");
1012         if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
1013                 dev_err(&spi->dev, "RX underrun\n");
1014         if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
1015                 dev_err(&spi->dev, "TX overrun\n");
1016         if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
1017                 dev_err(&spi->dev, "TX underrun\n");
1018
1019         return IRQ_HANDLED;
1020 }
1021
1022 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1023 {
1024         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1025         void __iomem *regs = sdd->regs;
1026         unsigned int val;
1027
1028         sdd->cur_speed = 0;
1029
1030         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1031
1032         /* Disable Interrupts - we use Polling if not DMA mode */
1033         writel(0, regs + S3C64XX_SPI_INT_EN);
1034
1035         if (!sdd->port_conf->clk_from_cmu)
1036                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1037                                 regs + S3C64XX_SPI_CLK_CFG);
1038         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1039         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1040
1041         /* Clear any irq pending bits */
1042         writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
1043                                 regs + S3C64XX_SPI_PENDING_CLR);
1044
1045         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1046
1047         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1048         val &= ~S3C64XX_SPI_MODE_4BURST;
1049         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1050         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1051         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1052
1053         flush_fifo(sdd);
1054 }
1055
1056 static int s3c64xx_spi_get_dmares(
1057                         struct s3c64xx_spi_driver_data *sdd, bool tx)
1058 {
1059         struct platform_device *pdev = sdd->pdev;
1060         struct s3c64xx_spi_dma_data *dma_data;
1061         struct property *prop;
1062         struct resource *res;
1063         char prop_name[15], *chan_str;
1064
1065         if (tx) {
1066                 dma_data = &sdd->tx_dma;
1067                 dma_data->direction = DMA_MEM_TO_DEV;
1068                 chan_str = "tx";
1069         } else {
1070                 dma_data = &sdd->rx_dma;
1071                 dma_data->direction = DMA_DEV_TO_MEM;
1072                 chan_str = "rx";
1073         }
1074
1075         if (!sdd->pdev->dev.of_node) {
1076                 res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
1077                 if (!res) {
1078                         dev_err(&pdev->dev, "Unable to get SPI-%s dma resource\n",
1079                                 chan_str);
1080                         return -ENXIO;
1081                 }
1082                 dma_data->dmach = res->start;
1083                 return 0;
1084         }
1085
1086         sprintf(prop_name, "%s-dma-channel", chan_str);
1087         prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
1088         if (!prop) {
1089                 dev_err(&pdev->dev, "%s dma channel property not specified\n",
1090                                         chan_str);
1091                 return -ENXIO;
1092         }
1093
1094         dma_data->dmach = DMACH_DT_PROP;
1095         dma_data->dma_prop = prop;
1096         return 0;
1097 }
1098
1099 #ifdef CONFIG_OF
1100 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1101 {
1102         struct device *dev = &sdd->pdev->dev;
1103         int idx, gpio, ret;
1104
1105         /* find gpios for mosi, miso and clock lines */
1106         for (idx = 0; idx < 3; idx++) {
1107                 gpio = of_get_gpio(dev->of_node, idx);
1108                 if (!gpio_is_valid(gpio)) {
1109                         dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1110                         goto free_gpio;
1111                 }
1112                 sdd->gpios[idx] = gpio;
1113                 ret = gpio_request(gpio, "spi-bus");
1114                 if (ret) {
1115                         dev_err(dev, "gpio [%d] request failed: %d\n",
1116                                 gpio, ret);
1117                         goto free_gpio;
1118                 }
1119         }
1120         return 0;
1121
1122 free_gpio:
1123         while (--idx >= 0)
1124                 gpio_free(sdd->gpios[idx]);
1125         return -EINVAL;
1126 }
1127
1128 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1129 {
1130         unsigned int idx;
1131         for (idx = 0; idx < 3; idx++)
1132                 gpio_free(sdd->gpios[idx]);
1133 }
1134
1135 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1136 {
1137         struct s3c64xx_spi_info *sci;
1138         u32 temp;
1139
1140         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1141         if (!sci) {
1142                 dev_err(dev, "memory allocation for spi_info failed\n");
1143                 return ERR_PTR(-ENOMEM);
1144         }
1145
1146         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1147                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1148                 sci->src_clk_nr = 0;
1149         } else {
1150                 sci->src_clk_nr = temp;
1151         }
1152
1153         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1154                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1155                 sci->num_cs = 1;
1156         } else {
1157                 sci->num_cs = temp;
1158         }
1159
1160         return sci;
1161 }
1162 #else
1163 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1164 {
1165         return dev->platform_data;
1166 }
1167
1168 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1169 {
1170         return -EINVAL;
1171 }
1172
1173 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1174 {
1175 }
1176 #endif
1177
1178 static const struct of_device_id s3c64xx_spi_dt_match[];
1179
1180 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1181                                                 struct platform_device *pdev)
1182 {
1183 #ifdef CONFIG_OF
1184         if (pdev->dev.of_node) {
1185                 const struct of_device_id *match;
1186                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1187                 return (struct s3c64xx_spi_port_config *)match->data;
1188         }
1189 #endif
1190         return (struct s3c64xx_spi_port_config *)
1191                          platform_get_device_id(pdev)->driver_data;
1192 }
1193
1194 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1195 {
1196         struct resource *mem_res;
1197         struct s3c64xx_spi_driver_data *sdd;
1198         struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
1199         struct spi_master *master;
1200         int ret, irq;
1201         char clk_name[16];
1202
1203         if (!sci && pdev->dev.of_node) {
1204                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1205                 if (IS_ERR(sci))
1206                         return PTR_ERR(sci);
1207         }
1208
1209         if (!sci) {
1210                 dev_err(&pdev->dev, "platform_data missing!\n");
1211                 return -ENODEV;
1212         }
1213
1214         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1215         if (mem_res == NULL) {
1216                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1217                 return -ENXIO;
1218         }
1219
1220         irq = platform_get_irq(pdev, 0);
1221         if (irq < 0) {
1222                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1223                 return irq;
1224         }
1225
1226         master = spi_alloc_master(&pdev->dev,
1227                                 sizeof(struct s3c64xx_spi_driver_data));
1228         if (master == NULL) {
1229                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1230                 return -ENOMEM;
1231         }
1232
1233         platform_set_drvdata(pdev, master);
1234
1235         sdd = spi_master_get_devdata(master);
1236         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1237         sdd->master = master;
1238         sdd->cntrlr_info = sci;
1239         sdd->pdev = pdev;
1240         sdd->sfr_start = mem_res->start;
1241         if (pdev->dev.of_node) {
1242                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1243                 if (ret < 0) {
1244                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1245                                 ret);
1246                         goto err0;
1247                 }
1248                 sdd->port_id = ret;
1249         } else {
1250                 sdd->port_id = pdev->id;
1251         }
1252
1253         sdd->cur_bpw = 8;
1254
1255         ret = s3c64xx_spi_get_dmares(sdd, true);
1256         if (ret)
1257                 goto err0;
1258
1259         ret = s3c64xx_spi_get_dmares(sdd, false);
1260         if (ret)
1261                 goto err0;
1262
1263         master->dev.of_node = pdev->dev.of_node;
1264         master->bus_num = sdd->port_id;
1265         master->setup = s3c64xx_spi_setup;
1266         master->cleanup = s3c64xx_spi_cleanup;
1267         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1268         master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1269         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1270         master->num_chipselect = sci->num_cs;
1271         master->dma_alignment = 8;
1272         /* the spi->mode bits understood by this driver: */
1273         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1274
1275         sdd->regs = devm_request_and_ioremap(&pdev->dev, mem_res);
1276         if (sdd->regs == NULL) {
1277                 dev_err(&pdev->dev, "Unable to remap IO\n");
1278                 ret = -ENXIO;
1279                 goto err0;
1280         }
1281
1282         if (!sci->cfg_gpio && pdev->dev.of_node) {
1283                 if (s3c64xx_spi_parse_dt_gpio(sdd))
1284                         return -EBUSY;
1285         } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
1286                 dev_err(&pdev->dev, "Unable to config gpio\n");
1287                 ret = -EBUSY;
1288                 goto err0;
1289         }
1290
1291         /* Setup clocks */
1292         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1293         if (IS_ERR(sdd->clk)) {
1294                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1295                 ret = PTR_ERR(sdd->clk);
1296                 goto err1;
1297         }
1298
1299         if (clk_prepare_enable(sdd->clk)) {
1300                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1301                 ret = -EBUSY;
1302                 goto err1;
1303         }
1304
1305         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1306         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1307         if (IS_ERR(sdd->src_clk)) {
1308                 dev_err(&pdev->dev,
1309                         "Unable to acquire clock '%s'\n", clk_name);
1310                 ret = PTR_ERR(sdd->src_clk);
1311                 goto err2;
1312         }
1313
1314         if (clk_prepare_enable(sdd->src_clk)) {
1315                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1316                 ret = -EBUSY;
1317                 goto err2;
1318         }
1319
1320         /* Setup Deufult Mode */
1321         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1322
1323         spin_lock_init(&sdd->lock);
1324         init_completion(&sdd->xfer_completion);
1325         INIT_LIST_HEAD(&sdd->queue);
1326
1327         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1328                                 "spi-s3c64xx", sdd);
1329         if (ret != 0) {
1330                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1331                         irq, ret);
1332                 goto err3;
1333         }
1334
1335         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1336                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1337                sdd->regs + S3C64XX_SPI_INT_EN);
1338
1339         if (spi_register_master(master)) {
1340                 dev_err(&pdev->dev, "cannot register SPI master\n");
1341                 ret = -EBUSY;
1342                 goto err3;
1343         }
1344
1345         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1346                                         sdd->port_id, master->num_chipselect);
1347         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1348                                         mem_res->end, mem_res->start,
1349                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1350
1351         pm_runtime_enable(&pdev->dev);
1352
1353         return 0;
1354
1355 err3:
1356         clk_disable_unprepare(sdd->src_clk);
1357 err2:
1358         clk_disable_unprepare(sdd->clk);
1359 err1:
1360         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1361                 s3c64xx_spi_dt_gpio_free(sdd);
1362 err0:
1363         platform_set_drvdata(pdev, NULL);
1364         spi_master_put(master);
1365
1366         return ret;
1367 }
1368
1369 static int s3c64xx_spi_remove(struct platform_device *pdev)
1370 {
1371         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1372         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1373
1374         pm_runtime_disable(&pdev->dev);
1375
1376         spi_unregister_master(master);
1377
1378         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1379
1380         clk_disable_unprepare(sdd->src_clk);
1381
1382         clk_disable_unprepare(sdd->clk);
1383
1384         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1385                 s3c64xx_spi_dt_gpio_free(sdd);
1386
1387         platform_set_drvdata(pdev, NULL);
1388         spi_master_put(master);
1389
1390         return 0;
1391 }
1392
1393 #ifdef CONFIG_PM
1394 static int s3c64xx_spi_suspend(struct device *dev)
1395 {
1396         struct spi_master *master = dev_get_drvdata(dev);
1397         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1398
1399         spi_master_suspend(master);
1400
1401         /* Disable the clock */
1402         clk_disable_unprepare(sdd->src_clk);
1403         clk_disable_unprepare(sdd->clk);
1404
1405         if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1406                 s3c64xx_spi_dt_gpio_free(sdd);
1407
1408         sdd->cur_speed = 0; /* Output Clock is stopped */
1409
1410         return 0;
1411 }
1412
1413 static int s3c64xx_spi_resume(struct device *dev)
1414 {
1415         struct spi_master *master = dev_get_drvdata(dev);
1416         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1417         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1418
1419         if (!sci->cfg_gpio && dev->of_node)
1420                 s3c64xx_spi_parse_dt_gpio(sdd);
1421         else
1422                 sci->cfg_gpio();
1423
1424         /* Enable the clock */
1425         clk_prepare_enable(sdd->src_clk);
1426         clk_prepare_enable(sdd->clk);
1427
1428         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1429
1430         spi_master_resume(master);
1431
1432         return 0;
1433 }
1434 #endif /* CONFIG_PM */
1435
1436 #ifdef CONFIG_PM_RUNTIME
1437 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1438 {
1439         struct spi_master *master = dev_get_drvdata(dev);
1440         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1441
1442         clk_disable_unprepare(sdd->clk);
1443         clk_disable_unprepare(sdd->src_clk);
1444
1445         return 0;
1446 }
1447
1448 static int s3c64xx_spi_runtime_resume(struct device *dev)
1449 {
1450         struct spi_master *master = dev_get_drvdata(dev);
1451         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1452
1453         clk_prepare_enable(sdd->src_clk);
1454         clk_prepare_enable(sdd->clk);
1455
1456         return 0;
1457 }
1458 #endif /* CONFIG_PM_RUNTIME */
1459
1460 static const struct dev_pm_ops s3c64xx_spi_pm = {
1461         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1462         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1463                            s3c64xx_spi_runtime_resume, NULL)
1464 };
1465
1466 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1467         .fifo_lvl_mask  = { 0x7f },
1468         .rx_lvl_offset  = 13,
1469         .tx_st_done     = 21,
1470         .high_speed     = true,
1471 };
1472
1473 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1474         .fifo_lvl_mask  = { 0x7f, 0x7F },
1475         .rx_lvl_offset  = 13,
1476         .tx_st_done     = 21,
1477 };
1478
1479 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1480         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1481         .rx_lvl_offset  = 15,
1482         .tx_st_done     = 25,
1483 };
1484
1485 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1486         .fifo_lvl_mask  = { 0x7f, 0x7F },
1487         .rx_lvl_offset  = 13,
1488         .tx_st_done     = 21,
1489         .high_speed     = true,
1490 };
1491
1492 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1493         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1494         .rx_lvl_offset  = 15,
1495         .tx_st_done     = 25,
1496         .high_speed     = true,
1497 };
1498
1499 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1500         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1501         .rx_lvl_offset  = 15,
1502         .tx_st_done     = 25,
1503         .high_speed     = true,
1504         .clk_from_cmu   = true,
1505 };
1506
1507 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1508         {
1509                 .name           = "s3c2443-spi",
1510                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1511         }, {
1512                 .name           = "s3c6410-spi",
1513                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1514         }, {
1515                 .name           = "s5p64x0-spi",
1516                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1517         }, {
1518                 .name           = "s5pc100-spi",
1519                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1520         }, {
1521                 .name           = "s5pv210-spi",
1522                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1523         }, {
1524                 .name           = "exynos4210-spi",
1525                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1526         },
1527         { },
1528 };
1529
1530 #ifdef CONFIG_OF
1531 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1532         { .compatible = "samsung,exynos4210-spi",
1533                         .data = (void *)&exynos4_spi_port_config,
1534         },
1535         { },
1536 };
1537 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1538 #endif /* CONFIG_OF */
1539
1540 static struct platform_driver s3c64xx_spi_driver = {
1541         .driver = {
1542                 .name   = "s3c64xx-spi",
1543                 .owner = THIS_MODULE,
1544                 .pm = &s3c64xx_spi_pm,
1545                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1546         },
1547         .remove = s3c64xx_spi_remove,
1548         .id_table = s3c64xx_spi_driver_ids,
1549 };
1550 MODULE_ALIAS("platform:s3c64xx-spi");
1551
1552 static int __init s3c64xx_spi_init(void)
1553 {
1554         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1555 }
1556 subsys_initcall(s3c64xx_spi_init);
1557
1558 static void __exit s3c64xx_spi_exit(void)
1559 {
1560         platform_driver_unregister(&s3c64xx_spi_driver);
1561 }
1562 module_exit(s3c64xx_spi_exit);
1563
1564 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1565 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1566 MODULE_LICENSE("GPL");