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tty: serial: OMAP: block idle while the UART is transferring data in PIO mode
[~shefty/rdma-dev.git] / drivers / tty / serial / omap-serial.c
1 /*
2  * Driver for OMAP-UART controller.
3  * Based on drivers/serial/8250.c
4  *
5  * Copyright (C) 2010 Texas Instruments.
6  *
7  * Authors:
8  *      Govindraj R     <govindraj.raja@ti.com>
9  *      Thara Gopinath  <thara@ti.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * Note: This driver is made separate from 8250 driver as we cannot
17  * over load 8250 driver with omap platform specific configuration for
18  * features like DMA, it makes easier to implement features like DMA and
19  * hardware flow control and software flow control configuration with
20  * this driver as required for the omap-platform.
21  */
22
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/io.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/of.h>
42
43 #include <plat/dma.h>
44 #include <plat/dmtimer.h>
45 #include <plat/omap-serial.h>
46
47 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
48
49 /* SCR register bitmasks */
50 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
51
52 /* FCR register bitmasks */
53 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT                6
54 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
55
56 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
57
58 /* Forward declaration of functions */
59 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
60 static void serial_omap_rxdma_poll(unsigned long uart_no);
61 static int serial_omap_start_rxdma(struct uart_omap_port *up);
62 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
63
64 static struct workqueue_struct *serial_omap_uart_wq;
65
66 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
67 {
68         offset <<= up->port.regshift;
69         return readw(up->port.membase + offset);
70 }
71
72 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
73 {
74         offset <<= up->port.regshift;
75         writew(value, up->port.membase + offset);
76 }
77
78 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
79 {
80         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
81         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
82                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
83         serial_out(up, UART_FCR, 0);
84 }
85
86 /*
87  * serial_omap_get_divisor - calculate divisor value
88  * @port: uart port info
89  * @baud: baudrate for which divisor needs to be calculated.
90  *
91  * We have written our own function to get the divisor so as to support
92  * 13x mode. 3Mbps Baudrate as an different divisor.
93  * Reference OMAP TRM Chapter 17:
94  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
95  * referring to oversampling - divisor value
96  * baudrate 460,800 to 3,686,400 all have divisor 13
97  * except 3,000,000 which has divisor value 16
98  */
99 static unsigned int
100 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
101 {
102         unsigned int divisor;
103
104         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
105                 divisor = 13;
106         else
107                 divisor = 16;
108         return port->uartclk/(baud * divisor);
109 }
110
111 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
112 {
113         if (up->uart_dma.rx_dma_used) {
114                 del_timer(&up->uart_dma.rx_timer);
115                 omap_stop_dma(up->uart_dma.rx_dma_channel);
116                 omap_free_dma(up->uart_dma.rx_dma_channel);
117                 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
118                 up->uart_dma.rx_dma_used = false;
119                 pm_runtime_mark_last_busy(&up->pdev->dev);
120                 pm_runtime_put_autosuspend(&up->pdev->dev);
121         }
122 }
123
124 static void serial_omap_enable_ms(struct uart_port *port)
125 {
126         struct uart_omap_port *up = (struct uart_omap_port *)port;
127
128         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
129
130         pm_runtime_get_sync(&up->pdev->dev);
131         up->ier |= UART_IER_MSI;
132         serial_out(up, UART_IER, up->ier);
133         pm_runtime_put(&up->pdev->dev);
134 }
135
136 static void serial_omap_stop_tx(struct uart_port *port)
137 {
138         struct uart_omap_port *up = (struct uart_omap_port *)port;
139         struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
140
141         if (up->use_dma &&
142                 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
143                 /*
144                  * Check if dma is still active. If yes do nothing,
145                  * return. Else stop dma
146                  */
147                 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
148                         return;
149                 omap_stop_dma(up->uart_dma.tx_dma_channel);
150                 omap_free_dma(up->uart_dma.tx_dma_channel);
151                 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
152                 pm_runtime_mark_last_busy(&up->pdev->dev);
153                 pm_runtime_put_autosuspend(&up->pdev->dev);
154         }
155
156         pm_runtime_get_sync(&up->pdev->dev);
157         if (up->ier & UART_IER_THRI) {
158                 up->ier &= ~UART_IER_THRI;
159                 serial_out(up, UART_IER, up->ier);
160         }
161
162         if (!up->use_dma && pdata->set_forceidle)
163                 pdata->set_forceidle(up->pdev);
164
165         pm_runtime_mark_last_busy(&up->pdev->dev);
166         pm_runtime_put_autosuspend(&up->pdev->dev);
167 }
168
169 static void serial_omap_stop_rx(struct uart_port *port)
170 {
171         struct uart_omap_port *up = (struct uart_omap_port *)port;
172
173         pm_runtime_get_sync(&up->pdev->dev);
174         if (up->use_dma)
175                 serial_omap_stop_rxdma(up);
176         up->ier &= ~UART_IER_RLSI;
177         up->port.read_status_mask &= ~UART_LSR_DR;
178         serial_out(up, UART_IER, up->ier);
179         pm_runtime_mark_last_busy(&up->pdev->dev);
180         pm_runtime_put_autosuspend(&up->pdev->dev);
181 }
182
183 static inline void receive_chars(struct uart_omap_port *up,
184                 unsigned int *status)
185 {
186         struct tty_struct *tty = up->port.state->port.tty;
187         unsigned int flag, lsr = *status;
188         unsigned char ch = 0;
189         int max_count = 256;
190
191         do {
192                 if (likely(lsr & UART_LSR_DR))
193                         ch = serial_in(up, UART_RX);
194                 flag = TTY_NORMAL;
195                 up->port.icount.rx++;
196
197                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
198                         /*
199                          * For statistics only
200                          */
201                         if (lsr & UART_LSR_BI) {
202                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
203                                 up->port.icount.brk++;
204                                 /*
205                                  * We do the SysRQ and SAK checking
206                                  * here because otherwise the break
207                                  * may get masked by ignore_status_mask
208                                  * or read_status_mask.
209                                  */
210                                 if (uart_handle_break(&up->port))
211                                         goto ignore_char;
212                         } else if (lsr & UART_LSR_PE) {
213                                 up->port.icount.parity++;
214                         } else if (lsr & UART_LSR_FE) {
215                                 up->port.icount.frame++;
216                         }
217
218                         if (lsr & UART_LSR_OE)
219                                 up->port.icount.overrun++;
220
221                         /*
222                          * Mask off conditions which should be ignored.
223                          */
224                         lsr &= up->port.read_status_mask;
225
226 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
227                         if (up->port.line == up->port.cons->index) {
228                                 /* Recover the break flag from console xmit */
229                                 lsr |= up->lsr_break_flag;
230                         }
231 #endif
232                         if (lsr & UART_LSR_BI)
233                                 flag = TTY_BREAK;
234                         else if (lsr & UART_LSR_PE)
235                                 flag = TTY_PARITY;
236                         else if (lsr & UART_LSR_FE)
237                                 flag = TTY_FRAME;
238                 }
239
240                 if (uart_handle_sysrq_char(&up->port, ch))
241                         goto ignore_char;
242                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
243 ignore_char:
244                 lsr = serial_in(up, UART_LSR);
245         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
246         spin_unlock(&up->port.lock);
247         tty_flip_buffer_push(tty);
248         spin_lock(&up->port.lock);
249 }
250
251 static void transmit_chars(struct uart_omap_port *up)
252 {
253         struct circ_buf *xmit = &up->port.state->xmit;
254         int count;
255
256         if (up->port.x_char) {
257                 serial_out(up, UART_TX, up->port.x_char);
258                 up->port.icount.tx++;
259                 up->port.x_char = 0;
260                 return;
261         }
262         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
263                 serial_omap_stop_tx(&up->port);
264                 return;
265         }
266         count = up->port.fifosize / 4;
267         do {
268                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
269                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
270                 up->port.icount.tx++;
271                 if (uart_circ_empty(xmit))
272                         break;
273         } while (--count > 0);
274
275         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
276                 uart_write_wakeup(&up->port);
277
278         if (uart_circ_empty(xmit))
279                 serial_omap_stop_tx(&up->port);
280 }
281
282 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
283 {
284         if (!(up->ier & UART_IER_THRI)) {
285                 up->ier |= UART_IER_THRI;
286                 serial_out(up, UART_IER, up->ier);
287         }
288 }
289
290 static void serial_omap_start_tx(struct uart_port *port)
291 {
292         struct uart_omap_port *up = (struct uart_omap_port *)port;
293         struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
294         struct circ_buf *xmit;
295         unsigned int start;
296         int ret = 0;
297
298         if (!up->use_dma) {
299                 pm_runtime_get_sync(&up->pdev->dev);
300                 serial_omap_enable_ier_thri(up);
301                 if (pdata->set_noidle)
302                         pdata->set_noidle(up->pdev);
303                 pm_runtime_mark_last_busy(&up->pdev->dev);
304                 pm_runtime_put_autosuspend(&up->pdev->dev);
305                 return;
306         }
307
308         if (up->uart_dma.tx_dma_used)
309                 return;
310
311         xmit = &up->port.state->xmit;
312
313         if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
314                 pm_runtime_get_sync(&up->pdev->dev);
315                 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
316                                 "UART Tx DMA",
317                                 (void *)uart_tx_dma_callback, up,
318                                 &(up->uart_dma.tx_dma_channel));
319
320                 if (ret < 0) {
321                         serial_omap_enable_ier_thri(up);
322                         return;
323                 }
324         }
325         spin_lock(&(up->uart_dma.tx_lock));
326         up->uart_dma.tx_dma_used = true;
327         spin_unlock(&(up->uart_dma.tx_lock));
328
329         start = up->uart_dma.tx_buf_dma_phys +
330                                 (xmit->tail & (UART_XMIT_SIZE - 1));
331
332         up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
333         /*
334          * It is a circular buffer. See if the buffer has wounded back.
335          * If yes it will have to be transferred in two separate dma
336          * transfers
337          */
338         if (start + up->uart_dma.tx_buf_size >=
339                         up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
340                 up->uart_dma.tx_buf_size =
341                         (up->uart_dma.tx_buf_dma_phys +
342                         UART_XMIT_SIZE) - start;
343
344         omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
345                                 OMAP_DMA_AMODE_CONSTANT,
346                                 up->uart_dma.uart_base, 0, 0);
347         omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
348                                 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
349         omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
350                                 OMAP_DMA_DATA_TYPE_S8,
351                                 up->uart_dma.tx_buf_size, 1,
352                                 OMAP_DMA_SYNC_ELEMENT,
353                                 up->uart_dma.uart_dma_tx, 0);
354         /* FIXME: Cache maintenance needed here? */
355         omap_start_dma(up->uart_dma.tx_dma_channel);
356 }
357
358 static unsigned int check_modem_status(struct uart_omap_port *up)
359 {
360         unsigned int status;
361
362         status = serial_in(up, UART_MSR);
363         status |= up->msr_saved_flags;
364         up->msr_saved_flags = 0;
365         if ((status & UART_MSR_ANY_DELTA) == 0)
366                 return status;
367
368         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
369             up->port.state != NULL) {
370                 if (status & UART_MSR_TERI)
371                         up->port.icount.rng++;
372                 if (status & UART_MSR_DDSR)
373                         up->port.icount.dsr++;
374                 if (status & UART_MSR_DDCD)
375                         uart_handle_dcd_change
376                                 (&up->port, status & UART_MSR_DCD);
377                 if (status & UART_MSR_DCTS)
378                         uart_handle_cts_change
379                                 (&up->port, status & UART_MSR_CTS);
380                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
381         }
382
383         return status;
384 }
385
386 /**
387  * serial_omap_irq() - This handles the interrupt from one port
388  * @irq: uart port irq number
389  * @dev_id: uart port info
390  */
391 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
392 {
393         struct uart_omap_port *up = dev_id;
394         unsigned int iir, lsr;
395         unsigned long flags;
396
397         pm_runtime_get_sync(&up->pdev->dev);
398         iir = serial_in(up, UART_IIR);
399         if (iir & UART_IIR_NO_INT) {
400                 pm_runtime_mark_last_busy(&up->pdev->dev);
401                 pm_runtime_put_autosuspend(&up->pdev->dev);
402                 return IRQ_NONE;
403         }
404
405         spin_lock_irqsave(&up->port.lock, flags);
406         lsr = serial_in(up, UART_LSR);
407         if (iir & UART_IIR_RLSI) {
408                 if (!up->use_dma) {
409                         if (lsr & UART_LSR_DR)
410                                 receive_chars(up, &lsr);
411                 } else {
412                         up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
413                         serial_out(up, UART_IER, up->ier);
414                         if ((serial_omap_start_rxdma(up) != 0) &&
415                                         (lsr & UART_LSR_DR))
416                                 receive_chars(up, &lsr);
417                 }
418         }
419
420         check_modem_status(up);
421         if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
422                 transmit_chars(up);
423
424         spin_unlock_irqrestore(&up->port.lock, flags);
425         pm_runtime_mark_last_busy(&up->pdev->dev);
426         pm_runtime_put_autosuspend(&up->pdev->dev);
427
428         up->port_activity = jiffies;
429         return IRQ_HANDLED;
430 }
431
432 static unsigned int serial_omap_tx_empty(struct uart_port *port)
433 {
434         struct uart_omap_port *up = (struct uart_omap_port *)port;
435         unsigned long flags = 0;
436         unsigned int ret = 0;
437
438         pm_runtime_get_sync(&up->pdev->dev);
439         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
440         spin_lock_irqsave(&up->port.lock, flags);
441         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
442         spin_unlock_irqrestore(&up->port.lock, flags);
443         pm_runtime_put(&up->pdev->dev);
444         return ret;
445 }
446
447 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
448 {
449         struct uart_omap_port *up = (struct uart_omap_port *)port;
450         unsigned int status;
451         unsigned int ret = 0;
452
453         pm_runtime_get_sync(&up->pdev->dev);
454         status = check_modem_status(up);
455         pm_runtime_put(&up->pdev->dev);
456
457         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
458
459         if (status & UART_MSR_DCD)
460                 ret |= TIOCM_CAR;
461         if (status & UART_MSR_RI)
462                 ret |= TIOCM_RNG;
463         if (status & UART_MSR_DSR)
464                 ret |= TIOCM_DSR;
465         if (status & UART_MSR_CTS)
466                 ret |= TIOCM_CTS;
467         return ret;
468 }
469
470 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
471 {
472         struct uart_omap_port *up = (struct uart_omap_port *)port;
473         unsigned char mcr = 0;
474
475         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
476         if (mctrl & TIOCM_RTS)
477                 mcr |= UART_MCR_RTS;
478         if (mctrl & TIOCM_DTR)
479                 mcr |= UART_MCR_DTR;
480         if (mctrl & TIOCM_OUT1)
481                 mcr |= UART_MCR_OUT1;
482         if (mctrl & TIOCM_OUT2)
483                 mcr |= UART_MCR_OUT2;
484         if (mctrl & TIOCM_LOOP)
485                 mcr |= UART_MCR_LOOP;
486
487         pm_runtime_get_sync(&up->pdev->dev);
488         up->mcr = serial_in(up, UART_MCR);
489         up->mcr |= mcr;
490         serial_out(up, UART_MCR, up->mcr);
491         pm_runtime_put(&up->pdev->dev);
492 }
493
494 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
495 {
496         struct uart_omap_port *up = (struct uart_omap_port *)port;
497         unsigned long flags = 0;
498
499         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
500         pm_runtime_get_sync(&up->pdev->dev);
501         spin_lock_irqsave(&up->port.lock, flags);
502         if (break_state == -1)
503                 up->lcr |= UART_LCR_SBC;
504         else
505                 up->lcr &= ~UART_LCR_SBC;
506         serial_out(up, UART_LCR, up->lcr);
507         spin_unlock_irqrestore(&up->port.lock, flags);
508         pm_runtime_put(&up->pdev->dev);
509 }
510
511 static int serial_omap_startup(struct uart_port *port)
512 {
513         struct uart_omap_port *up = (struct uart_omap_port *)port;
514         unsigned long flags = 0;
515         int retval;
516
517         /*
518          * Allocate the IRQ
519          */
520         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
521                                 up->name, up);
522         if (retval)
523                 return retval;
524
525         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
526
527         pm_runtime_get_sync(&up->pdev->dev);
528         /*
529          * Clear the FIFO buffers and disable them.
530          * (they will be reenabled in set_termios())
531          */
532         serial_omap_clear_fifos(up);
533         /* For Hardware flow control */
534         serial_out(up, UART_MCR, UART_MCR_RTS);
535
536         /*
537          * Clear the interrupt registers.
538          */
539         (void) serial_in(up, UART_LSR);
540         if (serial_in(up, UART_LSR) & UART_LSR_DR)
541                 (void) serial_in(up, UART_RX);
542         (void) serial_in(up, UART_IIR);
543         (void) serial_in(up, UART_MSR);
544
545         /*
546          * Now, initialize the UART
547          */
548         serial_out(up, UART_LCR, UART_LCR_WLEN8);
549         spin_lock_irqsave(&up->port.lock, flags);
550         /*
551          * Most PC uarts need OUT2 raised to enable interrupts.
552          */
553         up->port.mctrl |= TIOCM_OUT2;
554         serial_omap_set_mctrl(&up->port, up->port.mctrl);
555         spin_unlock_irqrestore(&up->port.lock, flags);
556
557         up->msr_saved_flags = 0;
558         if (up->use_dma) {
559                 free_page((unsigned long)up->port.state->xmit.buf);
560                 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
561                         UART_XMIT_SIZE,
562                         (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
563                         0);
564                 init_timer(&(up->uart_dma.rx_timer));
565                 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
566                 up->uart_dma.rx_timer.data = up->port.line;
567                 /* Currently the buffer size is 4KB. Can increase it */
568                 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
569                         up->uart_dma.rx_buf_size,
570                         (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
571         }
572         /*
573          * Finally, enable interrupts. Note: Modem status interrupts
574          * are set via set_termios(), which will be occurring imminently
575          * anyway, so we don't enable them here.
576          */
577         up->ier = UART_IER_RLSI | UART_IER_RDI;
578         serial_out(up, UART_IER, up->ier);
579
580         /* Enable module level wake up */
581         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
582
583         pm_runtime_mark_last_busy(&up->pdev->dev);
584         pm_runtime_put_autosuspend(&up->pdev->dev);
585         up->port_activity = jiffies;
586         return 0;
587 }
588
589 static void serial_omap_shutdown(struct uart_port *port)
590 {
591         struct uart_omap_port *up = (struct uart_omap_port *)port;
592         unsigned long flags = 0;
593
594         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
595
596         pm_runtime_get_sync(&up->pdev->dev);
597         /*
598          * Disable interrupts from this port
599          */
600         up->ier = 0;
601         serial_out(up, UART_IER, 0);
602
603         spin_lock_irqsave(&up->port.lock, flags);
604         up->port.mctrl &= ~TIOCM_OUT2;
605         serial_omap_set_mctrl(&up->port, up->port.mctrl);
606         spin_unlock_irqrestore(&up->port.lock, flags);
607
608         /*
609          * Disable break condition and FIFOs
610          */
611         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
612         serial_omap_clear_fifos(up);
613
614         /*
615          * Read data port to reset things, and then free the irq
616          */
617         if (serial_in(up, UART_LSR) & UART_LSR_DR)
618                 (void) serial_in(up, UART_RX);
619         if (up->use_dma) {
620                 dma_free_coherent(up->port.dev,
621                         UART_XMIT_SIZE, up->port.state->xmit.buf,
622                         up->uart_dma.tx_buf_dma_phys);
623                 up->port.state->xmit.buf = NULL;
624                 serial_omap_stop_rx(port);
625                 dma_free_coherent(up->port.dev,
626                         up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
627                         up->uart_dma.rx_buf_dma_phys);
628                 up->uart_dma.rx_buf = NULL;
629         }
630
631         pm_runtime_put(&up->pdev->dev);
632         free_irq(up->port.irq, up);
633 }
634
635 static inline void
636 serial_omap_configure_xonxoff
637                 (struct uart_omap_port *up, struct ktermios *termios)
638 {
639         up->lcr = serial_in(up, UART_LCR);
640         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
641         up->efr = serial_in(up, UART_EFR);
642         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
643
644         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
645         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
646
647         /* clear SW control mode bits */
648         up->efr &= OMAP_UART_SW_CLR;
649
650         /*
651          * IXON Flag:
652          * Enable XON/XOFF flow control on output.
653          * Transmit XON1, XOFF1
654          */
655         if (termios->c_iflag & IXON)
656                 up->efr |= OMAP_UART_SW_TX;
657
658         /*
659          * IXOFF Flag:
660          * Enable XON/XOFF flow control on input.
661          * Receiver compares XON1, XOFF1.
662          */
663         if (termios->c_iflag & IXOFF)
664                 up->efr |= OMAP_UART_SW_RX;
665
666         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
667         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
668
669         up->mcr = serial_in(up, UART_MCR);
670
671         /*
672          * IXANY Flag:
673          * Enable any character to restart output.
674          * Operation resumes after receiving any
675          * character after recognition of the XOFF character
676          */
677         if (termios->c_iflag & IXANY)
678                 up->mcr |= UART_MCR_XONANY;
679
680         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
681         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
682         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
683         /* Enable special char function UARTi.EFR_REG[5] and
684          * load the new software flow control mode IXON or IXOFF
685          * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
686          */
687         serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
688         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
689
690         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
691         serial_out(up, UART_LCR, up->lcr);
692 }
693
694 static void serial_omap_uart_qos_work(struct work_struct *work)
695 {
696         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
697                                                 qos_work);
698
699         pm_qos_update_request(&up->pm_qos_request, up->latency);
700 }
701
702 static void
703 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
704                         struct ktermios *old)
705 {
706         struct uart_omap_port *up = (struct uart_omap_port *)port;
707         unsigned char cval = 0;
708         unsigned char efr = 0;
709         unsigned long flags = 0;
710         unsigned int baud, quot;
711
712         switch (termios->c_cflag & CSIZE) {
713         case CS5:
714                 cval = UART_LCR_WLEN5;
715                 break;
716         case CS6:
717                 cval = UART_LCR_WLEN6;
718                 break;
719         case CS7:
720                 cval = UART_LCR_WLEN7;
721                 break;
722         default:
723         case CS8:
724                 cval = UART_LCR_WLEN8;
725                 break;
726         }
727
728         if (termios->c_cflag & CSTOPB)
729                 cval |= UART_LCR_STOP;
730         if (termios->c_cflag & PARENB)
731                 cval |= UART_LCR_PARITY;
732         if (!(termios->c_cflag & PARODD))
733                 cval |= UART_LCR_EPAR;
734
735         /*
736          * Ask the core to calculate the divisor for us.
737          */
738
739         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
740         quot = serial_omap_get_divisor(port, baud);
741
742         /* calculate wakeup latency constraint */
743         up->calc_latency = (1000000 * up->port.fifosize) /
744                                 (1000 * baud / 8);
745         up->latency = up->calc_latency;
746         schedule_work(&up->qos_work);
747
748         up->dll = quot & 0xff;
749         up->dlh = quot >> 8;
750         up->mdr1 = UART_OMAP_MDR1_DISABLE;
751
752         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
753                         UART_FCR_ENABLE_FIFO;
754         if (up->use_dma)
755                 up->fcr |= UART_FCR_DMA_SELECT;
756
757         /*
758          * Ok, we're now changing the port state. Do it with
759          * interrupts disabled.
760          */
761         pm_runtime_get_sync(&up->pdev->dev);
762         spin_lock_irqsave(&up->port.lock, flags);
763
764         /*
765          * Update the per-port timeout.
766          */
767         uart_update_timeout(port, termios->c_cflag, baud);
768
769         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
770         if (termios->c_iflag & INPCK)
771                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
772         if (termios->c_iflag & (BRKINT | PARMRK))
773                 up->port.read_status_mask |= UART_LSR_BI;
774
775         /*
776          * Characters to ignore
777          */
778         up->port.ignore_status_mask = 0;
779         if (termios->c_iflag & IGNPAR)
780                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
781         if (termios->c_iflag & IGNBRK) {
782                 up->port.ignore_status_mask |= UART_LSR_BI;
783                 /*
784                  * If we're ignoring parity and break indicators,
785                  * ignore overruns too (for real raw support).
786                  */
787                 if (termios->c_iflag & IGNPAR)
788                         up->port.ignore_status_mask |= UART_LSR_OE;
789         }
790
791         /*
792          * ignore all characters if CREAD is not set
793          */
794         if ((termios->c_cflag & CREAD) == 0)
795                 up->port.ignore_status_mask |= UART_LSR_DR;
796
797         /*
798          * Modem status interrupts
799          */
800         up->ier &= ~UART_IER_MSI;
801         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
802                 up->ier |= UART_IER_MSI;
803         serial_out(up, UART_IER, up->ier);
804         serial_out(up, UART_LCR, cval);         /* reset DLAB */
805         up->lcr = cval;
806         up->scr = OMAP_UART_SCR_TX_EMPTY;
807
808         /* FIFOs and DMA Settings */
809
810         /* FCR can be changed only when the
811          * baud clock is not running
812          * DLL_REG and DLH_REG set to 0.
813          */
814         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
815         serial_out(up, UART_DLL, 0);
816         serial_out(up, UART_DLM, 0);
817         serial_out(up, UART_LCR, 0);
818
819         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
820
821         up->efr = serial_in(up, UART_EFR);
822         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
823
824         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
825         up->mcr = serial_in(up, UART_MCR);
826         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
827         /* FIFO ENABLE, DMA MODE */
828
829         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
830
831         if (up->use_dma) {
832                 serial_out(up, UART_TI752_TLR, 0);
833                 up->scr |= UART_FCR_TRIGGER_4;
834         } else {
835                 /* Set receive FIFO threshold to 1 byte */
836                 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
837                 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
838         }
839
840         serial_out(up, UART_FCR, up->fcr);
841         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
842
843         serial_out(up, UART_OMAP_SCR, up->scr);
844
845         serial_out(up, UART_EFR, up->efr);
846         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
847         serial_out(up, UART_MCR, up->mcr);
848
849         /* Protocol, Baud Rate, and Interrupt Settings */
850
851         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
852                 serial_omap_mdr1_errataset(up, up->mdr1);
853         else
854                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
855
856         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
857
858         up->efr = serial_in(up, UART_EFR);
859         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
860
861         serial_out(up, UART_LCR, 0);
862         serial_out(up, UART_IER, 0);
863         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
864
865         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
866         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
867
868         serial_out(up, UART_LCR, 0);
869         serial_out(up, UART_IER, up->ier);
870         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
871
872         serial_out(up, UART_EFR, up->efr);
873         serial_out(up, UART_LCR, cval);
874
875         if (baud > 230400 && baud != 3000000)
876                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
877         else
878                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
879
880         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
881                 serial_omap_mdr1_errataset(up, up->mdr1);
882         else
883                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
884
885         /* Hardware Flow Control Configuration */
886
887         if (termios->c_cflag & CRTSCTS) {
888                 efr |= (UART_EFR_CTS | UART_EFR_RTS);
889                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
890
891                 up->mcr = serial_in(up, UART_MCR);
892                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
893
894                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
895                 up->efr = serial_in(up, UART_EFR);
896                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
897
898                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
899                 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
900                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
901                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
902                 serial_out(up, UART_LCR, cval);
903         }
904
905         serial_omap_set_mctrl(&up->port, up->port.mctrl);
906         /* Software Flow Control Configuration */
907         serial_omap_configure_xonxoff(up, termios);
908
909         spin_unlock_irqrestore(&up->port.lock, flags);
910         pm_runtime_put(&up->pdev->dev);
911         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
912 }
913
914 static void
915 serial_omap_pm(struct uart_port *port, unsigned int state,
916                unsigned int oldstate)
917 {
918         struct uart_omap_port *up = (struct uart_omap_port *)port;
919         unsigned char efr;
920
921         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
922
923         pm_runtime_get_sync(&up->pdev->dev);
924         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
925         efr = serial_in(up, UART_EFR);
926         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
927         serial_out(up, UART_LCR, 0);
928
929         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
930         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
931         serial_out(up, UART_EFR, efr);
932         serial_out(up, UART_LCR, 0);
933
934         if (!device_may_wakeup(&up->pdev->dev)) {
935                 if (!state)
936                         pm_runtime_forbid(&up->pdev->dev);
937                 else
938                         pm_runtime_allow(&up->pdev->dev);
939         }
940
941         pm_runtime_put(&up->pdev->dev);
942 }
943
944 static void serial_omap_release_port(struct uart_port *port)
945 {
946         dev_dbg(port->dev, "serial_omap_release_port+\n");
947 }
948
949 static int serial_omap_request_port(struct uart_port *port)
950 {
951         dev_dbg(port->dev, "serial_omap_request_port+\n");
952         return 0;
953 }
954
955 static void serial_omap_config_port(struct uart_port *port, int flags)
956 {
957         struct uart_omap_port *up = (struct uart_omap_port *)port;
958
959         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
960                                                         up->port.line);
961         up->port.type = PORT_OMAP;
962 }
963
964 static int
965 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
966 {
967         /* we don't want the core code to modify any port params */
968         dev_dbg(port->dev, "serial_omap_verify_port+\n");
969         return -EINVAL;
970 }
971
972 static const char *
973 serial_omap_type(struct uart_port *port)
974 {
975         struct uart_omap_port *up = (struct uart_omap_port *)port;
976
977         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
978         return up->name;
979 }
980
981 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
982
983 static inline void wait_for_xmitr(struct uart_omap_port *up)
984 {
985         unsigned int status, tmout = 10000;
986
987         /* Wait up to 10ms for the character(s) to be sent. */
988         do {
989                 status = serial_in(up, UART_LSR);
990
991                 if (status & UART_LSR_BI)
992                         up->lsr_break_flag = UART_LSR_BI;
993
994                 if (--tmout == 0)
995                         break;
996                 udelay(1);
997         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
998
999         /* Wait up to 1s for flow control if necessary */
1000         if (up->port.flags & UPF_CONS_FLOW) {
1001                 tmout = 1000000;
1002                 for (tmout = 1000000; tmout; tmout--) {
1003                         unsigned int msr = serial_in(up, UART_MSR);
1004
1005                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1006                         if (msr & UART_MSR_CTS)
1007                                 break;
1008
1009                         udelay(1);
1010                 }
1011         }
1012 }
1013
1014 #ifdef CONFIG_CONSOLE_POLL
1015
1016 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1017 {
1018         struct uart_omap_port *up = (struct uart_omap_port *)port;
1019
1020         pm_runtime_get_sync(&up->pdev->dev);
1021         wait_for_xmitr(up);
1022         serial_out(up, UART_TX, ch);
1023         pm_runtime_put(&up->pdev->dev);
1024 }
1025
1026 static int serial_omap_poll_get_char(struct uart_port *port)
1027 {
1028         struct uart_omap_port *up = (struct uart_omap_port *)port;
1029         unsigned int status;
1030
1031         pm_runtime_get_sync(&up->pdev->dev);
1032         status = serial_in(up, UART_LSR);
1033         if (!(status & UART_LSR_DR))
1034                 return NO_POLL_CHAR;
1035
1036         status = serial_in(up, UART_RX);
1037         pm_runtime_put(&up->pdev->dev);
1038         return status;
1039 }
1040
1041 #endif /* CONFIG_CONSOLE_POLL */
1042
1043 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1044
1045 static struct uart_omap_port *serial_omap_console_ports[4];
1046
1047 static struct uart_driver serial_omap_reg;
1048
1049 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1050 {
1051         struct uart_omap_port *up = (struct uart_omap_port *)port;
1052
1053         wait_for_xmitr(up);
1054         serial_out(up, UART_TX, ch);
1055 }
1056
1057 static void
1058 serial_omap_console_write(struct console *co, const char *s,
1059                 unsigned int count)
1060 {
1061         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1062         unsigned long flags;
1063         unsigned int ier;
1064         int locked = 1;
1065
1066         pm_runtime_get_sync(&up->pdev->dev);
1067
1068         local_irq_save(flags);
1069         if (up->port.sysrq)
1070                 locked = 0;
1071         else if (oops_in_progress)
1072                 locked = spin_trylock(&up->port.lock);
1073         else
1074                 spin_lock(&up->port.lock);
1075
1076         /*
1077          * First save the IER then disable the interrupts
1078          */
1079         ier = serial_in(up, UART_IER);
1080         serial_out(up, UART_IER, 0);
1081
1082         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1083
1084         /*
1085          * Finally, wait for transmitter to become empty
1086          * and restore the IER
1087          */
1088         wait_for_xmitr(up);
1089         serial_out(up, UART_IER, ier);
1090         /*
1091          * The receive handling will happen properly because the
1092          * receive ready bit will still be set; it is not cleared
1093          * on read.  However, modem control will not, we must
1094          * call it if we have saved something in the saved flags
1095          * while processing with interrupts off.
1096          */
1097         if (up->msr_saved_flags)
1098                 check_modem_status(up);
1099
1100         pm_runtime_mark_last_busy(&up->pdev->dev);
1101         pm_runtime_put_autosuspend(&up->pdev->dev);
1102         if (locked)
1103                 spin_unlock(&up->port.lock);
1104         local_irq_restore(flags);
1105 }
1106
1107 static int __init
1108 serial_omap_console_setup(struct console *co, char *options)
1109 {
1110         struct uart_omap_port *up;
1111         int baud = 115200;
1112         int bits = 8;
1113         int parity = 'n';
1114         int flow = 'n';
1115
1116         if (serial_omap_console_ports[co->index] == NULL)
1117                 return -ENODEV;
1118         up = serial_omap_console_ports[co->index];
1119
1120         if (options)
1121                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1122
1123         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1124 }
1125
1126 static struct console serial_omap_console = {
1127         .name           = OMAP_SERIAL_NAME,
1128         .write          = serial_omap_console_write,
1129         .device         = uart_console_device,
1130         .setup          = serial_omap_console_setup,
1131         .flags          = CON_PRINTBUFFER,
1132         .index          = -1,
1133         .data           = &serial_omap_reg,
1134 };
1135
1136 static void serial_omap_add_console_port(struct uart_omap_port *up)
1137 {
1138         serial_omap_console_ports[up->port.line] = up;
1139 }
1140
1141 #define OMAP_CONSOLE    (&serial_omap_console)
1142
1143 #else
1144
1145 #define OMAP_CONSOLE    NULL
1146
1147 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1148 {}
1149
1150 #endif
1151
1152 static struct uart_ops serial_omap_pops = {
1153         .tx_empty       = serial_omap_tx_empty,
1154         .set_mctrl      = serial_omap_set_mctrl,
1155         .get_mctrl      = serial_omap_get_mctrl,
1156         .stop_tx        = serial_omap_stop_tx,
1157         .start_tx       = serial_omap_start_tx,
1158         .stop_rx        = serial_omap_stop_rx,
1159         .enable_ms      = serial_omap_enable_ms,
1160         .break_ctl      = serial_omap_break_ctl,
1161         .startup        = serial_omap_startup,
1162         .shutdown       = serial_omap_shutdown,
1163         .set_termios    = serial_omap_set_termios,
1164         .pm             = serial_omap_pm,
1165         .type           = serial_omap_type,
1166         .release_port   = serial_omap_release_port,
1167         .request_port   = serial_omap_request_port,
1168         .config_port    = serial_omap_config_port,
1169         .verify_port    = serial_omap_verify_port,
1170 #ifdef CONFIG_CONSOLE_POLL
1171         .poll_put_char  = serial_omap_poll_put_char,
1172         .poll_get_char  = serial_omap_poll_get_char,
1173 #endif
1174 };
1175
1176 static struct uart_driver serial_omap_reg = {
1177         .owner          = THIS_MODULE,
1178         .driver_name    = "OMAP-SERIAL",
1179         .dev_name       = OMAP_SERIAL_NAME,
1180         .nr             = OMAP_MAX_HSUART_PORTS,
1181         .cons           = OMAP_CONSOLE,
1182 };
1183
1184 #ifdef CONFIG_PM_SLEEP
1185 static int serial_omap_suspend(struct device *dev)
1186 {
1187         struct uart_omap_port *up = dev_get_drvdata(dev);
1188
1189         if (up) {
1190                 uart_suspend_port(&serial_omap_reg, &up->port);
1191                 flush_work_sync(&up->qos_work);
1192         }
1193
1194         return 0;
1195 }
1196
1197 static int serial_omap_resume(struct device *dev)
1198 {
1199         struct uart_omap_port *up = dev_get_drvdata(dev);
1200
1201         if (up)
1202                 uart_resume_port(&serial_omap_reg, &up->port);
1203         return 0;
1204 }
1205 #endif
1206
1207 static void serial_omap_rxdma_poll(unsigned long uart_no)
1208 {
1209         struct uart_omap_port *up = ui[uart_no];
1210         unsigned int curr_dma_pos, curr_transmitted_size;
1211         int ret = 0;
1212
1213         curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1214         if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1215                              (curr_dma_pos == 0)) {
1216                 if (jiffies_to_msecs(jiffies - up->port_activity) <
1217                                                 up->uart_dma.rx_timeout) {
1218                         mod_timer(&up->uart_dma.rx_timer, jiffies +
1219                                 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1220                 } else {
1221                         serial_omap_stop_rxdma(up);
1222                         up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1223                         serial_out(up, UART_IER, up->ier);
1224                 }
1225                 return;
1226         }
1227
1228         curr_transmitted_size = curr_dma_pos -
1229                                         up->uart_dma.prev_rx_dma_pos;
1230         up->port.icount.rx += curr_transmitted_size;
1231         tty_insert_flip_string(up->port.state->port.tty,
1232                         up->uart_dma.rx_buf +
1233                         (up->uart_dma.prev_rx_dma_pos -
1234                         up->uart_dma.rx_buf_dma_phys),
1235                         curr_transmitted_size);
1236         tty_flip_buffer_push(up->port.state->port.tty);
1237         up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1238         if (up->uart_dma.rx_buf_size +
1239                         up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1240                 ret = serial_omap_start_rxdma(up);
1241                 if (ret < 0) {
1242                         serial_omap_stop_rxdma(up);
1243                         up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1244                         serial_out(up, UART_IER, up->ier);
1245                 }
1246         } else  {
1247                 mod_timer(&up->uart_dma.rx_timer, jiffies +
1248                         usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1249         }
1250         up->port_activity = jiffies;
1251 }
1252
1253 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1254 {
1255         return;
1256 }
1257
1258 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1259 {
1260         int ret = 0;
1261
1262         if (up->uart_dma.rx_dma_channel == -1) {
1263                 pm_runtime_get_sync(&up->pdev->dev);
1264                 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1265                                 "UART Rx DMA",
1266                                 (void *)uart_rx_dma_callback, up,
1267                                 &(up->uart_dma.rx_dma_channel));
1268                 if (ret < 0)
1269                         return ret;
1270
1271                 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1272                                 OMAP_DMA_AMODE_CONSTANT,
1273                                 up->uart_dma.uart_base, 0, 0);
1274                 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1275                                 OMAP_DMA_AMODE_POST_INC,
1276                                 up->uart_dma.rx_buf_dma_phys, 0, 0);
1277                 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1278                                 OMAP_DMA_DATA_TYPE_S8,
1279                                 up->uart_dma.rx_buf_size, 1,
1280                                 OMAP_DMA_SYNC_ELEMENT,
1281                                 up->uart_dma.uart_dma_rx, 0);
1282         }
1283         up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1284         /* FIXME: Cache maintenance needed here? */
1285         omap_start_dma(up->uart_dma.rx_dma_channel);
1286         mod_timer(&up->uart_dma.rx_timer, jiffies +
1287                                 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1288         up->uart_dma.rx_dma_used = true;
1289         return ret;
1290 }
1291
1292 static void serial_omap_continue_tx(struct uart_omap_port *up)
1293 {
1294         struct circ_buf *xmit = &up->port.state->xmit;
1295         unsigned int start = up->uart_dma.tx_buf_dma_phys
1296                         + (xmit->tail & (UART_XMIT_SIZE - 1));
1297
1298         if (uart_circ_empty(xmit))
1299                 return;
1300
1301         up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1302         /*
1303          * It is a circular buffer. See if the buffer has wounded back.
1304          * If yes it will have to be transferred in two separate dma
1305          * transfers
1306          */
1307         if (start + up->uart_dma.tx_buf_size >=
1308                         up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1309                 up->uart_dma.tx_buf_size =
1310                         (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1311         omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1312                                 OMAP_DMA_AMODE_CONSTANT,
1313                                 up->uart_dma.uart_base, 0, 0);
1314         omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1315                                 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1316         omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1317                                 OMAP_DMA_DATA_TYPE_S8,
1318                                 up->uart_dma.tx_buf_size, 1,
1319                                 OMAP_DMA_SYNC_ELEMENT,
1320                                 up->uart_dma.uart_dma_tx, 0);
1321         /* FIXME: Cache maintenance needed here? */
1322         omap_start_dma(up->uart_dma.tx_dma_channel);
1323 }
1324
1325 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1326 {
1327         struct uart_omap_port *up = (struct uart_omap_port *)data;
1328         struct circ_buf *xmit = &up->port.state->xmit;
1329
1330         xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1331                         (UART_XMIT_SIZE - 1);
1332         up->port.icount.tx += up->uart_dma.tx_buf_size;
1333
1334         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1335                 uart_write_wakeup(&up->port);
1336
1337         if (uart_circ_empty(xmit)) {
1338                 spin_lock(&(up->uart_dma.tx_lock));
1339                 serial_omap_stop_tx(&up->port);
1340                 up->uart_dma.tx_dma_used = false;
1341                 spin_unlock(&(up->uart_dma.tx_lock));
1342         } else {
1343                 omap_stop_dma(up->uart_dma.tx_dma_channel);
1344                 serial_omap_continue_tx(up);
1345         }
1346         up->port_activity = jiffies;
1347         return;
1348 }
1349
1350 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1351 {
1352         struct omap_uart_port_info *omap_up_info;
1353
1354         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1355         if (!omap_up_info)
1356                 return NULL; /* out of memory */
1357
1358         of_property_read_u32(dev->of_node, "clock-frequency",
1359                                          &omap_up_info->uartclk);
1360         return omap_up_info;
1361 }
1362
1363 static int serial_omap_probe(struct platform_device *pdev)
1364 {
1365         struct uart_omap_port   *up;
1366         struct resource         *mem, *irq, *dma_tx, *dma_rx;
1367         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1368         int ret = -ENOSPC;
1369
1370         if (pdev->dev.of_node)
1371                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1372
1373         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1374         if (!mem) {
1375                 dev_err(&pdev->dev, "no mem resource?\n");
1376                 return -ENODEV;
1377         }
1378
1379         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1380         if (!irq) {
1381                 dev_err(&pdev->dev, "no irq resource?\n");
1382                 return -ENODEV;
1383         }
1384
1385         if (!request_mem_region(mem->start, resource_size(mem),
1386                                 pdev->dev.driver->name)) {
1387                 dev_err(&pdev->dev, "memory region already claimed\n");
1388                 return -EBUSY;
1389         }
1390
1391         dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1392         if (!dma_rx) {
1393                 ret = -EINVAL;
1394                 goto err;
1395         }
1396
1397         dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1398         if (!dma_tx) {
1399                 ret = -EINVAL;
1400                 goto err;
1401         }
1402
1403         up = kzalloc(sizeof(*up), GFP_KERNEL);
1404         if (up == NULL) {
1405                 ret = -ENOMEM;
1406                 goto do_release_region;
1407         }
1408         up->pdev = pdev;
1409         up->port.dev = &pdev->dev;
1410         up->port.type = PORT_OMAP;
1411         up->port.iotype = UPIO_MEM;
1412         up->port.irq = irq->start;
1413
1414         up->port.regshift = 2;
1415         up->port.fifosize = 64;
1416         up->port.ops = &serial_omap_pops;
1417
1418         if (pdev->dev.of_node)
1419                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1420         else
1421                 up->port.line = pdev->id;
1422
1423         if (up->port.line < 0) {
1424                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1425                                                                 up->port.line);
1426                 ret = -ENODEV;
1427                 goto err;
1428         }
1429
1430         sprintf(up->name, "OMAP UART%d", up->port.line);
1431         up->port.mapbase = mem->start;
1432         up->port.membase = ioremap(mem->start, resource_size(mem));
1433         if (!up->port.membase) {
1434                 dev_err(&pdev->dev, "can't ioremap UART\n");
1435                 ret = -ENOMEM;
1436                 goto err;
1437         }
1438
1439         up->port.flags = omap_up_info->flags;
1440         up->port.uartclk = omap_up_info->uartclk;
1441         if (!up->port.uartclk) {
1442                 up->port.uartclk = DEFAULT_CLK_SPEED;
1443                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1444                                                 "%d\n", DEFAULT_CLK_SPEED);
1445         }
1446         up->uart_dma.uart_base = mem->start;
1447         up->errata = omap_up_info->errata;
1448
1449         if (omap_up_info->dma_enabled) {
1450                 up->uart_dma.uart_dma_tx = dma_tx->start;
1451                 up->uart_dma.uart_dma_rx = dma_rx->start;
1452                 up->use_dma = 1;
1453                 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1454                 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1455                 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1456                 spin_lock_init(&(up->uart_dma.tx_lock));
1457                 spin_lock_init(&(up->uart_dma.rx_lock));
1458                 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1459                 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1460         }
1461
1462         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1463         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1464         pm_qos_add_request(&up->pm_qos_request,
1465                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1466         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1467         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1468
1469         pm_runtime_use_autosuspend(&pdev->dev);
1470         pm_runtime_set_autosuspend_delay(&pdev->dev,
1471                         omap_up_info->autosuspend_timeout);
1472
1473         pm_runtime_irq_safe(&pdev->dev);
1474         pm_runtime_enable(&pdev->dev);
1475         pm_runtime_get_sync(&pdev->dev);
1476
1477         ui[up->port.line] = up;
1478         serial_omap_add_console_port(up);
1479
1480         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1481         if (ret != 0)
1482                 goto do_release_region;
1483
1484         pm_runtime_put(&pdev->dev);
1485         platform_set_drvdata(pdev, up);
1486         return 0;
1487 err:
1488         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1489                                 pdev->id, __func__, ret);
1490 do_release_region:
1491         release_mem_region(mem->start, resource_size(mem));
1492         return ret;
1493 }
1494
1495 static int serial_omap_remove(struct platform_device *dev)
1496 {
1497         struct uart_omap_port *up = platform_get_drvdata(dev);
1498
1499         if (up) {
1500                 pm_runtime_disable(&up->pdev->dev);
1501                 uart_remove_one_port(&serial_omap_reg, &up->port);
1502                 pm_qos_remove_request(&up->pm_qos_request);
1503
1504                 kfree(up);
1505         }
1506
1507         platform_set_drvdata(dev, NULL);
1508         return 0;
1509 }
1510
1511 /*
1512  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1513  * The access to uart register after MDR1 Access
1514  * causes UART to corrupt data.
1515  *
1516  * Need a delay =
1517  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1518  * give 10 times as much
1519  */
1520 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1521 {
1522         u8 timeout = 255;
1523
1524         serial_out(up, UART_OMAP_MDR1, mdr1);
1525         udelay(2);
1526         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1527                         UART_FCR_CLEAR_RCVR);
1528         /*
1529          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1530          * TX_FIFO_E bit is 1.
1531          */
1532         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1533                                 (UART_LSR_THRE | UART_LSR_DR))) {
1534                 timeout--;
1535                 if (!timeout) {
1536                         /* Should *never* happen. we warn and carry on */
1537                         dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1538                                                 serial_in(up, UART_LSR));
1539                         break;
1540                 }
1541                 udelay(1);
1542         }
1543 }
1544
1545 #ifdef CONFIG_PM_RUNTIME
1546 static void serial_omap_restore_context(struct uart_omap_port *up)
1547 {
1548         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1549                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1550         else
1551                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1552
1553         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1554         serial_out(up, UART_EFR, UART_EFR_ECB);
1555         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1556         serial_out(up, UART_IER, 0x0);
1557         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1558         serial_out(up, UART_DLL, up->dll);
1559         serial_out(up, UART_DLM, up->dlh);
1560         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1561         serial_out(up, UART_IER, up->ier);
1562         serial_out(up, UART_FCR, up->fcr);
1563         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1564         serial_out(up, UART_MCR, up->mcr);
1565         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1566         serial_out(up, UART_OMAP_SCR, up->scr);
1567         serial_out(up, UART_EFR, up->efr);
1568         serial_out(up, UART_LCR, up->lcr);
1569         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1570                 serial_omap_mdr1_errataset(up, up->mdr1);
1571         else
1572                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1573 }
1574
1575 static int serial_omap_runtime_suspend(struct device *dev)
1576 {
1577         struct uart_omap_port *up = dev_get_drvdata(dev);
1578         struct omap_uart_port_info *pdata = dev->platform_data;
1579
1580         if (!up)
1581                 return -EINVAL;
1582
1583         if (!pdata || !pdata->enable_wakeup)
1584                 return 0;
1585
1586         if (pdata->get_context_loss_count)
1587                 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1588
1589         if (device_may_wakeup(dev)) {
1590                 if (!up->wakeups_enabled) {
1591                         pdata->enable_wakeup(up->pdev, true);
1592                         up->wakeups_enabled = true;
1593                 }
1594         } else {
1595                 if (up->wakeups_enabled) {
1596                         pdata->enable_wakeup(up->pdev, false);
1597                         up->wakeups_enabled = false;
1598                 }
1599         }
1600
1601         /* Errata i291 */
1602         if (up->use_dma && pdata->set_forceidle &&
1603                         (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1604                 pdata->set_forceidle(up->pdev);
1605
1606         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1607         schedule_work(&up->qos_work);
1608
1609         return 0;
1610 }
1611
1612 static int serial_omap_runtime_resume(struct device *dev)
1613 {
1614         struct uart_omap_port *up = dev_get_drvdata(dev);
1615         struct omap_uart_port_info *pdata = dev->platform_data;
1616
1617         if (up) {
1618                 if (pdata->get_context_loss_count) {
1619                         u32 loss_cnt = pdata->get_context_loss_count(dev);
1620
1621                         if (up->context_loss_cnt != loss_cnt)
1622                                 serial_omap_restore_context(up);
1623                 }
1624
1625                 /* Errata i291 */
1626                 if (up->use_dma && pdata->set_noidle &&
1627                                 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1628                         pdata->set_noidle(up->pdev);
1629
1630                 up->latency = up->calc_latency;
1631                 schedule_work(&up->qos_work);
1632         }
1633
1634         return 0;
1635 }
1636 #endif
1637
1638 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1639         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1640         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1641                                 serial_omap_runtime_resume, NULL)
1642 };
1643
1644 #if defined(CONFIG_OF)
1645 static const struct of_device_id omap_serial_of_match[] = {
1646         { .compatible = "ti,omap2-uart" },
1647         { .compatible = "ti,omap3-uart" },
1648         { .compatible = "ti,omap4-uart" },
1649         {},
1650 };
1651 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1652 #endif
1653
1654 static struct platform_driver serial_omap_driver = {
1655         .probe          = serial_omap_probe,
1656         .remove         = serial_omap_remove,
1657         .driver         = {
1658                 .name   = DRIVER_NAME,
1659                 .pm     = &serial_omap_dev_pm_ops,
1660                 .of_match_table = of_match_ptr(omap_serial_of_match),
1661         },
1662 };
1663
1664 static int __init serial_omap_init(void)
1665 {
1666         int ret;
1667
1668         ret = uart_register_driver(&serial_omap_reg);
1669         if (ret != 0)
1670                 return ret;
1671         ret = platform_driver_register(&serial_omap_driver);
1672         if (ret != 0)
1673                 uart_unregister_driver(&serial_omap_reg);
1674         return ret;
1675 }
1676
1677 static void __exit serial_omap_exit(void)
1678 {
1679         platform_driver_unregister(&serial_omap_driver);
1680         uart_unregister_driver(&serial_omap_reg);
1681 }
1682
1683 module_init(serial_omap_init);
1684 module_exit(serial_omap_exit);
1685
1686 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1687 MODULE_LICENSE("GPL");
1688 MODULE_AUTHOR("Texas Instruments Inc");