Linux 3.8-rc2
[~shefty/rdma-dev.git] / drivers / usb / gadget / amd5536udc.c
1 /*
2  * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3  *
4  * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5  * Author: Thomas Dahlmann
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  */
12
13 /*
14  * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15  * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16  * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
17  *
18  * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19  * be used as host port) and UOC bits PAD_EN and APU are set (should be done
20  * by BIOS init).
21  *
22  * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23  * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24  * can be used with gadget ether.
25  */
26
27 /* debug control */
28 /* #define UDC_VERBOSE */
29
30 /* Driver strings */
31 #define UDC_MOD_DESCRIPTION             "AMD 5536 UDC - USB Device Controller"
32 #define UDC_DRIVER_VERSION_STRING       "01.00.0206"
33
34 /* system */
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/ioport.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/errno.h>
43 #include <linux/init.h>
44 #include <linux/timer.h>
45 #include <linux/list.h>
46 #include <linux/interrupt.h>
47 #include <linux/ioctl.h>
48 #include <linux/fs.h>
49 #include <linux/dmapool.h>
50 #include <linux/moduleparam.h>
51 #include <linux/device.h>
52 #include <linux/io.h>
53 #include <linux/irq.h>
54 #include <linux/prefetch.h>
55
56 #include <asm/byteorder.h>
57 #include <asm/unaligned.h>
58
59 /* gadget stack */
60 #include <linux/usb/ch9.h>
61 #include <linux/usb/gadget.h>
62
63 /* udc specific */
64 #include "amd5536udc.h"
65
66
67 static void udc_tasklet_disconnect(unsigned long);
68 static void empty_req_queue(struct udc_ep *);
69 static int udc_probe(struct udc *dev);
70 static void udc_basic_init(struct udc *dev);
71 static void udc_setup_endpoints(struct udc *dev);
72 static void udc_soft_reset(struct udc *dev);
73 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
74 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
75 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
76 static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
77                                 unsigned long buf_len, gfp_t gfp_flags);
78 static int udc_remote_wakeup(struct udc *dev);
79 static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
80 static void udc_pci_remove(struct pci_dev *pdev);
81
82 /* description */
83 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
84 static const char name[] = "amd5536udc";
85
86 /* structure to hold endpoint function pointers */
87 static const struct usb_ep_ops udc_ep_ops;
88
89 /* received setup data */
90 static union udc_setup_data setup_data;
91
92 /* pointer to device object */
93 static struct udc *udc;
94
95 /* irq spin lock for soft reset */
96 static DEFINE_SPINLOCK(udc_irq_spinlock);
97 /* stall spin lock */
98 static DEFINE_SPINLOCK(udc_stall_spinlock);
99
100 /*
101 * slave mode: pending bytes in rx fifo after nyet,
102 * used if EPIN irq came but no req was available
103 */
104 static unsigned int udc_rxfifo_pending;
105
106 /* count soft resets after suspend to avoid loop */
107 static int soft_reset_occured;
108 static int soft_reset_after_usbreset_occured;
109
110 /* timer */
111 static struct timer_list udc_timer;
112 static int stop_timer;
113
114 /* set_rde -- Is used to control enabling of RX DMA. Problem is
115  * that UDC has only one bit (RDE) to enable/disable RX DMA for
116  * all OUT endpoints. So we have to handle race conditions like
117  * when OUT data reaches the fifo but no request was queued yet.
118  * This cannot be solved by letting the RX DMA disabled until a
119  * request gets queued because there may be other OUT packets
120  * in the FIFO (important for not blocking control traffic).
121  * The value of set_rde controls the correspondig timer.
122  *
123  * set_rde -1 == not used, means it is alloed to be set to 0 or 1
124  * set_rde  0 == do not touch RDE, do no start the RDE timer
125  * set_rde  1 == timer function will look whether FIFO has data
126  * set_rde  2 == set by timer function to enable RX DMA on next call
127  */
128 static int set_rde = -1;
129
130 static DECLARE_COMPLETION(on_exit);
131 static struct timer_list udc_pollstall_timer;
132 static int stop_pollstall_timer;
133 static DECLARE_COMPLETION(on_pollstall_exit);
134
135 /* tasklet for usb disconnect */
136 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
137                 (unsigned long) &udc);
138
139
140 /* endpoint names used for print */
141 static const char ep0_string[] = "ep0in";
142 static const char *const ep_string[] = {
143         ep0_string,
144         "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
145         "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
146         "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
147         "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
148         "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
149         "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
150         "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
151 };
152
153 /* DMA usage flag */
154 static bool use_dma = 1;
155 /* packet per buffer dma */
156 static bool use_dma_ppb = 1;
157 /* with per descr. update */
158 static bool use_dma_ppb_du;
159 /* buffer fill mode */
160 static int use_dma_bufferfill_mode;
161 /* full speed only mode */
162 static bool use_fullspeed;
163 /* tx buffer size for high speed */
164 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
165
166 /* module parameters */
167 module_param(use_dma, bool, S_IRUGO);
168 MODULE_PARM_DESC(use_dma, "true for DMA");
169 module_param(use_dma_ppb, bool, S_IRUGO);
170 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
171 module_param(use_dma_ppb_du, bool, S_IRUGO);
172 MODULE_PARM_DESC(use_dma_ppb_du,
173         "true for DMA in packet per buffer mode with descriptor update");
174 module_param(use_fullspeed, bool, S_IRUGO);
175 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
176
177 /*---------------------------------------------------------------------------*/
178 /* Prints UDC device registers and endpoint irq registers */
179 static void print_regs(struct udc *dev)
180 {
181         DBG(dev, "------- Device registers -------\n");
182         DBG(dev, "dev config     = %08x\n", readl(&dev->regs->cfg));
183         DBG(dev, "dev control    = %08x\n", readl(&dev->regs->ctl));
184         DBG(dev, "dev status     = %08x\n", readl(&dev->regs->sts));
185         DBG(dev, "\n");
186         DBG(dev, "dev int's      = %08x\n", readl(&dev->regs->irqsts));
187         DBG(dev, "dev intmask    = %08x\n", readl(&dev->regs->irqmsk));
188         DBG(dev, "\n");
189         DBG(dev, "dev ep int's   = %08x\n", readl(&dev->regs->ep_irqsts));
190         DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
191         DBG(dev, "\n");
192         DBG(dev, "USE DMA        = %d\n", use_dma);
193         if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
194                 DBG(dev, "DMA mode       = PPBNDU (packet per buffer "
195                         "WITHOUT desc. update)\n");
196                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
197         } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
198                 DBG(dev, "DMA mode       = PPBDU (packet per buffer "
199                         "WITH desc. update)\n");
200                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
201         }
202         if (use_dma && use_dma_bufferfill_mode) {
203                 DBG(dev, "DMA mode       = BF (buffer fill mode)\n");
204                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
205         }
206         if (!use_dma)
207                 dev_info(&dev->pdev->dev, "FIFO mode\n");
208         DBG(dev, "-------------------------------------------------------\n");
209 }
210
211 /* Masks unused interrupts */
212 static int udc_mask_unused_interrupts(struct udc *dev)
213 {
214         u32 tmp;
215
216         /* mask all dev interrupts */
217         tmp =   AMD_BIT(UDC_DEVINT_SVC) |
218                 AMD_BIT(UDC_DEVINT_ENUM) |
219                 AMD_BIT(UDC_DEVINT_US) |
220                 AMD_BIT(UDC_DEVINT_UR) |
221                 AMD_BIT(UDC_DEVINT_ES) |
222                 AMD_BIT(UDC_DEVINT_SI) |
223                 AMD_BIT(UDC_DEVINT_SOF)|
224                 AMD_BIT(UDC_DEVINT_SC);
225         writel(tmp, &dev->regs->irqmsk);
226
227         /* mask all ep interrupts */
228         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
229
230         return 0;
231 }
232
233 /* Enables endpoint 0 interrupts */
234 static int udc_enable_ep0_interrupts(struct udc *dev)
235 {
236         u32 tmp;
237
238         DBG(dev, "udc_enable_ep0_interrupts()\n");
239
240         /* read irq mask */
241         tmp = readl(&dev->regs->ep_irqmsk);
242         /* enable ep0 irq's */
243         tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
244                 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
245         writel(tmp, &dev->regs->ep_irqmsk);
246
247         return 0;
248 }
249
250 /* Enables device interrupts for SET_INTF and SET_CONFIG */
251 static int udc_enable_dev_setup_interrupts(struct udc *dev)
252 {
253         u32 tmp;
254
255         DBG(dev, "enable device interrupts for setup data\n");
256
257         /* read irq mask */
258         tmp = readl(&dev->regs->irqmsk);
259
260         /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
261         tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
262                 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
263                 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
264                 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
265                 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
266         writel(tmp, &dev->regs->irqmsk);
267
268         return 0;
269 }
270
271 /* Calculates fifo start of endpoint based on preceding endpoints */
272 static int udc_set_txfifo_addr(struct udc_ep *ep)
273 {
274         struct udc      *dev;
275         u32 tmp;
276         int i;
277
278         if (!ep || !(ep->in))
279                 return -EINVAL;
280
281         dev = ep->dev;
282         ep->txfifo = dev->txfifo;
283
284         /* traverse ep's */
285         for (i = 0; i < ep->num; i++) {
286                 if (dev->ep[i].regs) {
287                         /* read fifo size */
288                         tmp = readl(&dev->ep[i].regs->bufin_framenum);
289                         tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
290                         ep->txfifo += tmp;
291                 }
292         }
293         return 0;
294 }
295
296 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
297 static u32 cnak_pending;
298
299 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
300 {
301         if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
302                 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
303                 cnak_pending |= 1 << (num);
304                 ep->naking = 1;
305         } else
306                 cnak_pending = cnak_pending & (~(1 << (num)));
307 }
308
309
310 /* Enables endpoint, is called by gadget driver */
311 static int
312 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
313 {
314         struct udc_ep           *ep;
315         struct udc              *dev;
316         u32                     tmp;
317         unsigned long           iflags;
318         u8 udc_csr_epix;
319         unsigned                maxpacket;
320
321         if (!usbep
322                         || usbep->name == ep0_string
323                         || !desc
324                         || desc->bDescriptorType != USB_DT_ENDPOINT)
325                 return -EINVAL;
326
327         ep = container_of(usbep, struct udc_ep, ep);
328         dev = ep->dev;
329
330         DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
331
332         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
333                 return -ESHUTDOWN;
334
335         spin_lock_irqsave(&dev->lock, iflags);
336         ep->ep.desc = desc;
337
338         ep->halted = 0;
339
340         /* set traffic type */
341         tmp = readl(&dev->ep[ep->num].regs->ctl);
342         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
343         writel(tmp, &dev->ep[ep->num].regs->ctl);
344
345         /* set max packet size */
346         maxpacket = usb_endpoint_maxp(desc);
347         tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
348         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
349         ep->ep.maxpacket = maxpacket;
350         writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
351
352         /* IN ep */
353         if (ep->in) {
354
355                 /* ep ix in UDC CSR register space */
356                 udc_csr_epix = ep->num;
357
358                 /* set buffer size (tx fifo entries) */
359                 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
360                 /* double buffering: fifo size = 2 x max packet size */
361                 tmp = AMD_ADDBITS(
362                                 tmp,
363                                 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
364                                           / UDC_DWORD_BYTES,
365                                 UDC_EPIN_BUFF_SIZE);
366                 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
367
368                 /* calc. tx fifo base addr */
369                 udc_set_txfifo_addr(ep);
370
371                 /* flush fifo */
372                 tmp = readl(&ep->regs->ctl);
373                 tmp |= AMD_BIT(UDC_EPCTL_F);
374                 writel(tmp, &ep->regs->ctl);
375
376         /* OUT ep */
377         } else {
378                 /* ep ix in UDC CSR register space */
379                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
380
381                 /* set max packet size UDC CSR  */
382                 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
383                 tmp = AMD_ADDBITS(tmp, maxpacket,
384                                         UDC_CSR_NE_MAX_PKT);
385                 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
386
387                 if (use_dma && !ep->in) {
388                         /* alloc and init BNA dummy request */
389                         ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
390                         ep->bna_occurred = 0;
391                 }
392
393                 if (ep->num != UDC_EP0OUT_IX)
394                         dev->data_ep_enabled = 1;
395         }
396
397         /* set ep values */
398         tmp = readl(&dev->csr->ne[udc_csr_epix]);
399         /* max packet */
400         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
401         /* ep number */
402         tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
403         /* ep direction */
404         tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
405         /* ep type */
406         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
407         /* ep config */
408         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
409         /* ep interface */
410         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
411         /* ep alt */
412         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
413         /* write reg */
414         writel(tmp, &dev->csr->ne[udc_csr_epix]);
415
416         /* enable ep irq */
417         tmp = readl(&dev->regs->ep_irqmsk);
418         tmp &= AMD_UNMASK_BIT(ep->num);
419         writel(tmp, &dev->regs->ep_irqmsk);
420
421         /*
422          * clear NAK by writing CNAK
423          * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
424          */
425         if (!use_dma || ep->in) {
426                 tmp = readl(&ep->regs->ctl);
427                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
428                 writel(tmp, &ep->regs->ctl);
429                 ep->naking = 0;
430                 UDC_QUEUE_CNAK(ep, ep->num);
431         }
432         tmp = desc->bEndpointAddress;
433         DBG(dev, "%s enabled\n", usbep->name);
434
435         spin_unlock_irqrestore(&dev->lock, iflags);
436         return 0;
437 }
438
439 /* Resets endpoint */
440 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
441 {
442         u32             tmp;
443
444         VDBG(ep->dev, "ep-%d reset\n", ep->num);
445         ep->ep.desc = NULL;
446         ep->ep.ops = &udc_ep_ops;
447         INIT_LIST_HEAD(&ep->queue);
448
449         ep->ep.maxpacket = (u16) ~0;
450         /* set NAK */
451         tmp = readl(&ep->regs->ctl);
452         tmp |= AMD_BIT(UDC_EPCTL_SNAK);
453         writel(tmp, &ep->regs->ctl);
454         ep->naking = 1;
455
456         /* disable interrupt */
457         tmp = readl(&regs->ep_irqmsk);
458         tmp |= AMD_BIT(ep->num);
459         writel(tmp, &regs->ep_irqmsk);
460
461         if (ep->in) {
462                 /* unset P and IN bit of potential former DMA */
463                 tmp = readl(&ep->regs->ctl);
464                 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
465                 writel(tmp, &ep->regs->ctl);
466
467                 tmp = readl(&ep->regs->sts);
468                 tmp |= AMD_BIT(UDC_EPSTS_IN);
469                 writel(tmp, &ep->regs->sts);
470
471                 /* flush the fifo */
472                 tmp = readl(&ep->regs->ctl);
473                 tmp |= AMD_BIT(UDC_EPCTL_F);
474                 writel(tmp, &ep->regs->ctl);
475
476         }
477         /* reset desc pointer */
478         writel(0, &ep->regs->desptr);
479 }
480
481 /* Disables endpoint, is called by gadget driver */
482 static int udc_ep_disable(struct usb_ep *usbep)
483 {
484         struct udc_ep   *ep = NULL;
485         unsigned long   iflags;
486
487         if (!usbep)
488                 return -EINVAL;
489
490         ep = container_of(usbep, struct udc_ep, ep);
491         if (usbep->name == ep0_string || !ep->ep.desc)
492                 return -EINVAL;
493
494         DBG(ep->dev, "Disable ep-%d\n", ep->num);
495
496         spin_lock_irqsave(&ep->dev->lock, iflags);
497         udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
498         empty_req_queue(ep);
499         ep_init(ep->dev->regs, ep);
500         spin_unlock_irqrestore(&ep->dev->lock, iflags);
501
502         return 0;
503 }
504
505 /* Allocates request packet, called by gadget driver */
506 static struct usb_request *
507 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
508 {
509         struct udc_request      *req;
510         struct udc_data_dma     *dma_desc;
511         struct udc_ep   *ep;
512
513         if (!usbep)
514                 return NULL;
515
516         ep = container_of(usbep, struct udc_ep, ep);
517
518         VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
519         req = kzalloc(sizeof(struct udc_request), gfp);
520         if (!req)
521                 return NULL;
522
523         req->req.dma = DMA_DONT_USE;
524         INIT_LIST_HEAD(&req->queue);
525
526         if (ep->dma) {
527                 /* ep0 in requests are allocated from data pool here */
528                 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
529                                                 &req->td_phys);
530                 if (!dma_desc) {
531                         kfree(req);
532                         return NULL;
533                 }
534
535                 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
536                                 "td_phys = %lx\n",
537                                 req, dma_desc,
538                                 (unsigned long)req->td_phys);
539                 /* prevent from using desc. - set HOST BUSY */
540                 dma_desc->status = AMD_ADDBITS(dma_desc->status,
541                                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
542                                                 UDC_DMA_STP_STS_BS);
543                 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
544                 req->td_data = dma_desc;
545                 req->td_data_last = NULL;
546                 req->chain_len = 1;
547         }
548
549         return &req->req;
550 }
551
552 /* Frees request packet, called by gadget driver */
553 static void
554 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
555 {
556         struct udc_ep   *ep;
557         struct udc_request      *req;
558
559         if (!usbep || !usbreq)
560                 return;
561
562         ep = container_of(usbep, struct udc_ep, ep);
563         req = container_of(usbreq, struct udc_request, req);
564         VDBG(ep->dev, "free_req req=%p\n", req);
565         BUG_ON(!list_empty(&req->queue));
566         if (req->td_data) {
567                 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
568
569                 /* free dma chain if created */
570                 if (req->chain_len > 1)
571                         udc_free_dma_chain(ep->dev, req);
572
573                 pci_pool_free(ep->dev->data_requests, req->td_data,
574                                                         req->td_phys);
575         }
576         kfree(req);
577 }
578
579 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
580 static void udc_init_bna_dummy(struct udc_request *req)
581 {
582         if (req) {
583                 /* set last bit */
584                 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
585                 /* set next pointer to itself */
586                 req->td_data->next = req->td_phys;
587                 /* set HOST BUSY */
588                 req->td_data->status
589                         = AMD_ADDBITS(req->td_data->status,
590                                         UDC_DMA_STP_STS_BS_DMA_DONE,
591                                         UDC_DMA_STP_STS_BS);
592 #ifdef UDC_VERBOSE
593                 pr_debug("bna desc = %p, sts = %08x\n",
594                         req->td_data, req->td_data->status);
595 #endif
596         }
597 }
598
599 /* Allocate BNA dummy descriptor */
600 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
601 {
602         struct udc_request *req = NULL;
603         struct usb_request *_req = NULL;
604
605         /* alloc the dummy request */
606         _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
607         if (_req) {
608                 req = container_of(_req, struct udc_request, req);
609                 ep->bna_dummy_req = req;
610                 udc_init_bna_dummy(req);
611         }
612         return req;
613 }
614
615 /* Write data to TX fifo for IN packets */
616 static void
617 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
618 {
619         u8                      *req_buf;
620         u32                     *buf;
621         int                     i, j;
622         unsigned                bytes = 0;
623         unsigned                remaining = 0;
624
625         if (!req || !ep)
626                 return;
627
628         req_buf = req->buf + req->actual;
629         prefetch(req_buf);
630         remaining = req->length - req->actual;
631
632         buf = (u32 *) req_buf;
633
634         bytes = ep->ep.maxpacket;
635         if (bytes > remaining)
636                 bytes = remaining;
637
638         /* dwords first */
639         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
640                 writel(*(buf + i), ep->txfifo);
641
642         /* remaining bytes must be written by byte access */
643         for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
644                 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
645                                                         ep->txfifo);
646         }
647
648         /* dummy write confirm */
649         writel(0, &ep->regs->confirm);
650 }
651
652 /* Read dwords from RX fifo for OUT transfers */
653 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
654 {
655         int i;
656
657         VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
658
659         for (i = 0; i < dwords; i++)
660                 *(buf + i) = readl(dev->rxfifo);
661         return 0;
662 }
663
664 /* Read bytes from RX fifo for OUT transfers */
665 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
666 {
667         int i, j;
668         u32 tmp;
669
670         VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
671
672         /* dwords first */
673         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
674                 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
675
676         /* remaining bytes must be read by byte access */
677         if (bytes % UDC_DWORD_BYTES) {
678                 tmp = readl(dev->rxfifo);
679                 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
680                         *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
681                         tmp = tmp >> UDC_BITS_PER_BYTE;
682                 }
683         }
684
685         return 0;
686 }
687
688 /* Read data from RX fifo for OUT transfers */
689 static int
690 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
691 {
692         u8 *buf;
693         unsigned buf_space;
694         unsigned bytes = 0;
695         unsigned finished = 0;
696
697         /* received number bytes */
698         bytes = readl(&ep->regs->sts);
699         bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
700
701         buf_space = req->req.length - req->req.actual;
702         buf = req->req.buf + req->req.actual;
703         if (bytes > buf_space) {
704                 if ((buf_space % ep->ep.maxpacket) != 0) {
705                         DBG(ep->dev,
706                                 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
707                                 ep->ep.name, bytes, buf_space);
708                         req->req.status = -EOVERFLOW;
709                 }
710                 bytes = buf_space;
711         }
712         req->req.actual += bytes;
713
714         /* last packet ? */
715         if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
716                 || ((req->req.actual == req->req.length) && !req->req.zero))
717                 finished = 1;
718
719         /* read rx fifo bytes */
720         VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
721         udc_rxfifo_read_bytes(ep->dev, buf, bytes);
722
723         return finished;
724 }
725
726 /* create/re-init a DMA descriptor or a DMA descriptor chain */
727 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
728 {
729         int     retval = 0;
730         u32     tmp;
731
732         VDBG(ep->dev, "prep_dma\n");
733         VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
734                         ep->num, req->td_data);
735
736         /* set buffer pointer */
737         req->td_data->bufptr = req->req.dma;
738
739         /* set last bit */
740         req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
741
742         /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
743         if (use_dma_ppb) {
744
745                 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
746                 if (retval != 0) {
747                         if (retval == -ENOMEM)
748                                 DBG(ep->dev, "Out of DMA memory\n");
749                         return retval;
750                 }
751                 if (ep->in) {
752                         if (req->req.length == ep->ep.maxpacket) {
753                                 /* write tx bytes */
754                                 req->td_data->status =
755                                         AMD_ADDBITS(req->td_data->status,
756                                                 ep->ep.maxpacket,
757                                                 UDC_DMA_IN_STS_TXBYTES);
758
759                         }
760                 }
761
762         }
763
764         if (ep->in) {
765                 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
766                                 "maxpacket=%d ep%d\n",
767                                 use_dma_ppb, req->req.length,
768                                 ep->ep.maxpacket, ep->num);
769                 /*
770                  * if bytes < max packet then tx bytes must
771                  * be written in packet per buffer mode
772                  */
773                 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
774                                 || ep->num == UDC_EP0OUT_IX
775                                 || ep->num == UDC_EP0IN_IX) {
776                         /* write tx bytes */
777                         req->td_data->status =
778                                 AMD_ADDBITS(req->td_data->status,
779                                                 req->req.length,
780                                                 UDC_DMA_IN_STS_TXBYTES);
781                         /* reset frame num */
782                         req->td_data->status =
783                                 AMD_ADDBITS(req->td_data->status,
784                                                 0,
785                                                 UDC_DMA_IN_STS_FRAMENUM);
786                 }
787                 /* set HOST BUSY */
788                 req->td_data->status =
789                         AMD_ADDBITS(req->td_data->status,
790                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
791                                 UDC_DMA_STP_STS_BS);
792         } else {
793                 VDBG(ep->dev, "OUT set host ready\n");
794                 /* set HOST READY */
795                 req->td_data->status =
796                         AMD_ADDBITS(req->td_data->status,
797                                 UDC_DMA_STP_STS_BS_HOST_READY,
798                                 UDC_DMA_STP_STS_BS);
799
800
801                         /* clear NAK by writing CNAK */
802                         if (ep->naking) {
803                                 tmp = readl(&ep->regs->ctl);
804                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
805                                 writel(tmp, &ep->regs->ctl);
806                                 ep->naking = 0;
807                                 UDC_QUEUE_CNAK(ep, ep->num);
808                         }
809
810         }
811
812         return retval;
813 }
814
815 /* Completes request packet ... caller MUST hold lock */
816 static void
817 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
818 __releases(ep->dev->lock)
819 __acquires(ep->dev->lock)
820 {
821         struct udc              *dev;
822         unsigned                halted;
823
824         VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
825
826         dev = ep->dev;
827         /* unmap DMA */
828         if (ep->dma)
829                 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
830
831         halted = ep->halted;
832         ep->halted = 1;
833
834         /* set new status if pending */
835         if (req->req.status == -EINPROGRESS)
836                 req->req.status = sts;
837
838         /* remove from ep queue */
839         list_del_init(&req->queue);
840
841         VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
842                 &req->req, req->req.length, ep->ep.name, sts);
843
844         spin_unlock(&dev->lock);
845         req->req.complete(&ep->ep, &req->req);
846         spin_lock(&dev->lock);
847         ep->halted = halted;
848 }
849
850 /* frees pci pool descriptors of a DMA chain */
851 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
852 {
853
854         int ret_val = 0;
855         struct udc_data_dma     *td;
856         struct udc_data_dma     *td_last = NULL;
857         unsigned int i;
858
859         DBG(dev, "free chain req = %p\n", req);
860
861         /* do not free first desc., will be done by free for request */
862         td_last = req->td_data;
863         td = phys_to_virt(td_last->next);
864
865         for (i = 1; i < req->chain_len; i++) {
866
867                 pci_pool_free(dev->data_requests, td,
868                                 (dma_addr_t) td_last->next);
869                 td_last = td;
870                 td = phys_to_virt(td_last->next);
871         }
872
873         return ret_val;
874 }
875
876 /* Iterates to the end of a DMA chain and returns last descriptor */
877 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
878 {
879         struct udc_data_dma     *td;
880
881         td = req->td_data;
882         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
883                 td = phys_to_virt(td->next);
884
885         return td;
886
887 }
888
889 /* Iterates to the end of a DMA chain and counts bytes received */
890 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
891 {
892         struct udc_data_dma     *td;
893         u32 count;
894
895         td = req->td_data;
896         /* received number bytes */
897         count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
898
899         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
900                 td = phys_to_virt(td->next);
901                 /* received number bytes */
902                 if (td) {
903                         count += AMD_GETBITS(td->status,
904                                 UDC_DMA_OUT_STS_RXBYTES);
905                 }
906         }
907
908         return count;
909
910 }
911
912 /* Creates or re-inits a DMA chain */
913 static int udc_create_dma_chain(
914         struct udc_ep *ep,
915         struct udc_request *req,
916         unsigned long buf_len, gfp_t gfp_flags
917 )
918 {
919         unsigned long bytes = req->req.length;
920         unsigned int i;
921         dma_addr_t dma_addr;
922         struct udc_data_dma     *td = NULL;
923         struct udc_data_dma     *last = NULL;
924         unsigned long txbytes;
925         unsigned create_new_chain = 0;
926         unsigned len;
927
928         VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
929                         bytes, buf_len);
930         dma_addr = DMA_DONT_USE;
931
932         /* unset L bit in first desc for OUT */
933         if (!ep->in)
934                 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
935
936         /* alloc only new desc's if not already available */
937         len = req->req.length / ep->ep.maxpacket;
938         if (req->req.length % ep->ep.maxpacket)
939                 len++;
940
941         if (len > req->chain_len) {
942                 /* shorter chain already allocated before */
943                 if (req->chain_len > 1)
944                         udc_free_dma_chain(ep->dev, req);
945                 req->chain_len = len;
946                 create_new_chain = 1;
947         }
948
949         td = req->td_data;
950         /* gen. required number of descriptors and buffers */
951         for (i = buf_len; i < bytes; i += buf_len) {
952                 /* create or determine next desc. */
953                 if (create_new_chain) {
954
955                         td = pci_pool_alloc(ep->dev->data_requests,
956                                         gfp_flags, &dma_addr);
957                         if (!td)
958                                 return -ENOMEM;
959
960                         td->status = 0;
961                 } else if (i == buf_len) {
962                         /* first td */
963                         td = (struct udc_data_dma *) phys_to_virt(
964                                                 req->td_data->next);
965                         td->status = 0;
966                 } else {
967                         td = (struct udc_data_dma *) phys_to_virt(last->next);
968                         td->status = 0;
969                 }
970
971
972                 if (td)
973                         td->bufptr = req->req.dma + i; /* assign buffer */
974                 else
975                         break;
976
977                 /* short packet ? */
978                 if ((bytes - i) >= buf_len) {
979                         txbytes = buf_len;
980                 } else {
981                         /* short packet */
982                         txbytes = bytes - i;
983                 }
984
985                 /* link td and assign tx bytes */
986                 if (i == buf_len) {
987                         if (create_new_chain)
988                                 req->td_data->next = dma_addr;
989                         /*
990                         else
991                                 req->td_data->next = virt_to_phys(td);
992                         */
993                         /* write tx bytes */
994                         if (ep->in) {
995                                 /* first desc */
996                                 req->td_data->status =
997                                         AMD_ADDBITS(req->td_data->status,
998                                                         ep->ep.maxpacket,
999                                                         UDC_DMA_IN_STS_TXBYTES);
1000                                 /* second desc */
1001                                 td->status = AMD_ADDBITS(td->status,
1002                                                         txbytes,
1003                                                         UDC_DMA_IN_STS_TXBYTES);
1004                         }
1005                 } else {
1006                         if (create_new_chain)
1007                                 last->next = dma_addr;
1008                         /*
1009                         else
1010                                 last->next = virt_to_phys(td);
1011                         */
1012                         if (ep->in) {
1013                                 /* write tx bytes */
1014                                 td->status = AMD_ADDBITS(td->status,
1015                                                         txbytes,
1016                                                         UDC_DMA_IN_STS_TXBYTES);
1017                         }
1018                 }
1019                 last = td;
1020         }
1021         /* set last bit */
1022         if (td) {
1023                 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1024                 /* last desc. points to itself */
1025                 req->td_data_last = td;
1026         }
1027
1028         return 0;
1029 }
1030
1031 /* Enabling RX DMA */
1032 static void udc_set_rde(struct udc *dev)
1033 {
1034         u32 tmp;
1035
1036         VDBG(dev, "udc_set_rde()\n");
1037         /* stop RDE timer */
1038         if (timer_pending(&udc_timer)) {
1039                 set_rde = 0;
1040                 mod_timer(&udc_timer, jiffies - 1);
1041         }
1042         /* set RDE */
1043         tmp = readl(&dev->regs->ctl);
1044         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1045         writel(tmp, &dev->regs->ctl);
1046 }
1047
1048 /* Queues a request packet, called by gadget driver */
1049 static int
1050 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1051 {
1052         int                     retval = 0;
1053         u8                      open_rxfifo = 0;
1054         unsigned long           iflags;
1055         struct udc_ep           *ep;
1056         struct udc_request      *req;
1057         struct udc              *dev;
1058         u32                     tmp;
1059
1060         /* check the inputs */
1061         req = container_of(usbreq, struct udc_request, req);
1062
1063         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1064                         || !list_empty(&req->queue))
1065                 return -EINVAL;
1066
1067         ep = container_of(usbep, struct udc_ep, ep);
1068         if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1069                 return -EINVAL;
1070
1071         VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1072         dev = ep->dev;
1073
1074         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1075                 return -ESHUTDOWN;
1076
1077         /* map dma (usually done before) */
1078         if (ep->dma) {
1079                 VDBG(dev, "DMA map req %p\n", req);
1080                 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1081                 if (retval)
1082                         return retval;
1083         }
1084
1085         VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1086                         usbep->name, usbreq, usbreq->length,
1087                         req->td_data, usbreq->buf);
1088
1089         spin_lock_irqsave(&dev->lock, iflags);
1090         usbreq->actual = 0;
1091         usbreq->status = -EINPROGRESS;
1092         req->dma_done = 0;
1093
1094         /* on empty queue just do first transfer */
1095         if (list_empty(&ep->queue)) {
1096                 /* zlp */
1097                 if (usbreq->length == 0) {
1098                         /* IN zlp's are handled by hardware */
1099                         complete_req(ep, req, 0);
1100                         VDBG(dev, "%s: zlp\n", ep->ep.name);
1101                         /*
1102                          * if set_config or set_intf is waiting for ack by zlp
1103                          * then set CSR_DONE
1104                          */
1105                         if (dev->set_cfg_not_acked) {
1106                                 tmp = readl(&dev->regs->ctl);
1107                                 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1108                                 writel(tmp, &dev->regs->ctl);
1109                                 dev->set_cfg_not_acked = 0;
1110                         }
1111                         /* setup command is ACK'ed now by zlp */
1112                         if (dev->waiting_zlp_ack_ep0in) {
1113                                 /* clear NAK by writing CNAK in EP0_IN */
1114                                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1115                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1116                                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1117                                 dev->ep[UDC_EP0IN_IX].naking = 0;
1118                                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1119                                                         UDC_EP0IN_IX);
1120                                 dev->waiting_zlp_ack_ep0in = 0;
1121                         }
1122                         goto finished;
1123                 }
1124                 if (ep->dma) {
1125                         retval = prep_dma(ep, req, gfp);
1126                         if (retval != 0)
1127                                 goto finished;
1128                         /* write desc pointer to enable DMA */
1129                         if (ep->in) {
1130                                 /* set HOST READY */
1131                                 req->td_data->status =
1132                                         AMD_ADDBITS(req->td_data->status,
1133                                                 UDC_DMA_IN_STS_BS_HOST_READY,
1134                                                 UDC_DMA_IN_STS_BS);
1135                         }
1136
1137                         /* disabled rx dma while descriptor update */
1138                         if (!ep->in) {
1139                                 /* stop RDE timer */
1140                                 if (timer_pending(&udc_timer)) {
1141                                         set_rde = 0;
1142                                         mod_timer(&udc_timer, jiffies - 1);
1143                                 }
1144                                 /* clear RDE */
1145                                 tmp = readl(&dev->regs->ctl);
1146                                 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1147                                 writel(tmp, &dev->regs->ctl);
1148                                 open_rxfifo = 1;
1149
1150                                 /*
1151                                  * if BNA occurred then let BNA dummy desc.
1152                                  * point to current desc.
1153                                  */
1154                                 if (ep->bna_occurred) {
1155                                         VDBG(dev, "copy to BNA dummy desc.\n");
1156                                         memcpy(ep->bna_dummy_req->td_data,
1157                                                 req->td_data,
1158                                                 sizeof(struct udc_data_dma));
1159                                 }
1160                         }
1161                         /* write desc pointer */
1162                         writel(req->td_phys, &ep->regs->desptr);
1163
1164                         /* clear NAK by writing CNAK */
1165                         if (ep->naking) {
1166                                 tmp = readl(&ep->regs->ctl);
1167                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1168                                 writel(tmp, &ep->regs->ctl);
1169                                 ep->naking = 0;
1170                                 UDC_QUEUE_CNAK(ep, ep->num);
1171                         }
1172
1173                         if (ep->in) {
1174                                 /* enable ep irq */
1175                                 tmp = readl(&dev->regs->ep_irqmsk);
1176                                 tmp &= AMD_UNMASK_BIT(ep->num);
1177                                 writel(tmp, &dev->regs->ep_irqmsk);
1178                         }
1179                 } else if (ep->in) {
1180                                 /* enable ep irq */
1181                                 tmp = readl(&dev->regs->ep_irqmsk);
1182                                 tmp &= AMD_UNMASK_BIT(ep->num);
1183                                 writel(tmp, &dev->regs->ep_irqmsk);
1184                         }
1185
1186         } else if (ep->dma) {
1187
1188                 /*
1189                  * prep_dma not used for OUT ep's, this is not possible
1190                  * for PPB modes, because of chain creation reasons
1191                  */
1192                 if (ep->in) {
1193                         retval = prep_dma(ep, req, gfp);
1194                         if (retval != 0)
1195                                 goto finished;
1196                 }
1197         }
1198         VDBG(dev, "list_add\n");
1199         /* add request to ep queue */
1200         if (req) {
1201
1202                 list_add_tail(&req->queue, &ep->queue);
1203
1204                 /* open rxfifo if out data queued */
1205                 if (open_rxfifo) {
1206                         /* enable DMA */
1207                         req->dma_going = 1;
1208                         udc_set_rde(dev);
1209                         if (ep->num != UDC_EP0OUT_IX)
1210                                 dev->data_ep_queued = 1;
1211                 }
1212                 /* stop OUT naking */
1213                 if (!ep->in) {
1214                         if (!use_dma && udc_rxfifo_pending) {
1215                                 DBG(dev, "udc_queue(): pending bytes in "
1216                                         "rxfifo after nyet\n");
1217                                 /*
1218                                  * read pending bytes afer nyet:
1219                                  * referring to isr
1220                                  */
1221                                 if (udc_rxfifo_read(ep, req)) {
1222                                         /* finish */
1223                                         complete_req(ep, req, 0);
1224                                 }
1225                                 udc_rxfifo_pending = 0;
1226
1227                         }
1228                 }
1229         }
1230
1231 finished:
1232         spin_unlock_irqrestore(&dev->lock, iflags);
1233         return retval;
1234 }
1235
1236 /* Empty request queue of an endpoint; caller holds spinlock */
1237 static void empty_req_queue(struct udc_ep *ep)
1238 {
1239         struct udc_request      *req;
1240
1241         ep->halted = 1;
1242         while (!list_empty(&ep->queue)) {
1243                 req = list_entry(ep->queue.next,
1244                         struct udc_request,
1245                         queue);
1246                 complete_req(ep, req, -ESHUTDOWN);
1247         }
1248 }
1249
1250 /* Dequeues a request packet, called by gadget driver */
1251 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1252 {
1253         struct udc_ep           *ep;
1254         struct udc_request      *req;
1255         unsigned                halted;
1256         unsigned long           iflags;
1257
1258         ep = container_of(usbep, struct udc_ep, ep);
1259         if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
1260                                 && ep->num != UDC_EP0OUT_IX)))
1261                 return -EINVAL;
1262
1263         req = container_of(usbreq, struct udc_request, req);
1264
1265         spin_lock_irqsave(&ep->dev->lock, iflags);
1266         halted = ep->halted;
1267         ep->halted = 1;
1268         /* request in processing or next one */
1269         if (ep->queue.next == &req->queue) {
1270                 if (ep->dma && req->dma_going) {
1271                         if (ep->in)
1272                                 ep->cancel_transfer = 1;
1273                         else {
1274                                 u32 tmp;
1275                                 u32 dma_sts;
1276                                 /* stop potential receive DMA */
1277                                 tmp = readl(&udc->regs->ctl);
1278                                 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1279                                                         &udc->regs->ctl);
1280                                 /*
1281                                  * Cancel transfer later in ISR
1282                                  * if descriptor was touched.
1283                                  */
1284                                 dma_sts = AMD_GETBITS(req->td_data->status,
1285                                                         UDC_DMA_OUT_STS_BS);
1286                                 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1287                                         ep->cancel_transfer = 1;
1288                                 else {
1289                                         udc_init_bna_dummy(ep->req);
1290                                         writel(ep->bna_dummy_req->td_phys,
1291                                                 &ep->regs->desptr);
1292                                 }
1293                                 writel(tmp, &udc->regs->ctl);
1294                         }
1295                 }
1296         }
1297         complete_req(ep, req, -ECONNRESET);
1298         ep->halted = halted;
1299
1300         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1301         return 0;
1302 }
1303
1304 /* Halt or clear halt of endpoint */
1305 static int
1306 udc_set_halt(struct usb_ep *usbep, int halt)
1307 {
1308         struct udc_ep   *ep;
1309         u32 tmp;
1310         unsigned long iflags;
1311         int retval = 0;
1312
1313         if (!usbep)
1314                 return -EINVAL;
1315
1316         pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1317
1318         ep = container_of(usbep, struct udc_ep, ep);
1319         if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1320                 return -EINVAL;
1321         if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1322                 return -ESHUTDOWN;
1323
1324         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1325         /* halt or clear halt */
1326         if (halt) {
1327                 if (ep->num == 0)
1328                         ep->dev->stall_ep0in = 1;
1329                 else {
1330                         /*
1331                          * set STALL
1332                          * rxfifo empty not taken into acount
1333                          */
1334                         tmp = readl(&ep->regs->ctl);
1335                         tmp |= AMD_BIT(UDC_EPCTL_S);
1336                         writel(tmp, &ep->regs->ctl);
1337                         ep->halted = 1;
1338
1339                         /* setup poll timer */
1340                         if (!timer_pending(&udc_pollstall_timer)) {
1341                                 udc_pollstall_timer.expires = jiffies +
1342                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1343                                         / (1000 * 1000);
1344                                 if (!stop_pollstall_timer) {
1345                                         DBG(ep->dev, "start polltimer\n");
1346                                         add_timer(&udc_pollstall_timer);
1347                                 }
1348                         }
1349                 }
1350         } else {
1351                 /* ep is halted by set_halt() before */
1352                 if (ep->halted) {
1353                         tmp = readl(&ep->regs->ctl);
1354                         /* clear stall bit */
1355                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1356                         /* clear NAK by writing CNAK */
1357                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1358                         writel(tmp, &ep->regs->ctl);
1359                         ep->halted = 0;
1360                         UDC_QUEUE_CNAK(ep, ep->num);
1361                 }
1362         }
1363         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1364         return retval;
1365 }
1366
1367 /* gadget interface */
1368 static const struct usb_ep_ops udc_ep_ops = {
1369         .enable         = udc_ep_enable,
1370         .disable        = udc_ep_disable,
1371
1372         .alloc_request  = udc_alloc_request,
1373         .free_request   = udc_free_request,
1374
1375         .queue          = udc_queue,
1376         .dequeue        = udc_dequeue,
1377
1378         .set_halt       = udc_set_halt,
1379         /* fifo ops not implemented */
1380 };
1381
1382 /*-------------------------------------------------------------------------*/
1383
1384 /* Get frame counter (not implemented) */
1385 static int udc_get_frame(struct usb_gadget *gadget)
1386 {
1387         return -EOPNOTSUPP;
1388 }
1389
1390 /* Remote wakeup gadget interface */
1391 static int udc_wakeup(struct usb_gadget *gadget)
1392 {
1393         struct udc              *dev;
1394
1395         if (!gadget)
1396                 return -EINVAL;
1397         dev = container_of(gadget, struct udc, gadget);
1398         udc_remote_wakeup(dev);
1399
1400         return 0;
1401 }
1402
1403 static int amd5536_start(struct usb_gadget_driver *driver,
1404                 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *));
1405 static int amd5536_stop(struct usb_gadget_driver *driver);
1406 /* gadget operations */
1407 static const struct usb_gadget_ops udc_ops = {
1408         .wakeup         = udc_wakeup,
1409         .get_frame      = udc_get_frame,
1410         .start          = amd5536_start,
1411         .stop           = amd5536_stop,
1412 };
1413
1414 /* Setups endpoint parameters, adds endpoints to linked list */
1415 static void make_ep_lists(struct udc *dev)
1416 {
1417         /* make gadget ep lists */
1418         INIT_LIST_HEAD(&dev->gadget.ep_list);
1419         list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1420                                                 &dev->gadget.ep_list);
1421         list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1422                                                 &dev->gadget.ep_list);
1423         list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1424                                                 &dev->gadget.ep_list);
1425
1426         /* fifo config */
1427         dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1428         if (dev->gadget.speed == USB_SPEED_FULL)
1429                 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1430         else if (dev->gadget.speed == USB_SPEED_HIGH)
1431                 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1432         dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1433 }
1434
1435 /* init registers at driver load time */
1436 static int startup_registers(struct udc *dev)
1437 {
1438         u32 tmp;
1439
1440         /* init controller by soft reset */
1441         udc_soft_reset(dev);
1442
1443         /* mask not needed interrupts */
1444         udc_mask_unused_interrupts(dev);
1445
1446         /* put into initial config */
1447         udc_basic_init(dev);
1448         /* link up all endpoints */
1449         udc_setup_endpoints(dev);
1450
1451         /* program speed */
1452         tmp = readl(&dev->regs->cfg);
1453         if (use_fullspeed)
1454                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1455         else
1456                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1457         writel(tmp, &dev->regs->cfg);
1458
1459         return 0;
1460 }
1461
1462 /* Inits UDC context */
1463 static void udc_basic_init(struct udc *dev)
1464 {
1465         u32     tmp;
1466
1467         DBG(dev, "udc_basic_init()\n");
1468
1469         dev->gadget.speed = USB_SPEED_UNKNOWN;
1470
1471         /* stop RDE timer */
1472         if (timer_pending(&udc_timer)) {
1473                 set_rde = 0;
1474                 mod_timer(&udc_timer, jiffies - 1);
1475         }
1476         /* stop poll stall timer */
1477         if (timer_pending(&udc_pollstall_timer))
1478                 mod_timer(&udc_pollstall_timer, jiffies - 1);
1479         /* disable DMA */
1480         tmp = readl(&dev->regs->ctl);
1481         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1482         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1483         writel(tmp, &dev->regs->ctl);
1484
1485         /* enable dynamic CSR programming */
1486         tmp = readl(&dev->regs->cfg);
1487         tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1488         /* set self powered */
1489         tmp |= AMD_BIT(UDC_DEVCFG_SP);
1490         /* set remote wakeupable */
1491         tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1492         writel(tmp, &dev->regs->cfg);
1493
1494         make_ep_lists(dev);
1495
1496         dev->data_ep_enabled = 0;
1497         dev->data_ep_queued = 0;
1498 }
1499
1500 /* Sets initial endpoint parameters */
1501 static void udc_setup_endpoints(struct udc *dev)
1502 {
1503         struct udc_ep   *ep;
1504         u32     tmp;
1505         u32     reg;
1506
1507         DBG(dev, "udc_setup_endpoints()\n");
1508
1509         /* read enum speed */
1510         tmp = readl(&dev->regs->sts);
1511         tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1512         if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1513                 dev->gadget.speed = USB_SPEED_HIGH;
1514         else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1515                 dev->gadget.speed = USB_SPEED_FULL;
1516
1517         /* set basic ep parameters */
1518         for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1519                 ep = &dev->ep[tmp];
1520                 ep->dev = dev;
1521                 ep->ep.name = ep_string[tmp];
1522                 ep->num = tmp;
1523                 /* txfifo size is calculated at enable time */
1524                 ep->txfifo = dev->txfifo;
1525
1526                 /* fifo size */
1527                 if (tmp < UDC_EPIN_NUM) {
1528                         ep->fifo_depth = UDC_TXFIFO_SIZE;
1529                         ep->in = 1;
1530                 } else {
1531                         ep->fifo_depth = UDC_RXFIFO_SIZE;
1532                         ep->in = 0;
1533
1534                 }
1535                 ep->regs = &dev->ep_regs[tmp];
1536                 /*
1537                  * ep will be reset only if ep was not enabled before to avoid
1538                  * disabling ep interrupts when ENUM interrupt occurs but ep is
1539                  * not enabled by gadget driver
1540                  */
1541                 if (!ep->ep.desc)
1542                         ep_init(dev->regs, ep);
1543
1544                 if (use_dma) {
1545                         /*
1546                          * ep->dma is not really used, just to indicate that
1547                          * DMA is active: remove this
1548                          * dma regs = dev control regs
1549                          */
1550                         ep->dma = &dev->regs->ctl;
1551
1552                         /* nak OUT endpoints until enable - not for ep0 */
1553                         if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1554                                                 && tmp > UDC_EPIN_NUM) {
1555                                 /* set NAK */
1556                                 reg = readl(&dev->ep[tmp].regs->ctl);
1557                                 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1558                                 writel(reg, &dev->ep[tmp].regs->ctl);
1559                                 dev->ep[tmp].naking = 1;
1560
1561                         }
1562                 }
1563         }
1564         /* EP0 max packet */
1565         if (dev->gadget.speed == USB_SPEED_FULL) {
1566                 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
1567                 dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
1568                                                 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1569         } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1570                 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
1571                 dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
1572         }
1573
1574         /*
1575          * with suspend bug workaround, ep0 params for gadget driver
1576          * are set at gadget driver bind() call
1577          */
1578         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1579         dev->ep[UDC_EP0IN_IX].halted = 0;
1580         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1581
1582         /* init cfg/alt/int */
1583         dev->cur_config = 0;
1584         dev->cur_intf = 0;
1585         dev->cur_alt = 0;
1586 }
1587
1588 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1589 static void usb_connect(struct udc *dev)
1590 {
1591
1592         dev_info(&dev->pdev->dev, "USB Connect\n");
1593
1594         dev->connected = 1;
1595
1596         /* put into initial config */
1597         udc_basic_init(dev);
1598
1599         /* enable device setup interrupts */
1600         udc_enable_dev_setup_interrupts(dev);
1601 }
1602
1603 /*
1604  * Calls gadget with disconnect event and resets the UDC and makes
1605  * initial bringup to be ready for ep0 events
1606  */
1607 static void usb_disconnect(struct udc *dev)
1608 {
1609
1610         dev_info(&dev->pdev->dev, "USB Disconnect\n");
1611
1612         dev->connected = 0;
1613
1614         /* mask interrupts */
1615         udc_mask_unused_interrupts(dev);
1616
1617         /* REVISIT there doesn't seem to be a point to having this
1618          * talk to a tasklet ... do it directly, we already hold
1619          * the spinlock needed to process the disconnect.
1620          */
1621
1622         tasklet_schedule(&disconnect_tasklet);
1623 }
1624
1625 /* Tasklet for disconnect to be outside of interrupt context */
1626 static void udc_tasklet_disconnect(unsigned long par)
1627 {
1628         struct udc *dev = (struct udc *)(*((struct udc **) par));
1629         u32 tmp;
1630
1631         DBG(dev, "Tasklet disconnect\n");
1632         spin_lock_irq(&dev->lock);
1633
1634         if (dev->driver) {
1635                 spin_unlock(&dev->lock);
1636                 dev->driver->disconnect(&dev->gadget);
1637                 spin_lock(&dev->lock);
1638
1639                 /* empty queues */
1640                 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1641                         empty_req_queue(&dev->ep[tmp]);
1642
1643         }
1644
1645         /* disable ep0 */
1646         ep_init(dev->regs,
1647                         &dev->ep[UDC_EP0IN_IX]);
1648
1649
1650         if (!soft_reset_occured) {
1651                 /* init controller by soft reset */
1652                 udc_soft_reset(dev);
1653                 soft_reset_occured++;
1654         }
1655
1656         /* re-enable dev interrupts */
1657         udc_enable_dev_setup_interrupts(dev);
1658         /* back to full speed ? */
1659         if (use_fullspeed) {
1660                 tmp = readl(&dev->regs->cfg);
1661                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1662                 writel(tmp, &dev->regs->cfg);
1663         }
1664
1665         spin_unlock_irq(&dev->lock);
1666 }
1667
1668 /* Reset the UDC core */
1669 static void udc_soft_reset(struct udc *dev)
1670 {
1671         unsigned long   flags;
1672
1673         DBG(dev, "Soft reset\n");
1674         /*
1675          * reset possible waiting interrupts, because int.
1676          * status is lost after soft reset,
1677          * ep int. status reset
1678          */
1679         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1680         /* device int. status reset */
1681         writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1682
1683         spin_lock_irqsave(&udc_irq_spinlock, flags);
1684         writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1685         readl(&dev->regs->cfg);
1686         spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1687
1688 }
1689
1690 /* RDE timer callback to set RDE bit */
1691 static void udc_timer_function(unsigned long v)
1692 {
1693         u32 tmp;
1694
1695         spin_lock_irq(&udc_irq_spinlock);
1696
1697         if (set_rde > 0) {
1698                 /*
1699                  * open the fifo if fifo was filled on last timer call
1700                  * conditionally
1701                  */
1702                 if (set_rde > 1) {
1703                         /* set RDE to receive setup data */
1704                         tmp = readl(&udc->regs->ctl);
1705                         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1706                         writel(tmp, &udc->regs->ctl);
1707                         set_rde = -1;
1708                 } else if (readl(&udc->regs->sts)
1709                                 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1710                         /*
1711                          * if fifo empty setup polling, do not just
1712                          * open the fifo
1713                          */
1714                         udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1715                         if (!stop_timer)
1716                                 add_timer(&udc_timer);
1717                 } else {
1718                         /*
1719                          * fifo contains data now, setup timer for opening
1720                          * the fifo when timer expires to be able to receive
1721                          * setup packets, when data packets gets queued by
1722                          * gadget layer then timer will forced to expire with
1723                          * set_rde=0 (RDE is set in udc_queue())
1724                          */
1725                         set_rde++;
1726                         /* debug: lhadmot_timer_start = 221070 */
1727                         udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1728                         if (!stop_timer)
1729                                 add_timer(&udc_timer);
1730                 }
1731
1732         } else
1733                 set_rde = -1; /* RDE was set by udc_queue() */
1734         spin_unlock_irq(&udc_irq_spinlock);
1735         if (stop_timer)
1736                 complete(&on_exit);
1737
1738 }
1739
1740 /* Handle halt state, used in stall poll timer */
1741 static void udc_handle_halt_state(struct udc_ep *ep)
1742 {
1743         u32 tmp;
1744         /* set stall as long not halted */
1745         if (ep->halted == 1) {
1746                 tmp = readl(&ep->regs->ctl);
1747                 /* STALL cleared ? */
1748                 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1749                         /*
1750                          * FIXME: MSC spec requires that stall remains
1751                          * even on receivng of CLEAR_FEATURE HALT. So
1752                          * we would set STALL again here to be compliant.
1753                          * But with current mass storage drivers this does
1754                          * not work (would produce endless host retries).
1755                          * So we clear halt on CLEAR_FEATURE.
1756                          *
1757                         DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1758                         tmp |= AMD_BIT(UDC_EPCTL_S);
1759                         writel(tmp, &ep->regs->ctl);*/
1760
1761                         /* clear NAK by writing CNAK */
1762                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1763                         writel(tmp, &ep->regs->ctl);
1764                         ep->halted = 0;
1765                         UDC_QUEUE_CNAK(ep, ep->num);
1766                 }
1767         }
1768 }
1769
1770 /* Stall timer callback to poll S bit and set it again after */
1771 static void udc_pollstall_timer_function(unsigned long v)
1772 {
1773         struct udc_ep *ep;
1774         int halted = 0;
1775
1776         spin_lock_irq(&udc_stall_spinlock);
1777         /*
1778          * only one IN and OUT endpoints are handled
1779          * IN poll stall
1780          */
1781         ep = &udc->ep[UDC_EPIN_IX];
1782         udc_handle_halt_state(ep);
1783         if (ep->halted)
1784                 halted = 1;
1785         /* OUT poll stall */
1786         ep = &udc->ep[UDC_EPOUT_IX];
1787         udc_handle_halt_state(ep);
1788         if (ep->halted)
1789                 halted = 1;
1790
1791         /* setup timer again when still halted */
1792         if (!stop_pollstall_timer && halted) {
1793                 udc_pollstall_timer.expires = jiffies +
1794                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1795                                         / (1000 * 1000);
1796                 add_timer(&udc_pollstall_timer);
1797         }
1798         spin_unlock_irq(&udc_stall_spinlock);
1799
1800         if (stop_pollstall_timer)
1801                 complete(&on_pollstall_exit);
1802 }
1803
1804 /* Inits endpoint 0 so that SETUP packets are processed */
1805 static void activate_control_endpoints(struct udc *dev)
1806 {
1807         u32 tmp;
1808
1809         DBG(dev, "activate_control_endpoints\n");
1810
1811         /* flush fifo */
1812         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1813         tmp |= AMD_BIT(UDC_EPCTL_F);
1814         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1815
1816         /* set ep0 directions */
1817         dev->ep[UDC_EP0IN_IX].in = 1;
1818         dev->ep[UDC_EP0OUT_IX].in = 0;
1819
1820         /* set buffer size (tx fifo entries) of EP0_IN */
1821         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1822         if (dev->gadget.speed == USB_SPEED_FULL)
1823                 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1824                                         UDC_EPIN_BUFF_SIZE);
1825         else if (dev->gadget.speed == USB_SPEED_HIGH)
1826                 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1827                                         UDC_EPIN_BUFF_SIZE);
1828         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1829
1830         /* set max packet size of EP0_IN */
1831         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1832         if (dev->gadget.speed == USB_SPEED_FULL)
1833                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1834                                         UDC_EP_MAX_PKT_SIZE);
1835         else if (dev->gadget.speed == USB_SPEED_HIGH)
1836                 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1837                                 UDC_EP_MAX_PKT_SIZE);
1838         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1839
1840         /* set max packet size of EP0_OUT */
1841         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1842         if (dev->gadget.speed == USB_SPEED_FULL)
1843                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1844                                         UDC_EP_MAX_PKT_SIZE);
1845         else if (dev->gadget.speed == USB_SPEED_HIGH)
1846                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1847                                         UDC_EP_MAX_PKT_SIZE);
1848         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1849
1850         /* set max packet size of EP0 in UDC CSR */
1851         tmp = readl(&dev->csr->ne[0]);
1852         if (dev->gadget.speed == USB_SPEED_FULL)
1853                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1854                                         UDC_CSR_NE_MAX_PKT);
1855         else if (dev->gadget.speed == USB_SPEED_HIGH)
1856                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1857                                         UDC_CSR_NE_MAX_PKT);
1858         writel(tmp, &dev->csr->ne[0]);
1859
1860         if (use_dma) {
1861                 dev->ep[UDC_EP0OUT_IX].td->status |=
1862                         AMD_BIT(UDC_DMA_OUT_STS_L);
1863                 /* write dma desc address */
1864                 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1865                         &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1866                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1867                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1868                 /* stop RDE timer */
1869                 if (timer_pending(&udc_timer)) {
1870                         set_rde = 0;
1871                         mod_timer(&udc_timer, jiffies - 1);
1872                 }
1873                 /* stop pollstall timer */
1874                 if (timer_pending(&udc_pollstall_timer))
1875                         mod_timer(&udc_pollstall_timer, jiffies - 1);
1876                 /* enable DMA */
1877                 tmp = readl(&dev->regs->ctl);
1878                 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1879                                 | AMD_BIT(UDC_DEVCTL_RDE)
1880                                 | AMD_BIT(UDC_DEVCTL_TDE);
1881                 if (use_dma_bufferfill_mode)
1882                         tmp |= AMD_BIT(UDC_DEVCTL_BF);
1883                 else if (use_dma_ppb_du)
1884                         tmp |= AMD_BIT(UDC_DEVCTL_DU);
1885                 writel(tmp, &dev->regs->ctl);
1886         }
1887
1888         /* clear NAK by writing CNAK for EP0IN */
1889         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1890         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1891         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1892         dev->ep[UDC_EP0IN_IX].naking = 0;
1893         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1894
1895         /* clear NAK by writing CNAK for EP0OUT */
1896         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1897         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1898         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1899         dev->ep[UDC_EP0OUT_IX].naking = 0;
1900         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1901 }
1902
1903 /* Make endpoint 0 ready for control traffic */
1904 static int setup_ep0(struct udc *dev)
1905 {
1906         activate_control_endpoints(dev);
1907         /* enable ep0 interrupts */
1908         udc_enable_ep0_interrupts(dev);
1909         /* enable device setup interrupts */
1910         udc_enable_dev_setup_interrupts(dev);
1911
1912         return 0;
1913 }
1914
1915 /* Called by gadget driver to register itself */
1916 static int amd5536_start(struct usb_gadget_driver *driver,
1917                 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *))
1918 {
1919         struct udc              *dev = udc;
1920         int                     retval;
1921         u32 tmp;
1922
1923         if (!driver || !bind || !driver->setup
1924                         || driver->max_speed < USB_SPEED_HIGH)
1925                 return -EINVAL;
1926         if (!dev)
1927                 return -ENODEV;
1928         if (dev->driver)
1929                 return -EBUSY;
1930
1931         driver->driver.bus = NULL;
1932         dev->driver = driver;
1933         dev->gadget.dev.driver = &driver->driver;
1934
1935         retval = bind(&dev->gadget, driver);
1936
1937         /* Some gadget drivers use both ep0 directions.
1938          * NOTE: to gadget driver, ep0 is just one endpoint...
1939          */
1940         dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1941                 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1942
1943         if (retval) {
1944                 DBG(dev, "binding to %s returning %d\n",
1945                                 driver->driver.name, retval);
1946                 dev->driver = NULL;
1947                 dev->gadget.dev.driver = NULL;
1948                 return retval;
1949         }
1950
1951         /* get ready for ep0 traffic */
1952         setup_ep0(dev);
1953
1954         /* clear SD */
1955         tmp = readl(&dev->regs->ctl);
1956         tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1957         writel(tmp, &dev->regs->ctl);
1958
1959         usb_connect(dev);
1960
1961         return 0;
1962 }
1963
1964 /* shutdown requests and disconnect from gadget */
1965 static void
1966 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1967 __releases(dev->lock)
1968 __acquires(dev->lock)
1969 {
1970         int tmp;
1971
1972         if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1973                 spin_unlock(&dev->lock);
1974                 driver->disconnect(&dev->gadget);
1975                 spin_lock(&dev->lock);
1976         }
1977
1978         /* empty queues and init hardware */
1979         udc_basic_init(dev);
1980         for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1981                 empty_req_queue(&dev->ep[tmp]);
1982
1983         udc_setup_endpoints(dev);
1984 }
1985
1986 /* Called by gadget driver to unregister itself */
1987 static int amd5536_stop(struct usb_gadget_driver *driver)
1988 {
1989         struct udc      *dev = udc;
1990         unsigned long   flags;
1991         u32 tmp;
1992
1993         if (!dev)
1994                 return -ENODEV;
1995         if (!driver || driver != dev->driver || !driver->unbind)
1996                 return -EINVAL;
1997
1998         spin_lock_irqsave(&dev->lock, flags);
1999         udc_mask_unused_interrupts(dev);
2000         shutdown(dev, driver);
2001         spin_unlock_irqrestore(&dev->lock, flags);
2002
2003         driver->unbind(&dev->gadget);
2004         dev->gadget.dev.driver = NULL;
2005         dev->driver = NULL;
2006
2007         /* set SD */
2008         tmp = readl(&dev->regs->ctl);
2009         tmp |= AMD_BIT(UDC_DEVCTL_SD);
2010         writel(tmp, &dev->regs->ctl);
2011
2012
2013         DBG(dev, "%s: unregistered\n", driver->driver.name);
2014
2015         return 0;
2016 }
2017
2018 /* Clear pending NAK bits */
2019 static void udc_process_cnak_queue(struct udc *dev)
2020 {
2021         u32 tmp;
2022         u32 reg;
2023
2024         /* check epin's */
2025         DBG(dev, "CNAK pending queue processing\n");
2026         for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2027                 if (cnak_pending & (1 << tmp)) {
2028                         DBG(dev, "CNAK pending for ep%d\n", tmp);
2029                         /* clear NAK by writing CNAK */
2030                         reg = readl(&dev->ep[tmp].regs->ctl);
2031                         reg |= AMD_BIT(UDC_EPCTL_CNAK);
2032                         writel(reg, &dev->ep[tmp].regs->ctl);
2033                         dev->ep[tmp].naking = 0;
2034                         UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2035                 }
2036         }
2037         /* ...  and ep0out */
2038         if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2039                 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2040                 /* clear NAK by writing CNAK */
2041                 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2042                 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2043                 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2044                 dev->ep[UDC_EP0OUT_IX].naking = 0;
2045                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2046                                 dev->ep[UDC_EP0OUT_IX].num);
2047         }
2048 }
2049
2050 /* Enabling RX DMA after setup packet */
2051 static void udc_ep0_set_rde(struct udc *dev)
2052 {
2053         if (use_dma) {
2054                 /*
2055                  * only enable RXDMA when no data endpoint enabled
2056                  * or data is queued
2057                  */
2058                 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2059                         udc_set_rde(dev);
2060                 } else {
2061                         /*
2062                          * setup timer for enabling RDE (to not enable
2063                          * RXFIFO DMA for data endpoints to early)
2064                          */
2065                         if (set_rde != 0 && !timer_pending(&udc_timer)) {
2066                                 udc_timer.expires =
2067                                         jiffies + HZ/UDC_RDE_TIMER_DIV;
2068                                 set_rde = 1;
2069                                 if (!stop_timer)
2070                                         add_timer(&udc_timer);
2071                         }
2072                 }
2073         }
2074 }
2075
2076
2077 /* Interrupt handler for data OUT traffic */
2078 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2079 {
2080         irqreturn_t             ret_val = IRQ_NONE;
2081         u32                     tmp;
2082         struct udc_ep           *ep;
2083         struct udc_request      *req;
2084         unsigned int            count;
2085         struct udc_data_dma     *td = NULL;
2086         unsigned                dma_done;
2087
2088         VDBG(dev, "ep%d irq\n", ep_ix);
2089         ep = &dev->ep[ep_ix];
2090
2091         tmp = readl(&ep->regs->sts);
2092         if (use_dma) {
2093                 /* BNA event ? */
2094                 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2095                         DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2096                                         ep->num, readl(&ep->regs->desptr));
2097                         /* clear BNA */
2098                         writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2099                         if (!ep->cancel_transfer)
2100                                 ep->bna_occurred = 1;
2101                         else
2102                                 ep->cancel_transfer = 0;
2103                         ret_val = IRQ_HANDLED;
2104                         goto finished;
2105                 }
2106         }
2107         /* HE event ? */
2108         if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2109                 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
2110
2111                 /* clear HE */
2112                 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2113                 ret_val = IRQ_HANDLED;
2114                 goto finished;
2115         }
2116
2117         if (!list_empty(&ep->queue)) {
2118
2119                 /* next request */
2120                 req = list_entry(ep->queue.next,
2121                         struct udc_request, queue);
2122         } else {
2123                 req = NULL;
2124                 udc_rxfifo_pending = 1;
2125         }
2126         VDBG(dev, "req = %p\n", req);
2127         /* fifo mode */
2128         if (!use_dma) {
2129
2130                 /* read fifo */
2131                 if (req && udc_rxfifo_read(ep, req)) {
2132                         ret_val = IRQ_HANDLED;
2133
2134                         /* finish */
2135                         complete_req(ep, req, 0);
2136                         /* next request */
2137                         if (!list_empty(&ep->queue) && !ep->halted) {
2138                                 req = list_entry(ep->queue.next,
2139                                         struct udc_request, queue);
2140                         } else
2141                                 req = NULL;
2142                 }
2143
2144         /* DMA */
2145         } else if (!ep->cancel_transfer && req != NULL) {
2146                 ret_val = IRQ_HANDLED;
2147
2148                 /* check for DMA done */
2149                 if (!use_dma_ppb) {
2150                         dma_done = AMD_GETBITS(req->td_data->status,
2151                                                 UDC_DMA_OUT_STS_BS);
2152                 /* packet per buffer mode - rx bytes */
2153                 } else {
2154                         /*
2155                          * if BNA occurred then recover desc. from
2156                          * BNA dummy desc.
2157                          */
2158                         if (ep->bna_occurred) {
2159                                 VDBG(dev, "Recover desc. from BNA dummy\n");
2160                                 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2161                                                 sizeof(struct udc_data_dma));
2162                                 ep->bna_occurred = 0;
2163                                 udc_init_bna_dummy(ep->req);
2164                         }
2165                         td = udc_get_last_dma_desc(req);
2166                         dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2167                 }
2168                 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2169                         /* buffer fill mode - rx bytes */
2170                         if (!use_dma_ppb) {
2171                                 /* received number bytes */
2172                                 count = AMD_GETBITS(req->td_data->status,
2173                                                 UDC_DMA_OUT_STS_RXBYTES);
2174                                 VDBG(dev, "rx bytes=%u\n", count);
2175                         /* packet per buffer mode - rx bytes */
2176                         } else {
2177                                 VDBG(dev, "req->td_data=%p\n", req->td_data);
2178                                 VDBG(dev, "last desc = %p\n", td);
2179                                 /* received number bytes */
2180                                 if (use_dma_ppb_du) {
2181                                         /* every desc. counts bytes */
2182                                         count = udc_get_ppbdu_rxbytes(req);
2183                                 } else {
2184                                         /* last desc. counts bytes */
2185                                         count = AMD_GETBITS(td->status,
2186                                                 UDC_DMA_OUT_STS_RXBYTES);
2187                                         if (!count && req->req.length
2188                                                 == UDC_DMA_MAXPACKET) {
2189                                                 /*
2190                                                  * on 64k packets the RXBYTES
2191                                                  * field is zero
2192                                                  */
2193                                                 count = UDC_DMA_MAXPACKET;
2194                                         }
2195                                 }
2196                                 VDBG(dev, "last desc rx bytes=%u\n", count);
2197                         }
2198
2199                         tmp = req->req.length - req->req.actual;
2200                         if (count > tmp) {
2201                                 if ((tmp % ep->ep.maxpacket) != 0) {
2202                                         DBG(dev, "%s: rx %db, space=%db\n",
2203                                                 ep->ep.name, count, tmp);
2204                                         req->req.status = -EOVERFLOW;
2205                                 }
2206                                 count = tmp;
2207                         }
2208                         req->req.actual += count;
2209                         req->dma_going = 0;
2210                         /* complete request */
2211                         complete_req(ep, req, 0);
2212
2213                         /* next request */
2214                         if (!list_empty(&ep->queue) && !ep->halted) {
2215                                 req = list_entry(ep->queue.next,
2216                                         struct udc_request,
2217                                         queue);
2218                                 /*
2219                                  * DMA may be already started by udc_queue()
2220                                  * called by gadget drivers completion
2221                                  * routine. This happens when queue
2222                                  * holds one request only.
2223                                  */
2224                                 if (req->dma_going == 0) {
2225                                         /* next dma */
2226                                         if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2227                                                 goto finished;
2228                                         /* write desc pointer */
2229                                         writel(req->td_phys,
2230                                                 &ep->regs->desptr);
2231                                         req->dma_going = 1;
2232                                         /* enable DMA */
2233                                         udc_set_rde(dev);
2234                                 }
2235                         } else {
2236                                 /*
2237                                  * implant BNA dummy descriptor to allow
2238                                  * RXFIFO opening by RDE
2239                                  */
2240                                 if (ep->bna_dummy_req) {
2241                                         /* write desc pointer */
2242                                         writel(ep->bna_dummy_req->td_phys,
2243                                                 &ep->regs->desptr);
2244                                         ep->bna_occurred = 0;
2245                                 }
2246
2247                                 /*
2248                                  * schedule timer for setting RDE if queue
2249                                  * remains empty to allow ep0 packets pass
2250                                  * through
2251                                  */
2252                                 if (set_rde != 0
2253                                                 && !timer_pending(&udc_timer)) {
2254                                         udc_timer.expires =
2255                                                 jiffies
2256                                                 + HZ*UDC_RDE_TIMER_SECONDS;
2257                                         set_rde = 1;
2258                                         if (!stop_timer)
2259                                                 add_timer(&udc_timer);
2260                                 }
2261                                 if (ep->num != UDC_EP0OUT_IX)
2262                                         dev->data_ep_queued = 0;
2263                         }
2264
2265                 } else {
2266                         /*
2267                         * RX DMA must be reenabled for each desc in PPBDU mode
2268                         * and must be enabled for PPBNDU mode in case of BNA
2269                         */
2270                         udc_set_rde(dev);
2271                 }
2272
2273         } else if (ep->cancel_transfer) {
2274                 ret_val = IRQ_HANDLED;
2275                 ep->cancel_transfer = 0;
2276         }
2277
2278         /* check pending CNAKS */
2279         if (cnak_pending) {
2280                 /* CNAk processing when rxfifo empty only */
2281                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2282                         udc_process_cnak_queue(dev);
2283         }
2284
2285         /* clear OUT bits in ep status */
2286         writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2287 finished:
2288         return ret_val;
2289 }
2290
2291 /* Interrupt handler for data IN traffic */
2292 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2293 {
2294         irqreturn_t ret_val = IRQ_NONE;
2295         u32 tmp;
2296         u32 epsts;
2297         struct udc_ep *ep;
2298         struct udc_request *req;
2299         struct udc_data_dma *td;
2300         unsigned dma_done;
2301         unsigned len;
2302
2303         ep = &dev->ep[ep_ix];
2304
2305         epsts = readl(&ep->regs->sts);
2306         if (use_dma) {
2307                 /* BNA ? */
2308                 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2309                         dev_err(&dev->pdev->dev,
2310                                 "BNA ep%din occurred - DESPTR = %08lx\n",
2311                                 ep->num,
2312                                 (unsigned long) readl(&ep->regs->desptr));
2313
2314                         /* clear BNA */
2315                         writel(epsts, &ep->regs->sts);
2316                         ret_val = IRQ_HANDLED;
2317                         goto finished;
2318                 }
2319         }
2320         /* HE event ? */
2321         if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2322                 dev_err(&dev->pdev->dev,
2323                         "HE ep%dn occurred - DESPTR = %08lx\n",
2324                         ep->num, (unsigned long) readl(&ep->regs->desptr));
2325
2326                 /* clear HE */
2327                 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2328                 ret_val = IRQ_HANDLED;
2329                 goto finished;
2330         }
2331
2332         /* DMA completion */
2333         if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2334                 VDBG(dev, "TDC set- completion\n");
2335                 ret_val = IRQ_HANDLED;
2336                 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2337                         req = list_entry(ep->queue.next,
2338                                         struct udc_request, queue);
2339                         /*
2340                          * length bytes transferred
2341                          * check dma done of last desc. in PPBDU mode
2342                          */
2343                         if (use_dma_ppb_du) {
2344                                 td = udc_get_last_dma_desc(req);
2345                                 if (td) {
2346                                         dma_done =
2347                                                 AMD_GETBITS(td->status,
2348                                                 UDC_DMA_IN_STS_BS);
2349                                         /* don't care DMA done */
2350                                         req->req.actual = req->req.length;
2351                                 }
2352                         } else {
2353                                 /* assume all bytes transferred */
2354                                 req->req.actual = req->req.length;
2355                         }
2356
2357                         if (req->req.actual == req->req.length) {
2358                                 /* complete req */
2359                                 complete_req(ep, req, 0);
2360                                 req->dma_going = 0;
2361                                 /* further request available ? */
2362                                 if (list_empty(&ep->queue)) {
2363                                         /* disable interrupt */
2364                                         tmp = readl(&dev->regs->ep_irqmsk);
2365                                         tmp |= AMD_BIT(ep->num);
2366                                         writel(tmp, &dev->regs->ep_irqmsk);
2367                                 }
2368                         }
2369                 }
2370                 ep->cancel_transfer = 0;
2371
2372         }
2373         /*
2374          * status reg has IN bit set and TDC not set (if TDC was handled,
2375          * IN must not be handled (UDC defect) ?
2376          */
2377         if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2378                         && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2379                 ret_val = IRQ_HANDLED;
2380                 if (!list_empty(&ep->queue)) {
2381                         /* next request */
2382                         req = list_entry(ep->queue.next,
2383                                         struct udc_request, queue);
2384                         /* FIFO mode */
2385                         if (!use_dma) {
2386                                 /* write fifo */
2387                                 udc_txfifo_write(ep, &req->req);
2388                                 len = req->req.length - req->req.actual;
2389                                 if (len > ep->ep.maxpacket)
2390                                         len = ep->ep.maxpacket;
2391                                 req->req.actual += len;
2392                                 if (req->req.actual == req->req.length
2393                                         || (len != ep->ep.maxpacket)) {
2394                                         /* complete req */
2395                                         complete_req(ep, req, 0);
2396                                 }
2397                         /* DMA */
2398                         } else if (req && !req->dma_going) {
2399                                 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2400                                         req, req->td_data);
2401                                 if (req->td_data) {
2402
2403                                         req->dma_going = 1;
2404
2405                                         /*
2406                                          * unset L bit of first desc.
2407                                          * for chain
2408                                          */
2409                                         if (use_dma_ppb && req->req.length >
2410                                                         ep->ep.maxpacket) {
2411                                                 req->td_data->status &=
2412                                                         AMD_CLEAR_BIT(
2413                                                         UDC_DMA_IN_STS_L);
2414                                         }
2415
2416                                         /* write desc pointer */
2417                                         writel(req->td_phys, &ep->regs->desptr);
2418
2419                                         /* set HOST READY */
2420                                         req->td_data->status =
2421                                                 AMD_ADDBITS(
2422                                                 req->td_data->status,
2423                                                 UDC_DMA_IN_STS_BS_HOST_READY,
2424                                                 UDC_DMA_IN_STS_BS);
2425
2426                                         /* set poll demand bit */
2427                                         tmp = readl(&ep->regs->ctl);
2428                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2429                                         writel(tmp, &ep->regs->ctl);
2430                                 }
2431                         }
2432
2433                 } else if (!use_dma && ep->in) {
2434                         /* disable interrupt */
2435                         tmp = readl(
2436                                 &dev->regs->ep_irqmsk);
2437                         tmp |= AMD_BIT(ep->num);
2438                         writel(tmp,
2439                                 &dev->regs->ep_irqmsk);
2440                 }
2441         }
2442         /* clear status bits */
2443         writel(epsts, &ep->regs->sts);
2444
2445 finished:
2446         return ret_val;
2447
2448 }
2449
2450 /* Interrupt handler for Control OUT traffic */
2451 static irqreturn_t udc_control_out_isr(struct udc *dev)
2452 __releases(dev->lock)
2453 __acquires(dev->lock)
2454 {
2455         irqreturn_t ret_val = IRQ_NONE;
2456         u32 tmp;
2457         int setup_supported;
2458         u32 count;
2459         int set = 0;
2460         struct udc_ep   *ep;
2461         struct udc_ep   *ep_tmp;
2462
2463         ep = &dev->ep[UDC_EP0OUT_IX];
2464
2465         /* clear irq */
2466         writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2467
2468         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2469         /* check BNA and clear if set */
2470         if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2471                 VDBG(dev, "ep0: BNA set\n");
2472                 writel(AMD_BIT(UDC_EPSTS_BNA),
2473                         &dev->ep[UDC_EP0OUT_IX].regs->sts);
2474                 ep->bna_occurred = 1;
2475                 ret_val = IRQ_HANDLED;
2476                 goto finished;
2477         }
2478
2479         /* type of data: SETUP or DATA 0 bytes */
2480         tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2481         VDBG(dev, "data_typ = %x\n", tmp);
2482
2483         /* setup data */
2484         if (tmp == UDC_EPSTS_OUT_SETUP) {
2485                 ret_val = IRQ_HANDLED;
2486
2487                 ep->dev->stall_ep0in = 0;
2488                 dev->waiting_zlp_ack_ep0in = 0;
2489
2490                 /* set NAK for EP0_IN */
2491                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2492                 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2493                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2494                 dev->ep[UDC_EP0IN_IX].naking = 1;
2495                 /* get setup data */
2496                 if (use_dma) {
2497
2498                         /* clear OUT bits in ep status */
2499                         writel(UDC_EPSTS_OUT_CLEAR,
2500                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2501
2502                         setup_data.data[0] =
2503                                 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2504                         setup_data.data[1] =
2505                                 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2506                         /* set HOST READY */
2507                         dev->ep[UDC_EP0OUT_IX].td_stp->status =
2508                                         UDC_DMA_STP_STS_BS_HOST_READY;
2509                 } else {
2510                         /* read fifo */
2511                         udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2512                 }
2513
2514                 /* determine direction of control data */
2515                 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2516                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2517                         /* enable RDE */
2518                         udc_ep0_set_rde(dev);
2519                         set = 0;
2520                 } else {
2521                         dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2522                         /*
2523                          * implant BNA dummy descriptor to allow RXFIFO opening
2524                          * by RDE
2525                          */
2526                         if (ep->bna_dummy_req) {
2527                                 /* write desc pointer */
2528                                 writel(ep->bna_dummy_req->td_phys,
2529                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2530                                 ep->bna_occurred = 0;
2531                         }
2532
2533                         set = 1;
2534                         dev->ep[UDC_EP0OUT_IX].naking = 1;
2535                         /*
2536                          * setup timer for enabling RDE (to not enable
2537                          * RXFIFO DMA for data to early)
2538                          */
2539                         set_rde = 1;
2540                         if (!timer_pending(&udc_timer)) {
2541                                 udc_timer.expires = jiffies +
2542                                                         HZ/UDC_RDE_TIMER_DIV;
2543                                 if (!stop_timer)
2544                                         add_timer(&udc_timer);
2545                         }
2546                 }
2547
2548                 /*
2549                  * mass storage reset must be processed here because
2550                  * next packet may be a CLEAR_FEATURE HALT which would not
2551                  * clear the stall bit when no STALL handshake was received
2552                  * before (autostall can cause this)
2553                  */
2554                 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2555                                 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2556                         DBG(dev, "MSC Reset\n");
2557                         /*
2558                          * clear stall bits
2559                          * only one IN and OUT endpoints are handled
2560                          */
2561                         ep_tmp = &udc->ep[UDC_EPIN_IX];
2562                         udc_set_halt(&ep_tmp->ep, 0);
2563                         ep_tmp = &udc->ep[UDC_EPOUT_IX];
2564                         udc_set_halt(&ep_tmp->ep, 0);
2565                 }
2566
2567                 /* call gadget with setup data received */
2568                 spin_unlock(&dev->lock);
2569                 setup_supported = dev->driver->setup(&dev->gadget,
2570                                                 &setup_data.request);
2571                 spin_lock(&dev->lock);
2572
2573                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2574                 /* ep0 in returns data (not zlp) on IN phase */
2575                 if (setup_supported >= 0 && setup_supported <
2576                                 UDC_EP0IN_MAXPACKET) {
2577                         /* clear NAK by writing CNAK in EP0_IN */
2578                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2579                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2580                         dev->ep[UDC_EP0IN_IX].naking = 0;
2581                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2582
2583                 /* if unsupported request then stall */
2584                 } else if (setup_supported < 0) {
2585                         tmp |= AMD_BIT(UDC_EPCTL_S);
2586                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2587                 } else
2588                         dev->waiting_zlp_ack_ep0in = 1;
2589
2590
2591                 /* clear NAK by writing CNAK in EP0_OUT */
2592                 if (!set) {
2593                         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2594                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2595                         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2596                         dev->ep[UDC_EP0OUT_IX].naking = 0;
2597                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2598                 }
2599
2600                 if (!use_dma) {
2601                         /* clear OUT bits in ep status */
2602                         writel(UDC_EPSTS_OUT_CLEAR,
2603                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2604                 }
2605
2606         /* data packet 0 bytes */
2607         } else if (tmp == UDC_EPSTS_OUT_DATA) {
2608                 /* clear OUT bits in ep status */
2609                 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2610
2611                 /* get setup data: only 0 packet */
2612                 if (use_dma) {
2613                         /* no req if 0 packet, just reactivate */
2614                         if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2615                                 VDBG(dev, "ZLP\n");
2616
2617                                 /* set HOST READY */
2618                                 dev->ep[UDC_EP0OUT_IX].td->status =
2619                                         AMD_ADDBITS(
2620                                         dev->ep[UDC_EP0OUT_IX].td->status,
2621                                         UDC_DMA_OUT_STS_BS_HOST_READY,
2622                                         UDC_DMA_OUT_STS_BS);
2623                                 /* enable RDE */
2624                                 udc_ep0_set_rde(dev);
2625                                 ret_val = IRQ_HANDLED;
2626
2627                         } else {
2628                                 /* control write */
2629                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2630                                 /* re-program desc. pointer for possible ZLPs */
2631                                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2632                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2633                                 /* enable RDE */
2634                                 udc_ep0_set_rde(dev);
2635                         }
2636                 } else {
2637
2638                         /* received number bytes */
2639                         count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2640                         count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2641                         /* out data for fifo mode not working */
2642                         count = 0;
2643
2644                         /* 0 packet or real data ? */
2645                         if (count != 0) {
2646                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2647                         } else {
2648                                 /* dummy read confirm */
2649                                 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2650                                 ret_val = IRQ_HANDLED;
2651                         }
2652                 }
2653         }
2654
2655         /* check pending CNAKS */
2656         if (cnak_pending) {
2657                 /* CNAk processing when rxfifo empty only */
2658                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2659                         udc_process_cnak_queue(dev);
2660         }
2661
2662 finished:
2663         return ret_val;
2664 }
2665
2666 /* Interrupt handler for Control IN traffic */
2667 static irqreturn_t udc_control_in_isr(struct udc *dev)
2668 {
2669         irqreturn_t ret_val = IRQ_NONE;
2670         u32 tmp;
2671         struct udc_ep *ep;
2672         struct udc_request *req;
2673         unsigned len;
2674
2675         ep = &dev->ep[UDC_EP0IN_IX];
2676
2677         /* clear irq */
2678         writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2679
2680         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2681         /* DMA completion */
2682         if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2683                 VDBG(dev, "isr: TDC clear\n");
2684                 ret_val = IRQ_HANDLED;
2685
2686                 /* clear TDC bit */
2687                 writel(AMD_BIT(UDC_EPSTS_TDC),
2688                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2689
2690         /* status reg has IN bit set ? */
2691         } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2692                 ret_val = IRQ_HANDLED;
2693
2694                 if (ep->dma) {
2695                         /* clear IN bit */
2696                         writel(AMD_BIT(UDC_EPSTS_IN),
2697                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2698                 }
2699                 if (dev->stall_ep0in) {
2700                         DBG(dev, "stall ep0in\n");
2701                         /* halt ep0in */
2702                         tmp = readl(&ep->regs->ctl);
2703                         tmp |= AMD_BIT(UDC_EPCTL_S);
2704                         writel(tmp, &ep->regs->ctl);
2705                 } else {
2706                         if (!list_empty(&ep->queue)) {
2707                                 /* next request */
2708                                 req = list_entry(ep->queue.next,
2709                                                 struct udc_request, queue);
2710
2711                                 if (ep->dma) {
2712                                         /* write desc pointer */
2713                                         writel(req->td_phys, &ep->regs->desptr);
2714                                         /* set HOST READY */
2715                                         req->td_data->status =
2716                                                 AMD_ADDBITS(
2717                                                 req->td_data->status,
2718                                                 UDC_DMA_STP_STS_BS_HOST_READY,
2719                                                 UDC_DMA_STP_STS_BS);
2720
2721                                         /* set poll demand bit */
2722                                         tmp =
2723                                         readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2724                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2725                                         writel(tmp,
2726                                         &dev->ep[UDC_EP0IN_IX].regs->ctl);
2727
2728                                         /* all bytes will be transferred */
2729                                         req->req.actual = req->req.length;
2730
2731                                         /* complete req */
2732                                         complete_req(ep, req, 0);
2733
2734                                 } else {
2735                                         /* write fifo */
2736                                         udc_txfifo_write(ep, &req->req);
2737
2738                                         /* lengh bytes transferred */
2739                                         len = req->req.length - req->req.actual;
2740                                         if (len > ep->ep.maxpacket)
2741                                                 len = ep->ep.maxpacket;
2742
2743                                         req->req.actual += len;
2744                                         if (req->req.actual == req->req.length
2745                                                 || (len != ep->ep.maxpacket)) {
2746                                                 /* complete req */
2747                                                 complete_req(ep, req, 0);
2748                                         }
2749                                 }
2750
2751                         }
2752                 }
2753                 ep->halted = 0;
2754                 dev->stall_ep0in = 0;
2755                 if (!ep->dma) {
2756                         /* clear IN bit */
2757                         writel(AMD_BIT(UDC_EPSTS_IN),
2758                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2759                 }
2760         }
2761
2762         return ret_val;
2763 }
2764
2765
2766 /* Interrupt handler for global device events */
2767 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2768 __releases(dev->lock)
2769 __acquires(dev->lock)
2770 {
2771         irqreturn_t ret_val = IRQ_NONE;
2772         u32 tmp;
2773         u32 cfg;
2774         struct udc_ep *ep;
2775         u16 i;
2776         u8 udc_csr_epix;
2777
2778         /* SET_CONFIG irq ? */
2779         if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2780                 ret_val = IRQ_HANDLED;
2781
2782                 /* read config value */
2783                 tmp = readl(&dev->regs->sts);
2784                 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2785                 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2786                 dev->cur_config = cfg;
2787                 dev->set_cfg_not_acked = 1;
2788
2789                 /* make usb request for gadget driver */
2790                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2791                 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2792                 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2793
2794                 /* programm the NE registers */
2795                 for (i = 0; i < UDC_EP_NUM; i++) {
2796                         ep = &dev->ep[i];
2797                         if (ep->in) {
2798
2799                                 /* ep ix in UDC CSR register space */
2800                                 udc_csr_epix = ep->num;
2801
2802
2803                         /* OUT ep */
2804                         } else {
2805                                 /* ep ix in UDC CSR register space */
2806                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2807                         }
2808
2809                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2810                         /* ep cfg */
2811                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2812                                                 UDC_CSR_NE_CFG);
2813                         /* write reg */
2814                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2815
2816                         /* clear stall bits */
2817                         ep->halted = 0;
2818                         tmp = readl(&ep->regs->ctl);
2819                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2820                         writel(tmp, &ep->regs->ctl);
2821                 }
2822                 /* call gadget zero with setup data received */
2823                 spin_unlock(&dev->lock);
2824                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2825                 spin_lock(&dev->lock);
2826
2827         } /* SET_INTERFACE ? */
2828         if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2829                 ret_val = IRQ_HANDLED;
2830
2831                 dev->set_cfg_not_acked = 1;
2832                 /* read interface and alt setting values */
2833                 tmp = readl(&dev->regs->sts);
2834                 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2835                 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2836
2837                 /* make usb request for gadget driver */
2838                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2839                 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2840                 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2841                 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2842                 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2843
2844                 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2845                                 dev->cur_alt, dev->cur_intf);
2846
2847                 /* programm the NE registers */
2848                 for (i = 0; i < UDC_EP_NUM; i++) {
2849                         ep = &dev->ep[i];
2850                         if (ep->in) {
2851
2852                                 /* ep ix in UDC CSR register space */
2853                                 udc_csr_epix = ep->num;
2854
2855
2856                         /* OUT ep */
2857                         } else {
2858                                 /* ep ix in UDC CSR register space */
2859                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2860                         }
2861
2862                         /* UDC CSR reg */
2863                         /* set ep values */
2864                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2865                         /* ep interface */
2866                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2867                                                 UDC_CSR_NE_INTF);
2868                         /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2869                         /* ep alt */
2870                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2871                                                 UDC_CSR_NE_ALT);
2872                         /* write reg */
2873                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2874
2875                         /* clear stall bits */
2876                         ep->halted = 0;
2877                         tmp = readl(&ep->regs->ctl);
2878                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2879                         writel(tmp, &ep->regs->ctl);
2880                 }
2881
2882                 /* call gadget zero with setup data received */
2883                 spin_unlock(&dev->lock);
2884                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2885                 spin_lock(&dev->lock);
2886
2887         } /* USB reset */
2888         if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2889                 DBG(dev, "USB Reset interrupt\n");
2890                 ret_val = IRQ_HANDLED;
2891
2892                 /* allow soft reset when suspend occurs */
2893                 soft_reset_occured = 0;
2894
2895                 dev->waiting_zlp_ack_ep0in = 0;
2896                 dev->set_cfg_not_acked = 0;
2897
2898                 /* mask not needed interrupts */
2899                 udc_mask_unused_interrupts(dev);
2900
2901                 /* call gadget to resume and reset configs etc. */
2902                 spin_unlock(&dev->lock);
2903                 if (dev->sys_suspended && dev->driver->resume) {
2904                         dev->driver->resume(&dev->gadget);
2905                         dev->sys_suspended = 0;
2906                 }
2907                 dev->driver->disconnect(&dev->gadget);
2908                 spin_lock(&dev->lock);
2909
2910                 /* disable ep0 to empty req queue */
2911                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2912                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2913
2914                 /* soft reset when rxfifo not empty */
2915                 tmp = readl(&dev->regs->sts);
2916                 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2917                                 && !soft_reset_after_usbreset_occured) {
2918                         udc_soft_reset(dev);
2919                         soft_reset_after_usbreset_occured++;
2920                 }
2921
2922                 /*
2923                  * DMA reset to kill potential old DMA hw hang,
2924                  * POLL bit is already reset by ep_init() through
2925                  * disconnect()
2926                  */
2927                 DBG(dev, "DMA machine reset\n");
2928                 tmp = readl(&dev->regs->cfg);
2929                 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2930                 writel(tmp, &dev->regs->cfg);
2931
2932                 /* put into initial config */
2933                 udc_basic_init(dev);
2934
2935                 /* enable device setup interrupts */
2936                 udc_enable_dev_setup_interrupts(dev);
2937
2938                 /* enable suspend interrupt */
2939                 tmp = readl(&dev->regs->irqmsk);
2940                 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2941                 writel(tmp, &dev->regs->irqmsk);
2942
2943         } /* USB suspend */
2944         if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2945                 DBG(dev, "USB Suspend interrupt\n");
2946                 ret_val = IRQ_HANDLED;
2947                 if (dev->driver->suspend) {
2948                         spin_unlock(&dev->lock);
2949                         dev->sys_suspended = 1;
2950                         dev->driver->suspend(&dev->gadget);
2951                         spin_lock(&dev->lock);
2952                 }
2953         } /* new speed ? */
2954         if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2955                 DBG(dev, "ENUM interrupt\n");
2956                 ret_val = IRQ_HANDLED;
2957                 soft_reset_after_usbreset_occured = 0;
2958
2959                 /* disable ep0 to empty req queue */
2960                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2961                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2962
2963                 /* link up all endpoints */
2964                 udc_setup_endpoints(dev);
2965                 dev_info(&dev->pdev->dev, "Connect: %s\n",
2966                          usb_speed_string(dev->gadget.speed));
2967
2968                 /* init ep 0 */
2969                 activate_control_endpoints(dev);
2970
2971                 /* enable ep0 interrupts */
2972                 udc_enable_ep0_interrupts(dev);
2973         }
2974         /* session valid change interrupt */
2975         if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2976                 DBG(dev, "USB SVC interrupt\n");
2977                 ret_val = IRQ_HANDLED;
2978
2979                 /* check that session is not valid to detect disconnect */
2980                 tmp = readl(&dev->regs->sts);
2981                 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2982                         /* disable suspend interrupt */
2983                         tmp = readl(&dev->regs->irqmsk);
2984                         tmp |= AMD_BIT(UDC_DEVINT_US);
2985                         writel(tmp, &dev->regs->irqmsk);
2986                         DBG(dev, "USB Disconnect (session valid low)\n");
2987                         /* cleanup on disconnect */
2988                         usb_disconnect(udc);
2989                 }
2990
2991         }
2992
2993         return ret_val;
2994 }
2995
2996 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2997 static irqreturn_t udc_irq(int irq, void *pdev)
2998 {
2999         struct udc *dev = pdev;
3000         u32 reg;
3001         u16 i;
3002         u32 ep_irq;
3003         irqreturn_t ret_val = IRQ_NONE;
3004
3005         spin_lock(&dev->lock);
3006
3007         /* check for ep irq */
3008         reg = readl(&dev->regs->ep_irqsts);
3009         if (reg) {
3010                 if&nb