Merge tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6
[~shefty/rdma-dev.git] / drivers / video / da8xx-fb.c
1 /*
2  * Copyright (C) 2008-2009 MontaVista Software Inc.
3  * Copyright (C) 2008-2009 Texas Instruments Inc
4  *
5  * Based on the LCD driver for TI Avalanche processors written by
6  * Ajay Singh and Shalom Hai.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option)any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/interrupt.h>
31 #include <linux/wait.h>
32 #include <linux/clk.h>
33 #include <linux/cpufreq.h>
34 #include <linux/console.h>
35 #include <linux/spinlock.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <linux/lcm.h>
39 #include <video/da8xx-fb.h>
40 #include <asm/div64.h>
41
42 #define DRIVER_NAME "da8xx_lcdc"
43
44 #define LCD_VERSION_1   1
45 #define LCD_VERSION_2   2
46
47 /* LCD Status Register */
48 #define LCD_END_OF_FRAME1               BIT(9)
49 #define LCD_END_OF_FRAME0               BIT(8)
50 #define LCD_PL_LOAD_DONE                BIT(6)
51 #define LCD_FIFO_UNDERFLOW              BIT(5)
52 #define LCD_SYNC_LOST                   BIT(2)
53 #define LCD_FRAME_DONE                  BIT(0)
54
55 /* LCD DMA Control Register */
56 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
57 #define LCD_DMA_BURST_1                 0x0
58 #define LCD_DMA_BURST_2                 0x1
59 #define LCD_DMA_BURST_4                 0x2
60 #define LCD_DMA_BURST_8                 0x3
61 #define LCD_DMA_BURST_16                0x4
62 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
63 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
64 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
65 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
66
67 /* LCD Control Register */
68 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
69 #define LCD_RASTER_MODE                 0x01
70
71 /* LCD Raster Control Register */
72 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
73 #define PALETTE_AND_DATA                0x00
74 #define PALETTE_ONLY                    0x01
75 #define DATA_ONLY                       0x02
76
77 #define LCD_MONO_8BIT_MODE              BIT(9)
78 #define LCD_RASTER_ORDER                BIT(8)
79 #define LCD_TFT_MODE                    BIT(7)
80 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
81 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
82 #define LCD_V1_PL_INT_ENA               BIT(4)
83 #define LCD_V2_PL_INT_ENA               BIT(6)
84 #define LCD_MONOCHROME_MODE             BIT(1)
85 #define LCD_RASTER_ENABLE               BIT(0)
86 #define LCD_TFT_ALT_ENABLE              BIT(23)
87 #define LCD_STN_565_ENABLE              BIT(24)
88 #define LCD_V2_DMA_CLK_EN               BIT(2)
89 #define LCD_V2_LIDD_CLK_EN              BIT(1)
90 #define LCD_V2_CORE_CLK_EN              BIT(0)
91 #define LCD_V2_LPP_B10                  26
92 #define LCD_V2_TFT_24BPP_MODE           BIT(25)
93 #define LCD_V2_TFT_24BPP_UNPACK         BIT(26)
94
95 /* LCD Raster Timing 2 Register */
96 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
97 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
98 #define LCD_SYNC_CTRL                           BIT(25)
99 #define LCD_SYNC_EDGE                           BIT(24)
100 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
101 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
102 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
103
104 /* LCD Block */
105 #define  LCD_PID_REG                            0x0
106 #define  LCD_CTRL_REG                           0x4
107 #define  LCD_STAT_REG                           0x8
108 #define  LCD_RASTER_CTRL_REG                    0x28
109 #define  LCD_RASTER_TIMING_0_REG                0x2C
110 #define  LCD_RASTER_TIMING_1_REG                0x30
111 #define  LCD_RASTER_TIMING_2_REG                0x34
112 #define  LCD_DMA_CTRL_REG                       0x40
113 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
114 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
115 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
116 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
117
118 /* Interrupt Registers available only in Version 2 */
119 #define  LCD_RAW_STAT_REG                       0x58
120 #define  LCD_MASKED_STAT_REG                    0x5c
121 #define  LCD_INT_ENABLE_SET_REG                 0x60
122 #define  LCD_INT_ENABLE_CLR_REG                 0x64
123 #define  LCD_END_OF_INT_IND_REG                 0x68
124
125 /* Clock registers available only on Version 2 */
126 #define  LCD_CLK_ENABLE_REG                     0x6c
127 #define  LCD_CLK_RESET_REG                      0x70
128 #define  LCD_CLK_MAIN_RESET                     BIT(3)
129
130 #define LCD_NUM_BUFFERS 2
131
132 #define WSI_TIMEOUT     50
133 #define PALETTE_SIZE    256
134 #define LEFT_MARGIN     64
135 #define RIGHT_MARGIN    64
136 #define UPPER_MARGIN    32
137 #define LOWER_MARGIN    32
138
139 static void __iomem *da8xx_fb_reg_base;
140 static struct resource *lcdc_regs;
141 static unsigned int lcd_revision;
142 static irq_handler_t lcdc_irq_handler;
143 static wait_queue_head_t frame_done_wq;
144 static int frame_done_flag;
145
146 static inline unsigned int lcdc_read(unsigned int addr)
147 {
148         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
149 }
150
151 static inline void lcdc_write(unsigned int val, unsigned int addr)
152 {
153         __raw_writel(val, da8xx_fb_reg_base + (addr));
154 }
155
156 struct da8xx_fb_par {
157         resource_size_t p_palette_base;
158         unsigned char *v_palette_base;
159         dma_addr_t              vram_phys;
160         unsigned long           vram_size;
161         void                    *vram_virt;
162         unsigned int            dma_start;
163         unsigned int            dma_end;
164         struct clk *lcdc_clk;
165         int irq;
166         unsigned int palette_sz;
167         unsigned int pxl_clk;
168         int blank;
169         wait_queue_head_t       vsync_wait;
170         int                     vsync_flag;
171         int                     vsync_timeout;
172         spinlock_t              lock_for_chan_update;
173
174         /*
175          * LCDC has 2 ping pong DMA channels, channel 0
176          * and channel 1.
177          */
178         unsigned int            which_dma_channel_done;
179 #ifdef CONFIG_CPU_FREQ
180         struct notifier_block   freq_transition;
181         unsigned int            lcd_fck_rate;
182 #endif
183         void (*panel_power_ctrl)(int);
184         u32 pseudo_palette[16];
185 };
186
187 /* Variable Screen Information */
188 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
189         .xoffset = 0,
190         .yoffset = 0,
191         .transp = {0, 0, 0},
192         .nonstd = 0,
193         .activate = 0,
194         .height = -1,
195         .width = -1,
196         .accel_flags = 0,
197         .left_margin = LEFT_MARGIN,
198         .right_margin = RIGHT_MARGIN,
199         .upper_margin = UPPER_MARGIN,
200         .lower_margin = LOWER_MARGIN,
201         .sync = 0,
202         .vmode = FB_VMODE_NONINTERLACED
203 };
204
205 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
206         .id = "DA8xx FB Drv",
207         .type = FB_TYPE_PACKED_PIXELS,
208         .type_aux = 0,
209         .visual = FB_VISUAL_PSEUDOCOLOR,
210         .xpanstep = 0,
211         .ypanstep = 1,
212         .ywrapstep = 0,
213         .accel = FB_ACCEL_NONE
214 };
215
216 struct da8xx_panel {
217         const char      name[25];       /* Full name <vendor>_<model> */
218         unsigned short  width;
219         unsigned short  height;
220         int             hfp;            /* Horizontal front porch */
221         int             hbp;            /* Horizontal back porch */
222         int             hsw;            /* Horizontal Sync Pulse Width */
223         int             vfp;            /* Vertical front porch */
224         int             vbp;            /* Vertical back porch */
225         int             vsw;            /* Vertical Sync Pulse Width */
226         unsigned int    pxl_clk;        /* Pixel clock */
227         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
228 };
229
230 static struct da8xx_panel known_lcd_panels[] = {
231         /* Sharp LCD035Q3DG01 */
232         [0] = {
233                 .name = "Sharp_LCD035Q3DG01",
234                 .width = 320,
235                 .height = 240,
236                 .hfp = 8,
237                 .hbp = 6,
238                 .hsw = 0,
239                 .vfp = 2,
240                 .vbp = 2,
241                 .vsw = 0,
242                 .pxl_clk = 4608000,
243                 .invert_pxl_clk = 1,
244         },
245         /* Sharp LK043T1DG01 */
246         [1] = {
247                 .name = "Sharp_LK043T1DG01",
248                 .width = 480,
249                 .height = 272,
250                 .hfp = 2,
251                 .hbp = 2,
252                 .hsw = 41,
253                 .vfp = 2,
254                 .vbp = 2,
255                 .vsw = 10,
256                 .pxl_clk = 7833600,
257                 .invert_pxl_clk = 0,
258         },
259         [2] = {
260                 /* Hitachi SP10Q010 */
261                 .name = "SP10Q010",
262                 .width = 320,
263                 .height = 240,
264                 .hfp = 10,
265                 .hbp = 10,
266                 .hsw = 10,
267                 .vfp = 10,
268                 .vbp = 10,
269                 .vsw = 10,
270                 .pxl_clk = 7833600,
271                 .invert_pxl_clk = 0,
272         },
273 };
274
275 /* Enable the Raster Engine of the LCD Controller */
276 static inline void lcd_enable_raster(void)
277 {
278         u32 reg;
279
280         /* Put LCDC in reset for several cycles */
281         if (lcd_revision == LCD_VERSION_2)
282                 /* Write 1 to reset LCDC */
283                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
284         mdelay(1);
285
286         /* Bring LCDC out of reset */
287         if (lcd_revision == LCD_VERSION_2)
288                 lcdc_write(0, LCD_CLK_RESET_REG);
289         mdelay(1);
290
291         /* Above reset sequence doesnot reset register context */
292         reg = lcdc_read(LCD_RASTER_CTRL_REG);
293         if (!(reg & LCD_RASTER_ENABLE))
294                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
295 }
296
297 /* Disable the Raster Engine of the LCD Controller */
298 static inline void lcd_disable_raster(bool wait_for_frame_done)
299 {
300         u32 reg;
301         int ret;
302
303         reg = lcdc_read(LCD_RASTER_CTRL_REG);
304         if (reg & LCD_RASTER_ENABLE)
305                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
306         else
307                 /* return if already disabled */
308                 return;
309
310         if ((wait_for_frame_done == true) && (lcd_revision == LCD_VERSION_2)) {
311                 frame_done_flag = 0;
312                 ret = wait_event_interruptible_timeout(frame_done_wq,
313                                 frame_done_flag != 0,
314                                 msecs_to_jiffies(50));
315                 if (ret == 0)
316                         pr_err("LCD Controller timed out\n");
317         }
318 }
319
320 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
321 {
322         u32 start;
323         u32 end;
324         u32 reg_ras;
325         u32 reg_dma;
326         u32 reg_int;
327
328         /* init reg to clear PLM (loading mode) fields */
329         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
330         reg_ras &= ~(3 << 20);
331
332         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
333
334         if (load_mode == LOAD_DATA) {
335                 start    = par->dma_start;
336                 end      = par->dma_end;
337
338                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
339                 if (lcd_revision == LCD_VERSION_1) {
340                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
341                 } else {
342                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
343                                 LCD_V2_END_OF_FRAME0_INT_ENA |
344                                 LCD_V2_END_OF_FRAME1_INT_ENA |
345                                 LCD_FRAME_DONE;
346                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
347                 }
348                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
349
350                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
351                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
352                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
353                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
354         } else if (load_mode == LOAD_PALETTE) {
355                 start    = par->p_palette_base;
356                 end      = start + par->palette_sz - 1;
357
358                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
359
360                 if (lcd_revision == LCD_VERSION_1) {
361                         reg_ras |= LCD_V1_PL_INT_ENA;
362                 } else {
363                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
364                                 LCD_V2_PL_INT_ENA;
365                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
366                 }
367
368                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
369                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
370         }
371
372         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
373         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
374
375         /*
376          * The Raster enable bit must be set after all other control fields are
377          * set.
378          */
379         lcd_enable_raster();
380 }
381
382 /* Configure the Burst Size and fifo threhold of DMA */
383 static int lcd_cfg_dma(int burst_size, int fifo_th)
384 {
385         u32 reg;
386
387         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
388         switch (burst_size) {
389         case 1:
390                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
391                 break;
392         case 2:
393                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
394                 break;
395         case 4:
396                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
397                 break;
398         case 8:
399                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
400                 break;
401         case 16:
402                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
403                 break;
404         default:
405                 return -EINVAL;
406         }
407
408         reg |= (fifo_th << 8);
409
410         lcdc_write(reg, LCD_DMA_CTRL_REG);
411
412         return 0;
413 }
414
415 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
416 {
417         u32 reg;
418
419         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
420         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
421         reg |= LCD_AC_BIAS_FREQUENCY(period) |
422                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
423         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
424 }
425
426 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
427                 int front_porch)
428 {
429         u32 reg;
430
431         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
432         reg |= ((back_porch & 0xff) << 24)
433             | ((front_porch & 0xff) << 16)
434             | ((pulse_width & 0x3f) << 10);
435         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
436 }
437
438 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
439                 int front_porch)
440 {
441         u32 reg;
442
443         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
444         reg |= ((back_porch & 0xff) << 24)
445             | ((front_porch & 0xff) << 16)
446             | ((pulse_width & 0x3f) << 10);
447         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
448 }
449
450 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
451 {
452         u32 reg;
453         u32 reg_int;
454
455         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
456                                                 LCD_MONO_8BIT_MODE |
457                                                 LCD_MONOCHROME_MODE);
458
459         switch (cfg->p_disp_panel->panel_shade) {
460         case MONOCHROME:
461                 reg |= LCD_MONOCHROME_MODE;
462                 if (cfg->mono_8bit_mode)
463                         reg |= LCD_MONO_8BIT_MODE;
464                 break;
465         case COLOR_ACTIVE:
466                 reg |= LCD_TFT_MODE;
467                 if (cfg->tft_alt_mode)
468                         reg |= LCD_TFT_ALT_ENABLE;
469                 break;
470
471         case COLOR_PASSIVE:
472                 if (cfg->stn_565_mode)
473                         reg |= LCD_STN_565_ENABLE;
474                 break;
475
476         default:
477                 return -EINVAL;
478         }
479
480         /* enable additional interrupts here */
481         if (lcd_revision == LCD_VERSION_1) {
482                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
483         } else {
484                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
485                         LCD_V2_UNDERFLOW_INT_ENA;
486                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
487         }
488
489         lcdc_write(reg, LCD_RASTER_CTRL_REG);
490
491         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
492
493         if (cfg->sync_ctrl)
494                 reg |= LCD_SYNC_CTRL;
495         else
496                 reg &= ~LCD_SYNC_CTRL;
497
498         if (cfg->sync_edge)
499                 reg |= LCD_SYNC_EDGE;
500         else
501                 reg &= ~LCD_SYNC_EDGE;
502
503         if (cfg->invert_line_clock)
504                 reg |= LCD_INVERT_LINE_CLOCK;
505         else
506                 reg &= ~LCD_INVERT_LINE_CLOCK;
507
508         if (cfg->invert_frm_clock)
509                 reg |= LCD_INVERT_FRAME_CLOCK;
510         else
511                 reg &= ~LCD_INVERT_FRAME_CLOCK;
512
513         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
514
515         return 0;
516 }
517
518 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
519                 u32 bpp, u32 raster_order)
520 {
521         u32 reg;
522
523         if (bpp > 16 && lcd_revision == LCD_VERSION_1)
524                 return -EINVAL;
525
526         /* Set the Panel Width */
527         /* Pixels per line = (PPL + 1)*16 */
528         if (lcd_revision == LCD_VERSION_1) {
529                 /*
530                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
531                  * pixels.
532                  */
533                 width &= 0x3f0;
534         } else {
535                 /*
536                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
537                  * pixels.
538                  */
539                 width &= 0x7f0;
540         }
541
542         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
543         reg &= 0xfffffc00;
544         if (lcd_revision == LCD_VERSION_1) {
545                 reg |= ((width >> 4) - 1) << 4;
546         } else {
547                 width = (width >> 4) - 1;
548                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
549         }
550         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
551
552         /* Set the Panel Height */
553         /* Set bits 9:0 of Lines Per Pixel */
554         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
555         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
556         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
557
558         /* Set bit 10 of Lines Per Pixel */
559         if (lcd_revision == LCD_VERSION_2) {
560                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
561                 reg |= ((height - 1) & 0x400) << 16;
562                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
563         }
564
565         /* Set the Raster Order of the Frame Buffer */
566         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
567         if (raster_order)
568                 reg |= LCD_RASTER_ORDER;
569
570         par->palette_sz = 16 * 2;
571
572         switch (bpp) {
573         case 1:
574         case 2:
575         case 4:
576         case 16:
577                 break;
578         case 24:
579                 reg |= LCD_V2_TFT_24BPP_MODE;
580         case 32:
581                 reg |= LCD_V2_TFT_24BPP_UNPACK;
582                 break;
583
584         case 8:
585                 par->palette_sz = 256 * 2;
586                 break;
587
588         default:
589                 return -EINVAL;
590         }
591
592         lcdc_write(reg, LCD_RASTER_CTRL_REG);
593
594         return 0;
595 }
596
597 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
598 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
599                               unsigned blue, unsigned transp,
600                               struct fb_info *info)
601 {
602         struct da8xx_fb_par *par = info->par;
603         unsigned short *palette = (unsigned short *) par->v_palette_base;
604         u_short pal;
605         int update_hw = 0;
606
607         if (regno > 255)
608                 return 1;
609
610         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
611                 return 1;
612
613         if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
614                 return -EINVAL;
615
616         switch (info->fix.visual) {
617         case FB_VISUAL_TRUECOLOR:
618                 red = CNVT_TOHW(red, info->var.red.length);
619                 green = CNVT_TOHW(green, info->var.green.length);
620                 blue = CNVT_TOHW(blue, info->var.blue.length);
621                 break;
622         case FB_VISUAL_PSEUDOCOLOR:
623                 switch (info->var.bits_per_pixel) {
624                 case 4:
625                         if (regno > 15)
626                                 return -EINVAL;
627
628                         if (info->var.grayscale) {
629                                 pal = regno;
630                         } else {
631                                 red >>= 4;
632                                 green >>= 8;
633                                 blue >>= 12;
634
635                                 pal = red & 0x0f00;
636                                 pal |= green & 0x00f0;
637                                 pal |= blue & 0x000f;
638                         }
639                         if (regno == 0)
640                                 pal |= 0x2000;
641                         palette[regno] = pal;
642                         break;
643
644                 case 8:
645                         red >>= 4;
646                         green >>= 8;
647                         blue >>= 12;
648
649                         pal = (red & 0x0f00);
650                         pal |= (green & 0x00f0);
651                         pal |= (blue & 0x000f);
652
653                         if (palette[regno] != pal) {
654                                 update_hw = 1;
655                                 palette[regno] = pal;
656                         }
657                         break;
658                 }
659                 break;
660         }
661
662         /* Truecolor has hardware independent palette */
663         if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
664                 u32 v;
665
666                 if (regno > 15)
667                         return -EINVAL;
668
669                 v = (red << info->var.red.offset) |
670                         (green << info->var.green.offset) |
671                         (blue << info->var.blue.offset);
672
673                 switch (info->var.bits_per_pixel) {
674                 case 16:
675                         ((u16 *) (info->pseudo_palette))[regno] = v;
676                         break;
677                 case 24:
678                 case 32:
679                         ((u32 *) (info->pseudo_palette))[regno] = v;
680                         break;
681                 }
682                 if (palette[0] != 0x4000) {
683                         update_hw = 1;
684                         palette[0] = 0x4000;
685                 }
686         }
687
688         /* Update the palette in the h/w as needed. */
689         if (update_hw)
690                 lcd_blit(LOAD_PALETTE, par);
691
692         return 0;
693 }
694 #undef CNVT_TOHW
695
696 static void lcd_reset(struct da8xx_fb_par *par)
697 {
698         /* Disable the Raster if previously Enabled */
699         lcd_disable_raster(false);
700
701         /* DMA has to be disabled */
702         lcdc_write(0, LCD_DMA_CTRL_REG);
703         lcdc_write(0, LCD_RASTER_CTRL_REG);
704
705         if (lcd_revision == LCD_VERSION_2) {
706                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
707                 /* Write 1 to reset */
708                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
709                 lcdc_write(0, LCD_CLK_RESET_REG);
710         }
711 }
712
713 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
714 {
715         unsigned int lcd_clk, div;
716
717         lcd_clk = clk_get_rate(par->lcdc_clk);
718         div = lcd_clk / par->pxl_clk;
719
720         /* Configure the LCD clock divisor. */
721         lcdc_write(LCD_CLK_DIVISOR(div) |
722                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
723
724         if (lcd_revision == LCD_VERSION_2)
725                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
726                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
727
728 }
729
730 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
731                 struct da8xx_panel *panel)
732 {
733         u32 bpp;
734         int ret = 0;
735
736         lcd_reset(par);
737
738         /* Calculate the divider */
739         lcd_calc_clk_divider(par);
740
741         if (panel->invert_pxl_clk)
742                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
743                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
744         else
745                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
746                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
747
748         /* Configure the DMA burst size and fifo threshold. */
749         ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
750         if (ret < 0)
751                 return ret;
752
753         /* Configure the AC bias properties. */
754         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
755
756         /* Configure the vertical and horizontal sync properties. */
757         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
758         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
759
760         /* Configure for disply */
761         ret = lcd_cfg_display(cfg);
762         if (ret < 0)
763                 return ret;
764
765         if (QVGA != cfg->p_disp_panel->panel_type)
766                 return -EINVAL;
767
768         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
769             cfg->bpp >= cfg->p_disp_panel->min_bpp)
770                 bpp = cfg->bpp;
771         else
772                 bpp = cfg->p_disp_panel->max_bpp;
773         if (bpp == 12)
774                 bpp = 16;
775         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
776                                 (unsigned int)panel->height, bpp,
777                                 cfg->raster_order);
778         if (ret < 0)
779                 return ret;
780
781         /* Configure FDD */
782         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
783                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
784
785         return 0;
786 }
787
788 /* IRQ handler for version 2 of LCDC */
789 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
790 {
791         struct da8xx_fb_par *par = arg;
792         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
793
794         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
795                 lcd_disable_raster(false);
796                 lcdc_write(stat, LCD_MASKED_STAT_REG);
797                 lcd_enable_raster();
798         } else if (stat & LCD_PL_LOAD_DONE) {
799                 /*
800                  * Must disable raster before changing state of any control bit.
801                  * And also must be disabled before clearing the PL loading
802                  * interrupt via the following write to the status register. If
803                  * this is done after then one gets multiple PL done interrupts.
804                  */
805                 lcd_disable_raster(false);
806
807                 lcdc_write(stat, LCD_MASKED_STAT_REG);
808
809                 /* Disable PL completion interrupt */
810                 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
811
812                 /* Setup and start data loading mode */
813                 lcd_blit(LOAD_DATA, par);
814         } else {
815                 lcdc_write(stat, LCD_MASKED_STAT_REG);
816
817                 if (stat & LCD_END_OF_FRAME0) {
818                         par->which_dma_channel_done = 0;
819                         lcdc_write(par->dma_start,
820                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
821                         lcdc_write(par->dma_end,
822                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
823                         par->vsync_flag = 1;
824                         wake_up_interruptible(&par->vsync_wait);
825                 }
826
827                 if (stat & LCD_END_OF_FRAME1) {
828                         par->which_dma_channel_done = 1;
829                         lcdc_write(par->dma_start,
830                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
831                         lcdc_write(par->dma_end,
832                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
833                         par->vsync_flag = 1;
834                         wake_up_interruptible(&par->vsync_wait);
835                 }
836
837                 /* Set only when controller is disabled and at the end of
838                  * active frame
839                  */
840                 if (stat & BIT(0)) {
841                         frame_done_flag = 1;
842                         wake_up_interruptible(&frame_done_wq);
843                 }
844         }
845
846         lcdc_write(0, LCD_END_OF_INT_IND_REG);
847         return IRQ_HANDLED;
848 }
849
850 /* IRQ handler for version 1 LCDC */
851 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
852 {
853         struct da8xx_fb_par *par = arg;
854         u32 stat = lcdc_read(LCD_STAT_REG);
855         u32 reg_ras;
856
857         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
858                 lcd_disable_raster(false);
859                 lcdc_write(stat, LCD_STAT_REG);
860                 lcd_enable_raster();
861         } else if (stat & LCD_PL_LOAD_DONE) {
862                 /*
863                  * Must disable raster before changing state of any control bit.
864                  * And also must be disabled before clearing the PL loading
865                  * interrupt via the following write to the status register. If
866                  * this is done after then one gets multiple PL done interrupts.
867                  */
868                 lcd_disable_raster(false);
869
870                 lcdc_write(stat, LCD_STAT_REG);
871
872                 /* Disable PL completion inerrupt */
873                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
874                 reg_ras &= ~LCD_V1_PL_INT_ENA;
875                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
876
877                 /* Setup and start data loading mode */
878                 lcd_blit(LOAD_DATA, par);
879         } else {
880                 lcdc_write(stat, LCD_STAT_REG);
881
882                 if (stat & LCD_END_OF_FRAME0) {
883                         par->which_dma_channel_done = 0;
884                         lcdc_write(par->dma_start,
885                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
886                         lcdc_write(par->dma_end,
887                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
888                         par->vsync_flag = 1;
889                         wake_up_interruptible(&par->vsync_wait);
890                 }
891
892                 if (stat & LCD_END_OF_FRAME1) {
893                         par->which_dma_channel_done = 1;
894                         lcdc_write(par->dma_start,
895                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
896                         lcdc_write(par->dma_end,
897                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
898                         par->vsync_flag = 1;
899                         wake_up_interruptible(&par->vsync_wait);
900                 }
901         }
902
903         return IRQ_HANDLED;
904 }
905
906 static int fb_check_var(struct fb_var_screeninfo *var,
907                         struct fb_info *info)
908 {
909         int err = 0;
910
911         if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
912                 return -EINVAL;
913
914         switch (var->bits_per_pixel) {
915         case 1:
916         case 8:
917                 var->red.offset = 0;
918                 var->red.length = 8;
919                 var->green.offset = 0;
920                 var->green.length = 8;
921                 var->blue.offset = 0;
922                 var->blue.length = 8;
923                 var->transp.offset = 0;
924                 var->transp.length = 0;
925                 var->nonstd = 0;
926                 break;
927         case 4:
928                 var->red.offset = 0;
929                 var->red.length = 4;
930                 var->green.offset = 0;
931                 var->green.length = 4;
932                 var->blue.offset = 0;
933                 var->blue.length = 4;
934                 var->transp.offset = 0;
935                 var->transp.length = 0;
936                 var->nonstd = FB_NONSTD_REV_PIX_IN_B;
937                 break;
938         case 16:                /* RGB 565 */
939                 var->red.offset = 11;
940                 var->red.length = 5;
941                 var->green.offset = 5;
942                 var->green.length = 6;
943                 var->blue.offset = 0;
944                 var->blue.length = 5;
945                 var->transp.offset = 0;
946                 var->transp.length = 0;
947                 var->nonstd = 0;
948                 break;
949         case 24:
950                 var->red.offset = 16;
951                 var->red.length = 8;
952                 var->green.offset = 8;
953                 var->green.length = 8;
954                 var->blue.offset = 0;
955                 var->blue.length = 8;
956                 var->nonstd = 0;
957                 break;
958         case 32:
959                 var->transp.offset = 24;
960                 var->transp.length = 8;
961                 var->red.offset = 16;
962                 var->red.length = 8;
963                 var->green.offset = 8;
964                 var->green.length = 8;
965                 var->blue.offset = 0;
966                 var->blue.length = 8;
967                 var->nonstd = 0;
968                 break;
969         default:
970                 err = -EINVAL;
971         }
972
973         var->red.msb_right = 0;
974         var->green.msb_right = 0;
975         var->blue.msb_right = 0;
976         var->transp.msb_right = 0;
977         return err;
978 }
979
980 #ifdef CONFIG_CPU_FREQ
981 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
982                                      unsigned long val, void *data)
983 {
984         struct da8xx_fb_par *par;
985
986         par = container_of(nb, struct da8xx_fb_par, freq_transition);
987         if (val == CPUFREQ_POSTCHANGE) {
988                 if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
989                         par->lcd_fck_rate = clk_get_rate(par->lcdc_clk);
990                         lcd_disable_raster(true);
991                         lcd_calc_clk_divider(par);
992                         if (par->blank == FB_BLANK_UNBLANK)
993                                 lcd_enable_raster();
994                 }
995         }
996
997         return 0;
998 }
999
1000 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1001 {
1002         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1003
1004         return cpufreq_register_notifier(&par->freq_transition,
1005                                          CPUFREQ_TRANSITION_NOTIFIER);
1006 }
1007
1008 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1009 {
1010         cpufreq_unregister_notifier(&par->freq_transition,
1011                                     CPUFREQ_TRANSITION_NOTIFIER);
1012 }
1013 #endif
1014
1015 static int __devexit fb_remove(struct platform_device *dev)
1016 {
1017         struct fb_info *info = dev_get_drvdata(&dev->dev);
1018
1019         if (info) {
1020                 struct da8xx_fb_par *par = info->par;
1021
1022 #ifdef CONFIG_CPU_FREQ
1023                 lcd_da8xx_cpufreq_deregister(par);
1024 #endif
1025                 if (par->panel_power_ctrl)
1026                         par->panel_power_ctrl(0);
1027
1028                 lcd_disable_raster(true);
1029                 lcdc_write(0, LCD_RASTER_CTRL_REG);
1030
1031                 /* disable DMA  */
1032                 lcdc_write(0, LCD_DMA_CTRL_REG);
1033
1034                 unregister_framebuffer(info);
1035                 fb_dealloc_cmap(&info->cmap);
1036                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1037                                   par->p_palette_base);
1038                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1039                                   par->vram_phys);
1040                 free_irq(par->irq, par);
1041                 pm_runtime_put_sync(&dev->dev);
1042                 pm_runtime_disable(&dev->dev);
1043                 framebuffer_release(info);
1044                 iounmap(da8xx_fb_reg_base);
1045                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
1046
1047         }
1048         return 0;
1049 }
1050
1051 /*
1052  * Function to wait for vertical sync which for this LCD peripheral
1053  * translates into waiting for the current raster frame to complete.
1054  */
1055 static int fb_wait_for_vsync(struct fb_info *info)
1056 {
1057         struct da8xx_fb_par *par = info->par;
1058         int ret;
1059
1060         /*
1061          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1062          * race condition here where the ISR could have occurred just before or
1063          * just after this set. But since we are just coarsely waiting for
1064          * a frame to complete then that's OK. i.e. if the frame completed
1065          * just before this code executed then we have to wait another full
1066          * frame time but there is no way to avoid such a situation. On the
1067          * other hand if the frame completed just after then we don't need
1068          * to wait long at all. Either way we are guaranteed to return to the
1069          * user immediately after a frame completion which is all that is
1070          * required.
1071          */
1072         par->vsync_flag = 0;
1073         ret = wait_event_interruptible_timeout(par->vsync_wait,
1074                                                par->vsync_flag != 0,
1075                                                par->vsync_timeout);
1076         if (ret < 0)
1077                 return ret;
1078         if (ret == 0)
1079                 return -ETIMEDOUT;
1080
1081         return 0;
1082 }
1083
1084 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1085                           unsigned long arg)
1086 {
1087         struct lcd_sync_arg sync_arg;
1088
1089         switch (cmd) {
1090         case FBIOGET_CONTRAST:
1091         case FBIOPUT_CONTRAST:
1092         case FBIGET_BRIGHTNESS:
1093         case FBIPUT_BRIGHTNESS:
1094         case FBIGET_COLOR:
1095         case FBIPUT_COLOR:
1096                 return -ENOTTY;
1097         case FBIPUT_HSYNC:
1098                 if (copy_from_user(&sync_arg, (char *)arg,
1099                                 sizeof(struct lcd_sync_arg)))
1100                         return -EFAULT;
1101                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1102                                         sync_arg.pulse_width,
1103                                         sync_arg.front_porch);
1104                 break;
1105         case FBIPUT_VSYNC:
1106                 if (copy_from_user(&sync_arg, (char *)arg,
1107                                 sizeof(struct lcd_sync_arg)))
1108                         return -EFAULT;
1109                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1110                                         sync_arg.pulse_width,
1111                                         sync_arg.front_porch);
1112                 break;
1113         case FBIO_WAITFORVSYNC:
1114                 return fb_wait_for_vsync(info);
1115         default:
1116                 return -EINVAL;
1117         }
1118         return 0;
1119 }
1120
1121 static int cfb_blank(int blank, struct fb_info *info)
1122 {
1123         struct da8xx_fb_par *par = info->par;
1124         int ret = 0;
1125
1126         if (par->blank == blank)
1127                 return 0;
1128
1129         par->blank = blank;
1130         switch (blank) {
1131         case FB_BLANK_UNBLANK:
1132                 lcd_enable_raster();
1133
1134                 if (par->panel_power_ctrl)
1135                         par->panel_power_ctrl(1);
1136                 break;
1137         case FB_BLANK_NORMAL:
1138         case FB_BLANK_VSYNC_SUSPEND:
1139         case FB_BLANK_HSYNC_SUSPEND:
1140         case FB_BLANK_POWERDOWN:
1141                 if (par->panel_power_ctrl)
1142                         par->panel_power_ctrl(0);
1143
1144                 lcd_disable_raster(true);
1145                 break;
1146         default:
1147                 ret = -EINVAL;
1148         }
1149
1150         return ret;
1151 }
1152
1153 /*
1154  * Set new x,y offsets in the virtual display for the visible area and switch
1155  * to the new mode.
1156  */
1157 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1158                              struct fb_info *fbi)
1159 {
1160         int ret = 0;
1161         struct fb_var_screeninfo new_var;
1162         struct da8xx_fb_par         *par = fbi->par;
1163         struct fb_fix_screeninfo    *fix = &fbi->fix;
1164         unsigned int end;
1165         unsigned int start;
1166         unsigned long irq_flags;
1167
1168         if (var->xoffset != fbi->var.xoffset ||
1169                         var->yoffset != fbi->var.yoffset) {
1170                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1171                 new_var.xoffset = var->xoffset;
1172                 new_var.yoffset = var->yoffset;
1173                 if (fb_check_var(&new_var, fbi))
1174                         ret = -EINVAL;
1175                 else {
1176                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1177
1178                         start   = fix->smem_start +
1179                                 new_var.yoffset * fix->line_length +
1180                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1181                         end     = start + fbi->var.yres * fix->line_length - 1;
1182                         par->dma_start  = start;
1183                         par->dma_end    = end;
1184                         spin_lock_irqsave(&par->lock_for_chan_update,
1185                                         irq_flags);
1186                         if (par->which_dma_channel_done == 0) {
1187                                 lcdc_write(par->dma_start,
1188                                            LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1189                                 lcdc_write(par->dma_end,
1190                                            LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1191                         } else if (par->which_dma_channel_done == 1) {
1192                                 lcdc_write(par->dma_start,
1193                                            LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1194                                 lcdc_write(par->dma_end,
1195                                            LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1196                         }
1197                         spin_unlock_irqrestore(&par->lock_for_chan_update,
1198                                         irq_flags);
1199                 }
1200         }
1201
1202         return ret;
1203 }
1204
1205 static struct fb_ops da8xx_fb_ops = {
1206         .owner = THIS_MODULE,
1207         .fb_check_var = fb_check_var,
1208         .fb_setcolreg = fb_setcolreg,
1209         .fb_pan_display = da8xx_pan_display,
1210         .fb_ioctl = fb_ioctl,
1211         .fb_fillrect = cfb_fillrect,
1212         .fb_copyarea = cfb_copyarea,
1213         .fb_imageblit = cfb_imageblit,
1214         .fb_blank = cfb_blank,
1215 };
1216
1217 /* Calculate and return pixel clock period in pico seconds */
1218 static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
1219 {
1220         unsigned int lcd_clk, div;
1221         unsigned int configured_pix_clk;
1222         unsigned long long pix_clk_period_picosec = 1000000000000ULL;
1223
1224         lcd_clk = clk_get_rate(par->lcdc_clk);
1225         div = lcd_clk / par->pxl_clk;
1226         configured_pix_clk = (lcd_clk / div);
1227
1228         do_div(pix_clk_period_picosec, configured_pix_clk);
1229
1230         return pix_clk_period_picosec;
1231 }
1232
1233 static int __devinit fb_probe(struct platform_device *device)
1234 {
1235         struct da8xx_lcdc_platform_data *fb_pdata =
1236                                                 device->dev.platform_data;
1237         struct lcd_ctrl_config *lcd_cfg;
1238         struct da8xx_panel *lcdc_info;
1239         struct fb_info *da8xx_fb_info;
1240         struct clk *fb_clk = NULL;
1241         struct da8xx_fb_par *par;
1242         resource_size_t len;
1243         int ret, i;
1244         unsigned long ulcm;
1245
1246         if (fb_pdata == NULL) {
1247                 dev_err(&device->dev, "Can not get platform data\n");
1248                 return -ENOENT;
1249         }
1250
1251         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1252         if (!lcdc_regs) {
1253                 dev_err(&device->dev,
1254                         "Can not get memory resource for LCD controller\n");
1255                 return -ENOENT;
1256         }
1257
1258         len = resource_size(lcdc_regs);
1259
1260         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1261         if (!lcdc_regs)
1262                 return -EBUSY;
1263
1264         da8xx_fb_reg_base = ioremap(lcdc_regs->start, len);
1265         if (!da8xx_fb_reg_base) {
1266                 ret = -EBUSY;
1267                 goto err_request_mem;
1268         }
1269
1270         fb_clk = clk_get(&device->dev, NULL);
1271         if (IS_ERR(fb_clk)) {
1272                 dev_err(&device->dev, "Can not get device clock\n");
1273                 ret = -ENODEV;
1274                 goto err_ioremap;
1275         }
1276
1277         pm_runtime_enable(&device->dev);
1278         pm_runtime_get_sync(&device->dev);
1279
1280         /* Determine LCD IP Version */
1281         switch (lcdc_read(LCD_PID_REG)) {
1282         case 0x4C100102:
1283                 lcd_revision = LCD_VERSION_1;
1284                 break;
1285         case 0x4F200800:
1286                 lcd_revision = LCD_VERSION_2;
1287                 break;
1288         default:
1289                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1290                                 "defaulting to LCD revision 1\n",
1291                                 lcdc_read(LCD_PID_REG));
1292                 lcd_revision = LCD_VERSION_1;
1293                 break;
1294         }
1295
1296         for (i = 0, lcdc_info = known_lcd_panels;
1297                 i < ARRAY_SIZE(known_lcd_panels);
1298                 i++, lcdc_info++) {
1299                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1300                         break;
1301         }
1302
1303         if (i == ARRAY_SIZE(known_lcd_panels)) {
1304                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1305                 ret = -ENODEV;
1306                 goto err_pm_runtime_disable;
1307         } else
1308                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1309                                         fb_pdata->type);
1310
1311         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1312
1313         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1314                                         &device->dev);
1315         if (!da8xx_fb_info) {
1316                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1317                 ret = -ENOMEM;
1318                 goto err_pm_runtime_disable;
1319         }
1320
1321         par = da8xx_fb_info->par;
1322         par->lcdc_clk = fb_clk;
1323 #ifdef CONFIG_CPU_FREQ
1324         par->lcd_fck_rate = clk_get_rate(fb_clk);
1325 #endif
1326         par->pxl_clk = lcdc_info->pxl_clk;
1327         if (fb_pdata->panel_power_ctrl) {
1328                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1329                 par->panel_power_ctrl(1);
1330         }
1331
1332         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1333                 dev_err(&device->dev, "lcd_init failed\n");
1334                 ret = -EFAULT;
1335                 goto err_release_fb;
1336         }
1337
1338         /* allocate frame buffer */
1339         par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1340         ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE);
1341         par->vram_size = roundup(par->vram_size/8, ulcm);
1342         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1343
1344         par->vram_virt = dma_alloc_coherent(NULL,
1345                                             par->vram_size,
1346                                             (resource_size_t *) &par->vram_phys,
1347                                             GFP_KERNEL | GFP_DMA);
1348         if (!par->vram_virt) {
1349                 dev_err(&device->dev,
1350                         "GLCD: kmalloc for frame buffer failed\n");
1351                 ret = -EINVAL;
1352                 goto err_release_fb;
1353         }
1354
1355         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1356         da8xx_fb_fix.smem_start    = par->vram_phys;
1357         da8xx_fb_fix.smem_len      = par->vram_size;
1358         da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
1359
1360         par->dma_start = par->vram_phys;
1361         par->dma_end   = par->dma_start + lcdc_info->height *
1362                 da8xx_fb_fix.line_length - 1;
1363
1364         /* allocate palette buffer */
1365         par->v_palette_base = dma_alloc_coherent(NULL,
1366                                                PALETTE_SIZE,
1367                                                (resource_size_t *)
1368                                                &par->p_palette_base,
1369                                                GFP_KERNEL | GFP_DMA);
1370         if (!par->v_palette_base) {
1371                 dev_err(&device->dev,
1372                         "GLCD: kmalloc for palette buffer failed\n");
1373                 ret = -EINVAL;
1374                 goto err_release_fb_mem;
1375         }
1376         memset(par->v_palette_base, 0, PALETTE_SIZE);
1377
1378         par->irq = platform_get_irq(device, 0);
1379         if (par->irq < 0) {
1380                 ret = -ENOENT;
1381                 goto err_release_pl_mem;
1382         }
1383
1384         /* Initialize par */
1385         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1386
1387         da8xx_fb_var.xres = lcdc_info->width;
1388         da8xx_fb_var.xres_virtual = lcdc_info->width;
1389
1390         da8xx_fb_var.yres         = lcdc_info->height;
1391         da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1392
1393         da8xx_fb_var.grayscale =
1394             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1395         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1396
1397         da8xx_fb_var.hsync_len = lcdc_info->hsw;
1398         da8xx_fb_var.vsync_len = lcdc_info->vsw;
1399         da8xx_fb_var.right_margin = lcdc_info->hfp;
1400         da8xx_fb_var.left_margin  = lcdc_info->hbp;
1401         da8xx_fb_var.lower_margin = lcdc_info->vfp;
1402         da8xx_fb_var.upper_margin = lcdc_info->vbp;
1403         da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
1404
1405         /* Initialize fbinfo */
1406         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1407         da8xx_fb_info->fix = da8xx_fb_fix;
1408         da8xx_fb_info->var = da8xx_fb_var;
1409         da8xx_fb_info->fbops = &da8xx_fb_ops;
1410         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1411         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1412                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1413
1414         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1415         if (ret)
1416                 goto err_release_pl_mem;
1417         da8xx_fb_info->cmap.len = par->palette_sz;
1418
1419         /* initialize var_screeninfo */
1420         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1421         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1422
1423         dev_set_drvdata(&device->dev, da8xx_fb_info);
1424
1425         /* initialize the vsync wait queue */
1426         init_waitqueue_head(&par->vsync_wait);
1427         par->vsync_timeout = HZ / 5;
1428         par->which_dma_channel_done = -1;
1429         spin_lock_init(&par->lock_for_chan_update);
1430
1431         /* Register the Frame Buffer  */
1432         if (register_framebuffer(da8xx_fb_info) < 0) {
1433                 dev_err(&device->dev,
1434                         "GLCD: Frame Buffer Registration Failed!\n");
1435                 ret = -EINVAL;
1436                 goto err_dealloc_cmap;
1437         }
1438
1439 #ifdef CONFIG_CPU_FREQ
1440         ret = lcd_da8xx_cpufreq_register(par);
1441         if (ret) {
1442                 dev_err(&device->dev, "failed to register cpufreq\n");
1443                 goto err_cpu_freq;
1444         }
1445 #endif
1446
1447         if (lcd_revision == LCD_VERSION_1)
1448                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1449         else {
1450                 init_waitqueue_head(&frame_done_wq);
1451                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1452         }
1453
1454         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1455                         DRIVER_NAME, par);
1456         if (ret)
1457                 goto irq_freq;
1458         return 0;
1459
1460 irq_freq:
1461 #ifdef CONFIG_CPU_FREQ
1462         lcd_da8xx_cpufreq_deregister(par);
1463 err_cpu_freq:
1464 #endif
1465         unregister_framebuffer(da8xx_fb_info);
1466
1467 err_dealloc_cmap:
1468         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1469
1470 err_release_pl_mem:
1471         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1472                           par->p_palette_base);
1473
1474 err_release_fb_mem:
1475         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1476
1477 err_release_fb:
1478         framebuffer_release(da8xx_fb_info);
1479
1480 err_pm_runtime_disable:
1481         pm_runtime_put_sync(&device->dev);
1482         pm_runtime_disable(&device->dev);
1483
1484 err_ioremap:
1485         iounmap(da8xx_fb_reg_base);
1486
1487 err_request_mem:
1488         release_mem_region(lcdc_regs->start, len);
1489
1490         return ret;
1491 }
1492
1493 #ifdef CONFIG_PM
1494 struct lcdc_context {
1495         u32 clk_enable;
1496         u32 ctrl;
1497         u32 dma_ctrl;
1498         u32 raster_timing_0;
1499         u32 raster_timing_1;
1500         u32 raster_timing_2;
1501         u32 int_enable_set;
1502         u32 dma_frm_buf_base_addr_0;
1503         u32 dma_frm_buf_ceiling_addr_0;
1504         u32 dma_frm_buf_base_addr_1;
1505         u32 dma_frm_buf_ceiling_addr_1;
1506         u32 raster_ctrl;
1507 } reg_context;
1508
1509 static void lcd_context_save(void)
1510 {
1511         if (lcd_revision == LCD_VERSION_2) {
1512                 reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1513                 reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1514         }
1515
1516         reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1517         reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1518         reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1519         reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1520         reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1521         reg_context.dma_frm_buf_base_addr_0 =
1522                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1523         reg_context.dma_frm_buf_ceiling_addr_0 =
1524                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1525         reg_context.dma_frm_buf_base_addr_1 =
1526                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1527         reg_context.dma_frm_buf_ceiling_addr_1 =
1528                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1529         reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1530         return;
1531 }
1532
1533 static void lcd_context_restore(void)
1534 {
1535         if (lcd_revision == LCD_VERSION_2) {
1536                 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1537                 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1538         }
1539
1540         lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1541         lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1542         lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1543         lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1544         lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1545         lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1546                         LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1547         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1548                         LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1549         lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1550                         LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1551         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1552                         LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1553         lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1554         return;
1555 }
1556
1557 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1558 {
1559         struct fb_info *info = platform_get_drvdata(dev);
1560         struct da8xx_fb_par *par = info->par;
1561
1562         console_lock();
1563         if (par->panel_power_ctrl)
1564                 par->panel_power_ctrl(0);
1565
1566         fb_set_suspend(info, 1);
1567         lcd_disable_raster(true);
1568         lcd_context_save();
1569         pm_runtime_put_sync(&dev->dev);
1570         console_unlock();
1571
1572         return 0;
1573 }
1574 static int fb_resume(struct platform_device *dev)
1575 {
1576         struct fb_info *info = platform_get_drvdata(dev);
1577         struct da8xx_fb_par *par = info->par;
1578
1579         console_lock();
1580         pm_runtime_get_sync(&dev->dev);
1581         lcd_context_restore();
1582         if (par->blank == FB_BLANK_UNBLANK) {
1583                 lcd_enable_raster();
1584
1585                 if (par->panel_power_ctrl)
1586                         par->panel_power_ctrl(1);
1587         }
1588
1589         fb_set_suspend(info, 0);
1590         console_unlock();
1591
1592         return 0;
1593 }
1594 #else
1595 #define fb_suspend NULL
1596 #define fb_resume NULL
1597 #endif
1598
1599 static struct platform_driver da8xx_fb_driver = {
1600         .probe = fb_probe,
1601         .remove = __devexit_p(fb_remove),
1602         .suspend = fb_suspend,
1603         .resume = fb_resume,
1604         .driver = {
1605                    .name = DRIVER_NAME,
1606                    .owner = THIS_MODULE,
1607                    },
1608 };
1609
1610 static int __init da8xx_fb_init(void)
1611 {
1612         return platform_driver_register(&da8xx_fb_driver);
1613 }
1614
1615 static void __exit da8xx_fb_cleanup(void)
1616 {
1617         platform_driver_unregister(&da8xx_fb_driver);
1618 }
1619
1620 module_init(da8xx_fb_init);
1621 module_exit(da8xx_fb_cleanup);
1622
1623 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1624 MODULE_AUTHOR("Texas Instruments");
1625 MODULE_LICENSE("GPL");