0f3a64baecc940adff2352e2b840eae8efd45aac
[~shefty/rdma-dev.git] / drivers / video / exynos / exynos_dp_core.c
1 /*
2  * Samsung SoC DP (Display Port) interface driver.
3  *
4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5  * Author: Jingoo Han <jg1.han@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  */
12
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21
22 #include <video/exynos_dp.h>
23
24 #include "exynos_dp_core.h"
25
26 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
27 {
28         exynos_dp_reset(dp);
29
30         exynos_dp_swreset(dp);
31
32         /* SW defined function Normal operation */
33         exynos_dp_enable_sw_function(dp);
34
35         exynos_dp_config_interrupt(dp);
36         exynos_dp_init_analog_func(dp);
37
38         exynos_dp_init_hpd(dp);
39         exynos_dp_init_aux(dp);
40
41         return 0;
42 }
43
44 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
45 {
46         int timeout_loop = 0;
47
48         exynos_dp_init_hpd(dp);
49
50         udelay(200);
51
52         while (exynos_dp_get_plug_in_status(dp) != 0) {
53                 timeout_loop++;
54                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
55                         dev_err(dp->dev, "failed to get hpd plug status\n");
56                         return -ETIMEDOUT;
57                 }
58                 udelay(10);
59         }
60
61         return 0;
62 }
63
64 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
65 {
66         int i;
67         unsigned char sum = 0;
68
69         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
70                 sum = sum + edid_data[i];
71
72         return sum;
73 }
74
75 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
76 {
77         unsigned char edid[EDID_BLOCK_LENGTH * 2];
78         unsigned int extend_block = 0;
79         unsigned char sum;
80         unsigned char test_vector;
81         int retval;
82
83         /*
84          * EDID device address is 0x50.
85          * However, if necessary, you must have set upper address
86          * into E-EDID in I2C device, 0x30.
87          */
88
89         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
90         exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
91                                 EDID_EXTENSION_FLAG,
92                                 &extend_block);
93
94         if (extend_block > 0) {
95                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
96
97                 /* Read EDID data */
98                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
99                                                 EDID_HEADER_PATTERN,
100                                                 EDID_BLOCK_LENGTH,
101                                                 &edid[EDID_HEADER_PATTERN]);
102                 if (retval != 0) {
103                         dev_err(dp->dev, "EDID Read failed!\n");
104                         return -EIO;
105                 }
106                 sum = exynos_dp_calc_edid_check_sum(edid);
107                 if (sum != 0) {
108                         dev_err(dp->dev, "EDID bad checksum!\n");
109                         return -EIO;
110                 }
111
112                 /* Read additional EDID data */
113                 retval = exynos_dp_read_bytes_from_i2c(dp,
114                                 I2C_EDID_DEVICE_ADDR,
115                                 EDID_BLOCK_LENGTH,
116                                 EDID_BLOCK_LENGTH,
117                                 &edid[EDID_BLOCK_LENGTH]);
118                 if (retval != 0) {
119                         dev_err(dp->dev, "EDID Read failed!\n");
120                         return -EIO;
121                 }
122                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
123                 if (sum != 0) {
124                         dev_err(dp->dev, "EDID bad checksum!\n");
125                         return -EIO;
126                 }
127
128                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
129                                         &test_vector);
130                 if (test_vector & DPCD_TEST_EDID_READ) {
131                         exynos_dp_write_byte_to_dpcd(dp,
132                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
133                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
134                         exynos_dp_write_byte_to_dpcd(dp,
135                                 DPCD_ADDR_TEST_RESPONSE,
136                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
137                 }
138         } else {
139                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
140
141                 /* Read EDID data */
142                 retval = exynos_dp_read_bytes_from_i2c(dp,
143                                 I2C_EDID_DEVICE_ADDR,
144                                 EDID_HEADER_PATTERN,
145                                 EDID_BLOCK_LENGTH,
146                                 &edid[EDID_HEADER_PATTERN]);
147                 if (retval != 0) {
148                         dev_err(dp->dev, "EDID Read failed!\n");
149                         return -EIO;
150                 }
151                 sum = exynos_dp_calc_edid_check_sum(edid);
152                 if (sum != 0) {
153                         dev_err(dp->dev, "EDID bad checksum!\n");
154                         return -EIO;
155                 }
156
157                 exynos_dp_read_byte_from_dpcd(dp,
158                         DPCD_ADDR_TEST_REQUEST,
159                         &test_vector);
160                 if (test_vector & DPCD_TEST_EDID_READ) {
161                         exynos_dp_write_byte_to_dpcd(dp,
162                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
163                                 edid[EDID_CHECKSUM]);
164                         exynos_dp_write_byte_to_dpcd(dp,
165                                 DPCD_ADDR_TEST_RESPONSE,
166                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
167                 }
168         }
169
170         dev_err(dp->dev, "EDID Read success!\n");
171         return 0;
172 }
173
174 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
175 {
176         u8 buf[12];
177         int i;
178         int retval;
179
180         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
181         exynos_dp_read_bytes_from_dpcd(dp,
182                 DPCD_ADDR_DPCD_REV,
183                 12, buf);
184
185         /* Read EDID */
186         for (i = 0; i < 3; i++) {
187                 retval = exynos_dp_read_edid(dp);
188                 if (retval == 0)
189                         break;
190         }
191
192         return retval;
193 }
194
195 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
196                                                 bool enable)
197 {
198         u8 data;
199
200         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
201
202         if (enable)
203                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
204                         DPCD_ENHANCED_FRAME_EN |
205                         DPCD_LANE_COUNT_SET(data));
206         else
207                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
208                         DPCD_LANE_COUNT_SET(data));
209 }
210
211 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
212 {
213         u8 data;
214         int retval;
215
216         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
217         retval = DPCD_ENHANCED_FRAME_CAP(data);
218
219         return retval;
220 }
221
222 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
223 {
224         u8 data;
225
226         data = exynos_dp_is_enhanced_mode_available(dp);
227         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
228         exynos_dp_enable_enhanced_mode(dp, data);
229 }
230
231 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
232 {
233         exynos_dp_set_training_pattern(dp, DP_NONE);
234
235         exynos_dp_write_byte_to_dpcd(dp,
236                 DPCD_ADDR_TRAINING_PATTERN_SET,
237                 DPCD_TRAINING_PATTERN_DISABLED);
238 }
239
240 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
241                                         int pre_emphasis, int lane)
242 {
243         switch (lane) {
244         case 0:
245                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
246                 break;
247         case 1:
248                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
249                 break;
250
251         case 2:
252                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
253                 break;
254
255         case 3:
256                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
257                 break;
258         }
259 }
260
261 static void exynos_dp_link_start(struct exynos_dp_device *dp)
262 {
263         u8 buf[5];
264         int lane;
265         int lane_count;
266
267         lane_count = dp->link_train.lane_count;
268
269         dp->link_train.lt_state = CLOCK_RECOVERY;
270         dp->link_train.eq_loop = 0;
271
272         for (lane = 0; lane < lane_count; lane++)
273                 dp->link_train.cr_loop[lane] = 0;
274
275         /* Set sink to D0 (Sink Not Ready) mode. */
276         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
277                                 DPCD_SET_POWER_STATE_D0);
278
279         /* Set link rate and count as you want to establish*/
280         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
281         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
282
283         /* Setup RX configuration */
284         buf[0] = dp->link_train.link_rate;
285         buf[1] = dp->link_train.lane_count;
286         exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
287                                 2, buf);
288
289         /* Set TX pre-emphasis to minimum */
290         for (lane = 0; lane < lane_count; lane++)
291                 exynos_dp_set_lane_lane_pre_emphasis(dp,
292                         PRE_EMPHASIS_LEVEL_0, lane);
293
294         /* Set training pattern 1 */
295         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
296
297         /* Set RX training pattern */
298         buf[0] = DPCD_SCRAMBLING_DISABLED |
299                  DPCD_TRAINING_PATTERN_1;
300         exynos_dp_write_byte_to_dpcd(dp,
301                 DPCD_ADDR_TRAINING_PATTERN_SET, buf[0]);
302
303         for (lane = 0; lane < lane_count; lane++)
304                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
305                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
306         exynos_dp_write_bytes_to_dpcd(dp,
307                 DPCD_ADDR_TRAINING_LANE0_SET,
308                 lane_count, buf);
309 }
310
311 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
312 {
313         int shift = (lane & 1) * 4;
314         u8 link_value = link_status[lane>>1];
315
316         return (link_value >> shift) & 0xf;
317 }
318
319 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
320 {
321         int lane;
322         u8 lane_status;
323
324         for (lane = 0; lane < lane_count; lane++) {
325                 lane_status = exynos_dp_get_lane_status(link_status, lane);
326                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
327                         return -EINVAL;
328         }
329         return 0;
330 }
331
332 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
333 {
334         int lane;
335         u8 lane_align;
336         u8 lane_status;
337
338         lane_align = link_status[2];
339         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
340                 return -EINVAL;
341
342         for (lane = 0; lane < lane_count; lane++) {
343                 lane_status = exynos_dp_get_lane_status(link_status, lane);
344                 lane_status &= DPCD_CHANNEL_EQ_BITS;
345                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
346                         return -EINVAL;
347         }
348         return 0;
349 }
350
351 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
352                                                         int lane)
353 {
354         int shift = (lane & 1) * 4;
355         u8 link_value = adjust_request[lane>>1];
356
357         return (link_value >> shift) & 0x3;
358 }
359
360 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
361                                         u8 adjust_request[2],
362                                         int lane)
363 {
364         int shift = (lane & 1) * 4;
365         u8 link_value = adjust_request[lane>>1];
366
367         return ((link_value >> shift) & 0xc) >> 2;
368 }
369
370 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
371                                         u8 training_lane_set, int lane)
372 {
373         switch (lane) {
374         case 0:
375                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
376                 break;
377         case 1:
378                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
379                 break;
380
381         case 2:
382                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
383                 break;
384
385         case 3:
386                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
387                 break;
388         }
389 }
390
391 static unsigned int exynos_dp_get_lane_link_training(
392                                 struct exynos_dp_device *dp,
393                                 int lane)
394 {
395         u32 reg;
396
397         switch (lane) {
398         case 0:
399                 reg = exynos_dp_get_lane0_link_training(dp);
400                 break;
401         case 1:
402                 reg = exynos_dp_get_lane1_link_training(dp);
403                 break;
404         case 2:
405                 reg = exynos_dp_get_lane2_link_training(dp);
406                 break;
407         case 3:
408                 reg = exynos_dp_get_lane3_link_training(dp);
409                 break;
410         default:
411                 WARN_ON(1);
412                 return 0;
413         }
414
415         return reg;
416 }
417
418 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
419 {
420         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
421                 /* set to reduced bit rate */
422                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
423                 dev_err(dp->dev, "set to bandwidth %.2x\n",
424                         dp->link_train.link_rate);
425                 dp->link_train.lt_state = START;
426         } else {
427                 exynos_dp_training_pattern_dis(dp);
428                 /* set enhanced mode if available */
429                 exynos_dp_set_enhanced_mode(dp);
430                 dp->link_train.lt_state = FAILED;
431         }
432 }
433
434 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
435                                 u8 adjust_request[2])
436 {
437         int lane;
438         int lane_count;
439         u8 voltage_swing;
440         u8 pre_emphasis;
441         u8 training_lane;
442
443         lane_count = dp->link_train.lane_count;
444         for (lane = 0; lane < lane_count; lane++) {
445                 voltage_swing = exynos_dp_get_adjust_request_voltage(
446                                                 adjust_request, lane);
447                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
448                                                 adjust_request, lane);
449                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
450                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
451
452                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
453                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
454                         training_lane |= DPCD_MAX_SWING_REACHED;
455                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
456                 }
457                 dp->link_train.training_lane[lane] = training_lane;
458         }
459 }
460
461 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
462                                         u8 voltage_swing)
463 {
464         int lane;
465         int lane_count;
466
467         lane_count = dp->link_train.lane_count;
468         for (lane = 0; lane < lane_count; lane++) {
469                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
470                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
471                         return -EINVAL;
472         }
473         return 0;
474 }
475
476 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
477 {
478         u8 data;
479         u8 link_status[6];
480         int lane;
481         int lane_count;
482         u8 buf[5];
483
484         u8 adjust_request[2];
485         u8 voltage_swing;
486         u8 pre_emphasis;
487         u8 training_lane;
488
489         udelay(100);
490
491         exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
492                                 6, link_status);
493         lane_count = dp->link_train.lane_count;
494
495         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
496                 /* set training pattern 2 for EQ */
497                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
498
499                 adjust_request[0] = link_status[4];
500                 adjust_request[1] = link_status[5];
501
502                 exynos_dp_get_adjust_train(dp, adjust_request);
503
504                 buf[0] = DPCD_SCRAMBLING_DISABLED |
505                          DPCD_TRAINING_PATTERN_2;
506                 exynos_dp_write_byte_to_dpcd(dp,
507                         DPCD_ADDR_TRAINING_PATTERN_SET,
508                         buf[0]);
509
510                 for (lane = 0; lane < lane_count; lane++) {
511                         exynos_dp_set_lane_link_training(dp,
512                                 dp->link_train.training_lane[lane],
513                                 lane);
514                         buf[lane] = dp->link_train.training_lane[lane];
515                         exynos_dp_write_byte_to_dpcd(dp,
516                                 DPCD_ADDR_TRAINING_LANE0_SET + lane,
517                                 buf[lane]);
518                 }
519                 dp->link_train.lt_state = EQUALIZER_TRAINING;
520         } else {
521                 exynos_dp_read_byte_from_dpcd(dp,
522                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
523                         &data);
524                 adjust_request[0] = data;
525
526                 exynos_dp_read_byte_from_dpcd(dp,
527                         DPCD_ADDR_ADJUST_REQUEST_LANE2_3,
528                         &data);
529                 adjust_request[1] = data;
530
531                 for (lane = 0; lane < lane_count; lane++) {
532                         training_lane = exynos_dp_get_lane_link_training(
533                                                         dp, lane);
534                         voltage_swing = exynos_dp_get_adjust_request_voltage(
535                                                         adjust_request, lane);
536                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
537                                                         adjust_request, lane);
538                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
539                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
540                                 dp->link_train.cr_loop[lane]++;
541                         dp->link_train.training_lane[lane] = training_lane;
542                 }
543
544                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
545                         exynos_dp_reduce_link_rate(dp);
546                 } else {
547                         exynos_dp_get_adjust_train(dp, adjust_request);
548
549                         for (lane = 0; lane < lane_count; lane++) {
550                                 exynos_dp_set_lane_link_training(dp,
551                                         dp->link_train.training_lane[lane],
552                                         lane);
553                                 buf[lane] = dp->link_train.training_lane[lane];
554                                 exynos_dp_write_byte_to_dpcd(dp,
555                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
556                                         buf[lane]);
557                         }
558                 }
559         }
560
561         return 0;
562 }
563
564 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
565 {
566         u8 link_status[6];
567         int lane;
568         int lane_count;
569         u8 buf[5];
570         u32 reg;
571
572         u8 adjust_request[2];
573
574         udelay(400);
575
576         exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
577                                 6, link_status);
578         lane_count = dp->link_train.lane_count;
579
580         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
581                 adjust_request[0] = link_status[4];
582                 adjust_request[1] = link_status[5];
583
584                 if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
585                         /* traing pattern Set to Normal */
586                         exynos_dp_training_pattern_dis(dp);
587
588                         dev_info(dp->dev, "Link Training success!\n");
589
590                         exynos_dp_get_link_bandwidth(dp, &reg);
591                         dp->link_train.link_rate = reg;
592                         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
593                                 dp->link_train.link_rate);
594
595                         exynos_dp_get_lane_count(dp, &reg);
596                         dp->link_train.lane_count = reg;
597                         dev_dbg(dp->dev, "final lane count = %.2x\n",
598                                 dp->link_train.lane_count);
599                         /* set enhanced mode if available */
600                         exynos_dp_set_enhanced_mode(dp);
601
602                         dp->link_train.lt_state = FINISHED;
603                 } else {
604                         /* not all locked */
605                         dp->link_train.eq_loop++;
606
607                         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
608                                 exynos_dp_reduce_link_rate(dp);
609                         } else {
610                                 exynos_dp_get_adjust_train(dp, adjust_request);
611
612                                 for (lane = 0; lane < lane_count; lane++) {
613                                         exynos_dp_set_lane_link_training(dp,
614                                                 dp->link_train.training_lane[lane],
615                                                 lane);
616                                         buf[lane] = dp->link_train.training_lane[lane];
617                                         exynos_dp_write_byte_to_dpcd(dp,
618                                                 DPCD_ADDR_TRAINING_LANE0_SET + lane,
619                                                 buf[lane]);
620                                 }
621                         }
622                 }
623         } else {
624                 exynos_dp_reduce_link_rate(dp);
625         }
626
627         return 0;
628 }
629
630 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
631                         u8 *bandwidth)
632 {
633         u8 data;
634
635         /*
636          * For DP rev.1.1, Maximum link rate of Main Link lanes
637          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
638          */
639         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
640         *bandwidth = data;
641 }
642
643 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
644                         u8 *lane_count)
645 {
646         u8 data;
647
648         /*
649          * For DP rev.1.1, Maximum number of Main Link lanes
650          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
651          */
652         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
653         *lane_count = DPCD_MAX_LANE_COUNT(data);
654 }
655
656 static void exynos_dp_init_training(struct exynos_dp_device *dp,
657                         enum link_lane_count_type max_lane,
658                         enum link_rate_type max_rate)
659 {
660         /*
661          * MACRO_RST must be applied after the PLL_LOCK to avoid
662          * the DP inter pair skew issue for at least 10 us
663          */
664         exynos_dp_reset_macro(dp);
665
666         /* Initialize by reading RX's DPCD */
667         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
668         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
669
670         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
671            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
672                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
673                         dp->link_train.link_rate);
674                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
675         }
676
677         if (dp->link_train.lane_count == 0) {
678                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
679                         dp->link_train.lane_count);
680                 dp->link_train.lane_count = (u8)LANE_COUNT1;
681         }
682
683         /* Setup TX lane count & rate */
684         if (dp->link_train.lane_count > max_lane)
685                 dp->link_train.lane_count = max_lane;
686         if (dp->link_train.link_rate > max_rate)
687                 dp->link_train.link_rate = max_rate;
688
689         /* All DP analog module power up */
690         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
691 }
692
693 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
694 {
695         int retval = 0;
696         int training_finished;
697
698         /* Turn off unnecessary lane */
699         if (dp->link_train.lane_count == 1)
700                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
701
702         training_finished = 0;
703
704         dp->link_train.lt_state = START;
705
706         /* Process here */
707         while (!training_finished) {
708                 switch (dp->link_train.lt_state) {
709                 case START:
710                         exynos_dp_link_start(dp);
711                         break;
712                 case CLOCK_RECOVERY:
713                         exynos_dp_process_clock_recovery(dp);
714                         break;
715                 case EQUALIZER_TRAINING:
716                         exynos_dp_process_equalizer_training(dp);
717                         break;
718                 case FINISHED:
719                         training_finished = 1;
720                         break;
721                 case FAILED:
722                         return -EREMOTEIO;
723                 }
724         }
725
726         return retval;
727 }
728
729 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
730                                 u32 count,
731                                 u32 bwtype)
732 {
733         int i;
734         int retval;
735
736         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
737                 exynos_dp_init_training(dp, count, bwtype);
738                 retval = exynos_dp_sw_link_training(dp);
739                 if (retval == 0)
740                         break;
741
742                 udelay(100);
743         }
744
745         return retval;
746 }
747
748 static int exynos_dp_config_video(struct exynos_dp_device *dp,
749                         struct video_info *video_info)
750 {
751         int retval = 0;
752         int timeout_loop = 0;
753         int done_count = 0;
754
755         exynos_dp_config_video_slave_mode(dp, video_info);
756
757         exynos_dp_set_video_color_format(dp, video_info->color_depth,
758                         video_info->color_space,
759                         video_info->dynamic_range,
760                         video_info->ycbcr_coeff);
761
762         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
763                 dev_err(dp->dev, "PLL is not locked yet.\n");
764                 return -EINVAL;
765         }
766
767         for (;;) {
768                 timeout_loop++;
769                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
770                         break;
771                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
772                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
773                         return -ETIMEDOUT;
774                 }
775
776                 udelay(1);
777         }
778
779         /* Set to use the register calculated M/N video */
780         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
781
782         /* For video bist, Video timing must be generated by register */
783         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
784
785         /* Disable video mute */
786         exynos_dp_enable_video_mute(dp, 0);
787
788         /* Configure video slave mode */
789         exynos_dp_enable_video_master(dp, 0);
790
791         /* Enable video */
792         exynos_dp_start_video(dp);
793
794         timeout_loop = 0;
795
796         for (;;) {
797                 timeout_loop++;
798                 if (exynos_dp_is_video_stream_on(dp) == 0) {
799                         done_count++;
800                         if (done_count > 10)
801                                 break;
802                 } else if (done_count) {
803                         done_count = 0;
804                 }
805                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
806                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
807                         return -ETIMEDOUT;
808                 }
809
810                 mdelay(1);
811         }
812
813         if (retval != 0)
814                 dev_err(dp->dev, "Video stream is not detected!\n");
815
816         return retval;
817 }
818
819 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
820 {
821         u8 data;
822
823         if (enable) {
824                 exynos_dp_enable_scrambling(dp);
825
826                 exynos_dp_read_byte_from_dpcd(dp,
827                         DPCD_ADDR_TRAINING_PATTERN_SET,
828                         &data);
829                 exynos_dp_write_byte_to_dpcd(dp,
830                         DPCD_ADDR_TRAINING_PATTERN_SET,
831                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
832         } else {
833                 exynos_dp_disable_scrambling(dp);
834
835                 exynos_dp_read_byte_from_dpcd(dp,
836                         DPCD_ADDR_TRAINING_PATTERN_SET,
837                         &data);
838                 exynos_dp_write_byte_to_dpcd(dp,
839                         DPCD_ADDR_TRAINING_PATTERN_SET,
840                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
841         }
842 }
843
844 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
845 {
846         struct exynos_dp_device *dp = arg;
847
848         dev_err(dp->dev, "exynos_dp_irq_handler\n");
849         return IRQ_HANDLED;
850 }
851
852 static int __devinit exynos_dp_probe(struct platform_device *pdev)
853 {
854         struct resource *res;
855         struct exynos_dp_device *dp;
856         struct exynos_dp_platdata *pdata;
857
858         int ret = 0;
859
860         pdata = pdev->dev.platform_data;
861         if (!pdata) {
862                 dev_err(&pdev->dev, "no platform data\n");
863                 return -EINVAL;
864         }
865
866         dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
867                                 GFP_KERNEL);
868         if (!dp) {
869                 dev_err(&pdev->dev, "no memory for device data\n");
870                 return -ENOMEM;
871         }
872
873         dp->dev = &pdev->dev;
874
875         dp->clock = clk_get(&pdev->dev, "dp");
876         if (IS_ERR(dp->clock)) {
877                 dev_err(&pdev->dev, "failed to get clock\n");
878                 return PTR_ERR(dp->clock);
879         }
880
881         clk_enable(dp->clock);
882
883         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
884         if (!res) {
885                 dev_err(&pdev->dev, "failed to get registers\n");
886                 ret = -EINVAL;
887                 goto err_clock;
888         }
889
890         dp->reg_base = devm_request_and_ioremap(&pdev->dev, res);
891         if (!dp->reg_base) {
892                 dev_err(&pdev->dev, "failed to ioremap\n");
893                 ret = -ENOMEM;
894                 goto err_clock;
895         }
896
897         dp->irq = platform_get_irq(pdev, 0);
898         if (!dp->irq) {
899                 dev_err(&pdev->dev, "failed to get irq\n");
900                 ret = -ENODEV;
901                 goto err_clock;
902         }
903
904         ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0,
905                                 "exynos-dp", dp);
906         if (ret) {
907                 dev_err(&pdev->dev, "failed to request irq\n");
908                 goto err_clock;
909         }
910
911         dp->video_info = pdata->video_info;
912         if (pdata->phy_init)
913                 pdata->phy_init();
914
915         exynos_dp_init_dp(dp);
916
917         ret = exynos_dp_detect_hpd(dp);
918         if (ret) {
919                 dev_err(&pdev->dev, "unable to detect hpd\n");
920                 goto err_clock;
921         }
922
923         exynos_dp_handle_edid(dp);
924
925         ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
926                                 dp->video_info->link_rate);
927         if (ret) {
928                 dev_err(&pdev->dev, "unable to do link train\n");
929                 goto err_clock;
930         }
931
932         exynos_dp_enable_scramble(dp, 1);
933         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
934         exynos_dp_enable_enhanced_mode(dp, 1);
935
936         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
937         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
938
939         exynos_dp_init_video(dp);
940         ret = exynos_dp_config_video(dp, dp->video_info);
941         if (ret) {
942                 dev_err(&pdev->dev, "unable to config video\n");
943                 goto err_clock;
944         }
945
946         platform_set_drvdata(pdev, dp);
947
948         return 0;
949
950 err_clock:
951         clk_put(dp->clock);
952
953         return ret;
954 }
955
956 static int __devexit exynos_dp_remove(struct platform_device *pdev)
957 {
958         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
959         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
960
961         if (pdata && pdata->phy_exit)
962                 pdata->phy_exit();
963
964         clk_disable(dp->clock);
965         clk_put(dp->clock);
966
967         return 0;
968 }
969
970 #ifdef CONFIG_PM_SLEEP
971 static int exynos_dp_suspend(struct device *dev)
972 {
973         struct platform_device *pdev = to_platform_device(dev);
974         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
975         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
976
977         if (pdata && pdata->phy_exit)
978                 pdata->phy_exit();
979
980         clk_disable(dp->clock);
981
982         return 0;
983 }
984
985 static int exynos_dp_resume(struct device *dev)
986 {
987         struct platform_device *pdev = to_platform_device(dev);
988         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
989         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
990
991         if (pdata && pdata->phy_init)
992                 pdata->phy_init();
993
994         clk_enable(dp->clock);
995
996         exynos_dp_init_dp(dp);
997
998         exynos_dp_detect_hpd(dp);
999         exynos_dp_handle_edid(dp);
1000
1001         exynos_dp_set_link_train(dp, dp->video_info->lane_count,
1002                                 dp->video_info->link_rate);
1003
1004         exynos_dp_enable_scramble(dp, 1);
1005         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1006         exynos_dp_enable_enhanced_mode(dp, 1);
1007
1008         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1009         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1010
1011         exynos_dp_init_video(dp);
1012         exynos_dp_config_video(dp, dp->video_info);
1013
1014         return 0;
1015 }
1016 #endif
1017
1018 static const struct dev_pm_ops exynos_dp_pm_ops = {
1019         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1020 };
1021
1022 static struct platform_driver exynos_dp_driver = {
1023         .probe          = exynos_dp_probe,
1024         .remove         = __devexit_p(exynos_dp_remove),
1025         .driver         = {
1026                 .name   = "exynos-dp",
1027                 .owner  = THIS_MODULE,
1028                 .pm     = &exynos_dp_pm_ops,
1029         },
1030 };
1031
1032 module_platform_driver(exynos_dp_driver);
1033
1034 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1035 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1036 MODULE_LICENSE("GPL");