2d0d144add1ba21d0f2ca8eb0752774ba5586f63
[~shefty/rdma-dev.git] / drivers / video / exynos / exynos_dp_core.c
1 /*
2  * Samsung SoC DP (Display Port) interface driver.
3  *
4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5  * Author: Jingoo Han <jg1.han@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  */
12
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/of.h>
22
23 #include <video/exynos_dp.h>
24
25 #include "exynos_dp_core.h"
26
27 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
28 {
29         exynos_dp_reset(dp);
30
31         exynos_dp_swreset(dp);
32
33         exynos_dp_init_analog_param(dp);
34         exynos_dp_init_interrupt(dp);
35
36         /* SW defined function Normal operation */
37         exynos_dp_enable_sw_function(dp);
38
39         exynos_dp_config_interrupt(dp);
40         exynos_dp_init_analog_func(dp);
41
42         exynos_dp_init_hpd(dp);
43         exynos_dp_init_aux(dp);
44
45         return 0;
46 }
47
48 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
49 {
50         int timeout_loop = 0;
51
52         while (exynos_dp_get_plug_in_status(dp) != 0) {
53                 timeout_loop++;
54                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
55                         dev_err(dp->dev, "failed to get hpd plug status\n");
56                         return -ETIMEDOUT;
57                 }
58                 usleep_range(10, 11);
59         }
60
61         return 0;
62 }
63
64 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
65 {
66         int i;
67         unsigned char sum = 0;
68
69         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
70                 sum = sum + edid_data[i];
71
72         return sum;
73 }
74
75 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
76 {
77         unsigned char edid[EDID_BLOCK_LENGTH * 2];
78         unsigned int extend_block = 0;
79         unsigned char sum;
80         unsigned char test_vector;
81         int retval;
82
83         /*
84          * EDID device address is 0x50.
85          * However, if necessary, you must have set upper address
86          * into E-EDID in I2C device, 0x30.
87          */
88
89         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
90         retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
91                                 EDID_EXTENSION_FLAG,
92                                 &extend_block);
93         if (retval)
94                 return retval;
95
96         if (extend_block > 0) {
97                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
98
99                 /* Read EDID data */
100                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
101                                                 EDID_HEADER_PATTERN,
102                                                 EDID_BLOCK_LENGTH,
103                                                 &edid[EDID_HEADER_PATTERN]);
104                 if (retval != 0) {
105                         dev_err(dp->dev, "EDID Read failed!\n");
106                         return -EIO;
107                 }
108                 sum = exynos_dp_calc_edid_check_sum(edid);
109                 if (sum != 0) {
110                         dev_err(dp->dev, "EDID bad checksum!\n");
111                         return -EIO;
112                 }
113
114                 /* Read additional EDID data */
115                 retval = exynos_dp_read_bytes_from_i2c(dp,
116                                 I2C_EDID_DEVICE_ADDR,
117                                 EDID_BLOCK_LENGTH,
118                                 EDID_BLOCK_LENGTH,
119                                 &edid[EDID_BLOCK_LENGTH]);
120                 if (retval != 0) {
121                         dev_err(dp->dev, "EDID Read failed!\n");
122                         return -EIO;
123                 }
124                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
125                 if (sum != 0) {
126                         dev_err(dp->dev, "EDID bad checksum!\n");
127                         return -EIO;
128                 }
129
130                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
131                                         &test_vector);
132                 if (test_vector & DPCD_TEST_EDID_READ) {
133                         exynos_dp_write_byte_to_dpcd(dp,
134                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
135                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
136                         exynos_dp_write_byte_to_dpcd(dp,
137                                 DPCD_ADDR_TEST_RESPONSE,
138                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
139                 }
140         } else {
141                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
142
143                 /* Read EDID data */
144                 retval = exynos_dp_read_bytes_from_i2c(dp,
145                                 I2C_EDID_DEVICE_ADDR,
146                                 EDID_HEADER_PATTERN,
147                                 EDID_BLOCK_LENGTH,
148                                 &edid[EDID_HEADER_PATTERN]);
149                 if (retval != 0) {
150                         dev_err(dp->dev, "EDID Read failed!\n");
151                         return -EIO;
152                 }
153                 sum = exynos_dp_calc_edid_check_sum(edid);
154                 if (sum != 0) {
155                         dev_err(dp->dev, "EDID bad checksum!\n");
156                         return -EIO;
157                 }
158
159                 exynos_dp_read_byte_from_dpcd(dp,
160                         DPCD_ADDR_TEST_REQUEST,
161                         &test_vector);
162                 if (test_vector & DPCD_TEST_EDID_READ) {
163                         exynos_dp_write_byte_to_dpcd(dp,
164                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
165                                 edid[EDID_CHECKSUM]);
166                         exynos_dp_write_byte_to_dpcd(dp,
167                                 DPCD_ADDR_TEST_RESPONSE,
168                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
169                 }
170         }
171
172         dev_err(dp->dev, "EDID Read success!\n");
173         return 0;
174 }
175
176 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
177 {
178         u8 buf[12];
179         int i;
180         int retval;
181
182         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
183         retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV,
184                                 12, buf);
185         if (retval)
186                 return retval;
187
188         /* Read EDID */
189         for (i = 0; i < 3; i++) {
190                 retval = exynos_dp_read_edid(dp);
191                 if (!retval)
192                         break;
193         }
194
195         return retval;
196 }
197
198 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
199                                                 bool enable)
200 {
201         u8 data;
202
203         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
204
205         if (enable)
206                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
207                         DPCD_ENHANCED_FRAME_EN |
208                         DPCD_LANE_COUNT_SET(data));
209         else
210                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
211                         DPCD_LANE_COUNT_SET(data));
212 }
213
214 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
215 {
216         u8 data;
217         int retval;
218
219         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
220         retval = DPCD_ENHANCED_FRAME_CAP(data);
221
222         return retval;
223 }
224
225 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
226 {
227         u8 data;
228
229         data = exynos_dp_is_enhanced_mode_available(dp);
230         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
231         exynos_dp_enable_enhanced_mode(dp, data);
232 }
233
234 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
235 {
236         exynos_dp_set_training_pattern(dp, DP_NONE);
237
238         exynos_dp_write_byte_to_dpcd(dp,
239                 DPCD_ADDR_TRAINING_PATTERN_SET,
240                 DPCD_TRAINING_PATTERN_DISABLED);
241 }
242
243 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
244                                         int pre_emphasis, int lane)
245 {
246         switch (lane) {
247         case 0:
248                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
249                 break;
250         case 1:
251                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
252                 break;
253
254         case 2:
255                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
256                 break;
257
258         case 3:
259                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
260                 break;
261         }
262 }
263
264 static int exynos_dp_link_start(struct exynos_dp_device *dp)
265 {
266         u8 buf[4];
267         int lane, lane_count, pll_tries, retval;
268
269         lane_count = dp->link_train.lane_count;
270
271         dp->link_train.lt_state = CLOCK_RECOVERY;
272         dp->link_train.eq_loop = 0;
273
274         for (lane = 0; lane < lane_count; lane++)
275                 dp->link_train.cr_loop[lane] = 0;
276
277         /* Set link rate and count as you want to establish*/
278         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
279         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
280
281         /* Setup RX configuration */
282         buf[0] = dp->link_train.link_rate;
283         buf[1] = dp->link_train.lane_count;
284         retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
285                                 2, buf);
286         if (retval)
287                 return retval;
288
289         /* Set TX pre-emphasis to minimum */
290         for (lane = 0; lane < lane_count; lane++)
291                 exynos_dp_set_lane_lane_pre_emphasis(dp,
292                         PRE_EMPHASIS_LEVEL_0, lane);
293
294         /* Wait for PLL lock */
295         pll_tries = 0;
296         while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
297                 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
298                         dev_err(dp->dev, "Wait for PLL lock timed out\n");
299                         return -ETIMEDOUT;
300                 }
301
302                 pll_tries++;
303                 usleep_range(90, 120);
304         }
305
306         /* Set training pattern 1 */
307         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
308
309         /* Set RX training pattern */
310         retval = exynos_dp_write_byte_to_dpcd(dp,
311                         DPCD_ADDR_TRAINING_PATTERN_SET,
312                         DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
313         if (retval)
314                 return retval;
315
316         for (lane = 0; lane < lane_count; lane++)
317                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
318                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
319
320         retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
321                         lane_count, buf);
322
323         return retval;
324 }
325
326 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
327 {
328         int shift = (lane & 1) * 4;
329         u8 link_value = link_status[lane>>1];
330
331         return (link_value >> shift) & 0xf;
332 }
333
334 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
335 {
336         int lane;
337         u8 lane_status;
338
339         for (lane = 0; lane < lane_count; lane++) {
340                 lane_status = exynos_dp_get_lane_status(link_status, lane);
341                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
342                         return -EINVAL;
343         }
344         return 0;
345 }
346
347 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
348                                 int lane_count)
349 {
350         int lane;
351         u8 lane_status;
352
353         if ((link_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
354                 return -EINVAL;
355
356         for (lane = 0; lane < lane_count; lane++) {
357                 lane_status = exynos_dp_get_lane_status(link_status, lane);
358                 lane_status &= DPCD_CHANNEL_EQ_BITS;
359                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
360                         return -EINVAL;
361         }
362
363         return 0;
364 }
365
366 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
367                                                         int lane)
368 {
369         int shift = (lane & 1) * 4;
370         u8 link_value = adjust_request[lane>>1];
371
372         return (link_value >> shift) & 0x3;
373 }
374
375 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
376                                         u8 adjust_request[2],
377                                         int lane)
378 {
379         int shift = (lane & 1) * 4;
380         u8 link_value = adjust_request[lane>>1];
381
382         return ((link_value >> shift) & 0xc) >> 2;
383 }
384
385 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
386                                         u8 training_lane_set, int lane)
387 {
388         switch (lane) {
389         case 0:
390                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
391                 break;
392         case 1:
393                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
394                 break;
395
396         case 2:
397                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
398                 break;
399
400         case 3:
401                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
402                 break;
403         }
404 }
405
406 static unsigned int exynos_dp_get_lane_link_training(
407                                 struct exynos_dp_device *dp,
408                                 int lane)
409 {
410         u32 reg;
411
412         switch (lane) {
413         case 0:
414                 reg = exynos_dp_get_lane0_link_training(dp);
415                 break;
416         case 1:
417                 reg = exynos_dp_get_lane1_link_training(dp);
418                 break;
419         case 2:
420                 reg = exynos_dp_get_lane2_link_training(dp);
421                 break;
422         case 3:
423                 reg = exynos_dp_get_lane3_link_training(dp);
424                 break;
425         default:
426                 WARN_ON(1);
427                 return 0;
428         }
429
430         return reg;
431 }
432
433 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
434 {
435         exynos_dp_training_pattern_dis(dp);
436         exynos_dp_set_enhanced_mode(dp);
437
438         dp->link_train.lt_state = FAILED;
439 }
440
441 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
442                                         u8 adjust_request[2])
443 {
444         int lane, lane_count;
445         u8 voltage_swing, pre_emphasis, training_lane;
446
447         lane_count = dp->link_train.lane_count;
448         for (lane = 0; lane < lane_count; lane++) {
449                 voltage_swing = exynos_dp_get_adjust_request_voltage(
450                                                 adjust_request, lane);
451                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
452                                                 adjust_request, lane);
453                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
454                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
455
456                 if (voltage_swing == VOLTAGE_LEVEL_3)
457                         training_lane |= DPCD_MAX_SWING_REACHED;
458                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
459                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
460
461                 dp->link_train.training_lane[lane] = training_lane;
462         }
463 }
464
465 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
466 {
467         int lane, lane_count, retval;
468         u8 voltage_swing, pre_emphasis, training_lane;
469         u8 link_status[2], adjust_request[2];
470
471         usleep_range(100, 101);
472
473         lane_count = dp->link_train.lane_count;
474
475         retval =  exynos_dp_read_bytes_from_dpcd(dp,
476                         DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
477         if (retval)
478                 return retval;
479
480         retval =  exynos_dp_read_bytes_from_dpcd(dp,
481                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
482         if (retval)
483                 return retval;
484
485         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
486                 /* set training pattern 2 for EQ */
487                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
488
489                 retval = exynos_dp_write_byte_to_dpcd(dp,
490                                 DPCD_ADDR_TRAINING_PATTERN_SET,
491                                 DPCD_SCRAMBLING_DISABLED |
492                                 DPCD_TRAINING_PATTERN_2);
493                 if (retval)
494                         return retval;
495
496                 dev_info(dp->dev, "Link Training Clock Recovery success\n");
497                 dp->link_train.lt_state = EQUALIZER_TRAINING;
498         } else {
499                 for (lane = 0; lane < lane_count; lane++) {
500                         training_lane = exynos_dp_get_lane_link_training(
501                                                         dp, lane);
502                         voltage_swing = exynos_dp_get_adjust_request_voltage(
503                                                         adjust_request, lane);
504                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
505                                                         adjust_request, lane);
506
507                         if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
508                                         voltage_swing &&
509                             DPCD_PRE_EMPHASIS_GET(training_lane) ==
510                                         pre_emphasis)
511                                 dp->link_train.cr_loop[lane]++;
512
513                         if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
514                             voltage_swing == VOLTAGE_LEVEL_3 ||
515                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
516                                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
517                                         dp->link_train.cr_loop[lane],
518                                         voltage_swing, pre_emphasis);
519                                 exynos_dp_reduce_link_rate(dp);
520                                 return -EIO;
521                         }
522                 }
523         }
524
525         exynos_dp_get_adjust_training_lane(dp, adjust_request);
526
527         for (lane = 0; lane < lane_count; lane++)
528                 exynos_dp_set_lane_link_training(dp,
529                         dp->link_train.training_lane[lane], lane);
530
531         retval = exynos_dp_write_bytes_to_dpcd(dp,
532                         DPCD_ADDR_TRAINING_LANE0_SET, lane_count,
533                         dp->link_train.training_lane);
534         if (retval)
535                 return retval;
536
537         return retval;
538 }
539
540 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
541 {
542         int lane, lane_count, retval;
543         u32 reg;
544         u8 link_align, link_status[2], adjust_request[2];
545
546         usleep_range(400, 401);
547
548         lane_count = dp->link_train.lane_count;
549
550         retval = exynos_dp_read_bytes_from_dpcd(dp,
551                         DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
552         if (retval)
553                 return retval;
554
555         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
556                 exynos_dp_reduce_link_rate(dp);
557                 return -EIO;
558         }
559
560         retval = exynos_dp_read_bytes_from_dpcd(dp,
561                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
562         if (retval)
563                 return retval;
564
565         retval = exynos_dp_read_byte_from_dpcd(dp,
566                         DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, &link_align);
567         if (retval)
568                 return retval;
569
570         exynos_dp_get_adjust_training_lane(dp, adjust_request);
571
572         if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
573                 /* traing pattern Set to Normal */
574                 exynos_dp_training_pattern_dis(dp);
575
576                 dev_info(dp->dev, "Link Training success!\n");
577
578                 exynos_dp_get_link_bandwidth(dp, &reg);
579                 dp->link_train.link_rate = reg;
580                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
581                         dp->link_train.link_rate);
582
583                 exynos_dp_get_lane_count(dp, &reg);
584                 dp->link_train.lane_count = reg;
585                 dev_dbg(dp->dev, "final lane count = %.2x\n",
586                         dp->link_train.lane_count);
587
588                 /* set enhanced mode if available */
589                 exynos_dp_set_enhanced_mode(dp);
590                 dp->link_train.lt_state = FINISHED;
591
592                 return 0;
593         }
594
595         /* not all locked */
596         dp->link_train.eq_loop++;
597
598         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
599                 dev_err(dp->dev, "EQ Max loop\n");
600                 exynos_dp_reduce_link_rate(dp);
601                 return -EIO;
602         }
603
604         for (lane = 0; lane < lane_count; lane++)
605                 exynos_dp_set_lane_link_training(dp,
606                         dp->link_train.training_lane[lane], lane);
607
608         retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
609                         lane_count, dp->link_train.training_lane);
610
611         return retval;
612 }
613
614 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
615                                         u8 *bandwidth)
616 {
617         u8 data;
618
619         /*
620          * For DP rev.1.1, Maximum link rate of Main Link lanes
621          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
622          */
623         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
624         *bandwidth = data;
625 }
626
627 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
628                                         u8 *lane_count)
629 {
630         u8 data;
631
632         /*
633          * For DP rev.1.1, Maximum number of Main Link lanes
634          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
635          */
636         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
637         *lane_count = DPCD_MAX_LANE_COUNT(data);
638 }
639
640 static void exynos_dp_init_training(struct exynos_dp_device *dp,
641                         enum link_lane_count_type max_lane,
642                         enum link_rate_type max_rate)
643 {
644         /*
645          * MACRO_RST must be applied after the PLL_LOCK to avoid
646          * the DP inter pair skew issue for at least 10 us
647          */
648         exynos_dp_reset_macro(dp);
649
650         /* Initialize by reading RX's DPCD */
651         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
652         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
653
654         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
655            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
656                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
657                         dp->link_train.link_rate);
658                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
659         }
660
661         if (dp->link_train.lane_count == 0) {
662                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
663                         dp->link_train.lane_count);
664                 dp->link_train.lane_count = (u8)LANE_COUNT1;
665         }
666
667         /* Setup TX lane count & rate */
668         if (dp->link_train.lane_count > max_lane)
669                 dp->link_train.lane_count = max_lane;
670         if (dp->link_train.link_rate > max_rate)
671                 dp->link_train.link_rate = max_rate;
672
673         /* All DP analog module power up */
674         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
675 }
676
677 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
678 {
679         int retval = 0, training_finished = 0;
680
681         dp->link_train.lt_state = START;
682
683         /* Process here */
684         while (!retval && !training_finished) {
685                 switch (dp->link_train.lt_state) {
686                 case START:
687                         retval = exynos_dp_link_start(dp);
688                         if (retval)
689                                 dev_err(dp->dev, "LT link start failed!\n");
690                         break;
691                 case CLOCK_RECOVERY:
692                         retval = exynos_dp_process_clock_recovery(dp);
693                         if (retval)
694                                 dev_err(dp->dev, "LT CR failed!\n");
695                         break;
696                 case EQUALIZER_TRAINING:
697                         retval = exynos_dp_process_equalizer_training(dp);
698                         if (retval)
699                                 dev_err(dp->dev, "LT EQ failed!\n");
700                         break;
701                 case FINISHED:
702                         training_finished = 1;
703                         break;
704                 case FAILED:
705                         return -EREMOTEIO;
706                 }
707         }
708         if (retval)
709                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
710
711         return retval;
712 }
713
714 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
715                                 u32 count,
716                                 u32 bwtype)
717 {
718         int i;
719         int retval;
720
721         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
722                 exynos_dp_init_training(dp, count, bwtype);
723                 retval = exynos_dp_sw_link_training(dp);
724                 if (retval == 0)
725                         break;
726
727                 usleep_range(100, 110);
728         }
729
730         return retval;
731 }
732
733 static int exynos_dp_config_video(struct exynos_dp_device *dp)
734 {
735         int retval = 0;
736         int timeout_loop = 0;
737         int done_count = 0;
738
739         exynos_dp_config_video_slave_mode(dp);
740
741         exynos_dp_set_video_color_format(dp);
742
743         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
744                 dev_err(dp->dev, "PLL is not locked yet.\n");
745                 return -EINVAL;
746         }
747
748         for (;;) {
749                 timeout_loop++;
750                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
751                         break;
752                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
753                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
754                         return -ETIMEDOUT;
755                 }
756
757                 usleep_range(1, 2);
758         }
759
760         /* Set to use the register calculated M/N video */
761         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
762
763         /* For video bist, Video timing must be generated by register */
764         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
765
766         /* Disable video mute */
767         exynos_dp_enable_video_mute(dp, 0);
768
769         /* Configure video slave mode */
770         exynos_dp_enable_video_master(dp, 0);
771
772         /* Enable video */
773         exynos_dp_start_video(dp);
774
775         timeout_loop = 0;
776
777         for (;;) {
778                 timeout_loop++;
779                 if (exynos_dp_is_video_stream_on(dp) == 0) {
780                         done_count++;
781                         if (done_count > 10)
782                                 break;
783                 } else if (done_count) {
784                         done_count = 0;
785                 }
786                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
787                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
788                         return -ETIMEDOUT;
789                 }
790
791                 usleep_range(1000, 1001);
792         }
793
794         if (retval != 0)
795                 dev_err(dp->dev, "Video stream is not detected!\n");
796
797         return retval;
798 }
799
800 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
801 {
802         u8 data;
803
804         if (enable) {
805                 exynos_dp_enable_scrambling(dp);
806
807                 exynos_dp_read_byte_from_dpcd(dp,
808                         DPCD_ADDR_TRAINING_PATTERN_SET,
809                         &data);
810                 exynos_dp_write_byte_to_dpcd(dp,
811                         DPCD_ADDR_TRAINING_PATTERN_SET,
812                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
813         } else {
814                 exynos_dp_disable_scrambling(dp);
815
816                 exynos_dp_read_byte_from_dpcd(dp,
817                         DPCD_ADDR_TRAINING_PATTERN_SET,
818                         &data);
819                 exynos_dp_write_byte_to_dpcd(dp,
820                         DPCD_ADDR_TRAINING_PATTERN_SET,
821                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
822         }
823 }
824
825 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
826 {
827         struct exynos_dp_device *dp = arg;
828
829         enum dp_irq_type irq_type;
830
831         irq_type = exynos_dp_get_irq_type(dp);
832         switch (irq_type) {
833         case DP_IRQ_TYPE_HP_CABLE_IN:
834                 dev_dbg(dp->dev, "Received irq - cable in\n");
835                 schedule_work(&dp->hotplug_work);
836                 exynos_dp_clear_hotplug_interrupts(dp);
837                 break;
838         case DP_IRQ_TYPE_HP_CABLE_OUT:
839                 dev_dbg(dp->dev, "Received irq - cable out\n");
840                 exynos_dp_clear_hotplug_interrupts(dp);
841                 break;
842         case DP_IRQ_TYPE_HP_CHANGE:
843                 /*
844                  * We get these change notifications once in a while, but there
845                  * is nothing we can do with them. Just ignore it for now and
846                  * only handle cable changes.
847                  */
848                 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
849                 exynos_dp_clear_hotplug_interrupts(dp);
850                 break;
851         default:
852                 dev_err(dp->dev, "Received irq - unknown type!\n");
853                 break;
854         }
855         return IRQ_HANDLED;
856 }
857
858 static void exynos_dp_hotplug(struct work_struct *work)
859 {
860         struct exynos_dp_device *dp;
861         int ret;
862
863         dp = container_of(work, struct exynos_dp_device, hotplug_work);
864
865         ret = exynos_dp_detect_hpd(dp);
866         if (ret) {
867                 /* Cable has been disconnected, we're done */
868                 return;
869         }
870
871         ret = exynos_dp_handle_edid(dp);
872         if (ret) {
873                 dev_err(dp->dev, "unable to handle edid\n");
874                 return;
875         }
876
877         ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
878                                         dp->video_info->link_rate);
879         if (ret) {
880                 dev_err(dp->dev, "unable to do link train\n");
881                 return;
882         }
883
884         exynos_dp_enable_scramble(dp, 1);
885         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
886         exynos_dp_enable_enhanced_mode(dp, 1);
887
888         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
889         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
890
891         exynos_dp_init_video(dp);
892         ret = exynos_dp_config_video(dp);
893         if (ret)
894                 dev_err(dp->dev, "unable to config video\n");
895 }
896
897 #ifdef CONFIG_OF
898 static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
899 {
900         struct device_node *dp_node = dev->of_node;
901         struct exynos_dp_platdata *pd;
902         struct video_info *dp_video_config;
903
904         pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
905         if (!pd) {
906                 dev_err(dev, "memory allocation for pdata failed\n");
907                 return ERR_PTR(-ENOMEM);
908         }
909         dp_video_config = devm_kzalloc(dev,
910                                 sizeof(*dp_video_config), GFP_KERNEL);
911
912         if (!dp_video_config) {
913                 dev_err(dev, "memory allocation for video config failed\n");
914                 return ERR_PTR(-ENOMEM);
915         }
916         pd->video_info = dp_video_config;
917
918         dp_video_config->h_sync_polarity =
919                 of_property_read_bool(dp_node, "hsync-active-high");
920
921         dp_video_config->v_sync_polarity =
922                 of_property_read_bool(dp_node, "vsync-active-high");
923
924         dp_video_config->interlaced =
925                 of_property_read_bool(dp_node, "interlaced");
926
927         if (of_property_read_u32(dp_node, "samsung,color-space",
928                                 &dp_video_config->color_space)) {
929                 dev_err(dev, "failed to get color-space\n");
930                 return ERR_PTR(-EINVAL);
931         }
932
933         if (of_property_read_u32(dp_node, "samsung,dynamic-range",
934                                 &dp_video_config->dynamic_range)) {
935                 dev_err(dev, "failed to get dynamic-range\n");
936                 return ERR_PTR(-EINVAL);
937         }
938
939         if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
940                                 &dp_video_config->ycbcr_coeff)) {
941                 dev_err(dev, "failed to get ycbcr-coeff\n");
942                 return ERR_PTR(-EINVAL);
943         }
944
945         if (of_property_read_u32(dp_node, "samsung,color-depth",
946                                 &dp_video_config->color_depth)) {
947                 dev_err(dev, "failed to get color-depth\n");
948                 return ERR_PTR(-EINVAL);
949         }
950
951         if (of_property_read_u32(dp_node, "samsung,link-rate",
952                                 &dp_video_config->link_rate)) {
953                 dev_err(dev, "failed to get link-rate\n");
954                 return ERR_PTR(-EINVAL);
955         }
956
957         if (of_property_read_u32(dp_node, "samsung,lane-count",
958                                 &dp_video_config->lane_count)) {
959                 dev_err(dev, "failed to get lane-count\n");
960                 return ERR_PTR(-EINVAL);
961         }
962
963         return pd;
964 }
965
966 static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
967 {
968         struct device_node *dp_phy_node;
969         u32 phy_base;
970
971         dp_phy_node = of_find_node_by_name(dp->dev->of_node, "dptx-phy");
972         if (!dp_phy_node) {
973                 dev_err(dp->dev, "could not find dptx-phy node\n");
974                 return -ENODEV;
975         }
976
977         if (of_property_read_u32(dp_phy_node, "reg", &phy_base)) {
978                 dev_err(dp->dev, "faild to get reg for dptx-phy\n");
979                 return -EINVAL;
980         }
981
982         if (of_property_read_u32(dp_phy_node, "samsung,enable-mask",
983                                 &dp->enable_mask)) {
984                 dev_err(dp->dev, "faild to get enable-mask for dptx-phy\n");
985                 return -EINVAL;
986         }
987
988         dp->phy_addr = ioremap(phy_base, SZ_4);
989         if (!dp->phy_addr) {
990                 dev_err(dp->dev, "failed to ioremap dp-phy\n");
991                 return -ENOMEM;
992         }
993
994         return 0;
995 }
996
997 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
998 {
999         u32 reg;
1000
1001         reg = __raw_readl(dp->phy_addr);
1002         reg |= dp->enable_mask;
1003         __raw_writel(reg, dp->phy_addr);
1004 }
1005
1006 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1007 {
1008         u32 reg;
1009
1010         reg = __raw_readl(dp->phy_addr);
1011         reg &= ~(dp->enable_mask);
1012         __raw_writel(reg, dp->phy_addr);
1013 }
1014 #else
1015 static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
1016 {
1017         return NULL;
1018 }
1019
1020 static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
1021 {
1022         return -EINVAL;
1023 }
1024
1025 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1026 {
1027         return;
1028 }
1029
1030 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1031 {
1032         return;
1033 }
1034 #endif /* CONFIG_OF */
1035
1036 static int exynos_dp_probe(struct platform_device *pdev)
1037 {
1038         struct resource *res;
1039         struct exynos_dp_device *dp;
1040         struct exynos_dp_platdata *pdata;
1041
1042         int ret = 0;
1043
1044         dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
1045                                 GFP_KERNEL);
1046         if (!dp) {
1047                 dev_err(&pdev->dev, "no memory for device data\n");
1048                 return -ENOMEM;
1049         }
1050
1051         dp->dev = &pdev->dev;
1052
1053         if (pdev->dev.of_node) {
1054                 pdata = exynos_dp_dt_parse_pdata(&pdev->dev);
1055                 if (IS_ERR(pdata))
1056                         return PTR_ERR(pdata);
1057
1058                 ret = exynos_dp_dt_parse_phydata(dp);
1059                 if (ret)
1060                         return ret;
1061         } else {
1062                 pdata = pdev->dev.platform_data;
1063                 if (!pdata) {
1064                         dev_err(&pdev->dev, "no platform data\n");
1065                         return -EINVAL;
1066                 }
1067         }
1068
1069         dp->clock = devm_clk_get(&pdev->dev, "dp");
1070         if (IS_ERR(dp->clock)) {
1071                 dev_err(&pdev->dev, "failed to get clock\n");
1072                 return PTR_ERR(dp->clock);
1073         }
1074
1075         clk_prepare_enable(dp->clock);
1076
1077         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1078
1079         dp->reg_base = devm_request_and_ioremap(&pdev->dev, res);
1080         if (!dp->reg_base) {
1081                 dev_err(&pdev->dev, "failed to ioremap\n");
1082                 return -ENOMEM;
1083         }
1084
1085         dp->irq = platform_get_irq(pdev, 0);
1086         if (dp->irq == -ENXIO) {
1087                 dev_err(&pdev->dev, "failed to get irq\n");
1088                 return -ENODEV;
1089         }
1090
1091         INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1092
1093         dp->video_info = pdata->video_info;
1094
1095         if (pdev->dev.of_node) {
1096                 if (dp->phy_addr)
1097                         exynos_dp_phy_init(dp);
1098         } else {
1099                 if (pdata->phy_init)
1100                         pdata->phy_init();
1101         }
1102
1103         exynos_dp_init_dp(dp);
1104
1105         ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0,
1106                                 "exynos-dp", dp);
1107         if (ret) {
1108                 dev_err(&pdev->dev, "failed to request irq\n");
1109                 return ret;
1110         }
1111
1112         platform_set_drvdata(pdev, dp);
1113
1114         return 0;
1115 }
1116
1117 static int exynos_dp_remove(struct platform_device *pdev)
1118 {
1119         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1120         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1121
1122         disable_irq(dp->irq);
1123
1124         flush_work(&dp->hotplug_work);
1125
1126         if (pdev->dev.of_node) {
1127                 if (dp->phy_addr)
1128                         exynos_dp_phy_exit(dp);
1129         } else {
1130                 if (pdata->phy_exit)
1131                         pdata->phy_exit();
1132         }
1133
1134         clk_disable_unprepare(dp->clock);
1135
1136
1137         return 0;
1138 }
1139
1140 #ifdef CONFIG_PM_SLEEP
1141 static int exynos_dp_suspend(struct device *dev)
1142 {
1143         struct exynos_dp_platdata *pdata = dev->platform_data;
1144         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1145
1146         flush_work(&dp->hotplug_work);
1147
1148         if (dev->of_node) {
1149                 if (dp->phy_addr)
1150                         exynos_dp_phy_exit(dp);
1151         } else {
1152                 if (pdata->phy_exit)
1153                         pdata->phy_exit();
1154         }
1155
1156         clk_disable_unprepare(dp->clock);
1157
1158         return 0;
1159 }
1160
1161 static int exynos_dp_resume(struct device *dev)
1162 {
1163         struct exynos_dp_platdata *pdata = dev->platform_data;
1164         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1165
1166         if (dev->of_node) {
1167                 if (dp->phy_addr)
1168                         exynos_dp_phy_init(dp);
1169         } else {
1170                 if (pdata->phy_init)
1171                         pdata->phy_init();
1172         }
1173
1174         clk_prepare_enable(dp->clock);
1175
1176         exynos_dp_init_dp(dp);
1177
1178         enable_irq(dp->irq);
1179
1180         return 0;
1181 }
1182 #endif
1183
1184 static const struct dev_pm_ops exynos_dp_pm_ops = {
1185         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1186 };
1187
1188 static const struct of_device_id exynos_dp_match[] = {
1189         { .compatible = "samsung,exynos5-dp" },
1190         {},
1191 };
1192 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1193
1194 static struct platform_driver exynos_dp_driver = {
1195         .probe          = exynos_dp_probe,
1196         .remove         = exynos_dp_remove,
1197         .driver         = {
1198                 .name   = "exynos-dp",
1199                 .owner  = THIS_MODULE,
1200                 .pm     = &exynos_dp_pm_ops,
1201                 .of_match_table = of_match_ptr(exynos_dp_match),
1202         },
1203 };
1204
1205 module_platform_driver(exynos_dp_driver);
1206
1207 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1208 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1209 MODULE_LICENSE("GPL");