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[~shefty/rdma-dev.git] / drivers / video / exynos / exynos_dp_core.c
1 /*
2  * Samsung SoC DP (Display Port) interface driver.
3  *
4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5  * Author: Jingoo Han <jg1.han@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  */
12
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21
22 #include <video/exynos_dp.h>
23
24 #include "exynos_dp_core.h"
25
26 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
27 {
28         exynos_dp_reset(dp);
29
30         /* SW defined function Normal operation */
31         exynos_dp_enable_sw_function(dp);
32
33         exynos_dp_config_interrupt(dp);
34         exynos_dp_init_analog_func(dp);
35
36         exynos_dp_init_hpd(dp);
37         exynos_dp_init_aux(dp);
38
39         return 0;
40 }
41
42 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
43 {
44         int timeout_loop = 0;
45
46         exynos_dp_init_hpd(dp);
47
48         udelay(200);
49
50         while (exynos_dp_get_plug_in_status(dp) != 0) {
51                 timeout_loop++;
52                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
53                         dev_err(dp->dev, "failed to get hpd plug status\n");
54                         return -ETIMEDOUT;
55                 }
56                 udelay(10);
57         }
58
59         return 0;
60 }
61
62 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
63 {
64         int i;
65         unsigned char sum = 0;
66
67         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
68                 sum = sum + edid_data[i];
69
70         return sum;
71 }
72
73 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
74 {
75         unsigned char edid[EDID_BLOCK_LENGTH * 2];
76         unsigned int extend_block = 0;
77         unsigned char sum;
78         unsigned char test_vector;
79         int retval;
80
81         /*
82          * EDID device address is 0x50.
83          * However, if necessary, you must have set upper address
84          * into E-EDID in I2C device, 0x30.
85          */
86
87         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
88         exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
89                                 EDID_EXTENSION_FLAG,
90                                 &extend_block);
91
92         if (extend_block > 0) {
93                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
94
95                 /* Read EDID data */
96                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
97                                                 EDID_HEADER_PATTERN,
98                                                 EDID_BLOCK_LENGTH,
99                                                 &edid[EDID_HEADER_PATTERN]);
100                 if (retval != 0) {
101                         dev_err(dp->dev, "EDID Read failed!\n");
102                         return -EIO;
103                 }
104                 sum = exynos_dp_calc_edid_check_sum(edid);
105                 if (sum != 0) {
106                         dev_err(dp->dev, "EDID bad checksum!\n");
107                         return -EIO;
108                 }
109
110                 /* Read additional EDID data */
111                 retval = exynos_dp_read_bytes_from_i2c(dp,
112                                 I2C_EDID_DEVICE_ADDR,
113                                 EDID_BLOCK_LENGTH,
114                                 EDID_BLOCK_LENGTH,
115                                 &edid[EDID_BLOCK_LENGTH]);
116                 if (retval != 0) {
117                         dev_err(dp->dev, "EDID Read failed!\n");
118                         return -EIO;
119                 }
120                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
121                 if (sum != 0) {
122                         dev_err(dp->dev, "EDID bad checksum!\n");
123                         return -EIO;
124                 }
125
126                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
127                                         &test_vector);
128                 if (test_vector & DPCD_TEST_EDID_READ) {
129                         exynos_dp_write_byte_to_dpcd(dp,
130                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
131                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
132                         exynos_dp_write_byte_to_dpcd(dp,
133                                 DPCD_ADDR_TEST_RESPONSE,
134                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
135                 }
136         } else {
137                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
138
139                 /* Read EDID data */
140                 retval = exynos_dp_read_bytes_from_i2c(dp,
141                                 I2C_EDID_DEVICE_ADDR,
142                                 EDID_HEADER_PATTERN,
143                                 EDID_BLOCK_LENGTH,
144                                 &edid[EDID_HEADER_PATTERN]);
145                 if (retval != 0) {
146                         dev_err(dp->dev, "EDID Read failed!\n");
147                         return -EIO;
148                 }
149                 sum = exynos_dp_calc_edid_check_sum(edid);
150                 if (sum != 0) {
151                         dev_err(dp->dev, "EDID bad checksum!\n");
152                         return -EIO;
153                 }
154
155                 exynos_dp_read_byte_from_dpcd(dp,
156                         DPCD_ADDR_TEST_REQUEST,
157                         &test_vector);
158                 if (test_vector & DPCD_TEST_EDID_READ) {
159                         exynos_dp_write_byte_to_dpcd(dp,
160                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
161                                 edid[EDID_CHECKSUM]);
162                         exynos_dp_write_byte_to_dpcd(dp,
163                                 DPCD_ADDR_TEST_RESPONSE,
164                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
165                 }
166         }
167
168         dev_err(dp->dev, "EDID Read success!\n");
169         return 0;
170 }
171
172 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
173 {
174         u8 buf[12];
175         int i;
176         int retval;
177
178         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
179         exynos_dp_read_bytes_from_dpcd(dp,
180                 DPCD_ADDR_DPCD_REV,
181                 12, buf);
182
183         /* Read EDID */
184         for (i = 0; i < 3; i++) {
185                 retval = exynos_dp_read_edid(dp);
186                 if (retval == 0)
187                         break;
188         }
189
190         return retval;
191 }
192
193 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
194                                                 bool enable)
195 {
196         u8 data;
197
198         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
199
200         if (enable)
201                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
202                         DPCD_ENHANCED_FRAME_EN |
203                         DPCD_LANE_COUNT_SET(data));
204         else
205                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
206                         DPCD_LANE_COUNT_SET(data));
207 }
208
209 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
210 {
211         u8 data;
212         int retval;
213
214         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
215         retval = DPCD_ENHANCED_FRAME_CAP(data);
216
217         return retval;
218 }
219
220 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
221 {
222         u8 data;
223
224         data = exynos_dp_is_enhanced_mode_available(dp);
225         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
226         exynos_dp_enable_enhanced_mode(dp, data);
227 }
228
229 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
230 {
231         exynos_dp_set_training_pattern(dp, DP_NONE);
232
233         exynos_dp_write_byte_to_dpcd(dp,
234                 DPCD_ADDR_TRAINING_PATTERN_SET,
235                 DPCD_TRAINING_PATTERN_DISABLED);
236 }
237
238 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
239                                         int pre_emphasis, int lane)
240 {
241         switch (lane) {
242         case 0:
243                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
244                 break;
245         case 1:
246                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
247                 break;
248
249         case 2:
250                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
251                 break;
252
253         case 3:
254                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
255                 break;
256         }
257 }
258
259 static void exynos_dp_link_start(struct exynos_dp_device *dp)
260 {
261         u8 buf[5];
262         int lane;
263         int lane_count;
264
265         lane_count = dp->link_train.lane_count;
266
267         dp->link_train.lt_state = CLOCK_RECOVERY;
268         dp->link_train.eq_loop = 0;
269
270         for (lane = 0; lane < lane_count; lane++)
271                 dp->link_train.cr_loop[lane] = 0;
272
273         /* Set sink to D0 (Sink Not Ready) mode. */
274         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
275                                 DPCD_SET_POWER_STATE_D0);
276
277         /* Set link rate and count as you want to establish*/
278         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
279         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
280
281         /* Setup RX configuration */
282         buf[0] = dp->link_train.link_rate;
283         buf[1] = dp->link_train.lane_count;
284         exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
285                                 2, buf);
286
287         /* Set TX pre-emphasis to minimum */
288         for (lane = 0; lane < lane_count; lane++)
289                 exynos_dp_set_lane_lane_pre_emphasis(dp,
290                         PRE_EMPHASIS_LEVEL_0, lane);
291
292         /* Set training pattern 1 */
293         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
294
295         /* Set RX training pattern */
296         buf[0] = DPCD_SCRAMBLING_DISABLED |
297                  DPCD_TRAINING_PATTERN_1;
298         exynos_dp_write_byte_to_dpcd(dp,
299                 DPCD_ADDR_TRAINING_PATTERN_SET, buf[0]);
300
301         for (lane = 0; lane < lane_count; lane++)
302                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
303                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
304         exynos_dp_write_bytes_to_dpcd(dp,
305                 DPCD_ADDR_TRAINING_PATTERN_SET,
306                 lane_count, buf);
307 }
308
309 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
310 {
311         int shift = (lane & 1) * 4;
312         u8 link_value = link_status[lane>>1];
313
314         return (link_value >> shift) & 0xf;
315 }
316
317 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
318 {
319         int lane;
320         u8 lane_status;
321
322         for (lane = 0; lane < lane_count; lane++) {
323                 lane_status = exynos_dp_get_lane_status(link_status, lane);
324                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
325                         return -EINVAL;
326         }
327         return 0;
328 }
329
330 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
331 {
332         int lane;
333         u8 lane_align;
334         u8 lane_status;
335
336         lane_align = link_status[2];
337         if ((lane_align == DPCD_INTERLANE_ALIGN_DONE) == 0)
338                 return -EINVAL;
339
340         for (lane = 0; lane < lane_count; lane++) {
341                 lane_status = exynos_dp_get_lane_status(link_status, lane);
342                 lane_status &= DPCD_CHANNEL_EQ_BITS;
343                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
344                         return -EINVAL;
345         }
346         return 0;
347 }
348
349 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
350                                                         int lane)
351 {
352         int shift = (lane & 1) * 4;
353         u8 link_value = adjust_request[lane>>1];
354
355         return (link_value >> shift) & 0x3;
356 }
357
358 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
359                                         u8 adjust_request[2],
360                                         int lane)
361 {
362         int shift = (lane & 1) * 4;
363         u8 link_value = adjust_request[lane>>1];
364
365         return ((link_value >> shift) & 0xc) >> 2;
366 }
367
368 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
369                                         u8 training_lane_set, int lane)
370 {
371         switch (lane) {
372         case 0:
373                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
374                 break;
375         case 1:
376                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
377                 break;
378
379         case 2:
380                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
381                 break;
382
383         case 3:
384                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
385                 break;
386         }
387 }
388
389 static unsigned int exynos_dp_get_lane_link_training(
390                                 struct exynos_dp_device *dp,
391                                 int lane)
392 {
393         u32 reg;
394
395         switch (lane) {
396         case 0:
397                 reg = exynos_dp_get_lane0_link_training(dp);
398                 break;
399         case 1:
400                 reg = exynos_dp_get_lane1_link_training(dp);
401                 break;
402         case 2:
403                 reg = exynos_dp_get_lane2_link_training(dp);
404                 break;
405         case 3:
406                 reg = exynos_dp_get_lane3_link_training(dp);
407                 break;
408         }
409
410         return reg;
411 }
412
413 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
414 {
415         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
416                 /* set to reduced bit rate */
417                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
418                 dev_err(dp->dev, "set to bandwidth %.2x\n",
419                         dp->link_train.link_rate);
420                 dp->link_train.lt_state = START;
421         } else {
422                 exynos_dp_training_pattern_dis(dp);
423                 /* set enhanced mode if available */
424                 exynos_dp_set_enhanced_mode(dp);
425                 dp->link_train.lt_state = FAILED;
426         }
427 }
428
429 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
430                                 u8 adjust_request[2])
431 {
432         int lane;
433         int lane_count;
434         u8 voltage_swing;
435         u8 pre_emphasis;
436         u8 training_lane;
437
438         lane_count = dp->link_train.lane_count;
439         for (lane = 0; lane < lane_count; lane++) {
440                 voltage_swing = exynos_dp_get_adjust_request_voltage(
441                                                 adjust_request, lane);
442                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
443                                                 adjust_request, lane);
444                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
445                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
446
447                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
448                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
449                         training_lane |= DPCD_MAX_SWING_REACHED;
450                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
451                 }
452                 dp->link_train.training_lane[lane] = training_lane;
453         }
454 }
455
456 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
457                                         u8 voltage_swing)
458 {
459         int lane;
460         int lane_count;
461
462         lane_count = dp->link_train.lane_count;
463         for (lane = 0; lane < lane_count; lane++) {
464                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
465                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
466                         return -EINVAL;
467         }
468         return 0;
469 }
470
471 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
472 {
473         u8 data;
474         u8 link_status[6];
475         int lane;
476         int lane_count;
477         u8 buf[5];
478
479         u8 adjust_request[2];
480         u8 voltage_swing;
481         u8 pre_emphasis;
482         u8 training_lane;
483
484         udelay(100);
485
486         exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
487                                 6, link_status);
488         lane_count = dp->link_train.lane_count;
489
490         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
491                 /* set training pattern 2 for EQ */
492                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
493
494                 adjust_request[0] = link_status[4];
495                 adjust_request[1] = link_status[5];
496
497                 exynos_dp_get_adjust_train(dp, adjust_request);
498
499                 buf[0] = DPCD_SCRAMBLING_DISABLED |
500                          DPCD_TRAINING_PATTERN_2;
501                 exynos_dp_write_byte_to_dpcd(dp,
502                         DPCD_ADDR_TRAINING_LANE0_SET,
503                         buf[0]);
504
505                 for (lane = 0; lane < lane_count; lane++) {
506                         exynos_dp_set_lane_link_training(dp,
507                                 dp->link_train.training_lane[lane],
508                                 lane);
509                         buf[lane] = dp->link_train.training_lane[lane];
510                         exynos_dp_write_byte_to_dpcd(dp,
511                                 DPCD_ADDR_TRAINING_LANE0_SET + lane,
512                                 buf[lane]);
513                 }
514                 dp->link_train.lt_state = EQUALIZER_TRAINING;
515         } else {
516                 exynos_dp_read_byte_from_dpcd(dp,
517                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
518                         &data);
519                 adjust_request[0] = data;
520
521                 exynos_dp_read_byte_from_dpcd(dp,
522                         DPCD_ADDR_ADJUST_REQUEST_LANE2_3,
523                         &data);
524                 adjust_request[1] = data;
525
526                 for (lane = 0; lane < lane_count; lane++) {
527                         training_lane = exynos_dp_get_lane_link_training(
528                                                         dp, lane);
529                         voltage_swing = exynos_dp_get_adjust_request_voltage(
530                                                         adjust_request, lane);
531                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
532                                                         adjust_request, lane);
533                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
534                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
535                                 dp->link_train.cr_loop[lane]++;
536                         dp->link_train.training_lane[lane] = training_lane;
537                 }
538
539                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
540                         exynos_dp_reduce_link_rate(dp);
541                 } else {
542                         exynos_dp_get_adjust_train(dp, adjust_request);
543
544                         for (lane = 0; lane < lane_count; lane++) {
545                                 exynos_dp_set_lane_link_training(dp,
546                                         dp->link_train.training_lane[lane],
547                                         lane);
548                                 buf[lane] = dp->link_train.training_lane[lane];
549                                 exynos_dp_write_byte_to_dpcd(dp,
550                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
551                                         buf[lane]);
552                         }
553                 }
554         }
555
556         return 0;
557 }
558
559 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
560 {
561         u8 link_status[6];
562         int lane;
563         int lane_count;
564         u8 buf[5];
565         u32 reg;
566
567         u8 adjust_request[2];
568
569         udelay(400);
570
571         exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
572                                 6, link_status);
573         lane_count = dp->link_train.lane_count;
574
575         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
576                 adjust_request[0] = link_status[4];
577                 adjust_request[1] = link_status[5];
578
579                 if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
580                         /* traing pattern Set to Normal */
581                         exynos_dp_training_pattern_dis(dp);
582
583                         dev_info(dp->dev, "Link Training success!\n");
584
585                         exynos_dp_get_link_bandwidth(dp, &reg);
586                         dp->link_train.link_rate = reg;
587                         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
588                                 dp->link_train.link_rate);
589
590                         exynos_dp_get_lane_count(dp, &reg);
591                         dp->link_train.lane_count = reg;
592                         dev_dbg(dp->dev, "final lane count = %.2x\n",
593                                 dp->link_train.lane_count);
594                         /* set enhanced mode if available */
595                         exynos_dp_set_enhanced_mode(dp);
596
597                         dp->link_train.lt_state = FINISHED;
598                 } else {
599                         /* not all locked */
600                         dp->link_train.eq_loop++;
601
602                         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
603                                 exynos_dp_reduce_link_rate(dp);
604                         } else {
605                                 exynos_dp_get_adjust_train(dp, adjust_request);
606
607                                 for (lane = 0; lane < lane_count; lane++) {
608                                         exynos_dp_set_lane_link_training(dp,
609                                                 dp->link_train.training_lane[lane],
610                                                 lane);
611                                         buf[lane] = dp->link_train.training_lane[lane];
612                                         exynos_dp_write_byte_to_dpcd(dp,
613                                                 DPCD_ADDR_TRAINING_LANE0_SET + lane,
614                                                 buf[lane]);
615                                 }
616                         }
617                 }
618         } else {
619                 exynos_dp_reduce_link_rate(dp);
620         }
621
622         return 0;
623 }
624
625 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
626                         u8 *bandwidth)
627 {
628         u8 data;
629
630         /*
631          * For DP rev.1.1, Maximum link rate of Main Link lanes
632          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
633          */
634         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
635         *bandwidth = data;
636 }
637
638 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
639                         u8 *lane_count)
640 {
641         u8 data;
642
643         /*
644          * For DP rev.1.1, Maximum number of Main Link lanes
645          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
646          */
647         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
648         *lane_count = DPCD_MAX_LANE_COUNT(data);
649 }
650
651 static void exynos_dp_init_training(struct exynos_dp_device *dp,
652                         enum link_lane_count_type max_lane,
653                         enum link_rate_type max_rate)
654 {
655         /*
656          * MACRO_RST must be applied after the PLL_LOCK to avoid
657          * the DP inter pair skew issue for at least 10 us
658          */
659         exynos_dp_reset_macro(dp);
660
661         /* Initialize by reading RX's DPCD */
662         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
663         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
664
665         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
666            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
667                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
668                         dp->link_train.link_rate);
669                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
670         }
671
672         if (dp->link_train.lane_count == 0) {
673                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
674                         dp->link_train.lane_count);
675                 dp->link_train.lane_count = (u8)LANE_COUNT1;
676         }
677
678         /* Setup TX lane count & rate */
679         if (dp->link_train.lane_count > max_lane)
680                 dp->link_train.lane_count = max_lane;
681         if (dp->link_train.link_rate > max_rate)
682                 dp->link_train.link_rate = max_rate;
683
684         /* All DP analog module power up */
685         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
686 }
687
688 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
689 {
690         int retval = 0;
691         int training_finished;
692
693         /* Turn off unnecessary lane */
694         if (dp->link_train.lane_count == 1)
695                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
696
697         training_finished = 0;
698
699         dp->link_train.lt_state = START;
700
701         /* Process here */
702         while (!training_finished) {
703                 switch (dp->link_train.lt_state) {
704                 case START:
705                         exynos_dp_link_start(dp);
706                         break;
707                 case CLOCK_RECOVERY:
708                         exynos_dp_process_clock_recovery(dp);
709                         break;
710                 case EQUALIZER_TRAINING:
711                         exynos_dp_process_equalizer_training(dp);
712                         break;
713                 case FINISHED:
714                         training_finished = 1;
715                         break;
716                 case FAILED:
717                         return -EREMOTEIO;
718                 }
719         }
720
721         return retval;
722 }
723
724 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
725                                 u32 count,
726                                 u32 bwtype)
727 {
728         int i;
729         int retval;
730
731         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
732                 exynos_dp_init_training(dp, count, bwtype);
733                 retval = exynos_dp_sw_link_training(dp);
734                 if (retval == 0)
735                         break;
736
737                 udelay(100);
738         }
739
740         return retval;
741 }
742
743 static int exynos_dp_config_video(struct exynos_dp_device *dp,
744                         struct video_info *video_info)
745 {
746         int retval = 0;
747         int timeout_loop = 0;
748         int done_count = 0;
749
750         exynos_dp_config_video_slave_mode(dp, video_info);
751
752         exynos_dp_set_video_color_format(dp, video_info->color_depth,
753                         video_info->color_space,
754                         video_info->dynamic_range,
755                         video_info->ycbcr_coeff);
756
757         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
758                 dev_err(dp->dev, "PLL is not locked yet.\n");
759                 return -EINVAL;
760         }
761
762         for (;;) {
763                 timeout_loop++;
764                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
765                         break;
766                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
767                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
768                         return -ETIMEDOUT;
769                 }
770
771                 mdelay(100);
772         }
773
774         /* Set to use the register calculated M/N video */
775         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
776
777         /* For video bist, Video timing must be generated by register */
778         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
779
780         /* Disable video mute */
781         exynos_dp_enable_video_mute(dp, 0);
782
783         /* Configure video slave mode */
784         exynos_dp_enable_video_master(dp, 0);
785
786         /* Enable video */
787         exynos_dp_start_video(dp);
788
789         timeout_loop = 0;
790
791         for (;;) {
792                 timeout_loop++;
793                 if (exynos_dp_is_video_stream_on(dp) == 0) {
794                         done_count++;
795                         if (done_count > 10)
796                                 break;
797                 } else if (done_count) {
798                         done_count = 0;
799                 }
800                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
801                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
802                         return -ETIMEDOUT;
803                 }
804
805                 mdelay(100);
806         }
807
808         if (retval != 0)
809                 dev_err(dp->dev, "Video stream is not detected!\n");
810
811         return retval;
812 }
813
814 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
815 {
816         u8 data;
817
818         if (enable) {
819                 exynos_dp_enable_scrambling(dp);
820
821                 exynos_dp_read_byte_from_dpcd(dp,
822                         DPCD_ADDR_TRAINING_PATTERN_SET,
823                         &data);
824                 exynos_dp_write_byte_to_dpcd(dp,
825                         DPCD_ADDR_TRAINING_PATTERN_SET,
826                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
827         } else {
828                 exynos_dp_disable_scrambling(dp);
829
830                 exynos_dp_read_byte_from_dpcd(dp,
831                         DPCD_ADDR_TRAINING_PATTERN_SET,
832                         &data);
833                 exynos_dp_write_byte_to_dpcd(dp,
834                         DPCD_ADDR_TRAINING_PATTERN_SET,
835                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
836         }
837 }
838
839 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
840 {
841         struct exynos_dp_device *dp = arg;
842
843         dev_err(dp->dev, "exynos_dp_irq_handler\n");
844         return IRQ_HANDLED;
845 }
846
847 static int __devinit exynos_dp_probe(struct platform_device *pdev)
848 {
849         struct resource *res;
850         struct exynos_dp_device *dp;
851         struct exynos_dp_platdata *pdata;
852
853         int ret = 0;
854
855         pdata = pdev->dev.platform_data;
856         if (!pdata) {
857                 dev_err(&pdev->dev, "no platform data\n");
858                 return -EINVAL;
859         }
860
861         dp = kzalloc(sizeof(struct exynos_dp_device), GFP_KERNEL);
862         if (!dp) {
863                 dev_err(&pdev->dev, "no memory for device data\n");
864                 return -ENOMEM;
865         }
866
867         dp->dev = &pdev->dev;
868
869         dp->clock = clk_get(&pdev->dev, "dp");
870         if (IS_ERR(dp->clock)) {
871                 dev_err(&pdev->dev, "failed to get clock\n");
872                 ret = PTR_ERR(dp->clock);
873                 goto err_dp;
874         }
875
876         clk_enable(dp->clock);
877
878         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
879         if (!res) {
880                 dev_err(&pdev->dev, "failed to get registers\n");
881                 ret = -EINVAL;
882                 goto err_clock;
883         }
884
885         res = request_mem_region(res->start, resource_size(res),
886                                 dev_name(&pdev->dev));
887         if (!res) {
888                 dev_err(&pdev->dev, "failed to request registers region\n");
889                 ret = -EINVAL;
890                 goto err_clock;
891         }
892
893         dp->res = res;
894
895         dp->reg_base = ioremap(res->start, resource_size(res));
896         if (!dp->reg_base) {
897                 dev_err(&pdev->dev, "failed to ioremap\n");
898                 ret = -ENOMEM;
899                 goto err_req_region;
900         }
901
902         dp->irq = platform_get_irq(pdev, 0);
903         if (!dp->irq) {
904                 dev_err(&pdev->dev, "failed to get irq\n");
905                 ret = -ENODEV;
906                 goto err_ioremap;
907         }
908
909         ret = request_irq(dp->irq, exynos_dp_irq_handler, 0,
910                         "exynos-dp", dp);
911         if (ret) {
912                 dev_err(&pdev->dev, "failed to request irq\n");
913                 goto err_ioremap;
914         }
915
916         dp->video_info = pdata->video_info;
917         if (pdata->phy_init)
918                 pdata->phy_init();
919
920         exynos_dp_init_dp(dp);
921
922         ret = exynos_dp_detect_hpd(dp);
923         if (ret) {
924                 dev_err(&pdev->dev, "unable to detect hpd\n");
925                 goto err_irq;
926         }
927
928         exynos_dp_handle_edid(dp);
929
930         ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
931                                 dp->video_info->link_rate);
932         if (ret) {
933                 dev_err(&pdev->dev, "unable to do link train\n");
934                 goto err_irq;
935         }
936
937         exynos_dp_enable_scramble(dp, 1);
938         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
939         exynos_dp_enable_enhanced_mode(dp, 1);
940
941         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
942         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
943
944         exynos_dp_init_video(dp);
945         ret = exynos_dp_config_video(dp, dp->video_info);
946         if (ret) {
947                 dev_err(&pdev->dev, "unable to config video\n");
948                 goto err_irq;
949         }
950
951         platform_set_drvdata(pdev, dp);
952
953         return 0;
954
955 err_irq:
956         free_irq(dp->irq, dp);
957 err_ioremap:
958         iounmap(dp->reg_base);
959 err_req_region:
960         release_mem_region(res->start, resource_size(res));
961 err_clock:
962         clk_put(dp->clock);
963 err_dp:
964         kfree(dp);
965
966         return ret;
967 }
968
969 static int __devexit exynos_dp_remove(struct platform_device *pdev)
970 {
971         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
972         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
973
974         if (pdata && pdata->phy_exit)
975                 pdata->phy_exit();
976
977         free_irq(dp->irq, dp);
978         iounmap(dp->reg_base);
979
980         clk_disable(dp->clock);
981         clk_put(dp->clock);
982
983         release_mem_region(dp->res->start, resource_size(dp->res));
984
985         kfree(dp);
986
987         return 0;
988 }
989
990 #ifdef CONFIG_PM_SLEEP
991 static int exynos_dp_suspend(struct device *dev)
992 {
993         struct platform_device *pdev = to_platform_device(dev);
994         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
995         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
996
997         if (pdata && pdata->phy_exit)
998                 pdata->phy_exit();
999
1000         clk_disable(dp->clock);
1001
1002         return 0;
1003 }
1004
1005 static int exynos_dp_resume(struct device *dev)
1006 {
1007         struct platform_device *pdev = to_platform_device(dev);
1008         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1009         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1010
1011         if (pdata && pdata->phy_init)
1012                 pdata->phy_init();
1013
1014         clk_enable(dp->clock);
1015
1016         exynos_dp_init_dp(dp);
1017
1018         exynos_dp_detect_hpd(dp);
1019         exynos_dp_handle_edid(dp);
1020
1021         exynos_dp_set_link_train(dp, dp->video_info->lane_count,
1022                                 dp->video_info->link_rate);
1023
1024         exynos_dp_enable_scramble(dp, 1);
1025         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1026         exynos_dp_enable_enhanced_mode(dp, 1);
1027
1028         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1029         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1030
1031         exynos_dp_init_video(dp);
1032         exynos_dp_config_video(dp, dp->video_info);
1033
1034         return 0;
1035 }
1036 #endif
1037
1038 static const struct dev_pm_ops exynos_dp_pm_ops = {
1039         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1040 };
1041
1042 static struct platform_driver exynos_dp_driver = {
1043         .probe          = exynos_dp_probe,
1044         .remove         = __devexit_p(exynos_dp_remove),
1045         .driver         = {
1046                 .name   = "exynos-dp",
1047                 .owner  = THIS_MODULE,
1048                 .pm     = &exynos_dp_pm_ops,
1049         },
1050 };
1051
1052 module_platform_driver(exynos_dp_driver);
1053
1054 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1055 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1056 MODULE_LICENSE("GPL");