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1 /*
2  * linux/drivers/video/omap2/dss/dss.c
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * Some code and ideas taken from drivers/video/omap/ driver
8  * by Imre Deak.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License version 2 as published by
12  * the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License along with
20  * this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #define DSS_SUBSYS_NAME "DSS"
24
25 #include <linux/kernel.h>
26 #include <linux/io.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/delay.h>
30 #include <linux/seq_file.h>
31 #include <linux/clk.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/gfp.h>
35
36 #include <video/omapdss.h>
37
38 #include <plat/cpu.h>
39
40 #include "dss.h"
41 #include "dss_features.h"
42
43 #define DSS_SZ_REGS                     SZ_512
44
45 struct dss_reg {
46         u16 idx;
47 };
48
49 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
50
51 #define DSS_REVISION                    DSS_REG(0x0000)
52 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
53 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
54 #define DSS_CONTROL                     DSS_REG(0x0040)
55 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
56 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
57 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
58
59 #define REG_GET(idx, start, end) \
60         FLD_GET(dss_read_reg(idx), start, end)
61
62 #define REG_FLD_MOD(idx, val, start, end) \
63         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
64
65 static int dss_runtime_get(void);
66 static void dss_runtime_put(void);
67
68 struct dss_features {
69         u8 fck_div_max;
70         u8 dss_fck_multiplier;
71         const char *clk_name;
72         int (*dpi_select_source)(enum omap_channel channel);
73 };
74
75 static struct {
76         struct platform_device *pdev;
77         void __iomem    *base;
78
79         struct clk      *dpll4_m4_ck;
80         struct clk      *dss_clk;
81
82         unsigned long   cache_req_pck;
83         unsigned long   cache_prate;
84         struct dss_clock_info cache_dss_cinfo;
85         struct dispc_clock_info cache_dispc_cinfo;
86
87         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
88         enum omap_dss_clk_source dispc_clk_source;
89         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
90
91         bool            ctx_valid;
92         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
93
94         const struct dss_features *feat;
95 } dss;
96
97 static const char * const dss_generic_clk_source_names[] = {
98         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
99         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
100         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
101 };
102
103 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
104 {
105         __raw_writel(val, dss.base + idx.idx);
106 }
107
108 static inline u32 dss_read_reg(const struct dss_reg idx)
109 {
110         return __raw_readl(dss.base + idx.idx);
111 }
112
113 #define SR(reg) \
114         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
115 #define RR(reg) \
116         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
117
118 static void dss_save_context(void)
119 {
120         DSSDBG("dss_save_context\n");
121
122         SR(CONTROL);
123
124         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
125                         OMAP_DISPLAY_TYPE_SDI) {
126                 SR(SDI_CONTROL);
127                 SR(PLL_CONTROL);
128         }
129
130         dss.ctx_valid = true;
131
132         DSSDBG("context saved\n");
133 }
134
135 static void dss_restore_context(void)
136 {
137         DSSDBG("dss_restore_context\n");
138
139         if (!dss.ctx_valid)
140                 return;
141
142         RR(CONTROL);
143
144         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
145                         OMAP_DISPLAY_TYPE_SDI) {
146                 RR(SDI_CONTROL);
147                 RR(PLL_CONTROL);
148         }
149
150         DSSDBG("context restored\n");
151 }
152
153 #undef SR
154 #undef RR
155
156 void dss_sdi_init(int datapairs)
157 {
158         u32 l;
159
160         BUG_ON(datapairs > 3 || datapairs < 1);
161
162         l = dss_read_reg(DSS_SDI_CONTROL);
163         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
164         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
165         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
166         dss_write_reg(DSS_SDI_CONTROL, l);
167
168         l = dss_read_reg(DSS_PLL_CONTROL);
169         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
170         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
171         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
172         dss_write_reg(DSS_PLL_CONTROL, l);
173 }
174
175 int dss_sdi_enable(void)
176 {
177         unsigned long timeout;
178
179         dispc_pck_free_enable(1);
180
181         /* Reset SDI PLL */
182         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
183         udelay(1);      /* wait 2x PCLK */
184
185         /* Lock SDI PLL */
186         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
187
188         /* Waiting for PLL lock request to complete */
189         timeout = jiffies + msecs_to_jiffies(500);
190         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
191                 if (time_after_eq(jiffies, timeout)) {
192                         DSSERR("PLL lock request timed out\n");
193                         goto err1;
194                 }
195         }
196
197         /* Clearing PLL_GO bit */
198         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
199
200         /* Waiting for PLL to lock */
201         timeout = jiffies + msecs_to_jiffies(500);
202         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
203                 if (time_after_eq(jiffies, timeout)) {
204                         DSSERR("PLL lock timed out\n");
205                         goto err1;
206                 }
207         }
208
209         dispc_lcd_enable_signal(1);
210
211         /* Waiting for SDI reset to complete */
212         timeout = jiffies + msecs_to_jiffies(500);
213         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
214                 if (time_after_eq(jiffies, timeout)) {
215                         DSSERR("SDI reset timed out\n");
216                         goto err2;
217                 }
218         }
219
220         return 0;
221
222  err2:
223         dispc_lcd_enable_signal(0);
224  err1:
225         /* Reset SDI PLL */
226         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
227
228         dispc_pck_free_enable(0);
229
230         return -ETIMEDOUT;
231 }
232
233 void dss_sdi_disable(void)
234 {
235         dispc_lcd_enable_signal(0);
236
237         dispc_pck_free_enable(0);
238
239         /* Reset SDI PLL */
240         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
241 }
242
243 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
244 {
245         return dss_generic_clk_source_names[clk_src];
246 }
247
248 void dss_dump_clocks(struct seq_file *s)
249 {
250         unsigned long dpll4_ck_rate;
251         unsigned long dpll4_m4_ck_rate;
252         const char *fclk_name, *fclk_real_name;
253         unsigned long fclk_rate;
254
255         if (dss_runtime_get())
256                 return;
257
258         seq_printf(s, "- DSS -\n");
259
260         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
261         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
262         fclk_rate = clk_get_rate(dss.dss_clk);
263
264         if (dss.dpll4_m4_ck) {
265                 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
266                 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
267
268                 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
269
270                 seq_printf(s, "%s (%s) = %lu / %lu * %d  = %lu\n",
271                                 fclk_name, fclk_real_name, dpll4_ck_rate,
272                                 dpll4_ck_rate / dpll4_m4_ck_rate,
273                                 dss.feat->dss_fck_multiplier, fclk_rate);
274         } else {
275                 seq_printf(s, "%s (%s) = %lu\n",
276                                 fclk_name, fclk_real_name,
277                                 fclk_rate);
278         }
279
280         dss_runtime_put();
281 }
282
283 static void dss_dump_regs(struct seq_file *s)
284 {
285 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
286
287         if (dss_runtime_get())
288                 return;
289
290         DUMPREG(DSS_REVISION);
291         DUMPREG(DSS_SYSCONFIG);
292         DUMPREG(DSS_SYSSTATUS);
293         DUMPREG(DSS_CONTROL);
294
295         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
296                         OMAP_DISPLAY_TYPE_SDI) {
297                 DUMPREG(DSS_SDI_CONTROL);
298                 DUMPREG(DSS_PLL_CONTROL);
299                 DUMPREG(DSS_SDI_STATUS);
300         }
301
302         dss_runtime_put();
303 #undef DUMPREG
304 }
305
306 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
307 {
308         struct platform_device *dsidev;
309         int b;
310         u8 start, end;
311
312         switch (clk_src) {
313         case OMAP_DSS_CLK_SRC_FCK:
314                 b = 0;
315                 break;
316         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
317                 b = 1;
318                 dsidev = dsi_get_dsidev_from_id(0);
319                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
320                 break;
321         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
322                 b = 2;
323                 dsidev = dsi_get_dsidev_from_id(1);
324                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
325                 break;
326         default:
327                 BUG();
328                 return;
329         }
330
331         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
332
333         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
334
335         dss.dispc_clk_source = clk_src;
336 }
337
338 void dss_select_dsi_clk_source(int dsi_module,
339                 enum omap_dss_clk_source clk_src)
340 {
341         struct platform_device *dsidev;
342         int b, pos;
343
344         switch (clk_src) {
345         case OMAP_DSS_CLK_SRC_FCK:
346                 b = 0;
347                 break;
348         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
349                 BUG_ON(dsi_module != 0);
350                 b = 1;
351                 dsidev = dsi_get_dsidev_from_id(0);
352                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
353                 break;
354         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
355                 BUG_ON(dsi_module != 1);
356                 b = 1;
357                 dsidev = dsi_get_dsidev_from_id(1);
358                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
359                 break;
360         default:
361                 BUG();
362                 return;
363         }
364
365         pos = dsi_module == 0 ? 1 : 10;
366         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
367
368         dss.dsi_clk_source[dsi_module] = clk_src;
369 }
370
371 void dss_select_lcd_clk_source(enum omap_channel channel,
372                 enum omap_dss_clk_source clk_src)
373 {
374         struct platform_device *dsidev;
375         int b, ix, pos;
376
377         if (!dss_has_feature(FEAT_LCD_CLK_SRC))
378                 return;
379
380         switch (clk_src) {
381         case OMAP_DSS_CLK_SRC_FCK:
382                 b = 0;
383                 break;
384         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
385                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
386                 b = 1;
387                 dsidev = dsi_get_dsidev_from_id(0);
388                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
389                 break;
390         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
391                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
392                        channel != OMAP_DSS_CHANNEL_LCD3);
393                 b = 1;
394                 dsidev = dsi_get_dsidev_from_id(1);
395                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
396                 break;
397         default:
398                 BUG();
399                 return;
400         }
401
402         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
403              (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
404         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
405
406         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
407             (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
408         dss.lcd_clk_source[ix] = clk_src;
409 }
410
411 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
412 {
413         return dss.dispc_clk_source;
414 }
415
416 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
417 {
418         return dss.dsi_clk_source[dsi_module];
419 }
420
421 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
422 {
423         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
424                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
425                         (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
426                 return dss.lcd_clk_source[ix];
427         } else {
428                 /* LCD_CLK source is the same as DISPC_FCLK source for
429                  * OMAP2 and OMAP3 */
430                 return dss.dispc_clk_source;
431         }
432 }
433
434 int dss_set_clock_div(struct dss_clock_info *cinfo)
435 {
436         if (dss.dpll4_m4_ck) {
437                 unsigned long prate;
438                 int r;
439
440                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
441                 DSSDBG("dpll4_m4 = %ld\n", prate);
442
443                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
444                 if (r)
445                         return r;
446         } else {
447                 if (cinfo->fck_div != 0)
448                         return -EINVAL;
449         }
450
451         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
452
453         return 0;
454 }
455
456 unsigned long dss_get_dpll4_rate(void)
457 {
458         if (dss.dpll4_m4_ck)
459                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
460         else
461                 return 0;
462 }
463
464 int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
465                 struct dispc_clock_info *dispc_cinfo)
466 {
467         unsigned long prate;
468         struct dss_clock_info best_dss;
469         struct dispc_clock_info best_dispc;
470
471         unsigned long fck, max_dss_fck;
472
473         u16 fck_div;
474
475         int match = 0;
476         int min_fck_per_pck;
477
478         prate = dss_get_dpll4_rate();
479
480         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
481
482         fck = clk_get_rate(dss.dss_clk);
483         if (req_pck == dss.cache_req_pck && prate == dss.cache_prate &&
484                 dss.cache_dss_cinfo.fck == fck) {
485                 DSSDBG("dispc clock info found from cache.\n");
486                 *dss_cinfo = dss.cache_dss_cinfo;
487                 *dispc_cinfo = dss.cache_dispc_cinfo;
488                 return 0;
489         }
490
491         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
492
493         if (min_fck_per_pck &&
494                 req_pck * min_fck_per_pck > max_dss_fck) {
495                 DSSERR("Requested pixel clock not possible with the current "
496                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
497                                 "the constraint off.\n");
498                 min_fck_per_pck = 0;
499         }
500
501 retry:
502         memset(&best_dss, 0, sizeof(best_dss));
503         memset(&best_dispc, 0, sizeof(best_dispc));
504
505         if (dss.dpll4_m4_ck == NULL) {
506                 struct dispc_clock_info cur_dispc;
507                 /* XXX can we change the clock on omap2? */
508                 fck = clk_get_rate(dss.dss_clk);
509                 fck_div = 1;
510
511                 dispc_find_clk_divs(req_pck, fck, &cur_dispc);
512                 match = 1;
513
514                 best_dss.fck = fck;
515                 best_dss.fck_div = fck_div;
516
517                 best_dispc = cur_dispc;
518
519                 goto found;
520         } else {
521                 for (fck_div = dss.feat->fck_div_max; fck_div > 0; --fck_div) {
522                         struct dispc_clock_info cur_dispc;
523
524                         fck = prate / fck_div * dss.feat->dss_fck_multiplier;
525
526                         if (fck > max_dss_fck)
527                                 continue;
528
529                         if (min_fck_per_pck &&
530                                         fck < req_pck * min_fck_per_pck)
531                                 continue;
532
533                         match = 1;
534
535                         dispc_find_clk_divs(req_pck, fck, &cur_dispc);
536
537                         if (abs(cur_dispc.pck - req_pck) <
538                                         abs(best_dispc.pck - req_pck)) {
539
540                                 best_dss.fck = fck;
541                                 best_dss.fck_div = fck_div;
542
543                                 best_dispc = cur_dispc;
544
545                                 if (cur_dispc.pck == req_pck)
546                                         goto found;
547                         }
548                 }
549         }
550
551 found:
552         if (!match) {
553                 if (min_fck_per_pck) {
554                         DSSERR("Could not find suitable clock settings.\n"
555                                         "Turning FCK/PCK constraint off and"
556                                         "trying again.\n");
557                         min_fck_per_pck = 0;
558                         goto retry;
559                 }
560
561                 DSSERR("Could not find suitable clock settings.\n");
562
563                 return -EINVAL;
564         }
565
566         if (dss_cinfo)
567                 *dss_cinfo = best_dss;
568         if (dispc_cinfo)
569                 *dispc_cinfo = best_dispc;
570
571         dss.cache_req_pck = req_pck;
572         dss.cache_prate = prate;
573         dss.cache_dss_cinfo = best_dss;
574         dss.cache_dispc_cinfo = best_dispc;
575
576         return 0;
577 }
578
579 void dss_set_venc_output(enum omap_dss_venc_type type)
580 {
581         int l = 0;
582
583         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
584                 l = 0;
585         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
586                 l = 1;
587         else
588                 BUG();
589
590         /* venc out selection. 0 = comp, 1 = svideo */
591         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
592 }
593
594 void dss_set_dac_pwrdn_bgz(bool enable)
595 {
596         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
597 }
598
599 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
600 {
601         enum omap_display_type dp;
602         dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
603
604         /* Complain about invalid selections */
605         WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
606         WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
607
608         /* Select only if we have options */
609         if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
610                 REG_FLD_MOD(DSS_CONTROL, src, 15, 15);  /* VENC_HDMI_SWITCH */
611 }
612
613 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
614 {
615         enum omap_display_type displays;
616
617         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
618         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
619                 return DSS_VENC_TV_CLK;
620
621         if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
622                 return DSS_HDMI_M_PCLK;
623
624         return REG_GET(DSS_CONTROL, 15, 15);
625 }
626
627 static int dss_dpi_select_source_omap2_omap3(enum omap_channel channel)
628 {
629         if (channel != OMAP_DSS_CHANNEL_LCD)
630                 return -EINVAL;
631
632         return 0;
633 }
634
635 static int dss_dpi_select_source_omap4(enum omap_channel channel)
636 {
637         int val;
638
639         switch (channel) {
640         case OMAP_DSS_CHANNEL_LCD2:
641                 val = 0;
642                 break;
643         case OMAP_DSS_CHANNEL_DIGIT:
644                 val = 1;
645                 break;
646         default:
647                 return -EINVAL;
648         }
649
650         REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
651
652         return 0;
653 }
654
655 static int dss_dpi_select_source_omap5(enum omap_channel channel)
656 {
657         int val;
658
659         switch (channel) {
660         case OMAP_DSS_CHANNEL_LCD:
661                 val = 1;
662                 break;
663         case OMAP_DSS_CHANNEL_LCD2:
664                 val = 2;
665                 break;
666         case OMAP_DSS_CHANNEL_LCD3:
667                 val = 3;
668                 break;
669         case OMAP_DSS_CHANNEL_DIGIT:
670                 val = 0;
671                 break;
672         default:
673                 return -EINVAL;
674         }
675
676         REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
677
678         return 0;
679 }
680
681 int dss_dpi_select_source(enum omap_channel channel)
682 {
683         return dss.feat->dpi_select_source(channel);
684 }
685
686 static int dss_get_clocks(void)
687 {
688         struct clk *clk;
689         int r;
690
691         clk = clk_get(&dss.pdev->dev, "fck");
692         if (IS_ERR(clk)) {
693                 DSSERR("can't get clock fck\n");
694                 r = PTR_ERR(clk);
695                 goto err;
696         }
697
698         dss.dss_clk = clk;
699
700         clk = clk_get(NULL, dss.feat->clk_name);
701         if (IS_ERR(clk)) {
702                 DSSERR("Failed to get %s\n", dss.feat->clk_name);
703                 r = PTR_ERR(clk);
704                 goto err;
705         }
706
707         dss.dpll4_m4_ck = clk;
708
709         return 0;
710
711 err:
712         if (dss.dss_clk)
713                 clk_put(dss.dss_clk);
714         if (dss.dpll4_m4_ck)
715                 clk_put(dss.dpll4_m4_ck);
716
717         return r;
718 }
719
720 static void dss_put_clocks(void)
721 {
722         if (dss.dpll4_m4_ck)
723                 clk_put(dss.dpll4_m4_ck);
724         clk_put(dss.dss_clk);
725 }
726
727 static int dss_runtime_get(void)
728 {
729         int r;
730
731         DSSDBG("dss_runtime_get\n");
732
733         r = pm_runtime_get_sync(&dss.pdev->dev);
734         WARN_ON(r < 0);
735         return r < 0 ? r : 0;
736 }
737
738 static void dss_runtime_put(void)
739 {
740         int r;
741
742         DSSDBG("dss_runtime_put\n");
743
744         r = pm_runtime_put_sync(&dss.pdev->dev);
745         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
746 }
747
748 /* DEBUGFS */
749 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
750 void dss_debug_dump_clocks(struct seq_file *s)
751 {
752         dss_dump_clocks(s);
753         dispc_dump_clocks(s);
754 #ifdef CONFIG_OMAP2_DSS_DSI
755         dsi_dump_clocks(s);
756 #endif
757 }
758 #endif
759
760 static const struct dss_features omap24xx_dss_feats __initconst = {
761         .fck_div_max            =       16,
762         .dss_fck_multiplier     =       2,
763         .clk_name               =       NULL,
764         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
765 };
766
767 static const struct dss_features omap34xx_dss_feats __initconst = {
768         .fck_div_max            =       16,
769         .dss_fck_multiplier     =       2,
770         .clk_name               =       "dpll4_m4_ck",
771         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
772 };
773
774 static const struct dss_features omap3630_dss_feats __initconst = {
775         .fck_div_max            =       32,
776         .dss_fck_multiplier     =       1,
777         .clk_name               =       "dpll4_m4_ck",
778         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
779 };
780
781 static const struct dss_features omap44xx_dss_feats __initconst = {
782         .fck_div_max            =       32,
783         .dss_fck_multiplier     =       1,
784         .clk_name               =       "dpll_per_m5x2_ck",
785         .dpi_select_source      =       &dss_dpi_select_source_omap4,
786 };
787
788 static const struct dss_features omap54xx_dss_feats __initconst = {
789         .fck_div_max            =       64,
790         .dss_fck_multiplier     =       1,
791         .clk_name               =       "dpll_per_h12x2_ck",
792         .dpi_select_source      =       &dss_dpi_select_source_omap5,
793 };
794
795 static int __init dss_init_features(struct device *dev)
796 {
797         const struct dss_features *src;
798         struct dss_features *dst;
799
800         dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
801         if (!dst) {
802                 dev_err(dev, "Failed to allocate local DSS Features\n");
803                 return -ENOMEM;
804         }
805
806         if (cpu_is_omap24xx())
807                 src = &omap24xx_dss_feats;
808         else if (cpu_is_omap3630())
809                 src = &omap3630_dss_feats;
810         else if (cpu_is_omap34xx())
811                 src = &omap34xx_dss_feats;
812         else if (cpu_is_omap44xx())
813                 src = &omap44xx_dss_feats;
814         else if (soc_is_omap54xx())
815                 src = &omap54xx_dss_feats;
816         else
817                 return -ENODEV;
818
819         memcpy(dst, src, sizeof(*dst));
820         dss.feat = dst;
821
822         return 0;
823 }
824
825 /* DSS HW IP initialisation */
826 static int __init omap_dsshw_probe(struct platform_device *pdev)
827 {
828         struct resource *dss_mem;
829         u32 rev;
830         int r;
831
832         dss.pdev = pdev;
833
834         r = dss_init_features(&dss.pdev->dev);
835         if (r)
836                 return r;
837
838         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
839         if (!dss_mem) {
840                 DSSERR("can't get IORESOURCE_MEM DSS\n");
841                 return -EINVAL;
842         }
843
844         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
845                                 resource_size(dss_mem));
846         if (!dss.base) {
847                 DSSERR("can't ioremap DSS\n");
848                 return -ENOMEM;
849         }
850
851         r = dss_get_clocks();
852         if (r)
853                 return r;
854
855         pm_runtime_enable(&pdev->dev);
856
857         r = dss_runtime_get();
858         if (r)
859                 goto err_runtime_get;
860
861         /* Select DPLL */
862         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
863
864 #ifdef CONFIG_OMAP2_DSS_VENC
865         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
866         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
867         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
868 #endif
869         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
870         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
871         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
872         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
873         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
874
875         rev = dss_read_reg(DSS_REVISION);
876         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
877                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
878
879         dss_runtime_put();
880
881         dss_debugfs_create_file("dss", dss_dump_regs);
882
883         return 0;
884
885 err_runtime_get:
886         pm_runtime_disable(&pdev->dev);
887         dss_put_clocks();
888         return r;
889 }
890
891 static int __exit omap_dsshw_remove(struct platform_device *pdev)
892 {
893         pm_runtime_disable(&pdev->dev);
894
895         dss_put_clocks();
896
897         return 0;
898 }
899
900 static int dss_runtime_suspend(struct device *dev)
901 {
902         dss_save_context();
903         dss_set_min_bus_tput(dev, 0);
904         return 0;
905 }
906
907 static int dss_runtime_resume(struct device *dev)
908 {
909         int r;
910         /*
911          * Set an arbitrarily high tput request to ensure OPP100.
912          * What we should really do is to make a request to stay in OPP100,
913          * without any tput requirements, but that is not currently possible
914          * via the PM layer.
915          */
916
917         r = dss_set_min_bus_tput(dev, 1000000000);
918         if (r)
919                 return r;
920
921         dss_restore_context();
922         return 0;
923 }
924
925 static const struct dev_pm_ops dss_pm_ops = {
926         .runtime_suspend = dss_runtime_suspend,
927         .runtime_resume = dss_runtime_resume,
928 };
929
930 static struct platform_driver omap_dsshw_driver = {
931         .remove         = __exit_p(omap_dsshw_remove),
932         .driver         = {
933                 .name   = "omapdss_dss",
934                 .owner  = THIS_MODULE,
935                 .pm     = &dss_pm_ops,
936         },
937 };
938
939 int __init dss_init_platform_driver(void)
940 {
941         return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
942 }
943
944 void dss_uninit_platform_driver(void)
945 {
946         platform_driver_unregister(&omap_dsshw_driver);
947 }