Merge branch 'fbdev/edid'
[~shefty/rdma-dev.git] / drivers / video / sh_mobile_hdmi.c
1 /*
2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3  * for SLISHDMI13T and SLIPHDMIT IP cores
4  *
5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/workqueue.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27
28 #include <video/sh_mobile_hdmi.h>
29 #include <video/sh_mobile_lcdc.h>
30
31 #include "sh_mobile_lcdcfb.h"
32
33 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
34 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
35                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
36 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
38 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
39                                                         bits 19..16 of Internal CTS */
40 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
41 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
42 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
43 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
44 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
45 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
46 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
47 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
48 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
49 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
50 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
51 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
52 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
53 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
54 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
55 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
56 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
57 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
58 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
59
60 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
61 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
62
63 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
64 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
65 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
66 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
67 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
68 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
69 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
70 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
71 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
72 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
73 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
74 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
75 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
76 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
77 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
78 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
79 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
80 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
81 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
82 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
83 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
84 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
85 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
86 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
87 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
97 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
98 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
129 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
130 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
132 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
133 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
134 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
135 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
136 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
137 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
138 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
139 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
140 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
141 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
142 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
143 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
144 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
145 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
146 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
147 #define HDMI_SHA0                               0xB9 /* sha0 */
148 #define HDMI_SHA1                               0xBA /* sha1 */
149 #define HDMI_SHA2                               0xBB /* sha2 */
150 #define HDMI_SHA3                               0xBC /* sha3 */
151 #define HDMI_SHA4                               0xBD /* sha4 */
152 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
153 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
154 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
155 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
156 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
157 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
158 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
159 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
160 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
161 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
162 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
163 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
164 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
165 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
166 #define HDMI_AN_SEED                            0xCC /* An seed */
167 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
168 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
170 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
171 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
172 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
173 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
174 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
175 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
176 #define HDMI_PJ                                 0xD7 /* Pj */
177 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
178 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
179 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
180 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
181 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
182 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
183 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
184 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
185 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
186 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
187 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
188 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
189 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
190 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
191 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
192 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
193 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
194 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
195 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
196 #define HDMI_AN_47_40                           0xED /* An [47:40] */
197 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
198 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
199 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
200 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
201 #define HDMI_TEST_MODE                          0xFE /* Test mode */
202
203 enum hotplug_state {
204         HDMI_HOTPLUG_DISCONNECTED,
205         HDMI_HOTPLUG_CONNECTED,
206         HDMI_HOTPLUG_EDID_DONE,
207 };
208
209 struct sh_hdmi {
210         void __iomem *base;
211         enum hotplug_state hp_state;    /* hot-plug status */
212         u8 preprogrammed_vic;           /* use a pre-programmed VIC or
213                                            the external mode */
214         struct clk *hdmi_clk;
215         struct device *dev;
216         struct fb_info *info;
217         struct mutex mutex;             /* Protect the info pointer */
218         struct delayed_work edid_work;
219         struct fb_var_screeninfo var;
220         struct fb_monspecs monspec;
221 };
222
223 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
224 {
225         iowrite8(data, hdmi->base + reg);
226 }
227
228 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
229 {
230         return ioread8(hdmi->base + reg);
231 }
232
233 /*
234  *      HDMI sound
235  */
236 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
237                                      unsigned int reg)
238 {
239         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
240
241         return hdmi_read(hdmi, reg);
242 }
243
244 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
245                              unsigned int reg,
246                              unsigned int value)
247 {
248         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
249
250         hdmi_write(hdmi, value, reg);
251         return 0;
252 }
253
254 static struct snd_soc_dai_driver sh_hdmi_dai = {
255         .name = "sh_mobile_hdmi-hifi",
256         .playback = {
257                 .stream_name = "Playback",
258                 .channels_min = 2,
259                 .channels_max = 8,
260                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
261                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
262                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
263                          SNDRV_PCM_RATE_192000,
264                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
265         },
266 };
267
268 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
269 {
270         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
271
272         return 0;
273 }
274
275 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
276         .probe          = sh_hdmi_snd_probe,
277         .read           = sh_hdmi_snd_read,
278         .write          = sh_hdmi_snd_write,
279 };
280
281 /*
282  *      HDMI video
283  */
284
285 /* External video parameter settings */
286 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
287 {
288         struct fb_var_screeninfo *var = &hdmi->var;
289         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
290         u8 sync = 0;
291
292         htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
293
294         hdelay = var->hsync_len + var->left_margin;
295         hblank = var->right_margin + hdelay;
296
297         /*
298          * Vertical timing looks a bit different in Figure 18,
299          * but let's try the same first by setting offset = 0
300          */
301         vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
302
303         vdelay = var->vsync_len + var->upper_margin;
304         vblank = var->lower_margin + vdelay;
305         voffset = min(var->upper_margin / 2, 6U);
306
307         /*
308          * [3]: VSYNC polarity: Positive
309          * [2]: HSYNC polarity: Positive
310          * [1]: Interlace/Progressive: Progressive
311          * [0]: External video settings enable: used.
312          */
313         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
314                 sync |= 4;
315         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
316                 sync |= 8;
317
318         dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
319                 htotal, hblank, hdelay, var->hsync_len,
320                 vtotal, vblank, vdelay, var->vsync_len, sync);
321
322         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
323
324         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
325         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
326
327         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
328         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
329
330         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
331         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
332
333         hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
334         hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
335
336         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
337         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
338
339         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
340
341         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
342
343         hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
344
345         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
346         if (!hdmi->preprogrammed_vic)
347                 hdmi_write(hdmi, sync | 1 | (voffset << 4),
348                            HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
349 }
350
351 /**
352  * sh_hdmi_video_config()
353  */
354 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
355 {
356         /*
357          * [7:4]: Audio sampling frequency: 48kHz
358          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
359          * [0]: Internal/External DE select: internal
360          */
361         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
362
363         /*
364          * [7:6]: Video output format: RGB 4:4:4
365          * [5:4]: Input video data width: 8 bit
366          * [3:1]: EAV/SAV location: channel 1
367          * [0]: Video input color space: RGB
368          */
369         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
370
371         /*
372          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
373          * left at 0 by default, this configures 24bpp and sets the Color Depth
374          * (CD) field in the General Control Packet
375          */
376         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
377 }
378
379 /**
380  * sh_hdmi_audio_config()
381  */
382 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
383 {
384         u8 data;
385         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
386
387         /*
388          * [7:4] L/R data swap control
389          * [3:0] appropriate N[19:16]
390          */
391         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
392         /* appropriate N[15:8] */
393         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
394         /* appropriate N[7:0] */
395         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
396
397         /* [7:4] 48 kHz SPDIF not used */
398         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
399
400         /*
401          * [6:5] set required down sampling rate if required
402          * [4:3] set required audio source
403          */
404         switch (pdata->flags & HDMI_SND_SRC_MASK) {
405         default:
406                 /* fall through */
407         case HDMI_SND_SRC_I2S:
408                 data = 0x0 << 3;
409                 break;
410         case HDMI_SND_SRC_SPDIF:
411                 data = 0x1 << 3;
412                 break;
413         case HDMI_SND_SRC_DSD:
414                 data = 0x2 << 3;
415                 break;
416         case HDMI_SND_SRC_HBR:
417                 data = 0x3 << 3;
418                 break;
419         }
420         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
421
422         /* [3:0] set sending channel number for channel status */
423         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
424
425         /*
426          * [5:2] set valid I2S source input pin
427          * [1:0] set input I2S source mode
428          */
429         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
430
431         /* [7:4] set valid DSD source input pin */
432         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
433
434         /* [7:0] set appropriate I2S input pin swap settings if required */
435         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
436
437         /*
438          * [7] set validity bit for channel status
439          * [3:0] set original sample frequency for channel status
440          */
441         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
442
443         /*
444          * [7] set value for channel status
445          * [6] set value for channel status
446          * [5] set copyright bit for channel status
447          * [4:2] set additional information for channel status
448          * [1:0] set clock accuracy for channel status
449          */
450         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
451
452         /* [7:0] set category code for channel status */
453         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
454
455         /*
456          * [7:4] set source number for channel status
457          * [3:0] set word length for channel status
458          */
459         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
460
461         /* [7:4] set sample frequency for channel status */
462         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
463 }
464
465 /**
466  * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
467  */
468 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
469 {
470         if (hdmi->var.pixclock < 10000) {
471                 /* for 1080p8bit 148MHz */
472                 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
473                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
474                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
475                 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
476                 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
477                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
478                 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
479                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
480                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
481         } else if (hdmi->var.pixclock < 30000) {
482                 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
483                 /*
484                  * [1:0]        Speed_A
485                  * [3:2]        Speed_B
486                  * [4]          PLLA_Bypass
487                  * [6]          DRV_TEST_EN
488                  * [7]          DRV_TEST_IN
489                  */
490                 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
491                 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
492                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
493                 /*
494                  * [2:0]        BGR_I_OFFSET
495                  * [6:4]        BGR_V_OFFSET
496                  */
497                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
498                 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
499                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
500                 /*
501                  * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
502                  * LPF capacitance, LPF resistance[1]
503                  */
504                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
505                 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
506                 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
507                 /*
508                  * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
509                  * LPF capacitance, LPF resistance[1]
510                  */
511                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
512                 /* DRV_CONFIG, PE_CONFIG */
513                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
514                 /*
515                  * [2:0]        AMON_SEL (4 == LPF voltage)
516                  * [4]          PLLA_CONFIG[16]
517                  * [5]          PLLB_CONFIG[16]
518                  */
519                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
520         } else {
521                 /* for 480p8bit 27MHz */
522                 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
523                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
524                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
525                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
526                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
527                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
528                 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
529                 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
530                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
531         }
532 }
533
534 /**
535  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
536  */
537 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
538 {
539         u8 vic;
540
541         /* AVI InfoFrame */
542         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
543
544         /* Packet Type = 0x82 */
545         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
546
547         /* Version = 0x02 */
548         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
549
550         /* Length = 13 (0x0D) */
551         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
552
553         /* N. A. Checksum */
554         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
555
556         /*
557          * Y = RGB
558          * A0 = No Data
559          * B = Bar Data not valid
560          * S = No Data
561          */
562         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
563
564         /*
565          * [7:6] C = Colorimetry: no data
566          * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
567          * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
568          */
569         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
570
571         /*
572          * ITC = No Data
573          * EC = xvYCC601
574          * Q = Default (depends on video format)
575          * SC = No Known non_uniform Scaling
576          */
577         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
578
579         /*
580          * VIC should be ignored if external config is used, so, we could just use 0,
581          * but play safe and use a valid value in any case just in case
582          */
583         if (hdmi->preprogrammed_vic)
584                 vic = hdmi->preprogrammed_vic;
585         else
586                 vic = 4;
587         hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
588
589         /* PR = No Repetition */
590         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
591
592         /* Line Number of End of Top Bar (lower 8 bits) */
593         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
594
595         /* Line Number of End of Top Bar (upper 8 bits) */
596         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
597
598         /* Line Number of Start of Bottom Bar (lower 8 bits) */
599         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
600
601         /* Line Number of Start of Bottom Bar (upper 8 bits) */
602         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
603
604         /* Pixel Number of End of Left Bar (lower 8 bits) */
605         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
606
607         /* Pixel Number of End of Left Bar (upper 8 bits) */
608         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
609
610         /* Pixel Number of Start of Right Bar (lower 8 bits) */
611         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
612
613         /* Pixel Number of Start of Right Bar (upper 8 bits) */
614         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
615 }
616
617 /**
618  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
619  */
620 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
621 {
622         /* Audio InfoFrame */
623         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
624
625         /* Packet Type = 0x84 */
626         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
627
628         /* Version Number = 0x01 */
629         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
630
631         /* 0 Length = 10 (0x0A) */
632         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
633
634         /* n. a. Checksum */
635         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
636
637         /* Audio Channel Count = Refer to Stream Header */
638         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
639
640         /* Refer to Stream Header */
641         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
642
643         /* Format depends on coding type (i.e. CT0...CT3) */
644         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
645
646         /* Speaker Channel Allocation = Front Right + Front Left */
647         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
648
649         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
650         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
651
652         /* Reserved (0) */
653         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
654         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
655         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
656         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
657         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
658 }
659
660 /**
661  * sh_hdmi_configure() - Initialise HDMI for output
662  */
663 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
664 {
665         /* Configure video format */
666         sh_hdmi_video_config(hdmi);
667
668         /* Configure audio format */
669         sh_hdmi_audio_config(hdmi);
670
671         /* Configure PHY */
672         sh_hdmi_phy_config(hdmi);
673
674         /* Auxiliary Video Information (AVI) InfoFrame */
675         sh_hdmi_avi_infoframe_setup(hdmi);
676
677         /* Audio InfoFrame */
678         sh_hdmi_audio_infoframe_setup(hdmi);
679
680         /*
681          * Control packet auto send with VSYNC control: auto send
682          * General control, Gamut metadata, ISRC, and ACP packets
683          */
684         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
685
686         /* FIXME */
687         msleep(10);
688
689         /* PS mode b->d, reset PLLA and PLLB */
690         hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
691
692         udelay(10);
693
694         hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
695 }
696
697 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
698                 const struct fb_videomode *mode,
699                 unsigned long *hdmi_rate, unsigned long *parent_rate)
700 {
701         unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
702         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
703
704         *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
705         if ((long)*hdmi_rate < 0)
706                 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
707
708         rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
709         if (rate_error && pdata->clk_optimize_parent)
710                 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
711         else if (clk_get_parent(hdmi->hdmi_clk))
712                 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
713
714         dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
715                 mode->left_margin, mode->xres,
716                 mode->right_margin, mode->hsync_len,
717                 mode->upper_margin, mode->yres,
718                 mode->lower_margin, mode->vsync_len);
719
720         dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
721                 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
722                 mode->refresh, *parent_rate);
723
724         return rate_error;
725 }
726
727 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
728                              unsigned long *parent_rate)
729 {
730         struct fb_var_screeninfo tmpvar;
731         struct fb_var_screeninfo *var = &tmpvar;
732         const struct fb_videomode *mode, *found = NULL;
733         struct fb_info *info = hdmi->info;
734         struct fb_modelist *modelist = NULL;
735         unsigned int f_width = 0, f_height = 0, f_refresh = 0;
736         unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
737         bool exact_match = false;
738         u8 edid[128];
739         char *forced;
740         int i;
741
742         /* Read EDID */
743         dev_dbg(hdmi->dev, "Read back EDID code:");
744         for (i = 0; i < 128; i++) {
745                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
746 #ifdef DEBUG
747                 if ((i % 16) == 0) {
748                         printk(KERN_CONT "\n");
749                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
750                 } else {
751                         printk(KERN_CONT " %02X", edid[i]);
752                 }
753 #endif
754         }
755 #ifdef DEBUG
756         printk(KERN_CONT "\n");
757 #endif
758
759         fb_edid_to_monspecs(edid, &hdmi->monspec);
760
761         fb_get_options("sh_mobile_lcdc", &forced);
762         if (forced && *forced) {
763                 /* Only primitive parsing so far */
764                 i = sscanf(forced, "%ux%u@%u",
765                            &f_width, &f_height, &f_refresh);
766                 if (i < 2) {
767                         f_width = 0;
768                         f_height = 0;
769                 }
770                 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
771                         f_width, f_height, f_refresh);
772         }
773
774         /* Walk monitor modes to find the best or the exact match */
775         for (i = 0, mode = hdmi->monspec.modedb;
776              f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
777              i++, mode++) {
778                 unsigned long rate_error;
779
780                 /* No interest in unmatching modes */
781                 if (f_width != mode->xres || f_height != mode->yres)
782                         continue;
783
784                 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
785
786                 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
787                         /*
788                          * Exact match if either the refresh rate matches or it
789                          * hasn't been specified and we've found a mode, for
790                          * which we can configure the clock precisely
791                          */
792                         exact_match = true;
793                 else if (found && found_rate_error <= rate_error)
794                         /*
795                          * We otherwise search for the closest matching clock
796                          * rate - either if no refresh rate has been specified
797                          * or we cannot find an exactly matching one
798                          */
799                         continue;
800
801                 /* Check if supported: sufficient fb memory, supported clock-rate */
802                 fb_videomode_to_var(var, mode);
803
804                 if (info && info->fbops->fb_check_var &&
805                     info->fbops->fb_check_var(var, info)) {
806                         exact_match = false;
807                         continue;
808                 }
809
810                 found = mode;
811                 found_rate_error = rate_error;
812         }
813
814         /*
815          * TODO 1: if no ->info is present, postpone running the config until
816          * after ->info first gets registered.
817          * TODO 2: consider registering the HDMI platform device from the LCDC
818          * driver, and passing ->info with HDMI platform data.
819          */
820         if (info && !found) {
821                 modelist = hdmi->info->modelist.next &&
822                         !list_empty(&hdmi->info->modelist) ?
823                         list_entry(hdmi->info->modelist.next,
824                                    struct fb_modelist, list) :
825                         NULL;
826
827                 if (modelist) {
828                         found = &modelist->mode;
829                         found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
830                 }
831         }
832
833         /* No cookie today */
834         if (!found)
835                 return -ENXIO;
836
837         if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
838                 hdmi->preprogrammed_vic = 1;
839         else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
840                 hdmi->preprogrammed_vic = 2;
841         else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
842                 hdmi->preprogrammed_vic = 17;
843         else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
844                 hdmi->preprogrammed_vic = 4;
845         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
846                 hdmi->preprogrammed_vic = 32;
847         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
848                 hdmi->preprogrammed_vic = 31;
849         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
850                 hdmi->preprogrammed_vic = 16;
851         else
852                 hdmi->preprogrammed_vic = 0;
853
854         dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
855                 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
856                 found->xres, found->yres, found->refresh,
857                 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
858
859         fb_videomode_to_var(&hdmi->var, found);
860         sh_hdmi_external_video_param(hdmi);
861
862         return 0;
863 }
864
865 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
866 {
867         struct sh_hdmi *hdmi = dev_id;
868         u8 status1, status2, mask1, mask2;
869
870         /* mode_b and PLLA and PLLB reset */
871         hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
872
873         /* How long shall reset be held? */
874         udelay(10);
875
876         /* mode_b and PLLA and PLLB reset release */
877         hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
878
879         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
880         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
881
882         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
883         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
884
885         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
886         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
887         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
888
889         if (printk_ratelimit())
890                 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
891                         irq, status1, mask1, status2, mask2);
892
893         if (!((status1 & mask1) | (status2 & mask2))) {
894                 return IRQ_NONE;
895         } else if (status1 & 0xc0) {
896                 u8 msens;
897
898                 /* Datasheet specifies 10ms... */
899                 udelay(500);
900
901                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
902                 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
903                 /* Check, if hot plug & MSENS pin status are both high */
904                 if ((msens & 0xC0) == 0xC0) {
905                         /* Display plug in */
906                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
907
908                         /* Set EDID word address  */
909                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
910                         /* Set EDID segment pointer */
911                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
912                         /* Enable EDID interrupt */
913                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
914                 } else if (!(status1 & 0x80)) {
915                         /* Display unplug, beware multiple interrupts */
916                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
917                                 schedule_delayed_work(&hdmi->edid_work, 0);
918
919                         hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
920                         /* display_off will switch back to mode_a */
921                 }
922         } else if (status1 & 2) {
923                 /* EDID error interrupt: retry */
924                 /* Set EDID word address  */
925                 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
926                 /* Set EDID segment pointer */
927                 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
928         } else if (status1 & 4) {
929                 /* Disable EDID interrupt */
930                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
931                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
932                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
933         }
934
935         return IRQ_HANDLED;
936 }
937
938 /* locking:     called with info->lock held, or before register_framebuffer() */
939 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
940 {
941         /*
942          * info is guaranteed to be valid, when we are called, because our
943          * FB_EVENT_FB_UNBIND notify is also called with info->lock held
944          */
945         struct sh_hdmi *hdmi = arg;
946         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
947         struct sh_mobile_lcdc_chan *ch = info->par;
948
949         dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
950                 pdata->lcd_dev, info->state);
951
952         /* No need to lock */
953         hdmi->info = info;
954
955         /*
956          * hp_state can be set to
957          * HDMI_HOTPLUG_DISCONNECTED:   on monitor unplug
958          * HDMI_HOTPLUG_CONNECTED:      on monitor plug-in
959          * HDMI_HOTPLUG_EDID_DONE:      on EDID read completion
960          */
961         switch (hdmi->hp_state) {
962         case HDMI_HOTPLUG_EDID_DONE:
963                 /* PS mode d->e. All functions are active */
964                 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
965                 dev_dbg(hdmi->dev, "HDMI running\n");
966                 break;
967         case HDMI_HOTPLUG_DISCONNECTED:
968                 info->state = FBINFO_STATE_SUSPENDED;
969         default:
970                 hdmi->var = ch->display_var;
971         }
972 }
973
974 /* locking: called with info->lock held */
975 static void sh_hdmi_display_off(void *arg)
976 {
977         struct sh_hdmi *hdmi = arg;
978         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
979
980         dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
981         /* PS mode e->a */
982         hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
983 }
984
985 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
986 {
987         struct fb_info *info = hdmi->info;
988         struct sh_mobile_lcdc_chan *ch = info->par;
989         struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
990         struct fb_videomode mode1, mode2;
991
992         fb_var_to_videomode(&mode1, old_var);
993         fb_var_to_videomode(&mode2, new_var);
994
995         dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
996                 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
997
998         if (fb_mode_is_equal(&mode1, &mode2))
999                 return false;
1000
1001         dev_dbg(info->dev, "Switching %u -> %u lines\n",
1002                 mode1.yres, mode2.yres);
1003         *old_var = *new_var;
1004
1005         return true;
1006 }
1007
1008 /**
1009  * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1010  * @hdmi:               driver context
1011  * @hdmi_rate:          HDMI clock frequency in Hz
1012  * @parent_rate:        if != 0 - set parent clock rate for optimal precision
1013  * return:              configured positive rate if successful
1014  *                      0 if couldn't set the rate, but managed to enable the
1015  *                      clock, negative error, if couldn't enable the clock
1016  */
1017 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1018                                   unsigned long parent_rate)
1019 {
1020         int ret;
1021
1022         if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1023                 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1024                 if (ret < 0) {
1025                         dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1026                         hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1027                 } else {
1028                         dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1029                 }
1030         }
1031
1032         ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1033         if (ret < 0) {
1034                 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1035                 hdmi_rate = 0;
1036         } else {
1037                 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1038         }
1039
1040         return hdmi_rate;
1041 }
1042
1043 /* Hotplug interrupt occurred, read EDID */
1044 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1045 {
1046         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1047         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1048         struct sh_mobile_lcdc_chan *ch;
1049         int ret;
1050
1051         dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1052                 pdata->lcd_dev, hdmi->hp_state);
1053
1054         if (!pdata->lcd_dev)
1055                 return;
1056
1057         mutex_lock(&hdmi->mutex);
1058
1059         if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
1060                 unsigned long parent_rate = 0, hdmi_rate;
1061
1062                 /* A device has been plugged in */
1063                 pm_runtime_get_sync(hdmi->dev);
1064
1065                 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1066                 if (ret < 0)
1067                         goto out;
1068
1069                 /* Reconfigure the clock */
1070                 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1071                 if (ret < 0)
1072                         goto out;
1073
1074                 msleep(10);
1075                 sh_hdmi_configure(hdmi);
1076                 /* Switched to another (d) power-save mode */
1077                 msleep(10);
1078
1079                 if (!hdmi->info)
1080                         goto out;
1081
1082                 ch = hdmi->info->par;
1083
1084                 acquire_console_sem();
1085
1086                 /* HDMI plug in */
1087                 if (!sh_hdmi_must_reconfigure(hdmi) &&
1088                     hdmi->info->state == FBINFO_STATE_RUNNING) {
1089                         /*
1090                          * First activation with the default monitor - just turn
1091                          * on, if we run a resume here, the logo disappears
1092                          */
1093                         if (lock_fb_info(hdmi->info)) {
1094                                 sh_hdmi_display_on(hdmi, hdmi->info);
1095                                 unlock_fb_info(hdmi->info);
1096                         }
1097                 } else {
1098                         /* New monitor or have to wake up */
1099                         fb_set_suspend(hdmi->info, 0);
1100                 }
1101
1102                 release_console_sem();
1103         } else {
1104                 ret = 0;
1105                 if (!hdmi->info)
1106                         goto out;
1107
1108                 hdmi->monspec.modedb_len = 0;
1109                 fb_destroy_modedb(hdmi->monspec.modedb);
1110                 hdmi->monspec.modedb = NULL;
1111
1112                 acquire_console_sem();
1113
1114                 /* HDMI disconnect */
1115                 fb_set_suspend(hdmi->info, 1);
1116
1117                 release_console_sem();
1118                 pm_runtime_put(hdmi->dev);
1119         }
1120
1121 out:
1122         if (ret < 0)
1123                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1124         mutex_unlock(&hdmi->mutex);
1125
1126         dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
1127 }
1128
1129 static int sh_hdmi_notify(struct notifier_block *nb,
1130                           unsigned long action, void *data);
1131
1132 static struct notifier_block sh_hdmi_notifier = {
1133         .notifier_call = sh_hdmi_notify,
1134 };
1135
1136 static int sh_hdmi_notify(struct notifier_block *nb,
1137                           unsigned long action, void *data)
1138 {
1139         struct fb_event *event = data;
1140         struct fb_info *info = event->info;
1141         struct sh_mobile_lcdc_chan *ch = info->par;
1142         struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1143         struct sh_hdmi *hdmi = board_cfg->board_data;
1144
1145         if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
1146                 return NOTIFY_DONE;
1147
1148         switch(action) {
1149         case FB_EVENT_FB_REGISTERED:
1150                 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1151                 break;
1152         case FB_EVENT_FB_UNREGISTERED:
1153                 /*
1154                  * We are called from unregister_framebuffer() with the
1155                  * info->lock held. This is bad for us, because we can race with
1156                  * the scheduled work, which has to call fb_set_suspend(), which
1157                  * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1158                  * cannot take and hold info->lock for the whole function
1159                  * duration. Using an additional lock creates a classical AB-BA
1160                  * lock up. Therefore, we have to release the info->lock
1161                  * temporarily, synchronise with the work queue and re-acquire
1162                  * the info->lock.
1163                  */
1164                 unlock_fb_info(hdmi->info);
1165                 mutex_lock(&hdmi->mutex);
1166                 hdmi->info = NULL;
1167                 mutex_unlock(&hdmi->mutex);
1168                 lock_fb_info(hdmi->info);
1169                 return NOTIFY_OK;
1170         }
1171         return NOTIFY_DONE;
1172 }
1173
1174 static int __init sh_hdmi_probe(struct platform_device *pdev)
1175 {
1176         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1177         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1178         struct sh_mobile_lcdc_board_cfg *board_cfg;
1179         int irq = platform_get_irq(pdev, 0), ret;
1180         struct sh_hdmi *hdmi;
1181         long rate;
1182
1183         if (!res || !pdata || irq < 0)
1184                 return -ENODEV;
1185
1186         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1187         if (!hdmi) {
1188                 dev_err(&pdev->dev, "Cannot allocate device data\n");
1189                 return -ENOMEM;
1190         }
1191
1192         mutex_init(&hdmi->mutex);
1193
1194         hdmi->dev = &pdev->dev;
1195
1196         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1197         if (IS_ERR(hdmi->hdmi_clk)) {
1198                 ret = PTR_ERR(hdmi->hdmi_clk);
1199                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1200                 goto egetclk;
1201         }
1202
1203         /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1204         rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1205         if (rate > 0)
1206                 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1207
1208         if (rate < 0) {
1209                 ret = rate;
1210                 goto erate;
1211         }
1212
1213         ret = clk_enable(hdmi->hdmi_clk);
1214         if (ret < 0) {
1215                 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1216                 goto erate;
1217         }
1218
1219         dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1220
1221         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1222                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1223                 ret = -EBUSY;
1224                 goto ereqreg;
1225         }
1226
1227         hdmi->base = ioremap(res->start, resource_size(res));
1228         if (!hdmi->base) {
1229                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1230                 ret = -ENOMEM;
1231                 goto emap;
1232         }
1233
1234         platform_set_drvdata(pdev, hdmi);
1235
1236         /* Set up LCDC callbacks */
1237         board_cfg = &pdata->lcd_chan->board_cfg;
1238         board_cfg->owner = THIS_MODULE;
1239         board_cfg->board_data = hdmi;
1240         board_cfg->display_on = sh_hdmi_display_on;
1241         board_cfg->display_off = sh_hdmi_display_off;
1242
1243         INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1244
1245         pm_runtime_enable(&pdev->dev);
1246         pm_runtime_resume(&pdev->dev);
1247
1248         /* Product and revision IDs are 0 in sh-mobile version */
1249         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1250                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1251
1252         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1253                           dev_name(&pdev->dev), hdmi);
1254         if (ret < 0) {
1255                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1256                 goto ereqirq;
1257         }
1258
1259         ret = snd_soc_register_codec(&pdev->dev,
1260                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1261         if (ret < 0) {
1262                 dev_err(&pdev->dev, "codec registration failed\n");
1263                 goto ecodec;
1264         }
1265
1266         return 0;
1267
1268 ecodec:
1269         free_irq(irq, hdmi);
1270 ereqirq:
1271         pm_runtime_disable(&pdev->dev);
1272         iounmap(hdmi->base);
1273 emap:
1274         release_mem_region(res->start, resource_size(res));
1275 ereqreg:
1276         clk_disable(hdmi->hdmi_clk);
1277 erate:
1278         clk_put(hdmi->hdmi_clk);
1279 egetclk:
1280         mutex_destroy(&hdmi->mutex);
1281         kfree(hdmi);
1282
1283         return ret;
1284 }
1285
1286 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1287 {
1288         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1289         struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1290         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1291         struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1292         int irq = platform_get_irq(pdev, 0);
1293
1294         snd_soc_unregister_codec(&pdev->dev);
1295
1296         board_cfg->display_on = NULL;
1297         board_cfg->display_off = NULL;
1298         board_cfg->board_data = NULL;
1299         board_cfg->owner = NULL;
1300
1301         /* No new work will be scheduled, wait for running ISR */
1302         free_irq(irq, hdmi);
1303         /* Wait for already scheduled work */
1304         cancel_delayed_work_sync(&hdmi->edid_work);
1305         pm_runtime_disable(&pdev->dev);
1306         clk_disable(hdmi->hdmi_clk);
1307         clk_put(hdmi->hdmi_clk);
1308         iounmap(hdmi->base);
1309         release_mem_region(res->start, resource_size(res));
1310         mutex_destroy(&hdmi->mutex);
1311         kfree(hdmi);
1312
1313         return 0;
1314 }
1315
1316 static struct platform_driver sh_hdmi_driver = {
1317         .remove         = __exit_p(sh_hdmi_remove),
1318         .driver = {
1319                 .name   = "sh-mobile-hdmi",
1320         },
1321 };
1322
1323 static int __init sh_hdmi_init(void)
1324 {
1325         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1326 }
1327 module_init(sh_hdmi_init);
1328
1329 static void __exit sh_hdmi_exit(void)
1330 {
1331         platform_driver_unregister(&sh_hdmi_driver);
1332 }
1333 module_exit(sh_hdmi_exit);
1334
1335 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1336 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1337 MODULE_LICENSE("GPL v2");