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[~shefty/rdma-dev.git] / drivers / video / via / dvi.c
1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21 #include <linux/via-core.h>
22 #include <linux/via_i2c.h>
23 #include "global.h"
24
25 static void tmds_register_write(int index, u8 data);
26 static int tmds_register_read(int index);
27 static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
28 static void __devinit dvi_get_panel_size_from_DDCv1(
29         struct tmds_chip_information *tmds_chip,
30         struct tmds_setting_information *tmds_setting);
31 static void __devinit dvi_get_panel_size_from_DDCv2(
32         struct tmds_chip_information *tmds_chip,
33         struct tmds_setting_information *tmds_setting);
34 static int viafb_dvi_query_EDID(void);
35
36 static int check_tmds_chip(int device_id_subaddr, int device_id)
37 {
38         if (tmds_register_read(device_id_subaddr) == device_id)
39                 return OK;
40         else
41                 return FAIL;
42 }
43
44 void __devinit viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
45         struct tmds_setting_information *tmds_setting)
46 {
47         DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
48
49         viafb_dvi_sense();
50         switch (viafb_dvi_query_EDID()) {
51         case 1:
52                 dvi_get_panel_size_from_DDCv1(tmds_chip, tmds_setting);
53                 break;
54         case 2:
55                 dvi_get_panel_size_from_DDCv2(tmds_chip, tmds_setting);
56                 break;
57         default:
58                 printk(KERN_WARNING "viafb_init_dvi_size: DVI panel size undetected!\n");
59                 break;
60         }
61
62         return;
63 }
64
65 int __devinit viafb_tmds_trasmitter_identify(void)
66 {
67         unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
68
69         /* Turn on ouputting pad */
70         switch (viaparinfo->chip_info->gfx_chip_name) {
71         case UNICHROME_K8M890:
72             /*=* DFP Low Pad on *=*/
73                 sr2a = viafb_read_reg(VIASR, SR2A);
74                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
75                 break;
76
77         case UNICHROME_P4M900:
78         case UNICHROME_P4M890:
79                 /* DFP Low Pad on */
80                 sr2a = viafb_read_reg(VIASR, SR2A);
81                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
82                 /* DVP0 Pad on */
83                 sr1e = viafb_read_reg(VIASR, SR1E);
84                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
85                 break;
86
87         default:
88             /* DVP0/DVP1 Pad on */
89                 sr1e = viafb_read_reg(VIASR, SR1E);
90                 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
91                         BIT5 + BIT6 + BIT7);
92             /* SR3E[1]Multi-function selection:
93             0 = Emulate I2C and DDC bus by GPIO2/3/4. */
94                 sr3e = viafb_read_reg(VIASR, SR3E);
95                 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
96                 break;
97         }
98
99         /* Check for VT1632: */
100         viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS;
101         viaparinfo->chip_info->
102                 tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
103         viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_31;
104         if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID) != FAIL) {
105                 /*
106                  * Currently only support 12bits,dual edge,add 24bits mode later
107                  */
108                 tmds_register_write(0x08, 0x3b);
109
110                 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
111                 DEBUG_MSG(KERN_INFO "\n %2d",
112                           viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
113                 DEBUG_MSG(KERN_INFO "\n %2d",
114                           viaparinfo->chip_info->tmds_chip_info.i2c_port);
115                 return OK;
116         } else {
117                 viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_2C;
118                 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)
119                     != FAIL) {
120                         tmds_register_write(0x08, 0x3b);
121                         DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
122                         DEBUG_MSG(KERN_INFO "\n %2d",
123                                   viaparinfo->chip_info->
124                                   tmds_chip_info.tmds_chip_name);
125                         DEBUG_MSG(KERN_INFO "\n %2d",
126                                   viaparinfo->chip_info->
127                                   tmds_chip_info.i2c_port);
128                         return OK;
129                 }
130         }
131
132         viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS;
133
134         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) &&
135             ((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) ||
136              (viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) {
137                 DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n");
138                 return OK;
139         }
140
141         switch (viaparinfo->chip_info->gfx_chip_name) {
142         case UNICHROME_K8M890:
143                 viafb_write_reg(SR2A, VIASR, sr2a);
144                 break;
145
146         case UNICHROME_P4M900:
147         case UNICHROME_P4M890:
148                 viafb_write_reg(SR2A, VIASR, sr2a);
149                 viafb_write_reg(SR1E, VIASR, sr1e);
150                 break;
151
152         default:
153                 viafb_write_reg(SR1E, VIASR, sr1e);
154                 viafb_write_reg(SR3E, VIASR, sr3e);
155                 break;
156         }
157
158         viaparinfo->chip_info->
159                 tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER;
160         viaparinfo->chip_info->tmds_chip_info.
161                 tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
162         return FAIL;
163 }
164
165 static void tmds_register_write(int index, u8 data)
166 {
167         viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
168                             viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
169                             index, data);
170 }
171
172 static int tmds_register_read(int index)
173 {
174         u8 data;
175
176         viafb_i2c_readbyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
177                            (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
178                            (u8) index, &data);
179         return data;
180 }
181
182 static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
183 {
184         viafb_i2c_readbytes(viaparinfo->chip_info->tmds_chip_info.i2c_port,
185                             (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
186                             (u8) index, buff, buff_len);
187         return 0;
188 }
189
190 /* DVI Set Mode */
191 void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
192         int set_iga)
193 {
194         struct VideoModeTable *rb_mode;
195         struct crt_mode_table *pDviTiming;
196         unsigned long desirePixelClock, maxPixelClock;
197         pDviTiming = mode->crtc;
198         desirePixelClock = pDviTiming->clk / 1000000;
199         maxPixelClock = (unsigned long)viaparinfo->
200                 tmds_setting_info->max_pixel_clock;
201
202         DEBUG_MSG(KERN_INFO "\nDVI_set_mode!!\n");
203
204         if ((maxPixelClock != 0) && (desirePixelClock > maxPixelClock)) {
205                 rb_mode = viafb_get_rb_mode(mode->crtc[0].crtc.hor_addr,
206                         mode->crtc[0].crtc.ver_addr);
207                 if (rb_mode) {
208                         mode = rb_mode;
209                         pDviTiming = rb_mode->crtc;
210                 }
211         }
212         viafb_fill_crtc_timing(pDviTiming, mode, mode_bpp / 8, set_iga);
213 }
214
215 /* Sense DVI Connector */
216 int viafb_dvi_sense(void)
217 {
218         u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,
219                 RegCR93 = 0, RegCR9B = 0, data;
220         int ret = false;
221
222         DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n");
223
224         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
225                 /* DI1 Pad on */
226                 RegSR1E = viafb_read_reg(VIASR, SR1E);
227                 viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);
228
229                 /* CR6B[0]VCK Input Selection: 1 = External clock. */
230                 RegCR6B = viafb_read_reg(VIACR, CR6B);
231                 viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);
232
233                 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
234                    [0] Software Control Power Sequence */
235                 RegCR91 = viafb_read_reg(VIACR, CR91);
236                 viafb_write_reg(CR91, VIACR, 0x1D);
237
238                 /* CR93[7] DI1 Data Source Selection: 1 = DSP2.
239                    CR93[5] DI1 Clock Source: 1 = internal.
240                    CR93[4] DI1 Clock Polarity.
241                    CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */
242                 RegCR93 = viafb_read_reg(VIACR, CR93);
243                 viafb_write_reg(CR93, VIACR, 0x01);
244         } else {
245                 /* DVP0/DVP1 Pad on */
246                 RegSR1E = viafb_read_reg(VIASR, SR1E);
247                 viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);
248
249                 /* SR3E[1]Multi-function selection:
250                    0 = Emulate I2C and DDC bus by GPIO2/3/4. */
251                 RegSR3E = viafb_read_reg(VIASR, SR3E);
252                 viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));
253
254                 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
255                    [0] Software Control Power Sequence */
256                 RegCR91 = viafb_read_reg(VIACR, CR91);
257                 viafb_write_reg(CR91, VIACR, 0x1D);
258
259                 /*CR9B[4] DVP1 Data Source Selection: 1 = From secondary
260                 display.CR9B[2:0] DVP1 Clock Adjust */
261                 RegCR9B = viafb_read_reg(VIACR, CR9B);
262                 viafb_write_reg(CR9B, VIACR, 0x01);
263         }
264
265         data = (u8) tmds_register_read(0x09);
266         if (data & 0x04)
267                 ret = true;
268
269         if (ret == false) {
270                 if (viafb_dvi_query_EDID())
271                         ret = true;
272         }
273
274         /* Restore status */
275         viafb_write_reg(SR1E, VIASR, RegSR1E);
276         viafb_write_reg(CR91, VIACR, RegCR91);
277         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
278                 viafb_write_reg(CR6B, VIACR, RegCR6B);
279                 viafb_write_reg(CR93, VIACR, RegCR93);
280         } else {
281                 viafb_write_reg(SR3E, VIASR, RegSR3E);
282                 viafb_write_reg(CR9B, VIACR, RegCR9B);
283         }
284
285         return ret;
286 }
287
288 /* Query Flat Panel's EDID Table Version Through DVI Connector */
289 static int viafb_dvi_query_EDID(void)
290 {
291         u8 data0, data1;
292         int restore;
293
294         DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");
295
296         restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
297         viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
298
299         data0 = (u8) tmds_register_read(0x00);
300         data1 = (u8) tmds_register_read(0x01);
301         if ((data0 == 0) && (data1 == 0xFF)) {
302                 viaparinfo->chip_info->
303                         tmds_chip_info.tmds_chip_slave_addr = restore;
304                 return EDID_VERSION_1;  /* Found EDID1 Table */
305         }
306
307         data0 = (u8) tmds_register_read(0x00);
308         viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
309         if (data0 == 0x20)
310                 return EDID_VERSION_2;  /* Found EDID2 Table */
311         else
312                 return false;
313 }
314
315 /* Get Panel Size Using EDID1 Table */
316 static void __devinit dvi_get_panel_size_from_DDCv1(
317         struct tmds_chip_information *tmds_chip,
318         struct tmds_setting_information *tmds_setting)
319 {
320         int i, max_h = 0, tmp, restore;
321         unsigned char rData;
322         unsigned char EDID_DATA[18];
323
324         DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
325
326         restore = tmds_chip->tmds_chip_slave_addr;
327         tmds_chip->tmds_chip_slave_addr = 0xA0;
328
329         rData = tmds_register_read(0x23);
330         if (rData & 0x3C)
331                 max_h = 640;
332         if (rData & 0xC0)
333                 max_h = 720;
334         if (rData & 0x03)
335                 max_h = 800;
336
337         rData = tmds_register_read(0x24);
338         if (rData & 0xC0)
339                 max_h = 800;
340         if (rData & 0x1E)
341                 max_h = 1024;
342         if (rData & 0x01)
343                 max_h = 1280;
344
345         for (i = 0x25; i < 0x6D; i++) {
346                 switch (i) {
347                 case 0x26:
348                 case 0x28:
349                 case 0x2A:
350                 case 0x2C:
351                 case 0x2E:
352                 case 0x30:
353                 case 0x32:
354                 case 0x34:
355                         rData = tmds_register_read(i);
356                         if (rData == 1)
357                                 break;
358                         /* data = (data + 31) * 8 */
359                         tmp = (rData + 31) << 3;
360                         if (tmp > max_h)
361                                 max_h = tmp;
362                         break;
363
364                 case 0x36:
365                 case 0x48:
366                 case 0x5A:
367                 case 0x6C:
368                         tmds_register_read_bytes(i, EDID_DATA, 10);
369                         if (!(EDID_DATA[0] || EDID_DATA[1])) {
370                                 /* The first two byte must be zero. */
371                                 if (EDID_DATA[3] == 0xFD) {
372                                         /* To get max pixel clock. */
373                                         tmds_setting->max_pixel_clock =
374                                                 EDID_DATA[9] * 10;
375                                 }
376                         }
377                         break;
378
379                 default:
380                         break;
381                 }
382         }
383
384         tmds_setting->max_hres = max_h;
385         switch (max_h) {
386         case 640:
387                 tmds_setting->max_vres = 480;
388                 break;
389         case 800:
390                 tmds_setting->max_vres = 600;
391                 break;
392         case 1024:
393                 tmds_setting->max_vres = 768;
394                 break;
395         case 1280:
396                 tmds_setting->max_vres = 1024;
397                 break;
398         case 1400:
399                 tmds_setting->max_vres = 1050;
400                 break;
401         case 1440:
402                 tmds_setting->max_vres = 1050;
403                 break;
404         case 1600:
405                 tmds_setting->max_vres = 1200;
406                 break;
407         case 1920:
408                 tmds_setting->max_vres = 1080;
409                 break;
410         default:
411                 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d ! "
412                                          "set default panel size.\n", max_h);
413                 break;
414         }
415
416         DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
417                 tmds_setting->max_pixel_clock);
418         tmds_chip->tmds_chip_slave_addr = restore;
419 }
420
421 /* Get Panel Size Using EDID2 Table */
422 static void __devinit dvi_get_panel_size_from_DDCv2(
423         struct tmds_chip_information *tmds_chip,
424         struct tmds_setting_information *tmds_setting)
425 {
426         int restore;
427         unsigned char R_Buffer[2];
428
429         DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv2 \n");
430
431         restore = tmds_chip->tmds_chip_slave_addr;
432         tmds_chip->tmds_chip_slave_addr = 0xA2;
433
434         /* Horizontal: 0x76, 0x77 */
435         tmds_register_read_bytes(0x76, R_Buffer, 2);
436         tmds_setting->max_hres = R_Buffer[0] + (R_Buffer[1] << 8);
437
438         switch (tmds_setting->max_hres) {
439         case 640:
440                 tmds_setting->max_vres = 480;
441                 break;
442         case 800:
443                 tmds_setting->max_vres = 600;
444                 break;
445         case 1024:
446                 tmds_setting->max_vres = 768;
447                 break;
448         case 1280:
449                 tmds_setting->max_vres = 1024;
450                 break;
451         case 1400:
452                 tmds_setting->max_vres = 1050;
453                 break;
454         case 1440:
455                 tmds_setting->max_vres = 1050;
456                 break;
457         case 1600:
458                 tmds_setting->max_vres = 1200;
459                 break;
460         default:
461                 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d! "
462                         "set default panel size.\n", tmds_setting->max_hres);
463                 break;
464         }
465
466         tmds_chip->tmds_chip_slave_addr = restore;
467 }
468
469 /* If Disable DVI, turn off pad */
470 void viafb_dvi_disable(void)
471 {
472         if (viaparinfo->chip_info->
473                 tmds_chip_info.output_interface == INTERFACE_DVP0)
474                 viafb_write_reg(SR1E, VIASR,
475                 viafb_read_reg(VIASR, SR1E) & (~0xC0));
476
477         if (viaparinfo->chip_info->
478                 tmds_chip_info.output_interface == INTERFACE_DVP1)
479                 viafb_write_reg(SR1E, VIASR,
480                 viafb_read_reg(VIASR, SR1E) & (~0x30));
481
482         if (viaparinfo->chip_info->
483                 tmds_chip_info.output_interface == INTERFACE_DFP_HIGH)
484                 viafb_write_reg(SR2A, VIASR,
485                 viafb_read_reg(VIASR, SR2A) & (~0x0C));
486
487         if (viaparinfo->chip_info->
488                 tmds_chip_info.output_interface == INTERFACE_DFP_LOW)
489                 viafb_write_reg(SR2A, VIASR,
490                 viafb_read_reg(VIASR, SR2A) & (~0x03));
491
492         if (viaparinfo->chip_info->
493                 tmds_chip_info.output_interface == INTERFACE_TMDS)
494                 /* Turn off TMDS power. */
495                 viafb_write_reg(CRD2, VIACR,
496                 viafb_read_reg(VIACR, CRD2) | 0x08);
497 }
498
499 static void dvi_patch_skew_dvp0(void)
500 {
501         /* Reset data driving first: */
502         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
503         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
504
505         switch (viaparinfo->chip_info->gfx_chip_name) {
506         case UNICHROME_P4M890:
507                 {
508                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
509                                 (viaparinfo->tmds_setting_info->v_active ==
510                                 1200))
511                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
512                                                BIT0 + BIT1 + BIT2);
513                         else
514                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
515                                                BIT0 + BIT1 + BIT2);
516                         break;
517                 }
518
519         case UNICHROME_P4M900:
520                 {
521                         viafb_write_reg_mask(CR96, VIACR, 0x07,
522                                        BIT0 + BIT1 + BIT2 + BIT3);
523                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
524                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
525                         break;
526                 }
527
528         default:
529                 {
530                         break;
531                 }
532         }
533 }
534
535 static void dvi_patch_skew_dvp_low(void)
536 {
537         switch (viaparinfo->chip_info->gfx_chip_name) {
538         case UNICHROME_K8M890:
539                 {
540                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
541                         break;
542                 }
543
544         case UNICHROME_P4M900:
545                 {
546                         viafb_write_reg_mask(CR99, VIACR, 0x08,
547                                        BIT0 + BIT1 + BIT2 + BIT3);
548                         break;
549                 }
550
551         case UNICHROME_P4M890:
552                 {
553                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
554                                        BIT0 + BIT1 + BIT2 + BIT3);
555                         break;
556                 }
557
558         default:
559                 {
560                         break;
561                 }
562         }
563 }
564
565 /* If Enable DVI, turn off pad */
566 void viafb_dvi_enable(void)
567 {
568         u8 data;
569
570         switch (viaparinfo->chip_info->tmds_chip_info.output_interface) {
571         case INTERFACE_DVP0:
572                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
573                 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
574                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
575                 dvi_patch_skew_dvp0();
576                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
577                         tmds_register_write(0x88, 0x3b);
578                 else
579                         /*clear CR91[5] to direct on display period
580                            in the secondary diplay path */
581                         via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
582                 break;
583
584         case INTERFACE_DVP1:
585                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
586                         viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
587
588                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
589                 /*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
590                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
591                         tmds_register_write(0x88, 0x3b);
592                 else
593                         /*clear CR91[5] to direct on display period
594                           in the secondary diplay path */
595                         via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
596
597                 /*fix DVI cannot enable on EPIA-M board */
598                 if (viafb_platform_epia_dvi == 1) {
599                         viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
600                         viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
601                         if (viafb_bus_width == 24) {
602                                 if (viafb_device_lcd_dualedge == 1)
603                                         data = 0x3F;
604                                 else
605                                         data = 0x37;
606                                 viafb_i2c_writebyte(viaparinfo->chip_info->
607                                         tmds_chip_info.i2c_port,
608                                         viaparinfo->chip_info->
609                                         tmds_chip_info.tmds_chip_slave_addr,
610                                         0x08, data);
611                         }
612                 }
613                 break;
614
615         case INTERFACE_DFP_HIGH:
616                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
617                         via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
618
619                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
620                 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
621                 break;
622
623         case INTERFACE_DFP_LOW:
624                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
625                         break;
626                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
627                 dvi_patch_skew_dvp_low();
628                 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
629                 break;
630
631         case INTERFACE_TMDS:
632                 /* Turn on Display period in the panel path. */
633                 viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
634
635                 /* Turn on TMDS power. */
636                 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
637                 break;
638         }
639
640         if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
641                 /* Disable LCD Scaling */
642                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
643         }
644 }