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1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 #include <linux/via-core.h>
23 #include "global.h"
24
25 static struct pll_map pll_value[] = {
26         {25175000,
27                 {99, 7, 3},
28                 {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
29                 {141, 5, 4},
30                 {141, 5, 4} },
31         {29581000,
32                 {33, 4, 2},
33                 {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
34                 {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
35                 {165, 5, 4} },
36         {26880000,
37                 {15, 4, 1},
38                 {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
39                 {150, 5, 4},
40                 {150, 5, 4} },
41         {31500000,
42                 {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
43                 {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
44                 {176, 5, 4},
45                 {176, 5, 4} },
46         {31728000,
47                 {31, 7, 1},
48                 {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
49                 {177, 5, 4},
50                 {142, 4, 4} },
51         {32688000,
52                 {73, 4, 3},
53                 {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
54                 {183, 5, 4},
55                 {146, 4, 4} },
56         {36000000,
57                 {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
58                 {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
59                 {202, 5, 4},
60                 {161, 4, 4} },
61         {40000000,
62                 {89, 4, 3},
63                 {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
64                 {112, 5, 3},
65                 {112, 5, 3} },
66         {41291000,
67                 {23, 4, 1},
68                 {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
69                 {115, 5, 3},
70                 {115, 5, 3} },
71         {43163000,
72                 {121, 5, 3},
73                 {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
74                 {121, 5, 3},
75                 {121, 5, 3} },
76         {45250000,
77                 {127, 5, 3},
78                 {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
79                 {127, 5, 3},
80                 {127, 5, 3} },
81         {46000000,
82                 {90, 7, 2},
83                 {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
84                 {129, 5, 3},
85                 {103, 4, 3} },
86         {46996000,
87                 {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
88                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
89                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
90                 {105, 4, 3} },
91         {48000000,
92                 {67, 20, 0},
93                 {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
94                 {134, 5, 3},
95                 {134, 5, 3} },
96         {48875000,
97                 {99, 29, 0},
98                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
99                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
100                 {137, 5, 3} },
101         {49500000,
102                 {83, 6, 2},
103                 {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
104                 {138, 5, 3},
105                 {83, 3, 3} },
106         {52406000,
107                 {117, 4, 3},
108                 {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
109                 {117, 4, 3},
110                 {88, 3, 3} },
111         {52977000,
112                 {37, 5, 1},
113                 {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
114                 {148, 5, 3},
115                 {148, 5, 3} },
116         {56250000,
117                 {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
118                 {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
119                 {157, 5, 3},
120                 {157, 5, 3} },
121         {57275000,
122                 {0, 0, 0},
123                 {2, 2, 0},
124                 {2, 2, 0},
125                 {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
126         {60466000,
127                 {76, 9, 1},
128                 {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
129                 {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
130                 {169, 5, 3} },
131         {61500000,
132                 {86, 20, 0},
133                 {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
134                 {172, 5, 3},
135                 {172, 5, 3} },
136         {65000000,
137                 {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
138                 {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
139                 {109, 3, 3},
140                 {109, 3, 3} },
141         {65178000,
142                 {91, 5, 2},
143                 {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
144                 {109, 3, 3},
145                 {182, 5, 3} },
146         {66750000,
147                 {75, 4, 2},
148                 {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
149                 {150, 4, 3},
150                 {112, 3, 3} },
151         {68179000,
152                 {19, 4, 0},
153                 {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
154                 {190, 5, 3},
155                 {191, 5, 3} },
156         {69924000,
157                 {83, 17, 0},
158                 {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
159                 {195, 5, 3},
160                 {195, 5, 3} },
161         {70159000,
162                 {98, 20, 0},
163                 {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
164                 {196, 5, 3},
165                 {195, 5, 3} },
166         {72000000,
167                 {121, 24, 0},
168                 {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
169                 {161, 4, 3},
170                 {161, 4, 3} },
171         {78750000,
172                 {33, 3, 1},
173                 {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
174                 {110, 5, 2},
175                 {110, 5, 2} },
176         {80136000,
177                 {28, 5, 0},
178                 {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
179                 {112, 5, 2},
180                 {112, 5, 2} },
181         {83375000,
182                 {93, 2, 3},
183                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
184                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
185                 {117, 5, 2} },
186         {83950000,
187                 {41, 7, 0},
188                 {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
189                 {117, 5, 2},
190                 {117, 5, 2} },
191         {84750000,
192                 {118, 5, 2},
193                 {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
194                 {118, 5, 2},
195                 {118, 5, 2} },
196         {85860000,
197                 {84, 7, 1},
198                 {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
199                 {120, 5, 2},
200                 {118, 5, 2} },
201         {88750000,
202                 {31, 5, 0},
203                 {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
204                 {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
205                 {124, 5, 2} },
206         {94500000,
207                 {33, 5, 0},
208                 {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
209                 {132, 5, 2},
210                 {132, 5, 2} },
211         {97750000,
212                 {82, 6, 1},
213                 {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
214                 {137, 5, 2},
215                 {137, 5, 2} },
216         {101000000,
217                 {127, 9, 1},
218                 {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
219                 {141, 5, 2},
220                 {141, 5, 2} },
221         {106500000,
222                 {119, 4, 2},
223                 {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
224                 {119, 4, 2},
225                 {149, 5, 2} },
226         {108000000,
227                 {121, 4, 2},
228                 {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
229                 {151, 5, 2},
230                 {151, 5, 2} },
231         {113309000,
232                 {95, 12, 0},
233                 {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
234                 {95, 3, 2},
235                 {159, 5, 2} },
236         {118840000,
237                 {83, 5, 1},
238                 {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
239                 {166, 5, 2},
240                 {166, 5, 2} },
241         {119000000,
242                 {108, 13, 0},
243                 {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
244                 {133, 4, 2},
245                 {167, 5, 2} },
246         {121750000,
247                 {85, 5, 1},
248                 {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
249                 {68, 2, 2},
250                 {0, 0, 0} },
251         {125104000,
252                 {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
253                 {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
254                 {175, 5, 2},
255                 {0, 0, 0} },
256         {135000000,
257                 {94, 5, 1},
258                 {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
259                 {151, 4, 2},
260                 {189, 5, 2} },
261         {136700000,
262                 {115, 12, 0},
263                 {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
264                 {191, 5, 2},
265                 {191, 5, 2} },
266         {138400000,
267                 {87, 9, 0},
268                 {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
269                 {116, 3, 2},
270                 {194, 5, 2} },
271         {146760000,
272                 {103, 5, 1},
273                 {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
274                 {206, 5, 2},
275                 {206, 5, 2} },
276         {153920000,
277                 {86, 8, 0},
278                 {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
279                 {86, 4, 1},
280                 {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
281         {156000000,
282                 {109, 5, 1},
283                 {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
284                 {109, 5, 1},
285                 {108, 5, 1} },
286         {157500000,
287                 {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
288                 {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
289                 {110, 5, 1},
290                 {110, 5, 1} },
291         {162000000,
292                 {113, 5, 1},
293                 {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
294                 {113, 5, 1},
295                 {113, 5, 1} },
296         {187000000,
297                 {118, 9, 0},
298                 {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
299                 {131, 5, 1},
300                 {131, 5, 1} },
301         {193295000,
302                 {108, 8, 0},
303                 {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
304                 {135, 5, 1},
305                 {135, 5, 1} },
306         {202500000,
307                 {99, 7, 0},
308                 {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
309                 {142, 5, 1},
310                 {142, 5, 1} },
311         {204000000,
312                 {100, 7, 0},
313                 {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
314                 {143, 5, 1},
315                 {143, 5, 1} },
316         {218500000,
317                 {92, 6, 0},
318                 {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
319                 {153, 5, 1},
320                 {153, 5, 1} },
321         {234000000,
322                 {98, 6, 0},
323                 {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
324                 {98, 3, 1},
325                 {164, 5, 1} },
326         {267250000,
327                 {112, 6, 0},
328                 {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
329                 {187, 5, 1},
330                 {187, 5, 1} },
331         {297500000,
332                 {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
333                 {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
334                 {208, 5, 1},
335                 {208, 5, 1} },
336         {74481000,
337                 {26, 5, 0},
338                 {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
339                 {208, 5, 3},
340                 {209, 5, 3} },
341         {172798000,
342                 {121, 5, 1},
343                 {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
344                 {121, 5, 1},
345                 {121, 5, 1} },
346         {122614000,
347                 {60, 7, 0},
348                 {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
349                 {137, 4, 2},
350                 {172, 5, 2} },
351         {74270000,
352                 {83, 8, 1},
353                 {208, 5, 3},
354                 {208, 5, 3},
355                 {0, 0, 0} },
356         {148500000,
357                 {83, 8, 0},
358                 {208, 5, 2},
359                 {166, 4, 2},
360                 {208, 5, 2} }
361 };
362
363 static struct fifo_depth_select display_fifo_depth_reg = {
364         /* IGA1 FIFO Depth_Select */
365         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
366         /* IGA2 FIFO Depth_Select */
367         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
368          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
369 };
370
371 static struct fifo_threshold_select fifo_threshold_select_reg = {
372         /* IGA1 FIFO Threshold Select */
373         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
374         /* IGA2 FIFO Threshold Select */
375         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
376 };
377
378 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
379         /* IGA1 FIFO High Threshold Select */
380         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
381         /* IGA2 FIFO High Threshold Select */
382         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
383 };
384
385 static struct display_queue_expire_num display_queue_expire_num_reg = {
386         /* IGA1 Display Queue Expire Num */
387         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
388         /* IGA2 Display Queue Expire Num */
389         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
390 };
391
392 /* Definition Fetch Count Registers*/
393 static struct fetch_count fetch_count_reg = {
394         /* IGA1 Fetch Count Register */
395         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
396         /* IGA2 Fetch Count Register */
397         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
398 };
399
400 static struct iga1_crtc_timing iga1_crtc_reg = {
401         /* IGA1 Horizontal Total */
402         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
403         /* IGA1 Horizontal Addressable Video */
404         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
405         /* IGA1 Horizontal Blank Start */
406         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
407         /* IGA1 Horizontal Blank End */
408         {IGA1_HOR_BLANK_END_REG_NUM,
409          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
410         /* IGA1 Horizontal Sync Start */
411         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
412         /* IGA1 Horizontal Sync End */
413         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
414         /* IGA1 Vertical Total */
415         {IGA1_VER_TOTAL_REG_NUM,
416          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
417         /* IGA1 Vertical Addressable Video */
418         {IGA1_VER_ADDR_REG_NUM,
419          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
420         /* IGA1 Vertical Blank Start */
421         {IGA1_VER_BLANK_START_REG_NUM,
422          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
423         /* IGA1 Vertical Blank End */
424         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
425         /* IGA1 Vertical Sync Start */
426         {IGA1_VER_SYNC_START_REG_NUM,
427          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
428         /* IGA1 Vertical Sync End */
429         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
430 };
431
432 static struct iga2_crtc_timing iga2_crtc_reg = {
433         /* IGA2 Horizontal Total */
434         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
435         /* IGA2 Horizontal Addressable Video */
436         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
437         /* IGA2 Horizontal Blank Start */
438         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
439         /* IGA2 Horizontal Blank End */
440         {IGA2_HOR_BLANK_END_REG_NUM,
441          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
442         /* IGA2 Horizontal Sync Start */
443         {IGA2_HOR_SYNC_START_REG_NUM,
444          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
445         /* IGA2 Horizontal Sync End */
446         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
447         /* IGA2 Vertical Total */
448         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
449         /* IGA2 Vertical Addressable Video */
450         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
451         /* IGA2 Vertical Blank Start */
452         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
453         /* IGA2 Vertical Blank End */
454         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
455         /* IGA2 Vertical Sync Start */
456         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
457         /* IGA2 Vertical Sync End */
458         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
459 };
460
461 static struct rgbLUT palLUT_table[] = {
462         /* {R,G,B} */
463         /* Index 0x00~0x03 */
464         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
465                                                                      0x2A,
466                                                                      0x2A},
467         /* Index 0x04~0x07 */
468         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
469                                                                      0x2A,
470                                                                      0x2A},
471         /* Index 0x08~0x0B */
472         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
473                                                                      0x3F,
474                                                                      0x3F},
475         /* Index 0x0C~0x0F */
476         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
477                                                                      0x3F,
478                                                                      0x3F},
479         /* Index 0x10~0x13 */
480         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
481                                                                      0x0B,
482                                                                      0x0B},
483         /* Index 0x14~0x17 */
484         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
485                                                                      0x18,
486                                                                      0x18},
487         /* Index 0x18~0x1B */
488         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
489                                                                      0x28,
490                                                                      0x28},
491         /* Index 0x1C~0x1F */
492         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
493                                                                      0x3F,
494                                                                      0x3F},
495         /* Index 0x20~0x23 */
496         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
497                                                                      0x00,
498                                                                      0x3F},
499         /* Index 0x24~0x27 */
500         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
501                                                                      0x00,
502                                                                      0x10},
503         /* Index 0x28~0x2B */
504         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
505                                                                      0x2F,
506                                                                      0x00},
507         /* Index 0x2C~0x2F */
508         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
509                                                                      0x3F,
510                                                                      0x00},
511         /* Index 0x30~0x33 */
512         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
513                                                                      0x3F,
514                                                                      0x2F},
515         /* Index 0x34~0x37 */
516         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
517                                                                      0x10,
518                                                                      0x3F},
519         /* Index 0x38~0x3B */
520         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
521                                                                      0x1F,
522                                                                      0x3F},
523         /* Index 0x3C~0x3F */
524         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
525                                                                      0x1F,
526                                                                      0x27},
527         /* Index 0x40~0x43 */
528         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
529                                                                      0x3F,
530                                                                      0x1F},
531         /* Index 0x44~0x47 */
532         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
533                                                                      0x3F,
534                                                                      0x1F},
535         /* Index 0x48~0x4B */
536         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
537                                                                      0x3F,
538                                                                      0x37},
539         /* Index 0x4C~0x4F */
540         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
541                                                                      0x27,
542                                                                      0x3F},
543         /* Index 0x50~0x53 */
544         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
545                                                                      0x2D,
546                                                                      0x3F},
547         /* Index 0x54~0x57 */
548         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
549                                                                      0x2D,
550                                                                      0x31},
551         /* Index 0x58~0x5B */
552         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
553                                                                      0x3A,
554                                                                      0x2D},
555         /* Index 0x5C~0x5F */
556         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
557                                                                      0x3F,
558                                                                      0x2D},
559         /* Index 0x60~0x63 */
560         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
561                                                                      0x3F,
562                                                                      0x3A},
563         /* Index 0x64~0x67 */
564         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
565                                                                      0x31,
566                                                                      0x3F},
567         /* Index 0x68~0x6B */
568         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
569                                                                      0x00,
570                                                                      0x1C},
571         /* Index 0x6C~0x6F */
572         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
573                                                                      0x00,
574                                                                      0x07},
575         /* Index 0x70~0x73 */
576         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
577                                                                      0x15,
578                                                                      0x00},
579         /* Index 0x74~0x77 */
580         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
581                                                                      0x1C,
582                                                                      0x00},
583         /* Index 0x78~0x7B */
584         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
585                                                                      0x1C,
586                                                                      0x15},
587         /* Index 0x7C~0x7F */
588         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
589                                                                      0x07,
590                                                                      0x1C},
591         /* Index 0x80~0x83 */
592         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
593                                                                      0x0E,
594                                                                      0x1C},
595         /* Index 0x84~0x87 */
596         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
597                                                                      0x0E,
598                                                                      0x11},
599         /* Index 0x88~0x8B */
600         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
601                                                                      0x18,
602                                                                      0x0E},
603         /* Index 0x8C~0x8F */
604         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
605                                                                      0x1C,
606                                                                      0x0E},
607         /* Index 0x90~0x93 */
608         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
609                                                                      0x1C,
610                                                                      0x18},
611         /* Index 0x94~0x97 */
612         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
613                                                                      0x11,
614                                                                      0x1C},
615         /* Index 0x98~0x9B */
616         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
617                                                                      0x14,
618                                                                      0x1C},
619         /* Index 0x9C~0x9F */
620         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
621                                                                      0x14,
622                                                                      0x16},
623         /* Index 0xA0~0xA3 */
624         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
625                                                                      0x1A,
626                                                                      0x14},
627         /* Index 0xA4~0xA7 */
628         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
629                                                                      0x1C,
630                                                                      0x14},
631         /* Index 0xA8~0xAB */
632         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
633                                                                      0x1C,
634                                                                      0x1A},
635         /* Index 0xAC~0xAF */
636         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
637                                                                      0x16,
638                                                                      0x1C},
639         /* Index 0xB0~0xB3 */
640         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
641                                                                      0x00,
642                                                                      0x10},
643         /* Index 0xB4~0xB7 */
644         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
645                                                                      0x00,
646                                                                      0x04},
647         /* Index 0xB8~0xBB */
648         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
649                                                                      0x0C,
650                                                                      0x00},
651         /* Index 0xBC~0xBF */
652         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
653                                                                      0x10,
654                                                                      0x00},
655         /* Index 0xC0~0xC3 */
656         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
657                                                                      0x10,
658                                                                      0x0C},
659         /* Index 0xC4~0xC7 */
660         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
661                                                                      0x04,
662                                                                      0x10},
663         /* Index 0xC8~0xCB */
664         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
665                                                                      0x08,
666                                                                      0x10},
667         /* Index 0xCC~0xCF */
668         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
669                                                                      0x08,
670                                                                      0x0A},
671         /* Index 0xD0~0xD3 */
672         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
673                                                                      0x0E,
674                                                                      0x08},
675         /* Index 0xD4~0xD7 */
676         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
677                                                                      0x10,
678                                                                      0x08},
679         /* Index 0xD8~0xDB */
680         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
681                                                                      0x10,
682                                                                      0x0E},
683         /* Index 0xDC~0xDF */
684         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
685                                                                      0x0A,
686                                                                      0x10},
687         /* Index 0xE0~0xE3 */
688         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
689                                                                      0x0B,
690                                                                      0x10},
691         /* Index 0xE4~0xE7 */
692         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
693                                                                      0x0B,
694                                                                      0x0C},
695         /* Index 0xE8~0xEB */
696         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
697                                                                      0x0F,
698                                                                      0x0B},
699         /* Index 0xEC~0xEF */
700         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
701                                                                      0x10,
702                                                                      0x0B},
703         /* Index 0xF0~0xF3 */
704         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
705                                                                      0x10,
706                                                                      0x0F},
707         /* Index 0xF4~0xF7 */
708         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
709                                                                      0x0C,
710                                                                      0x10},
711         /* Index 0xF8~0xFB */
712         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
713                                                                      0x00,
714                                                                      0x00},
715         /* Index 0xFC~0xFF */
716         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
717                                                                      0x00,
718                                                                      0x00}
719 };
720
721 static void load_fix_bit_crtc_reg(void);
722 static void __devinit init_gfx_chip_info(int chip_type);
723 static void __devinit init_tmds_chip_info(void);
724 static void __devinit init_lvds_chip_info(void);
725 static void device_screen_off(void);
726 static void device_screen_on(void);
727 static void set_display_channel(void);
728 static void device_off(void);
729 static void device_on(void);
730 static void enable_second_display_channel(void);
731 static void disable_second_display_channel(void);
732
733 void viafb_lock_crt(void)
734 {
735         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
736 }
737
738 void viafb_unlock_crt(void)
739 {
740         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
741         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
742 }
743
744 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
745 {
746         outb(index, LUT_INDEX_WRITE);
747         outb(r, LUT_DATA);
748         outb(g, LUT_DATA);
749         outb(b, LUT_DATA);
750 }
751
752 static u32 get_dvi_devices(int output_interface)
753 {
754         switch (output_interface) {
755         case INTERFACE_DVP0:
756                 return VIA_96 | VIA_6C;
757
758         case INTERFACE_DVP1:
759                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
760                         return VIA_93;
761                 else
762                         return VIA_DVP1;
763
764         case INTERFACE_DFP_HIGH:
765                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
766                         return 0;
767                 else
768                         return VIA_LVDS2 | VIA_96;
769
770         case INTERFACE_DFP_LOW:
771                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
772                         return 0;
773                 else
774                         return VIA_DVP1 | VIA_LVDS1;
775
776         case INTERFACE_TMDS:
777                 return VIA_LVDS1;
778         }
779
780         return 0;
781 }
782
783 static u32 get_lcd_devices(int output_interface)
784 {
785         switch (output_interface) {
786         case INTERFACE_DVP0:
787                 return VIA_96;
788
789         case INTERFACE_DVP1:
790                 return VIA_DVP1;
791
792         case INTERFACE_DFP_HIGH:
793                 return VIA_LVDS2 | VIA_96;
794
795         case INTERFACE_DFP_LOW:
796                 return VIA_LVDS1 | VIA_DVP1;
797
798         case INTERFACE_DFP:
799                 return VIA_LVDS1 | VIA_LVDS2;
800
801         case INTERFACE_LVDS0:
802         case INTERFACE_LVDS0LVDS1:
803                 return VIA_LVDS1;
804
805         case INTERFACE_LVDS1:
806                 return VIA_LVDS2;
807         }
808
809         return 0;
810 }
811
812 /*Set IGA path for each device*/
813 void viafb_set_iga_path(void)
814 {
815
816         if (viafb_SAMM_ON == 1) {
817                 if (viafb_CRT_ON) {
818                         if (viafb_primary_dev == CRT_Device)
819                                 viaparinfo->crt_setting_info->iga_path = IGA1;
820                         else
821                                 viaparinfo->crt_setting_info->iga_path = IGA2;
822                 }
823
824                 if (viafb_DVI_ON) {
825                         if (viafb_primary_dev == DVI_Device)
826                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
827                         else
828                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
829                 }
830
831                 if (viafb_LCD_ON) {
832                         if (viafb_primary_dev == LCD_Device) {
833                                 if (viafb_dual_fb &&
834                                         (viaparinfo->chip_info->gfx_chip_name ==
835                                         UNICHROME_CLE266)) {
836                                         viaparinfo->
837                                         lvds_setting_info->iga_path = IGA2;
838                                         viaparinfo->
839                                         crt_setting_info->iga_path = IGA1;
840                                         viaparinfo->
841                                         tmds_setting_info->iga_path = IGA1;
842                                 } else
843                                         viaparinfo->
844                                         lvds_setting_info->iga_path = IGA1;
845                         } else {
846                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
847                         }
848                 }
849                 if (viafb_LCD2_ON) {
850                         if (LCD2_Device == viafb_primary_dev)
851                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
852                         else
853                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
854                 }
855         } else {
856                 viafb_SAMM_ON = 0;
857
858                 if (viafb_CRT_ON && viafb_LCD_ON) {
859                         viaparinfo->crt_setting_info->iga_path = IGA1;
860                         viaparinfo->lvds_setting_info->iga_path = IGA2;
861                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
862                         viaparinfo->crt_setting_info->iga_path = IGA1;
863                         viaparinfo->tmds_setting_info->iga_path = IGA2;
864                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
865                         viaparinfo->tmds_setting_info->iga_path = IGA1;
866                         viaparinfo->lvds_setting_info->iga_path = IGA2;
867                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
868                         viaparinfo->lvds_setting_info->iga_path = IGA2;
869                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
870                 } else if (viafb_CRT_ON) {
871                         viaparinfo->crt_setting_info->iga_path = IGA1;
872                 } else if (viafb_LCD_ON) {
873                         viaparinfo->lvds_setting_info->iga_path = IGA2;
874                 } else if (viafb_DVI_ON) {
875                         viaparinfo->tmds_setting_info->iga_path = IGA1;
876                 }
877         }
878
879         viaparinfo->shared->iga1_devices = 0;
880         viaparinfo->shared->iga2_devices = 0;
881         if (viafb_CRT_ON) {
882                 if (viaparinfo->crt_setting_info->iga_path == IGA1)
883                         viaparinfo->shared->iga1_devices |= VIA_CRT;
884                 else
885                         viaparinfo->shared->iga2_devices |= VIA_CRT;
886         }
887
888         if (viafb_DVI_ON) {
889                 if (viaparinfo->tmds_setting_info->iga_path == IGA1)
890                         viaparinfo->shared->iga1_devices |= get_dvi_devices(
891                                 viaparinfo->chip_info->
892                                 tmds_chip_info.output_interface);
893                 else
894                         viaparinfo->shared->iga2_devices |= get_dvi_devices(
895                                 viaparinfo->chip_info->
896                                 tmds_chip_info.output_interface);
897         }
898
899         if (viafb_LCD_ON) {
900                 if (viaparinfo->lvds_setting_info->iga_path == IGA1)
901                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
902                                 viaparinfo->chip_info->
903                                 lvds_chip_info.output_interface);
904                 else
905                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
906                                 viaparinfo->chip_info->
907                                 lvds_chip_info.output_interface);
908         }
909
910         if (viafb_LCD2_ON) {
911                 if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
912                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
913                                 viaparinfo->chip_info->
914                                 lvds_chip_info2.output_interface);
915                 else
916                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
917                                 viaparinfo->chip_info->
918                                 lvds_chip_info2.output_interface);
919         }
920 }
921
922 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
923 {
924         outb(0xFF, 0x3C6); /* bit mask of palette */
925         outb(index, 0x3C8);
926         outb(red, 0x3C9);
927         outb(green, 0x3C9);
928         outb(blue, 0x3C9);
929 }
930
931 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
932 {
933         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
934         set_color_register(index, red, green, blue);
935 }
936
937 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
938 {
939         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
940         set_color_register(index, red, green, blue);
941 }
942
943 static void set_source_common(u8 index, u8 offset, u8 iga)
944 {
945         u8 value, mask = 1 << offset;
946
947         switch (iga) {
948         case IGA1:
949                 value = 0x00;
950                 break;
951         case IGA2:
952                 value = mask;
953                 break;
954         default:
955                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
956                 return;
957         }
958
959         via_write_reg_mask(VIACR, index, value, mask);
960 }
961
962 static void set_crt_source(u8 iga)
963 {
964         u8 value;
965
966         switch (iga) {
967         case IGA1:
968                 value = 0x00;
969                 break;
970         case IGA2:
971                 value = 0x40;
972                 break;
973         default:
974                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
975                 return;
976         }
977
978         via_write_reg_mask(VIASR, 0x16, value, 0x40);
979 }
980
981 static inline void set_6C_source(u8 iga)
982 {
983         set_source_common(0x6C, 7, iga);
984 }
985
986 static inline void set_93_source(u8 iga)
987 {
988         set_source_common(0x93, 7, iga);
989 }
990
991 static inline void set_96_source(u8 iga)
992 {
993         set_source_common(0x96, 4, iga);
994 }
995
996 static inline void set_dvp1_source(u8 iga)
997 {
998         set_source_common(0x9B, 4, iga);
999 }
1000
1001 static inline void set_lvds1_source(u8 iga)
1002 {
1003         set_source_common(0x99, 4, iga);
1004 }
1005
1006 static inline void set_lvds2_source(u8 iga)
1007 {
1008         set_source_common(0x97, 4, iga);
1009 }
1010
1011 void via_set_source(u32 devices, u8 iga)
1012 {
1013         if (devices & VIA_6C)
1014                 set_6C_source(iga);
1015         if (devices & VIA_93)
1016                 set_93_source(iga);
1017         if (devices & VIA_96)
1018                 set_96_source(iga);
1019         if (devices & VIA_CRT)
1020                 set_crt_source(iga);
1021         if (devices & VIA_DVP1)
1022                 set_dvp1_source(iga);
1023         if (devices & VIA_LVDS1)
1024                 set_lvds1_source(iga);
1025         if (devices & VIA_LVDS2)
1026                 set_lvds2_source(iga);
1027 }
1028
1029 static void load_fix_bit_crtc_reg(void)
1030 {
1031         /* always set to 1 */
1032         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1033         /* line compare should set all bits = 1 (extend modes) */
1034         viafb_write_reg(CR18, VIACR, 0xff);
1035         /* line compare should set all bits = 1 (extend modes) */
1036         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1037         /* line compare should set all bits = 1 (extend modes) */
1038         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1039         /* line compare should set all bits = 1 (extend modes) */
1040         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1041         /* line compare should set all bits = 1 (extend modes) */
1042         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1043         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1044         /* extend mode always set to e3h */
1045         viafb_write_reg(CR17, VIACR, 0xe3);
1046         /* extend mode always set to 0h */
1047         viafb_write_reg(CR08, VIACR, 0x00);
1048         /* extend mode always set to 0h */
1049         viafb_write_reg(CR14, VIACR, 0x00);
1050
1051         /* If K8M800, enable Prefetch Mode. */
1052         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1053                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1054                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1055         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1056             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1057                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1058
1059 }
1060
1061 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1062         struct io_register *reg,
1063               int io_type)
1064 {
1065         int reg_mask;
1066         int bit_num = 0;
1067         int data;
1068         int i, j;
1069         int shift_next_reg;
1070         int start_index, end_index, cr_index;
1071         u16 get_bit;
1072
1073         for (i = 0; i < viafb_load_reg_num; i++) {
1074                 reg_mask = 0;
1075                 data = 0;
1076                 start_index = reg[i].start_bit;
1077                 end_index = reg[i].end_bit;
1078                 cr_index = reg[i].io_addr;
1079
1080                 shift_next_reg = bit_num;
1081                 for (j = start_index; j <= end_index; j++) {
1082                         /*if (bit_num==8) timing_value = timing_value >>8; */
1083                         reg_mask = reg_mask | (BIT0 << j);
1084                         get_bit = (timing_value & (BIT0 << bit_num));
1085                         data =
1086                             data | ((get_bit >> shift_next_reg) << start_index);
1087                         bit_num++;
1088                 }
1089                 if (io_type == VIACR)
1090                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1091                 else
1092                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1093         }
1094
1095 }
1096
1097 /* Write Registers */
1098 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1099 {
1100         int i;
1101
1102         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1103
1104         for (i = 0; i < ItemNum; i++)
1105                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1106                         RegTable[i].value, RegTable[i].mask);
1107 }
1108
1109 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1110 {
1111         int reg_value;
1112         int viafb_load_reg_num;
1113         struct io_register *reg = NULL;
1114
1115         switch (set_iga) {
1116         case IGA1:
1117                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1118                 viafb_load_reg_num = fetch_count_reg.
1119                         iga1_fetch_count_reg.reg_num;
1120                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1121                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1122                 break;
1123         case IGA2:
1124                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1125                 viafb_load_reg_num = fetch_count_reg.
1126                         iga2_fetch_count_reg.reg_num;
1127                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1128                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1129                 break;
1130         }
1131
1132 }
1133
1134 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1135 {
1136         int reg_value;
1137         int viafb_load_reg_num;
1138         struct io_register *reg = NULL;
1139         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1140             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1141         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1142             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1143
1144         if (set_iga == IGA1) {
1145                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1146                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1147                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1148                         iga1_fifo_high_threshold =
1149                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1150                         /* If resolution > 1280x1024, expire length = 64, else
1151                            expire length = 128 */
1152                         if ((hor_active > 1280) && (ver_active > 1024))
1153                                 iga1_display_queue_expire_num = 16;
1154                         else
1155                                 iga1_display_queue_expire_num =
1156                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1157
1158                 }
1159
1160                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1161                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1162                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1163                         iga1_fifo_high_threshold =
1164                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1165                         iga1_display_queue_expire_num =
1166                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1167
1168                         /* If resolution > 1280x1024, expire length = 64, else
1169                            expire length = 128 */
1170                         if ((hor_active > 1280) && (ver_active > 1024))
1171                                 iga1_display_queue_expire_num = 16;
1172                         else
1173                                 iga1_display_queue_expire_num =
1174                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1175                 }
1176
1177                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1178                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1179                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1180                         iga1_fifo_high_threshold =
1181                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1182
1183                         /* If resolution > 1280x1024, expire length = 64,
1184                            else expire length = 128 */
1185                         if ((hor_active > 1280) && (ver_active > 1024))
1186                                 iga1_display_queue_expire_num = 16;
1187                         else
1188                                 iga1_display_queue_expire_num =
1189                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1190                 }
1191
1192                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1193                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1194                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1195                         iga1_fifo_high_threshold =
1196                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1197                         iga1_display_queue_expire_num =
1198                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1199                 }
1200
1201                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1202                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1203                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1204                         iga1_fifo_high_threshold =
1205                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1206                         iga1_display_queue_expire_num =
1207                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1208                 }
1209
1210                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1211                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1212                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1213                         iga1_fifo_high_threshold =
1214                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1215                         iga1_display_queue_expire_num =
1216                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1217                 }
1218
1219                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1220                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1221                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1222                         iga1_fifo_high_threshold =
1223                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1224                         iga1_display_queue_expire_num =
1225                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1226                 }
1227
1228                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1229                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1230                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1231                         iga1_fifo_high_threshold =
1232                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1233                         iga1_display_queue_expire_num =
1234                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1235                 }
1236
1237                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1238                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1239                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1240                         iga1_fifo_high_threshold =
1241                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1242                         iga1_display_queue_expire_num =
1243                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1244                 }
1245
1246                 /* Set Display FIFO Depath Select */
1247                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1248                 viafb_load_reg_num =
1249                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1250                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1251                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1252
1253                 /* Set Display FIFO Threshold Select */
1254                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1255                 viafb_load_reg_num =
1256                     fifo_threshold_select_reg.
1257                     iga1_fifo_threshold_select_reg.reg_num;
1258                 reg =
1259                     fifo_threshold_select_reg.
1260                     iga1_fifo_threshold_select_reg.reg;
1261                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1262
1263                 /* Set FIFO High Threshold Select */
1264                 reg_value =
1265                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1266                 viafb_load_reg_num =
1267                     fifo_high_threshold_select_reg.
1268                     iga1_fifo_high_threshold_select_reg.reg_num;
1269                 reg =
1270                     fifo_high_threshold_select_reg.
1271                     iga1_fifo_high_threshold_select_reg.reg;
1272                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1273
1274                 /* Set Display Queue Expire Num */
1275                 reg_value =
1276                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1277                     (iga1_display_queue_expire_num);
1278                 viafb_load_reg_num =
1279                     display_queue_expire_num_reg.
1280                     iga1_display_queue_expire_num_reg.reg_num;
1281                 reg =
1282                     display_queue_expire_num_reg.
1283                     iga1_display_queue_expire_num_reg.reg;
1284                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1285
1286         } else {
1287                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1288                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1289                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1290                         iga2_fifo_high_threshold =
1291                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1292
1293                         /* If resolution > 1280x1024, expire length = 64,
1294                            else  expire length = 128 */
1295                         if ((hor_active > 1280) && (ver_active > 1024))
1296                                 iga2_display_queue_expire_num = 16;
1297                         else
1298                                 iga2_display_queue_expire_num =
1299                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1300                 }
1301
1302                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1303                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1304                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1305                         iga2_fifo_high_threshold =
1306                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1307
1308                         /* If resolution > 1280x1024, expire length = 64,
1309                            else  expire length = 128 */
1310                         if ((hor_active > 1280) && (ver_active > 1024))
1311                                 iga2_display_queue_expire_num = 16;
1312                         else
1313                                 iga2_display_queue_expire_num =
1314                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1315                 }
1316
1317                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1318                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1319                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1320                         iga2_fifo_high_threshold =
1321                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1322
1323                         /* If resolution > 1280x1024, expire length = 64,
1324                            else expire length = 128 */
1325                         if ((hor_active > 1280) && (ver_active > 1024))
1326                                 iga2_display_queue_expire_num = 16;
1327                         else
1328                                 iga2_display_queue_expire_num =
1329                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1330                 }
1331
1332                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1333                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1334                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1335                         iga2_fifo_high_threshold =
1336                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1337                         iga2_display_queue_expire_num =
1338                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1339                 }
1340
1341                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1342                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1343                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1344                         iga2_fifo_high_threshold =
1345                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1346                         iga2_display_queue_expire_num =
1347                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1348                 }
1349
1350                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1351                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1352                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1353                         iga2_fifo_high_threshold =
1354                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1355                         iga2_display_queue_expire_num =
1356                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1357                 }
1358
1359                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1360                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1361                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1362                         iga2_fifo_high_threshold =
1363                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1364                         iga2_display_queue_expire_num =
1365                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1366                 }
1367
1368                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1369                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1370                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1371                         iga2_fifo_high_threshold =
1372                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1373                         iga2_display_queue_expire_num =
1374                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1375                 }
1376
1377                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1378                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1379                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1380                         iga2_fifo_high_threshold =
1381                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1382                         iga2_display_queue_expire_num =
1383                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1384                 }
1385
1386                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1387                         /* Set Display FIFO Depath Select */
1388                         reg_value =
1389                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1390                             - 1;
1391                         /* Patch LCD in IGA2 case */
1392                         viafb_load_reg_num =
1393                             display_fifo_depth_reg.
1394                             iga2_fifo_depth_select_reg.reg_num;
1395                         reg =
1396                             display_fifo_depth_reg.
1397                             iga2_fifo_depth_select_reg.reg;
1398                         viafb_load_reg(reg_value,
1399                                 viafb_load_reg_num, reg, VIACR);
1400                 } else {
1401
1402                         /* Set Display FIFO Depath Select */
1403                         reg_value =
1404                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1405                         viafb_load_reg_num =
1406                             display_fifo_depth_reg.
1407                             iga2_fifo_depth_select_reg.reg_num;
1408                         reg =
1409                             display_fifo_depth_reg.
1410                             iga2_fifo_depth_select_reg.reg;
1411                         viafb_load_reg(reg_value,
1412                                 viafb_load_reg_num, reg, VIACR);
1413                 }
1414
1415                 /* Set Display FIFO Threshold Select */
1416                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1417                 viafb_load_reg_num =
1418                     fifo_threshold_select_reg.
1419                     iga2_fifo_threshold_select_reg.reg_num;
1420                 reg =
1421                     fifo_threshold_select_reg.
1422                     iga2_fifo_threshold_select_reg.reg;
1423                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1424
1425                 /* Set FIFO High Threshold Select */
1426                 reg_value =
1427                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1428                 viafb_load_reg_num =
1429                     fifo_high_threshold_select_reg.
1430                     iga2_fifo_high_threshold_select_reg.reg_num;
1431                 reg =
1432                     fifo_high_threshold_select_reg.
1433                     iga2_fifo_high_threshold_select_reg.reg;
1434                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1435
1436                 /* Set Display Queue Expire Num */
1437                 reg_value =
1438                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1439                     (iga2_display_queue_expire_num);
1440                 viafb_load_reg_num =
1441                     display_queue_expire_num_reg.
1442                     iga2_display_queue_expire_num_reg.reg_num;
1443                 reg =
1444                     display_queue_expire_num_reg.
1445                     iga2_display_queue_expire_num_reg.reg;
1446                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1447
1448         }
1449
1450 }
1451
1452 static u32 cle266_encode_pll(struct pll_config pll)
1453 {
1454         return (pll.multiplier << 8)
1455                 | (pll.rshift << 6)
1456                 | pll.divisor;
1457 }
1458
1459 static u32 k800_encode_pll(struct pll_config pll)
1460 {
1461         return ((pll.divisor - 2) << 16)
1462                 | (pll.rshift << 10)
1463                 | (pll.multiplier - 2);
1464 }
1465
1466 static u32 vx855_encode_pll(struct pll_config pll)
1467 {
1468         return (pll.divisor << 16)
1469                 | (pll.rshift << 10)
1470                 | pll.multiplier;
1471 }
1472
1473 u32 viafb_get_clk_value(int clk)
1474 {
1475         u32 value = 0;
1476         int i = 0;
1477
1478         while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1479                 i++;
1480
1481         if (i == NUM_TOTAL_PLL_TABLE) {
1482                 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1483         } else {
1484                 switch (viaparinfo->chip_info->gfx_chip_name) {
1485                 case UNICHROME_CLE266:
1486                 case UNICHROME_K400:
1487                         value = cle266_encode_pll(pll_value[i].cle266_pll);
1488                         break;
1489
1490                 case UNICHROME_K800:
1491                 case UNICHROME_PM800:
1492                 case UNICHROME_CN700:
1493                         value = k800_encode_pll(pll_value[i].k800_pll);
1494                         break;
1495
1496                 case UNICHROME_CX700:
1497                 case UNICHROME_CN750:
1498                 case UNICHROME_K8M890:
1499                 case UNICHROME_P4M890:
1500                 case UNICHROME_P4M900:
1501                 case UNICHROME_VX800:
1502                         value = k800_encode_pll(pll_value[i].cx700_pll);
1503                         break;
1504
1505                 case UNICHROME_VX855:
1506                         value = vx855_encode_pll(pll_value[i].vx855_pll);
1507                         break;
1508                 }
1509         }
1510
1511         return value;
1512 }
1513
1514 /* Set VCLK*/
1515 void viafb_set_vclock(u32 clk, int set_iga)
1516 {
1517         /* H.W. Reset : ON */
1518         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1519
1520         if (set_iga == IGA1) {
1521                 /* Change D,N FOR VCLK */
1522                 switch (viaparinfo->chip_info->gfx_chip_name) {
1523                 case UNICHROME_CLE266:
1524                 case UNICHROME_K400:
1525                         via_write_reg(VIASR, SR46, (clk & 0x00FF));
1526                         via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1527                         break;
1528
1529                 case UNICHROME_K800:
1530                 case UNICHROME_PM800:
1531                 case UNICHROME_CN700:
1532                 case UNICHROME_CX700:
1533                 case UNICHROME_CN750:
1534                 case UNICHROME_K8M890:
1535                 case UNICHROME_P4M890:
1536                 case UNICHROME_P4M900:
1537                 case UNICHROME_VX800:
1538                 case UNICHROME_VX855:
1539                         via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1540                         via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1541                         via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1542                         break;
1543                 }
1544         }
1545
1546         if (set_iga == IGA2) {
1547                 /* Change D,N FOR LCK */
1548                 switch (viaparinfo->chip_info->gfx_chip_name) {
1549                 case UNICHROME_CLE266:
1550                 case UNICHROME_K400:
1551                         via_write_reg(VIASR, SR44, (clk & 0x00FF));
1552                         via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1553                         break;
1554
1555                 case UNICHROME_K800:
1556                 case UNICHROME_PM800:
1557                 case UNICHROME_CN700:
1558                 case UNICHROME_CX700:
1559                 case UNICHROME_CN750:
1560                 case UNICHROME_K8M890:
1561                 case UNICHROME_P4M890:
1562                 case UNICHROME_P4M900:
1563                 case UNICHROME_VX800:
1564                 case UNICHROME_VX855:
1565                         via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1566                         via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1567                         via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1568                         break;
1569                 }
1570         }
1571
1572         /* H.W. Reset : OFF */
1573         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1574
1575         /* Reset PLL */
1576         if (set_iga == IGA1) {
1577                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1578                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1579         }
1580
1581         if (set_iga == IGA2) {
1582                 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1583                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1584         }
1585
1586         /* Fire! */
1587         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1588 }
1589
1590 void viafb_load_crtc_timing(struct display_timing device_timing,
1591         int set_iga)
1592 {
1593         int i;
1594         int viafb_load_reg_num = 0;
1595         int reg_value = 0;
1596         struct io_register *reg = NULL;
1597
1598         viafb_unlock_crt();
1599
1600         for (i = 0; i < 12; i++) {
1601                 if (set_iga == IGA1) {
1602                         switch (i) {
1603                         case H_TOTAL_INDEX:
1604                                 reg_value =
1605                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1606                                                            hor_total);
1607                                 viafb_load_reg_num =
1608                                         iga1_crtc_reg.hor_total.reg_num;
1609                                 reg = iga1_crtc_reg.hor_total.reg;
1610                                 break;
1611                         case H_ADDR_INDEX:
1612                                 reg_value =
1613                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1614                                                           hor_addr);
1615                                 viafb_load_reg_num =
1616                                         iga1_crtc_reg.hor_addr.reg_num;
1617                                 reg = iga1_crtc_reg.hor_addr.reg;
1618                                 break;
1619                         case H_BLANK_START_INDEX:
1620                                 reg_value =
1621                                     IGA1_HOR_BLANK_START_FORMULA
1622                                     (device_timing.hor_blank_start);
1623                                 viafb_load_reg_num =
1624                                     iga1_crtc_reg.hor_blank_start.reg_num;
1625                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1626                                 break;
1627                         case H_BLANK_END_INDEX:
1628                                 reg_value =
1629                                     IGA1_HOR_BLANK_END_FORMULA
1630                                     (device_timing.hor_blank_start,
1631                                      device_timing.hor_blank_end);
1632                                 viafb_load_reg_num =
1633                                     iga1_crtc_reg.hor_blank_end.reg_num;
1634                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1635                                 break;
1636                         case H_SYNC_START_INDEX:
1637                                 reg_value =
1638                                     IGA1_HOR_SYNC_START_FORMULA
1639                                     (device_timing.hor_sync_start);
1640                                 viafb_load_reg_num =
1641                                     iga1_crtc_reg.hor_sync_start.reg_num;
1642                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1643                                 break;
1644                         case H_SYNC_END_INDEX:
1645                                 reg_value =
1646                                     IGA1_HOR_SYNC_END_FORMULA
1647                                     (device_timing.hor_sync_start,
1648                                      device_timing.hor_sync_end);
1649                                 viafb_load_reg_num =
1650                                     iga1_crtc_reg.hor_sync_end.reg_num;
1651                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1652                                 break;
1653                         case V_TOTAL_INDEX:
1654                                 reg_value =
1655                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1656                                                            ver_total);
1657                                 viafb_load_reg_num =
1658                                         iga1_crtc_reg.ver_total.reg_num;
1659                                 reg = iga1_crtc_reg.ver_total.reg;
1660                                 break;
1661                         case V_ADDR_INDEX:
1662                                 reg_value =
1663                                     IGA1_VER_ADDR_FORMULA(device_timing.
1664                                                           ver_addr);
1665                                 viafb_load_reg_num =
1666                                         iga1_crtc_reg.ver_addr.reg_num;
1667                                 reg = iga1_crtc_reg.ver_addr.reg;
1668                                 break;
1669                         case V_BLANK_START_INDEX:
1670                                 reg_value =
1671                                     IGA1_VER_BLANK_START_FORMULA
1672                                     (device_timing.ver_blank_start);
1673                                 viafb_load_reg_num =
1674                                     iga1_crtc_reg.ver_blank_start.reg_num;
1675                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1676                                 break;
1677                         case V_BLANK_END_INDEX:
1678                                 reg_value =
1679                                     IGA1_VER_BLANK_END_FORMULA
1680                                     (device_timing.ver_blank_start,
1681                                      device_timing.ver_blank_end);
1682                                 viafb_load_reg_num =
1683                                     iga1_crtc_reg.ver_blank_end.reg_num;
1684                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1685                                 break;
1686                         case V_SYNC_START_INDEX:
1687                                 reg_value =
1688                                     IGA1_VER_SYNC_START_FORMULA
1689                                     (device_timing.ver_sync_start);
1690                                 viafb_load_reg_num =
1691                                     iga1_crtc_reg.ver_sync_start.reg_num;
1692                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1693                                 break;
1694                         case V_SYNC_END_INDEX:
1695                                 reg_value =
1696                                     IGA1_VER_SYNC_END_FORMULA
1697                                     (device_timing.ver_sync_start,
1698                                      device_timing.ver_sync_end);
1699                                 viafb_load_reg_num =
1700                                     iga1_crtc_reg.ver_sync_end.reg_num;
1701                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1702                                 break;
1703
1704                         }
1705                 }
1706
1707                 if (set_iga == IGA2) {
1708                         switch (i) {
1709                         case H_TOTAL_INDEX:
1710                                 reg_value =
1711                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1712                                                            hor_total);
1713                                 viafb_load_reg_num =
1714                                         iga2_crtc_reg.hor_total.reg_num;
1715                                 reg = iga2_crtc_reg.hor_total.reg;
1716                                 break;
1717                         case H_ADDR_INDEX:
1718                                 reg_value =
1719                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1720                                                           hor_addr);
1721                                 viafb_load_reg_num =
1722                                         iga2_crtc_reg.hor_addr.reg_num;
1723                                 reg = iga2_crtc_reg.hor_addr.reg;
1724                                 break;
1725                         case H_BLANK_START_INDEX:
1726                                 reg_value =
1727                                     IGA2_HOR_BLANK_START_FORMULA
1728                                     (device_timing.hor_blank_start);
1729                                 viafb_load_reg_num =
1730                                     iga2_crtc_reg.hor_blank_start.reg_num;
1731                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1732                                 break;
1733                         case H_BLANK_END_INDEX:
1734                                 reg_value =
1735                                     IGA2_HOR_BLANK_END_FORMULA
1736                                     (device_timing.hor_blank_start,
1737                                      device_timing.hor_blank_end);
1738                                 viafb_load_reg_num =
1739                                     iga2_crtc_reg.hor_blank_end.reg_num;
1740                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1741                                 break;
1742                         case H_SYNC_START_INDEX:
1743                                 reg_value =
1744                                     IGA2_HOR_SYNC_START_FORMULA
1745                                     (device_timing.hor_sync_start);
1746                                 if (UNICHROME_CN700 <=
1747                                         viaparinfo->chip_info->gfx_chip_name)
1748                                         viafb_load_reg_num =
1749                                             iga2_crtc_reg.hor_sync_start.
1750                                             reg_num;
1751                                 else
1752                                         viafb_load_reg_num = 3;
1753                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1754                                 break;
1755                         case H_SYNC_END_INDEX:
1756                                 reg_value =
1757                                     IGA2_HOR_SYNC_END_FORMULA
1758                                     (device_timing.hor_sync_start,
1759                                      device_timing.hor_sync_end);
1760                                 viafb_load_reg_num =
1761                                     iga2_crtc_reg.hor_sync_end.reg_num;
1762                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1763                                 break;
1764                         case V_TOTAL_INDEX:
1765                                 reg_value =
1766                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1767                                                            ver_total);
1768                                 viafb_load_reg_num =
1769                                         iga2_crtc_reg.ver_total.reg_num;
1770                                 reg = iga2_crtc_reg.ver_total.reg;
1771                                 break;
1772                         case V_ADDR_INDEX:
1773                                 reg_value =
1774                                     IGA2_VER_ADDR_FORMULA(device_timing.
1775                                                           ver_addr);
1776                                 viafb_load_reg_num =
1777                                         iga2_crtc_reg.ver_addr.reg_num;
1778                                 reg = iga2_crtc_reg.ver_addr.reg;
1779                                 break;
1780                         case V_BLANK_START_INDEX:
1781                                 reg_value =
1782                                     IGA2_VER_BLANK_START_FORMULA
1783                                     (device_timing.ver_blank_start);
1784                                 viafb_load_reg_num =
1785                                     iga2_crtc_reg.ver_blank_start.reg_num;
1786                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1787                                 break;
1788                         case V_BLANK_END_INDEX:
1789                                 reg_value =
1790                                     IGA2_VER_BLANK_END_FORMULA
1791                                     (device_timing.ver_blank_start,
1792                                      device_timing.ver_blank_end);
1793                                 viafb_load_reg_num =
1794                                     iga2_crtc_reg.ver_blank_end.reg_num;
1795                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1796                                 break;
1797                         case V_SYNC_START_INDEX:
1798                                 reg_value =
1799                                     IGA2_VER_SYNC_START_FORMULA
1800                                     (device_timing.ver_sync_start);
1801                                 viafb_load_reg_num =
1802                                     iga2_crtc_reg.ver_sync_start.reg_num;
1803                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1804                                 break;
1805                         case V_SYNC_END_INDEX:
1806                                 reg_value =
1807                                     IGA2_VER_SYNC_END_FORMULA
1808                                     (device_timing.ver_sync_start,
1809                                      device_timing.ver_sync_end);
1810                                 viafb_load_reg_num =
1811                                     iga2_crtc_reg.ver_sync_end.reg_num;
1812                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1813                                 break;
1814
1815                         }
1816                 }
1817                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1818         }
1819
1820         viafb_lock_crt();
1821 }
1822
1823 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1824         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1825 {
1826         struct display_timing crt_reg;
1827         int i;
1828         int index = 0;
1829         int h_addr, v_addr;
1830         u32 pll_D_N;
1831         u8 polarity = 0;
1832
1833         for (i = 0; i < video_mode->mode_array; i++) {
1834                 index = i;
1835
1836                 if (crt_table[i].refresh_rate == viaparinfo->
1837                         crt_setting_info->refresh_rate)
1838                         break;
1839         }
1840
1841         crt_reg = crt_table[index].crtc;
1842
1843         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1844         /* So we would delete border. */
1845         if ((viafb_LCD_ON | viafb_DVI_ON)
1846             && video_mode->crtc[0].crtc.hor_addr == 640
1847             && video_mode->crtc[0].crtc.ver_addr == 480
1848             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1849                 /* The border is 8 pixels. */
1850                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1851
1852                 /* Blanking time should add left and right borders. */
1853                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1854         }
1855
1856         h_addr = crt_reg.hor_addr;
1857         v_addr = crt_reg.ver_addr;
1858
1859         /* update polarity for CRT timing */
1860         if (crt_table[index].h_sync_polarity == NEGATIVE)
1861                 polarity |= BIT6;
1862         if (crt_table[index].v_sync_polarity == NEGATIVE)
1863                 polarity |= BIT7;
1864         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1865
1866         if (set_iga == IGA1) {
1867                 viafb_unlock_crt();
1868                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1869                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1870                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1871         }
1872
1873         switch (set_iga) {
1874         case IGA1:
1875                 viafb_load_crtc_timing(crt_reg, IGA1);
1876                 break;
1877         case IGA2:
1878                 viafb_load_crtc_timing(crt_reg, IGA2);
1879                 break;
1880         }
1881
1882         load_fix_bit_crtc_reg();
1883         viafb_lock_crt();
1884         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1885         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1886
1887         /* load FIFO */
1888         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1889             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1890                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1891
1892         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1893         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1894         viafb_set_vclock(pll_D_N, set_iga);
1895
1896 }
1897
1898 void __devinit viafb_init_chip_info(int chip_type)
1899 {
1900         init_gfx_chip_info(chip_type);
1901         init_tmds_chip_info();
1902         init_lvds_chip_info();
1903
1904         viaparinfo->crt_setting_info->iga_path = IGA1;
1905         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1906
1907         /*Set IGA path for each device */
1908         viafb_set_iga_path();
1909
1910         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1911         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1912         viaparinfo->lvds_setting_info2->display_method =
1913                 viaparinfo->lvds_setting_info->display_method;
1914         viaparinfo->lvds_setting_info2->lcd_mode =
1915                 viaparinfo->lvds_setting_info->lcd_mode;
1916 }
1917
1918 void viafb_update_device_setting(int hres, int vres,
1919         int bpp, int vmode_refresh, int flag)
1920 {
1921         if (flag == 0) {
1922                 viaparinfo->crt_setting_info->h_active = hres;
1923                 viaparinfo->crt_setting_info->v_active = vres;
1924                 viaparinfo->crt_setting_info->bpp = bpp;
1925                 viaparinfo->crt_setting_info->refresh_rate =
1926                         vmode_refresh;
1927
1928                 viaparinfo->tmds_setting_info->h_active = hres;
1929                 viaparinfo->tmds_setting_info->v_active = vres;
1930
1931                 viaparinfo->lvds_setting_info->h_active = hres;
1932                 viaparinfo->lvds_setting_info->v_active = vres;
1933                 viaparinfo->lvds_setting_info->bpp = bpp;
1934                 viaparinfo->lvds_setting_info->refresh_rate =
1935                         vmode_refresh;
1936                 viaparinfo->lvds_setting_info2->h_active = hres;
1937                 viaparinfo->lvds_setting_info2->v_active = vres;
1938                 viaparinfo->lvds_setting_info2->bpp = bpp;
1939                 viaparinfo->lvds_setting_info2->refresh_rate =
1940                         vmode_refresh;
1941         } else {
1942
1943                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1944                         viaparinfo->tmds_setting_info->h_active = hres;
1945                         viaparinfo->tmds_setting_info->v_active = vres;
1946                 }
1947
1948                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1949                         viaparinfo->lvds_setting_info->h_active = hres;
1950                         viaparinfo->lvds_setting_info->v_active = vres;
1951                         viaparinfo->lvds_setting_info->bpp = bpp;
1952                         viaparinfo->lvds_setting_info->refresh_rate =
1953                                 vmode_refresh;
1954                 }
1955                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1956                         viaparinfo->lvds_setting_info2->h_active = hres;
1957                         viaparinfo->lvds_setting_info2->v_active = vres;
1958                         viaparinfo->lvds_setting_info2->bpp = bpp;
1959                         viaparinfo->lvds_setting_info2->refresh_rate =
1960                                 vmode_refresh;
1961                 }
1962         }
1963 }
1964
1965 static void __devinit init_gfx_chip_info(int chip_type)
1966 {
1967         u8 tmp;
1968
1969         viaparinfo->chip_info->gfx_chip_name = chip_type;
1970
1971         /* Check revision of CLE266 Chip */
1972         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1973                 /* CR4F only define in CLE266.CX chip */
1974                 tmp = viafb_read_reg(VIACR, CR4F);
1975                 viafb_write_reg(CR4F, VIACR, 0x55);
1976                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1977                         viaparinfo->chip_info->gfx_chip_revision =
1978                         CLE266_REVISION_AX;
1979                 else
1980                         viaparinfo->chip_info->gfx_chip_revision =
1981                         CLE266_REVISION_CX;
1982                 /* restore orignal CR4F value */
1983                 viafb_write_reg(CR4F, VIACR, tmp);
1984         }
1985
1986         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1987                 tmp = viafb_read_reg(VIASR, SR43);
1988                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1989                 if (tmp & 0x02) {
1990                         viaparinfo->chip_info->gfx_chip_revision =
1991                                 CX700_REVISION_700M2;
1992                 } else if (tmp & 0x40) {
1993                         viaparinfo->chip_info->gfx_chip_revision =
1994                                 CX700_REVISION_700M;
1995                 } else {
1996                         viaparinfo->chip_info->gfx_chip_revision =
1997                                 CX700_REVISION_700;
1998                 }
1999         }
2000
2001         /* Determine which 2D engine we have */
2002         switch (viaparinfo->chip_info->gfx_chip_name) {
2003         case UNICHROME_VX800:
2004         case UNICHROME_VX855:
2005                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2006                 break;
2007         case UNICHROME_K8M890:
2008         case UNICHROME_P4M900:
2009                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2010                 break;
2011         default:
2012                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2013                 break;
2014         }
2015 }
2016
2017 static void __devinit init_tmds_chip_info(void)
2018 {
2019         viafb_tmds_trasmitter_identify();
2020
2021         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2022                 output_interface) {
2023                 switch (viaparinfo->chip_info->gfx_chip_name) {
2024                 case UNICHROME_CX700:
2025                         {
2026                                 /* we should check support by hardware layout.*/
2027                                 if ((viafb_display_hardware_layout ==
2028                                      HW_LAYOUT_DVI_ONLY)
2029                                     || (viafb_display_hardware_layout ==
2030                                         HW_LAYOUT_LCD_DVI)) {
2031                                         viaparinfo->chip_info->tmds_chip_info.
2032                                             output_interface = INTERFACE_TMDS;
2033                                 } else {
2034                                         viaparinfo->chip_info->tmds_chip_info.
2035                                                 output_interface =
2036                                                 INTERFACE_NONE;
2037                                 }
2038                                 break;
2039                         }
2040                 case UNICHROME_K8M890:
2041                 case UNICHROME_P4M900:
2042                 case UNICHROME_P4M890:
2043                         /* TMDS on PCIE, we set DFPLOW as default. */
2044                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2045                             INTERFACE_DFP_LOW;
2046                         break;
2047                 default:
2048                         {
2049                                 /* set DVP1 default for DVI */
2050                                 viaparinfo->chip_info->tmds_chip_info
2051                                 .output_interface = INTERFACE_DVP1;
2052                         }
2053                 }
2054         }
2055
2056         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2057                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2058         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2059                 &viaparinfo->shared->tmds_setting_info);
2060 }
2061
2062 static void __devinit init_lvds_chip_info(void)
2063 {
2064         viafb_lvds_trasmitter_identify();
2065         viafb_init_lcd_size();
2066         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2067                                    viaparinfo->lvds_setting_info);
2068         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2069                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2070                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2071         }
2072         /*If CX700,two singel LCD, we need to reassign
2073            LCD interface to different LVDS port */
2074         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2075             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2076                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2077                         lvds_chip_name) && (INTEGRATED_LVDS ==
2078                         viaparinfo->chip_info->
2079                         lvds_chip_info2.lvds_chip_name)) {
2080                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2081                                 INTERFACE_LVDS0;
2082                         viaparinfo->chip_info->lvds_chip_info2.
2083                                 output_interface =
2084                             INTERFACE_LVDS1;
2085                 }
2086         }
2087
2088         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2089                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2090         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2091                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2092         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2093                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2094 }
2095
2096 void __devinit viafb_init_dac(int set_iga)
2097 {
2098         int i;
2099         u8 tmp;
2100
2101         if (set_iga == IGA1) {
2102                 /* access Primary Display's LUT */
2103                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2104                 /* turn off LCK */
2105                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2106                 for (i = 0; i < 256; i++) {
2107                         write_dac_reg(i, palLUT_table[i].red,
2108                                       palLUT_table[i].green,
2109                                       palLUT_table[i].blue);
2110                 }
2111                 /* turn on LCK */
2112                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2113         } else {
2114                 tmp = viafb_read_reg(VIACR, CR6A);
2115                 /* access Secondary Display's LUT */
2116                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2117                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2118                 for (i = 0; i < 256; i++) {
2119                         write_dac_reg(i, palLUT_table[i].red,
2120                                       palLUT_table[i].green,
2121                                       palLUT_table[i].blue);
2122                 }
2123                 /* set IGA1 DAC for default */
2124                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2125                 viafb_write_reg(CR6A, VIACR, tmp);
2126         }
2127 }
2128
2129 static void device_screen_off(void)
2130 {
2131         /* turn off CRT screen (IGA1) */
2132         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2133 }
2134
2135 static void device_screen_on(void)
2136 {
2137         /* turn on CRT screen (IGA1) */
2138         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2139 }
2140
2141 static void set_display_channel(void)
2142 {
2143         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2144         is keeped on lvds_setting_info2 */
2145         if (viafb_LCD2_ON &&
2146                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2147                 /* For dual channel LCD: */
2148                 /* Set to Dual LVDS channel. */
2149                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2150         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2151                 /* For LCD+DFP: */
2152                 /* Set to LVDS1 + TMDS channel. */
2153                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2154         } else if (viafb_DVI_ON) {
2155                 /* Set to single TMDS channel. */
2156                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2157         } else if (viafb_LCD_ON) {
2158                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2159                         /* For dual channel LCD: */
2160                         /* Set to Dual LVDS channel. */
2161                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2162                 } else {
2163                         /* Set to LVDS0 + LVDS1 channel. */
2164                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2165                 }
2166         }
2167 }
2168
2169 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2170         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2171 {
2172         int i, j;
2173         int port;
2174         u8 value, index, mask;
2175         struct crt_mode_table *crt_timing;
2176         struct crt_mode_table *crt_timing1 = NULL;
2177
2178         device_screen_off();
2179         crt_timing = vmode_tbl->crtc;
2180
2181         if (viafb_SAMM_ON == 1) {
2182                 crt_timing1 = vmode_tbl1->crtc;
2183         }
2184
2185         inb(VIAStatus);
2186         outb(0x00, VIAAR);
2187
2188         /* Write Common Setting for Video Mode */
2189         switch (viaparinfo->chip_info->gfx_chip_name) {
2190         case UNICHROME_CLE266:
2191                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2192                 break;
2193
2194         case UNICHROME_K400:
2195                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2196                 break;
2197
2198         case UNICHROME_K800:
2199         case UNICHROME_PM800:
2200                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2201                 break;
2202
2203         case UNICHROME_CN700:
2204         case UNICHROME_K8M890:
2205         case UNICHROME_P4M890:
2206         case UNICHROME_P4M900:
2207                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2208                 break;
2209
2210         case UNICHROME_CX700:
2211         case UNICHROME_VX800:
2212                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2213                 break;
2214
2215         case UNICHROME_VX855:
2216                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2217                 break;
2218         }
2219
2220         device_off();
2221
2222         /* Fill VPIT Parameters */
2223         /* Write Misc Register */
2224         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2225
2226         /* Write Sequencer */
2227         for (i = 1; i <= StdSR; i++)
2228                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2229
2230         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2231
2232         /* Write CRTC */
2233         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2234
2235         /* Write Graphic Controller */
2236         for (i = 0; i < StdGR; i++)
2237                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2238
2239         /* Write Attribute Controller */
2240         for (i = 0; i < StdAR; i++) {
2241                 inb(VIAStatus);
2242                 outb(i, VIAAR);
2243                 outb(VPIT.AR[i], VIAAR);
2244         }
2245
2246         inb(VIAStatus);
2247         outb(0x20, VIAAR);
2248
2249         /* Update Patch Register */
2250
2251         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2252             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2253             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2254             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2255                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2256                         index = res_patch_table[0].io_reg_table[j].index;
2257                         port = res_patch_table[0].io_reg_table[j].port;
2258                         value = res_patch_table[0].io_reg_table[j].value;
2259                         mask = res_patch_table[0].io_reg_table[j].mask;
2260                         viafb_write_reg_mask(index, port, value, mask);
2261                 }
2262         }
2263
2264         via_set_primary_pitch(viafbinfo->fix.line_length);
2265         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2266                 : viafbinfo->fix.line_length);
2267         via_set_primary_color_depth(viaparinfo->depth);
2268         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2269                 : viaparinfo->depth);
2270         via_set_source(viaparinfo->shared->iga1_devices, IGA1);
2271         via_set_source(viaparinfo->shared->iga2_devices, IGA2);
2272         if (viaparinfo->shared->iga2_devices)
2273                 enable_second_display_channel();
2274         else
2275                 disable_second_display_channel();
2276
2277         /* Update Refresh Rate Setting */
2278
2279         /* Clear On Screen */
2280
2281         /* CRT set mode */
2282         if (viafb_CRT_ON) {
2283                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2284                         IGA2)) {
2285                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2286                                 video_bpp1 / 8,
2287                                 viaparinfo->crt_setting_info->iga_path);
2288                 } else {
2289                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2290                                 video_bpp / 8,
2291                                 viaparinfo->crt_setting_info->iga_path);
2292                 }
2293
2294                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2295                 to 8 alignment (1368),there is several pixels (2 pixels)
2296                 on right side of screen. */
2297                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2298                         viafb_unlock_crt();
2299                         viafb_write_reg(CR02, VIACR,
2300                                 viafb_read_reg(VIACR, CR02) - 1);
2301                         viafb_lock_crt();
2302                 }
2303         }
2304
2305         if (viafb_DVI_ON) {
2306                 if (viafb_SAMM_ON &&
2307                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2308                         viafb_dvi_set_mode(viafb_get_mode
2309                                      (viaparinfo->tmds_setting_info->h_active,
2310                                       viaparinfo->tmds_setting_info->
2311                                       v_active),
2312                                      video_bpp1, viaparinfo->
2313                                      tmds_setting_info->iga_path);
2314                 } else {
2315                         viafb_dvi_set_mode(viafb_get_mode
2316                                      (viaparinfo->tmds_setting_info->h_active,
2317                                       viaparinfo->
2318                                       tmds_setting_info->v_active),
2319                                      video_bpp, viaparinfo->
2320                                      tmds_setting_info->iga_path);
2321                 }
2322         }
2323
2324         if (viafb_LCD_ON) {
2325                 if (viafb_SAMM_ON &&
2326                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2327                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2328                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2329                                 lvds_setting_info,
2330                                      &viaparinfo->chip_info->lvds_chip_info);
2331                 } else {
2332                         /* IGA1 doesn't have LCD scaling, so set it center. */
2333                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2334                                 viaparinfo->lvds_setting_info->display_method =
2335                                     LCD_CENTERING;
2336                         }
2337                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2338                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2339                                 lvds_setting_info,
2340                                      &viaparinfo->chip_info->lvds_chip_info);
2341                 }
2342         }
2343         if (viafb_LCD2_ON) {
2344                 if (viafb_SAMM_ON &&
2345                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2346                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2347                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2348                                 lvds_setting_info2,
2349                                      &viaparinfo->chip_info->lvds_chip_info2);
2350                 } else {
2351                         /* IGA1 doesn't have LCD scaling, so set it center. */
2352                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2353                                 viaparinfo->lvds_setting_info2->display_method =
2354                                     LCD_CENTERING;
2355                         }
2356                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2357                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2358                                 lvds_setting_info2,
2359                                      &viaparinfo->chip_info->lvds_chip_info2);
2360                 }
2361         }
2362
2363         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2364             && (viafb_LCD_ON || viafb_DVI_ON))
2365                 set_display_channel();
2366
2367         /* If set mode normally, save resolution information for hot-plug . */
2368         if (!viafb_hotplug) {
2369                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2370                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2371                 viafb_hotplug_bpp = video_bpp;
2372                 viafb_hotplug_refresh = viafb_refresh;
2373
2374                 if (viafb_DVI_ON)
2375                         viafb_DeviceStatus = DVI_Device;
2376                 else
2377                         viafb_DeviceStatus = CRT_Device;
2378         }
2379         device_on();
2380         device_screen_on();
2381         return 1;
2382 }
2383
2384 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2385 {
2386         int i;
2387
2388         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2389                 if ((hres == res_map_refresh_tbl[i].hres)
2390                     && (vres == res_map_refresh_tbl[i].vres)
2391                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2392                         return res_map_refresh_tbl[i].pixclock;
2393         }
2394         return RES_640X480_60HZ_PIXCLOCK;
2395
2396 }
2397
2398 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2399 {
2400 #define REFRESH_TOLERANCE 3
2401         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2402         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2403                 if ((hres == res_map_refresh_tbl[i].hres)
2404                     && (vres == res_map_refresh_tbl[i].vres)
2405                     && (diff > (abs(long_refresh -
2406                     res_map_refresh_tbl[i].vmode_refresh)))) {
2407                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2408                                 vmode_refresh);
2409                         nearest = i;
2410                 }
2411         }
2412 #undef REFRESH_TOLERANCE
2413         if (nearest > 0)
2414                 return res_map_refresh_tbl[nearest].vmode_refresh;
2415         return 60;
2416 }
2417
2418 static void device_off(void)
2419 {
2420         viafb_crt_disable();
2421         viafb_dvi_disable();
2422         viafb_lcd_disable();
2423 }
2424
2425 static void device_on(void)
2426 {
2427         if (viafb_CRT_ON == 1)
2428                 viafb_crt_enable();
2429         if (viafb_DVI_ON == 1)
2430                 viafb_dvi_enable();
2431         if (viafb_LCD_ON == 1)
2432                 viafb_lcd_enable();
2433 }
2434
2435 void viafb_crt_disable(void)
2436 {
2437         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2438 }
2439
2440 void viafb_crt_enable(void)
2441 {
2442         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2443 }
2444
2445 static void enable_second_display_channel(void)
2446 {
2447         /* to enable second display channel. */
2448         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2449         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2450         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2451 }
2452
2453 static void disable_second_display_channel(void)
2454 {
2455         /* to disable second display channel. */
2456         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2457         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2458         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2459 }
2460
2461 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2462                                         *p_gfx_dpa_setting)
2463 {
2464         switch (output_interface) {
2465         case INTERFACE_DVP0:
2466                 {
2467                         /* DVP0 Clock Polarity and Adjust: */
2468                         viafb_write_reg_mask(CR96, VIACR,
2469                                        p_gfx_dpa_setting->DVP0, 0x0F);
2470
2471                         /* DVP0 Clock and Data Pads Driving: */
2472                         viafb_write_reg_mask(SR1E, VIASR,
2473                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2474                         viafb_write_reg_mask(SR2A, VIASR,
2475                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2476                                        BIT4);
2477                         viafb_write_reg_mask(SR1B, VIASR,
2478                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2479                         viafb_write_reg_mask(SR2A, VIASR,
2480                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2481                         break;
2482                 }
2483
2484         case INTERFACE_DVP1:
2485                 {
2486                         /* DVP1 Clock Polarity and Adjust: */
2487                         viafb_write_reg_mask(CR9B, VIACR,
2488                                        p_gfx_dpa_setting->DVP1, 0x0F);
2489
2490                         /* DVP1 Clock and Data Pads Driving: */
2491                         viafb_write_reg_mask(SR65, VIASR,
2492                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2493                         break;
2494                 }
2495
2496         case INTERFACE_DFP_HIGH:
2497                 {
2498                         viafb_write_reg_mask(CR97, VIACR,
2499                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2500                         break;
2501                 }
2502
2503         case INTERFACE_DFP_LOW:
2504                 {
2505                         viafb_write_reg_mask(CR99, VIACR,
2506                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2507                         break;
2508                 }
2509
2510         case INTERFACE_DFP:
2511                 {
2512                         viafb_write_reg_mask(CR97, VIACR,
2513                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2514                         viafb_write_reg_mask(CR99, VIACR,
2515                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2516                         break;
2517                 }
2518         }
2519 }
2520
2521 /*According var's xres, yres fill var's other timing information*/
2522 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2523         struct VideoModeTable *vmode_tbl)
2524 {
2525         struct crt_mode_table *crt_timing = NULL;
2526         struct display_timing crt_reg;
2527         int i = 0, index = 0;
2528         crt_timing = vmode_tbl->crtc;
2529         for (i = 0; i < vmode_tbl->mode_array; i++) {
2530                 index = i;
2531                 if (crt_timing[i].refresh_rate == refresh)
2532                         break;
2533         }
2534
2535         crt_reg = crt_timing[index].crtc;
2536         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2537         var->left_margin =
2538             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2539         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2540         var->hsync_len = crt_reg.hor_sync_end;
2541         var->upper_margin =
2542             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2543         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2544         var->vsync_len = crt_reg.ver_sync_end;
2545 }