]> git.openfabrics.org - ~shefty/rdma-dev.git/blob - drivers/video/via/hw.c
viafb: simplify lcd size "detection"
[~shefty/rdma-dev.git] / drivers / video / via / hw.c
1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 #include <linux/via-core.h>
23 #include "global.h"
24
25 static struct pll_map pll_value[] = {
26         {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
27          CX700_25_175M, VX855_25_175M},
28         {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
29          CX700_29_581M, VX855_29_581M},
30         {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
31          CX700_26_880M, VX855_26_880M},
32         {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
33          CX700_31_490M, VX855_31_490M},
34         {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
35          CX700_31_500M, VX855_31_500M},
36         {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
37          CX700_31_728M, VX855_31_728M},
38         {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
39          CX700_32_668M, VX855_32_668M},
40         {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
41          CX700_36_000M, VX855_36_000M},
42         {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
43          CX700_40_000M, VX855_40_000M},
44         {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
45          CX700_41_291M, VX855_41_291M},
46         {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
47          CX700_43_163M, VX855_43_163M},
48         {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
49          CX700_45_250M, VX855_45_250M},
50         {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
51          CX700_46_000M, VX855_46_000M},
52         {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
53          CX700_46_996M, VX855_46_996M},
54         {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
55          CX700_48_000M, VX855_48_000M},
56         {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
57          CX700_48_875M, VX855_48_875M},
58         {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
59          CX700_49_500M, VX855_49_500M},
60         {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
61          CX700_52_406M, VX855_52_406M},
62         {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
63          CX700_52_977M, VX855_52_977M},
64         {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
65          CX700_56_250M, VX855_56_250M},
66         {CLK_57_275M, 0, 0, 0, VX855_57_275M},
67         {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
68          CX700_60_466M, VX855_60_466M},
69         {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
70          CX700_61_500M, VX855_61_500M},
71         {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
72          CX700_65_000M, VX855_65_000M},
73         {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
74          CX700_65_178M, VX855_65_178M},
75         {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
76          CX700_66_750M, VX855_66_750M},
77         {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
78          CX700_68_179M, VX855_68_179M},
79         {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
80          CX700_69_924M, VX855_69_924M},
81         {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
82          CX700_70_159M, VX855_70_159M},
83         {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
84          CX700_72_000M, VX855_72_000M},
85         {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
86          CX700_78_750M, VX855_78_750M},
87         {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
88          CX700_80_136M, VX855_80_136M},
89         {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
90          CX700_83_375M, VX855_83_375M},
91         {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
92          CX700_83_950M, VX855_83_950M},
93         {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
94          CX700_84_750M, VX855_84_750M},
95         {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
96          CX700_85_860M, VX855_85_860M},
97         {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
98          CX700_88_750M, VX855_88_750M},
99         {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
100          CX700_94_500M, VX855_94_500M},
101         {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
102          CX700_97_750M, VX855_97_750M},
103         {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
104          CX700_101_000M, VX855_101_000M},
105         {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
106          CX700_106_500M, VX855_106_500M},
107         {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
108          CX700_108_000M, VX855_108_000M},
109         {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
110          CX700_113_309M, VX855_113_309M},
111         {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
112          CX700_118_840M, VX855_118_840M},
113         {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
114          CX700_119_000M, VX855_119_000M},
115         {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
116          CX700_121_750M, 0},
117         {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
118          CX700_125_104M, 0},
119         {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
120          CX700_133_308M, 0},
121         {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
122          CX700_135_000M, VX855_135_000M},
123         {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
124          CX700_136_700M, VX855_136_700M},
125         {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
126          CX700_138_400M, VX855_138_400M},
127         {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
128          CX700_146_760M, VX855_146_760M},
129         {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
130          CX700_153_920M, VX855_153_920M},
131         {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
132          CX700_156_000M, VX855_156_000M},
133         {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
134          CX700_157_500M, VX855_157_500M},
135         {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
136          CX700_162_000M, VX855_162_000M},
137         {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
138          CX700_187_000M, VX855_187_000M},
139         {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
140          CX700_193_295M, VX855_193_295M},
141         {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
142          CX700_202_500M, VX855_202_500M},
143         {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
144          CX700_204_000M, VX855_204_000M},
145         {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
146          CX700_218_500M, VX855_218_500M},
147         {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
148          CX700_234_000M, VX855_234_000M},
149         {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
150          CX700_267_250M, VX855_267_250M},
151         {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
152          CX700_297_500M, VX855_297_500M},
153         {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
154          CX700_74_481M, VX855_74_481M},
155         {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
156          CX700_172_798M, VX855_172_798M},
157         {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
158          CX700_122_614M, VX855_122_614M},
159         {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
160          CX700_74_270M, 0},
161         {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
162          CX700_148_500M, VX855_148_500M}
163 };
164
165 static struct fifo_depth_select display_fifo_depth_reg = {
166         /* IGA1 FIFO Depth_Select */
167         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
168         /* IGA2 FIFO Depth_Select */
169         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
170          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
171 };
172
173 static struct fifo_threshold_select fifo_threshold_select_reg = {
174         /* IGA1 FIFO Threshold Select */
175         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
176         /* IGA2 FIFO Threshold Select */
177         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
178 };
179
180 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
181         /* IGA1 FIFO High Threshold Select */
182         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
183         /* IGA2 FIFO High Threshold Select */
184         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
185 };
186
187 static struct display_queue_expire_num display_queue_expire_num_reg = {
188         /* IGA1 Display Queue Expire Num */
189         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
190         /* IGA2 Display Queue Expire Num */
191         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
192 };
193
194 /* Definition Fetch Count Registers*/
195 static struct fetch_count fetch_count_reg = {
196         /* IGA1 Fetch Count Register */
197         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
198         /* IGA2 Fetch Count Register */
199         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
200 };
201
202 static struct iga1_crtc_timing iga1_crtc_reg = {
203         /* IGA1 Horizontal Total */
204         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
205         /* IGA1 Horizontal Addressable Video */
206         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
207         /* IGA1 Horizontal Blank Start */
208         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
209         /* IGA1 Horizontal Blank End */
210         {IGA1_HOR_BLANK_END_REG_NUM,
211          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
212         /* IGA1 Horizontal Sync Start */
213         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
214         /* IGA1 Horizontal Sync End */
215         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
216         /* IGA1 Vertical Total */
217         {IGA1_VER_TOTAL_REG_NUM,
218          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
219         /* IGA1 Vertical Addressable Video */
220         {IGA1_VER_ADDR_REG_NUM,
221          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
222         /* IGA1 Vertical Blank Start */
223         {IGA1_VER_BLANK_START_REG_NUM,
224          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
225         /* IGA1 Vertical Blank End */
226         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
227         /* IGA1 Vertical Sync Start */
228         {IGA1_VER_SYNC_START_REG_NUM,
229          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
230         /* IGA1 Vertical Sync End */
231         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
232 };
233
234 static struct iga2_crtc_timing iga2_crtc_reg = {
235         /* IGA2 Horizontal Total */
236         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
237         /* IGA2 Horizontal Addressable Video */
238         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
239         /* IGA2 Horizontal Blank Start */
240         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
241         /* IGA2 Horizontal Blank End */
242         {IGA2_HOR_BLANK_END_REG_NUM,
243          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
244         /* IGA2 Horizontal Sync Start */
245         {IGA2_HOR_SYNC_START_REG_NUM,
246          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
247         /* IGA2 Horizontal Sync End */
248         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
249         /* IGA2 Vertical Total */
250         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
251         /* IGA2 Vertical Addressable Video */
252         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
253         /* IGA2 Vertical Blank Start */
254         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
255         /* IGA2 Vertical Blank End */
256         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
257         /* IGA2 Vertical Sync Start */
258         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
259         /* IGA2 Vertical Sync End */
260         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
261 };
262
263 static struct rgbLUT palLUT_table[] = {
264         /* {R,G,B} */
265         /* Index 0x00~0x03 */
266         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
267                                                                      0x2A,
268                                                                      0x2A},
269         /* Index 0x04~0x07 */
270         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
271                                                                      0x2A,
272                                                                      0x2A},
273         /* Index 0x08~0x0B */
274         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
275                                                                      0x3F,
276                                                                      0x3F},
277         /* Index 0x0C~0x0F */
278         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
279                                                                      0x3F,
280                                                                      0x3F},
281         /* Index 0x10~0x13 */
282         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
283                                                                      0x0B,
284                                                                      0x0B},
285         /* Index 0x14~0x17 */
286         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
287                                                                      0x18,
288                                                                      0x18},
289         /* Index 0x18~0x1B */
290         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
291                                                                      0x28,
292                                                                      0x28},
293         /* Index 0x1C~0x1F */
294         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
295                                                                      0x3F,
296                                                                      0x3F},
297         /* Index 0x20~0x23 */
298         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
299                                                                      0x00,
300                                                                      0x3F},
301         /* Index 0x24~0x27 */
302         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
303                                                                      0x00,
304                                                                      0x10},
305         /* Index 0x28~0x2B */
306         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
307                                                                      0x2F,
308                                                                      0x00},
309         /* Index 0x2C~0x2F */
310         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
311                                                                      0x3F,
312                                                                      0x00},
313         /* Index 0x30~0x33 */
314         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
315                                                                      0x3F,
316                                                                      0x2F},
317         /* Index 0x34~0x37 */
318         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
319                                                                      0x10,
320                                                                      0x3F},
321         /* Index 0x38~0x3B */
322         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
323                                                                      0x1F,
324                                                                      0x3F},
325         /* Index 0x3C~0x3F */
326         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
327                                                                      0x1F,
328                                                                      0x27},
329         /* Index 0x40~0x43 */
330         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
331                                                                      0x3F,
332                                                                      0x1F},
333         /* Index 0x44~0x47 */
334         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
335                                                                      0x3F,
336                                                                      0x1F},
337         /* Index 0x48~0x4B */
338         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
339                                                                      0x3F,
340                                                                      0x37},
341         /* Index 0x4C~0x4F */
342         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
343                                                                      0x27,
344                                                                      0x3F},
345         /* Index 0x50~0x53 */
346         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
347                                                                      0x2D,
348                                                                      0x3F},
349         /* Index 0x54~0x57 */
350         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
351                                                                      0x2D,
352                                                                      0x31},
353         /* Index 0x58~0x5B */
354         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
355                                                                      0x3A,
356                                                                      0x2D},
357         /* Index 0x5C~0x5F */
358         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
359                                                                      0x3F,
360                                                                      0x2D},
361         /* Index 0x60~0x63 */
362         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
363                                                                      0x3F,
364                                                                      0x3A},
365         /* Index 0x64~0x67 */
366         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
367                                                                      0x31,
368                                                                      0x3F},
369         /* Index 0x68~0x6B */
370         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
371                                                                      0x00,
372                                                                      0x1C},
373         /* Index 0x6C~0x6F */
374         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
375                                                                      0x00,
376                                                                      0x07},
377         /* Index 0x70~0x73 */
378         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
379                                                                      0x15,
380                                                                      0x00},
381         /* Index 0x74~0x77 */
382         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
383                                                                      0x1C,
384                                                                      0x00},
385         /* Index 0x78~0x7B */
386         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
387                                                                      0x1C,
388                                                                      0x15},
389         /* Index 0x7C~0x7F */
390         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
391                                                                      0x07,
392                                                                      0x1C},
393         /* Index 0x80~0x83 */
394         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
395                                                                      0x0E,
396                                                                      0x1C},
397         /* Index 0x84~0x87 */
398         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
399                                                                      0x0E,
400                                                                      0x11},
401         /* Index 0x88~0x8B */
402         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
403                                                                      0x18,
404                                                                      0x0E},
405         /* Index 0x8C~0x8F */
406         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
407                                                                      0x1C,
408                                                                      0x0E},
409         /* Index 0x90~0x93 */
410         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
411                                                                      0x1C,
412                                                                      0x18},
413         /* Index 0x94~0x97 */
414         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
415                                                                      0x11,
416                                                                      0x1C},
417         /* Index 0x98~0x9B */
418         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
419                                                                      0x14,
420                                                                      0x1C},
421         /* Index 0x9C~0x9F */
422         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
423                                                                      0x14,
424                                                                      0x16},
425         /* Index 0xA0~0xA3 */
426         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
427                                                                      0x1A,
428                                                                      0x14},
429         /* Index 0xA4~0xA7 */
430         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
431                                                                      0x1C,
432                                                                      0x14},
433         /* Index 0xA8~0xAB */
434         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
435                                                                      0x1C,
436                                                                      0x1A},
437         /* Index 0xAC~0xAF */
438         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
439                                                                      0x16,
440                                                                      0x1C},
441         /* Index 0xB0~0xB3 */
442         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
443                                                                      0x00,
444                                                                      0x10},
445         /* Index 0xB4~0xB7 */
446         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
447                                                                      0x00,
448                                                                      0x04},
449         /* Index 0xB8~0xBB */
450         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
451                                                                      0x0C,
452                                                                      0x00},
453         /* Index 0xBC~0xBF */
454         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
455                                                                      0x10,
456                                                                      0x00},
457         /* Index 0xC0~0xC3 */
458         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
459                                                                      0x10,
460                                                                      0x0C},
461         /* Index 0xC4~0xC7 */
462         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
463                                                                      0x04,
464                                                                      0x10},
465         /* Index 0xC8~0xCB */
466         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
467                                                                      0x08,
468                                                                      0x10},
469         /* Index 0xCC~0xCF */
470         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
471                                                                      0x08,
472                                                                      0x0A},
473         /* Index 0xD0~0xD3 */
474         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
475                                                                      0x0E,
476                                                                      0x08},
477         /* Index 0xD4~0xD7 */
478         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
479                                                                      0x10,
480                                                                      0x08},
481         /* Index 0xD8~0xDB */
482         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
483                                                                      0x10,
484                                                                      0x0E},
485         /* Index 0xDC~0xDF */
486         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
487                                                                      0x0A,
488                                                                      0x10},
489         /* Index 0xE0~0xE3 */
490         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
491                                                                      0x0B,
492                                                                      0x10},
493         /* Index 0xE4~0xE7 */
494         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
495                                                                      0x0B,
496                                                                      0x0C},
497         /* Index 0xE8~0xEB */
498         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
499                                                                      0x0F,
500                                                                      0x0B},
501         /* Index 0xEC~0xEF */
502         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
503                                                                      0x10,
504                                                                      0x0B},
505         /* Index 0xF0~0xF3 */
506         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
507                                                                      0x10,
508                                                                      0x0F},
509         /* Index 0xF4~0xF7 */
510         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
511                                                                      0x0C,
512                                                                      0x10},
513         /* Index 0xF8~0xFB */
514         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
515                                                                      0x00,
516                                                                      0x00},
517         /* Index 0xFC~0xFF */
518         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
519                                                                      0x00,
520                                                                      0x00}
521 };
522
523 static void set_crt_output_path(int set_iga);
524 static void dvi_patch_skew_dvp0(void);
525 static void dvi_patch_skew_dvp1(void);
526 static void dvi_patch_skew_dvp_low(void);
527 static void set_dvi_output_path(int set_iga, int output_interface);
528 static void set_lcd_output_path(int set_iga, int output_interface);
529 static void load_fix_bit_crtc_reg(void);
530 static void init_gfx_chip_info(int chip_type);
531 static void init_tmds_chip_info(void);
532 static void init_lvds_chip_info(void);
533 static void device_screen_off(void);
534 static void device_screen_on(void);
535 static void set_display_channel(void);
536 static void device_off(void);
537 static void device_on(void);
538 static void enable_second_display_channel(void);
539 static void disable_second_display_channel(void);
540
541 void viafb_lock_crt(void)
542 {
543         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
544 }
545
546 void viafb_unlock_crt(void)
547 {
548         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
549         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
550 }
551
552 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
553 {
554         outb(index, LUT_INDEX_WRITE);
555         outb(r, LUT_DATA);
556         outb(g, LUT_DATA);
557         outb(b, LUT_DATA);
558 }
559
560 /*Set IGA path for each device*/
561 void viafb_set_iga_path(void)
562 {
563
564         if (viafb_SAMM_ON == 1) {
565                 if (viafb_CRT_ON) {
566                         if (viafb_primary_dev == CRT_Device)
567                                 viaparinfo->crt_setting_info->iga_path = IGA1;
568                         else
569                                 viaparinfo->crt_setting_info->iga_path = IGA2;
570                 }
571
572                 if (viafb_DVI_ON) {
573                         if (viafb_primary_dev == DVI_Device)
574                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
575                         else
576                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
577                 }
578
579                 if (viafb_LCD_ON) {
580                         if (viafb_primary_dev == LCD_Device) {
581                                 if (viafb_dual_fb &&
582                                         (viaparinfo->chip_info->gfx_chip_name ==
583                                         UNICHROME_CLE266)) {
584                                         viaparinfo->
585                                         lvds_setting_info->iga_path = IGA2;
586                                         viaparinfo->
587                                         crt_setting_info->iga_path = IGA1;
588                                         viaparinfo->
589                                         tmds_setting_info->iga_path = IGA1;
590                                 } else
591                                         viaparinfo->
592                                         lvds_setting_info->iga_path = IGA1;
593                         } else {
594                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
595                         }
596                 }
597                 if (viafb_LCD2_ON) {
598                         if (LCD2_Device == viafb_primary_dev)
599                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
600                         else
601                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
602                 }
603         } else {
604                 viafb_SAMM_ON = 0;
605
606                 if (viafb_CRT_ON && viafb_LCD_ON) {
607                         viaparinfo->crt_setting_info->iga_path = IGA1;
608                         viaparinfo->lvds_setting_info->iga_path = IGA2;
609                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
610                         viaparinfo->crt_setting_info->iga_path = IGA1;
611                         viaparinfo->tmds_setting_info->iga_path = IGA2;
612                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
613                         viaparinfo->tmds_setting_info->iga_path = IGA1;
614                         viaparinfo->lvds_setting_info->iga_path = IGA2;
615                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
616                         viaparinfo->lvds_setting_info->iga_path = IGA2;
617                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
618                 } else if (viafb_CRT_ON) {
619                         viaparinfo->crt_setting_info->iga_path = IGA1;
620                 } else if (viafb_LCD_ON) {
621                         viaparinfo->lvds_setting_info->iga_path = IGA2;
622                 } else if (viafb_DVI_ON) {
623                         viaparinfo->tmds_setting_info->iga_path = IGA1;
624                 }
625         }
626 }
627
628 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
629 {
630         outb(0xFF, 0x3C6); /* bit mask of palette */
631         outb(index, 0x3C8);
632         outb(red, 0x3C9);
633         outb(green, 0x3C9);
634         outb(blue, 0x3C9);
635 }
636
637 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
638 {
639         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
640         set_color_register(index, red, green, blue);
641 }
642
643 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
644 {
645         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
646         set_color_register(index, red, green, blue);
647 }
648
649 void viafb_set_output_path(int device, int set_iga, int output_interface)
650 {
651         switch (device) {
652         case DEVICE_CRT:
653                 set_crt_output_path(set_iga);
654                 break;
655         case DEVICE_DVI:
656                 set_dvi_output_path(set_iga, output_interface);
657                 break;
658         case DEVICE_LCD:
659                 set_lcd_output_path(set_iga, output_interface);
660                 break;
661         }
662 }
663
664 static void set_crt_output_path(int set_iga)
665 {
666         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
667
668         switch (set_iga) {
669         case IGA1:
670                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
671                 break;
672         case IGA2:
673                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
674                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
675                 break;
676         }
677 }
678
679 static void dvi_patch_skew_dvp0(void)
680 {
681         /* Reset data driving first: */
682         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
683         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
684
685         switch (viaparinfo->chip_info->gfx_chip_name) {
686         case UNICHROME_P4M890:
687                 {
688                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
689                                 (viaparinfo->tmds_setting_info->v_active ==
690                                 1200))
691                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
692                                                BIT0 + BIT1 + BIT2);
693                         else
694                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
695                                                BIT0 + BIT1 + BIT2);
696                         break;
697                 }
698
699         case UNICHROME_P4M900:
700                 {
701                         viafb_write_reg_mask(CR96, VIACR, 0x07,
702                                        BIT0 + BIT1 + BIT2 + BIT3);
703                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
704                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
705                         break;
706                 }
707
708         default:
709                 {
710                         break;
711                 }
712         }
713 }
714
715 static void dvi_patch_skew_dvp1(void)
716 {
717         switch (viaparinfo->chip_info->gfx_chip_name) {
718         case UNICHROME_CX700:
719                 {
720                         break;
721                 }
722
723         default:
724                 {
725                         break;
726                 }
727         }
728 }
729
730 static void dvi_patch_skew_dvp_low(void)
731 {
732         switch (viaparinfo->chip_info->gfx_chip_name) {
733         case UNICHROME_K8M890:
734                 {
735                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
736                         break;
737                 }
738
739         case UNICHROME_P4M900:
740                 {
741                         viafb_write_reg_mask(CR99, VIACR, 0x08,
742                                        BIT0 + BIT1 + BIT2 + BIT3);
743                         break;
744                 }
745
746         case UNICHROME_P4M890:
747                 {
748                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
749                                        BIT0 + BIT1 + BIT2 + BIT3);
750                         break;
751                 }
752
753         default:
754                 {
755                         break;
756                 }
757         }
758 }
759
760 static void set_dvi_output_path(int set_iga, int output_interface)
761 {
762         switch (output_interface) {
763         case INTERFACE_DVP0:
764                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
765
766                 if (set_iga == IGA1) {
767                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
768                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
769                                 BIT5 + BIT7);
770                 } else {
771                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
772                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
773                                 BIT5 + BIT7);
774                 }
775
776                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
777
778                 dvi_patch_skew_dvp0();
779                 break;
780
781         case INTERFACE_DVP1:
782                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
783                         if (set_iga == IGA1)
784                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
785                                                BIT0 + BIT5 + BIT7);
786                         else
787                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
788                                                BIT0 + BIT5 + BIT7);
789                 } else {
790                         if (set_iga == IGA1)
791                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
792                         else
793                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
794                 }
795
796                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
797                 dvi_patch_skew_dvp1();
798                 break;
799         case INTERFACE_DFP_HIGH:
800                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
801                         if (set_iga == IGA1) {
802                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
803                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
804                                                BIT0 + BIT1 + BIT4);
805                         } else {
806                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
807                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
808                                                BIT0 + BIT1 + BIT4);
809                         }
810                 }
811                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
812                 break;
813
814         case INTERFACE_DFP_LOW:
815                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
816                         break;
817
818                 if (set_iga == IGA1) {
819                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
820                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
821                 } else {
822                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
823                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
824                 }
825
826                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
827                 dvi_patch_skew_dvp_low();
828                 break;
829
830         case INTERFACE_TMDS:
831                 if (set_iga == IGA1)
832                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
833                 else
834                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
835                 break;
836         }
837
838         if (set_iga == IGA2) {
839                 enable_second_display_channel();
840                 /* Disable LCD Scaling */
841                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
842         }
843 }
844
845 static void set_lcd_output_path(int set_iga, int output_interface)
846 {
847         DEBUG_MSG(KERN_INFO
848                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
849                   set_iga, output_interface);
850         switch (set_iga) {
851         case IGA1:
852                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
853                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
854
855                 disable_second_display_channel();
856                 break;
857
858         case IGA2:
859                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
860                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
861
862                 enable_second_display_channel();
863                 break;
864         }
865
866         switch (output_interface) {
867         case INTERFACE_DVP0:
868                 if (set_iga == IGA1) {
869                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
870                 } else {
871                         viafb_write_reg(CR91, VIACR, 0x00);
872                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
873                 }
874                 break;
875
876         case INTERFACE_DVP1:
877                 if (set_iga == IGA1)
878                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
879                 else {
880                         viafb_write_reg(CR91, VIACR, 0x00);
881                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
882                 }
883                 break;
884
885         case INTERFACE_DFP_HIGH:
886                 if (set_iga == IGA1)
887                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
888                 else {
889                         viafb_write_reg(CR91, VIACR, 0x00);
890                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
891                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
892                 }
893                 break;
894
895         case INTERFACE_DFP_LOW:
896                 if (set_iga == IGA1)
897                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
898                 else {
899                         viafb_write_reg(CR91, VIACR, 0x00);
900                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
901                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
902                 }
903
904                 break;
905
906         case INTERFACE_DFP:
907                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
908                     || (UNICHROME_P4M890 ==
909                     viaparinfo->chip_info->gfx_chip_name))
910                         viafb_write_reg_mask(CR97, VIACR, 0x84,
911                                        BIT7 + BIT2 + BIT1 + BIT0);
912                 if (set_iga == IGA1) {
913                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
914                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
915                 } else {
916                         viafb_write_reg(CR91, VIACR, 0x00);
917                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
918                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
919                 }
920                 break;
921
922         case INTERFACE_LVDS0:
923         case INTERFACE_LVDS0LVDS1:
924                 if (set_iga == IGA1)
925                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
926                 else
927                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
928
929                 break;
930
931         case INTERFACE_LVDS1:
932                 if (set_iga == IGA1)
933                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
934                 else
935                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
936                 break;
937         }
938 }
939
940 static void load_fix_bit_crtc_reg(void)
941 {
942         /* always set to 1 */
943         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
944         /* line compare should set all bits = 1 (extend modes) */
945         viafb_write_reg(CR18, VIACR, 0xff);
946         /* line compare should set all bits = 1 (extend modes) */
947         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
948         /* line compare should set all bits = 1 (extend modes) */
949         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
950         /* line compare should set all bits = 1 (extend modes) */
951         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
952         /* line compare should set all bits = 1 (extend modes) */
953         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
954         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
955         /* extend mode always set to e3h */
956         viafb_write_reg(CR17, VIACR, 0xe3);
957         /* extend mode always set to 0h */
958         viafb_write_reg(CR08, VIACR, 0x00);
959         /* extend mode always set to 0h */
960         viafb_write_reg(CR14, VIACR, 0x00);
961
962         /* If K8M800, enable Prefetch Mode. */
963         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
964                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
965                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
966         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
967             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
968                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
969
970 }
971
972 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
973         struct io_register *reg,
974               int io_type)
975 {
976         int reg_mask;
977         int bit_num = 0;
978         int data;
979         int i, j;
980         int shift_next_reg;
981         int start_index, end_index, cr_index;
982         u16 get_bit;
983
984         for (i = 0; i < viafb_load_reg_num; i++) {
985                 reg_mask = 0;
986                 data = 0;
987                 start_index = reg[i].start_bit;
988                 end_index = reg[i].end_bit;
989                 cr_index = reg[i].io_addr;
990
991                 shift_next_reg = bit_num;
992                 for (j = start_index; j <= end_index; j++) {
993                         /*if (bit_num==8) timing_value = timing_value >>8; */
994                         reg_mask = reg_mask | (BIT0 << j);
995                         get_bit = (timing_value & (BIT0 << bit_num));
996                         data =
997                             data | ((get_bit >> shift_next_reg) << start_index);
998                         bit_num++;
999                 }
1000                 if (io_type == VIACR)
1001                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1002                 else
1003                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1004         }
1005
1006 }
1007
1008 /* Write Registers */
1009 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1010 {
1011         int i;
1012
1013         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1014
1015         for (i = 0; i < ItemNum; i++)
1016                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1017                         RegTable[i].value, RegTable[i].mask);
1018 }
1019
1020 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1021 {
1022         int reg_value;
1023         int viafb_load_reg_num;
1024         struct io_register *reg = NULL;
1025
1026         switch (set_iga) {
1027         case IGA1:
1028                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1029                 viafb_load_reg_num = fetch_count_reg.
1030                         iga1_fetch_count_reg.reg_num;
1031                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1032                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1033                 break;
1034         case IGA2:
1035                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1036                 viafb_load_reg_num = fetch_count_reg.
1037                         iga2_fetch_count_reg.reg_num;
1038                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1039                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1040                 break;
1041         }
1042
1043 }
1044
1045 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1046 {
1047         int reg_value;
1048         int viafb_load_reg_num;
1049         struct io_register *reg = NULL;
1050         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1051             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1052         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1053             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1054
1055         if (set_iga == IGA1) {
1056                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1057                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1058                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1059                         iga1_fifo_high_threshold =
1060                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1061                         /* If resolution > 1280x1024, expire length = 64, else
1062                            expire length = 128 */
1063                         if ((hor_active > 1280) && (ver_active > 1024))
1064                                 iga1_display_queue_expire_num = 16;
1065                         else
1066                                 iga1_display_queue_expire_num =
1067                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1068
1069                 }
1070
1071                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1072                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1073                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1074                         iga1_fifo_high_threshold =
1075                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1076                         iga1_display_queue_expire_num =
1077                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1078
1079                         /* If resolution > 1280x1024, expire length = 64, else
1080                            expire length = 128 */
1081                         if ((hor_active > 1280) && (ver_active > 1024))
1082                                 iga1_display_queue_expire_num = 16;
1083                         else
1084                                 iga1_display_queue_expire_num =
1085                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1086                 }
1087
1088                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1089                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1090                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1091                         iga1_fifo_high_threshold =
1092                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1093
1094                         /* If resolution > 1280x1024, expire length = 64,
1095                            else expire length = 128 */
1096                         if ((hor_active > 1280) && (ver_active > 1024))
1097                                 iga1_display_queue_expire_num = 16;
1098                         else
1099                                 iga1_display_queue_expire_num =
1100                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1101                 }
1102
1103                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1104                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1105                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1106                         iga1_fifo_high_threshold =
1107                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1108                         iga1_display_queue_expire_num =
1109                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1110                 }
1111
1112                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1113                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1114                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1115                         iga1_fifo_high_threshold =
1116                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1117                         iga1_display_queue_expire_num =
1118                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1119                 }
1120
1121                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1122                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1123                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1124                         iga1_fifo_high_threshold =
1125                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1126                         iga1_display_queue_expire_num =
1127                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1128                 }
1129
1130                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1131                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1132                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1133                         iga1_fifo_high_threshold =
1134                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1135                         iga1_display_queue_expire_num =
1136                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1137                 }
1138
1139                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1140                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1141                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1142                         iga1_fifo_high_threshold =
1143                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1144                         iga1_display_queue_expire_num =
1145                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1146                 }
1147
1148                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1149                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1150                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1151                         iga1_fifo_high_threshold =
1152                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1153                         iga1_display_queue_expire_num =
1154                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1155                 }
1156
1157                 /* Set Display FIFO Depath Select */
1158                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1159                 viafb_load_reg_num =
1160                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1161                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1162                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1163
1164                 /* Set Display FIFO Threshold Select */
1165                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1166                 viafb_load_reg_num =
1167                     fifo_threshold_select_reg.
1168                     iga1_fifo_threshold_select_reg.reg_num;
1169                 reg =
1170                     fifo_threshold_select_reg.
1171                     iga1_fifo_threshold_select_reg.reg;
1172                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1173
1174                 /* Set FIFO High Threshold Select */
1175                 reg_value =
1176                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1177                 viafb_load_reg_num =
1178                     fifo_high_threshold_select_reg.
1179                     iga1_fifo_high_threshold_select_reg.reg_num;
1180                 reg =
1181                     fifo_high_threshold_select_reg.
1182                     iga1_fifo_high_threshold_select_reg.reg;
1183                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1184
1185                 /* Set Display Queue Expire Num */
1186                 reg_value =
1187                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1188                     (iga1_display_queue_expire_num);
1189                 viafb_load_reg_num =
1190                     display_queue_expire_num_reg.
1191                     iga1_display_queue_expire_num_reg.reg_num;
1192                 reg =
1193                     display_queue_expire_num_reg.
1194                     iga1_display_queue_expire_num_reg.reg;
1195                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1196
1197         } else {
1198                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1199                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1200                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1201                         iga2_fifo_high_threshold =
1202                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1203
1204                         /* If resolution > 1280x1024, expire length = 64,
1205                            else  expire length = 128 */
1206                         if ((hor_active > 1280) && (ver_active > 1024))
1207                                 iga2_display_queue_expire_num = 16;
1208                         else
1209                                 iga2_display_queue_expire_num =
1210                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1211                 }
1212
1213                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1214                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1215                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1216                         iga2_fifo_high_threshold =
1217                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1218
1219                         /* If resolution > 1280x1024, expire length = 64,
1220                            else  expire length = 128 */
1221                         if ((hor_active > 1280) && (ver_active > 1024))
1222                                 iga2_display_queue_expire_num = 16;
1223                         else
1224                                 iga2_display_queue_expire_num =
1225                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1226                 }
1227
1228                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1229                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1230                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1231                         iga2_fifo_high_threshold =
1232                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1233
1234                         /* If resolution > 1280x1024, expire length = 64,
1235                            else expire length = 128 */
1236                         if ((hor_active > 1280) && (ver_active > 1024))
1237                                 iga2_display_queue_expire_num = 16;
1238                         else
1239                                 iga2_display_queue_expire_num =
1240                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1241                 }
1242
1243                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1244                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1245                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1246                         iga2_fifo_high_threshold =
1247                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1248                         iga2_display_queue_expire_num =
1249                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1250                 }
1251
1252                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1253                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1254                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1255                         iga2_fifo_high_threshold =
1256                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1257                         iga2_display_queue_expire_num =
1258                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1259                 }
1260
1261                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1262                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1263                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1264                         iga2_fifo_high_threshold =
1265                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1266                         iga2_display_queue_expire_num =
1267                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1268                 }
1269
1270                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1271                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1272                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1273                         iga2_fifo_high_threshold =
1274                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1275                         iga2_display_queue_expire_num =
1276                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1277                 }
1278
1279                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1280                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1281                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1282                         iga2_fifo_high_threshold =
1283                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1284                         iga2_display_queue_expire_num =
1285                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1286                 }
1287
1288                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1289                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1290                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1291                         iga2_fifo_high_threshold =
1292                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1293                         iga2_display_queue_expire_num =
1294                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1295                 }
1296
1297                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1298                         /* Set Display FIFO Depath Select */
1299                         reg_value =
1300                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1301                             - 1;
1302                         /* Patch LCD in IGA2 case */
1303                         viafb_load_reg_num =
1304                             display_fifo_depth_reg.
1305                             iga2_fifo_depth_select_reg.reg_num;
1306                         reg =
1307                             display_fifo_depth_reg.
1308                             iga2_fifo_depth_select_reg.reg;
1309                         viafb_load_reg(reg_value,
1310                                 viafb_load_reg_num, reg, VIACR);
1311                 } else {
1312
1313                         /* Set Display FIFO Depath Select */
1314                         reg_value =
1315                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1316                         viafb_load_reg_num =
1317                             display_fifo_depth_reg.
1318                             iga2_fifo_depth_select_reg.reg_num;
1319                         reg =
1320                             display_fifo_depth_reg.
1321                             iga2_fifo_depth_select_reg.reg;
1322                         viafb_load_reg(reg_value,
1323                                 viafb_load_reg_num, reg, VIACR);
1324                 }
1325
1326                 /* Set Display FIFO Threshold Select */
1327                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1328                 viafb_load_reg_num =
1329                     fifo_threshold_select_reg.
1330                     iga2_fifo_threshold_select_reg.reg_num;
1331                 reg =
1332                     fifo_threshold_select_reg.
1333                     iga2_fifo_threshold_select_reg.reg;
1334                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1335
1336                 /* Set FIFO High Threshold Select */
1337                 reg_value =
1338                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1339                 viafb_load_reg_num =
1340                     fifo_high_threshold_select_reg.
1341                     iga2_fifo_high_threshold_select_reg.reg_num;
1342                 reg =
1343                     fifo_high_threshold_select_reg.
1344                     iga2_fifo_high_threshold_select_reg.reg;
1345                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1346
1347                 /* Set Display Queue Expire Num */
1348                 reg_value =
1349                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1350                     (iga2_display_queue_expire_num);
1351                 viafb_load_reg_num =
1352                     display_queue_expire_num_reg.
1353                     iga2_display_queue_expire_num_reg.reg_num;
1354                 reg =
1355                     display_queue_expire_num_reg.
1356                     iga2_display_queue_expire_num_reg.reg;
1357                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1358
1359         }
1360
1361 }
1362
1363 u32 viafb_get_clk_value(int clk)
1364 {
1365         int i;
1366
1367         for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1368                 if (clk == pll_value[i].clk) {
1369                         switch (viaparinfo->chip_info->gfx_chip_name) {
1370                         case UNICHROME_CLE266:
1371                         case UNICHROME_K400:
1372                                 return pll_value[i].cle266_pll;
1373
1374                         case UNICHROME_K800:
1375                         case UNICHROME_PM800:
1376                         case UNICHROME_CN700:
1377                                 return pll_value[i].k800_pll;
1378
1379                         case UNICHROME_CX700:
1380                         case UNICHROME_K8M890:
1381                         case UNICHROME_P4M890:
1382                         case UNICHROME_P4M900:
1383                         case UNICHROME_VX800:
1384                                 return pll_value[i].cx700_pll;
1385                         case UNICHROME_VX855:
1386                                 return pll_value[i].vx855_pll;
1387                         }
1388                 }
1389         }
1390
1391         DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1392         return 0;
1393 }
1394
1395 /* Set VCLK*/
1396 void viafb_set_vclock(u32 CLK, int set_iga)
1397 {
1398         /* H.W. Reset : ON */
1399         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1400
1401         if (set_iga == IGA1) {
1402                 /* Change D,N FOR VCLK */
1403                 switch (viaparinfo->chip_info->gfx_chip_name) {
1404                 case UNICHROME_CLE266:
1405                 case UNICHROME_K400:
1406                         viafb_write_reg(SR46, VIASR, CLK / 0x100);
1407                         viafb_write_reg(SR47, VIASR, CLK % 0x100);
1408                         break;
1409
1410                 case UNICHROME_K800:
1411                 case UNICHROME_PM800:
1412                 case UNICHROME_CN700:
1413                 case UNICHROME_CX700:
1414                 case UNICHROME_K8M890:
1415                 case UNICHROME_P4M890:
1416                 case UNICHROME_P4M900:
1417                 case UNICHROME_VX800:
1418                 case UNICHROME_VX855:
1419                         viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1420                         DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1421                         viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1422                         DEBUG_MSG(KERN_INFO "\nSR45=%x",
1423                                   (CLK & 0xFFFF) / 0x100);
1424                         viafb_write_reg(SR46, VIASR, CLK % 0x100);
1425                         DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1426                         break;
1427                 }
1428         }
1429
1430         if (set_iga == IGA2) {
1431                 /* Change D,N FOR LCK */
1432                 switch (viaparinfo->chip_info->gfx_chip_name) {
1433                 case UNICHROME_CLE266:
1434                 case UNICHROME_K400:
1435                         viafb_write_reg(SR44, VIASR, CLK / 0x100);
1436                         viafb_write_reg(SR45, VIASR, CLK % 0x100);
1437                         break;
1438
1439                 case UNICHROME_K800:
1440                 case UNICHROME_PM800:
1441                 case UNICHROME_CN700:
1442                 case UNICHROME_CX700:
1443                 case UNICHROME_K8M890:
1444                 case UNICHROME_P4M890:
1445                 case UNICHROME_P4M900:
1446                 case UNICHROME_VX800:
1447                 case UNICHROME_VX855:
1448                         viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1449                         viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1450                         viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1451                         break;
1452                 }
1453         }
1454
1455         /* H.W. Reset : OFF */
1456         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1457
1458         /* Reset PLL */
1459         if (set_iga == IGA1) {
1460                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1461                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1462         }
1463
1464         if (set_iga == IGA2) {
1465                 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1466                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1467         }
1468
1469         /* Fire! */
1470         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1471 }
1472
1473 void viafb_load_crtc_timing(struct display_timing device_timing,
1474         int set_iga)
1475 {
1476         int i;
1477         int viafb_load_reg_num = 0;
1478         int reg_value = 0;
1479         struct io_register *reg = NULL;
1480
1481         viafb_unlock_crt();
1482
1483         for (i = 0; i < 12; i++) {
1484                 if (set_iga == IGA1) {
1485                         switch (i) {
1486                         case H_TOTAL_INDEX:
1487                                 reg_value =
1488                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1489                                                            hor_total);
1490                                 viafb_load_reg_num =
1491                                         iga1_crtc_reg.hor_total.reg_num;
1492                                 reg = iga1_crtc_reg.hor_total.reg;
1493                                 break;
1494                         case H_ADDR_INDEX:
1495                                 reg_value =
1496                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1497                                                           hor_addr);
1498                                 viafb_load_reg_num =
1499                                         iga1_crtc_reg.hor_addr.reg_num;
1500                                 reg = iga1_crtc_reg.hor_addr.reg;
1501                                 break;
1502                         case H_BLANK_START_INDEX:
1503                                 reg_value =
1504                                     IGA1_HOR_BLANK_START_FORMULA
1505                                     (device_timing.hor_blank_start);
1506                                 viafb_load_reg_num =
1507                                     iga1_crtc_reg.hor_blank_start.reg_num;
1508                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1509                                 break;
1510                         case H_BLANK_END_INDEX:
1511                                 reg_value =
1512                                     IGA1_HOR_BLANK_END_FORMULA
1513                                     (device_timing.hor_blank_start,
1514                                      device_timing.hor_blank_end);
1515                                 viafb_load_reg_num =
1516                                     iga1_crtc_reg.hor_blank_end.reg_num;
1517                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1518                                 break;
1519                         case H_SYNC_START_INDEX:
1520                                 reg_value =
1521                                     IGA1_HOR_SYNC_START_FORMULA
1522                                     (device_timing.hor_sync_start);
1523                                 viafb_load_reg_num =
1524                                     iga1_crtc_reg.hor_sync_start.reg_num;
1525                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1526                                 break;
1527                         case H_SYNC_END_INDEX:
1528                                 reg_value =
1529                                     IGA1_HOR_SYNC_END_FORMULA
1530                                     (device_timing.hor_sync_start,
1531                                      device_timing.hor_sync_end);
1532                                 viafb_load_reg_num =
1533                                     iga1_crtc_reg.hor_sync_end.reg_num;
1534                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1535                                 break;
1536                         case V_TOTAL_INDEX:
1537                                 reg_value =
1538                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1539                                                            ver_total);
1540                                 viafb_load_reg_num =
1541                                         iga1_crtc_reg.ver_total.reg_num;
1542                                 reg = iga1_crtc_reg.ver_total.reg;
1543                                 break;
1544                         case V_ADDR_INDEX:
1545                                 reg_value =
1546                                     IGA1_VER_ADDR_FORMULA(device_timing.
1547                                                           ver_addr);
1548                                 viafb_load_reg_num =
1549                                         iga1_crtc_reg.ver_addr.reg_num;
1550                                 reg = iga1_crtc_reg.ver_addr.reg;
1551                                 break;
1552                         case V_BLANK_START_INDEX:
1553                                 reg_value =
1554                                     IGA1_VER_BLANK_START_FORMULA
1555                                     (device_timing.ver_blank_start);
1556                                 viafb_load_reg_num =
1557                                     iga1_crtc_reg.ver_blank_start.reg_num;
1558                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1559                                 break;
1560                         case V_BLANK_END_INDEX:
1561                                 reg_value =
1562                                     IGA1_VER_BLANK_END_FORMULA
1563                                     (device_timing.ver_blank_start,
1564                                      device_timing.ver_blank_end);
1565                                 viafb_load_reg_num =
1566                                     iga1_crtc_reg.ver_blank_end.reg_num;
1567                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1568                                 break;
1569                         case V_SYNC_START_INDEX:
1570                                 reg_value =
1571                                     IGA1_VER_SYNC_START_FORMULA
1572                                     (device_timing.ver_sync_start);
1573                                 viafb_load_reg_num =
1574                                     iga1_crtc_reg.ver_sync_start.reg_num;
1575                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1576                                 break;
1577                         case V_SYNC_END_INDEX:
1578                                 reg_value =
1579                                     IGA1_VER_SYNC_END_FORMULA
1580                                     (device_timing.ver_sync_start,
1581                                      device_timing.ver_sync_end);
1582                                 viafb_load_reg_num =
1583                                     iga1_crtc_reg.ver_sync_end.reg_num;
1584                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1585                                 break;
1586
1587                         }
1588                 }
1589
1590                 if (set_iga == IGA2) {
1591                         switch (i) {
1592                         case H_TOTAL_INDEX:
1593                                 reg_value =
1594                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1595                                                            hor_total);
1596                                 viafb_load_reg_num =
1597                                         iga2_crtc_reg.hor_total.reg_num;
1598                                 reg = iga2_crtc_reg.hor_total.reg;
1599                                 break;
1600                         case H_ADDR_INDEX:
1601                                 reg_value =
1602                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1603                                                           hor_addr);
1604                                 viafb_load_reg_num =
1605                                         iga2_crtc_reg.hor_addr.reg_num;
1606                                 reg = iga2_crtc_reg.hor_addr.reg;
1607                                 break;
1608                         case H_BLANK_START_INDEX:
1609                                 reg_value =
1610                                     IGA2_HOR_BLANK_START_FORMULA
1611                                     (device_timing.hor_blank_start);
1612                                 viafb_load_reg_num =
1613                                     iga2_crtc_reg.hor_blank_start.reg_num;
1614                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1615                                 break;
1616                         case H_BLANK_END_INDEX:
1617                                 reg_value =
1618                                     IGA2_HOR_BLANK_END_FORMULA
1619                                     (device_timing.hor_blank_start,
1620                                      device_timing.hor_blank_end);
1621                                 viafb_load_reg_num =
1622                                     iga2_crtc_reg.hor_blank_end.reg_num;
1623                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1624                                 break;
1625                         case H_SYNC_START_INDEX:
1626                                 reg_value =
1627                                     IGA2_HOR_SYNC_START_FORMULA
1628                                     (device_timing.hor_sync_start);
1629                                 if (UNICHROME_CN700 <=
1630                                         viaparinfo->chip_info->gfx_chip_name)
1631                                         viafb_load_reg_num =
1632                                             iga2_crtc_reg.hor_sync_start.
1633                                             reg_num;
1634                                 else
1635                                         viafb_load_reg_num = 3;
1636                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1637                                 break;
1638                         case H_SYNC_END_INDEX:
1639                                 reg_value =
1640                                     IGA2_HOR_SYNC_END_FORMULA
1641                                     (device_timing.hor_sync_start,
1642                                      device_timing.hor_sync_end);
1643                                 viafb_load_reg_num =
1644                                     iga2_crtc_reg.hor_sync_end.reg_num;
1645                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1646                                 break;
1647                         case V_TOTAL_INDEX:
1648                                 reg_value =
1649                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1650                                                            ver_total);
1651                                 viafb_load_reg_num =
1652                                         iga2_crtc_reg.ver_total.reg_num;
1653                                 reg = iga2_crtc_reg.ver_total.reg;
1654                                 break;
1655                         case V_ADDR_INDEX:
1656                                 reg_value =
1657                                     IGA2_VER_ADDR_FORMULA(device_timing.
1658                                                           ver_addr);
1659                                 viafb_load_reg_num =
1660                                         iga2_crtc_reg.ver_addr.reg_num;
1661                                 reg = iga2_crtc_reg.ver_addr.reg;
1662                                 break;
1663                         case V_BLANK_START_INDEX:
1664                                 reg_value =
1665                                     IGA2_VER_BLANK_START_FORMULA
1666                                     (device_timing.ver_blank_start);
1667                                 viafb_load_reg_num =
1668                                     iga2_crtc_reg.ver_blank_start.reg_num;
1669                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1670                                 break;
1671                         case V_BLANK_END_INDEX:
1672                                 reg_value =
1673                                     IGA2_VER_BLANK_END_FORMULA
1674                                     (device_timing.ver_blank_start,
1675                                      device_timing.ver_blank_end);
1676                                 viafb_load_reg_num =
1677                                     iga2_crtc_reg.ver_blank_end.reg_num;
1678                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1679                                 break;
1680                         case V_SYNC_START_INDEX:
1681                                 reg_value =
1682                                     IGA2_VER_SYNC_START_FORMULA
1683                                     (device_timing.ver_sync_start);
1684                                 viafb_load_reg_num =
1685                                     iga2_crtc_reg.ver_sync_start.reg_num;
1686                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1687                                 break;
1688                         case V_SYNC_END_INDEX:
1689                                 reg_value =
1690                                     IGA2_VER_SYNC_END_FORMULA
1691                                     (device_timing.ver_sync_start,
1692                                      device_timing.ver_sync_end);
1693                                 viafb_load_reg_num =
1694                                     iga2_crtc_reg.ver_sync_end.reg_num;
1695                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1696                                 break;
1697
1698                         }
1699                 }
1700                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1701         }
1702
1703         viafb_lock_crt();
1704 }
1705
1706 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1707         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1708 {
1709         struct display_timing crt_reg;
1710         int i;
1711         int index = 0;
1712         int h_addr, v_addr;
1713         u32 pll_D_N;
1714         u8 polarity = 0;
1715
1716         for (i = 0; i < video_mode->mode_array; i++) {
1717                 index = i;
1718
1719                 if (crt_table[i].refresh_rate == viaparinfo->
1720                         crt_setting_info->refresh_rate)
1721                         break;
1722         }
1723
1724         crt_reg = crt_table[index].crtc;
1725
1726         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1727         /* So we would delete border. */
1728         if ((viafb_LCD_ON | viafb_DVI_ON)
1729             && video_mode->crtc[0].crtc.hor_addr == 640
1730             && video_mode->crtc[0].crtc.ver_addr == 480
1731             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1732                 /* The border is 8 pixels. */
1733                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1734
1735                 /* Blanking time should add left and right borders. */
1736                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1737         }
1738
1739         h_addr = crt_reg.hor_addr;
1740         v_addr = crt_reg.ver_addr;
1741
1742         /* update polarity for CRT timing */
1743         if (crt_table[index].h_sync_polarity == NEGATIVE)
1744                 polarity |= BIT6;
1745         if (crt_table[index].v_sync_polarity == NEGATIVE)
1746                 polarity |= BIT7;
1747         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1748
1749         if (set_iga == IGA1) {
1750                 viafb_unlock_crt();
1751                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1752                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1753                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1754         }
1755
1756         switch (set_iga) {
1757         case IGA1:
1758                 viafb_load_crtc_timing(crt_reg, IGA1);
1759                 break;
1760         case IGA2:
1761                 viafb_load_crtc_timing(crt_reg, IGA2);
1762                 break;
1763         }
1764
1765         load_fix_bit_crtc_reg();
1766         viafb_lock_crt();
1767         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1768         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1769
1770         /* load FIFO */
1771         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1772             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1773                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1774
1775         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1776         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1777         viafb_set_vclock(pll_D_N, set_iga);
1778
1779 }
1780
1781 void viafb_init_chip_info(int chip_type)
1782 {
1783         init_gfx_chip_info(chip_type);
1784         init_tmds_chip_info();
1785         init_lvds_chip_info();
1786
1787         viaparinfo->crt_setting_info->iga_path = IGA1;
1788         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1789
1790         /*Set IGA path for each device */
1791         viafb_set_iga_path();
1792
1793         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1794         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1795         viaparinfo->lvds_setting_info2->display_method =
1796                 viaparinfo->lvds_setting_info->display_method;
1797         viaparinfo->lvds_setting_info2->lcd_mode =
1798                 viaparinfo->lvds_setting_info->lcd_mode;
1799 }
1800
1801 void viafb_update_device_setting(int hres, int vres,
1802         int bpp, int vmode_refresh, int flag)
1803 {
1804         if (flag == 0) {
1805                 viaparinfo->crt_setting_info->h_active = hres;
1806                 viaparinfo->crt_setting_info->v_active = vres;
1807                 viaparinfo->crt_setting_info->bpp = bpp;
1808                 viaparinfo->crt_setting_info->refresh_rate =
1809                         vmode_refresh;
1810
1811                 viaparinfo->tmds_setting_info->h_active = hres;
1812                 viaparinfo->tmds_setting_info->v_active = vres;
1813
1814                 viaparinfo->lvds_setting_info->h_active = hres;
1815                 viaparinfo->lvds_setting_info->v_active = vres;
1816                 viaparinfo->lvds_setting_info->bpp = bpp;
1817                 viaparinfo->lvds_setting_info->refresh_rate =
1818                         vmode_refresh;
1819                 viaparinfo->lvds_setting_info2->h_active = hres;
1820                 viaparinfo->lvds_setting_info2->v_active = vres;
1821                 viaparinfo->lvds_setting_info2->bpp = bpp;
1822                 viaparinfo->lvds_setting_info2->refresh_rate =
1823                         vmode_refresh;
1824         } else {
1825
1826                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1827                         viaparinfo->tmds_setting_info->h_active = hres;
1828                         viaparinfo->tmds_setting_info->v_active = vres;
1829                 }
1830
1831                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1832                         viaparinfo->lvds_setting_info->h_active = hres;
1833                         viaparinfo->lvds_setting_info->v_active = vres;
1834                         viaparinfo->lvds_setting_info->bpp = bpp;
1835                         viaparinfo->lvds_setting_info->refresh_rate =
1836                                 vmode_refresh;
1837                 }
1838                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1839                         viaparinfo->lvds_setting_info2->h_active = hres;
1840                         viaparinfo->lvds_setting_info2->v_active = vres;
1841                         viaparinfo->lvds_setting_info2->bpp = bpp;
1842                         viaparinfo->lvds_setting_info2->refresh_rate =
1843                                 vmode_refresh;
1844                 }
1845         }
1846 }
1847
1848 static void init_gfx_chip_info(int chip_type)
1849 {
1850         u8 tmp;
1851
1852         viaparinfo->chip_info->gfx_chip_name = chip_type;
1853
1854         /* Check revision of CLE266 Chip */
1855         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1856                 /* CR4F only define in CLE266.CX chip */
1857                 tmp = viafb_read_reg(VIACR, CR4F);
1858                 viafb_write_reg(CR4F, VIACR, 0x55);
1859                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1860                         viaparinfo->chip_info->gfx_chip_revision =
1861                         CLE266_REVISION_AX;
1862                 else
1863                         viaparinfo->chip_info->gfx_chip_revision =
1864                         CLE266_REVISION_CX;
1865                 /* restore orignal CR4F value */
1866                 viafb_write_reg(CR4F, VIACR, tmp);
1867         }
1868
1869         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1870                 tmp = viafb_read_reg(VIASR, SR43);
1871                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1872                 if (tmp & 0x02) {
1873                         viaparinfo->chip_info->gfx_chip_revision =
1874                                 CX700_REVISION_700M2;
1875                 } else if (tmp & 0x40) {
1876                         viaparinfo->chip_info->gfx_chip_revision =
1877                                 CX700_REVISION_700M;
1878                 } else {
1879                         viaparinfo->chip_info->gfx_chip_revision =
1880                                 CX700_REVISION_700;
1881                 }
1882         }
1883
1884         /* Determine which 2D engine we have */
1885         switch (viaparinfo->chip_info->gfx_chip_name) {
1886         case UNICHROME_VX800:
1887         case UNICHROME_VX855:
1888                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
1889                 break;
1890         case UNICHROME_K8M890:
1891         case UNICHROME_P4M900:
1892                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
1893                 break;
1894         default:
1895                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
1896                 break;
1897         }
1898 }
1899
1900 static void init_tmds_chip_info(void)
1901 {
1902         viafb_tmds_trasmitter_identify();
1903
1904         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
1905                 output_interface) {
1906                 switch (viaparinfo->chip_info->gfx_chip_name) {
1907                 case UNICHROME_CX700:
1908                         {
1909                                 /* we should check support by hardware layout.*/
1910                                 if ((viafb_display_hardware_layout ==
1911                                      HW_LAYOUT_DVI_ONLY)
1912                                     || (viafb_display_hardware_layout ==
1913                                         HW_LAYOUT_LCD_DVI)) {
1914                                         viaparinfo->chip_info->tmds_chip_info.
1915                                             output_interface = INTERFACE_TMDS;
1916                                 } else {
1917                                         viaparinfo->chip_info->tmds_chip_info.
1918                                                 output_interface =
1919                                                 INTERFACE_NONE;
1920                                 }
1921                                 break;
1922                         }
1923                 case UNICHROME_K8M890:
1924                 case UNICHROME_P4M900:
1925                 case UNICHROME_P4M890:
1926                         /* TMDS on PCIE, we set DFPLOW as default. */
1927                         viaparinfo->chip_info->tmds_chip_info.output_interface =
1928                             INTERFACE_DFP_LOW;
1929                         break;
1930                 default:
1931                         {
1932                                 /* set DVP1 default for DVI */
1933                                 viaparinfo->chip_info->tmds_chip_info
1934                                 .output_interface = INTERFACE_DVP1;
1935                         }
1936                 }
1937         }
1938
1939         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
1940                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
1941         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
1942                 &viaparinfo->shared->tmds_setting_info);
1943 }
1944
1945 static void init_lvds_chip_info(void)
1946 {
1947         viafb_lvds_trasmitter_identify();
1948         viafb_init_lcd_size();
1949         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
1950                                    viaparinfo->lvds_setting_info);
1951         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
1952                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
1953                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
1954         }
1955         /*If CX700,two singel LCD, we need to reassign
1956            LCD interface to different LVDS port */
1957         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
1958             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
1959                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
1960                         lvds_chip_name) && (INTEGRATED_LVDS ==
1961                         viaparinfo->chip_info->
1962                         lvds_chip_info2.lvds_chip_name)) {
1963                         viaparinfo->chip_info->lvds_chip_info.output_interface =
1964                                 INTERFACE_LVDS0;
1965                         viaparinfo->chip_info->lvds_chip_info2.
1966                                 output_interface =
1967                             INTERFACE_LVDS1;
1968                 }
1969         }
1970
1971         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
1972                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
1973         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
1974                   viaparinfo->chip_info->lvds_chip_info.output_interface);
1975         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
1976                   viaparinfo->chip_info->lvds_chip_info.output_interface);
1977 }
1978
1979 void viafb_init_dac(int set_iga)
1980 {
1981         int i;
1982         u8 tmp;
1983
1984         if (set_iga == IGA1) {
1985                 /* access Primary Display's LUT */
1986                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
1987                 /* turn off LCK */
1988                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
1989                 for (i = 0; i < 256; i++) {
1990                         write_dac_reg(i, palLUT_table[i].red,
1991                                       palLUT_table[i].green,
1992                                       palLUT_table[i].blue);
1993                 }
1994                 /* turn on LCK */
1995                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
1996         } else {
1997                 tmp = viafb_read_reg(VIACR, CR6A);
1998                 /* access Secondary Display's LUT */
1999                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2000                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2001                 for (i = 0; i < 256; i++) {
2002                         write_dac_reg(i, palLUT_table[i].red,
2003                                       palLUT_table[i].green,
2004                                       palLUT_table[i].blue);
2005                 }
2006                 /* set IGA1 DAC for default */
2007                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2008                 viafb_write_reg(CR6A, VIACR, tmp);
2009         }
2010 }
2011
2012 static void device_screen_off(void)
2013 {
2014         /* turn off CRT screen (IGA1) */
2015         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2016 }
2017
2018 static void device_screen_on(void)
2019 {
2020         /* turn on CRT screen (IGA1) */
2021         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2022 }
2023
2024 static void set_display_channel(void)
2025 {
2026         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2027         is keeped on lvds_setting_info2 */
2028         if (viafb_LCD2_ON &&
2029                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2030                 /* For dual channel LCD: */
2031                 /* Set to Dual LVDS channel. */
2032                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2033         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2034                 /* For LCD+DFP: */
2035                 /* Set to LVDS1 + TMDS channel. */
2036                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2037         } else if (viafb_DVI_ON) {
2038                 /* Set to single TMDS channel. */
2039                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2040         } else if (viafb_LCD_ON) {
2041                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2042                         /* For dual channel LCD: */
2043                         /* Set to Dual LVDS channel. */
2044                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2045                 } else {
2046                         /* Set to LVDS0 + LVDS1 channel. */
2047                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2048                 }
2049         }
2050 }
2051
2052 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2053         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2054 {
2055         int i, j;
2056         int port;
2057         u8 value, index, mask;
2058         struct crt_mode_table *crt_timing;
2059         struct crt_mode_table *crt_timing1 = NULL;
2060
2061         device_screen_off();
2062         crt_timing = vmode_tbl->crtc;
2063
2064         if (viafb_SAMM_ON == 1) {
2065                 crt_timing1 = vmode_tbl1->crtc;
2066         }
2067
2068         inb(VIAStatus);
2069         outb(0x00, VIAAR);
2070
2071         /* Write Common Setting for Video Mode */
2072         switch (viaparinfo->chip_info->gfx_chip_name) {
2073         case UNICHROME_CLE266:
2074                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2075                 break;
2076
2077         case UNICHROME_K400:
2078                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2079                 break;
2080
2081         case UNICHROME_K800:
2082         case UNICHROME_PM800:
2083                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2084                 break;
2085
2086         case UNICHROME_CN700:
2087         case UNICHROME_K8M890:
2088         case UNICHROME_P4M890:
2089         case UNICHROME_P4M900:
2090                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2091                 break;
2092
2093         case UNICHROME_CX700:
2094         case UNICHROME_VX800:
2095                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2096                 break;
2097
2098         case UNICHROME_VX855:
2099                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2100                 break;
2101         }
2102
2103         device_off();
2104
2105         /* Fill VPIT Parameters */
2106         /* Write Misc Register */
2107         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2108
2109         /* Write Sequencer */
2110         for (i = 1; i <= StdSR; i++)
2111                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2112
2113         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2114         viafb_set_iga_path();
2115
2116         /* Write CRTC */
2117         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2118
2119         /* Write Graphic Controller */
2120         for (i = 0; i < StdGR; i++)
2121                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2122
2123         /* Write Attribute Controller */
2124         for (i = 0; i < StdAR; i++) {
2125                 inb(VIAStatus);
2126                 outb(i, VIAAR);
2127                 outb(VPIT.AR[i], VIAAR);
2128         }
2129
2130         inb(VIAStatus);
2131         outb(0x20, VIAAR);
2132
2133         /* Update Patch Register */
2134
2135         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2136             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2137             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2138             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2139                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2140                         index = res_patch_table[0].io_reg_table[j].index;
2141                         port = res_patch_table[0].io_reg_table[j].port;
2142                         value = res_patch_table[0].io_reg_table[j].value;
2143                         mask = res_patch_table[0].io_reg_table[j].mask;
2144                         viafb_write_reg_mask(index, port, value, mask);
2145                 }
2146         }
2147
2148         via_set_primary_pitch(viafbinfo->fix.line_length);
2149         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2150                 : viafbinfo->fix.line_length);
2151         via_set_primary_color_depth(viaparinfo->depth);
2152         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2153                 : viaparinfo->depth);
2154         /* Update Refresh Rate Setting */
2155
2156         /* Clear On Screen */
2157
2158         /* CRT set mode */
2159         if (viafb_CRT_ON) {
2160                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2161                         IGA2)) {
2162                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2163                                 video_bpp1 / 8,
2164                                 viaparinfo->crt_setting_info->iga_path);
2165                 } else {
2166                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2167                                 video_bpp / 8,
2168                                 viaparinfo->crt_setting_info->iga_path);
2169                 }
2170
2171                 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2172
2173                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2174                 to 8 alignment (1368),there is several pixels (2 pixels)
2175                 on right side of screen. */
2176                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2177                         viafb_unlock_crt();
2178                         viafb_write_reg(CR02, VIACR,
2179                                 viafb_read_reg(VIACR, CR02) - 1);
2180                         viafb_lock_crt();
2181                 }
2182         }
2183
2184         if (viafb_DVI_ON) {
2185                 if (viafb_SAMM_ON &&
2186                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2187                         viafb_dvi_set_mode(viafb_get_mode
2188                                      (viaparinfo->tmds_setting_info->h_active,
2189                                       viaparinfo->tmds_setting_info->
2190                                       v_active),
2191                                      video_bpp1, viaparinfo->
2192                                      tmds_setting_info->iga_path);
2193                 } else {
2194                         viafb_dvi_set_mode(viafb_get_mode
2195                                      (viaparinfo->tmds_setting_info->h_active,
2196                                       viaparinfo->
2197                                       tmds_setting_info->v_active),
2198                                      video_bpp, viaparinfo->
2199                                      tmds_setting_info->iga_path);
2200                 }
2201         }
2202
2203         if (viafb_LCD_ON) {
2204                 if (viafb_SAMM_ON &&
2205                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2206                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2207                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2208                                 lvds_setting_info,
2209                                      &viaparinfo->chip_info->lvds_chip_info);
2210                 } else {
2211                         /* IGA1 doesn't have LCD scaling, so set it center. */
2212                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2213                                 viaparinfo->lvds_setting_info->display_method =
2214                                     LCD_CENTERING;
2215                         }
2216                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2217                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2218                                 lvds_setting_info,
2219                                      &viaparinfo->chip_info->lvds_chip_info);
2220                 }
2221         }
2222         if (viafb_LCD2_ON) {
2223                 if (viafb_SAMM_ON &&
2224                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2225                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2226                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2227                                 lvds_setting_info2,
2228                                      &viaparinfo->chip_info->lvds_chip_info2);
2229                 } else {
2230                         /* IGA1 doesn't have LCD scaling, so set it center. */
2231                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2232                                 viaparinfo->lvds_setting_info2->display_method =
2233                                     LCD_CENTERING;
2234                         }
2235                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2236                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2237                                 lvds_setting_info2,
2238                                      &viaparinfo->chip_info->lvds_chip_info2);
2239                 }
2240         }
2241
2242         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2243             && (viafb_LCD_ON || viafb_DVI_ON))
2244                 set_display_channel();
2245
2246         /* If set mode normally, save resolution information for hot-plug . */
2247         if (!viafb_hotplug) {
2248                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2249                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2250                 viafb_hotplug_bpp = video_bpp;
2251                 viafb_hotplug_refresh = viafb_refresh;
2252
2253                 if (viafb_DVI_ON)
2254                         viafb_DeviceStatus = DVI_Device;
2255                 else
2256                         viafb_DeviceStatus = CRT_Device;
2257         }
2258         device_on();
2259
2260         if (viafb_SAMM_ON == 1)
2261                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2262
2263         device_screen_on();
2264         return 1;
2265 }
2266
2267 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2268 {
2269         int i;
2270
2271         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2272                 if ((hres == res_map_refresh_tbl[i].hres)
2273                     && (vres == res_map_refresh_tbl[i].vres)
2274                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2275                         return res_map_refresh_tbl[i].pixclock;
2276         }
2277         return RES_640X480_60HZ_PIXCLOCK;
2278
2279 }
2280
2281 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2282 {
2283 #define REFRESH_TOLERANCE 3
2284         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2285         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2286                 if ((hres == res_map_refresh_tbl[i].hres)
2287                     && (vres == res_map_refresh_tbl[i].vres)
2288                     && (diff > (abs(long_refresh -
2289                     res_map_refresh_tbl[i].vmode_refresh)))) {
2290                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2291                                 vmode_refresh);
2292                         nearest = i;
2293                 }
2294         }
2295 #undef REFRESH_TOLERANCE
2296         if (nearest > 0)
2297                 return res_map_refresh_tbl[nearest].vmode_refresh;
2298         return 60;
2299 }
2300
2301 static void device_off(void)
2302 {
2303         viafb_crt_disable();
2304         viafb_dvi_disable();
2305         viafb_lcd_disable();
2306 }
2307
2308 static void device_on(void)
2309 {
2310         if (viafb_CRT_ON == 1)
2311                 viafb_crt_enable();
2312         if (viafb_DVI_ON == 1)
2313                 viafb_dvi_enable();
2314         if (viafb_LCD_ON == 1)
2315                 viafb_lcd_enable();
2316 }
2317
2318 void viafb_crt_disable(void)
2319 {
2320         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2321 }
2322
2323 void viafb_crt_enable(void)
2324 {
2325         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2326 }
2327
2328 static void enable_second_display_channel(void)
2329 {
2330         /* to enable second display channel. */
2331         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2332         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2333         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2334 }
2335
2336 static void disable_second_display_channel(void)
2337 {
2338         /* to disable second display channel. */
2339         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2340         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2341         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2342 }
2343
2344
2345 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2346                                         *p_gfx_dpa_setting)
2347 {
2348         switch (output_interface) {
2349         case INTERFACE_DVP0:
2350                 {
2351                         /* DVP0 Clock Polarity and Adjust: */
2352                         viafb_write_reg_mask(CR96, VIACR,
2353                                        p_gfx_dpa_setting->DVP0, 0x0F);
2354
2355                         /* DVP0 Clock and Data Pads Driving: */
2356                         viafb_write_reg_mask(SR1E, VIASR,
2357                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2358                         viafb_write_reg_mask(SR2A, VIASR,
2359                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2360                                        BIT4);
2361                         viafb_write_reg_mask(SR1B, VIASR,
2362                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2363                         viafb_write_reg_mask(SR2A, VIASR,
2364                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2365                         break;
2366                 }
2367
2368         case INTERFACE_DVP1:
2369                 {
2370                         /* DVP1 Clock Polarity and Adjust: */
2371                         viafb_write_reg_mask(CR9B, VIACR,
2372                                        p_gfx_dpa_setting->DVP1, 0x0F);
2373
2374                         /* DVP1 Clock and Data Pads Driving: */
2375                         viafb_write_reg_mask(SR65, VIASR,
2376                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2377                         break;
2378                 }
2379
2380         case INTERFACE_DFP_HIGH:
2381                 {
2382                         viafb_write_reg_mask(CR97, VIACR,
2383                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2384                         break;
2385                 }
2386
2387         case INTERFACE_DFP_LOW:
2388                 {
2389                         viafb_write_reg_mask(CR99, VIACR,
2390                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2391                         break;
2392                 }
2393
2394         case INTERFACE_DFP:
2395                 {
2396                         viafb_write_reg_mask(CR97, VIACR,
2397                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2398                         viafb_write_reg_mask(CR99, VIACR,
2399                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2400                         break;
2401                 }
2402         }
2403 }
2404
2405 /*According var's xres, yres fill var's other timing information*/
2406 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2407         struct VideoModeTable *vmode_tbl)
2408 {
2409         struct crt_mode_table *crt_timing = NULL;
2410         struct display_timing crt_reg;
2411         int i = 0, index = 0;
2412         crt_timing = vmode_tbl->crtc;
2413         for (i = 0; i < vmode_tbl->mode_array; i++) {
2414                 index = i;
2415                 if (crt_timing[i].refresh_rate == refresh)
2416                         break;
2417         }
2418
2419         crt_reg = crt_timing[index].crtc;
2420         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2421         var->left_margin =
2422             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2423         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2424         var->hsync_len = crt_reg.hor_sync_end;
2425         var->upper_margin =
2426             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2427         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2428         var->vsync_len = crt_reg.ver_sync_end;
2429 }