]> git.openfabrics.org - ~shefty/rdma-dev.git/blob - drivers/video/via/hw.c
viafb: enable second display channel at central place
[~shefty/rdma-dev.git] / drivers / video / via / hw.c
1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 #include <linux/via-core.h>
23 #include "global.h"
24
25 static struct pll_map pll_value[] = {
26         {25175000,
27                 {99, 7, 3},
28                 {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
29                 {141, 5, 4},
30                 {141, 5, 4} },
31         {29581000,
32                 {33, 4, 2},
33                 {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
34                 {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
35                 {165, 5, 4} },
36         {26880000,
37                 {15, 4, 1},
38                 {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
39                 {150, 5, 4},
40                 {150, 5, 4} },
41         {31500000,
42                 {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
43                 {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
44                 {176, 5, 4},
45                 {176, 5, 4} },
46         {31728000,
47                 {31, 7, 1},
48                 {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
49                 {177, 5, 4},
50                 {142, 4, 4} },
51         {32688000,
52                 {73, 4, 3},
53                 {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
54                 {183, 5, 4},
55                 {146, 4, 4} },
56         {36000000,
57                 {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
58                 {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
59                 {202, 5, 4},
60                 {161, 4, 4} },
61         {40000000,
62                 {89, 4, 3},
63                 {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
64                 {112, 5, 3},
65                 {112, 5, 3} },
66         {41291000,
67                 {23, 4, 1},
68                 {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
69                 {115, 5, 3},
70                 {115, 5, 3} },
71         {43163000,
72                 {121, 5, 3},
73                 {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
74                 {121, 5, 3},
75                 {121, 5, 3} },
76         {45250000,
77                 {127, 5, 3},
78                 {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
79                 {127, 5, 3},
80                 {127, 5, 3} },
81         {46000000,
82                 {90, 7, 2},
83                 {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
84                 {129, 5, 3},
85                 {103, 4, 3} },
86         {46996000,
87                 {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
88                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
89                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
90                 {105, 4, 3} },
91         {48000000,
92                 {67, 20, 0},
93                 {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
94                 {134, 5, 3},
95                 {134, 5, 3} },
96         {48875000,
97                 {99, 29, 0},
98                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
99                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
100                 {137, 5, 3} },
101         {49500000,
102                 {83, 6, 2},
103                 {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
104                 {138, 5, 3},
105                 {83, 3, 3} },
106         {52406000,
107                 {117, 4, 3},
108                 {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
109                 {117, 4, 3},
110                 {88, 3, 3} },
111         {52977000,
112                 {37, 5, 1},
113                 {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
114                 {148, 5, 3},
115                 {148, 5, 3} },
116         {56250000,
117                 {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
118                 {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
119                 {157, 5, 3},
120                 {157, 5, 3} },
121         {57275000,
122                 {0, 0, 0},
123                 {2, 2, 0},
124                 {2, 2, 0},
125                 {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
126         {60466000,
127                 {76, 9, 1},
128                 {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
129                 {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
130                 {169, 5, 3} },
131         {61500000,
132                 {86, 20, 0},
133                 {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
134                 {172, 5, 3},
135                 {172, 5, 3} },
136         {65000000,
137                 {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
138                 {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
139                 {109, 3, 3},
140                 {109, 3, 3} },
141         {65178000,
142                 {91, 5, 2},
143                 {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
144                 {109, 3, 3},
145                 {182, 5, 3} },
146         {66750000,
147                 {75, 4, 2},
148                 {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
149                 {150, 4, 3},
150                 {112, 3, 3} },
151         {68179000,
152                 {19, 4, 0},
153                 {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
154                 {190, 5, 3},
155                 {191, 5, 3} },
156         {69924000,
157                 {83, 17, 0},
158                 {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
159                 {195, 5, 3},
160                 {195, 5, 3} },
161         {70159000,
162                 {98, 20, 0},
163                 {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
164                 {196, 5, 3},
165                 {195, 5, 3} },
166         {72000000,
167                 {121, 24, 0},
168                 {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
169                 {161, 4, 3},
170                 {161, 4, 3} },
171         {78750000,
172                 {33, 3, 1},
173                 {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
174                 {110, 5, 2},
175                 {110, 5, 2} },
176         {80136000,
177                 {28, 5, 0},
178                 {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
179                 {112, 5, 2},
180                 {112, 5, 2} },
181         {83375000,
182                 {93, 2, 3},
183                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
184                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
185                 {117, 5, 2} },
186         {83950000,
187                 {41, 7, 0},
188                 {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
189                 {117, 5, 2},
190                 {117, 5, 2} },
191         {84750000,
192                 {118, 5, 2},
193                 {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
194                 {118, 5, 2},
195                 {118, 5, 2} },
196         {85860000,
197                 {84, 7, 1},
198                 {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
199                 {120, 5, 2},
200                 {118, 5, 2} },
201         {88750000,
202                 {31, 5, 0},
203                 {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
204                 {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
205                 {124, 5, 2} },
206         {94500000,
207                 {33, 5, 0},
208                 {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
209                 {132, 5, 2},
210                 {132, 5, 2} },
211         {97750000,
212                 {82, 6, 1},
213                 {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
214                 {137, 5, 2},
215                 {137, 5, 2} },
216         {101000000,
217                 {127, 9, 1},
218                 {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
219                 {141, 5, 2},
220                 {141, 5, 2} },
221         {106500000,
222                 {119, 4, 2},
223                 {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
224                 {119, 4, 2},
225                 {149, 5, 2} },
226         {108000000,
227                 {121, 4, 2},
228                 {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
229                 {151, 5, 2},
230                 {151, 5, 2} },
231         {113309000,
232                 {95, 12, 0},
233                 {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
234                 {95, 3, 2},
235                 {159, 5, 2} },
236         {118840000,
237                 {83, 5, 1},
238                 {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
239                 {166, 5, 2},
240                 {166, 5, 2} },
241         {119000000,
242                 {108, 13, 0},
243                 {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
244                 {133, 4, 2},
245                 {167, 5, 2} },
246         {121750000,
247                 {85, 5, 1},
248                 {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
249                 {68, 2, 2},
250                 {0, 0, 0} },
251         {125104000,
252                 {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
253                 {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
254                 {175, 5, 2},
255                 {0, 0, 0} },
256         {135000000,
257                 {94, 5, 1},
258                 {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
259                 {151, 4, 2},
260                 {189, 5, 2} },
261         {136700000,
262                 {115, 12, 0},
263                 {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
264                 {191, 5, 2},
265                 {191, 5, 2} },
266         {138400000,
267                 {87, 9, 0},
268                 {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
269                 {116, 3, 2},
270                 {194, 5, 2} },
271         {146760000,
272                 {103, 5, 1},
273                 {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
274                 {206, 5, 2},
275                 {206, 5, 2} },
276         {153920000,
277                 {86, 8, 0},
278                 {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
279                 {86, 4, 1},
280                 {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
281         {156000000,
282                 {109, 5, 1},
283                 {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
284                 {109, 5, 1},
285                 {108, 5, 1} },
286         {157500000,
287                 {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
288                 {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
289                 {110, 5, 1},
290                 {110, 5, 1} },
291         {162000000,
292                 {113, 5, 1},
293                 {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
294                 {113, 5, 1},
295                 {113, 5, 1} },
296         {187000000,
297                 {118, 9, 0},
298                 {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
299                 {131, 5, 1},
300                 {131, 5, 1} },
301         {193295000,
302                 {108, 8, 0},
303                 {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
304                 {135, 5, 1},
305                 {135, 5, 1} },
306         {202500000,
307                 {99, 7, 0},
308                 {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
309                 {142, 5, 1},
310                 {142, 5, 1} },
311         {204000000,
312                 {100, 7, 0},
313                 {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
314                 {143, 5, 1},
315                 {143, 5, 1} },
316         {218500000,
317                 {92, 6, 0},
318                 {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
319                 {153, 5, 1},
320                 {153, 5, 1} },
321         {234000000,
322                 {98, 6, 0},
323                 {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
324                 {98, 3, 1},
325                 {164, 5, 1} },
326         {267250000,
327                 {112, 6, 0},
328                 {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
329                 {187, 5, 1},
330                 {187, 5, 1} },
331         {297500000,
332                 {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
333                 {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
334                 {208, 5, 1},
335                 {208, 5, 1} },
336         {74481000,
337                 {26, 5, 0},
338                 {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
339                 {208, 5, 3},
340                 {209, 5, 3} },
341         {172798000,
342                 {121, 5, 1},
343                 {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
344                 {121, 5, 1},
345                 {121, 5, 1} },
346         {122614000,
347                 {60, 7, 0},
348                 {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
349                 {137, 4, 2},
350                 {172, 5, 2} },
351         {74270000,
352                 {83, 8, 1},
353                 {208, 5, 3},
354                 {208, 5, 3},
355                 {0, 0, 0} },
356         {148500000,
357                 {83, 8, 0},
358                 {208, 5, 2},
359                 {166, 4, 2},
360                 {208, 5, 2} }
361 };
362
363 static struct fifo_depth_select display_fifo_depth_reg = {
364         /* IGA1 FIFO Depth_Select */
365         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
366         /* IGA2 FIFO Depth_Select */
367         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
368          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
369 };
370
371 static struct fifo_threshold_select fifo_threshold_select_reg = {
372         /* IGA1 FIFO Threshold Select */
373         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
374         /* IGA2 FIFO Threshold Select */
375         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
376 };
377
378 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
379         /* IGA1 FIFO High Threshold Select */
380         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
381         /* IGA2 FIFO High Threshold Select */
382         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
383 };
384
385 static struct display_queue_expire_num display_queue_expire_num_reg = {
386         /* IGA1 Display Queue Expire Num */
387         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
388         /* IGA2 Display Queue Expire Num */
389         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
390 };
391
392 /* Definition Fetch Count Registers*/
393 static struct fetch_count fetch_count_reg = {
394         /* IGA1 Fetch Count Register */
395         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
396         /* IGA2 Fetch Count Register */
397         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
398 };
399
400 static struct iga1_crtc_timing iga1_crtc_reg = {
401         /* IGA1 Horizontal Total */
402         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
403         /* IGA1 Horizontal Addressable Video */
404         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
405         /* IGA1 Horizontal Blank Start */
406         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
407         /* IGA1 Horizontal Blank End */
408         {IGA1_HOR_BLANK_END_REG_NUM,
409          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
410         /* IGA1 Horizontal Sync Start */
411         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
412         /* IGA1 Horizontal Sync End */
413         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
414         /* IGA1 Vertical Total */
415         {IGA1_VER_TOTAL_REG_NUM,
416          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
417         /* IGA1 Vertical Addressable Video */
418         {IGA1_VER_ADDR_REG_NUM,
419          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
420         /* IGA1 Vertical Blank Start */
421         {IGA1_VER_BLANK_START_REG_NUM,
422          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
423         /* IGA1 Vertical Blank End */
424         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
425         /* IGA1 Vertical Sync Start */
426         {IGA1_VER_SYNC_START_REG_NUM,
427          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
428         /* IGA1 Vertical Sync End */
429         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
430 };
431
432 static struct iga2_crtc_timing iga2_crtc_reg = {
433         /* IGA2 Horizontal Total */
434         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
435         /* IGA2 Horizontal Addressable Video */
436         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
437         /* IGA2 Horizontal Blank Start */
438         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
439         /* IGA2 Horizontal Blank End */
440         {IGA2_HOR_BLANK_END_REG_NUM,
441          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
442         /* IGA2 Horizontal Sync Start */
443         {IGA2_HOR_SYNC_START_REG_NUM,
444          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
445         /* IGA2 Horizontal Sync End */
446         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
447         /* IGA2 Vertical Total */
448         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
449         /* IGA2 Vertical Addressable Video */
450         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
451         /* IGA2 Vertical Blank Start */
452         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
453         /* IGA2 Vertical Blank End */
454         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
455         /* IGA2 Vertical Sync Start */
456         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
457         /* IGA2 Vertical Sync End */
458         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
459 };
460
461 static struct rgbLUT palLUT_table[] = {
462         /* {R,G,B} */
463         /* Index 0x00~0x03 */
464         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
465                                                                      0x2A,
466                                                                      0x2A},
467         /* Index 0x04~0x07 */
468         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
469                                                                      0x2A,
470                                                                      0x2A},
471         /* Index 0x08~0x0B */
472         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
473                                                                      0x3F,
474                                                                      0x3F},
475         /* Index 0x0C~0x0F */
476         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
477                                                                      0x3F,
478                                                                      0x3F},
479         /* Index 0x10~0x13 */
480         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
481                                                                      0x0B,
482                                                                      0x0B},
483         /* Index 0x14~0x17 */
484         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
485                                                                      0x18,
486                                                                      0x18},
487         /* Index 0x18~0x1B */
488         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
489                                                                      0x28,
490                                                                      0x28},
491         /* Index 0x1C~0x1F */
492         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
493                                                                      0x3F,
494                                                                      0x3F},
495         /* Index 0x20~0x23 */
496         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
497                                                                      0x00,
498                                                                      0x3F},
499         /* Index 0x24~0x27 */
500         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
501                                                                      0x00,
502                                                                      0x10},
503         /* Index 0x28~0x2B */
504         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
505                                                                      0x2F,
506                                                                      0x00},
507         /* Index 0x2C~0x2F */
508         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
509                                                                      0x3F,
510                                                                      0x00},
511         /* Index 0x30~0x33 */
512         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
513                                                                      0x3F,
514                                                                      0x2F},
515         /* Index 0x34~0x37 */
516         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
517                                                                      0x10,
518                                                                      0x3F},
519         /* Index 0x38~0x3B */
520         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
521                                                                      0x1F,
522                                                                      0x3F},
523         /* Index 0x3C~0x3F */
524         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
525                                                                      0x1F,
526                                                                      0x27},
527         /* Index 0x40~0x43 */
528         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
529                                                                      0x3F,
530                                                                      0x1F},
531         /* Index 0x44~0x47 */
532         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
533                                                                      0x3F,
534                                                                      0x1F},
535         /* Index 0x48~0x4B */
536         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
537                                                                      0x3F,
538                                                                      0x37},
539         /* Index 0x4C~0x4F */
540         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
541                                                                      0x27,
542                                                                      0x3F},
543         /* Index 0x50~0x53 */
544         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
545                                                                      0x2D,
546                                                                      0x3F},
547         /* Index 0x54~0x57 */
548         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
549                                                                      0x2D,
550                                                                      0x31},
551         /* Index 0x58~0x5B */
552         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
553                                                                      0x3A,
554                                                                      0x2D},
555         /* Index 0x5C~0x5F */
556         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
557                                                                      0x3F,
558                                                                      0x2D},
559         /* Index 0x60~0x63 */
560         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
561                                                                      0x3F,
562                                                                      0x3A},
563         /* Index 0x64~0x67 */
564         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
565                                                                      0x31,
566                                                                      0x3F},
567         /* Index 0x68~0x6B */
568         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
569                                                                      0x00,
570                                                                      0x1C},
571         /* Index 0x6C~0x6F */
572         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
573                                                                      0x00,
574                                                                      0x07},
575         /* Index 0x70~0x73 */
576         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
577                                                                      0x15,
578                                                                      0x00},
579         /* Index 0x74~0x77 */
580         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
581                                                                      0x1C,
582                                                                      0x00},
583         /* Index 0x78~0x7B */
584         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
585                                                                      0x1C,
586                                                                      0x15},
587         /* Index 0x7C~0x7F */
588         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
589                                                                      0x07,
590                                                                      0x1C},
591         /* Index 0x80~0x83 */
592         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
593                                                                      0x0E,
594                                                                      0x1C},
595         /* Index 0x84~0x87 */
596         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
597                                                                      0x0E,
598                                                                      0x11},
599         /* Index 0x88~0x8B */
600         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
601                                                                      0x18,
602                                                                      0x0E},
603         /* Index 0x8C~0x8F */
604         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
605                                                                      0x1C,
606                                                                      0x0E},
607         /* Index 0x90~0x93 */
608         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
609                                                                      0x1C,
610                                                                      0x18},
611         /* Index 0x94~0x97 */
612         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
613                                                                      0x11,
614                                                                      0x1C},
615         /* Index 0x98~0x9B */
616         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
617                                                                      0x14,
618                                                                      0x1C},
619         /* Index 0x9C~0x9F */
620         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
621                                                                      0x14,
622                                                                      0x16},
623         /* Index 0xA0~0xA3 */
624         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
625                                                                      0x1A,
626                                                                      0x14},
627         /* Index 0xA4~0xA7 */
628         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
629                                                                      0x1C,
630                                                                      0x14},
631         /* Index 0xA8~0xAB */
632         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
633                                                                      0x1C,
634                                                                      0x1A},
635         /* Index 0xAC~0xAF */
636         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
637                                                                      0x16,
638                                                                      0x1C},
639         /* Index 0xB0~0xB3 */
640         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
641                                                                      0x00,
642                                                                      0x10},
643         /* Index 0xB4~0xB7 */
644         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
645                                                                      0x00,
646                                                                      0x04},
647         /* Index 0xB8~0xBB */
648         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
649                                                                      0x0C,
650                                                                      0x00},
651         /* Index 0xBC~0xBF */
652         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
653                                                                      0x10,
654                                                                      0x00},
655         /* Index 0xC0~0xC3 */
656         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
657                                                                      0x10,
658                                                                      0x0C},
659         /* Index 0xC4~0xC7 */
660         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
661                                                                      0x04,
662                                                                      0x10},
663         /* Index 0xC8~0xCB */
664         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
665                                                                      0x08,
666                                                                      0x10},
667         /* Index 0xCC~0xCF */
668         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
669                                                                      0x08,
670                                                                      0x0A},
671         /* Index 0xD0~0xD3 */
672         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
673                                                                      0x0E,
674                                                                      0x08},
675         /* Index 0xD4~0xD7 */
676         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
677                                                                      0x10,
678                                                                      0x08},
679         /* Index 0xD8~0xDB */
680         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
681                                                                      0x10,
682                                                                      0x0E},
683         /* Index 0xDC~0xDF */
684         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
685                                                                      0x0A,
686                                                                      0x10},
687         /* Index 0xE0~0xE3 */
688         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
689                                                                      0x0B,
690                                                                      0x10},
691         /* Index 0xE4~0xE7 */
692         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
693                                                                      0x0B,
694                                                                      0x0C},
695         /* Index 0xE8~0xEB */
696         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
697                                                                      0x0F,
698                                                                      0x0B},
699         /* Index 0xEC~0xEF */
700         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
701                                                                      0x10,
702                                                                      0x0B},
703         /* Index 0xF0~0xF3 */
704         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
705                                                                      0x10,
706                                                                      0x0F},
707         /* Index 0xF4~0xF7 */
708         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
709                                                                      0x0C,
710                                                                      0x10},
711         /* Index 0xF8~0xFB */
712         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
713                                                                      0x00,
714                                                                      0x00},
715         /* Index 0xFC~0xFF */
716         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
717                                                                      0x00,
718                                                                      0x00}
719 };
720
721 static void set_crt_output_path(int set_iga);
722 static void dvi_patch_skew_dvp0(void);
723 static void dvi_patch_skew_dvp_low(void);
724 static void set_dvi_output_path(int set_iga, int output_interface);
725 static void set_lcd_output_path(int set_iga, int output_interface);
726 static void load_fix_bit_crtc_reg(void);
727 static void init_gfx_chip_info(int chip_type);
728 static void init_tmds_chip_info(void);
729 static void init_lvds_chip_info(void);
730 static void device_screen_off(void);
731 static void device_screen_on(void);
732 static void set_display_channel(void);
733 static void device_off(void);
734 static void device_on(void);
735 static void enable_second_display_channel(void);
736
737 void viafb_lock_crt(void)
738 {
739         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
740 }
741
742 void viafb_unlock_crt(void)
743 {
744         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
745         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
746 }
747
748 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
749 {
750         outb(index, LUT_INDEX_WRITE);
751         outb(r, LUT_DATA);
752         outb(g, LUT_DATA);
753         outb(b, LUT_DATA);
754 }
755
756 /*Set IGA path for each device*/
757 void viafb_set_iga_path(void)
758 {
759
760         if (viafb_SAMM_ON == 1) {
761                 if (viafb_CRT_ON) {
762                         if (viafb_primary_dev == CRT_Device)
763                                 viaparinfo->crt_setting_info->iga_path = IGA1;
764                         else
765                                 viaparinfo->crt_setting_info->iga_path = IGA2;
766                 }
767
768                 if (viafb_DVI_ON) {
769                         if (viafb_primary_dev == DVI_Device)
770                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
771                         else
772                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
773                 }
774
775                 if (viafb_LCD_ON) {
776                         if (viafb_primary_dev == LCD_Device) {
777                                 if (viafb_dual_fb &&
778                                         (viaparinfo->chip_info->gfx_chip_name ==
779                                         UNICHROME_CLE266)) {
780                                         viaparinfo->
781                                         lvds_setting_info->iga_path = IGA2;
782                                         viaparinfo->
783                                         crt_setting_info->iga_path = IGA1;
784                                         viaparinfo->
785                                         tmds_setting_info->iga_path = IGA1;
786                                 } else
787                                         viaparinfo->
788                                         lvds_setting_info->iga_path = IGA1;
789                         } else {
790                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
791                         }
792                 }
793                 if (viafb_LCD2_ON) {
794                         if (LCD2_Device == viafb_primary_dev)
795                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
796                         else
797                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
798                 }
799         } else {
800                 viafb_SAMM_ON = 0;
801
802                 if (viafb_CRT_ON && viafb_LCD_ON) {
803                         viaparinfo->crt_setting_info->iga_path = IGA1;
804                         viaparinfo->lvds_setting_info->iga_path = IGA2;
805                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
806                         viaparinfo->crt_setting_info->iga_path = IGA1;
807                         viaparinfo->tmds_setting_info->iga_path = IGA2;
808                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
809                         viaparinfo->tmds_setting_info->iga_path = IGA1;
810                         viaparinfo->lvds_setting_info->iga_path = IGA2;
811                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
812                         viaparinfo->lvds_setting_info->iga_path = IGA2;
813                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
814                 } else if (viafb_CRT_ON) {
815                         viaparinfo->crt_setting_info->iga_path = IGA1;
816                 } else if (viafb_LCD_ON) {
817                         viaparinfo->lvds_setting_info->iga_path = IGA2;
818                 } else if (viafb_DVI_ON) {
819                         viaparinfo->tmds_setting_info->iga_path = IGA1;
820                 }
821         }
822 }
823
824 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
825 {
826         outb(0xFF, 0x3C6); /* bit mask of palette */
827         outb(index, 0x3C8);
828         outb(red, 0x3C9);
829         outb(green, 0x3C9);
830         outb(blue, 0x3C9);
831 }
832
833 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
834 {
835         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
836         set_color_register(index, red, green, blue);
837 }
838
839 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
840 {
841         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
842         set_color_register(index, red, green, blue);
843 }
844
845 void viafb_set_output_path(int device, int set_iga, int output_interface)
846 {
847         switch (device) {
848         case DEVICE_CRT:
849                 set_crt_output_path(set_iga);
850                 break;
851         case DEVICE_DVI:
852                 set_dvi_output_path(set_iga, output_interface);
853                 break;
854         case DEVICE_LCD:
855                 set_lcd_output_path(set_iga, output_interface);
856                 break;
857         }
858
859         if (set_iga == IGA2)
860                 enable_second_display_channel();
861 }
862
863 static void set_crt_output_path(int set_iga)
864 {
865         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
866
867         switch (set_iga) {
868         case IGA1:
869                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
870                 break;
871         case IGA2:
872                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
873                 break;
874         }
875 }
876
877 static void dvi_patch_skew_dvp0(void)
878 {
879         /* Reset data driving first: */
880         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
881         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
882
883         switch (viaparinfo->chip_info->gfx_chip_name) {
884         case UNICHROME_P4M890:
885                 {
886                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
887                                 (viaparinfo->tmds_setting_info->v_active ==
888                                 1200))
889                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
890                                                BIT0 + BIT1 + BIT2);
891                         else
892                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
893                                                BIT0 + BIT1 + BIT2);
894                         break;
895                 }
896
897         case UNICHROME_P4M900:
898                 {
899                         viafb_write_reg_mask(CR96, VIACR, 0x07,
900                                        BIT0 + BIT1 + BIT2 + BIT3);
901                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
902                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
903                         break;
904                 }
905
906         default:
907                 {
908                         break;
909                 }
910         }
911 }
912
913 static void dvi_patch_skew_dvp_low(void)
914 {
915         switch (viaparinfo->chip_info->gfx_chip_name) {
916         case UNICHROME_K8M890:
917                 {
918                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
919                         break;
920                 }
921
922         case UNICHROME_P4M900:
923                 {
924                         viafb_write_reg_mask(CR99, VIACR, 0x08,
925                                        BIT0 + BIT1 + BIT2 + BIT3);
926                         break;
927                 }
928
929         case UNICHROME_P4M890:
930                 {
931                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
932                                        BIT0 + BIT1 + BIT2 + BIT3);
933                         break;
934                 }
935
936         default:
937                 {
938                         break;
939                 }
940         }
941 }
942
943 static void set_dvi_output_path(int set_iga, int output_interface)
944 {
945         switch (output_interface) {
946         case INTERFACE_DVP0:
947                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
948
949                 if (set_iga == IGA1) {
950                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
951                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
952                                 BIT5 + BIT7);
953                 } else {
954                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
955                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
956                                 BIT5 + BIT7);
957                 }
958
959                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
960
961                 dvi_patch_skew_dvp0();
962                 break;
963
964         case INTERFACE_DVP1:
965                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
966                         if (set_iga == IGA1)
967                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
968                                                BIT0 + BIT5 + BIT7);
969                         else
970                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
971                                                BIT0 + BIT5 + BIT7);
972                 } else {
973                         if (set_iga == IGA1)
974                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
975                         else
976                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
977                 }
978
979                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
980                 break;
981         case INTERFACE_DFP_HIGH:
982                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
983                         if (set_iga == IGA1) {
984                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
985                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
986                                                BIT0 + BIT1 + BIT4);
987                         } else {
988                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
989                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
990                                                BIT0 + BIT1 + BIT4);
991                         }
992                 }
993                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
994                 break;
995
996         case INTERFACE_DFP_LOW:
997                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
998                         break;
999
1000                 if (set_iga == IGA1) {
1001                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1002                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
1003                 } else {
1004                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1005                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1006                 }
1007
1008                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
1009                 dvi_patch_skew_dvp_low();
1010                 break;
1011
1012         case INTERFACE_TMDS:
1013                 if (set_iga == IGA1)
1014                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1015                 else
1016                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1017                 break;
1018         }
1019
1020         if (set_iga == IGA2) {
1021                 /* Disable LCD Scaling */
1022                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
1023         }
1024 }
1025
1026 static void set_lcd_output_path(int set_iga, int output_interface)
1027 {
1028         DEBUG_MSG(KERN_INFO
1029                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
1030                   set_iga, output_interface);
1031
1032         viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1033         viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1034
1035         switch (output_interface) {
1036         case INTERFACE_DVP0:
1037                 if (set_iga == IGA1) {
1038                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
1039                 } else {
1040                         viafb_write_reg(CR91, VIACR, 0x00);
1041                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1042                 }
1043                 break;
1044
1045         case INTERFACE_DVP1:
1046                 if (set_iga == IGA1)
1047                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
1048                 else {
1049                         viafb_write_reg(CR91, VIACR, 0x00);
1050                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1051                 }
1052                 break;
1053
1054         case INTERFACE_DFP_HIGH:
1055                 if (set_iga == IGA1)
1056                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1057                 else {
1058                         viafb_write_reg(CR91, VIACR, 0x00);
1059                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1060                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1061                 }
1062                 break;
1063
1064         case INTERFACE_DFP_LOW:
1065                 if (set_iga == IGA1)
1066                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1067                 else {
1068                         viafb_write_reg(CR91, VIACR, 0x00);
1069                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1070                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1071                 }
1072
1073                 break;
1074
1075         case INTERFACE_DFP:
1076                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1077                     || (UNICHROME_P4M890 ==
1078                     viaparinfo->chip_info->gfx_chip_name))
1079                         viafb_write_reg_mask(CR97, VIACR, 0x84,
1080                                        BIT7 + BIT2 + BIT1 + BIT0);
1081                 if (set_iga == IGA1) {
1082                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1083                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1084                 } else {
1085                         viafb_write_reg(CR91, VIACR, 0x00);
1086                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1087                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1088                 }
1089                 break;
1090
1091         case INTERFACE_LVDS0:
1092         case INTERFACE_LVDS0LVDS1:
1093                 if (set_iga == IGA1)
1094                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1095                 else
1096                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1097
1098                 break;
1099
1100         case INTERFACE_LVDS1:
1101                 if (set_iga == IGA1)
1102                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1103                 else
1104                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1105                 break;
1106         }
1107 }
1108
1109 static void load_fix_bit_crtc_reg(void)
1110 {
1111         /* always set to 1 */
1112         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1113         /* line compare should set all bits = 1 (extend modes) */
1114         viafb_write_reg(CR18, VIACR, 0xff);
1115         /* line compare should set all bits = 1 (extend modes) */
1116         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1117         /* line compare should set all bits = 1 (extend modes) */
1118         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1119         /* line compare should set all bits = 1 (extend modes) */
1120         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1121         /* line compare should set all bits = 1 (extend modes) */
1122         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1123         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1124         /* extend mode always set to e3h */
1125         viafb_write_reg(CR17, VIACR, 0xe3);
1126         /* extend mode always set to 0h */
1127         viafb_write_reg(CR08, VIACR, 0x00);
1128         /* extend mode always set to 0h */
1129         viafb_write_reg(CR14, VIACR, 0x00);
1130
1131         /* If K8M800, enable Prefetch Mode. */
1132         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1133                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1134                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1135         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1136             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1137                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1138
1139 }
1140
1141 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1142         struct io_register *reg,
1143               int io_type)
1144 {
1145         int reg_mask;
1146         int bit_num = 0;
1147         int data;
1148         int i, j;
1149         int shift_next_reg;
1150         int start_index, end_index, cr_index;
1151         u16 get_bit;
1152
1153         for (i = 0; i < viafb_load_reg_num; i++) {
1154                 reg_mask = 0;
1155                 data = 0;
1156                 start_index = reg[i].start_bit;
1157                 end_index = reg[i].end_bit;
1158                 cr_index = reg[i].io_addr;
1159
1160                 shift_next_reg = bit_num;
1161                 for (j = start_index; j <= end_index; j++) {
1162                         /*if (bit_num==8) timing_value = timing_value >>8; */
1163                         reg_mask = reg_mask | (BIT0 << j);
1164                         get_bit = (timing_value & (BIT0 << bit_num));
1165                         data =
1166                             data | ((get_bit >> shift_next_reg) << start_index);
1167                         bit_num++;
1168                 }
1169                 if (io_type == VIACR)
1170                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1171                 else
1172                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1173         }
1174
1175 }
1176
1177 /* Write Registers */
1178 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1179 {
1180         int i;
1181
1182         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1183
1184         for (i = 0; i < ItemNum; i++)
1185                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1186                         RegTable[i].value, RegTable[i].mask);
1187 }
1188
1189 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1190 {
1191         int reg_value;
1192         int viafb_load_reg_num;
1193         struct io_register *reg = NULL;
1194
1195         switch (set_iga) {
1196         case IGA1:
1197                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1198                 viafb_load_reg_num = fetch_count_reg.
1199                         iga1_fetch_count_reg.reg_num;
1200                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1201                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1202                 break;
1203         case IGA2:
1204                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1205                 viafb_load_reg_num = fetch_count_reg.
1206                         iga2_fetch_count_reg.reg_num;
1207                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1208                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1209                 break;
1210         }
1211
1212 }
1213
1214 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1215 {
1216         int reg_value;
1217         int viafb_load_reg_num;
1218         struct io_register *reg = NULL;
1219         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1220             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1221         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1222             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1223
1224         if (set_iga == IGA1) {
1225                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1226                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1227                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1228                         iga1_fifo_high_threshold =
1229                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1230                         /* If resolution > 1280x1024, expire length = 64, else
1231                            expire length = 128 */
1232                         if ((hor_active > 1280) && (ver_active > 1024))
1233                                 iga1_display_queue_expire_num = 16;
1234                         else
1235                                 iga1_display_queue_expire_num =
1236                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1237
1238                 }
1239
1240                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1241                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1242                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1243                         iga1_fifo_high_threshold =
1244                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1245                         iga1_display_queue_expire_num =
1246                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1247
1248                         /* If resolution > 1280x1024, expire length = 64, else
1249                            expire length = 128 */
1250                         if ((hor_active > 1280) && (ver_active > 1024))
1251                                 iga1_display_queue_expire_num = 16;
1252                         else
1253                                 iga1_display_queue_expire_num =
1254                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1255                 }
1256
1257                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1258                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1259                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1260                         iga1_fifo_high_threshold =
1261                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1262
1263                         /* If resolution > 1280x1024, expire length = 64,
1264                            else expire length = 128 */
1265                         if ((hor_active > 1280) && (ver_active > 1024))
1266                                 iga1_display_queue_expire_num = 16;
1267                         else
1268                                 iga1_display_queue_expire_num =
1269                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1270                 }
1271
1272                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1273                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1274                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1275                         iga1_fifo_high_threshold =
1276                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1277                         iga1_display_queue_expire_num =
1278                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1279                 }
1280
1281                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1282                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1283                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1284                         iga1_fifo_high_threshold =
1285                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1286                         iga1_display_queue_expire_num =
1287                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1288                 }
1289
1290                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1291                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1292                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1293                         iga1_fifo_high_threshold =
1294                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1295                         iga1_display_queue_expire_num =
1296                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1297                 }
1298
1299                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1300                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1301                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1302                         iga1_fifo_high_threshold =
1303                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1304                         iga1_display_queue_expire_num =
1305                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1306                 }
1307
1308                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1309                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1310                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1311                         iga1_fifo_high_threshold =
1312                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1313                         iga1_display_queue_expire_num =
1314                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1315                 }
1316
1317                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1318                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1319                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1320                         iga1_fifo_high_threshold =
1321                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1322                         iga1_display_queue_expire_num =
1323                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1324                 }
1325
1326                 /* Set Display FIFO Depath Select */
1327                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1328                 viafb_load_reg_num =
1329                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1330                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1331                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1332
1333                 /* Set Display FIFO Threshold Select */
1334                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1335                 viafb_load_reg_num =
1336                     fifo_threshold_select_reg.
1337                     iga1_fifo_threshold_select_reg.reg_num;
1338                 reg =
1339                     fifo_threshold_select_reg.
1340                     iga1_fifo_threshold_select_reg.reg;
1341                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1342
1343                 /* Set FIFO High Threshold Select */
1344                 reg_value =
1345                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1346                 viafb_load_reg_num =
1347                     fifo_high_threshold_select_reg.
1348                     iga1_fifo_high_threshold_select_reg.reg_num;
1349                 reg =
1350                     fifo_high_threshold_select_reg.
1351                     iga1_fifo_high_threshold_select_reg.reg;
1352                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1353
1354                 /* Set Display Queue Expire Num */
1355                 reg_value =
1356                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1357                     (iga1_display_queue_expire_num);
1358                 viafb_load_reg_num =
1359                     display_queue_expire_num_reg.
1360                     iga1_display_queue_expire_num_reg.reg_num;
1361                 reg =
1362                     display_queue_expire_num_reg.
1363                     iga1_display_queue_expire_num_reg.reg;
1364                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1365
1366         } else {
1367                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1368                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1369                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1370                         iga2_fifo_high_threshold =
1371                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1372
1373                         /* If resolution > 1280x1024, expire length = 64,
1374                            else  expire length = 128 */
1375                         if ((hor_active > 1280) && (ver_active > 1024))
1376                                 iga2_display_queue_expire_num = 16;
1377                         else
1378                                 iga2_display_queue_expire_num =
1379                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1380                 }
1381
1382                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1383                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1384                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1385                         iga2_fifo_high_threshold =
1386                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1387
1388                         /* If resolution > 1280x1024, expire length = 64,
1389                            else  expire length = 128 */
1390                         if ((hor_active > 1280) && (ver_active > 1024))
1391                                 iga2_display_queue_expire_num = 16;
1392                         else
1393                                 iga2_display_queue_expire_num =
1394                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1395                 }
1396
1397                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1398                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1399                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1400                         iga2_fifo_high_threshold =
1401                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1402
1403                         /* If resolution > 1280x1024, expire length = 64,
1404                            else expire length = 128 */
1405                         if ((hor_active > 1280) && (ver_active > 1024))
1406                                 iga2_display_queue_expire_num = 16;
1407                         else
1408                                 iga2_display_queue_expire_num =
1409                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1410                 }
1411
1412                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1413                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1414                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1415                         iga2_fifo_high_threshold =
1416                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1417                         iga2_display_queue_expire_num =
1418                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1419                 }
1420
1421                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1422                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1423                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1424                         iga2_fifo_high_threshold =
1425                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1426                         iga2_display_queue_expire_num =
1427                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1428                 }
1429
1430                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1431                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1432                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1433                         iga2_fifo_high_threshold =
1434                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1435                         iga2_display_queue_expire_num =
1436                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1437                 }
1438
1439                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1440                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1441                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1442                         iga2_fifo_high_threshold =
1443                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1444                         iga2_display_queue_expire_num =
1445                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1446                 }
1447
1448                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1449                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1450                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1451                         iga2_fifo_high_threshold =
1452                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1453                         iga2_display_queue_expire_num =
1454                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1455                 }
1456
1457                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1458                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1459                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1460                         iga2_fifo_high_threshold =
1461                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1462                         iga2_display_queue_expire_num =
1463                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1464                 }
1465
1466                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1467                         /* Set Display FIFO Depath Select */
1468                         reg_value =
1469                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1470                             - 1;
1471                         /* Patch LCD in IGA2 case */
1472                         viafb_load_reg_num =
1473                             display_fifo_depth_reg.
1474                             iga2_fifo_depth_select_reg.reg_num;
1475                         reg =
1476                             display_fifo_depth_reg.
1477                             iga2_fifo_depth_select_reg.reg;
1478                         viafb_load_reg(reg_value,
1479                                 viafb_load_reg_num, reg, VIACR);
1480                 } else {
1481
1482                         /* Set Display FIFO Depath Select */
1483                         reg_value =
1484                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1485                         viafb_load_reg_num =
1486                             display_fifo_depth_reg.
1487                             iga2_fifo_depth_select_reg.reg_num;
1488                         reg =
1489                             display_fifo_depth_reg.
1490                             iga2_fifo_depth_select_reg.reg;
1491                         viafb_load_reg(reg_value,
1492                                 viafb_load_reg_num, reg, VIACR);
1493                 }
1494
1495                 /* Set Display FIFO Threshold Select */
1496                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1497                 viafb_load_reg_num =
1498                     fifo_threshold_select_reg.
1499                     iga2_fifo_threshold_select_reg.reg_num;
1500                 reg =
1501                     fifo_threshold_select_reg.
1502                     iga2_fifo_threshold_select_reg.reg;
1503                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1504
1505                 /* Set FIFO High Threshold Select */
1506                 reg_value =
1507                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1508                 viafb_load_reg_num =
1509                     fifo_high_threshold_select_reg.
1510                     iga2_fifo_high_threshold_select_reg.reg_num;
1511                 reg =
1512                     fifo_high_threshold_select_reg.
1513                     iga2_fifo_high_threshold_select_reg.reg;
1514                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1515
1516                 /* Set Display Queue Expire Num */
1517                 reg_value =
1518                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1519                     (iga2_display_queue_expire_num);
1520                 viafb_load_reg_num =
1521                     display_queue_expire_num_reg.
1522                     iga2_display_queue_expire_num_reg.reg_num;
1523                 reg =
1524                     display_queue_expire_num_reg.
1525                     iga2_display_queue_expire_num_reg.reg;
1526                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1527
1528         }
1529
1530 }
1531
1532 static u32 cle266_encode_pll(struct pll_config pll)
1533 {
1534         return (pll.multiplier << 8)
1535                 | (pll.rshift << 6)
1536                 | pll.divisor;
1537 }
1538
1539 static u32 k800_encode_pll(struct pll_config pll)
1540 {
1541         return ((pll.divisor - 2) << 16)
1542                 | (pll.rshift << 10)
1543                 | (pll.multiplier - 2);
1544 }
1545
1546 static u32 vx855_encode_pll(struct pll_config pll)
1547 {
1548         return (pll.divisor << 16)
1549                 | (pll.rshift << 10)
1550                 | pll.multiplier;
1551 }
1552
1553 u32 viafb_get_clk_value(int clk)
1554 {
1555         u32 value = 0;
1556         int i = 0;
1557
1558         while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1559                 i++;
1560
1561         if (i == NUM_TOTAL_PLL_TABLE) {
1562                 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1563         } else {
1564                 switch (viaparinfo->chip_info->gfx_chip_name) {
1565                 case UNICHROME_CLE266:
1566                 case UNICHROME_K400:
1567                         value = cle266_encode_pll(pll_value[i].cle266_pll);
1568                         break;
1569
1570                 case UNICHROME_K800:
1571                 case UNICHROME_PM800:
1572                 case UNICHROME_CN700:
1573                         value = k800_encode_pll(pll_value[i].k800_pll);
1574                         break;
1575
1576                 case UNICHROME_CX700:
1577                 case UNICHROME_CN750:
1578                 case UNICHROME_K8M890:
1579                 case UNICHROME_P4M890:
1580                 case UNICHROME_P4M900:
1581                 case UNICHROME_VX800:
1582                         value = k800_encode_pll(pll_value[i].cx700_pll);
1583                         break;
1584
1585                 case UNICHROME_VX855:
1586                         value = vx855_encode_pll(pll_value[i].vx855_pll);
1587                         break;
1588                 }
1589         }
1590
1591         return value;
1592 }
1593
1594 /* Set VCLK*/
1595 void viafb_set_vclock(u32 clk, int set_iga)
1596 {
1597         /* H.W. Reset : ON */
1598         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1599
1600         if (set_iga == IGA1) {
1601                 /* Change D,N FOR VCLK */
1602                 switch (viaparinfo->chip_info->gfx_chip_name) {
1603                 case UNICHROME_CLE266:
1604                 case UNICHROME_K400:
1605                         via_write_reg(VIASR, SR46, (clk & 0x00FF));
1606                         via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1607                         break;
1608
1609                 case UNICHROME_K800:
1610                 case UNICHROME_PM800:
1611                 case UNICHROME_CN700:
1612                 case UNICHROME_CX700:
1613                 case UNICHROME_CN750:
1614                 case UNICHROME_K8M890:
1615                 case UNICHROME_P4M890:
1616                 case UNICHROME_P4M900:
1617                 case UNICHROME_VX800:
1618                 case UNICHROME_VX855:
1619                         via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1620                         via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1621                         via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1622                         break;
1623                 }
1624         }
1625
1626         if (set_iga == IGA2) {
1627                 /* Change D,N FOR LCK */
1628                 switch (viaparinfo->chip_info->gfx_chip_name) {
1629                 case UNICHROME_CLE266:
1630                 case UNICHROME_K400:
1631                         via_write_reg(VIASR, SR44, (clk & 0x00FF));
1632                         via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1633                         break;
1634
1635                 case UNICHROME_K800:
1636                 case UNICHROME_PM800:
1637                 case UNICHROME_CN700:
1638                 case UNICHROME_CX700:
1639                 case UNICHROME_CN750:
1640                 case UNICHROME_K8M890:
1641                 case UNICHROME_P4M890:
1642                 case UNICHROME_P4M900:
1643                 case UNICHROME_VX800:
1644                 case UNICHROME_VX855:
1645                         via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1646                         via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1647                         via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1648                         break;
1649                 }
1650         }
1651
1652         /* H.W. Reset : OFF */
1653         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1654
1655         /* Reset PLL */
1656         if (set_iga == IGA1) {
1657                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1658                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1659         }
1660
1661         if (set_iga == IGA2) {
1662                 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1663                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1664         }
1665
1666         /* Fire! */
1667         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1668 }
1669
1670 void viafb_load_crtc_timing(struct display_timing device_timing,
1671         int set_iga)
1672 {
1673         int i;
1674         int viafb_load_reg_num = 0;
1675         int reg_value = 0;
1676         struct io_register *reg = NULL;
1677
1678         viafb_unlock_crt();
1679
1680         for (i = 0; i < 12; i++) {
1681                 if (set_iga == IGA1) {
1682                         switch (i) {
1683                         case H_TOTAL_INDEX:
1684                                 reg_value =
1685                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1686                                                            hor_total);
1687                                 viafb_load_reg_num =
1688                                         iga1_crtc_reg.hor_total.reg_num;
1689                                 reg = iga1_crtc_reg.hor_total.reg;
1690                                 break;
1691                         case H_ADDR_INDEX:
1692                                 reg_value =
1693                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1694                                                           hor_addr);
1695                                 viafb_load_reg_num =
1696                                         iga1_crtc_reg.hor_addr.reg_num;
1697                                 reg = iga1_crtc_reg.hor_addr.reg;
1698                                 break;
1699                         case H_BLANK_START_INDEX:
1700                                 reg_value =
1701                                     IGA1_HOR_BLANK_START_FORMULA
1702                                     (device_timing.hor_blank_start);
1703                                 viafb_load_reg_num =
1704                                     iga1_crtc_reg.hor_blank_start.reg_num;
1705                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1706                                 break;
1707                         case H_BLANK_END_INDEX:
1708                                 reg_value =
1709                                     IGA1_HOR_BLANK_END_FORMULA
1710                                     (device_timing.hor_blank_start,
1711                                      device_timing.hor_blank_end);
1712                                 viafb_load_reg_num =
1713                                     iga1_crtc_reg.hor_blank_end.reg_num;
1714                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1715                                 break;
1716                         case H_SYNC_START_INDEX:
1717                                 reg_value =
1718                                     IGA1_HOR_SYNC_START_FORMULA
1719                                     (device_timing.hor_sync_start);
1720                                 viafb_load_reg_num =
1721                                     iga1_crtc_reg.hor_sync_start.reg_num;
1722                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1723                                 break;
1724                         case H_SYNC_END_INDEX:
1725                                 reg_value =
1726                                     IGA1_HOR_SYNC_END_FORMULA
1727                                     (device_timing.hor_sync_start,
1728                                      device_timing.hor_sync_end);
1729                                 viafb_load_reg_num =
1730                                     iga1_crtc_reg.hor_sync_end.reg_num;
1731                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1732                                 break;
1733                         case V_TOTAL_INDEX:
1734                                 reg_value =
1735                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1736                                                            ver_total);
1737                                 viafb_load_reg_num =
1738                                         iga1_crtc_reg.ver_total.reg_num;
1739                                 reg = iga1_crtc_reg.ver_total.reg;
1740                                 break;
1741                         case V_ADDR_INDEX:
1742                                 reg_value =
1743                                     IGA1_VER_ADDR_FORMULA(device_timing.
1744                                                           ver_addr);
1745                                 viafb_load_reg_num =
1746                                         iga1_crtc_reg.ver_addr.reg_num;
1747                                 reg = iga1_crtc_reg.ver_addr.reg;
1748                                 break;
1749                         case V_BLANK_START_INDEX:
1750                                 reg_value =
1751                                     IGA1_VER_BLANK_START_FORMULA
1752                                     (device_timing.ver_blank_start);
1753                                 viafb_load_reg_num =
1754                                     iga1_crtc_reg.ver_blank_start.reg_num;
1755                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1756                                 break;
1757                         case V_BLANK_END_INDEX:
1758                                 reg_value =
1759                                     IGA1_VER_BLANK_END_FORMULA
1760                                     (device_timing.ver_blank_start,
1761                                      device_timing.ver_blank_end);
1762                                 viafb_load_reg_num =
1763                                     iga1_crtc_reg.ver_blank_end.reg_num;
1764                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1765                                 break;
1766                         case V_SYNC_START_INDEX:
1767                                 reg_value =
1768                                     IGA1_VER_SYNC_START_FORMULA
1769                                     (device_timing.ver_sync_start);
1770                                 viafb_load_reg_num =
1771                                     iga1_crtc_reg.ver_sync_start.reg_num;
1772                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1773                                 break;
1774                         case V_SYNC_END_INDEX:
1775                                 reg_value =
1776                                     IGA1_VER_SYNC_END_FORMULA
1777                                     (device_timing.ver_sync_start,
1778                                      device_timing.ver_sync_end);
1779                                 viafb_load_reg_num =
1780                                     iga1_crtc_reg.ver_sync_end.reg_num;
1781                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1782                                 break;
1783
1784                         }
1785                 }
1786
1787                 if (set_iga == IGA2) {
1788                         switch (i) {
1789                         case H_TOTAL_INDEX:
1790                                 reg_value =
1791                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1792                                                            hor_total);
1793                                 viafb_load_reg_num =
1794                                         iga2_crtc_reg.hor_total.reg_num;
1795                                 reg = iga2_crtc_reg.hor_total.reg;
1796                                 break;
1797                         case H_ADDR_INDEX:
1798                                 reg_value =
1799                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1800                                                           hor_addr);
1801                                 viafb_load_reg_num =
1802                                         iga2_crtc_reg.hor_addr.reg_num;
1803                                 reg = iga2_crtc_reg.hor_addr.reg;
1804                                 break;
1805                         case H_BLANK_START_INDEX:
1806                                 reg_value =
1807                                     IGA2_HOR_BLANK_START_FORMULA
1808                                     (device_timing.hor_blank_start);
1809                                 viafb_load_reg_num =
1810                                     iga2_crtc_reg.hor_blank_start.reg_num;
1811                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1812                                 break;
1813                         case H_BLANK_END_INDEX:
1814                                 reg_value =
1815                                     IGA2_HOR_BLANK_END_FORMULA
1816                                     (device_timing.hor_blank_start,
1817                                      device_timing.hor_blank_end);
1818                                 viafb_load_reg_num =
1819                                     iga2_crtc_reg.hor_blank_end.reg_num;
1820                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1821                                 break;
1822                         case H_SYNC_START_INDEX:
1823                                 reg_value =
1824                                     IGA2_HOR_SYNC_START_FORMULA
1825                                     (device_timing.hor_sync_start);
1826                                 if (UNICHROME_CN700 <=
1827                                         viaparinfo->chip_info->gfx_chip_name)
1828                                         viafb_load_reg_num =
1829                                             iga2_crtc_reg.hor_sync_start.
1830                                             reg_num;
1831                                 else
1832                                         viafb_load_reg_num = 3;
1833                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1834                                 break;
1835                         case H_SYNC_END_INDEX:
1836                                 reg_value =
1837                                     IGA2_HOR_SYNC_END_FORMULA
1838                                     (device_timing.hor_sync_start,
1839                                      device_timing.hor_sync_end);
1840                                 viafb_load_reg_num =
1841                                     iga2_crtc_reg.hor_sync_end.reg_num;
1842                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1843                                 break;
1844                         case V_TOTAL_INDEX:
1845                                 reg_value =
1846                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1847                                                            ver_total);
1848                                 viafb_load_reg_num =
1849                                         iga2_crtc_reg.ver_total.reg_num;
1850                                 reg = iga2_crtc_reg.ver_total.reg;
1851                                 break;
1852                         case V_ADDR_INDEX:
1853                                 reg_value =
1854                                     IGA2_VER_ADDR_FORMULA(device_timing.
1855                                                           ver_addr);
1856                                 viafb_load_reg_num =
1857                                         iga2_crtc_reg.ver_addr.reg_num;
1858                                 reg = iga2_crtc_reg.ver_addr.reg;
1859                                 break;
1860                         case V_BLANK_START_INDEX:
1861                                 reg_value =
1862                                     IGA2_VER_BLANK_START_FORMULA
1863                                     (device_timing.ver_blank_start);
1864                                 viafb_load_reg_num =
1865                                     iga2_crtc_reg.ver_blank_start.reg_num;
1866                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1867                                 break;
1868                         case V_BLANK_END_INDEX:
1869                                 reg_value =
1870                                     IGA2_VER_BLANK_END_FORMULA
1871                                     (device_timing.ver_blank_start,
1872                                      device_timing.ver_blank_end);
1873                                 viafb_load_reg_num =
1874                                     iga2_crtc_reg.ver_blank_end.reg_num;
1875                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1876                                 break;
1877                         case V_SYNC_START_INDEX:
1878                                 reg_value =
1879                                     IGA2_VER_SYNC_START_FORMULA
1880                                     (device_timing.ver_sync_start);
1881                                 viafb_load_reg_num =
1882                                     iga2_crtc_reg.ver_sync_start.reg_num;
1883                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1884                                 break;
1885                         case V_SYNC_END_INDEX:
1886                                 reg_value =
1887                                     IGA2_VER_SYNC_END_FORMULA
1888                                     (device_timing.ver_sync_start,
1889                                      device_timing.ver_sync_end);
1890                                 viafb_load_reg_num =
1891                                     iga2_crtc_reg.ver_sync_end.reg_num;
1892                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1893                                 break;
1894
1895                         }
1896                 }
1897                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1898         }
1899
1900         viafb_lock_crt();
1901 }
1902
1903 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1904         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1905 {
1906         struct display_timing crt_reg;
1907         int i;
1908         int index = 0;
1909         int h_addr, v_addr;
1910         u32 pll_D_N;
1911         u8 polarity = 0;
1912
1913         for (i = 0; i < video_mode->mode_array; i++) {
1914                 index = i;
1915
1916                 if (crt_table[i].refresh_rate == viaparinfo->
1917                         crt_setting_info->refresh_rate)
1918                         break;
1919         }
1920
1921         crt_reg = crt_table[index].crtc;
1922
1923         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1924         /* So we would delete border. */
1925         if ((viafb_LCD_ON | viafb_DVI_ON)
1926             && video_mode->crtc[0].crtc.hor_addr == 640
1927             && video_mode->crtc[0].crtc.ver_addr == 480
1928             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1929                 /* The border is 8 pixels. */
1930                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1931
1932                 /* Blanking time should add left and right borders. */
1933                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1934         }
1935
1936         h_addr = crt_reg.hor_addr;
1937         v_addr = crt_reg.ver_addr;
1938
1939         /* update polarity for CRT timing */
1940         if (crt_table[index].h_sync_polarity == NEGATIVE)
1941                 polarity |= BIT6;
1942         if (crt_table[index].v_sync_polarity == NEGATIVE)
1943                 polarity |= BIT7;
1944         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1945
1946         if (set_iga == IGA1) {
1947                 viafb_unlock_crt();
1948                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1949                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1950                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1951         }
1952
1953         switch (set_iga) {
1954         case IGA1:
1955                 viafb_load_crtc_timing(crt_reg, IGA1);
1956                 break;
1957         case IGA2:
1958                 viafb_load_crtc_timing(crt_reg, IGA2);
1959                 break;
1960         }
1961
1962         load_fix_bit_crtc_reg();
1963         viafb_lock_crt();
1964         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1965         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1966
1967         /* load FIFO */
1968         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1969             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1970                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1971
1972         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1973         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1974         viafb_set_vclock(pll_D_N, set_iga);
1975
1976 }
1977
1978 void viafb_init_chip_info(int chip_type)
1979 {
1980         init_gfx_chip_info(chip_type);
1981         init_tmds_chip_info();
1982         init_lvds_chip_info();
1983
1984         viaparinfo->crt_setting_info->iga_path = IGA1;
1985         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1986
1987         /*Set IGA path for each device */
1988         viafb_set_iga_path();
1989
1990         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1991         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1992         viaparinfo->lvds_setting_info2->display_method =
1993                 viaparinfo->lvds_setting_info->display_method;
1994         viaparinfo->lvds_setting_info2->lcd_mode =
1995                 viaparinfo->lvds_setting_info->lcd_mode;
1996 }
1997
1998 void viafb_update_device_setting(int hres, int vres,
1999         int bpp, int vmode_refresh, int flag)
2000 {
2001         if (flag == 0) {
2002                 viaparinfo->crt_setting_info->h_active = hres;
2003                 viaparinfo->crt_setting_info->v_active = vres;
2004                 viaparinfo->crt_setting_info->bpp = bpp;
2005                 viaparinfo->crt_setting_info->refresh_rate =
2006                         vmode_refresh;
2007
2008                 viaparinfo->tmds_setting_info->h_active = hres;
2009                 viaparinfo->tmds_setting_info->v_active = vres;
2010
2011                 viaparinfo->lvds_setting_info->h_active = hres;
2012                 viaparinfo->lvds_setting_info->v_active = vres;
2013                 viaparinfo->lvds_setting_info->bpp = bpp;
2014                 viaparinfo->lvds_setting_info->refresh_rate =
2015                         vmode_refresh;
2016                 viaparinfo->lvds_setting_info2->h_active = hres;
2017                 viaparinfo->lvds_setting_info2->v_active = vres;
2018                 viaparinfo->lvds_setting_info2->bpp = bpp;
2019                 viaparinfo->lvds_setting_info2->refresh_rate =
2020                         vmode_refresh;
2021         } else {
2022
2023                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
2024                         viaparinfo->tmds_setting_info->h_active = hres;
2025                         viaparinfo->tmds_setting_info->v_active = vres;
2026                 }
2027
2028                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
2029                         viaparinfo->lvds_setting_info->h_active = hres;
2030                         viaparinfo->lvds_setting_info->v_active = vres;
2031                         viaparinfo->lvds_setting_info->bpp = bpp;
2032                         viaparinfo->lvds_setting_info->refresh_rate =
2033                                 vmode_refresh;
2034                 }
2035                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2036                         viaparinfo->lvds_setting_info2->h_active = hres;
2037                         viaparinfo->lvds_setting_info2->v_active = vres;
2038                         viaparinfo->lvds_setting_info2->bpp = bpp;
2039                         viaparinfo->lvds_setting_info2->refresh_rate =
2040                                 vmode_refresh;
2041                 }
2042         }
2043 }
2044
2045 static void init_gfx_chip_info(int chip_type)
2046 {
2047         u8 tmp;
2048
2049         viaparinfo->chip_info->gfx_chip_name = chip_type;
2050
2051         /* Check revision of CLE266 Chip */
2052         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2053                 /* CR4F only define in CLE266.CX chip */
2054                 tmp = viafb_read_reg(VIACR, CR4F);
2055                 viafb_write_reg(CR4F, VIACR, 0x55);
2056                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2057                         viaparinfo->chip_info->gfx_chip_revision =
2058                         CLE266_REVISION_AX;
2059                 else
2060                         viaparinfo->chip_info->gfx_chip_revision =
2061                         CLE266_REVISION_CX;
2062                 /* restore orignal CR4F value */
2063                 viafb_write_reg(CR4F, VIACR, tmp);
2064         }
2065
2066         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2067                 tmp = viafb_read_reg(VIASR, SR43);
2068                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2069                 if (tmp & 0x02) {
2070                         viaparinfo->chip_info->gfx_chip_revision =
2071                                 CX700_REVISION_700M2;
2072                 } else if (tmp & 0x40) {
2073                         viaparinfo->chip_info->gfx_chip_revision =
2074                                 CX700_REVISION_700M;
2075                 } else {
2076                         viaparinfo->chip_info->gfx_chip_revision =
2077                                 CX700_REVISION_700;
2078                 }
2079         }
2080
2081         /* Determine which 2D engine we have */
2082         switch (viaparinfo->chip_info->gfx_chip_name) {
2083         case UNICHROME_VX800:
2084         case UNICHROME_VX855:
2085                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2086                 break;
2087         case UNICHROME_K8M890:
2088         case UNICHROME_P4M900:
2089                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2090                 break;
2091         default:
2092                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2093                 break;
2094         }
2095 }
2096
2097 static void init_tmds_chip_info(void)
2098 {
2099         viafb_tmds_trasmitter_identify();
2100
2101         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2102                 output_interface) {
2103                 switch (viaparinfo->chip_info->gfx_chip_name) {
2104                 case UNICHROME_CX700:
2105                         {
2106                                 /* we should check support by hardware layout.*/
2107                                 if ((viafb_display_hardware_layout ==
2108                                      HW_LAYOUT_DVI_ONLY)
2109                                     || (viafb_display_hardware_layout ==
2110                                         HW_LAYOUT_LCD_DVI)) {
2111                                         viaparinfo->chip_info->tmds_chip_info.
2112                                             output_interface = INTERFACE_TMDS;
2113                                 } else {
2114                                         viaparinfo->chip_info->tmds_chip_info.
2115                                                 output_interface =
2116                                                 INTERFACE_NONE;
2117                                 }
2118                                 break;
2119                         }
2120                 case UNICHROME_K8M890:
2121                 case UNICHROME_P4M900:
2122                 case UNICHROME_P4M890:
2123                         /* TMDS on PCIE, we set DFPLOW as default. */
2124                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2125                             INTERFACE_DFP_LOW;
2126                         break;
2127                 default:
2128                         {
2129                                 /* set DVP1 default for DVI */
2130                                 viaparinfo->chip_info->tmds_chip_info
2131                                 .output_interface = INTERFACE_DVP1;
2132                         }
2133                 }
2134         }
2135
2136         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2137                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2138         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2139                 &viaparinfo->shared->tmds_setting_info);
2140 }
2141
2142 static void init_lvds_chip_info(void)
2143 {
2144         viafb_lvds_trasmitter_identify();
2145         viafb_init_lcd_size();
2146         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2147                                    viaparinfo->lvds_setting_info);
2148         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2149                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2150                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2151         }
2152         /*If CX700,two singel LCD, we need to reassign
2153            LCD interface to different LVDS port */
2154         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2155             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2156                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2157                         lvds_chip_name) && (INTEGRATED_LVDS ==
2158                         viaparinfo->chip_info->
2159                         lvds_chip_info2.lvds_chip_name)) {
2160                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2161                                 INTERFACE_LVDS0;
2162                         viaparinfo->chip_info->lvds_chip_info2.
2163                                 output_interface =
2164                             INTERFACE_LVDS1;
2165                 }
2166         }
2167
2168         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2169                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2170         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2171                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2172         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2173                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2174 }
2175
2176 void viafb_init_dac(int set_iga)
2177 {
2178         int i;
2179         u8 tmp;
2180
2181         if (set_iga == IGA1) {
2182                 /* access Primary Display's LUT */
2183                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2184                 /* turn off LCK */
2185                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2186                 for (i = 0; i < 256; i++) {
2187                         write_dac_reg(i, palLUT_table[i].red,
2188                                       palLUT_table[i].green,
2189                                       palLUT_table[i].blue);
2190                 }
2191                 /* turn on LCK */
2192                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2193         } else {
2194                 tmp = viafb_read_reg(VIACR, CR6A);
2195                 /* access Secondary Display's LUT */
2196                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2197                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2198                 for (i = 0; i < 256; i++) {
2199                         write_dac_reg(i, palLUT_table[i].red,
2200                                       palLUT_table[i].green,
2201                                       palLUT_table[i].blue);
2202                 }
2203                 /* set IGA1 DAC for default */
2204                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2205                 viafb_write_reg(CR6A, VIACR, tmp);
2206         }
2207 }
2208
2209 static void device_screen_off(void)
2210 {
2211         /* turn off CRT screen (IGA1) */
2212         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2213 }
2214
2215 static void device_screen_on(void)
2216 {
2217         /* turn on CRT screen (IGA1) */
2218         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2219 }
2220
2221 static void set_display_channel(void)
2222 {
2223         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2224         is keeped on lvds_setting_info2 */
2225         if (viafb_LCD2_ON &&
2226                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2227                 /* For dual channel LCD: */
2228                 /* Set to Dual LVDS channel. */
2229                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2230         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2231                 /* For LCD+DFP: */
2232                 /* Set to LVDS1 + TMDS channel. */
2233                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2234         } else if (viafb_DVI_ON) {
2235                 /* Set to single TMDS channel. */
2236                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2237         } else if (viafb_LCD_ON) {
2238                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2239                         /* For dual channel LCD: */
2240                         /* Set to Dual LVDS channel. */
2241                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2242                 } else {
2243                         /* Set to LVDS0 + LVDS1 channel. */
2244                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2245                 }
2246         }
2247 }
2248
2249 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2250         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2251 {
2252         int i, j;
2253         int port;
2254         u8 value, index, mask;
2255         struct crt_mode_table *crt_timing;
2256         struct crt_mode_table *crt_timing1 = NULL;
2257
2258         device_screen_off();
2259         crt_timing = vmode_tbl->crtc;
2260
2261         if (viafb_SAMM_ON == 1) {
2262                 crt_timing1 = vmode_tbl1->crtc;
2263         }
2264
2265         inb(VIAStatus);
2266         outb(0x00, VIAAR);
2267
2268         /* Write Common Setting for Video Mode */
2269         switch (viaparinfo->chip_info->gfx_chip_name) {
2270         case UNICHROME_CLE266:
2271                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2272                 break;
2273
2274         case UNICHROME_K400:
2275                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2276                 break;
2277
2278         case UNICHROME_K800:
2279         case UNICHROME_PM800:
2280                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2281                 break;
2282
2283         case UNICHROME_CN700:
2284         case UNICHROME_K8M890:
2285         case UNICHROME_P4M890:
2286         case UNICHROME_P4M900:
2287                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2288                 break;
2289
2290         case UNICHROME_CX700:
2291         case UNICHROME_VX800:
2292                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2293                 break;
2294
2295         case UNICHROME_VX855:
2296                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2297                 break;
2298         }
2299
2300         device_off();
2301
2302         /* Fill VPIT Parameters */
2303         /* Write Misc Register */
2304         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2305
2306         /* Write Sequencer */
2307         for (i = 1; i <= StdSR; i++)
2308                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2309
2310         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2311         viafb_set_iga_path();
2312
2313         /* Write CRTC */
2314         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2315
2316         /* Write Graphic Controller */
2317         for (i = 0; i < StdGR; i++)
2318                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2319
2320         /* Write Attribute Controller */
2321         for (i = 0; i < StdAR; i++) {
2322                 inb(VIAStatus);
2323                 outb(i, VIAAR);
2324                 outb(VPIT.AR[i], VIAAR);
2325         }
2326
2327         inb(VIAStatus);
2328         outb(0x20, VIAAR);
2329
2330         /* Update Patch Register */
2331
2332         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2333             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2334             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2335             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2336                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2337                         index = res_patch_table[0].io_reg_table[j].index;
2338                         port = res_patch_table[0].io_reg_table[j].port;
2339                         value = res_patch_table[0].io_reg_table[j].value;
2340                         mask = res_patch_table[0].io_reg_table[j].mask;
2341                         viafb_write_reg_mask(index, port, value, mask);
2342                 }
2343         }
2344
2345         via_set_primary_pitch(viafbinfo->fix.line_length);
2346         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2347                 : viafbinfo->fix.line_length);
2348         via_set_primary_color_depth(viaparinfo->depth);
2349         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2350                 : viaparinfo->depth);
2351         /* Update Refresh Rate Setting */
2352
2353         /* Clear On Screen */
2354
2355         /* CRT set mode */
2356         if (viafb_CRT_ON) {
2357                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2358                         IGA2)) {
2359                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2360                                 video_bpp1 / 8,
2361                                 viaparinfo->crt_setting_info->iga_path);
2362                 } else {
2363                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2364                                 video_bpp / 8,
2365                                 viaparinfo->crt_setting_info->iga_path);
2366                 }
2367
2368                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2369                 to 8 alignment (1368),there is several pixels (2 pixels)
2370                 on right side of screen. */
2371                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2372                         viafb_unlock_crt();
2373                         viafb_write_reg(CR02, VIACR,
2374                                 viafb_read_reg(VIACR, CR02) - 1);
2375                         viafb_lock_crt();
2376                 }
2377
2378                 viafb_set_output_path(DEVICE_CRT,
2379                         viaparinfo->crt_setting_info->iga_path, 0);
2380         }
2381
2382         if (viafb_DVI_ON) {
2383                 if (viafb_SAMM_ON &&
2384                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2385                         viafb_dvi_set_mode(viafb_get_mode
2386                                      (viaparinfo->tmds_setting_info->h_active,
2387                                       viaparinfo->tmds_setting_info->
2388                                       v_active),
2389                                      video_bpp1, viaparinfo->
2390                                      tmds_setting_info->iga_path);
2391                 } else {
2392                         viafb_dvi_set_mode(viafb_get_mode
2393                                      (viaparinfo->tmds_setting_info->h_active,
2394                                       viaparinfo->
2395                                       tmds_setting_info->v_active),
2396                                      video_bpp, viaparinfo->
2397                                      tmds_setting_info->iga_path);
2398                 }
2399
2400                 viafb_set_output_path(DEVICE_DVI,
2401                         viaparinfo->tmds_setting_info->iga_path,
2402                         viaparinfo->chip_info->tmds_chip_info.output_interface);
2403         }
2404
2405         if (viafb_LCD_ON) {
2406                 if (viafb_SAMM_ON &&
2407                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2408                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2409                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2410                                 lvds_setting_info,
2411                                      &viaparinfo->chip_info->lvds_chip_info);
2412                 } else {
2413                         /* IGA1 doesn't have LCD scaling, so set it center. */
2414                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2415                                 viaparinfo->lvds_setting_info->display_method =
2416                                     LCD_CENTERING;
2417                         }
2418                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2419                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2420                                 lvds_setting_info,
2421                                      &viaparinfo->chip_info->lvds_chip_info);
2422                 }
2423
2424                 viafb_set_output_path(DEVICE_LCD,
2425                         viaparinfo->lvds_setting_info->iga_path,
2426                         viaparinfo->chip_info->
2427                         lvds_chip_info.output_interface);
2428         }
2429         if (viafb_LCD2_ON) {
2430                 if (viafb_SAMM_ON &&
2431                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2432                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2433                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2434                                 lvds_setting_info2,
2435                                      &viaparinfo->chip_info->lvds_chip_info2);
2436                 } else {
2437                         /* IGA1 doesn't have LCD scaling, so set it center. */
2438                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2439                                 viaparinfo->lvds_setting_info2->display_method =
2440                                     LCD_CENTERING;
2441                         }
2442                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2443                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2444                                 lvds_setting_info2,
2445                                      &viaparinfo->chip_info->lvds_chip_info2);
2446                 }
2447
2448                 viafb_set_output_path(DEVICE_LCD,
2449                         viaparinfo->lvds_setting_info2->iga_path,
2450                         viaparinfo->chip_info->
2451                         lvds_chip_info2.output_interface);
2452         }
2453
2454         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2455             && (viafb_LCD_ON || viafb_DVI_ON))
2456                 set_display_channel();
2457
2458         /* If set mode normally, save resolution information for hot-plug . */
2459         if (!viafb_hotplug) {
2460                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2461                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2462                 viafb_hotplug_bpp = video_bpp;
2463                 viafb_hotplug_refresh = viafb_refresh;
2464
2465                 if (viafb_DVI_ON)
2466                         viafb_DeviceStatus = DVI_Device;
2467                 else
2468                         viafb_DeviceStatus = CRT_Device;
2469         }
2470         device_on();
2471         device_screen_on();
2472         return 1;
2473 }
2474
2475 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2476 {
2477         int i;
2478
2479         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2480                 if ((hres == res_map_refresh_tbl[i].hres)
2481                     && (vres == res_map_refresh_tbl[i].vres)
2482                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2483                         return res_map_refresh_tbl[i].pixclock;
2484         }
2485         return RES_640X480_60HZ_PIXCLOCK;
2486
2487 }
2488
2489 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2490 {
2491 #define REFRESH_TOLERANCE 3
2492         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2493         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2494                 if ((hres == res_map_refresh_tbl[i].hres)
2495                     && (vres == res_map_refresh_tbl[i].vres)
2496                     && (diff > (abs(long_refresh -
2497                     res_map_refresh_tbl[i].vmode_refresh)))) {
2498                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2499                                 vmode_refresh);
2500                         nearest = i;
2501                 }
2502         }
2503 #undef REFRESH_TOLERANCE
2504         if (nearest > 0)
2505                 return res_map_refresh_tbl[nearest].vmode_refresh;
2506         return 60;
2507 }
2508
2509 static void device_off(void)
2510 {
2511         viafb_crt_disable();
2512         viafb_dvi_disable();
2513         viafb_lcd_disable();
2514 }
2515
2516 static void device_on(void)
2517 {
2518         if (viafb_CRT_ON == 1)
2519                 viafb_crt_enable();
2520         if (viafb_DVI_ON == 1)
2521                 viafb_dvi_enable();
2522         if (viafb_LCD_ON == 1)
2523                 viafb_lcd_enable();
2524 }
2525
2526 void viafb_crt_disable(void)
2527 {
2528         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2529 }
2530
2531 void viafb_crt_enable(void)
2532 {
2533         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2534 }
2535
2536 static void enable_second_display_channel(void)
2537 {
2538         /* to enable second display channel. */
2539         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2540         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2541         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2542 }
2543
2544 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2545                                         *p_gfx_dpa_setting)
2546 {
2547         switch (output_interface) {
2548         case INTERFACE_DVP0:
2549                 {
2550                         /* DVP0 Clock Polarity and Adjust: */
2551                         viafb_write_reg_mask(CR96, VIACR,
2552                                        p_gfx_dpa_setting->DVP0, 0x0F);
2553
2554                         /* DVP0 Clock and Data Pads Driving: */
2555                         viafb_write_reg_mask(SR1E, VIASR,
2556                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2557                         viafb_write_reg_mask(SR2A, VIASR,
2558                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2559                                        BIT4);
2560                         viafb_write_reg_mask(SR1B, VIASR,
2561                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2562                         viafb_write_reg_mask(SR2A, VIASR,
2563                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2564                         break;
2565                 }
2566
2567         case INTERFACE_DVP1:
2568                 {
2569                         /* DVP1 Clock Polarity and Adjust: */
2570                         viafb_write_reg_mask(CR9B, VIACR,
2571                                        p_gfx_dpa_setting->DVP1, 0x0F);
2572
2573                         /* DVP1 Clock and Data Pads Driving: */
2574                         viafb_write_reg_mask(SR65, VIASR,
2575                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2576                         break;
2577                 }
2578
2579         case INTERFACE_DFP_HIGH:
2580                 {
2581                         viafb_write_reg_mask(CR97, VIACR,
2582                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2583                         break;
2584                 }
2585
2586         case INTERFACE_DFP_LOW:
2587                 {
2588                         viafb_write_reg_mask(CR99, VIACR,
2589                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2590                         break;
2591                 }
2592
2593         case INTERFACE_DFP:
2594                 {
2595                         viafb_write_reg_mask(CR97, VIACR,
2596                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2597                         viafb_write_reg_mask(CR99, VIACR,
2598                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2599                         break;
2600                 }
2601         }
2602 }
2603
2604 /*According var's xres, yres fill var's other timing information*/
2605 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2606         struct VideoModeTable *vmode_tbl)
2607 {
2608         struct crt_mode_table *crt_timing = NULL;
2609         struct display_timing crt_reg;
2610         int i = 0, index = 0;
2611         crt_timing = vmode_tbl->crtc;
2612         for (i = 0; i < vmode_tbl->mode_array; i++) {
2613                 index = i;
2614                 if (crt_timing[i].refresh_rate == refresh)
2615                         break;
2616         }
2617
2618         crt_reg = crt_timing[index].crtc;
2619         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2620         var->left_margin =
2621             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2622         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2623         var->hsync_len = crt_reg.hor_sync_end;
2624         var->upper_margin =
2625             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2626         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2627         var->vsync_len = crt_reg.ver_sync_end;
2628 }