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viafb: reduce viafb_set_iga_path usage
[~shefty/rdma-dev.git] / drivers / video / via / hw.c
1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 #include <linux/via-core.h>
23 #include "global.h"
24
25 static struct pll_map pll_value[] = {
26         {25175000,
27                 {99, 7, 3},
28                 {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
29                 {141, 5, 4},
30                 {141, 5, 4} },
31         {29581000,
32                 {33, 4, 2},
33                 {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
34                 {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
35                 {165, 5, 4} },
36         {26880000,
37                 {15, 4, 1},
38                 {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
39                 {150, 5, 4},
40                 {150, 5, 4} },
41         {31500000,
42                 {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
43                 {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
44                 {176, 5, 4},
45                 {176, 5, 4} },
46         {31728000,
47                 {31, 7, 1},
48                 {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
49                 {177, 5, 4},
50                 {142, 4, 4} },
51         {32688000,
52                 {73, 4, 3},
53                 {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
54                 {183, 5, 4},
55                 {146, 4, 4} },
56         {36000000,
57                 {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
58                 {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
59                 {202, 5, 4},
60                 {161, 4, 4} },
61         {40000000,
62                 {89, 4, 3},
63                 {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
64                 {112, 5, 3},
65                 {112, 5, 3} },
66         {41291000,
67                 {23, 4, 1},
68                 {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
69                 {115, 5, 3},
70                 {115, 5, 3} },
71         {43163000,
72                 {121, 5, 3},
73                 {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
74                 {121, 5, 3},
75                 {121, 5, 3} },
76         {45250000,
77                 {127, 5, 3},
78                 {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
79                 {127, 5, 3},
80                 {127, 5, 3} },
81         {46000000,
82                 {90, 7, 2},
83                 {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
84                 {129, 5, 3},
85                 {103, 4, 3} },
86         {46996000,
87                 {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
88                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
89                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
90                 {105, 4, 3} },
91         {48000000,
92                 {67, 20, 0},
93                 {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
94                 {134, 5, 3},
95                 {134, 5, 3} },
96         {48875000,
97                 {99, 29, 0},
98                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
99                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
100                 {137, 5, 3} },
101         {49500000,
102                 {83, 6, 2},
103                 {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
104                 {138, 5, 3},
105                 {83, 3, 3} },
106         {52406000,
107                 {117, 4, 3},
108                 {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
109                 {117, 4, 3},
110                 {88, 3, 3} },
111         {52977000,
112                 {37, 5, 1},
113                 {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
114                 {148, 5, 3},
115                 {148, 5, 3} },
116         {56250000,
117                 {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
118                 {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
119                 {157, 5, 3},
120                 {157, 5, 3} },
121         {57275000,
122                 {0, 0, 0},
123                 {2, 2, 0},
124                 {2, 2, 0},
125                 {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
126         {60466000,
127                 {76, 9, 1},
128                 {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
129                 {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
130                 {169, 5, 3} },
131         {61500000,
132                 {86, 20, 0},
133                 {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
134                 {172, 5, 3},
135                 {172, 5, 3} },
136         {65000000,
137                 {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
138                 {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
139                 {109, 3, 3},
140                 {109, 3, 3} },
141         {65178000,
142                 {91, 5, 2},
143                 {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
144                 {109, 3, 3},
145                 {182, 5, 3} },
146         {66750000,
147                 {75, 4, 2},
148                 {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
149                 {150, 4, 3},
150                 {112, 3, 3} },
151         {68179000,
152                 {19, 4, 0},
153                 {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
154                 {190, 5, 3},
155                 {191, 5, 3} },
156         {69924000,
157                 {83, 17, 0},
158                 {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
159                 {195, 5, 3},
160                 {195, 5, 3} },
161         {70159000,
162                 {98, 20, 0},
163                 {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
164                 {196, 5, 3},
165                 {195, 5, 3} },
166         {72000000,
167                 {121, 24, 0},
168                 {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
169                 {161, 4, 3},
170                 {161, 4, 3} },
171         {78750000,
172                 {33, 3, 1},
173                 {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
174                 {110, 5, 2},
175                 {110, 5, 2} },
176         {80136000,
177                 {28, 5, 0},
178                 {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
179                 {112, 5, 2},
180                 {112, 5, 2} },
181         {83375000,
182                 {93, 2, 3},
183                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
184                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
185                 {117, 5, 2} },
186         {83950000,
187                 {41, 7, 0},
188                 {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
189                 {117, 5, 2},
190                 {117, 5, 2} },
191         {84750000,
192                 {118, 5, 2},
193                 {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
194                 {118, 5, 2},
195                 {118, 5, 2} },
196         {85860000,
197                 {84, 7, 1},
198                 {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
199                 {120, 5, 2},
200                 {118, 5, 2} },
201         {88750000,
202                 {31, 5, 0},
203                 {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
204                 {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
205                 {124, 5, 2} },
206         {94500000,
207                 {33, 5, 0},
208                 {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
209                 {132, 5, 2},
210                 {132, 5, 2} },
211         {97750000,
212                 {82, 6, 1},
213                 {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
214                 {137, 5, 2},
215                 {137, 5, 2} },
216         {101000000,
217                 {127, 9, 1},
218                 {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
219                 {141, 5, 2},
220                 {141, 5, 2} },
221         {106500000,
222                 {119, 4, 2},
223                 {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
224                 {119, 4, 2},
225                 {149, 5, 2} },
226         {108000000,
227                 {121, 4, 2},
228                 {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
229                 {151, 5, 2},
230                 {151, 5, 2} },
231         {113309000,
232                 {95, 12, 0},
233                 {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
234                 {95, 3, 2},
235                 {159, 5, 2} },
236         {118840000,
237                 {83, 5, 1},
238                 {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
239                 {166, 5, 2},
240                 {166, 5, 2} },
241         {119000000,
242                 {108, 13, 0},
243                 {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
244                 {133, 4, 2},
245                 {167, 5, 2} },
246         {121750000,
247                 {85, 5, 1},
248                 {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
249                 {68, 2, 2},
250                 {0, 0, 0} },
251         {125104000,
252                 {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
253                 {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
254                 {175, 5, 2},
255                 {0, 0, 0} },
256         {135000000,
257                 {94, 5, 1},
258                 {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
259                 {151, 4, 2},
260                 {189, 5, 2} },
261         {136700000,
262                 {115, 12, 0},
263                 {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
264                 {191, 5, 2},
265                 {191, 5, 2} },
266         {138400000,
267                 {87, 9, 0},
268                 {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
269                 {116, 3, 2},
270                 {194, 5, 2} },
271         {146760000,
272                 {103, 5, 1},
273                 {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
274                 {206, 5, 2},
275                 {206, 5, 2} },
276         {153920000,
277                 {86, 8, 0},
278                 {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
279                 {86, 4, 1},
280                 {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
281         {156000000,
282                 {109, 5, 1},
283                 {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
284                 {109, 5, 1},
285                 {108, 5, 1} },
286         {157500000,
287                 {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
288                 {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
289                 {110, 5, 1},
290                 {110, 5, 1} },
291         {162000000,
292                 {113, 5, 1},
293                 {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
294                 {113, 5, 1},
295                 {113, 5, 1} },
296         {187000000,
297                 {118, 9, 0},
298                 {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
299                 {131, 5, 1},
300                 {131, 5, 1} },
301         {193295000,
302                 {108, 8, 0},
303                 {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
304                 {135, 5, 1},
305                 {135, 5, 1} },
306         {202500000,
307                 {99, 7, 0},
308                 {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
309                 {142, 5, 1},
310                 {142, 5, 1} },
311         {204000000,
312                 {100, 7, 0},
313                 {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
314                 {143, 5, 1},
315                 {143, 5, 1} },
316         {218500000,
317                 {92, 6, 0},
318                 {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
319                 {153, 5, 1},
320                 {153, 5, 1} },
321         {234000000,
322                 {98, 6, 0},
323                 {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
324                 {98, 3, 1},
325                 {164, 5, 1} },
326         {267250000,
327                 {112, 6, 0},
328                 {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
329                 {187, 5, 1},
330                 {187, 5, 1} },
331         {297500000,
332                 {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
333                 {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
334                 {208, 5, 1},
335                 {208, 5, 1} },
336         {74481000,
337                 {26, 5, 0},
338                 {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
339                 {208, 5, 3},
340                 {209, 5, 3} },
341         {172798000,
342                 {121, 5, 1},
343                 {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
344                 {121, 5, 1},
345                 {121, 5, 1} },
346         {122614000,
347                 {60, 7, 0},
348                 {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
349                 {137, 4, 2},
350                 {172, 5, 2} },
351         {74270000,
352                 {83, 8, 1},
353                 {208, 5, 3},
354                 {208, 5, 3},
355                 {0, 0, 0} },
356         {148500000,
357                 {83, 8, 0},
358                 {208, 5, 2},
359                 {166, 4, 2},
360                 {208, 5, 2} }
361 };
362
363 static struct fifo_depth_select display_fifo_depth_reg = {
364         /* IGA1 FIFO Depth_Select */
365         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
366         /* IGA2 FIFO Depth_Select */
367         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
368          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
369 };
370
371 static struct fifo_threshold_select fifo_threshold_select_reg = {
372         /* IGA1 FIFO Threshold Select */
373         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
374         /* IGA2 FIFO Threshold Select */
375         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
376 };
377
378 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
379         /* IGA1 FIFO High Threshold Select */
380         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
381         /* IGA2 FIFO High Threshold Select */
382         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
383 };
384
385 static struct display_queue_expire_num display_queue_expire_num_reg = {
386         /* IGA1 Display Queue Expire Num */
387         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
388         /* IGA2 Display Queue Expire Num */
389         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
390 };
391
392 /* Definition Fetch Count Registers*/
393 static struct fetch_count fetch_count_reg = {
394         /* IGA1 Fetch Count Register */
395         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
396         /* IGA2 Fetch Count Register */
397         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
398 };
399
400 static struct iga1_crtc_timing iga1_crtc_reg = {
401         /* IGA1 Horizontal Total */
402         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
403         /* IGA1 Horizontal Addressable Video */
404         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
405         /* IGA1 Horizontal Blank Start */
406         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
407         /* IGA1 Horizontal Blank End */
408         {IGA1_HOR_BLANK_END_REG_NUM,
409          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
410         /* IGA1 Horizontal Sync Start */
411         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
412         /* IGA1 Horizontal Sync End */
413         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
414         /* IGA1 Vertical Total */
415         {IGA1_VER_TOTAL_REG_NUM,
416          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
417         /* IGA1 Vertical Addressable Video */
418         {IGA1_VER_ADDR_REG_NUM,
419          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
420         /* IGA1 Vertical Blank Start */
421         {IGA1_VER_BLANK_START_REG_NUM,
422          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
423         /* IGA1 Vertical Blank End */
424         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
425         /* IGA1 Vertical Sync Start */
426         {IGA1_VER_SYNC_START_REG_NUM,
427          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
428         /* IGA1 Vertical Sync End */
429         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
430 };
431
432 static struct iga2_crtc_timing iga2_crtc_reg = {
433         /* IGA2 Horizontal Total */
434         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
435         /* IGA2 Horizontal Addressable Video */
436         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
437         /* IGA2 Horizontal Blank Start */
438         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
439         /* IGA2 Horizontal Blank End */
440         {IGA2_HOR_BLANK_END_REG_NUM,
441          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
442         /* IGA2 Horizontal Sync Start */
443         {IGA2_HOR_SYNC_START_REG_NUM,
444          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
445         /* IGA2 Horizontal Sync End */
446         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
447         /* IGA2 Vertical Total */
448         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
449         /* IGA2 Vertical Addressable Video */
450         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
451         /* IGA2 Vertical Blank Start */
452         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
453         /* IGA2 Vertical Blank End */
454         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
455         /* IGA2 Vertical Sync Start */
456         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
457         /* IGA2 Vertical Sync End */
458         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
459 };
460
461 static struct rgbLUT palLUT_table[] = {
462         /* {R,G,B} */
463         /* Index 0x00~0x03 */
464         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
465                                                                      0x2A,
466                                                                      0x2A},
467         /* Index 0x04~0x07 */
468         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
469                                                                      0x2A,
470                                                                      0x2A},
471         /* Index 0x08~0x0B */
472         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
473                                                                      0x3F,
474                                                                      0x3F},
475         /* Index 0x0C~0x0F */
476         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
477                                                                      0x3F,
478                                                                      0x3F},
479         /* Index 0x10~0x13 */
480         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
481                                                                      0x0B,
482                                                                      0x0B},
483         /* Index 0x14~0x17 */
484         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
485                                                                      0x18,
486                                                                      0x18},
487         /* Index 0x18~0x1B */
488         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
489                                                                      0x28,
490                                                                      0x28},
491         /* Index 0x1C~0x1F */
492         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
493                                                                      0x3F,
494                                                                      0x3F},
495         /* Index 0x20~0x23 */
496         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
497                                                                      0x00,
498                                                                      0x3F},
499         /* Index 0x24~0x27 */
500         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
501                                                                      0x00,
502                                                                      0x10},
503         /* Index 0x28~0x2B */
504         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
505                                                                      0x2F,
506                                                                      0x00},
507         /* Index 0x2C~0x2F */
508         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
509                                                                      0x3F,
510                                                                      0x00},
511         /* Index 0x30~0x33 */
512         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
513                                                                      0x3F,
514                                                                      0x2F},
515         /* Index 0x34~0x37 */
516         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
517                                                                      0x10,
518                                                                      0x3F},
519         /* Index 0x38~0x3B */
520         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
521                                                                      0x1F,
522                                                                      0x3F},
523         /* Index 0x3C~0x3F */
524         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
525                                                                      0x1F,
526                                                                      0x27},
527         /* Index 0x40~0x43 */
528         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
529                                                                      0x3F,
530                                                                      0x1F},
531         /* Index 0x44~0x47 */
532         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
533                                                                      0x3F,
534                                                                      0x1F},
535         /* Index 0x48~0x4B */
536         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
537                                                                      0x3F,
538                                                                      0x37},
539         /* Index 0x4C~0x4F */
540         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
541                                                                      0x27,
542                                                                      0x3F},
543         /* Index 0x50~0x53 */
544         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
545                                                                      0x2D,
546                                                                      0x3F},
547         /* Index 0x54~0x57 */
548         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
549                                                                      0x2D,
550                                                                      0x31},
551         /* Index 0x58~0x5B */
552         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
553                                                                      0x3A,
554                                                                      0x2D},
555         /* Index 0x5C~0x5F */
556         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
557                                                                      0x3F,
558                                                                      0x2D},
559         /* Index 0x60~0x63 */
560         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
561                                                                      0x3F,
562                                                                      0x3A},
563         /* Index 0x64~0x67 */
564         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
565                                                                      0x31,
566                                                                      0x3F},
567         /* Index 0x68~0x6B */
568         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
569                                                                      0x00,
570                                                                      0x1C},
571         /* Index 0x6C~0x6F */
572         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
573                                                                      0x00,
574                                                                      0x07},
575         /* Index 0x70~0x73 */
576         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
577                                                                      0x15,
578                                                                      0x00},
579         /* Index 0x74~0x77 */
580         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
581                                                                      0x1C,
582                                                                      0x00},
583         /* Index 0x78~0x7B */
584         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
585                                                                      0x1C,
586                                                                      0x15},
587         /* Index 0x7C~0x7F */
588         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
589                                                                      0x07,
590                                                                      0x1C},
591         /* Index 0x80~0x83 */
592         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
593                                                                      0x0E,
594                                                                      0x1C},
595         /* Index 0x84~0x87 */
596         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
597                                                                      0x0E,
598                                                                      0x11},
599         /* Index 0x88~0x8B */
600         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
601                                                                      0x18,
602                                                                      0x0E},
603         /* Index 0x8C~0x8F */
604         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
605                                                                      0x1C,
606                                                                      0x0E},
607         /* Index 0x90~0x93 */
608         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
609                                                                      0x1C,
610                                                                      0x18},
611         /* Index 0x94~0x97 */
612         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
613                                                                      0x11,
614                                                                      0x1C},
615         /* Index 0x98~0x9B */
616         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
617                                                                      0x14,
618                                                                      0x1C},
619         /* Index 0x9C~0x9F */
620         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
621                                                                      0x14,
622                                                                      0x16},
623         /* Index 0xA0~0xA3 */
624         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
625                                                                      0x1A,
626                                                                      0x14},
627         /* Index 0xA4~0xA7 */
628         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
629                                                                      0x1C,
630                                                                      0x14},
631         /* Index 0xA8~0xAB */
632         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
633                                                                      0x1C,
634                                                                      0x1A},
635         /* Index 0xAC~0xAF */
636         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
637                                                                      0x16,
638                                                                      0x1C},
639         /* Index 0xB0~0xB3 */
640         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
641                                                                      0x00,
642                                                                      0x10},
643         /* Index 0xB4~0xB7 */
644         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
645                                                                      0x00,
646                                                                      0x04},
647         /* Index 0xB8~0xBB */
648         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
649                                                                      0x0C,
650                                                                      0x00},
651         /* Index 0xBC~0xBF */
652         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
653                                                                      0x10,
654                                                                      0x00},
655         /* Index 0xC0~0xC3 */
656         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
657                                                                      0x10,
658                                                                      0x0C},
659         /* Index 0xC4~0xC7 */
660         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
661                                                                      0x04,
662                                                                      0x10},
663         /* Index 0xC8~0xCB */
664         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
665                                                                      0x08,
666                                                                      0x10},
667         /* Index 0xCC~0xCF */
668         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
669                                                                      0x08,
670                                                                      0x0A},
671         /* Index 0xD0~0xD3 */
672         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
673                                                                      0x0E,
674                                                                      0x08},
675         /* Index 0xD4~0xD7 */
676         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
677                                                                      0x10,
678                                                                      0x08},
679         /* Index 0xD8~0xDB */
680         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
681                                                                      0x10,
682                                                                      0x0E},
683         /* Index 0xDC~0xDF */
684         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
685                                                                      0x0A,
686                                                                      0x10},
687         /* Index 0xE0~0xE3 */
688         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
689                                                                      0x0B,
690                                                                      0x10},
691         /* Index 0xE4~0xE7 */
692         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
693                                                                      0x0B,
694                                                                      0x0C},
695         /* Index 0xE8~0xEB */
696         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
697                                                                      0x0F,
698                                                                      0x0B},
699         /* Index 0xEC~0xEF */
700         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
701                                                                      0x10,
702                                                                      0x0B},
703         /* Index 0xF0~0xF3 */
704         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
705                                                                      0x10,
706                                                                      0x0F},
707         /* Index 0xF4~0xF7 */
708         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
709                                                                      0x0C,
710                                                                      0x10},
711         /* Index 0xF8~0xFB */
712         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
713                                                                      0x00,
714                                                                      0x00},
715         /* Index 0xFC~0xFF */
716         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
717                                                                      0x00,
718                                                                      0x00}
719 };
720
721 static void set_crt_output_path(int set_iga);
722 static void dvi_patch_skew_dvp0(void);
723 static void dvi_patch_skew_dvp_low(void);
724 static void set_dvi_output_path(int set_iga, int output_interface);
725 static void set_lcd_output_path(int set_iga, int output_interface);
726 static void load_fix_bit_crtc_reg(void);
727 static void __devinit init_gfx_chip_info(int chip_type);
728 static void __devinit init_tmds_chip_info(void);
729 static void __devinit init_lvds_chip_info(void);
730 static void device_screen_off(void);
731 static void device_screen_on(void);
732 static void set_display_channel(void);
733 static void device_off(void);
734 static void device_on(void);
735 static void enable_second_display_channel(void);
736
737 void viafb_lock_crt(void)
738 {
739         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
740 }
741
742 void viafb_unlock_crt(void)
743 {
744         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
745         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
746 }
747
748 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
749 {
750         outb(index, LUT_INDEX_WRITE);
751         outb(r, LUT_DATA);
752         outb(g, LUT_DATA);
753         outb(b, LUT_DATA);
754 }
755
756 /*Set IGA path for each device*/
757 void viafb_set_iga_path(void)
758 {
759
760         if (viafb_SAMM_ON == 1) {
761                 if (viafb_CRT_ON) {
762                         if (viafb_primary_dev == CRT_Device)
763                                 viaparinfo->crt_setting_info->iga_path = IGA1;
764                         else
765                                 viaparinfo->crt_setting_info->iga_path = IGA2;
766                 }
767
768                 if (viafb_DVI_ON) {
769                         if (viafb_primary_dev == DVI_Device)
770                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
771                         else
772                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
773                 }
774
775                 if (viafb_LCD_ON) {
776                         if (viafb_primary_dev == LCD_Device) {
777                                 if (viafb_dual_fb &&
778                                         (viaparinfo->chip_info->gfx_chip_name ==
779                                         UNICHROME_CLE266)) {
780                                         viaparinfo->
781                                         lvds_setting_info->iga_path = IGA2;
782                                         viaparinfo->
783                                         crt_setting_info->iga_path = IGA1;
784                                         viaparinfo->
785                                         tmds_setting_info->iga_path = IGA1;
786                                 } else
787                                         viaparinfo->
788                                         lvds_setting_info->iga_path = IGA1;
789                         } else {
790                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
791                         }
792                 }
793                 if (viafb_LCD2_ON) {
794                         if (LCD2_Device == viafb_primary_dev)
795                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
796                         else
797                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
798                 }
799         } else {
800                 viafb_SAMM_ON = 0;
801
802                 if (viafb_CRT_ON && viafb_LCD_ON) {
803                         viaparinfo->crt_setting_info->iga_path = IGA1;
804                         viaparinfo->lvds_setting_info->iga_path = IGA2;
805                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
806                         viaparinfo->crt_setting_info->iga_path = IGA1;
807                         viaparinfo->tmds_setting_info->iga_path = IGA2;
808                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
809                         viaparinfo->tmds_setting_info->iga_path = IGA1;
810                         viaparinfo->lvds_setting_info->iga_path = IGA2;
811                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
812                         viaparinfo->lvds_setting_info->iga_path = IGA2;
813                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
814                 } else if (viafb_CRT_ON) {
815                         viaparinfo->crt_setting_info->iga_path = IGA1;
816                 } else if (viafb_LCD_ON) {
817                         viaparinfo->lvds_setting_info->iga_path = IGA2;
818                 } else if (viafb_DVI_ON) {
819                         viaparinfo->tmds_setting_info->iga_path = IGA1;
820                 }
821         }
822 }
823
824 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
825 {
826         outb(0xFF, 0x3C6); /* bit mask of palette */
827         outb(index, 0x3C8);
828         outb(red, 0x3C9);
829         outb(green, 0x3C9);
830         outb(blue, 0x3C9);
831 }
832
833 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
834 {
835         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
836         set_color_register(index, red, green, blue);
837 }
838
839 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
840 {
841         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
842         set_color_register(index, red, green, blue);
843 }
844
845 void viafb_set_output_path(int device, int set_iga, int output_interface)
846 {
847         switch (device) {
848         case DEVICE_CRT:
849                 set_crt_output_path(set_iga);
850                 break;
851         case DEVICE_DVI:
852                 set_dvi_output_path(set_iga, output_interface);
853                 break;
854         case DEVICE_LCD:
855                 set_lcd_output_path(set_iga, output_interface);
856                 break;
857         }
858
859         if (set_iga == IGA2)
860                 enable_second_display_channel();
861 }
862
863 static void set_source_common(u8 index, u8 offset, u8 iga)
864 {
865         u8 value, mask = 1 << offset;
866
867         switch (iga) {
868         case IGA1:
869                 value = 0x00;
870                 break;
871         case IGA2:
872                 value = mask;
873                 break;
874         default:
875                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
876                 return;
877         }
878
879         via_write_reg_mask(VIACR, index, value, mask);
880 }
881
882 static void set_crt_source(u8 iga)
883 {
884         u8 value;
885
886         switch (iga) {
887         case IGA1:
888                 value = 0x00;
889                 break;
890         case IGA2:
891                 value = 0x40;
892                 break;
893         default:
894                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
895                 return;
896         }
897
898         via_write_reg_mask(VIASR, 0x16, value, 0x40);
899 }
900
901 static inline void set_6C_source(u8 iga)
902 {
903         set_source_common(0x6C, 7, iga);
904 }
905
906 static inline void set_93_source(u8 iga)
907 {
908         set_source_common(0x93, 7, iga);
909 }
910
911 static inline void set_96_source(u8 iga)
912 {
913         set_source_common(0x96, 4, iga);
914 }
915
916 static inline void set_dvp1_source(u8 iga)
917 {
918         set_source_common(0x9B, 4, iga);
919 }
920
921 static inline void set_lvds1_source(u8 iga)
922 {
923         set_source_common(0x99, 4, iga);
924 }
925
926 static inline void set_lvds2_source(u8 iga)
927 {
928         set_source_common(0x97, 4, iga);
929 }
930
931 static void set_crt_output_path(int set_iga)
932 {
933         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
934         set_crt_source(set_iga);
935 }
936
937 static void dvi_patch_skew_dvp0(void)
938 {
939         /* Reset data driving first: */
940         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
941         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
942
943         switch (viaparinfo->chip_info->gfx_chip_name) {
944         case UNICHROME_P4M890:
945                 {
946                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
947                                 (viaparinfo->tmds_setting_info->v_active ==
948                                 1200))
949                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
950                                                BIT0 + BIT1 + BIT2);
951                         else
952                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
953                                                BIT0 + BIT1 + BIT2);
954                         break;
955                 }
956
957         case UNICHROME_P4M900:
958                 {
959                         viafb_write_reg_mask(CR96, VIACR, 0x07,
960                                        BIT0 + BIT1 + BIT2 + BIT3);
961                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
962                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
963                         break;
964                 }
965
966         default:
967                 {
968                         break;
969                 }
970         }
971 }
972
973 static void dvi_patch_skew_dvp_low(void)
974 {
975         switch (viaparinfo->chip_info->gfx_chip_name) {
976         case UNICHROME_K8M890:
977                 {
978                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
979                         break;
980                 }
981
982         case UNICHROME_P4M900:
983                 {
984                         viafb_write_reg_mask(CR99, VIACR, 0x08,
985                                        BIT0 + BIT1 + BIT2 + BIT3);
986                         break;
987                 }
988
989         case UNICHROME_P4M890:
990                 {
991                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
992                                        BIT0 + BIT1 + BIT2 + BIT3);
993                         break;
994                 }
995
996         default:
997                 {
998                         break;
999                 }
1000         }
1001 }
1002
1003 static void set_dvi_output_path(int set_iga, int output_interface)
1004 {
1005         switch (output_interface) {
1006         case INTERFACE_DVP0:
1007                 set_96_source(set_iga);
1008                 set_6C_source(set_iga);
1009                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
1010                 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
1011                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
1012                 dvi_patch_skew_dvp0();
1013                 break;
1014
1015         case INTERFACE_DVP1:
1016                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1017                         set_93_source(set_iga);
1018                         viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
1019                 } else {
1020                         set_dvp1_source(set_iga);
1021                 }
1022
1023                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
1024                 break;
1025         case INTERFACE_DFP_HIGH:
1026                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
1027                         via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
1028                         set_lvds2_source(set_iga);
1029                         set_96_source(set_iga);
1030                 }
1031
1032                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
1033                 break;
1034
1035         case INTERFACE_DFP_LOW:
1036                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1037                         break;
1038                 set_dvp1_source(set_iga);
1039                 set_lvds1_source(set_iga);
1040                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
1041                 dvi_patch_skew_dvp_low();
1042                 break;
1043
1044         case INTERFACE_TMDS:
1045                 set_lvds1_source(set_iga);
1046                 break;
1047         }
1048
1049         if (set_iga == IGA2) {
1050                 /* Disable LCD Scaling */
1051                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
1052         }
1053 }
1054
1055 static void set_lcd_output_path(int set_iga, int output_interface)
1056 {
1057         DEBUG_MSG(KERN_INFO
1058                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
1059                   set_iga, output_interface);
1060
1061         viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1062         viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1063         switch (output_interface) {
1064         case INTERFACE_DVP0:
1065                 set_96_source(set_iga);
1066                 if (set_iga == IGA2)
1067                         viafb_write_reg(CR91, VIACR, 0x00);
1068                 break;
1069
1070         case INTERFACE_DVP1:
1071                 set_dvp1_source(set_iga);
1072                 if (set_iga == IGA2)
1073                         viafb_write_reg(CR91, VIACR, 0x00);
1074                 break;
1075
1076         case INTERFACE_DFP_HIGH:
1077                 set_lvds2_source(set_iga);
1078                 set_96_source(set_iga);
1079                 if (set_iga == IGA2)
1080                         viafb_write_reg(CR91, VIACR, 0x00);
1081                 break;
1082
1083         case INTERFACE_DFP_LOW:
1084                 set_lvds1_source(set_iga);
1085                 set_dvp1_source(set_iga);
1086                 if (set_iga == IGA2)
1087                         viafb_write_reg(CR91, VIACR, 0x00);
1088                 break;
1089
1090         case INTERFACE_DFP:
1091                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1092                     || (UNICHROME_P4M890 ==
1093                     viaparinfo->chip_info->gfx_chip_name))
1094                         viafb_write_reg_mask(CR97, VIACR, 0x84,
1095                                        BIT7 + BIT2 + BIT1 + BIT0);
1096
1097                 set_lvds1_source(set_iga);
1098                 set_lvds2_source(set_iga);
1099                 if (set_iga == IGA2)
1100                         viafb_write_reg(CR91, VIACR, 0x00);
1101                 break;
1102
1103         case INTERFACE_LVDS0:
1104         case INTERFACE_LVDS0LVDS1:
1105                 set_lvds1_source(set_iga);
1106                 break;
1107
1108         case INTERFACE_LVDS1:
1109                 set_lvds2_source(set_iga);
1110                 break;
1111         }
1112 }
1113
1114 static void load_fix_bit_crtc_reg(void)
1115 {
1116         /* always set to 1 */
1117         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1118         /* line compare should set all bits = 1 (extend modes) */
1119         viafb_write_reg(CR18, VIACR, 0xff);
1120         /* line compare should set all bits = 1 (extend modes) */
1121         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1122         /* line compare should set all bits = 1 (extend modes) */
1123         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1124         /* line compare should set all bits = 1 (extend modes) */
1125         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1126         /* line compare should set all bits = 1 (extend modes) */
1127         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1128         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1129         /* extend mode always set to e3h */
1130         viafb_write_reg(CR17, VIACR, 0xe3);
1131         /* extend mode always set to 0h */
1132         viafb_write_reg(CR08, VIACR, 0x00);
1133         /* extend mode always set to 0h */
1134         viafb_write_reg(CR14, VIACR, 0x00);
1135
1136         /* If K8M800, enable Prefetch Mode. */
1137         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1138                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1139                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1140         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1141             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1142                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1143
1144 }
1145
1146 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1147         struct io_register *reg,
1148               int io_type)
1149 {
1150         int reg_mask;
1151         int bit_num = 0;
1152         int data;
1153         int i, j;
1154         int shift_next_reg;
1155         int start_index, end_index, cr_index;
1156         u16 get_bit;
1157
1158         for (i = 0; i < viafb_load_reg_num; i++) {
1159                 reg_mask = 0;
1160                 data = 0;
1161                 start_index = reg[i].start_bit;
1162                 end_index = reg[i].end_bit;
1163                 cr_index = reg[i].io_addr;
1164
1165                 shift_next_reg = bit_num;
1166                 for (j = start_index; j <= end_index; j++) {
1167                         /*if (bit_num==8) timing_value = timing_value >>8; */
1168                         reg_mask = reg_mask | (BIT0 << j);
1169                         get_bit = (timing_value & (BIT0 << bit_num));
1170                         data =
1171                             data | ((get_bit >> shift_next_reg) << start_index);
1172                         bit_num++;
1173                 }
1174                 if (io_type == VIACR)
1175                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1176                 else
1177                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1178         }
1179
1180 }
1181
1182 /* Write Registers */
1183 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1184 {
1185         int i;
1186
1187         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1188
1189         for (i = 0; i < ItemNum; i++)
1190                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1191                         RegTable[i].value, RegTable[i].mask);
1192 }
1193
1194 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1195 {
1196         int reg_value;
1197         int viafb_load_reg_num;
1198         struct io_register *reg = NULL;
1199
1200         switch (set_iga) {
1201         case IGA1:
1202                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1203                 viafb_load_reg_num = fetch_count_reg.
1204                         iga1_fetch_count_reg.reg_num;
1205                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1206                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1207                 break;
1208         case IGA2:
1209                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1210                 viafb_load_reg_num = fetch_count_reg.
1211                         iga2_fetch_count_reg.reg_num;
1212                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1213                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1214                 break;
1215         }
1216
1217 }
1218
1219 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1220 {
1221         int reg_value;
1222         int viafb_load_reg_num;
1223         struct io_register *reg = NULL;
1224         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1225             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1226         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1227             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1228
1229         if (set_iga == IGA1) {
1230                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1231                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1232                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1233                         iga1_fifo_high_threshold =
1234                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1235                         /* If resolution > 1280x1024, expire length = 64, else
1236                            expire length = 128 */
1237                         if ((hor_active > 1280) && (ver_active > 1024))
1238                                 iga1_display_queue_expire_num = 16;
1239                         else
1240                                 iga1_display_queue_expire_num =
1241                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1242
1243                 }
1244
1245                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1246                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1247                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1248                         iga1_fifo_high_threshold =
1249                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1250                         iga1_display_queue_expire_num =
1251                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1252
1253                         /* If resolution > 1280x1024, expire length = 64, else
1254                            expire length = 128 */
1255                         if ((hor_active > 1280) && (ver_active > 1024))
1256                                 iga1_display_queue_expire_num = 16;
1257                         else
1258                                 iga1_display_queue_expire_num =
1259                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1260                 }
1261
1262                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1263                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1264                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1265                         iga1_fifo_high_threshold =
1266                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1267
1268                         /* If resolution > 1280x1024, expire length = 64,
1269                            else expire length = 128 */
1270                         if ((hor_active > 1280) && (ver_active > 1024))
1271                                 iga1_display_queue_expire_num = 16;
1272                         else
1273                                 iga1_display_queue_expire_num =
1274                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1275                 }
1276
1277                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1278                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1279                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1280                         iga1_fifo_high_threshold =
1281                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1282                         iga1_display_queue_expire_num =
1283                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1284                 }
1285
1286                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1287                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1288                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1289                         iga1_fifo_high_threshold =
1290                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1291                         iga1_display_queue_expire_num =
1292                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1293                 }
1294
1295                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1296                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1297                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1298                         iga1_fifo_high_threshold =
1299                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1300                         iga1_display_queue_expire_num =
1301                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1302                 }
1303
1304                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1305                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1306                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1307                         iga1_fifo_high_threshold =
1308                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1309                         iga1_display_queue_expire_num =
1310                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1311                 }
1312
1313                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1314                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1315                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1316                         iga1_fifo_high_threshold =
1317                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1318                         iga1_display_queue_expire_num =
1319                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1320                 }
1321
1322                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1323                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1324                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1325                         iga1_fifo_high_threshold =
1326                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1327                         iga1_display_queue_expire_num =
1328                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1329                 }
1330
1331                 /* Set Display FIFO Depath Select */
1332                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1333                 viafb_load_reg_num =
1334                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1335                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1336                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1337
1338                 /* Set Display FIFO Threshold Select */
1339                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1340                 viafb_load_reg_num =
1341                     fifo_threshold_select_reg.
1342                     iga1_fifo_threshold_select_reg.reg_num;
1343                 reg =
1344                     fifo_threshold_select_reg.
1345                     iga1_fifo_threshold_select_reg.reg;
1346                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1347
1348                 /* Set FIFO High Threshold Select */
1349                 reg_value =
1350                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1351                 viafb_load_reg_num =
1352                     fifo_high_threshold_select_reg.
1353                     iga1_fifo_high_threshold_select_reg.reg_num;
1354                 reg =
1355                     fifo_high_threshold_select_reg.
1356                     iga1_fifo_high_threshold_select_reg.reg;
1357                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1358
1359                 /* Set Display Queue Expire Num */
1360                 reg_value =
1361                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1362                     (iga1_display_queue_expire_num);
1363                 viafb_load_reg_num =
1364                     display_queue_expire_num_reg.
1365                     iga1_display_queue_expire_num_reg.reg_num;
1366                 reg =
1367                     display_queue_expire_num_reg.
1368                     iga1_display_queue_expire_num_reg.reg;
1369                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1370
1371         } else {
1372                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1373                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1374                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1375                         iga2_fifo_high_threshold =
1376                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1377
1378                         /* If resolution > 1280x1024, expire length = 64,
1379                            else  expire length = 128 */
1380                         if ((hor_active > 1280) && (ver_active > 1024))
1381                                 iga2_display_queue_expire_num = 16;
1382                         else
1383                                 iga2_display_queue_expire_num =
1384                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1385                 }
1386
1387                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1388                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1389                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1390                         iga2_fifo_high_threshold =
1391                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1392
1393                         /* If resolution > 1280x1024, expire length = 64,
1394                            else  expire length = 128 */
1395                         if ((hor_active > 1280) && (ver_active > 1024))
1396                                 iga2_display_queue_expire_num = 16;
1397                         else
1398                                 iga2_display_queue_expire_num =
1399                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1400                 }
1401
1402                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1403                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1404                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1405                         iga2_fifo_high_threshold =
1406                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1407
1408                         /* If resolution > 1280x1024, expire length = 64,
1409                            else expire length = 128 */
1410                         if ((hor_active > 1280) && (ver_active > 1024))
1411                                 iga2_display_queue_expire_num = 16;
1412                         else
1413                                 iga2_display_queue_expire_num =
1414                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1415                 }
1416
1417                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1418                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1419                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1420                         iga2_fifo_high_threshold =
1421                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1422                         iga2_display_queue_expire_num =
1423                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1424                 }
1425
1426                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1427                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1428                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1429                         iga2_fifo_high_threshold =
1430                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1431                         iga2_display_queue_expire_num =
1432                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1433                 }
1434
1435                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1436                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1437                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1438                         iga2_fifo_high_threshold =
1439                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1440                         iga2_display_queue_expire_num =
1441                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1442                 }
1443
1444                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1445                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1446                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1447                         iga2_fifo_high_threshold =
1448                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1449                         iga2_display_queue_expire_num =
1450                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1451                 }
1452
1453                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1454                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1455                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1456                         iga2_fifo_high_threshold =
1457                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1458                         iga2_display_queue_expire_num =
1459                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1460                 }
1461
1462                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1463                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1464                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1465                         iga2_fifo_high_threshold =
1466                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1467                         iga2_display_queue_expire_num =
1468                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1469                 }
1470
1471                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1472                         /* Set Display FIFO Depath Select */
1473                         reg_value =
1474                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1475                             - 1;
1476                         /* Patch LCD in IGA2 case */
1477                         viafb_load_reg_num =
1478                             display_fifo_depth_reg.
1479                             iga2_fifo_depth_select_reg.reg_num;
1480                         reg =
1481                             display_fifo_depth_reg.
1482                             iga2_fifo_depth_select_reg.reg;
1483                         viafb_load_reg(reg_value,
1484                                 viafb_load_reg_num, reg, VIACR);
1485                 } else {
1486
1487                         /* Set Display FIFO Depath Select */
1488                         reg_value =
1489                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1490                         viafb_load_reg_num =
1491                             display_fifo_depth_reg.
1492                             iga2_fifo_depth_select_reg.reg_num;
1493                         reg =
1494                             display_fifo_depth_reg.
1495                             iga2_fifo_depth_select_reg.reg;
1496                         viafb_load_reg(reg_value,
1497                                 viafb_load_reg_num, reg, VIACR);
1498                 }
1499
1500                 /* Set Display FIFO Threshold Select */
1501                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1502                 viafb_load_reg_num =
1503                     fifo_threshold_select_reg.
1504                     iga2_fifo_threshold_select_reg.reg_num;
1505                 reg =
1506                     fifo_threshold_select_reg.
1507                     iga2_fifo_threshold_select_reg.reg;
1508                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1509
1510                 /* Set FIFO High Threshold Select */
1511                 reg_value =
1512                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1513                 viafb_load_reg_num =
1514                     fifo_high_threshold_select_reg.
1515                     iga2_fifo_high_threshold_select_reg.reg_num;
1516                 reg =
1517                     fifo_high_threshold_select_reg.
1518                     iga2_fifo_high_threshold_select_reg.reg;
1519                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1520
1521                 /* Set Display Queue Expire Num */
1522                 reg_value =
1523                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1524                     (iga2_display_queue_expire_num);
1525                 viafb_load_reg_num =
1526                     display_queue_expire_num_reg.
1527                     iga2_display_queue_expire_num_reg.reg_num;
1528                 reg =
1529                     display_queue_expire_num_reg.
1530                     iga2_display_queue_expire_num_reg.reg;
1531                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1532
1533         }
1534
1535 }
1536
1537 static u32 cle266_encode_pll(struct pll_config pll)
1538 {
1539         return (pll.multiplier << 8)
1540                 | (pll.rshift << 6)
1541                 | pll.divisor;
1542 }
1543
1544 static u32 k800_encode_pll(struct pll_config pll)
1545 {
1546         return ((pll.divisor - 2) << 16)
1547                 | (pll.rshift << 10)
1548                 | (pll.multiplier - 2);
1549 }
1550
1551 static u32 vx855_encode_pll(struct pll_config pll)
1552 {
1553         return (pll.divisor << 16)
1554                 | (pll.rshift << 10)
1555                 | pll.multiplier;
1556 }
1557
1558 u32 viafb_get_clk_value(int clk)
1559 {
1560         u32 value = 0;
1561         int i = 0;
1562
1563         while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1564                 i++;
1565
1566         if (i == NUM_TOTAL_PLL_TABLE) {
1567                 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1568         } else {
1569                 switch (viaparinfo->chip_info->gfx_chip_name) {
1570                 case UNICHROME_CLE266:
1571                 case UNICHROME_K400:
1572                         value = cle266_encode_pll(pll_value[i].cle266_pll);
1573                         break;
1574
1575                 case UNICHROME_K800:
1576                 case UNICHROME_PM800:
1577                 case UNICHROME_CN700:
1578                         value = k800_encode_pll(pll_value[i].k800_pll);
1579                         break;
1580
1581                 case UNICHROME_CX700:
1582                 case UNICHROME_CN750:
1583                 case UNICHROME_K8M890:
1584                 case UNICHROME_P4M890:
1585                 case UNICHROME_P4M900:
1586                 case UNICHROME_VX800:
1587                         value = k800_encode_pll(pll_value[i].cx700_pll);
1588                         break;
1589
1590                 case UNICHROME_VX855:
1591                         value = vx855_encode_pll(pll_value[i].vx855_pll);
1592                         break;
1593                 }
1594         }
1595
1596         return value;
1597 }
1598
1599 /* Set VCLK*/
1600 void viafb_set_vclock(u32 clk, int set_iga)
1601 {
1602         /* H.W. Reset : ON */
1603         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1604
1605         if (set_iga == IGA1) {
1606                 /* Change D,N FOR VCLK */
1607                 switch (viaparinfo->chip_info->gfx_chip_name) {
1608                 case UNICHROME_CLE266:
1609                 case UNICHROME_K400:
1610                         via_write_reg(VIASR, SR46, (clk & 0x00FF));
1611                         via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1612                         break;
1613
1614                 case UNICHROME_K800:
1615                 case UNICHROME_PM800:
1616                 case UNICHROME_CN700:
1617                 case UNICHROME_CX700:
1618                 case UNICHROME_CN750:
1619                 case UNICHROME_K8M890:
1620                 case UNICHROME_P4M890:
1621                 case UNICHROME_P4M900:
1622                 case UNICHROME_VX800:
1623                 case UNICHROME_VX855:
1624                         via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1625                         via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1626                         via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1627                         break;
1628                 }
1629         }
1630
1631         if (set_iga == IGA2) {
1632                 /* Change D,N FOR LCK */
1633                 switch (viaparinfo->chip_info->gfx_chip_name) {
1634                 case UNICHROME_CLE266:
1635                 case UNICHROME_K400:
1636                         via_write_reg(VIASR, SR44, (clk & 0x00FF));
1637                         via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1638                         break;
1639
1640                 case UNICHROME_K800:
1641                 case UNICHROME_PM800:
1642                 case UNICHROME_CN700:
1643                 case UNICHROME_CX700:
1644                 case UNICHROME_CN750:
1645                 case UNICHROME_K8M890:
1646                 case UNICHROME_P4M890:
1647                 case UNICHROME_P4M900:
1648                 case UNICHROME_VX800:
1649                 case UNICHROME_VX855:
1650                         via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1651                         via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1652                         via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1653                         break;
1654                 }
1655         }
1656
1657         /* H.W. Reset : OFF */
1658         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1659
1660         /* Reset PLL */
1661         if (set_iga == IGA1) {
1662                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1663                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1664         }
1665
1666         if (set_iga == IGA2) {
1667                 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1668                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1669         }
1670
1671         /* Fire! */
1672         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1673 }
1674
1675 void viafb_load_crtc_timing(struct display_timing device_timing,
1676         int set_iga)
1677 {
1678         int i;
1679         int viafb_load_reg_num = 0;
1680         int reg_value = 0;
1681         struct io_register *reg = NULL;
1682
1683         viafb_unlock_crt();
1684
1685         for (i = 0; i < 12; i++) {
1686                 if (set_iga == IGA1) {
1687                         switch (i) {
1688                         case H_TOTAL_INDEX:
1689                                 reg_value =
1690                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1691                                                            hor_total);
1692                                 viafb_load_reg_num =
1693                                         iga1_crtc_reg.hor_total.reg_num;
1694                                 reg = iga1_crtc_reg.hor_total.reg;
1695                                 break;
1696                         case H_ADDR_INDEX:
1697                                 reg_value =
1698                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1699                                                           hor_addr);
1700                                 viafb_load_reg_num =
1701                                         iga1_crtc_reg.hor_addr.reg_num;
1702                                 reg = iga1_crtc_reg.hor_addr.reg;
1703                                 break;
1704                         case H_BLANK_START_INDEX:
1705                                 reg_value =
1706                                     IGA1_HOR_BLANK_START_FORMULA
1707                                     (device_timing.hor_blank_start);
1708                                 viafb_load_reg_num =
1709                                     iga1_crtc_reg.hor_blank_start.reg_num;
1710                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1711                                 break;
1712                         case H_BLANK_END_INDEX:
1713                                 reg_value =
1714                                     IGA1_HOR_BLANK_END_FORMULA
1715                                     (device_timing.hor_blank_start,
1716                                      device_timing.hor_blank_end);
1717                                 viafb_load_reg_num =
1718                                     iga1_crtc_reg.hor_blank_end.reg_num;
1719                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1720                                 break;
1721                         case H_SYNC_START_INDEX:
1722                                 reg_value =
1723                                     IGA1_HOR_SYNC_START_FORMULA
1724                                     (device_timing.hor_sync_start);
1725                                 viafb_load_reg_num =
1726                                     iga1_crtc_reg.hor_sync_start.reg_num;
1727                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1728                                 break;
1729                         case H_SYNC_END_INDEX:
1730                                 reg_value =
1731                                     IGA1_HOR_SYNC_END_FORMULA
1732                                     (device_timing.hor_sync_start,
1733                                      device_timing.hor_sync_end);
1734                                 viafb_load_reg_num =
1735                                     iga1_crtc_reg.hor_sync_end.reg_num;
1736                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1737                                 break;
1738                         case V_TOTAL_INDEX:
1739                                 reg_value =
1740                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1741                                                            ver_total);
1742                                 viafb_load_reg_num =
1743                                         iga1_crtc_reg.ver_total.reg_num;
1744                                 reg = iga1_crtc_reg.ver_total.reg;
1745                                 break;
1746                         case V_ADDR_INDEX:
1747                                 reg_value =
1748                                     IGA1_VER_ADDR_FORMULA(device_timing.
1749                                                           ver_addr);
1750                                 viafb_load_reg_num =
1751                                         iga1_crtc_reg.ver_addr.reg_num;
1752                                 reg = iga1_crtc_reg.ver_addr.reg;
1753                                 break;
1754                         case V_BLANK_START_INDEX:
1755                                 reg_value =
1756                                     IGA1_VER_BLANK_START_FORMULA
1757                                     (device_timing.ver_blank_start);
1758                                 viafb_load_reg_num =
1759                                     iga1_crtc_reg.ver_blank_start.reg_num;
1760                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1761                                 break;
1762                         case V_BLANK_END_INDEX:
1763                                 reg_value =
1764                                     IGA1_VER_BLANK_END_FORMULA
1765                                     (device_timing.ver_blank_start,
1766                                      device_timing.ver_blank_end);
1767                                 viafb_load_reg_num =
1768                                     iga1_crtc_reg.ver_blank_end.reg_num;
1769                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1770                                 break;
1771                         case V_SYNC_START_INDEX:
1772                                 reg_value =
1773                                     IGA1_VER_SYNC_START_FORMULA
1774                                     (device_timing.ver_sync_start);
1775                                 viafb_load_reg_num =
1776                                     iga1_crtc_reg.ver_sync_start.reg_num;
1777                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1778                                 break;
1779                         case V_SYNC_END_INDEX:
1780                                 reg_value =
1781                                     IGA1_VER_SYNC_END_FORMULA
1782                                     (device_timing.ver_sync_start,
1783                                      device_timing.ver_sync_end);
1784                                 viafb_load_reg_num =
1785                                     iga1_crtc_reg.ver_sync_end.reg_num;
1786                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1787                                 break;
1788
1789                         }
1790                 }
1791
1792                 if (set_iga == IGA2) {
1793                         switch (i) {
1794                         case H_TOTAL_INDEX:
1795                                 reg_value =
1796                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1797                                                            hor_total);
1798                                 viafb_load_reg_num =
1799                                         iga2_crtc_reg.hor_total.reg_num;
1800                                 reg = iga2_crtc_reg.hor_total.reg;
1801                                 break;
1802                         case H_ADDR_INDEX:
1803                                 reg_value =
1804                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1805                                                           hor_addr);
1806                                 viafb_load_reg_num =
1807                                         iga2_crtc_reg.hor_addr.reg_num;
1808                                 reg = iga2_crtc_reg.hor_addr.reg;
1809                                 break;
1810                         case H_BLANK_START_INDEX:
1811                                 reg_value =
1812                                     IGA2_HOR_BLANK_START_FORMULA
1813                                     (device_timing.hor_blank_start);
1814                                 viafb_load_reg_num =
1815                                     iga2_crtc_reg.hor_blank_start.reg_num;
1816                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1817                                 break;
1818                         case H_BLANK_END_INDEX:
1819                                 reg_value =
1820                                     IGA2_HOR_BLANK_END_FORMULA
1821                                     (device_timing.hor_blank_start,
1822                                      device_timing.hor_blank_end);
1823                                 viafb_load_reg_num =
1824                                     iga2_crtc_reg.hor_blank_end.reg_num;
1825                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1826                                 break;
1827                         case H_SYNC_START_INDEX:
1828                                 reg_value =
1829                                     IGA2_HOR_SYNC_START_FORMULA
1830                                     (device_timing.hor_sync_start);
1831                                 if (UNICHROME_CN700 <=
1832                                         viaparinfo->chip_info->gfx_chip_name)
1833                                         viafb_load_reg_num =
1834                                             iga2_crtc_reg.hor_sync_start.
1835                                             reg_num;
1836                                 else
1837                                         viafb_load_reg_num = 3;
1838                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1839                                 break;
1840                         case H_SYNC_END_INDEX:
1841                                 reg_value =
1842                                     IGA2_HOR_SYNC_END_FORMULA
1843                                     (device_timing.hor_sync_start,
1844                                      device_timing.hor_sync_end);
1845                                 viafb_load_reg_num =
1846                                     iga2_crtc_reg.hor_sync_end.reg_num;
1847                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1848                                 break;
1849                         case V_TOTAL_INDEX:
1850                                 reg_value =
1851                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1852                                                            ver_total);
1853                                 viafb_load_reg_num =
1854                                         iga2_crtc_reg.ver_total.reg_num;
1855                                 reg = iga2_crtc_reg.ver_total.reg;
1856                                 break;
1857                         case V_ADDR_INDEX:
1858                                 reg_value =
1859                                     IGA2_VER_ADDR_FORMULA(device_timing.
1860                                                           ver_addr);
1861                                 viafb_load_reg_num =
1862                                         iga2_crtc_reg.ver_addr.reg_num;
1863                                 reg = iga2_crtc_reg.ver_addr.reg;
1864                                 break;
1865                         case V_BLANK_START_INDEX:
1866                                 reg_value =
1867                                     IGA2_VER_BLANK_START_FORMULA
1868                                     (device_timing.ver_blank_start);
1869                                 viafb_load_reg_num =
1870                                     iga2_crtc_reg.ver_blank_start.reg_num;
1871                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1872                                 break;
1873                         case V_BLANK_END_INDEX:
1874                                 reg_value =
1875                                     IGA2_VER_BLANK_END_FORMULA
1876                                     (device_timing.ver_blank_start,
1877                                      device_timing.ver_blank_end);
1878                                 viafb_load_reg_num =
1879                                     iga2_crtc_reg.ver_blank_end.reg_num;
1880                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1881                                 break;
1882                         case V_SYNC_START_INDEX:
1883                                 reg_value =
1884                                     IGA2_VER_SYNC_START_FORMULA
1885                                     (device_timing.ver_sync_start);
1886                                 viafb_load_reg_num =
1887                                     iga2_crtc_reg.ver_sync_start.reg_num;
1888                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1889                                 break;
1890                         case V_SYNC_END_INDEX:
1891                                 reg_value =
1892                                     IGA2_VER_SYNC_END_FORMULA
1893                                     (device_timing.ver_sync_start,
1894                                      device_timing.ver_sync_end);
1895                                 viafb_load_reg_num =
1896                                     iga2_crtc_reg.ver_sync_end.reg_num;
1897                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1898                                 break;
1899
1900                         }
1901                 }
1902                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1903         }
1904
1905         viafb_lock_crt();
1906 }
1907
1908 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1909         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1910 {
1911         struct display_timing crt_reg;
1912         int i;
1913         int index = 0;
1914         int h_addr, v_addr;
1915         u32 pll_D_N;
1916         u8 polarity = 0;
1917
1918         for (i = 0; i < video_mode->mode_array; i++) {
1919                 index = i;
1920
1921                 if (crt_table[i].refresh_rate == viaparinfo->
1922                         crt_setting_info->refresh_rate)
1923                         break;
1924         }
1925
1926         crt_reg = crt_table[index].crtc;
1927
1928         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1929         /* So we would delete border. */
1930         if ((viafb_LCD_ON | viafb_DVI_ON)
1931             && video_mode->crtc[0].crtc.hor_addr == 640
1932             && video_mode->crtc[0].crtc.ver_addr == 480
1933             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1934                 /* The border is 8 pixels. */
1935                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1936
1937                 /* Blanking time should add left and right borders. */
1938                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1939         }
1940
1941         h_addr = crt_reg.hor_addr;
1942         v_addr = crt_reg.ver_addr;
1943
1944         /* update polarity for CRT timing */
1945         if (crt_table[index].h_sync_polarity == NEGATIVE)
1946                 polarity |= BIT6;
1947         if (crt_table[index].v_sync_polarity == NEGATIVE)
1948                 polarity |= BIT7;
1949         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1950
1951         if (set_iga == IGA1) {
1952                 viafb_unlock_crt();
1953                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1954                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1955                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1956         }
1957
1958         switch (set_iga) {
1959         case IGA1:
1960                 viafb_load_crtc_timing(crt_reg, IGA1);
1961                 break;
1962         case IGA2:
1963                 viafb_load_crtc_timing(crt_reg, IGA2);
1964                 break;
1965         }
1966
1967         load_fix_bit_crtc_reg();
1968         viafb_lock_crt();
1969         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1970         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1971
1972         /* load FIFO */
1973         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1974             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1975                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1976
1977         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1978         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1979         viafb_set_vclock(pll_D_N, set_iga);
1980
1981 }
1982
1983 void __devinit viafb_init_chip_info(int chip_type)
1984 {
1985         init_gfx_chip_info(chip_type);
1986         init_tmds_chip_info();
1987         init_lvds_chip_info();
1988
1989         viaparinfo->crt_setting_info->iga_path = IGA1;
1990         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1991
1992         /*Set IGA path for each device */
1993         viafb_set_iga_path();
1994
1995         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1996         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1997         viaparinfo->lvds_setting_info2->display_method =
1998                 viaparinfo->lvds_setting_info->display_method;
1999         viaparinfo->lvds_setting_info2->lcd_mode =
2000                 viaparinfo->lvds_setting_info->lcd_mode;
2001 }
2002
2003 void viafb_update_device_setting(int hres, int vres,
2004         int bpp, int vmode_refresh, int flag)
2005 {
2006         if (flag == 0) {
2007                 viaparinfo->crt_setting_info->h_active = hres;
2008                 viaparinfo->crt_setting_info->v_active = vres;
2009                 viaparinfo->crt_setting_info->bpp = bpp;
2010                 viaparinfo->crt_setting_info->refresh_rate =
2011                         vmode_refresh;
2012
2013                 viaparinfo->tmds_setting_info->h_active = hres;
2014                 viaparinfo->tmds_setting_info->v_active = vres;
2015
2016                 viaparinfo->lvds_setting_info->h_active = hres;
2017                 viaparinfo->lvds_setting_info->v_active = vres;
2018                 viaparinfo->lvds_setting_info->bpp = bpp;
2019                 viaparinfo->lvds_setting_info->refresh_rate =
2020                         vmode_refresh;
2021                 viaparinfo->lvds_setting_info2->h_active = hres;
2022                 viaparinfo->lvds_setting_info2->v_active = vres;
2023                 viaparinfo->lvds_setting_info2->bpp = bpp;
2024                 viaparinfo->lvds_setting_info2->refresh_rate =
2025                         vmode_refresh;
2026         } else {
2027
2028                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
2029                         viaparinfo->tmds_setting_info->h_active = hres;
2030                         viaparinfo->tmds_setting_info->v_active = vres;
2031                 }
2032
2033                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
2034                         viaparinfo->lvds_setting_info->h_active = hres;
2035                         viaparinfo->lvds_setting_info->v_active = vres;
2036                         viaparinfo->lvds_setting_info->bpp = bpp;
2037                         viaparinfo->lvds_setting_info->refresh_rate =
2038                                 vmode_refresh;
2039                 }
2040                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2041                         viaparinfo->lvds_setting_info2->h_active = hres;
2042                         viaparinfo->lvds_setting_info2->v_active = vres;
2043                         viaparinfo->lvds_setting_info2->bpp = bpp;
2044                         viaparinfo->lvds_setting_info2->refresh_rate =
2045                                 vmode_refresh;
2046                 }
2047         }
2048 }
2049
2050 static void __devinit init_gfx_chip_info(int chip_type)
2051 {
2052         u8 tmp;
2053
2054         viaparinfo->chip_info->gfx_chip_name = chip_type;
2055
2056         /* Check revision of CLE266 Chip */
2057         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2058                 /* CR4F only define in CLE266.CX chip */
2059                 tmp = viafb_read_reg(VIACR, CR4F);
2060                 viafb_write_reg(CR4F, VIACR, 0x55);
2061                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2062                         viaparinfo->chip_info->gfx_chip_revision =
2063                         CLE266_REVISION_AX;
2064                 else
2065                         viaparinfo->chip_info->gfx_chip_revision =
2066                         CLE266_REVISION_CX;
2067                 /* restore orignal CR4F value */
2068                 viafb_write_reg(CR4F, VIACR, tmp);
2069         }
2070
2071         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2072                 tmp = viafb_read_reg(VIASR, SR43);
2073                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2074                 if (tmp & 0x02) {
2075                         viaparinfo->chip_info->gfx_chip_revision =
2076                                 CX700_REVISION_700M2;
2077                 } else if (tmp & 0x40) {
2078                         viaparinfo->chip_info->gfx_chip_revision =
2079                                 CX700_REVISION_700M;
2080                 } else {
2081                         viaparinfo->chip_info->gfx_chip_revision =
2082                                 CX700_REVISION_700;
2083                 }
2084         }
2085
2086         /* Determine which 2D engine we have */
2087         switch (viaparinfo->chip_info->gfx_chip_name) {
2088         case UNICHROME_VX800:
2089         case UNICHROME_VX855:
2090                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2091                 break;
2092         case UNICHROME_K8M890:
2093         case UNICHROME_P4M900:
2094                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2095                 break;
2096         default:
2097                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2098                 break;
2099         }
2100 }
2101
2102 static void __devinit init_tmds_chip_info(void)
2103 {
2104         viafb_tmds_trasmitter_identify();
2105
2106         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2107                 output_interface) {
2108                 switch (viaparinfo->chip_info->gfx_chip_name) {
2109                 case UNICHROME_CX700:
2110                         {
2111                                 /* we should check support by hardware layout.*/
2112                                 if ((viafb_display_hardware_layout ==
2113                                      HW_LAYOUT_DVI_ONLY)
2114                                     || (viafb_display_hardware_layout ==
2115                                         HW_LAYOUT_LCD_DVI)) {
2116                                         viaparinfo->chip_info->tmds_chip_info.
2117                                             output_interface = INTERFACE_TMDS;
2118                                 } else {
2119                                         viaparinfo->chip_info->tmds_chip_info.
2120                                                 output_interface =
2121                                                 INTERFACE_NONE;
2122                                 }
2123                                 break;
2124                         }
2125                 case UNICHROME_K8M890:
2126                 case UNICHROME_P4M900:
2127                 case UNICHROME_P4M890:
2128                         /* TMDS on PCIE, we set DFPLOW as default. */
2129                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2130                             INTERFACE_DFP_LOW;
2131                         break;
2132                 default:
2133                         {
2134                                 /* set DVP1 default for DVI */
2135                                 viaparinfo->chip_info->tmds_chip_info
2136                                 .output_interface = INTERFACE_DVP1;
2137                         }
2138                 }
2139         }
2140
2141         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2142                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2143         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2144                 &viaparinfo->shared->tmds_setting_info);
2145 }
2146
2147 static void __devinit init_lvds_chip_info(void)
2148 {
2149         viafb_lvds_trasmitter_identify();
2150         viafb_init_lcd_size();
2151         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2152                                    viaparinfo->lvds_setting_info);
2153         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2154                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2155                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2156         }
2157         /*If CX700,two singel LCD, we need to reassign
2158            LCD interface to different LVDS port */
2159         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2160             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2161                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2162                         lvds_chip_name) && (INTEGRATED_LVDS ==
2163                         viaparinfo->chip_info->
2164                         lvds_chip_info2.lvds_chip_name)) {
2165                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2166                                 INTERFACE_LVDS0;
2167                         viaparinfo->chip_info->lvds_chip_info2.
2168                                 output_interface =
2169                             INTERFACE_LVDS1;
2170                 }
2171         }
2172
2173         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2174                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2175         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2176                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2177         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2178                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2179 }
2180
2181 void __devinit viafb_init_dac(int set_iga)
2182 {
2183         int i;
2184         u8 tmp;
2185
2186         if (set_iga == IGA1) {
2187                 /* access Primary Display's LUT */
2188                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2189                 /* turn off LCK */
2190                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2191                 for (i = 0; i < 256; i++) {
2192                         write_dac_reg(i, palLUT_table[i].red,
2193                                       palLUT_table[i].green,
2194                                       palLUT_table[i].blue);
2195                 }
2196                 /* turn on LCK */
2197                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2198         } else {
2199                 tmp = viafb_read_reg(VIACR, CR6A);
2200                 /* access Secondary Display's LUT */
2201                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2202                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2203                 for (i = 0; i < 256; i++) {
2204                         write_dac_reg(i, palLUT_table[i].red,
2205                                       palLUT_table[i].green,
2206                                       palLUT_table[i].blue);
2207                 }
2208                 /* set IGA1 DAC for default */
2209                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2210                 viafb_write_reg(CR6A, VIACR, tmp);
2211         }
2212 }
2213
2214 static void device_screen_off(void)
2215 {
2216         /* turn off CRT screen (IGA1) */
2217         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2218 }
2219
2220 static void device_screen_on(void)
2221 {
2222         /* turn on CRT screen (IGA1) */
2223         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2224 }
2225
2226 static void set_display_channel(void)
2227 {
2228         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2229         is keeped on lvds_setting_info2 */
2230         if (viafb_LCD2_ON &&
2231                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2232                 /* For dual channel LCD: */
2233                 /* Set to Dual LVDS channel. */
2234                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2235         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2236                 /* For LCD+DFP: */
2237                 /* Set to LVDS1 + TMDS channel. */
2238                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2239         } else if (viafb_DVI_ON) {
2240                 /* Set to single TMDS channel. */
2241                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2242         } else if (viafb_LCD_ON) {
2243                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2244                         /* For dual channel LCD: */
2245                         /* Set to Dual LVDS channel. */
2246                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2247                 } else {
2248                         /* Set to LVDS0 + LVDS1 channel. */
2249                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2250                 }
2251         }
2252 }
2253
2254 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2255         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2256 {
2257         int i, j;
2258         int port;
2259         u8 value, index, mask;
2260         struct crt_mode_table *crt_timing;
2261         struct crt_mode_table *crt_timing1 = NULL;
2262
2263         device_screen_off();
2264         crt_timing = vmode_tbl->crtc;
2265
2266         if (viafb_SAMM_ON == 1) {
2267                 crt_timing1 = vmode_tbl1->crtc;
2268         }
2269
2270         inb(VIAStatus);
2271         outb(0x00, VIAAR);
2272
2273         /* Write Common Setting for Video Mode */
2274         switch (viaparinfo->chip_info->gfx_chip_name) {
2275         case UNICHROME_CLE266:
2276                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2277                 break;
2278
2279         case UNICHROME_K400:
2280                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2281                 break;
2282
2283         case UNICHROME_K800:
2284         case UNICHROME_PM800:
2285                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2286                 break;
2287
2288         case UNICHROME_CN700:
2289         case UNICHROME_K8M890:
2290         case UNICHROME_P4M890:
2291         case UNICHROME_P4M900:
2292                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2293                 break;
2294
2295         case UNICHROME_CX700:
2296         case UNICHROME_VX800:
2297                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2298                 break;
2299
2300         case UNICHROME_VX855:
2301                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2302                 break;
2303         }
2304
2305         device_off();
2306
2307         /* Fill VPIT Parameters */
2308         /* Write Misc Register */
2309         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2310
2311         /* Write Sequencer */
2312         for (i = 1; i <= StdSR; i++)
2313                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2314
2315         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2316
2317         /* Write CRTC */
2318         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2319
2320         /* Write Graphic Controller */
2321         for (i = 0; i < StdGR; i++)
2322                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2323
2324         /* Write Attribute Controller */
2325         for (i = 0; i < StdAR; i++) {
2326                 inb(VIAStatus);
2327                 outb(i, VIAAR);
2328                 outb(VPIT.AR[i], VIAAR);
2329         }
2330
2331         inb(VIAStatus);
2332         outb(0x20, VIAAR);
2333
2334         /* Update Patch Register */
2335
2336         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2337             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2338             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2339             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2340                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2341                         index = res_patch_table[0].io_reg_table[j].index;
2342                         port = res_patch_table[0].io_reg_table[j].port;
2343                         value = res_patch_table[0].io_reg_table[j].value;
2344                         mask = res_patch_table[0].io_reg_table[j].mask;
2345                         viafb_write_reg_mask(index, port, value, mask);
2346                 }
2347         }
2348
2349         via_set_primary_pitch(viafbinfo->fix.line_length);
2350         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2351                 : viafbinfo->fix.line_length);
2352         via_set_primary_color_depth(viaparinfo->depth);
2353         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2354                 : viaparinfo->depth);
2355         /* Update Refresh Rate Setting */
2356
2357         /* Clear On Screen */
2358
2359         /* CRT set mode */
2360         if (viafb_CRT_ON) {
2361                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2362                         IGA2)) {
2363                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2364                                 video_bpp1 / 8,
2365                                 viaparinfo->crt_setting_info->iga_path);
2366                 } else {
2367                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2368                                 video_bpp / 8,
2369                                 viaparinfo->crt_setting_info->iga_path);
2370                 }
2371
2372                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2373                 to 8 alignment (1368),there is several pixels (2 pixels)
2374                 on right side of screen. */
2375                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2376                         viafb_unlock_crt();
2377                         viafb_write_reg(CR02, VIACR,
2378                                 viafb_read_reg(VIACR, CR02) - 1);
2379                         viafb_lock_crt();
2380                 }
2381
2382                 viafb_set_output_path(DEVICE_CRT,
2383                         viaparinfo->crt_setting_info->iga_path, 0);
2384         }
2385
2386         if (viafb_DVI_ON) {
2387                 if (viafb_SAMM_ON &&
2388                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2389                         viafb_dvi_set_mode(viafb_get_mode
2390                                      (viaparinfo->tmds_setting_info->h_active,
2391                                       viaparinfo->tmds_setting_info->
2392                                       v_active),
2393                                      video_bpp1, viaparinfo->
2394                                      tmds_setting_info->iga_path);
2395                 } else {
2396                         viafb_dvi_set_mode(viafb_get_mode
2397                                      (viaparinfo->tmds_setting_info->h_active,
2398                                       viaparinfo->
2399                                       tmds_setting_info->v_active),
2400                                      video_bpp, viaparinfo->
2401                                      tmds_setting_info->iga_path);
2402                 }
2403
2404                 viafb_set_output_path(DEVICE_DVI,
2405                         viaparinfo->tmds_setting_info->iga_path,
2406                         viaparinfo->chip_info->tmds_chip_info.output_interface);
2407         }
2408
2409         if (viafb_LCD_ON) {
2410                 if (viafb_SAMM_ON &&
2411                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2412                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2413                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2414                                 lvds_setting_info,
2415                                      &viaparinfo->chip_info->lvds_chip_info);
2416                 } else {
2417                         /* IGA1 doesn't have LCD scaling, so set it center. */
2418                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2419                                 viaparinfo->lvds_setting_info->display_method =
2420                                     LCD_CENTERING;
2421                         }
2422                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2423                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2424                                 lvds_setting_info,
2425                                      &viaparinfo->chip_info->lvds_chip_info);
2426                 }
2427
2428                 viafb_set_output_path(DEVICE_LCD,
2429                         viaparinfo->lvds_setting_info->iga_path,
2430                         viaparinfo->chip_info->
2431                         lvds_chip_info.output_interface);
2432         }
2433         if (viafb_LCD2_ON) {
2434                 if (viafb_SAMM_ON &&
2435                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2436                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2437                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2438                                 lvds_setting_info2,
2439                                      &viaparinfo->chip_info->lvds_chip_info2);
2440                 } else {
2441                         /* IGA1 doesn't have LCD scaling, so set it center. */
2442                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2443                                 viaparinfo->lvds_setting_info2->display_method =
2444                                     LCD_CENTERING;
2445                         }
2446                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2447                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2448                                 lvds_setting_info2,
2449                                      &viaparinfo->chip_info->lvds_chip_info2);
2450                 }
2451
2452                 viafb_set_output_path(DEVICE_LCD,
2453                         viaparinfo->lvds_setting_info2->iga_path,
2454                         viaparinfo->chip_info->
2455                         lvds_chip_info2.output_interface);
2456         }
2457
2458         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2459             && (viafb_LCD_ON || viafb_DVI_ON))
2460                 set_display_channel();
2461
2462         /* If set mode normally, save resolution information for hot-plug . */
2463         if (!viafb_hotplug) {
2464                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2465                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2466                 viafb_hotplug_bpp = video_bpp;
2467                 viafb_hotplug_refresh = viafb_refresh;
2468
2469                 if (viafb_DVI_ON)
2470                         viafb_DeviceStatus = DVI_Device;
2471                 else
2472                         viafb_DeviceStatus = CRT_Device;
2473         }
2474         device_on();
2475         device_screen_on();
2476         return 1;
2477 }
2478
2479 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2480 {
2481         int i;
2482
2483         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2484                 if ((hres == res_map_refresh_tbl[i].hres)
2485                     && (vres == res_map_refresh_tbl[i].vres)
2486                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2487                         return res_map_refresh_tbl[i].pixclock;
2488         }
2489         return RES_640X480_60HZ_PIXCLOCK;
2490
2491 }
2492
2493 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2494 {
2495 #define REFRESH_TOLERANCE 3
2496         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2497         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2498                 if ((hres == res_map_refresh_tbl[i].hres)
2499                     && (vres == res_map_refresh_tbl[i].vres)
2500                     && (diff > (abs(long_refresh -
2501                     res_map_refresh_tbl[i].vmode_refresh)))) {
2502                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2503                                 vmode_refresh);
2504                         nearest = i;
2505                 }
2506         }
2507 #undef REFRESH_TOLERANCE
2508         if (nearest > 0)
2509                 return res_map_refresh_tbl[nearest].vmode_refresh;
2510         return 60;
2511 }
2512
2513 static void device_off(void)
2514 {
2515         viafb_crt_disable();
2516         viafb_dvi_disable();
2517         viafb_lcd_disable();
2518 }
2519
2520 static void device_on(void)
2521 {
2522         if (viafb_CRT_ON == 1)
2523                 viafb_crt_enable();
2524         if (viafb_DVI_ON == 1)
2525                 viafb_dvi_enable();
2526         if (viafb_LCD_ON == 1)
2527                 viafb_lcd_enable();
2528 }
2529
2530 void viafb_crt_disable(void)
2531 {
2532         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2533 }
2534
2535 void viafb_crt_enable(void)
2536 {
2537         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2538 }
2539
2540 static void enable_second_display_channel(void)
2541 {
2542         /* to enable second display channel. */
2543         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2544         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2545         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2546 }
2547
2548 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2549                                         *p_gfx_dpa_setting)
2550 {
2551         switch (output_interface) {
2552         case INTERFACE_DVP0:
2553                 {
2554                         /* DVP0 Clock Polarity and Adjust: */
2555                         viafb_write_reg_mask(CR96, VIACR,
2556                                        p_gfx_dpa_setting->DVP0, 0x0F);
2557
2558                         /* DVP0 Clock and Data Pads Driving: */
2559                         viafb_write_reg_mask(SR1E, VIASR,
2560                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2561                         viafb_write_reg_mask(SR2A, VIASR,
2562                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2563                                        BIT4);
2564                         viafb_write_reg_mask(SR1B, VIASR,
2565                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2566                         viafb_write_reg_mask(SR2A, VIASR,
2567                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2568                         break;
2569                 }
2570
2571         case INTERFACE_DVP1:
2572                 {
2573                         /* DVP1 Clock Polarity and Adjust: */
2574                         viafb_write_reg_mask(CR9B, VIACR,
2575                                        p_gfx_dpa_setting->DVP1, 0x0F);
2576
2577                         /* DVP1 Clock and Data Pads Driving: */
2578                         viafb_write_reg_mask(SR65, VIASR,
2579                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2580                         break;
2581                 }
2582
2583         case INTERFACE_DFP_HIGH:
2584                 {
2585                         viafb_write_reg_mask(CR97, VIACR,
2586                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2587                         break;
2588                 }
2589
2590         case INTERFACE_DFP_LOW:
2591                 {
2592                         viafb_write_reg_mask(CR99, VIACR,
2593                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2594                         break;
2595                 }
2596
2597         case INTERFACE_DFP:
2598                 {
2599                         viafb_write_reg_mask(CR97, VIACR,
2600                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2601                         viafb_write_reg_mask(CR99, VIACR,
2602                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2603                         break;
2604                 }
2605         }
2606 }
2607
2608 /*According var's xres, yres fill var's other timing information*/
2609 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2610         struct VideoModeTable *vmode_tbl)
2611 {
2612         struct crt_mode_table *crt_timing = NULL;
2613         struct display_timing crt_reg;
2614         int i = 0, index = 0;
2615         crt_timing = vmode_tbl->crtc;
2616         for (i = 0; i < vmode_tbl->mode_array; i++) {
2617                 index = i;
2618                 if (crt_timing[i].refresh_rate == refresh)
2619                         break;
2620         }
2621
2622         crt_reg = crt_timing[index].crtc;
2623         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2624         var->left_margin =
2625             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2626         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2627         var->hsync_len = crt_reg.hor_sync_end;
2628         var->upper_margin =
2629             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2630         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2631         var->vsync_len = crt_reg.ver_sync_end;
2632 }