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1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 #ifndef __HW_H__
23 #define __HW_H__
24
25 #include <linux/seq_file.h>
26
27 #include "viamode.h"
28 #include "global.h"
29 #include "via_modesetting.h"
30
31 #define viafb_read_reg(p, i)                    via_read_reg(p, i)
32 #define viafb_write_reg(i, p, d)                via_write_reg(p, i, d)
33 #define viafb_write_reg_mask(i, p, d, m)        via_write_reg_mask(p, i, d, m)
34
35 /* VIA output devices */
36 #define VIA_6C          0x00000001
37 #define VIA_93          0x00000002
38 #define VIA_96          0x00000004
39 #define VIA_CRT         0x00000010
40 #define VIA_DVP1        0x00000020
41 #define VIA_LVDS1       0x00000040
42 #define VIA_LVDS2       0x00000080
43
44 /***************************************************
45 * Definition IGA1 Design Method of CRTC Registers *
46 ****************************************************/
47 #define IGA1_HOR_TOTAL_FORMULA(x)           (((x)/8)-5)
48 #define IGA1_HOR_ADDR_FORMULA(x)            (((x)/8)-1)
49 #define IGA1_HOR_BLANK_START_FORMULA(x)     (((x)/8)-1)
50 #define IGA1_HOR_BLANK_END_FORMULA(x, y)     (((x+y)/8)-1)
51 #define IGA1_HOR_SYNC_START_FORMULA(x)      ((x)/8)
52 #define IGA1_HOR_SYNC_END_FORMULA(x, y)      ((x+y)/8)
53
54 #define IGA1_VER_TOTAL_FORMULA(x)           ((x)-2)
55 #define IGA1_VER_ADDR_FORMULA(x)            ((x)-1)
56 #define IGA1_VER_BLANK_START_FORMULA(x)     ((x)-1)
57 #define IGA1_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
58 #define IGA1_VER_SYNC_START_FORMULA(x)      ((x)-1)
59 #define IGA1_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
60
61 /***************************************************
62 ** Definition IGA2 Design Method of CRTC Registers *
63 ****************************************************/
64 #define IGA2_HOR_TOTAL_FORMULA(x)           ((x)-1)
65 #define IGA2_HOR_ADDR_FORMULA(x)            ((x)-1)
66 #define IGA2_HOR_BLANK_START_FORMULA(x)     ((x)-1)
67 #define IGA2_HOR_BLANK_END_FORMULA(x, y)     ((x+y)-1)
68 #define IGA2_HOR_SYNC_START_FORMULA(x)      ((x)-1)
69 #define IGA2_HOR_SYNC_END_FORMULA(x, y)      ((x+y)-1)
70
71 #define IGA2_VER_TOTAL_FORMULA(x)           ((x)-1)
72 #define IGA2_VER_ADDR_FORMULA(x)            ((x)-1)
73 #define IGA2_VER_BLANK_START_FORMULA(x)     ((x)-1)
74 #define IGA2_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
75 #define IGA2_VER_SYNC_START_FORMULA(x)      ((x)-1)
76 #define IGA2_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
77
78 /**********************************************************/
79 /* Definition IGA2 Design Method of CRTC Shadow Registers */
80 /**********************************************************/
81 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           ((x/8)-5)
82 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y)     (((x+y)/8)-1)
83 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           ((x)-2)
84 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            ((x)-1)
85 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     ((x)-1)
86 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y)     ((x+y)-1)
87 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
88 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y)      (x+y)
89
90 /* Define Register Number for IGA1 CRTC Timing */
91
92 /* location: {CR00,0,7},{CR36,3,3} */
93 #define IGA1_HOR_TOTAL_REG_NUM          2
94 /* location: {CR01,0,7} */
95 #define IGA1_HOR_ADDR_REG_NUM           1
96 /* location: {CR02,0,7} */
97 #define IGA1_HOR_BLANK_START_REG_NUM    1
98 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
99 #define IGA1_HOR_BLANK_END_REG_NUM      3
100 /* location: {CR04,0,7},{CR33,4,4} */
101 #define IGA1_HOR_SYNC_START_REG_NUM     2
102 /* location: {CR05,0,4} */
103 #define IGA1_HOR_SYNC_END_REG_NUM       1
104 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
105 #define IGA1_VER_TOTAL_REG_NUM          4
106 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
107 #define IGA1_VER_ADDR_REG_NUM           4
108 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
109 #define IGA1_VER_BLANK_START_REG_NUM    4
110 /* location: {CR16,0,7} */
111 #define IGA1_VER_BLANK_END_REG_NUM      1
112 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
113 #define IGA1_VER_SYNC_START_REG_NUM     4
114 /* location: {CR11,0,3} */
115 #define IGA1_VER_SYNC_END_REG_NUM       1
116
117 /* Define Register Number for IGA2 Shadow CRTC Timing */
118
119 /* location: {CR6D,0,7},{CR71,3,3} */
120 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2
121 /* location: {CR6E,0,7} */
122 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1
123 /* location: {CR6F,0,7},{CR71,0,2} */
124 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2
125 /* location: {CR70,0,7},{CR71,4,6} */
126 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2
127 /* location: {CR72,0,7},{CR74,4,6} */
128 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
129 /* location: {CR73,0,7},{CR74,0,2} */
130 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2
131 /* location: {CR75,0,7},{CR76,4,6} */
132 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2
133 /* location: {CR76,0,3} */
134 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1
135
136 /* Define Register Number for IGA2 CRTC Timing */
137
138 /* location: {CR50,0,7},{CR55,0,3} */
139 #define IGA2_HOR_TOTAL_REG_NUM          2
140 /* location: {CR51,0,7},{CR55,4,6} */
141 #define IGA2_HOR_ADDR_REG_NUM           2
142 /* location: {CR52,0,7},{CR54,0,2} */
143 #define IGA2_HOR_BLANK_START_REG_NUM    2
144 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
145 is reserved, so it may have problem to set 1600x1200 on IGA2. */
146 /*              Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
147 #define IGA2_HOR_BLANK_END_REG_NUM      3
148 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
149 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
150 #define IGA2_HOR_SYNC_START_REG_NUM     4
151
152 /* location: {CR57,0,7},{CR5C,6,6} */
153 #define IGA2_HOR_SYNC_END_REG_NUM       2
154 /* location: {CR58,0,7},{CR5D,0,2} */
155 #define IGA2_VER_TOTAL_REG_NUM          2
156 /* location: {CR59,0,7},{CR5D,3,5} */
157 #define IGA2_VER_ADDR_REG_NUM           2
158 /* location: {CR5A,0,7},{CR5C,0,2} */
159 #define IGA2_VER_BLANK_START_REG_NUM    2
160 /* location: {CR5E,0,7},{CR5C,3,5} */
161 #define IGA2_VER_BLANK_END_REG_NUM      2
162 /* location: {CR5E,0,7},{CR5F,5,7} */
163 #define IGA2_VER_SYNC_START_REG_NUM     2
164 /* location: {CR5F,0,4} */
165 #define IGA2_VER_SYNC_END_REG_NUM       1
166
167 /* Define Fetch Count Register*/
168
169 /* location: {SR1C,0,7},{SR1D,0,1} */
170 #define IGA1_FETCH_COUNT_REG_NUM        2
171 /* 16 bytes alignment. */
172 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16
173 /* x: H resolution, y: color depth */
174 #define IGA1_FETCH_COUNT_PATCH_VALUE    4
175 #define IGA1_FETCH_COUNT_FORMULA(x, y)   \
176         (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
177
178 /* location: {CR65,0,7},{CR67,2,3} */
179 #define IGA2_FETCH_COUNT_REG_NUM        2
180 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
181 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
182 #define IGA2_FETCH_COUNT_FORMULA(x, y)   \
183         (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
184
185 /* Staring Address*/
186
187 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
188 #define IGA1_STARTING_ADDR_REG_NUM      4
189 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
190 #define IGA2_STARTING_ADDR_REG_NUM      3
191
192 /* Define Display OFFSET*/
193 /* These value are by HW suggested value*/
194 /* location: {SR17,0,7} */
195 #define K800_IGA1_FIFO_MAX_DEPTH                384
196 /* location: {SR16,0,5},{SR16,7,7} */
197 #define K800_IGA1_FIFO_THRESHOLD                328
198 /* location: {SR18,0,5},{SR18,7,7} */
199 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296
200 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
201                                 /* because HW only 5 bits */
202 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
203
204 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
205 #define K800_IGA2_FIFO_MAX_DEPTH                384
206 /* location: {CR68,0,3},{CR95,4,6} */
207 #define K800_IGA2_FIFO_THRESHOLD                328
208 /* location: {CR92,0,3},{CR95,0,2} */
209 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296
210 /* location: {CR94,0,6} */
211 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
212
213 /* location: {SR17,0,7} */
214 #define P880_IGA1_FIFO_MAX_DEPTH                192
215 /* location: {SR16,0,5},{SR16,7,7} */
216 #define P880_IGA1_FIFO_THRESHOLD                128
217 /* location: {SR18,0,5},{SR18,7,7} */
218 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64
219 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
220                                 /* because HW only 5 bits */
221 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
222
223 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
224 #define P880_IGA2_FIFO_MAX_DEPTH                96
225 /* location: {CR68,0,3},{CR95,4,6} */
226 #define P880_IGA2_FIFO_THRESHOLD                64
227 /* location: {CR92,0,3},{CR95,0,2} */
228 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32
229 /* location: {CR94,0,6} */
230 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
231
232 /* VT3314 chipset*/
233
234 /* location: {SR17,0,7} */
235 #define CN700_IGA1_FIFO_MAX_DEPTH               96
236 /* location: {SR16,0,5},{SR16,7,7} */
237 #define CN700_IGA1_FIFO_THRESHOLD               80
238 /* location: {SR18,0,5},{SR18,7,7} */
239 #define CN700_IGA1_FIFO_HIGH_THRESHOLD          64
240 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
241                                 because HW only 5 bits */
242 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0
243 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
244 #define CN700_IGA2_FIFO_MAX_DEPTH               96
245 /* location: {CR68,0,3},{CR95,4,6} */
246 #define CN700_IGA2_FIFO_THRESHOLD               80
247 /* location: {CR92,0,3},{CR95,0,2} */
248 #define CN700_IGA2_FIFO_HIGH_THRESHOLD          32
249 /* location: {CR94,0,6} */
250 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
251
252 /* For VT3324, these values are suggested by HW */
253 /* location: {SR17,0,7} */
254 #define CX700_IGA1_FIFO_MAX_DEPTH               192
255 /* location: {SR16,0,5},{SR16,7,7} */
256 #define CX700_IGA1_FIFO_THRESHOLD               128
257 /* location: {SR18,0,5},{SR18,7,7} */
258 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128
259 /* location: {SR22,0,4} */
260 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
261
262 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
263 #define CX700_IGA2_FIFO_MAX_DEPTH               96
264 /* location: {CR68,0,3},{CR95,4,6} */
265 #define CX700_IGA2_FIFO_THRESHOLD               64
266 /* location: {CR92,0,3},{CR95,0,2} */
267 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32
268 /* location: {CR94,0,6} */
269 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
270
271 /* VT3336 chipset*/
272 /* location: {SR17,0,7} */
273 #define K8M890_IGA1_FIFO_MAX_DEPTH               360
274 /* location: {SR16,0,5},{SR16,7,7} */
275 #define K8M890_IGA1_FIFO_THRESHOLD               328
276 /* location: {SR18,0,5},{SR18,7,7} */
277 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD          296
278 /* location: {SR22,0,4}. */
279 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
280
281 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
282 #define K8M890_IGA2_FIFO_MAX_DEPTH               360
283 /* location: {CR68,0,3},{CR95,4,6} */
284 #define K8M890_IGA2_FIFO_THRESHOLD               328
285 /* location: {CR92,0,3},{CR95,0,2} */
286 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD          296
287 /* location: {CR94,0,6} */
288 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     124
289
290 /* VT3327 chipset*/
291 /* location: {SR17,0,7} */
292 #define P4M890_IGA1_FIFO_MAX_DEPTH               96
293 /* location: {SR16,0,5},{SR16,7,7} */
294 #define P4M890_IGA1_FIFO_THRESHOLD               76
295 /* location: {SR18,0,5},{SR18,7,7} */
296 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD          64
297 /* location: {SR22,0,4}. (32/4) =8 */
298 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
299 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
300 #define P4M890_IGA2_FIFO_MAX_DEPTH               96
301 /* location: {CR68,0,3},{CR95,4,6} */
302 #define P4M890_IGA2_FIFO_THRESHOLD               76
303 /* location: {CR92,0,3},{CR95,0,2} */
304 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD          64
305 /* location: {CR94,0,6} */
306 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
307
308 /* VT3364 chipset*/
309 /* location: {SR17,0,7} */
310 #define P4M900_IGA1_FIFO_MAX_DEPTH               96
311 /* location: {SR16,0,5},{SR16,7,7} */
312 #define P4M900_IGA1_FIFO_THRESHOLD               76
313 /* location: {SR18,0,5},{SR18,7,7} */
314 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD          76
315 /* location: {SR22,0,4}. */
316 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
317 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
318 #define P4M900_IGA2_FIFO_MAX_DEPTH               96
319 /* location: {CR68,0,3},{CR95,4,6} */
320 #define P4M900_IGA2_FIFO_THRESHOLD               76
321 /* location: {CR92,0,3},{CR95,0,2} */
322 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD          76
323 /* location: {CR94,0,6} */
324 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
325
326 /* For VT3353, these values are suggested by HW */
327 /* location: {SR17,0,7} */
328 #define VX800_IGA1_FIFO_MAX_DEPTH               192
329 /* location: {SR16,0,5},{SR16,7,7} */
330 #define VX800_IGA1_FIFO_THRESHOLD               152
331 /* location: {SR18,0,5},{SR18,7,7} */
332 #define VX800_IGA1_FIFO_HIGH_THRESHOLD          152
333 /* location: {SR22,0,4} */
334 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      64
335 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
336 #define VX800_IGA2_FIFO_MAX_DEPTH               96
337 /* location: {CR68,0,3},{CR95,4,6} */
338 #define VX800_IGA2_FIFO_THRESHOLD               64
339 /* location: {CR92,0,3},{CR95,0,2} */
340 #define VX800_IGA2_FIFO_HIGH_THRESHOLD          32
341 /* location: {CR94,0,6} */
342 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
343
344 /* For VT3409 */
345 #define VX855_IGA1_FIFO_MAX_DEPTH               400
346 #define VX855_IGA1_FIFO_THRESHOLD               320
347 #define VX855_IGA1_FIFO_HIGH_THRESHOLD          320
348 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
349
350 #define VX855_IGA2_FIFO_MAX_DEPTH               200
351 #define VX855_IGA2_FIFO_THRESHOLD               160
352 #define VX855_IGA2_FIFO_HIGH_THRESHOLD          160
353 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
354
355 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
356 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
357 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
358 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
359
360 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
361 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
362 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
363 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
364
365 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)-1)
366 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
367 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
368 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
369 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   (((x/2)/4)-1)
370 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
371 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
372 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
373
374 /************************************************************************/
375 /*  LCD Timing                                                          */
376 /************************************************************************/
377
378 /* 500 ms = 500000 us */
379 #define LCD_POWER_SEQ_TD0               500000
380 /* 50 ms = 50000 us */
381 #define LCD_POWER_SEQ_TD1               50000
382 /* 0 us */
383 #define LCD_POWER_SEQ_TD2               0
384 /* 210 ms = 210000 us */
385 #define LCD_POWER_SEQ_TD3               210000
386 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
387 #define CLE266_POWER_SEQ_UNIT           71
388 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
389 #define K800_POWER_SEQ_UNIT             142
390 /* 2^13 * (1/14.31818M) = 572.1 us */
391 #define P880_POWER_SEQ_UNIT             572
392
393 #define CLE266_POWER_SEQ_FORMULA(x)     ((x)/CLE266_POWER_SEQ_UNIT)
394 #define K800_POWER_SEQ_FORMULA(x)       ((x)/K800_POWER_SEQ_UNIT)
395 #define P880_POWER_SEQ_FORMULA(x)       ((x)/P880_POWER_SEQ_UNIT)
396
397 /* location: {CR8B,0,7},{CR8F,0,3} */
398 #define LCD_POWER_SEQ_TD0_REG_NUM       2
399 /* location: {CR8C,0,7},{CR8F,4,7} */
400 #define LCD_POWER_SEQ_TD1_REG_NUM       2
401 /* location: {CR8D,0,7},{CR90,0,3} */
402 #define LCD_POWER_SEQ_TD2_REG_NUM       2
403 /* location: {CR8E,0,7},{CR90,4,7} */
404 #define LCD_POWER_SEQ_TD3_REG_NUM       2
405
406 /* LCD Scaling factor*/
407 /* x: indicate setting horizontal size*/
408 /* y: indicate panel horizontal size*/
409
410 /* Horizontal scaling factor 10 bits (2^10) */
411 #define CLE266_LCD_HOR_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
412 /* Vertical scaling factor 10 bits (2^10) */
413 #define CLE266_LCD_VER_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
414 /* Horizontal scaling factor 10 bits (2^12) */
415 #define K800_LCD_HOR_SCF_FORMULA(x, y)     (((x-1)*4096)/(y-1))
416 /* Vertical scaling factor 10 bits (2^11) */
417 #define K800_LCD_VER_SCF_FORMULA(x, y)     (((x-1)*2048)/(y-1))
418
419 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
420 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3
421 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
422 #define LCD_VER_SCALING_FACTOR_REG_NUM  3
423 /* location: {CR77,0,7},{CR79,4,5} */
424 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2
425 /* location: {CR78,0,7},{CR79,6,7} */
426 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2
427
428 /************************************************
429  *****     Define IGA1 Display Timing       *****
430  ************************************************/
431 struct io_register {
432         u8 io_addr;
433         u8 start_bit;
434         u8 end_bit;
435 };
436
437 /* IGA1 Horizontal Total */
438 struct iga1_hor_total {
439         int reg_num;
440         struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
441 };
442
443 /* IGA1 Horizontal Addressable Video */
444 struct iga1_hor_addr {
445         int reg_num;
446         struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
447 };
448
449 /* IGA1 Horizontal Blank Start */
450 struct iga1_hor_blank_start {
451         int reg_num;
452         struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
453 };
454
455 /* IGA1 Horizontal Blank End */
456 struct iga1_hor_blank_end {
457         int reg_num;
458         struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
459 };
460
461 /* IGA1 Horizontal Sync Start */
462 struct iga1_hor_sync_start {
463         int reg_num;
464         struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
465 };
466
467 /* IGA1 Horizontal Sync End */
468 struct iga1_hor_sync_end {
469         int reg_num;
470         struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
471 };
472
473 /* IGA1 Vertical Total */
474 struct iga1_ver_total {
475         int reg_num;
476         struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
477 };
478
479 /* IGA1 Vertical Addressable Video */
480 struct iga1_ver_addr {
481         int reg_num;
482         struct io_register reg[IGA1_VER_ADDR_REG_NUM];
483 };
484
485 /* IGA1 Vertical Blank Start */
486 struct iga1_ver_blank_start {
487         int reg_num;
488         struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
489 };
490
491 /* IGA1 Vertical Blank End */
492 struct iga1_ver_blank_end {
493         int reg_num;
494         struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
495 };
496
497 /* IGA1 Vertical Sync Start */
498 struct iga1_ver_sync_start {
499         int reg_num;
500         struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
501 };
502
503 /* IGA1 Vertical Sync End */
504 struct iga1_ver_sync_end {
505         int reg_num;
506         struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
507 };
508
509 /*****************************************************
510 **      Define IGA2 Shadow Display Timing         ****
511 *****************************************************/
512
513 /* IGA2 Shadow Horizontal Total */
514 struct iga2_shadow_hor_total {
515         int reg_num;
516         struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
517 };
518
519 /* IGA2 Shadow Horizontal Blank End */
520 struct iga2_shadow_hor_blank_end {
521         int reg_num;
522         struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
523 };
524
525 /* IGA2 Shadow Vertical Total */
526 struct iga2_shadow_ver_total {
527         int reg_num;
528         struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
529 };
530
531 /* IGA2 Shadow Vertical Addressable Video */
532 struct iga2_shadow_ver_addr {
533         int reg_num;
534         struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
535 };
536
537 /* IGA2 Shadow Vertical Blank Start */
538 struct iga2_shadow_ver_blank_start {
539         int reg_num;
540         struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
541 };
542
543 /* IGA2 Shadow Vertical Blank End */
544 struct iga2_shadow_ver_blank_end {
545         int reg_num;
546         struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
547 };
548
549 /* IGA2 Shadow Vertical Sync Start */
550 struct iga2_shadow_ver_sync_start {
551         int reg_num;
552         struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
553 };
554
555 /* IGA2 Shadow Vertical Sync End */
556 struct iga2_shadow_ver_sync_end {
557         int reg_num;
558         struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
559 };
560
561 /*****************************************************
562 **      Define IGA2 Display Timing                ****
563 ******************************************************/
564
565 /* IGA2 Horizontal Total */
566 struct iga2_hor_total {
567         int reg_num;
568         struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
569 };
570
571 /* IGA2 Horizontal Addressable Video */
572 struct iga2_hor_addr {
573         int reg_num;
574         struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
575 };
576
577 /* IGA2 Horizontal Blank Start */
578 struct iga2_hor_blank_start {
579         int reg_num;
580         struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
581 };
582
583 /* IGA2 Horizontal Blank End */
584 struct iga2_hor_blank_end {
585         int reg_num;
586         struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
587 };
588
589 /* IGA2 Horizontal Sync Start */
590 struct iga2_hor_sync_start {
591         int reg_num;
592         struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
593 };
594
595 /* IGA2 Horizontal Sync End */
596 struct iga2_hor_sync_end {
597         int reg_num;
598         struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
599 };
600
601 /* IGA2 Vertical Total */
602 struct iga2_ver_total {
603         int reg_num;
604         struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
605 };
606
607 /* IGA2 Vertical Addressable Video */
608 struct iga2_ver_addr {
609         int reg_num;
610         struct io_register reg[IGA2_VER_ADDR_REG_NUM];
611 };
612
613 /* IGA2 Vertical Blank Start */
614 struct iga2_ver_blank_start {
615         int reg_num;
616         struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
617 };
618
619 /* IGA2 Vertical Blank End */
620 struct iga2_ver_blank_end {
621         int reg_num;
622         struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
623 };
624
625 /* IGA2 Vertical Sync Start */
626 struct iga2_ver_sync_start {
627         int reg_num;
628         struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
629 };
630
631 /* IGA2 Vertical Sync End */
632 struct iga2_ver_sync_end {
633         int reg_num;
634         struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
635 };
636
637 /* IGA1 Fetch Count Register */
638 struct iga1_fetch_count {
639         int reg_num;
640         struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
641 };
642
643 /* IGA2 Fetch Count Register */
644 struct iga2_fetch_count {
645         int reg_num;
646         struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
647 };
648
649 struct fetch_count {
650         struct iga1_fetch_count iga1_fetch_count_reg;
651         struct iga2_fetch_count iga2_fetch_count_reg;
652 };
653
654 /* Starting Address Register */
655 struct iga1_starting_addr {
656         int reg_num;
657         struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
658 };
659
660 struct iga2_starting_addr {
661         int reg_num;
662         struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
663 };
664
665 struct starting_addr {
666         struct iga1_starting_addr iga1_starting_addr_reg;
667         struct iga2_starting_addr iga2_starting_addr_reg;
668 };
669
670 /* LCD Power Sequence Timer */
671 struct lcd_pwd_seq_td0 {
672         int reg_num;
673         struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
674 };
675
676 struct lcd_pwd_seq_td1 {
677         int reg_num;
678         struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
679 };
680
681 struct lcd_pwd_seq_td2 {
682         int reg_num;
683         struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
684 };
685
686 struct lcd_pwd_seq_td3 {
687         int reg_num;
688         struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
689 };
690
691 struct _lcd_pwd_seq_timer {
692         struct lcd_pwd_seq_td0 td0;
693         struct lcd_pwd_seq_td1 td1;
694         struct lcd_pwd_seq_td2 td2;
695         struct lcd_pwd_seq_td3 td3;
696 };
697
698 /* LCD Scaling Factor */
699 struct _lcd_hor_scaling_factor {
700         int reg_num;
701         struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
702 };
703
704 struct _lcd_ver_scaling_factor {
705         int reg_num;
706         struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
707 };
708
709 struct _lcd_scaling_factor {
710         struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
711         struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
712 };
713
714 struct pll_config {
715         u16 multiplier;
716         u8 divisor;
717         u8 rshift;
718 };
719
720 struct pll_map {
721         u32 clk;
722         struct pll_config cle266_pll;
723         struct pll_config k800_pll;
724         struct pll_config cx700_pll;
725         struct pll_config vx855_pll;
726 };
727
728 struct rgbLUT {
729         u8 red;
730         u8 green;
731         u8 blue;
732 };
733
734 struct lcd_pwd_seq_timer {
735         u16 td0;
736         u16 td1;
737         u16 td2;
738         u16 td3;
739 };
740
741 /* Display FIFO Relation Registers*/
742 struct iga1_fifo_depth_select {
743         int reg_num;
744         struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
745 };
746
747 struct iga1_fifo_threshold_select {
748         int reg_num;
749         struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
750 };
751
752 struct iga1_fifo_high_threshold_select {
753         int reg_num;
754         struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
755 };
756
757 struct iga1_display_queue_expire_num {
758         int reg_num;
759         struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
760 };
761
762 struct iga2_fifo_depth_select {
763         int reg_num;
764         struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
765 };
766
767 struct iga2_fifo_threshold_select {
768         int reg_num;
769         struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
770 };
771
772 struct iga2_fifo_high_threshold_select {
773         int reg_num;
774         struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
775 };
776
777 struct iga2_display_queue_expire_num {
778         int reg_num;
779         struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
780 };
781
782 struct fifo_depth_select {
783         struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
784         struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
785 };
786
787 struct fifo_threshold_select {
788         struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
789         struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
790 };
791
792 struct fifo_high_threshold_select {
793         struct iga1_fifo_high_threshold_select
794          iga1_fifo_high_threshold_select_reg;
795         struct iga2_fifo_high_threshold_select
796          iga2_fifo_high_threshold_select_reg;
797 };
798
799 struct display_queue_expire_num {
800         struct iga1_display_queue_expire_num
801          iga1_display_queue_expire_num_reg;
802         struct iga2_display_queue_expire_num
803          iga2_display_queue_expire_num_reg;
804 };
805
806 struct iga1_crtc_timing {
807         struct iga1_hor_total hor_total;
808         struct iga1_hor_addr hor_addr;
809         struct iga1_hor_blank_start hor_blank_start;
810         struct iga1_hor_blank_end hor_blank_end;
811         struct iga1_hor_sync_start hor_sync_start;
812         struct iga1_hor_sync_end hor_sync_end;
813         struct iga1_ver_total ver_total;
814         struct iga1_ver_addr ver_addr;
815         struct iga1_ver_blank_start ver_blank_start;
816         struct iga1_ver_blank_end ver_blank_end;
817         struct iga1_ver_sync_start ver_sync_start;
818         struct iga1_ver_sync_end ver_sync_end;
819 };
820
821 struct iga2_shadow_crtc_timing {
822         struct iga2_shadow_hor_total hor_total_shadow;
823         struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
824         struct iga2_shadow_ver_total ver_total_shadow;
825         struct iga2_shadow_ver_addr ver_addr_shadow;
826         struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
827         struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
828         struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
829         struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
830 };
831
832 struct iga2_crtc_timing {
833         struct iga2_hor_total hor_total;
834         struct iga2_hor_addr hor_addr;
835         struct iga2_hor_blank_start hor_blank_start;
836         struct iga2_hor_blank_end hor_blank_end;
837         struct iga2_hor_sync_start hor_sync_start;
838         struct iga2_hor_sync_end hor_sync_end;
839         struct iga2_ver_total ver_total;
840         struct iga2_ver_addr ver_addr;
841         struct iga2_ver_blank_start ver_blank_start;
842         struct iga2_ver_blank_end ver_blank_end;
843         struct iga2_ver_sync_start ver_sync_start;
844         struct iga2_ver_sync_end ver_sync_end;
845 };
846
847 /* device ID */
848 #define CLE266_FUNCTION3    0x3123
849 #define KM400_FUNCTION3     0x3205
850 #define CN400_FUNCTION2     0x2259
851 #define CN400_FUNCTION3     0x3259
852 /* support VT3314 chipset */
853 #define CN700_FUNCTION2     0x2314
854 #define CN700_FUNCTION3     0x3208
855 /* VT3324 chipset */
856 #define CX700_FUNCTION2     0x2324
857 #define CX700_FUNCTION3     0x3324
858 /* VT3204 chipset*/
859 #define KM800_FUNCTION3      0x3204
860 /* VT3336 chipset*/
861 #define KM890_FUNCTION3      0x3336
862 /* VT3327 chipset*/
863 #define P4M890_FUNCTION3     0x3327
864 /* VT3293 chipset*/
865 #define CN750_FUNCTION3     0x3208
866 /* VT3364 chipset*/
867 #define P4M900_FUNCTION3    0x3364
868 /* VT3353 chipset*/
869 #define VX800_FUNCTION3     0x3353
870 /* VT3409 chipset*/
871 #define VX855_FUNCTION3     0x3409
872
873 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
874
875 struct IODATA {
876         u8 Index;
877         u8 Mask;
878         u8 Data;
879 };
880
881 struct pci_device_id_info {
882         u32 vendor;
883         u32 device;
884         u32 chip_index;
885 };
886
887 struct via_device_mapping {
888         u32 device;
889         const char *name;
890 };
891
892 extern unsigned int viafb_second_virtual_xres;
893 extern int viafb_SAMM_ON;
894 extern int viafb_dual_fb;
895 extern int viafb_LCD2_ON;
896 extern int viafb_LCD_ON;
897 extern int viafb_DVI_ON;
898 extern int viafb_hotplug;
899
900 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
901         struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
902
903 void viafb_set_vclock(u32 CLK, int set_iga);
904 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
905         struct io_register *reg,
906               int io_type);
907 void viafb_crt_disable(void);
908 void viafb_crt_enable(void);
909 void via_set_source(u32 devices, u8 iga);
910 u32 via_parse_odev(char *input, char **end);
911 void via_odev_to_seq(struct seq_file *m, u32 odev);
912 void init_ad9389(void);
913 /* Access I/O Function */
914 void viafb_lock_crt(void);
915 void viafb_unlock_crt(void);
916 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
917 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
918 u32 viafb_get_clk_value(int clk);
919 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
920 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
921                                         *p_gfx_dpa_setting);
922
923 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
924         struct VideoModeTable *vmode_tbl1, int video_bpp1);
925 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
926         struct VideoModeTable *vmode_tbl);
927 void __devinit viafb_init_chip_info(int chip_type);
928 void __devinit viafb_init_dac(int set_iga);
929 int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
930 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
931 void viafb_update_device_setting(int hres, int vres, int bpp,
932                            int vmode_refresh, int flag);
933
934 void viafb_set_iga_path(void);
935 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
936 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
937 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
938
939 #endif /* __HW_H__ */