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viafb: introduce per output device power management
[~shefty/rdma-dev.git] / drivers / video / via / hw.h
1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 #ifndef __HW_H__
23 #define __HW_H__
24
25 #include <linux/seq_file.h>
26
27 #include "viamode.h"
28 #include "global.h"
29 #include "via_modesetting.h"
30
31 #define viafb_read_reg(p, i)                    via_read_reg(p, i)
32 #define viafb_write_reg(i, p, d)                via_write_reg(p, i, d)
33 #define viafb_write_reg_mask(i, p, d, m)        via_write_reg_mask(p, i, d, m)
34
35 /* VIA output devices */
36 #define VIA_6C          0x00000001
37 #define VIA_93          0x00000002
38 #define VIA_96          0x00000004
39 #define VIA_CRT         0x00000010
40 #define VIA_DVP1        0x00000020
41 #define VIA_LVDS1       0x00000040
42 #define VIA_LVDS2       0x00000080
43
44 /* VIA output device power states */
45 #define VIA_STATE_ON            0
46 #define VIA_STATE_STANDBY       1
47 #define VIA_STATE_SUSPEND       2
48 #define VIA_STATE_OFF           3
49
50 /***************************************************
51 * Definition IGA1 Design Method of CRTC Registers *
52 ****************************************************/
53 #define IGA1_HOR_TOTAL_FORMULA(x)           (((x)/8)-5)
54 #define IGA1_HOR_ADDR_FORMULA(x)            (((x)/8)-1)
55 #define IGA1_HOR_BLANK_START_FORMULA(x)     (((x)/8)-1)
56 #define IGA1_HOR_BLANK_END_FORMULA(x, y)     (((x+y)/8)-1)
57 #define IGA1_HOR_SYNC_START_FORMULA(x)      ((x)/8)
58 #define IGA1_HOR_SYNC_END_FORMULA(x, y)      ((x+y)/8)
59
60 #define IGA1_VER_TOTAL_FORMULA(x)           ((x)-2)
61 #define IGA1_VER_ADDR_FORMULA(x)            ((x)-1)
62 #define IGA1_VER_BLANK_START_FORMULA(x)     ((x)-1)
63 #define IGA1_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
64 #define IGA1_VER_SYNC_START_FORMULA(x)      ((x)-1)
65 #define IGA1_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
66
67 /***************************************************
68 ** Definition IGA2 Design Method of CRTC Registers *
69 ****************************************************/
70 #define IGA2_HOR_TOTAL_FORMULA(x)           ((x)-1)
71 #define IGA2_HOR_ADDR_FORMULA(x)            ((x)-1)
72 #define IGA2_HOR_BLANK_START_FORMULA(x)     ((x)-1)
73 #define IGA2_HOR_BLANK_END_FORMULA(x, y)     ((x+y)-1)
74 #define IGA2_HOR_SYNC_START_FORMULA(x)      ((x)-1)
75 #define IGA2_HOR_SYNC_END_FORMULA(x, y)      ((x+y)-1)
76
77 #define IGA2_VER_TOTAL_FORMULA(x)           ((x)-1)
78 #define IGA2_VER_ADDR_FORMULA(x)            ((x)-1)
79 #define IGA2_VER_BLANK_START_FORMULA(x)     ((x)-1)
80 #define IGA2_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
81 #define IGA2_VER_SYNC_START_FORMULA(x)      ((x)-1)
82 #define IGA2_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
83
84 /**********************************************************/
85 /* Definition IGA2 Design Method of CRTC Shadow Registers */
86 /**********************************************************/
87 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           ((x/8)-5)
88 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y)     (((x+y)/8)-1)
89 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           ((x)-2)
90 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            ((x)-1)
91 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     ((x)-1)
92 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y)     ((x+y)-1)
93 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
94 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y)      (x+y)
95
96 /* Define Register Number for IGA1 CRTC Timing */
97
98 /* location: {CR00,0,7},{CR36,3,3} */
99 #define IGA1_HOR_TOTAL_REG_NUM          2
100 /* location: {CR01,0,7} */
101 #define IGA1_HOR_ADDR_REG_NUM           1
102 /* location: {CR02,0,7} */
103 #define IGA1_HOR_BLANK_START_REG_NUM    1
104 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
105 #define IGA1_HOR_BLANK_END_REG_NUM      3
106 /* location: {CR04,0,7},{CR33,4,4} */
107 #define IGA1_HOR_SYNC_START_REG_NUM     2
108 /* location: {CR05,0,4} */
109 #define IGA1_HOR_SYNC_END_REG_NUM       1
110 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
111 #define IGA1_VER_TOTAL_REG_NUM          4
112 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
113 #define IGA1_VER_ADDR_REG_NUM           4
114 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
115 #define IGA1_VER_BLANK_START_REG_NUM    4
116 /* location: {CR16,0,7} */
117 #define IGA1_VER_BLANK_END_REG_NUM      1
118 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
119 #define IGA1_VER_SYNC_START_REG_NUM     4
120 /* location: {CR11,0,3} */
121 #define IGA1_VER_SYNC_END_REG_NUM       1
122
123 /* Define Register Number for IGA2 Shadow CRTC Timing */
124
125 /* location: {CR6D,0,7},{CR71,3,3} */
126 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2
127 /* location: {CR6E,0,7} */
128 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1
129 /* location: {CR6F,0,7},{CR71,0,2} */
130 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2
131 /* location: {CR70,0,7},{CR71,4,6} */
132 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2
133 /* location: {CR72,0,7},{CR74,4,6} */
134 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
135 /* location: {CR73,0,7},{CR74,0,2} */
136 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2
137 /* location: {CR75,0,7},{CR76,4,6} */
138 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2
139 /* location: {CR76,0,3} */
140 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1
141
142 /* Define Register Number for IGA2 CRTC Timing */
143
144 /* location: {CR50,0,7},{CR55,0,3} */
145 #define IGA2_HOR_TOTAL_REG_NUM          2
146 /* location: {CR51,0,7},{CR55,4,6} */
147 #define IGA2_HOR_ADDR_REG_NUM           2
148 /* location: {CR52,0,7},{CR54,0,2} */
149 #define IGA2_HOR_BLANK_START_REG_NUM    2
150 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
151 is reserved, so it may have problem to set 1600x1200 on IGA2. */
152 /*              Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
153 #define IGA2_HOR_BLANK_END_REG_NUM      3
154 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
155 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
156 #define IGA2_HOR_SYNC_START_REG_NUM     4
157
158 /* location: {CR57,0,7},{CR5C,6,6} */
159 #define IGA2_HOR_SYNC_END_REG_NUM       2
160 /* location: {CR58,0,7},{CR5D,0,2} */
161 #define IGA2_VER_TOTAL_REG_NUM          2
162 /* location: {CR59,0,7},{CR5D,3,5} */
163 #define IGA2_VER_ADDR_REG_NUM           2
164 /* location: {CR5A,0,7},{CR5C,0,2} */
165 #define IGA2_VER_BLANK_START_REG_NUM    2
166 /* location: {CR5E,0,7},{CR5C,3,5} */
167 #define IGA2_VER_BLANK_END_REG_NUM      2
168 /* location: {CR5E,0,7},{CR5F,5,7} */
169 #define IGA2_VER_SYNC_START_REG_NUM     2
170 /* location: {CR5F,0,4} */
171 #define IGA2_VER_SYNC_END_REG_NUM       1
172
173 /* Define Fetch Count Register*/
174
175 /* location: {SR1C,0,7},{SR1D,0,1} */
176 #define IGA1_FETCH_COUNT_REG_NUM        2
177 /* 16 bytes alignment. */
178 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16
179 /* x: H resolution, y: color depth */
180 #define IGA1_FETCH_COUNT_PATCH_VALUE    4
181 #define IGA1_FETCH_COUNT_FORMULA(x, y)   \
182         (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
183
184 /* location: {CR65,0,7},{CR67,2,3} */
185 #define IGA2_FETCH_COUNT_REG_NUM        2
186 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
187 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
188 #define IGA2_FETCH_COUNT_FORMULA(x, y)   \
189         (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
190
191 /* Staring Address*/
192
193 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
194 #define IGA1_STARTING_ADDR_REG_NUM      4
195 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
196 #define IGA2_STARTING_ADDR_REG_NUM      3
197
198 /* Define Display OFFSET*/
199 /* These value are by HW suggested value*/
200 /* location: {SR17,0,7} */
201 #define K800_IGA1_FIFO_MAX_DEPTH                384
202 /* location: {SR16,0,5},{SR16,7,7} */
203 #define K800_IGA1_FIFO_THRESHOLD                328
204 /* location: {SR18,0,5},{SR18,7,7} */
205 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296
206 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
207                                 /* because HW only 5 bits */
208 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
209
210 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
211 #define K800_IGA2_FIFO_MAX_DEPTH                384
212 /* location: {CR68,0,3},{CR95,4,6} */
213 #define K800_IGA2_FIFO_THRESHOLD                328
214 /* location: {CR92,0,3},{CR95,0,2} */
215 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296
216 /* location: {CR94,0,6} */
217 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
218
219 /* location: {SR17,0,7} */
220 #define P880_IGA1_FIFO_MAX_DEPTH                192
221 /* location: {SR16,0,5},{SR16,7,7} */
222 #define P880_IGA1_FIFO_THRESHOLD                128
223 /* location: {SR18,0,5},{SR18,7,7} */
224 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64
225 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
226                                 /* because HW only 5 bits */
227 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
228
229 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
230 #define P880_IGA2_FIFO_MAX_DEPTH                96
231 /* location: {CR68,0,3},{CR95,4,6} */
232 #define P880_IGA2_FIFO_THRESHOLD                64
233 /* location: {CR92,0,3},{CR95,0,2} */
234 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32
235 /* location: {CR94,0,6} */
236 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
237
238 /* VT3314 chipset*/
239
240 /* location: {SR17,0,7} */
241 #define CN700_IGA1_FIFO_MAX_DEPTH               96
242 /* location: {SR16,0,5},{SR16,7,7} */
243 #define CN700_IGA1_FIFO_THRESHOLD               80
244 /* location: {SR18,0,5},{SR18,7,7} */
245 #define CN700_IGA1_FIFO_HIGH_THRESHOLD          64
246 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
247                                 because HW only 5 bits */
248 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0
249 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
250 #define CN700_IGA2_FIFO_MAX_DEPTH               96
251 /* location: {CR68,0,3},{CR95,4,6} */
252 #define CN700_IGA2_FIFO_THRESHOLD               80
253 /* location: {CR92,0,3},{CR95,0,2} */
254 #define CN700_IGA2_FIFO_HIGH_THRESHOLD          32
255 /* location: {CR94,0,6} */
256 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
257
258 /* For VT3324, these values are suggested by HW */
259 /* location: {SR17,0,7} */
260 #define CX700_IGA1_FIFO_MAX_DEPTH               192
261 /* location: {SR16,0,5},{SR16,7,7} */
262 #define CX700_IGA1_FIFO_THRESHOLD               128
263 /* location: {SR18,0,5},{SR18,7,7} */
264 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128
265 /* location: {SR22,0,4} */
266 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
267
268 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
269 #define CX700_IGA2_FIFO_MAX_DEPTH               96
270 /* location: {CR68,0,3},{CR95,4,6} */
271 #define CX700_IGA2_FIFO_THRESHOLD               64
272 /* location: {CR92,0,3},{CR95,0,2} */
273 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32
274 /* location: {CR94,0,6} */
275 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
276
277 /* VT3336 chipset*/
278 /* location: {SR17,0,7} */
279 #define K8M890_IGA1_FIFO_MAX_DEPTH               360
280 /* location: {SR16,0,5},{SR16,7,7} */
281 #define K8M890_IGA1_FIFO_THRESHOLD               328
282 /* location: {SR18,0,5},{SR18,7,7} */
283 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD          296
284 /* location: {SR22,0,4}. */
285 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
286
287 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
288 #define K8M890_IGA2_FIFO_MAX_DEPTH               360
289 /* location: {CR68,0,3},{CR95,4,6} */
290 #define K8M890_IGA2_FIFO_THRESHOLD               328
291 /* location: {CR92,0,3},{CR95,0,2} */
292 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD          296
293 /* location: {CR94,0,6} */
294 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     124
295
296 /* VT3327 chipset*/
297 /* location: {SR17,0,7} */
298 #define P4M890_IGA1_FIFO_MAX_DEPTH               96
299 /* location: {SR16,0,5},{SR16,7,7} */
300 #define P4M890_IGA1_FIFO_THRESHOLD               76
301 /* location: {SR18,0,5},{SR18,7,7} */
302 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD          64
303 /* location: {SR22,0,4}. (32/4) =8 */
304 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
305 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
306 #define P4M890_IGA2_FIFO_MAX_DEPTH               96
307 /* location: {CR68,0,3},{CR95,4,6} */
308 #define P4M890_IGA2_FIFO_THRESHOLD               76
309 /* location: {CR92,0,3},{CR95,0,2} */
310 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD          64
311 /* location: {CR94,0,6} */
312 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
313
314 /* VT3364 chipset*/
315 /* location: {SR17,0,7} */
316 #define P4M900_IGA1_FIFO_MAX_DEPTH               96
317 /* location: {SR16,0,5},{SR16,7,7} */
318 #define P4M900_IGA1_FIFO_THRESHOLD               76
319 /* location: {SR18,0,5},{SR18,7,7} */
320 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD          76
321 /* location: {SR22,0,4}. */
322 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
323 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
324 #define P4M900_IGA2_FIFO_MAX_DEPTH               96
325 /* location: {CR68,0,3},{CR95,4,6} */
326 #define P4M900_IGA2_FIFO_THRESHOLD               76
327 /* location: {CR92,0,3},{CR95,0,2} */
328 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD          76
329 /* location: {CR94,0,6} */
330 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
331
332 /* For VT3353, these values are suggested by HW */
333 /* location: {SR17,0,7} */
334 #define VX800_IGA1_FIFO_MAX_DEPTH               192
335 /* location: {SR16,0,5},{SR16,7,7} */
336 #define VX800_IGA1_FIFO_THRESHOLD               152
337 /* location: {SR18,0,5},{SR18,7,7} */
338 #define VX800_IGA1_FIFO_HIGH_THRESHOLD          152
339 /* location: {SR22,0,4} */
340 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      64
341 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
342 #define VX800_IGA2_FIFO_MAX_DEPTH               96
343 /* location: {CR68,0,3},{CR95,4,6} */
344 #define VX800_IGA2_FIFO_THRESHOLD               64
345 /* location: {CR92,0,3},{CR95,0,2} */
346 #define VX800_IGA2_FIFO_HIGH_THRESHOLD          32
347 /* location: {CR94,0,6} */
348 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
349
350 /* For VT3409 */
351 #define VX855_IGA1_FIFO_MAX_DEPTH               400
352 #define VX855_IGA1_FIFO_THRESHOLD               320
353 #define VX855_IGA1_FIFO_HIGH_THRESHOLD          320
354 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
355
356 #define VX855_IGA2_FIFO_MAX_DEPTH               200
357 #define VX855_IGA2_FIFO_THRESHOLD               160
358 #define VX855_IGA2_FIFO_HIGH_THRESHOLD          160
359 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
360
361 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
362 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
363 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
364 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
365
366 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
367 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
368 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
369 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
370
371 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)-1)
372 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
373 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
374 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
375 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   (((x/2)/4)-1)
376 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
377 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
378 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
379
380 /************************************************************************/
381 /*  LCD Timing                                                          */
382 /************************************************************************/
383
384 /* 500 ms = 500000 us */
385 #define LCD_POWER_SEQ_TD0               500000
386 /* 50 ms = 50000 us */
387 #define LCD_POWER_SEQ_TD1               50000
388 /* 0 us */
389 #define LCD_POWER_SEQ_TD2               0
390 /* 210 ms = 210000 us */
391 #define LCD_POWER_SEQ_TD3               210000
392 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
393 #define CLE266_POWER_SEQ_UNIT           71
394 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
395 #define K800_POWER_SEQ_UNIT             142
396 /* 2^13 * (1/14.31818M) = 572.1 us */
397 #define P880_POWER_SEQ_UNIT             572
398
399 #define CLE266_POWER_SEQ_FORMULA(x)     ((x)/CLE266_POWER_SEQ_UNIT)
400 #define K800_POWER_SEQ_FORMULA(x)       ((x)/K800_POWER_SEQ_UNIT)
401 #define P880_POWER_SEQ_FORMULA(x)       ((x)/P880_POWER_SEQ_UNIT)
402
403 /* location: {CR8B,0,7},{CR8F,0,3} */
404 #define LCD_POWER_SEQ_TD0_REG_NUM       2
405 /* location: {CR8C,0,7},{CR8F,4,7} */
406 #define LCD_POWER_SEQ_TD1_REG_NUM       2
407 /* location: {CR8D,0,7},{CR90,0,3} */
408 #define LCD_POWER_SEQ_TD2_REG_NUM       2
409 /* location: {CR8E,0,7},{CR90,4,7} */
410 #define LCD_POWER_SEQ_TD3_REG_NUM       2
411
412 /* LCD Scaling factor*/
413 /* x: indicate setting horizontal size*/
414 /* y: indicate panel horizontal size*/
415
416 /* Horizontal scaling factor 10 bits (2^10) */
417 #define CLE266_LCD_HOR_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
418 /* Vertical scaling factor 10 bits (2^10) */
419 #define CLE266_LCD_VER_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
420 /* Horizontal scaling factor 10 bits (2^12) */
421 #define K800_LCD_HOR_SCF_FORMULA(x, y)     (((x-1)*4096)/(y-1))
422 /* Vertical scaling factor 10 bits (2^11) */
423 #define K800_LCD_VER_SCF_FORMULA(x, y)     (((x-1)*2048)/(y-1))
424
425 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
426 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3
427 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
428 #define LCD_VER_SCALING_FACTOR_REG_NUM  3
429 /* location: {CR77,0,7},{CR79,4,5} */
430 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2
431 /* location: {CR78,0,7},{CR79,6,7} */
432 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2
433
434 /************************************************
435  *****     Define IGA1 Display Timing       *****
436  ************************************************/
437 struct io_register {
438         u8 io_addr;
439         u8 start_bit;
440         u8 end_bit;
441 };
442
443 /* IGA1 Horizontal Total */
444 struct iga1_hor_total {
445         int reg_num;
446         struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
447 };
448
449 /* IGA1 Horizontal Addressable Video */
450 struct iga1_hor_addr {
451         int reg_num;
452         struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
453 };
454
455 /* IGA1 Horizontal Blank Start */
456 struct iga1_hor_blank_start {
457         int reg_num;
458         struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
459 };
460
461 /* IGA1 Horizontal Blank End */
462 struct iga1_hor_blank_end {
463         int reg_num;
464         struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
465 };
466
467 /* IGA1 Horizontal Sync Start */
468 struct iga1_hor_sync_start {
469         int reg_num;
470         struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
471 };
472
473 /* IGA1 Horizontal Sync End */
474 struct iga1_hor_sync_end {
475         int reg_num;
476         struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
477 };
478
479 /* IGA1 Vertical Total */
480 struct iga1_ver_total {
481         int reg_num;
482         struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
483 };
484
485 /* IGA1 Vertical Addressable Video */
486 struct iga1_ver_addr {
487         int reg_num;
488         struct io_register reg[IGA1_VER_ADDR_REG_NUM];
489 };
490
491 /* IGA1 Vertical Blank Start */
492 struct iga1_ver_blank_start {
493         int reg_num;
494         struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
495 };
496
497 /* IGA1 Vertical Blank End */
498 struct iga1_ver_blank_end {
499         int reg_num;
500         struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
501 };
502
503 /* IGA1 Vertical Sync Start */
504 struct iga1_ver_sync_start {
505         int reg_num;
506         struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
507 };
508
509 /* IGA1 Vertical Sync End */
510 struct iga1_ver_sync_end {
511         int reg_num;
512         struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
513 };
514
515 /*****************************************************
516 **      Define IGA2 Shadow Display Timing         ****
517 *****************************************************/
518
519 /* IGA2 Shadow Horizontal Total */
520 struct iga2_shadow_hor_total {
521         int reg_num;
522         struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
523 };
524
525 /* IGA2 Shadow Horizontal Blank End */
526 struct iga2_shadow_hor_blank_end {
527         int reg_num;
528         struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
529 };
530
531 /* IGA2 Shadow Vertical Total */
532 struct iga2_shadow_ver_total {
533         int reg_num;
534         struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
535 };
536
537 /* IGA2 Shadow Vertical Addressable Video */
538 struct iga2_shadow_ver_addr {
539         int reg_num;
540         struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
541 };
542
543 /* IGA2 Shadow Vertical Blank Start */
544 struct iga2_shadow_ver_blank_start {
545         int reg_num;
546         struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
547 };
548
549 /* IGA2 Shadow Vertical Blank End */
550 struct iga2_shadow_ver_blank_end {
551         int reg_num;
552         struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
553 };
554
555 /* IGA2 Shadow Vertical Sync Start */
556 struct iga2_shadow_ver_sync_start {
557         int reg_num;
558         struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
559 };
560
561 /* IGA2 Shadow Vertical Sync End */
562 struct iga2_shadow_ver_sync_end {
563         int reg_num;
564         struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
565 };
566
567 /*****************************************************
568 **      Define IGA2 Display Timing                ****
569 ******************************************************/
570
571 /* IGA2 Horizontal Total */
572 struct iga2_hor_total {
573         int reg_num;
574         struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
575 };
576
577 /* IGA2 Horizontal Addressable Video */
578 struct iga2_hor_addr {
579         int reg_num;
580         struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
581 };
582
583 /* IGA2 Horizontal Blank Start */
584 struct iga2_hor_blank_start {
585         int reg_num;
586         struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
587 };
588
589 /* IGA2 Horizontal Blank End */
590 struct iga2_hor_blank_end {
591         int reg_num;
592         struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
593 };
594
595 /* IGA2 Horizontal Sync Start */
596 struct iga2_hor_sync_start {
597         int reg_num;
598         struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
599 };
600
601 /* IGA2 Horizontal Sync End */
602 struct iga2_hor_sync_end {
603         int reg_num;
604         struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
605 };
606
607 /* IGA2 Vertical Total */
608 struct iga2_ver_total {
609         int reg_num;
610         struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
611 };
612
613 /* IGA2 Vertical Addressable Video */
614 struct iga2_ver_addr {
615         int reg_num;
616         struct io_register reg[IGA2_VER_ADDR_REG_NUM];
617 };
618
619 /* IGA2 Vertical Blank Start */
620 struct iga2_ver_blank_start {
621         int reg_num;
622         struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
623 };
624
625 /* IGA2 Vertical Blank End */
626 struct iga2_ver_blank_end {
627         int reg_num;
628         struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
629 };
630
631 /* IGA2 Vertical Sync Start */
632 struct iga2_ver_sync_start {
633         int reg_num;
634         struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
635 };
636
637 /* IGA2 Vertical Sync End */
638 struct iga2_ver_sync_end {
639         int reg_num;
640         struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
641 };
642
643 /* IGA1 Fetch Count Register */
644 struct iga1_fetch_count {
645         int reg_num;
646         struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
647 };
648
649 /* IGA2 Fetch Count Register */
650 struct iga2_fetch_count {
651         int reg_num;
652         struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
653 };
654
655 struct fetch_count {
656         struct iga1_fetch_count iga1_fetch_count_reg;
657         struct iga2_fetch_count iga2_fetch_count_reg;
658 };
659
660 /* Starting Address Register */
661 struct iga1_starting_addr {
662         int reg_num;
663         struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
664 };
665
666 struct iga2_starting_addr {
667         int reg_num;
668         struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
669 };
670
671 struct starting_addr {
672         struct iga1_starting_addr iga1_starting_addr_reg;
673         struct iga2_starting_addr iga2_starting_addr_reg;
674 };
675
676 /* LCD Power Sequence Timer */
677 struct lcd_pwd_seq_td0 {
678         int reg_num;
679         struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
680 };
681
682 struct lcd_pwd_seq_td1 {
683         int reg_num;
684         struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
685 };
686
687 struct lcd_pwd_seq_td2 {
688         int reg_num;
689         struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
690 };
691
692 struct lcd_pwd_seq_td3 {
693         int reg_num;
694         struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
695 };
696
697 struct _lcd_pwd_seq_timer {
698         struct lcd_pwd_seq_td0 td0;
699         struct lcd_pwd_seq_td1 td1;
700         struct lcd_pwd_seq_td2 td2;
701         struct lcd_pwd_seq_td3 td3;
702 };
703
704 /* LCD Scaling Factor */
705 struct _lcd_hor_scaling_factor {
706         int reg_num;
707         struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
708 };
709
710 struct _lcd_ver_scaling_factor {
711         int reg_num;
712         struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
713 };
714
715 struct _lcd_scaling_factor {
716         struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
717         struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
718 };
719
720 struct pll_config {
721         u16 multiplier;
722         u8 divisor;
723         u8 rshift;
724 };
725
726 struct pll_map {
727         u32 clk;
728         struct pll_config cle266_pll;
729         struct pll_config k800_pll;
730         struct pll_config cx700_pll;
731         struct pll_config vx855_pll;
732 };
733
734 struct rgbLUT {
735         u8 red;
736         u8 green;
737         u8 blue;
738 };
739
740 struct lcd_pwd_seq_timer {
741         u16 td0;
742         u16 td1;
743         u16 td2;
744         u16 td3;
745 };
746
747 /* Display FIFO Relation Registers*/
748 struct iga1_fifo_depth_select {
749         int reg_num;
750         struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
751 };
752
753 struct iga1_fifo_threshold_select {
754         int reg_num;
755         struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
756 };
757
758 struct iga1_fifo_high_threshold_select {
759         int reg_num;
760         struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
761 };
762
763 struct iga1_display_queue_expire_num {
764         int reg_num;
765         struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
766 };
767
768 struct iga2_fifo_depth_select {
769         int reg_num;
770         struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
771 };
772
773 struct iga2_fifo_threshold_select {
774         int reg_num;
775         struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
776 };
777
778 struct iga2_fifo_high_threshold_select {
779         int reg_num;
780         struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
781 };
782
783 struct iga2_display_queue_expire_num {
784         int reg_num;
785         struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
786 };
787
788 struct fifo_depth_select {
789         struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
790         struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
791 };
792
793 struct fifo_threshold_select {
794         struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
795         struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
796 };
797
798 struct fifo_high_threshold_select {
799         struct iga1_fifo_high_threshold_select
800          iga1_fifo_high_threshold_select_reg;
801         struct iga2_fifo_high_threshold_select
802          iga2_fifo_high_threshold_select_reg;
803 };
804
805 struct display_queue_expire_num {
806         struct iga1_display_queue_expire_num
807          iga1_display_queue_expire_num_reg;
808         struct iga2_display_queue_expire_num
809          iga2_display_queue_expire_num_reg;
810 };
811
812 struct iga1_crtc_timing {
813         struct iga1_hor_total hor_total;
814         struct iga1_hor_addr hor_addr;
815         struct iga1_hor_blank_start hor_blank_start;
816         struct iga1_hor_blank_end hor_blank_end;
817         struct iga1_hor_sync_start hor_sync_start;
818         struct iga1_hor_sync_end hor_sync_end;
819         struct iga1_ver_total ver_total;
820         struct iga1_ver_addr ver_addr;
821         struct iga1_ver_blank_start ver_blank_start;
822         struct iga1_ver_blank_end ver_blank_end;
823         struct iga1_ver_sync_start ver_sync_start;
824         struct iga1_ver_sync_end ver_sync_end;
825 };
826
827 struct iga2_shadow_crtc_timing {
828         struct iga2_shadow_hor_total hor_total_shadow;
829         struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
830         struct iga2_shadow_ver_total ver_total_shadow;
831         struct iga2_shadow_ver_addr ver_addr_shadow;
832         struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
833         struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
834         struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
835         struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
836 };
837
838 struct iga2_crtc_timing {
839         struct iga2_hor_total hor_total;
840         struct iga2_hor_addr hor_addr;
841         struct iga2_hor_blank_start hor_blank_start;
842         struct iga2_hor_blank_end hor_blank_end;
843         struct iga2_hor_sync_start hor_sync_start;
844         struct iga2_hor_sync_end hor_sync_end;
845         struct iga2_ver_total ver_total;
846         struct iga2_ver_addr ver_addr;
847         struct iga2_ver_blank_start ver_blank_start;
848         struct iga2_ver_blank_end ver_blank_end;
849         struct iga2_ver_sync_start ver_sync_start;
850         struct iga2_ver_sync_end ver_sync_end;
851 };
852
853 /* device ID */
854 #define CLE266_FUNCTION3    0x3123
855 #define KM400_FUNCTION3     0x3205
856 #define CN400_FUNCTION2     0x2259
857 #define CN400_FUNCTION3     0x3259
858 /* support VT3314 chipset */
859 #define CN700_FUNCTION2     0x2314
860 #define CN700_FUNCTION3     0x3208
861 /* VT3324 chipset */
862 #define CX700_FUNCTION2     0x2324
863 #define CX700_FUNCTION3     0x3324
864 /* VT3204 chipset*/
865 #define KM800_FUNCTION3      0x3204
866 /* VT3336 chipset*/
867 #define KM890_FUNCTION3      0x3336
868 /* VT3327 chipset*/
869 #define P4M890_FUNCTION3     0x3327
870 /* VT3293 chipset*/
871 #define CN750_FUNCTION3     0x3208
872 /* VT3364 chipset*/
873 #define P4M900_FUNCTION3    0x3364
874 /* VT3353 chipset*/
875 #define VX800_FUNCTION3     0x3353
876 /* VT3409 chipset*/
877 #define VX855_FUNCTION3     0x3409
878
879 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
880
881 struct IODATA {
882         u8 Index;
883         u8 Mask;
884         u8 Data;
885 };
886
887 struct pci_device_id_info {
888         u32 vendor;
889         u32 device;
890         u32 chip_index;
891 };
892
893 struct via_device_mapping {
894         u32 device;
895         const char *name;
896 };
897
898 extern unsigned int viafb_second_virtual_xres;
899 extern int viafb_SAMM_ON;
900 extern int viafb_dual_fb;
901 extern int viafb_LCD2_ON;
902 extern int viafb_LCD_ON;
903 extern int viafb_DVI_ON;
904 extern int viafb_hotplug;
905
906 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
907         struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
908
909 void viafb_set_vclock(u32 CLK, int set_iga);
910 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
911         struct io_register *reg,
912               int io_type);
913 void via_set_source(u32 devices, u8 iga);
914 void via_set_state(u32 devices, u8 state);
915 u32 via_parse_odev(char *input, char **end);
916 void via_odev_to_seq(struct seq_file *m, u32 odev);
917 void init_ad9389(void);
918 /* Access I/O Function */
919 void viafb_lock_crt(void);
920 void viafb_unlock_crt(void);
921 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
922 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
923 u32 viafb_get_clk_value(int clk);
924 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
925 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
926                                         *p_gfx_dpa_setting);
927
928 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
929         struct VideoModeTable *vmode_tbl1, int video_bpp1);
930 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
931         struct VideoModeTable *vmode_tbl);
932 void __devinit viafb_init_chip_info(int chip_type);
933 void __devinit viafb_init_dac(int set_iga);
934 int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
935 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
936 void viafb_update_device_setting(int hres, int vres, int bpp,
937                            int vmode_refresh, int flag);
938
939 void viafb_set_iga_path(void);
940 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
941 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
942 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
943
944 #endif /* __HW_H__ */