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viafb: rename output devices
[~shefty/rdma-dev.git] / drivers / video / via / hw.h
1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 #ifndef __HW_H__
23 #define __HW_H__
24
25 #include <linux/seq_file.h>
26
27 #include "viamode.h"
28 #include "global.h"
29 #include "via_modesetting.h"
30
31 #define viafb_read_reg(p, i)                    via_read_reg(p, i)
32 #define viafb_write_reg(i, p, d)                via_write_reg(p, i, d)
33 #define viafb_write_reg_mask(i, p, d, m)        via_write_reg_mask(p, i, d, m)
34
35 /* VIA output devices */
36 #define VIA_LDVP0       0x00000001
37 #define VIA_LDVP1       0x00000002
38 #define VIA_DVP0        0x00000004
39 #define VIA_CRT         0x00000010
40 #define VIA_DVP1        0x00000020
41 #define VIA_LVDS1       0x00000040
42 #define VIA_LVDS2       0x00000080
43
44 /* VIA output device power states */
45 #define VIA_STATE_ON            0
46 #define VIA_STATE_STANDBY       1
47 #define VIA_STATE_SUSPEND       2
48 #define VIA_STATE_OFF           3
49
50 /* VIA output device sync polarity */
51 #define VIA_HSYNC_NEGATIVE      0x01
52 #define VIA_VSYNC_NEGATIVE      0x02
53
54 /***************************************************
55 * Definition IGA1 Design Method of CRTC Registers *
56 ****************************************************/
57 #define IGA1_HOR_TOTAL_FORMULA(x)           (((x)/8)-5)
58 #define IGA1_HOR_ADDR_FORMULA(x)            (((x)/8)-1)
59 #define IGA1_HOR_BLANK_START_FORMULA(x)     (((x)/8)-1)
60 #define IGA1_HOR_BLANK_END_FORMULA(x, y)     (((x+y)/8)-1)
61 #define IGA1_HOR_SYNC_START_FORMULA(x)      ((x)/8)
62 #define IGA1_HOR_SYNC_END_FORMULA(x, y)      ((x+y)/8)
63
64 #define IGA1_VER_TOTAL_FORMULA(x)           ((x)-2)
65 #define IGA1_VER_ADDR_FORMULA(x)            ((x)-1)
66 #define IGA1_VER_BLANK_START_FORMULA(x)     ((x)-1)
67 #define IGA1_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
68 #define IGA1_VER_SYNC_START_FORMULA(x)      ((x)-1)
69 #define IGA1_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
70
71 /***************************************************
72 ** Definition IGA2 Design Method of CRTC Registers *
73 ****************************************************/
74 #define IGA2_HOR_TOTAL_FORMULA(x)           ((x)-1)
75 #define IGA2_HOR_ADDR_FORMULA(x)            ((x)-1)
76 #define IGA2_HOR_BLANK_START_FORMULA(x)     ((x)-1)
77 #define IGA2_HOR_BLANK_END_FORMULA(x, y)     ((x+y)-1)
78 #define IGA2_HOR_SYNC_START_FORMULA(x)      ((x)-1)
79 #define IGA2_HOR_SYNC_END_FORMULA(x, y)      ((x+y)-1)
80
81 #define IGA2_VER_TOTAL_FORMULA(x)           ((x)-1)
82 #define IGA2_VER_ADDR_FORMULA(x)            ((x)-1)
83 #define IGA2_VER_BLANK_START_FORMULA(x)     ((x)-1)
84 #define IGA2_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
85 #define IGA2_VER_SYNC_START_FORMULA(x)      ((x)-1)
86 #define IGA2_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
87
88 /**********************************************************/
89 /* Definition IGA2 Design Method of CRTC Shadow Registers */
90 /**********************************************************/
91 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           ((x/8)-5)
92 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y)     (((x+y)/8)-1)
93 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           ((x)-2)
94 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            ((x)-1)
95 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     ((x)-1)
96 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y)     ((x+y)-1)
97 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
98 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y)      (x+y)
99
100 /* Define Register Number for IGA1 CRTC Timing */
101
102 /* location: {CR00,0,7},{CR36,3,3} */
103 #define IGA1_HOR_TOTAL_REG_NUM          2
104 /* location: {CR01,0,7} */
105 #define IGA1_HOR_ADDR_REG_NUM           1
106 /* location: {CR02,0,7} */
107 #define IGA1_HOR_BLANK_START_REG_NUM    1
108 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
109 #define IGA1_HOR_BLANK_END_REG_NUM      3
110 /* location: {CR04,0,7},{CR33,4,4} */
111 #define IGA1_HOR_SYNC_START_REG_NUM     2
112 /* location: {CR05,0,4} */
113 #define IGA1_HOR_SYNC_END_REG_NUM       1
114 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
115 #define IGA1_VER_TOTAL_REG_NUM          4
116 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
117 #define IGA1_VER_ADDR_REG_NUM           4
118 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
119 #define IGA1_VER_BLANK_START_REG_NUM    4
120 /* location: {CR16,0,7} */
121 #define IGA1_VER_BLANK_END_REG_NUM      1
122 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
123 #define IGA1_VER_SYNC_START_REG_NUM     4
124 /* location: {CR11,0,3} */
125 #define IGA1_VER_SYNC_END_REG_NUM       1
126
127 /* Define Register Number for IGA2 Shadow CRTC Timing */
128
129 /* location: {CR6D,0,7},{CR71,3,3} */
130 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2
131 /* location: {CR6E,0,7} */
132 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1
133 /* location: {CR6F,0,7},{CR71,0,2} */
134 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2
135 /* location: {CR70,0,7},{CR71,4,6} */
136 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2
137 /* location: {CR72,0,7},{CR74,4,6} */
138 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
139 /* location: {CR73,0,7},{CR74,0,2} */
140 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2
141 /* location: {CR75,0,7},{CR76,4,6} */
142 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2
143 /* location: {CR76,0,3} */
144 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1
145
146 /* Define Register Number for IGA2 CRTC Timing */
147
148 /* location: {CR50,0,7},{CR55,0,3} */
149 #define IGA2_HOR_TOTAL_REG_NUM          2
150 /* location: {CR51,0,7},{CR55,4,6} */
151 #define IGA2_HOR_ADDR_REG_NUM           2
152 /* location: {CR52,0,7},{CR54,0,2} */
153 #define IGA2_HOR_BLANK_START_REG_NUM    2
154 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
155 is reserved, so it may have problem to set 1600x1200 on IGA2. */
156 /*              Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
157 #define IGA2_HOR_BLANK_END_REG_NUM      3
158 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
159 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
160 #define IGA2_HOR_SYNC_START_REG_NUM     4
161
162 /* location: {CR57,0,7},{CR5C,6,6} */
163 #define IGA2_HOR_SYNC_END_REG_NUM       2
164 /* location: {CR58,0,7},{CR5D,0,2} */
165 #define IGA2_VER_TOTAL_REG_NUM          2
166 /* location: {CR59,0,7},{CR5D,3,5} */
167 #define IGA2_VER_ADDR_REG_NUM           2
168 /* location: {CR5A,0,7},{CR5C,0,2} */
169 #define IGA2_VER_BLANK_START_REG_NUM    2
170 /* location: {CR5E,0,7},{CR5C,3,5} */
171 #define IGA2_VER_BLANK_END_REG_NUM      2
172 /* location: {CR5E,0,7},{CR5F,5,7} */
173 #define IGA2_VER_SYNC_START_REG_NUM     2
174 /* location: {CR5F,0,4} */
175 #define IGA2_VER_SYNC_END_REG_NUM       1
176
177 /* Define Fetch Count Register*/
178
179 /* location: {SR1C,0,7},{SR1D,0,1} */
180 #define IGA1_FETCH_COUNT_REG_NUM        2
181 /* 16 bytes alignment. */
182 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16
183 /* x: H resolution, y: color depth */
184 #define IGA1_FETCH_COUNT_PATCH_VALUE    4
185 #define IGA1_FETCH_COUNT_FORMULA(x, y)   \
186         (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
187
188 /* location: {CR65,0,7},{CR67,2,3} */
189 #define IGA2_FETCH_COUNT_REG_NUM        2
190 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
191 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
192 #define IGA2_FETCH_COUNT_FORMULA(x, y)   \
193         (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
194
195 /* Staring Address*/
196
197 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
198 #define IGA1_STARTING_ADDR_REG_NUM      4
199 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
200 #define IGA2_STARTING_ADDR_REG_NUM      3
201
202 /* Define Display OFFSET*/
203 /* These value are by HW suggested value*/
204 /* location: {SR17,0,7} */
205 #define K800_IGA1_FIFO_MAX_DEPTH                384
206 /* location: {SR16,0,5},{SR16,7,7} */
207 #define K800_IGA1_FIFO_THRESHOLD                328
208 /* location: {SR18,0,5},{SR18,7,7} */
209 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296
210 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
211                                 /* because HW only 5 bits */
212 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
213
214 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
215 #define K800_IGA2_FIFO_MAX_DEPTH                384
216 /* location: {CR68,0,3},{CR95,4,6} */
217 #define K800_IGA2_FIFO_THRESHOLD                328
218 /* location: {CR92,0,3},{CR95,0,2} */
219 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296
220 /* location: {CR94,0,6} */
221 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
222
223 /* location: {SR17,0,7} */
224 #define P880_IGA1_FIFO_MAX_DEPTH                192
225 /* location: {SR16,0,5},{SR16,7,7} */
226 #define P880_IGA1_FIFO_THRESHOLD                128
227 /* location: {SR18,0,5},{SR18,7,7} */
228 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64
229 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
230                                 /* because HW only 5 bits */
231 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
232
233 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
234 #define P880_IGA2_FIFO_MAX_DEPTH                96
235 /* location: {CR68,0,3},{CR95,4,6} */
236 #define P880_IGA2_FIFO_THRESHOLD                64
237 /* location: {CR92,0,3},{CR95,0,2} */
238 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32
239 /* location: {CR94,0,6} */
240 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
241
242 /* VT3314 chipset*/
243
244 /* location: {SR17,0,7} */
245 #define CN700_IGA1_FIFO_MAX_DEPTH               96
246 /* location: {SR16,0,5},{SR16,7,7} */
247 #define CN700_IGA1_FIFO_THRESHOLD               80
248 /* location: {SR18,0,5},{SR18,7,7} */
249 #define CN700_IGA1_FIFO_HIGH_THRESHOLD          64
250 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
251                                 because HW only 5 bits */
252 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0
253 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
254 #define CN700_IGA2_FIFO_MAX_DEPTH               96
255 /* location: {CR68,0,3},{CR95,4,6} */
256 #define CN700_IGA2_FIFO_THRESHOLD               80
257 /* location: {CR92,0,3},{CR95,0,2} */
258 #define CN700_IGA2_FIFO_HIGH_THRESHOLD          32
259 /* location: {CR94,0,6} */
260 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
261
262 /* For VT3324, these values are suggested by HW */
263 /* location: {SR17,0,7} */
264 #define CX700_IGA1_FIFO_MAX_DEPTH               192
265 /* location: {SR16,0,5},{SR16,7,7} */
266 #define CX700_IGA1_FIFO_THRESHOLD               128
267 /* location: {SR18,0,5},{SR18,7,7} */
268 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128
269 /* location: {SR22,0,4} */
270 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
271
272 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
273 #define CX700_IGA2_FIFO_MAX_DEPTH               96
274 /* location: {CR68,0,3},{CR95,4,6} */
275 #define CX700_IGA2_FIFO_THRESHOLD               64
276 /* location: {CR92,0,3},{CR95,0,2} */
277 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32
278 /* location: {CR94,0,6} */
279 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
280
281 /* VT3336 chipset*/
282 /* location: {SR17,0,7} */
283 #define K8M890_IGA1_FIFO_MAX_DEPTH               360
284 /* location: {SR16,0,5},{SR16,7,7} */
285 #define K8M890_IGA1_FIFO_THRESHOLD               328
286 /* location: {SR18,0,5},{SR18,7,7} */
287 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD          296
288 /* location: {SR22,0,4}. */
289 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
290
291 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
292 #define K8M890_IGA2_FIFO_MAX_DEPTH               360
293 /* location: {CR68,0,3},{CR95,4,6} */
294 #define K8M890_IGA2_FIFO_THRESHOLD               328
295 /* location: {CR92,0,3},{CR95,0,2} */
296 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD          296
297 /* location: {CR94,0,6} */
298 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     124
299
300 /* VT3327 chipset*/
301 /* location: {SR17,0,7} */
302 #define P4M890_IGA1_FIFO_MAX_DEPTH               96
303 /* location: {SR16,0,5},{SR16,7,7} */
304 #define P4M890_IGA1_FIFO_THRESHOLD               76
305 /* location: {SR18,0,5},{SR18,7,7} */
306 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD          64
307 /* location: {SR22,0,4}. (32/4) =8 */
308 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
309 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
310 #define P4M890_IGA2_FIFO_MAX_DEPTH               96
311 /* location: {CR68,0,3},{CR95,4,6} */
312 #define P4M890_IGA2_FIFO_THRESHOLD               76
313 /* location: {CR92,0,3},{CR95,0,2} */
314 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD          64
315 /* location: {CR94,0,6} */
316 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
317
318 /* VT3364 chipset*/
319 /* location: {SR17,0,7} */
320 #define P4M900_IGA1_FIFO_MAX_DEPTH               96
321 /* location: {SR16,0,5},{SR16,7,7} */
322 #define P4M900_IGA1_FIFO_THRESHOLD               76
323 /* location: {SR18,0,5},{SR18,7,7} */
324 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD          76
325 /* location: {SR22,0,4}. */
326 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
327 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
328 #define P4M900_IGA2_FIFO_MAX_DEPTH               96
329 /* location: {CR68,0,3},{CR95,4,6} */
330 #define P4M900_IGA2_FIFO_THRESHOLD               76
331 /* location: {CR92,0,3},{CR95,0,2} */
332 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD          76
333 /* location: {CR94,0,6} */
334 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
335
336 /* For VT3353, these values are suggested by HW */
337 /* location: {SR17,0,7} */
338 #define VX800_IGA1_FIFO_MAX_DEPTH               192
339 /* location: {SR16,0,5},{SR16,7,7} */
340 #define VX800_IGA1_FIFO_THRESHOLD               152
341 /* location: {SR18,0,5},{SR18,7,7} */
342 #define VX800_IGA1_FIFO_HIGH_THRESHOLD          152
343 /* location: {SR22,0,4} */
344 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      64
345 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
346 #define VX800_IGA2_FIFO_MAX_DEPTH               96
347 /* location: {CR68,0,3},{CR95,4,6} */
348 #define VX800_IGA2_FIFO_THRESHOLD               64
349 /* location: {CR92,0,3},{CR95,0,2} */
350 #define VX800_IGA2_FIFO_HIGH_THRESHOLD          32
351 /* location: {CR94,0,6} */
352 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
353
354 /* For VT3409 */
355 #define VX855_IGA1_FIFO_MAX_DEPTH               400
356 #define VX855_IGA1_FIFO_THRESHOLD               320
357 #define VX855_IGA1_FIFO_HIGH_THRESHOLD          320
358 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
359
360 #define VX855_IGA2_FIFO_MAX_DEPTH               200
361 #define VX855_IGA2_FIFO_THRESHOLD               160
362 #define VX855_IGA2_FIFO_HIGH_THRESHOLD          160
363 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
364
365 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
366 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
367 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
368 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
369
370 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
371 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
372 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
373 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
374
375 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)-1)
376 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
377 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
378 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
379 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   (((x/2)/4)-1)
380 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
381 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
382 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
383
384 /************************************************************************/
385 /*  LCD Timing                                                          */
386 /************************************************************************/
387
388 /* 500 ms = 500000 us */
389 #define LCD_POWER_SEQ_TD0               500000
390 /* 50 ms = 50000 us */
391 #define LCD_POWER_SEQ_TD1               50000
392 /* 0 us */
393 #define LCD_POWER_SEQ_TD2               0
394 /* 210 ms = 210000 us */
395 #define LCD_POWER_SEQ_TD3               210000
396 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
397 #define CLE266_POWER_SEQ_UNIT           71
398 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
399 #define K800_POWER_SEQ_UNIT             142
400 /* 2^13 * (1/14.31818M) = 572.1 us */
401 #define P880_POWER_SEQ_UNIT             572
402
403 #define CLE266_POWER_SEQ_FORMULA(x)     ((x)/CLE266_POWER_SEQ_UNIT)
404 #define K800_POWER_SEQ_FORMULA(x)       ((x)/K800_POWER_SEQ_UNIT)
405 #define P880_POWER_SEQ_FORMULA(x)       ((x)/P880_POWER_SEQ_UNIT)
406
407 /* location: {CR8B,0,7},{CR8F,0,3} */
408 #define LCD_POWER_SEQ_TD0_REG_NUM       2
409 /* location: {CR8C,0,7},{CR8F,4,7} */
410 #define LCD_POWER_SEQ_TD1_REG_NUM       2
411 /* location: {CR8D,0,7},{CR90,0,3} */
412 #define LCD_POWER_SEQ_TD2_REG_NUM       2
413 /* location: {CR8E,0,7},{CR90,4,7} */
414 #define LCD_POWER_SEQ_TD3_REG_NUM       2
415
416 /* LCD Scaling factor*/
417 /* x: indicate setting horizontal size*/
418 /* y: indicate panel horizontal size*/
419
420 /* Horizontal scaling factor 10 bits (2^10) */
421 #define CLE266_LCD_HOR_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
422 /* Vertical scaling factor 10 bits (2^10) */
423 #define CLE266_LCD_VER_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
424 /* Horizontal scaling factor 10 bits (2^12) */
425 #define K800_LCD_HOR_SCF_FORMULA(x, y)     (((x-1)*4096)/(y-1))
426 /* Vertical scaling factor 10 bits (2^11) */
427 #define K800_LCD_VER_SCF_FORMULA(x, y)     (((x-1)*2048)/(y-1))
428
429 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
430 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3
431 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
432 #define LCD_VER_SCALING_FACTOR_REG_NUM  3
433 /* location: {CR77,0,7},{CR79,4,5} */
434 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2
435 /* location: {CR78,0,7},{CR79,6,7} */
436 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2
437
438 /************************************************
439  *****     Define IGA1 Display Timing       *****
440  ************************************************/
441 struct io_register {
442         u8 io_addr;
443         u8 start_bit;
444         u8 end_bit;
445 };
446
447 /* IGA1 Horizontal Total */
448 struct iga1_hor_total {
449         int reg_num;
450         struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
451 };
452
453 /* IGA1 Horizontal Addressable Video */
454 struct iga1_hor_addr {
455         int reg_num;
456         struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
457 };
458
459 /* IGA1 Horizontal Blank Start */
460 struct iga1_hor_blank_start {
461         int reg_num;
462         struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
463 };
464
465 /* IGA1 Horizontal Blank End */
466 struct iga1_hor_blank_end {
467         int reg_num;
468         struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
469 };
470
471 /* IGA1 Horizontal Sync Start */
472 struct iga1_hor_sync_start {
473         int reg_num;
474         struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
475 };
476
477 /* IGA1 Horizontal Sync End */
478 struct iga1_hor_sync_end {
479         int reg_num;
480         struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
481 };
482
483 /* IGA1 Vertical Total */
484 struct iga1_ver_total {
485         int reg_num;
486         struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
487 };
488
489 /* IGA1 Vertical Addressable Video */
490 struct iga1_ver_addr {
491         int reg_num;
492         struct io_register reg[IGA1_VER_ADDR_REG_NUM];
493 };
494
495 /* IGA1 Vertical Blank Start */
496 struct iga1_ver_blank_start {
497         int reg_num;
498         struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
499 };
500
501 /* IGA1 Vertical Blank End */
502 struct iga1_ver_blank_end {
503         int reg_num;
504         struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
505 };
506
507 /* IGA1 Vertical Sync Start */
508 struct iga1_ver_sync_start {
509         int reg_num;
510         struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
511 };
512
513 /* IGA1 Vertical Sync End */
514 struct iga1_ver_sync_end {
515         int reg_num;
516         struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
517 };
518
519 /*****************************************************
520 **      Define IGA2 Shadow Display Timing         ****
521 *****************************************************/
522
523 /* IGA2 Shadow Horizontal Total */
524 struct iga2_shadow_hor_total {
525         int reg_num;
526         struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
527 };
528
529 /* IGA2 Shadow Horizontal Blank End */
530 struct iga2_shadow_hor_blank_end {
531         int reg_num;
532         struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
533 };
534
535 /* IGA2 Shadow Vertical Total */
536 struct iga2_shadow_ver_total {
537         int reg_num;
538         struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
539 };
540
541 /* IGA2 Shadow Vertical Addressable Video */
542 struct iga2_shadow_ver_addr {
543         int reg_num;
544         struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
545 };
546
547 /* IGA2 Shadow Vertical Blank Start */
548 struct iga2_shadow_ver_blank_start {
549         int reg_num;
550         struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
551 };
552
553 /* IGA2 Shadow Vertical Blank End */
554 struct iga2_shadow_ver_blank_end {
555         int reg_num;
556         struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
557 };
558
559 /* IGA2 Shadow Vertical Sync Start */
560 struct iga2_shadow_ver_sync_start {
561         int reg_num;
562         struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
563 };
564
565 /* IGA2 Shadow Vertical Sync End */
566 struct iga2_shadow_ver_sync_end {
567         int reg_num;
568         struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
569 };
570
571 /*****************************************************
572 **      Define IGA2 Display Timing                ****
573 ******************************************************/
574
575 /* IGA2 Horizontal Total */
576 struct iga2_hor_total {
577         int reg_num;
578         struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
579 };
580
581 /* IGA2 Horizontal Addressable Video */
582 struct iga2_hor_addr {
583         int reg_num;
584         struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
585 };
586
587 /* IGA2 Horizontal Blank Start */
588 struct iga2_hor_blank_start {
589         int reg_num;
590         struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
591 };
592
593 /* IGA2 Horizontal Blank End */
594 struct iga2_hor_blank_end {
595         int reg_num;
596         struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
597 };
598
599 /* IGA2 Horizontal Sync Start */
600 struct iga2_hor_sync_start {
601         int reg_num;
602         struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
603 };
604
605 /* IGA2 Horizontal Sync End */
606 struct iga2_hor_sync_end {
607         int reg_num;
608         struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
609 };
610
611 /* IGA2 Vertical Total */
612 struct iga2_ver_total {
613         int reg_num;
614         struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
615 };
616
617 /* IGA2 Vertical Addressable Video */
618 struct iga2_ver_addr {
619         int reg_num;
620         struct io_register reg[IGA2_VER_ADDR_REG_NUM];
621 };
622
623 /* IGA2 Vertical Blank Start */
624 struct iga2_ver_blank_start {
625         int reg_num;
626         struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
627 };
628
629 /* IGA2 Vertical Blank End */
630 struct iga2_ver_blank_end {
631         int reg_num;
632         struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
633 };
634
635 /* IGA2 Vertical Sync Start */
636 struct iga2_ver_sync_start {
637         int reg_num;
638         struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
639 };
640
641 /* IGA2 Vertical Sync End */
642 struct iga2_ver_sync_end {
643         int reg_num;
644         struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
645 };
646
647 /* IGA1 Fetch Count Register */
648 struct iga1_fetch_count {
649         int reg_num;
650         struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
651 };
652
653 /* IGA2 Fetch Count Register */
654 struct iga2_fetch_count {
655         int reg_num;
656         struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
657 };
658
659 struct fetch_count {
660         struct iga1_fetch_count iga1_fetch_count_reg;
661         struct iga2_fetch_count iga2_fetch_count_reg;
662 };
663
664 /* Starting Address Register */
665 struct iga1_starting_addr {
666         int reg_num;
667         struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
668 };
669
670 struct iga2_starting_addr {
671         int reg_num;
672         struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
673 };
674
675 struct starting_addr {
676         struct iga1_starting_addr iga1_starting_addr_reg;
677         struct iga2_starting_addr iga2_starting_addr_reg;
678 };
679
680 /* LCD Power Sequence Timer */
681 struct lcd_pwd_seq_td0 {
682         int reg_num;
683         struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
684 };
685
686 struct lcd_pwd_seq_td1 {
687         int reg_num;
688         struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
689 };
690
691 struct lcd_pwd_seq_td2 {
692         int reg_num;
693         struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
694 };
695
696 struct lcd_pwd_seq_td3 {
697         int reg_num;
698         struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
699 };
700
701 struct _lcd_pwd_seq_timer {
702         struct lcd_pwd_seq_td0 td0;
703         struct lcd_pwd_seq_td1 td1;
704         struct lcd_pwd_seq_td2 td2;
705         struct lcd_pwd_seq_td3 td3;
706 };
707
708 /* LCD Scaling Factor */
709 struct _lcd_hor_scaling_factor {
710         int reg_num;
711         struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
712 };
713
714 struct _lcd_ver_scaling_factor {
715         int reg_num;
716         struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
717 };
718
719 struct _lcd_scaling_factor {
720         struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
721         struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
722 };
723
724 struct pll_config {
725         u16 multiplier;
726         u8 divisor;
727         u8 rshift;
728 };
729
730 struct pll_map {
731         u32 clk;
732         struct pll_config cle266_pll;
733         struct pll_config k800_pll;
734         struct pll_config cx700_pll;
735         struct pll_config vx855_pll;
736 };
737
738 struct rgbLUT {
739         u8 red;
740         u8 green;
741         u8 blue;
742 };
743
744 struct lcd_pwd_seq_timer {
745         u16 td0;
746         u16 td1;
747         u16 td2;
748         u16 td3;
749 };
750
751 /* Display FIFO Relation Registers*/
752 struct iga1_fifo_depth_select {
753         int reg_num;
754         struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
755 };
756
757 struct iga1_fifo_threshold_select {
758         int reg_num;
759         struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
760 };
761
762 struct iga1_fifo_high_threshold_select {
763         int reg_num;
764         struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
765 };
766
767 struct iga1_display_queue_expire_num {
768         int reg_num;
769         struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
770 };
771
772 struct iga2_fifo_depth_select {
773         int reg_num;
774         struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
775 };
776
777 struct iga2_fifo_threshold_select {
778         int reg_num;
779         struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
780 };
781
782 struct iga2_fifo_high_threshold_select {
783         int reg_num;
784         struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
785 };
786
787 struct iga2_display_queue_expire_num {
788         int reg_num;
789         struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
790 };
791
792 struct fifo_depth_select {
793         struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
794         struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
795 };
796
797 struct fifo_threshold_select {
798         struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
799         struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
800 };
801
802 struct fifo_high_threshold_select {
803         struct iga1_fifo_high_threshold_select
804          iga1_fifo_high_threshold_select_reg;
805         struct iga2_fifo_high_threshold_select
806          iga2_fifo_high_threshold_select_reg;
807 };
808
809 struct display_queue_expire_num {
810         struct iga1_display_queue_expire_num
811          iga1_display_queue_expire_num_reg;
812         struct iga2_display_queue_expire_num
813          iga2_display_queue_expire_num_reg;
814 };
815
816 struct iga1_crtc_timing {
817         struct iga1_hor_total hor_total;
818         struct iga1_hor_addr hor_addr;
819         struct iga1_hor_blank_start hor_blank_start;
820         struct iga1_hor_blank_end hor_blank_end;
821         struct iga1_hor_sync_start hor_sync_start;
822         struct iga1_hor_sync_end hor_sync_end;
823         struct iga1_ver_total ver_total;
824         struct iga1_ver_addr ver_addr;
825         struct iga1_ver_blank_start ver_blank_start;
826         struct iga1_ver_blank_end ver_blank_end;
827         struct iga1_ver_sync_start ver_sync_start;
828         struct iga1_ver_sync_end ver_sync_end;
829 };
830
831 struct iga2_shadow_crtc_timing {
832         struct iga2_shadow_hor_total hor_total_shadow;
833         struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
834         struct iga2_shadow_ver_total ver_total_shadow;
835         struct iga2_shadow_ver_addr ver_addr_shadow;
836         struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
837         struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
838         struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
839         struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
840 };
841
842 struct iga2_crtc_timing {
843         struct iga2_hor_total hor_total;
844         struct iga2_hor_addr hor_addr;
845         struct iga2_hor_blank_start hor_blank_start;
846         struct iga2_hor_blank_end hor_blank_end;
847         struct iga2_hor_sync_start hor_sync_start;
848         struct iga2_hor_sync_end hor_sync_end;
849         struct iga2_ver_total ver_total;
850         struct iga2_ver_addr ver_addr;
851         struct iga2_ver_blank_start ver_blank_start;
852         struct iga2_ver_blank_end ver_blank_end;
853         struct iga2_ver_sync_start ver_sync_start;
854         struct iga2_ver_sync_end ver_sync_end;
855 };
856
857 /* device ID */
858 #define CLE266_FUNCTION3    0x3123
859 #define KM400_FUNCTION3     0x3205
860 #define CN400_FUNCTION2     0x2259
861 #define CN400_FUNCTION3     0x3259
862 /* support VT3314 chipset */
863 #define CN700_FUNCTION2     0x2314
864 #define CN700_FUNCTION3     0x3208
865 /* VT3324 chipset */
866 #define CX700_FUNCTION2     0x2324
867 #define CX700_FUNCTION3     0x3324
868 /* VT3204 chipset*/
869 #define KM800_FUNCTION3      0x3204
870 /* VT3336 chipset*/
871 #define KM890_FUNCTION3      0x3336
872 /* VT3327 chipset*/
873 #define P4M890_FUNCTION3     0x3327
874 /* VT3293 chipset*/
875 #define CN750_FUNCTION3     0x3208
876 /* VT3364 chipset*/
877 #define P4M900_FUNCTION3    0x3364
878 /* VT3353 chipset*/
879 #define VX800_FUNCTION3     0x3353
880 /* VT3409 chipset*/
881 #define VX855_FUNCTION3     0x3409
882
883 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
884
885 struct IODATA {
886         u8 Index;
887         u8 Mask;
888         u8 Data;
889 };
890
891 struct pci_device_id_info {
892         u32 vendor;
893         u32 device;
894         u32 chip_index;
895 };
896
897 struct via_device_mapping {
898         u32 device;
899         const char *name;
900 };
901
902 extern unsigned int viafb_second_virtual_xres;
903 extern int viafb_SAMM_ON;
904 extern int viafb_dual_fb;
905 extern int viafb_LCD2_ON;
906 extern int viafb_LCD_ON;
907 extern int viafb_DVI_ON;
908 extern int viafb_hotplug;
909
910 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
911         struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
912
913 void viafb_set_vclock(u32 CLK, int set_iga);
914 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
915         struct io_register *reg,
916               int io_type);
917 void via_set_source(u32 devices, u8 iga);
918 void via_set_state(u32 devices, u8 state);
919 void via_set_sync_polarity(u32 devices, u8 polarity);
920 u32 via_parse_odev(char *input, char **end);
921 void via_odev_to_seq(struct seq_file *m, u32 odev);
922 void init_ad9389(void);
923 /* Access I/O Function */
924 void viafb_lock_crt(void);
925 void viafb_unlock_crt(void);
926 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
927 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
928 u32 viafb_get_clk_value(int clk);
929 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
930 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
931                                         *p_gfx_dpa_setting);
932
933 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
934         struct VideoModeTable *vmode_tbl1, int video_bpp1);
935 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
936         struct VideoModeTable *vmode_tbl);
937 void __devinit viafb_init_chip_info(int chip_type);
938 void __devinit viafb_init_dac(int set_iga);
939 int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
940 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
941 void viafb_update_device_setting(int hres, int vres, int bpp,
942                            int vmode_refresh, int flag);
943
944 void viafb_set_iga_path(void);
945 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
946 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
947 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
948
949 #endif /* __HW_H__ */