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[~shefty/rdma-dev.git] / drivers / video / via / lcd.c
1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21 #include <linux/via-core.h>
22 #include <linux/via_i2c.h>
23 #include "global.h"
24 #include "lcdtbl.h"
25
26 #define viafb_compact_res(x, y) (((x)<<16)|(y))
27
28 static struct _lcd_scaling_factor lcd_scaling_factor = {
29         /* LCD Horizontal Scaling Factor Register */
30         {LCD_HOR_SCALING_FACTOR_REG_NUM,
31          {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
32         /* LCD Vertical Scaling Factor Register */
33         {LCD_VER_SCALING_FACTOR_REG_NUM,
34          {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
35 };
36 static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
37         /* LCD Horizontal Scaling Factor Register */
38         {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
39         /* LCD Vertical Scaling Factor Register */
40         {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
41 };
42
43 static int check_lvds_chip(int device_id_subaddr, int device_id);
44 static bool lvds_identify_integratedlvds(void);
45 static void fp_id_to_vindex(int panel_id);
46 static int lvds_register_read(int index);
47 static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
48                       int panel_vres);
49 static void via_pitch_alignment_patch_lcd(
50         struct lvds_setting_information *plvds_setting_info,
51                                    struct lvds_chip_information
52                                    *plvds_chip_info);
53 static void lcd_patch_skew_dvp0(struct lvds_setting_information
54                          *plvds_setting_info,
55                          struct lvds_chip_information *plvds_chip_info);
56 static void lcd_patch_skew_dvp1(struct lvds_setting_information
57                          *plvds_setting_info,
58                          struct lvds_chip_information *plvds_chip_info);
59 static void lcd_patch_skew(struct lvds_setting_information
60         *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
61
62 static void integrated_lvds_disable(struct lvds_setting_information
63                              *plvds_setting_info,
64                              struct lvds_chip_information *plvds_chip_info);
65 static void integrated_lvds_enable(struct lvds_setting_information
66                             *plvds_setting_info,
67                             struct lvds_chip_information *plvds_chip_info);
68 static void lcd_powersequence_off(void);
69 static void lcd_powersequence_on(void);
70 static void fill_lcd_format(void);
71 static void check_diport_of_integrated_lvds(
72         struct lvds_chip_information *plvds_chip_info,
73                                      struct lvds_setting_information
74                                      *plvds_setting_info);
75 static struct display_timing lcd_centering_timging(struct display_timing
76                                             mode_crt_reg,
77                                            struct display_timing panel_crt_reg);
78
79 static int check_lvds_chip(int device_id_subaddr, int device_id)
80 {
81         if (lvds_register_read(device_id_subaddr) == device_id)
82                 return OK;
83         else
84                 return FAIL;
85 }
86
87 void viafb_init_lcd_size(void)
88 {
89         DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
90         DEBUG_MSG(KERN_INFO
91                 "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
92                 viaparinfo->lvds_setting_info->get_lcd_size_method);
93
94         switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
95         case GET_LCD_SIZE_BY_SYSTEM_BIOS:
96                 break;
97         case GET_LCD_SZIE_BY_HW_STRAPPING:
98                 break;
99         case GET_LCD_SIZE_BY_VGA_BIOS:
100                 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
101                 fp_id_to_vindex(viafb_lcd_panel_id);
102                 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
103                           viaparinfo->lvds_setting_info->lcd_panel_id);
104                 break;
105         case GET_LCD_SIZE_BY_USER_SETTING:
106                 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
107                 fp_id_to_vindex(viafb_lcd_panel_id);
108                 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
109                           viaparinfo->lvds_setting_info->lcd_panel_id);
110                 break;
111         default:
112                 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
113                 viaparinfo->lvds_setting_info->lcd_panel_id =
114                         LCD_PANEL_ID1_800X600;
115                 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
116         }
117         viaparinfo->lvds_setting_info2->lcd_panel_id =
118                 viaparinfo->lvds_setting_info->lcd_panel_id;
119         viaparinfo->lvds_setting_info2->lcd_panel_hres =
120                 viaparinfo->lvds_setting_info->lcd_panel_hres;
121         viaparinfo->lvds_setting_info2->lcd_panel_vres =
122                 viaparinfo->lvds_setting_info->lcd_panel_vres;
123         viaparinfo->lvds_setting_info2->device_lcd_dualedge =
124             viaparinfo->lvds_setting_info->device_lcd_dualedge;
125         viaparinfo->lvds_setting_info2->LCDDithering =
126                 viaparinfo->lvds_setting_info->LCDDithering;
127 }
128
129 static bool lvds_identify_integratedlvds(void)
130 {
131         if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
132                 /* Two dual channel LCD (Internal LVDS + External LVDS): */
133                 /* If we have an external LVDS, such as VT1636, we should
134                    have its chip ID already. */
135                 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
136                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
137                             INTEGRATED_LVDS;
138                         DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
139                                   "(Internal LVDS + External LVDS)\n");
140                 } else {
141                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
142                             INTEGRATED_LVDS;
143                         DEBUG_MSG(KERN_INFO "Not found external LVDS, "
144                                   "so can't support two dual channel LVDS!\n");
145                 }
146         } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
147                 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
148                 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
149                 INTEGRATED_LVDS;
150                 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
151                         INTEGRATED_LVDS;
152                 DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
153                           "(Internal LVDS + Internal LVDS)\n");
154         } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
155                 /* If we have found external LVDS, just use it,
156                    otherwise, we will use internal LVDS as default. */
157                 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
158                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
159                             INTEGRATED_LVDS;
160                         DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
161                 }
162         } else {
163                 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
164                         NON_LVDS_TRANSMITTER;
165                 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
166                 return false;
167         }
168
169         return true;
170 }
171
172 int viafb_lvds_trasmitter_identify(void)
173 {
174         if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
175                 viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
176                 DEBUG_MSG(KERN_INFO
177                           "Found VIA VT1636 LVDS on port i2c 0x31\n");
178         } else {
179                 if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
180                         viaparinfo->chip_info->lvds_chip_info.i2c_port =
181                                 VIA_PORT_2C;
182                         DEBUG_MSG(KERN_INFO
183                                   "Found VIA VT1636 LVDS on port gpio 0x2c\n");
184                 }
185         }
186
187         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
188                 lvds_identify_integratedlvds();
189
190         if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
191                 return true;
192         /* Check for VT1631: */
193         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
194         viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
195                 VT1631_LVDS_I2C_ADDR;
196
197         if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
198                 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
199                 DEBUG_MSG(KERN_INFO "\n %2d",
200                           viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
201                 DEBUG_MSG(KERN_INFO "\n %2d",
202                           viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
203                 return OK;
204         }
205
206         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
207                 NON_LVDS_TRANSMITTER;
208         viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
209                 VT1631_LVDS_I2C_ADDR;
210         return FAIL;
211 }
212
213 static void fp_id_to_vindex(int panel_id)
214 {
215         DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
216
217         if (panel_id > LCD_PANEL_ID_MAXIMUM)
218                 viafb_lcd_panel_id = panel_id =
219                 viafb_read_reg(VIACR, CR3F) & 0x0F;
220
221         switch (panel_id) {
222         case 0x0:
223                 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
224                 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
225                 viaparinfo->lvds_setting_info->lcd_panel_id =
226                         LCD_PANEL_ID0_640X480;
227                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
228                 viaparinfo->lvds_setting_info->LCDDithering = 1;
229                 break;
230         case 0x1:
231                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
232                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
233                 viaparinfo->lvds_setting_info->lcd_panel_id =
234                         LCD_PANEL_ID1_800X600;
235                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
236                 viaparinfo->lvds_setting_info->LCDDithering = 1;
237                 break;
238         case 0x2:
239                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
240                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
241                 viaparinfo->lvds_setting_info->lcd_panel_id =
242                         LCD_PANEL_ID2_1024X768;
243                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
244                 viaparinfo->lvds_setting_info->LCDDithering = 1;
245                 break;
246         case 0x3:
247                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
248                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
249                 viaparinfo->lvds_setting_info->lcd_panel_id =
250                         LCD_PANEL_ID3_1280X768;
251                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
252                 viaparinfo->lvds_setting_info->LCDDithering = 1;
253                 break;
254         case 0x4:
255                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
256                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
257                 viaparinfo->lvds_setting_info->lcd_panel_id =
258                         LCD_PANEL_ID4_1280X1024;
259                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
260                 viaparinfo->lvds_setting_info->LCDDithering = 1;
261                 break;
262         case 0x5:
263                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
264                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
265                 viaparinfo->lvds_setting_info->lcd_panel_id =
266                         LCD_PANEL_ID5_1400X1050;
267                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
268                 viaparinfo->lvds_setting_info->LCDDithering = 1;
269                 break;
270         case 0x6:
271                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
272                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
273                 viaparinfo->lvds_setting_info->lcd_panel_id =
274                         LCD_PANEL_ID6_1600X1200;
275                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
276                 viaparinfo->lvds_setting_info->LCDDithering = 1;
277                 break;
278         case 0x8:
279                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
280                 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
281                 viaparinfo->lvds_setting_info->lcd_panel_id =
282                         LCD_PANEL_IDA_800X480;
283                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
284                 viaparinfo->lvds_setting_info->LCDDithering = 1;
285                 break;
286         case 0x9:
287                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
288                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
289                 viaparinfo->lvds_setting_info->lcd_panel_id =
290                         LCD_PANEL_ID2_1024X768;
291                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
292                 viaparinfo->lvds_setting_info->LCDDithering = 1;
293                 break;
294         case 0xA:
295                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
296                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
297                 viaparinfo->lvds_setting_info->lcd_panel_id =
298                         LCD_PANEL_ID2_1024X768;
299                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
300                 viaparinfo->lvds_setting_info->LCDDithering = 0;
301                 break;
302         case 0xB:
303                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
304                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
305                 viaparinfo->lvds_setting_info->lcd_panel_id =
306                         LCD_PANEL_ID2_1024X768;
307                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
308                 viaparinfo->lvds_setting_info->LCDDithering = 0;
309                 break;
310         case 0xC:
311                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
312                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
313                 viaparinfo->lvds_setting_info->lcd_panel_id =
314                         LCD_PANEL_ID3_1280X768;
315                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
316                 viaparinfo->lvds_setting_info->LCDDithering = 0;
317                 break;
318         case 0xD:
319                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
320                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
321                 viaparinfo->lvds_setting_info->lcd_panel_id =
322                         LCD_PANEL_ID4_1280X1024;
323                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
324                 viaparinfo->lvds_setting_info->LCDDithering = 0;
325                 break;
326         case 0xE:
327                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
328                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
329                 viaparinfo->lvds_setting_info->lcd_panel_id =
330                         LCD_PANEL_ID5_1400X1050;
331                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
332                 viaparinfo->lvds_setting_info->LCDDithering = 0;
333                 break;
334         case 0xF:
335                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
336                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
337                 viaparinfo->lvds_setting_info->lcd_panel_id =
338                         LCD_PANEL_ID6_1600X1200;
339                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
340                 viaparinfo->lvds_setting_info->LCDDithering = 0;
341                 break;
342         case 0x10:
343                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
344                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
345                 viaparinfo->lvds_setting_info->lcd_panel_id =
346                         LCD_PANEL_ID7_1366X768;
347                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
348                 viaparinfo->lvds_setting_info->LCDDithering = 0;
349                 break;
350         case 0x11:
351                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
352                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
353                 viaparinfo->lvds_setting_info->lcd_panel_id =
354                         LCD_PANEL_ID8_1024X600;
355                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
356                 viaparinfo->lvds_setting_info->LCDDithering = 1;
357                 break;
358         case 0x12:
359                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
360                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
361                 viaparinfo->lvds_setting_info->lcd_panel_id =
362                         LCD_PANEL_ID3_1280X768;
363                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
364                 viaparinfo->lvds_setting_info->LCDDithering = 1;
365                 break;
366         case 0x13:
367                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
368                 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
369                 viaparinfo->lvds_setting_info->lcd_panel_id =
370                         LCD_PANEL_ID9_1280X800;
371                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
372                 viaparinfo->lvds_setting_info->LCDDithering = 1;
373                 break;
374         case 0x14:
375                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
376                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
377                 viaparinfo->lvds_setting_info->lcd_panel_id =
378                         LCD_PANEL_IDB_1360X768;
379                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
380                 viaparinfo->lvds_setting_info->LCDDithering = 0;
381                 break;
382         case 0x15:
383                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
384                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
385                 viaparinfo->lvds_setting_info->lcd_panel_id =
386                         LCD_PANEL_ID3_1280X768;
387                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
388                 viaparinfo->lvds_setting_info->LCDDithering = 0;
389                 break;
390         case 0x16:
391                 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
392                 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
393                 viaparinfo->lvds_setting_info->lcd_panel_id =
394                         LCD_PANEL_IDC_480X640;
395                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
396                 viaparinfo->lvds_setting_info->LCDDithering = 1;
397                 break;
398         case 0x17:
399                 /* OLPC XO-1.5 panel */
400                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
401                 viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
402                 viaparinfo->lvds_setting_info->lcd_panel_id =
403                         LCD_PANEL_IDD_1200X900;
404                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
405                 viaparinfo->lvds_setting_info->LCDDithering = 0;
406                 break;
407         default:
408                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
409                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
410                 viaparinfo->lvds_setting_info->lcd_panel_id =
411                         LCD_PANEL_ID1_800X600;
412                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
413                 viaparinfo->lvds_setting_info->LCDDithering = 1;
414         }
415 }
416
417 static int lvds_register_read(int index)
418 {
419         u8 data;
420
421         viafb_i2c_readbyte(VIA_PORT_2C,
422                         (u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
423                         (u8) index, &data);
424         return data;
425 }
426
427 static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
428                       int panel_vres)
429 {
430         int reg_value = 0;
431         int viafb_load_reg_num;
432         struct io_register *reg = NULL;
433
434         DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
435
436         /* LCD Scaling Enable */
437         viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
438
439         /* Check if expansion for horizontal */
440         if (set_hres < panel_hres) {
441                 /* Load Horizontal Scaling Factor */
442                 switch (viaparinfo->chip_info->gfx_chip_name) {
443                 case UNICHROME_CLE266:
444                 case UNICHROME_K400:
445                         reg_value =
446                             CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
447                         viafb_load_reg_num =
448                             lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
449                             reg_num;
450                         reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
451                         viafb_load_reg(reg_value,
452                                 viafb_load_reg_num, reg, VIACR);
453                         break;
454                 case UNICHROME_K800:
455                 case UNICHROME_PM800:
456                 case UNICHROME_CN700:
457                 case UNICHROME_CX700:
458                 case UNICHROME_K8M890:
459                 case UNICHROME_P4M890:
460                 case UNICHROME_P4M900:
461                 case UNICHROME_CN750:
462                 case UNICHROME_VX800:
463                 case UNICHROME_VX855:
464                         reg_value =
465                             K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
466                         /* Horizontal scaling enabled */
467                         viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
468                         viafb_load_reg_num =
469                             lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
470                         reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
471                         viafb_load_reg(reg_value,
472                                 viafb_load_reg_num, reg, VIACR);
473                         break;
474                 }
475
476                 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
477         } else {
478                 /* Horizontal scaling disabled */
479                 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
480         }
481
482         /* Check if expansion for vertical */
483         if (set_vres < panel_vres) {
484                 /* Load Vertical Scaling Factor */
485                 switch (viaparinfo->chip_info->gfx_chip_name) {
486                 case UNICHROME_CLE266:
487                 case UNICHROME_K400:
488                         reg_value =
489                             CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
490                         viafb_load_reg_num =
491                             lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
492                             reg_num;
493                         reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
494                         viafb_load_reg(reg_value,
495                                 viafb_load_reg_num, reg, VIACR);
496                         break;
497                 case UNICHROME_K800:
498                 case UNICHROME_PM800:
499                 case UNICHROME_CN700:
500                 case UNICHROME_CX700:
501                 case UNICHROME_K8M890:
502                 case UNICHROME_P4M890:
503                 case UNICHROME_P4M900:
504                 case UNICHROME_CN750:
505                 case UNICHROME_VX800:
506                 case UNICHROME_VX855:
507                         reg_value =
508                             K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
509                         /* Vertical scaling enabled */
510                         viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
511                         viafb_load_reg_num =
512                             lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
513                         reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
514                         viafb_load_reg(reg_value,
515                                 viafb_load_reg_num, reg, VIACR);
516                         break;
517                 }
518
519                 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
520         } else {
521                 /* Vertical scaling disabled */
522                 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
523         }
524 }
525
526 static void via_pitch_alignment_patch_lcd(
527         struct lvds_setting_information *plvds_setting_info,
528                                    struct lvds_chip_information
529                                    *plvds_chip_info)
530 {
531         unsigned char cr13, cr35, cr65, cr66, cr67;
532         unsigned long dwScreenPitch = 0;
533         unsigned long dwPitch;
534
535         dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
536         if (dwPitch & 0x1F) {
537                 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
538                 if (plvds_setting_info->iga_path == IGA2) {
539                         if (plvds_setting_info->bpp > 8) {
540                                 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
541                                 viafb_write_reg(CR66, VIACR, cr66);
542                                 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
543                                 cr67 |=
544                                     (unsigned
545                                      char)((dwScreenPitch & 0x300) >> 8);
546                                 viafb_write_reg(CR67, VIACR, cr67);
547                         }
548
549                         /* Fetch Count */
550                         cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
551                         cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
552                         viafb_write_reg(CR67, VIACR, cr67);
553                         cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
554                         cr65 += 2;
555                         viafb_write_reg(CR65, VIACR, cr65);
556                 } else {
557                         if (plvds_setting_info->bpp > 8) {
558                                 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
559                                 viafb_write_reg(CR13, VIACR, cr13);
560                                 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
561                                 cr35 |=
562                                     (unsigned
563                                      char)((dwScreenPitch & 0x700) >> 3);
564                                 viafb_write_reg(CR35, VIACR, cr35);
565                         }
566                 }
567         }
568 }
569 static void lcd_patch_skew_dvp0(struct lvds_setting_information
570                          *plvds_setting_info,
571                          struct lvds_chip_information *plvds_chip_info)
572 {
573         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
574                 switch (viaparinfo->chip_info->gfx_chip_name) {
575                 case UNICHROME_P4M900:
576                         viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
577                                                     plvds_chip_info);
578                         break;
579                 case UNICHROME_P4M890:
580                         viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
581                                                     plvds_chip_info);
582                         break;
583                 }
584         }
585 }
586 static void lcd_patch_skew_dvp1(struct lvds_setting_information
587                          *plvds_setting_info,
588                          struct lvds_chip_information *plvds_chip_info)
589 {
590         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
591                 switch (viaparinfo->chip_info->gfx_chip_name) {
592                 case UNICHROME_CX700:
593                         viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
594                                                     plvds_chip_info);
595                         break;
596                 }
597         }
598 }
599 static void lcd_patch_skew(struct lvds_setting_information
600         *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
601 {
602         DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
603         switch (plvds_chip_info->output_interface) {
604         case INTERFACE_DVP0:
605                 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
606                 break;
607         case INTERFACE_DVP1:
608                 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
609                 break;
610         case INTERFACE_DFP_LOW:
611                 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
612                         viafb_write_reg_mask(CR99, VIACR, 0x08,
613                                        BIT0 + BIT1 + BIT2 + BIT3);
614                 }
615                 break;
616         }
617 }
618
619 /* LCD Set Mode */
620 void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
621                   struct lvds_setting_information *plvds_setting_info,
622                   struct lvds_chip_information *plvds_chip_info)
623 {
624         int set_iga = plvds_setting_info->iga_path;
625         int mode_bpp = plvds_setting_info->bpp;
626         int set_hres = plvds_setting_info->h_active;
627         int set_vres = plvds_setting_info->v_active;
628         int panel_hres = plvds_setting_info->lcd_panel_hres;
629         int panel_vres = plvds_setting_info->lcd_panel_vres;
630         u32 pll_D_N;
631         struct display_timing mode_crt_reg, panel_crt_reg;
632         struct crt_mode_table *panel_crt_table = NULL;
633         struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
634                 panel_vres);
635
636         DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
637         /* Get mode table */
638         mode_crt_reg = mode_crt_table->crtc;
639         /* Get panel table Pointer */
640         panel_crt_table = vmode_tbl->crtc;
641         panel_crt_reg = panel_crt_table->crtc;
642         DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
643         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
644                 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
645         plvds_setting_info->vclk = panel_crt_table->clk;
646         if (set_iga == IGA1) {
647                 /* IGA1 doesn't have LCD scaling, so set it as centering. */
648                 viafb_load_crtc_timing(lcd_centering_timging
649                                  (mode_crt_reg, panel_crt_reg), IGA1);
650         } else {
651                 /* Expansion */
652                 if (plvds_setting_info->display_method == LCD_EXPANDSION
653                         && (set_hres < panel_hres || set_vres < panel_vres)) {
654                         /* expansion timing IGA2 loaded panel set timing*/
655                         viafb_load_crtc_timing(panel_crt_reg, IGA2);
656                         DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
657                         load_lcd_scaling(set_hres, set_vres, panel_hres,
658                                          panel_vres);
659                         DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
660                 } else {        /* Centering */
661                         /* centering timing IGA2 always loaded panel
662                            and mode releative timing */
663                         viafb_load_crtc_timing(lcd_centering_timging
664                                          (mode_crt_reg, panel_crt_reg), IGA2);
665                         viafb_write_reg_mask(CR79, VIACR, 0x00,
666                                 BIT0 + BIT1 + BIT2);
667                         /* LCD scaling disabled */
668                 }
669         }
670
671         /* Fetch count for IGA2 only */
672         viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
673
674         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
675                 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
676                 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
677
678         fill_lcd_format();
679
680         pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
681         DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
682         viafb_set_vclock(pll_D_N, set_iga);
683
684         viafb_set_output_path(DEVICE_LCD, set_iga,
685                 plvds_chip_info->output_interface);
686         lcd_patch_skew(plvds_setting_info, plvds_chip_info);
687
688         /* If K8M800, enable LCD Prefetch Mode. */
689         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
690             || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
691                 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
692
693         /* Patch for non 32bit alignment mode */
694         via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
695 }
696
697 static void integrated_lvds_disable(struct lvds_setting_information
698                              *plvds_setting_info,
699                              struct lvds_chip_information *plvds_chip_info)
700 {
701         bool turn_off_first_powersequence = false;
702         bool turn_off_second_powersequence = false;
703         if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
704                 turn_off_first_powersequence = true;
705         if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
706                 turn_off_first_powersequence = true;
707         if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
708                 turn_off_second_powersequence = true;
709         if (turn_off_second_powersequence) {
710                 /* Use second power sequence control: */
711
712                 /* Turn off power sequence. */
713                 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
714
715                 /* Turn off back light. */
716                 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
717         }
718         if (turn_off_first_powersequence) {
719                 /* Use first power sequence control: */
720
721                 /* Turn off power sequence. */
722                 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
723
724                 /* Turn off back light. */
725                 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
726         }
727
728         /* Turn DFP High/Low Pad off. */
729         viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
730
731         /* Power off LVDS channel. */
732         switch (plvds_chip_info->output_interface) {
733         case INTERFACE_LVDS0:
734                 {
735                         viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
736                         break;
737                 }
738
739         case INTERFACE_LVDS1:
740                 {
741                         viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
742                         break;
743                 }
744
745         case INTERFACE_LVDS0LVDS1:
746                 {
747                         viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
748                         break;
749                 }
750         }
751 }
752
753 static void integrated_lvds_enable(struct lvds_setting_information
754                             *plvds_setting_info,
755                             struct lvds_chip_information *plvds_chip_info)
756 {
757         DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
758                   plvds_chip_info->output_interface);
759         if (plvds_setting_info->lcd_mode == LCD_SPWG)
760                 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
761         else
762                 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
763
764         switch (plvds_chip_info->output_interface) {
765         case INTERFACE_LVDS0LVDS1:
766         case INTERFACE_LVDS0:
767                 /* Use first power sequence control: */
768                 /* Use hardware control power sequence. */
769                 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
770                 /* Turn on back light. */
771                 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
772                 /* Turn on hardware power sequence. */
773                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
774                 break;
775         case INTERFACE_LVDS1:
776                 /* Use second power sequence control: */
777                 /* Use hardware control power sequence. */
778                 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
779                 /* Turn on back light. */
780                 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
781                 /* Turn on hardware power sequence. */
782                 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
783                 break;
784         }
785
786         /* Turn DFP High/Low pad on. */
787         viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
788
789         /* Power on LVDS channel. */
790         switch (plvds_chip_info->output_interface) {
791         case INTERFACE_LVDS0:
792                 {
793                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
794                         break;
795                 }
796
797         case INTERFACE_LVDS1:
798                 {
799                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
800                         break;
801                 }
802
803         case INTERFACE_LVDS0LVDS1:
804                 {
805                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
806                         break;
807                 }
808         }
809 }
810
811 void viafb_lcd_disable(void)
812 {
813
814         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
815                 lcd_powersequence_off();
816                 /* DI1 pad off */
817                 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
818         } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
819                 if (viafb_LCD2_ON
820                     && (INTEGRATED_LVDS ==
821                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
822                         integrated_lvds_disable(viaparinfo->lvds_setting_info,
823                                 &viaparinfo->chip_info->lvds_chip_info2);
824                 if (INTEGRATED_LVDS ==
825                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
826                         integrated_lvds_disable(viaparinfo->lvds_setting_info,
827                                 &viaparinfo->chip_info->lvds_chip_info);
828                 if (VT1636_LVDS == viaparinfo->chip_info->
829                         lvds_chip_info.lvds_chip_name)
830                         viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
831                                 &viaparinfo->chip_info->lvds_chip_info);
832         } else if (VT1636_LVDS ==
833         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
834                 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
835                                     &viaparinfo->chip_info->lvds_chip_info);
836         } else {
837                 /* DFP-HL pad off          */
838                 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
839                 /* Backlight off           */
840                 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
841                 /* 24 bit DI data paht off */
842                 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
843                 /* Simultaneout disabled   */
844                 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
845         }
846
847         /* Disable expansion bit   */
848         viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
849         /* CRT path set to IGA1    */
850         viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
851         /* Simultaneout disabled   */
852         viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
853         /* IGA2 path disabled      */
854         viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
855
856 }
857
858 void viafb_lcd_enable(void)
859 {
860         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
861                 /* DI1 pad on */
862                 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
863                 lcd_powersequence_on();
864         } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
865                 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
866                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
867                         integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
868                                 &viaparinfo->chip_info->lvds_chip_info2);
869                 if (INTEGRATED_LVDS ==
870                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
871                         integrated_lvds_enable(viaparinfo->lvds_setting_info,
872                                 &viaparinfo->chip_info->lvds_chip_info);
873                 if (VT1636_LVDS == viaparinfo->chip_info->
874                         lvds_chip_info.lvds_chip_name)
875                         viafb_enable_lvds_vt1636(viaparinfo->
876                         lvds_setting_info, &viaparinfo->chip_info->
877                         lvds_chip_info);
878         } else if (VT1636_LVDS ==
879         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
880                 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
881                                    &viaparinfo->chip_info->lvds_chip_info);
882         } else {
883                 /* DFP-HL pad on           */
884                 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
885                 /* Backlight on            */
886                 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
887                 /* 24 bit DI data paht on  */
888                 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
889
890                 /* Set data source selection bit by iga path */
891                 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
892                         /* DFP-H set to IGA1       */
893                         viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
894                         /* DFP-L set to IGA1       */
895                         viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
896                 } else {
897                         /* DFP-H set to IGA2       */
898                         viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
899                         /* DFP-L set to IGA2       */
900                         viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
901                 }
902                 /* LCD enabled             */
903                 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
904         }
905
906         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
907                 /* CRT path set to IGA2    */
908                 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
909                 /* IGA2 path disabled      */
910                 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
911                 /* IGA2 path enabled       */
912         } else {                /* IGA2 */
913                 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
914         }
915
916 }
917
918 static void lcd_powersequence_off(void)
919 {
920         int i, mask, data;
921
922         /* Software control power sequence */
923         viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
924
925         for (i = 0; i < 3; i++) {
926                 mask = PowerSequenceOff[0][i];
927                 data = PowerSequenceOff[1][i] & mask;
928                 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
929                 udelay(PowerSequenceOff[2][i]);
930         }
931
932         /* Disable LCD */
933         viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
934 }
935
936 static void lcd_powersequence_on(void)
937 {
938         int i, mask, data;
939
940         /* Software control power sequence */
941         viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
942
943         /* Enable LCD */
944         viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
945
946         for (i = 0; i < 3; i++) {
947                 mask = PowerSequenceOn[0][i];
948                 data = PowerSequenceOn[1][i] & mask;
949                 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
950                 udelay(PowerSequenceOn[2][i]);
951         }
952
953         udelay(1);
954 }
955
956 static void fill_lcd_format(void)
957 {
958         u8 bdithering = 0, bdual = 0;
959
960         if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
961                 bdual = BIT4;
962         if (viaparinfo->lvds_setting_info->LCDDithering)
963                 bdithering = BIT0;
964         /* Dual & Dithering */
965         viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
966 }
967
968 static void check_diport_of_integrated_lvds(
969         struct lvds_chip_information *plvds_chip_info,
970                                      struct lvds_setting_information
971                                      *plvds_setting_info)
972 {
973         /* Determine LCD DI Port by hardware layout. */
974         switch (viafb_display_hardware_layout) {
975         case HW_LAYOUT_LCD_ONLY:
976                 {
977                         if (plvds_setting_info->device_lcd_dualedge) {
978                                 plvds_chip_info->output_interface =
979                                     INTERFACE_LVDS0LVDS1;
980                         } else {
981                                 plvds_chip_info->output_interface =
982                                     INTERFACE_LVDS0;
983                         }
984
985                         break;
986                 }
987
988         case HW_LAYOUT_DVI_ONLY:
989                 {
990                         plvds_chip_info->output_interface = INTERFACE_NONE;
991                         break;
992                 }
993
994         case HW_LAYOUT_LCD1_LCD2:
995         case HW_LAYOUT_LCD_EXTERNAL_LCD2:
996                 {
997                         plvds_chip_info->output_interface =
998                             INTERFACE_LVDS0LVDS1;
999                         break;
1000                 }
1001
1002         case HW_LAYOUT_LCD_DVI:
1003                 {
1004                         plvds_chip_info->output_interface = INTERFACE_LVDS1;
1005                         break;
1006                 }
1007
1008         default:
1009                 {
1010                         plvds_chip_info->output_interface = INTERFACE_LVDS1;
1011                         break;
1012                 }
1013         }
1014
1015         DEBUG_MSG(KERN_INFO
1016                   "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
1017                   viafb_display_hardware_layout,
1018                   plvds_chip_info->output_interface);
1019 }
1020
1021 void viafb_init_lvds_output_interface(struct lvds_chip_information
1022                                 *plvds_chip_info,
1023                                 struct lvds_setting_information
1024                                 *plvds_setting_info)
1025 {
1026         if (INTERFACE_NONE != plvds_chip_info->output_interface) {
1027                 /*Do nothing, lcd port is specified by module parameter */
1028                 return;
1029         }
1030
1031         switch (plvds_chip_info->lvds_chip_name) {
1032
1033         case VT1636_LVDS:
1034                 switch (viaparinfo->chip_info->gfx_chip_name) {
1035                 case UNICHROME_CX700:
1036                         plvds_chip_info->output_interface = INTERFACE_DVP1;
1037                         break;
1038                 case UNICHROME_CN700:
1039                         plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1040                         break;
1041                 default:
1042                         plvds_chip_info->output_interface = INTERFACE_DVP0;
1043                         break;
1044                 }
1045                 break;
1046
1047         case INTEGRATED_LVDS:
1048                 check_diport_of_integrated_lvds(plvds_chip_info,
1049                                                 plvds_setting_info);
1050                 break;
1051
1052         default:
1053                 switch (viaparinfo->chip_info->gfx_chip_name) {
1054                 case UNICHROME_K8M890:
1055                 case UNICHROME_P4M900:
1056                 case UNICHROME_P4M890:
1057                         plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1058                         break;
1059                 default:
1060                         plvds_chip_info->output_interface = INTERFACE_DFP;
1061                         break;
1062                 }
1063                 break;
1064         }
1065 }
1066
1067 static struct display_timing lcd_centering_timging(struct display_timing
1068                                             mode_crt_reg,
1069                                             struct display_timing panel_crt_reg)
1070 {
1071         struct display_timing crt_reg;
1072
1073         crt_reg.hor_total = panel_crt_reg.hor_total;
1074         crt_reg.hor_addr = mode_crt_reg.hor_addr;
1075         crt_reg.hor_blank_start =
1076             (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
1077             crt_reg.hor_addr;
1078         crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1079         crt_reg.hor_sync_start =
1080             (panel_crt_reg.hor_sync_start -
1081              panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1082         crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1083
1084         crt_reg.ver_total = panel_crt_reg.ver_total;
1085         crt_reg.ver_addr = mode_crt_reg.ver_addr;
1086         crt_reg.ver_blank_start =
1087             (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1088             crt_reg.ver_addr;
1089         crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1090         crt_reg.ver_sync_start =
1091             (panel_crt_reg.ver_sync_start -
1092              panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1093         crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1094
1095         return crt_reg;
1096 }
1097
1098 bool viafb_lcd_get_mobile_state(bool *mobile)
1099 {
1100         unsigned char *romptr, *tableptr;
1101         u8 core_base;
1102         unsigned char *biosptr;
1103         /* Rom address */
1104         u32 romaddr = 0x000C0000;
1105         u16 start_pattern = 0;
1106
1107         biosptr = ioremap(romaddr, 0x10000);
1108
1109         memcpy(&start_pattern, biosptr, 2);
1110         /* Compare pattern */
1111         if (start_pattern == 0xAA55) {
1112                 /* Get the start of Table */
1113                 /* 0x1B means BIOS offset position */
1114                 romptr = biosptr + 0x1B;
1115                 tableptr = biosptr + *((u16 *) romptr);
1116
1117                 /* Get the start of biosver structure */
1118                 /* 18 means BIOS version position. */
1119                 romptr = tableptr + 18;
1120                 romptr = biosptr + *((u16 *) romptr);
1121
1122                 /* The offset should be 44, but the
1123                    actual image is less three char. */
1124                 /* pRom += 44; */
1125                 romptr += 41;
1126
1127                 core_base = *romptr++;
1128
1129                 if (core_base & 0x8)
1130                         *mobile = false;
1131                 else
1132                         *mobile = true;
1133                 /* release memory */
1134                 iounmap(biosptr);
1135
1136                 return true;
1137         } else {
1138                 iounmap(biosptr);
1139                 return false;
1140         }
1141 }