Merge branch 'topic/hda-ca0132-dsp' into for-next
[~shefty/rdma-dev.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
70 static char *model[SNDRV_CARDS];
71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_only[SNDRV_CARDS];
75 static int jackpoll_ms[SNDRV_CARDS];
76 static bool single_cmd;
77 static int enable_msi = -1;
78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
79 static char *patch[SNDRV_CARDS];
80 #endif
81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
84 #endif
85
86 module_param_array(index, int, NULL, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
88 module_param_array(id, charp, NULL, 0444);
89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
90 module_param_array(enable, bool, NULL, 0444);
91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92 module_param_array(model, charp, NULL, 0444);
93 MODULE_PARM_DESC(model, "Use the given board model.");
94 module_param_array(position_fix, int, NULL, 0444);
95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
97 module_param_array(bdl_pos_adj, int, NULL, 0644);
98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
99 module_param_array(probe_mask, int, NULL, 0444);
100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
101 module_param_array(probe_only, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
103 module_param_array(jackpoll_ms, int, NULL, 0444);
104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
105 module_param(single_cmd, bool, 0444);
106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107                  "(for debugging only).");
108 module_param(enable_msi, bint, 0444);
109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
111 module_param_array(patch, charp, NULL, 0444);
112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113 #endif
114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
115 module_param_array(beep_mode, bool, NULL, 0444);
116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
117                             "(0=off, 1=on) (default=1).");
118 #endif
119
120 #ifdef CONFIG_PM
121 static int param_set_xint(const char *val, const struct kernel_param *kp);
122 static struct kernel_param_ops param_ops_xint = {
123         .set = param_set_xint,
124         .get = param_get_int,
125 };
126 #define param_check_xint param_check_int
127
128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
129 module_param(power_save, xint, 0644);
130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131                  "(in second, 0 = disable).");
132
133 /* reset the HD-audio controller in power save mode.
134  * this may give more power-saving, but will take longer time to
135  * wake up.
136  */
137 static int power_save_controller = -1;
138 module_param(power_save_controller, bint, 0644);
139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
140 #endif /* CONFIG_PM */
141
142 static int align_buffer_size = -1;
143 module_param(align_buffer_size, bint, 0644);
144 MODULE_PARM_DESC(align_buffer_size,
145                 "Force buffer and period sizes to be multiple of 128 bytes.");
146
147 #ifdef CONFIG_X86
148 static bool hda_snoop = true;
149 module_param_named(snoop, hda_snoop, bool, 0444);
150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151 #define azx_snoop(chip)         (chip)->snoop
152 #else
153 #define hda_snoop               true
154 #define azx_snoop(chip)         true
155 #endif
156
157
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160                          "{Intel, ICH6M},"
161                          "{Intel, ICH7},"
162                          "{Intel, ESB2},"
163                          "{Intel, ICH8},"
164                          "{Intel, ICH9},"
165                          "{Intel, ICH10},"
166                          "{Intel, PCH},"
167                          "{Intel, CPT},"
168                          "{Intel, PPT},"
169                          "{Intel, LPT},"
170                          "{Intel, LPT_LP},"
171                          "{Intel, HPT},"
172                          "{Intel, PBG},"
173                          "{Intel, SCH},"
174                          "{ATI, SB450},"
175                          "{ATI, SB600},"
176                          "{ATI, RS600},"
177                          "{ATI, RS690},"
178                          "{ATI, RS780},"
179                          "{ATI, R600},"
180                          "{ATI, RV630},"
181                          "{ATI, RV610},"
182                          "{ATI, RV670},"
183                          "{ATI, RV635},"
184                          "{ATI, RV620},"
185                          "{ATI, RV770},"
186                          "{VIA, VT8251},"
187                          "{VIA, VT8237A},"
188                          "{SiS, SIS966},"
189                          "{ULI, M5461}}");
190 MODULE_DESCRIPTION("Intel HDA driver");
191
192 #ifdef CONFIG_SND_VERBOSE_PRINTK
193 #define SFX     /* nop */
194 #else
195 #define SFX     "hda-intel "
196 #endif
197
198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
200 #define SUPPORT_VGA_SWITCHEROO
201 #endif
202 #endif
203
204
205 /*
206  * registers
207  */
208 #define ICH6_REG_GCAP                   0x00
209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
214 #define ICH6_REG_VMIN                   0x02
215 #define ICH6_REG_VMAJ                   0x03
216 #define ICH6_REG_OUTPAY                 0x04
217 #define ICH6_REG_INPAY                  0x06
218 #define ICH6_REG_GCTL                   0x08
219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
222 #define ICH6_REG_WAKEEN                 0x0c
223 #define ICH6_REG_STATESTS               0x0e
224 #define ICH6_REG_GSTS                   0x10
225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
226 #define ICH6_REG_INTCTL                 0x20
227 #define ICH6_REG_INTSTS                 0x24
228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
230 #define ICH6_REG_SSYNC                  0x38
231 #define ICH6_REG_CORBLBASE              0x40
232 #define ICH6_REG_CORBUBASE              0x44
233 #define ICH6_REG_CORBWP                 0x48
234 #define ICH6_REG_CORBRP                 0x4a
235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
236 #define ICH6_REG_CORBCTL                0x4c
237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
239 #define ICH6_REG_CORBSTS                0x4d
240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
241 #define ICH6_REG_CORBSIZE               0x4e
242
243 #define ICH6_REG_RIRBLBASE              0x50
244 #define ICH6_REG_RIRBUBASE              0x54
245 #define ICH6_REG_RIRBWP                 0x58
246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
247 #define ICH6_REG_RINTCNT                0x5a
248 #define ICH6_REG_RIRBCTL                0x5c
249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
252 #define ICH6_REG_RIRBSTS                0x5d
253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
255 #define ICH6_REG_RIRBSIZE               0x5e
256
257 #define ICH6_REG_IC                     0x60
258 #define ICH6_REG_IR                     0x64
259 #define ICH6_REG_IRS                    0x68
260 #define   ICH6_IRS_VALID        (1<<1)
261 #define   ICH6_IRS_BUSY         (1<<0)
262
263 #define ICH6_REG_DPLBASE                0x70
264 #define ICH6_REG_DPUBASE                0x74
265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
266
267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270 /* stream register offsets from stream base */
271 #define ICH6_REG_SD_CTL                 0x00
272 #define ICH6_REG_SD_STS                 0x03
273 #define ICH6_REG_SD_LPIB                0x04
274 #define ICH6_REG_SD_CBL                 0x08
275 #define ICH6_REG_SD_LVI                 0x0c
276 #define ICH6_REG_SD_FIFOW               0x0e
277 #define ICH6_REG_SD_FIFOSIZE            0x10
278 #define ICH6_REG_SD_FORMAT              0x12
279 #define ICH6_REG_SD_BDLPL               0x18
280 #define ICH6_REG_SD_BDLPU               0x1c
281
282 /* PCI space */
283 #define ICH6_PCIREG_TCSEL       0x44
284
285 /*
286  * other constants
287  */
288
289 /* max number of SDs */
290 /* ICH, ATI and VIA have 4 playback and 4 capture */
291 #define ICH6_NUM_CAPTURE        4
292 #define ICH6_NUM_PLAYBACK       4
293
294 /* ULI has 6 playback and 5 capture */
295 #define ULI_NUM_CAPTURE         5
296 #define ULI_NUM_PLAYBACK        6
297
298 /* ATI HDMI has 1 playback and 0 capture */
299 #define ATIHDMI_NUM_CAPTURE     0
300 #define ATIHDMI_NUM_PLAYBACK    1
301
302 /* TERA has 4 playback and 3 capture */
303 #define TERA_NUM_CAPTURE        3
304 #define TERA_NUM_PLAYBACK       4
305
306 /* this number is statically defined for simplicity */
307 #define MAX_AZX_DEV             16
308
309 /* max number of fragments - we may use more if allocating more pages for BDL */
310 #define BDL_SIZE                4096
311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
312 #define AZX_MAX_FRAG            32
313 /* max buffer size - no h/w limit, you can increase as you like */
314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
315
316 /* RIRB int mask: overrun[2], response[0] */
317 #define RIRB_INT_RESPONSE       0x01
318 #define RIRB_INT_OVERRUN        0x04
319 #define RIRB_INT_MASK           0x05
320
321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
322 #define AZX_MAX_CODECS          8
323 #define AZX_DEFAULT_CODECS      4
324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
325
326 /* SD_CTL bits */
327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
333 #define SD_CTL_STREAM_TAG_SHIFT 20
334
335 /* SD_CTL and SD_STS */
336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340                                  SD_INT_COMPLETE)
341
342 /* SD_STS */
343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
344
345 /* INTCTL and INTSTS */
346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
349
350 /* below are so far hardcoded - should read registers in future */
351 #define ICH6_MAX_CORB_ENTRIES   256
352 #define ICH6_MAX_RIRB_ENTRIES   256
353
354 /* position fix mode */
355 enum {
356         POS_FIX_AUTO,
357         POS_FIX_LPIB,
358         POS_FIX_POSBUF,
359         POS_FIX_VIACOMBO,
360         POS_FIX_COMBO,
361 };
362
363 /* Defines for ATI HD Audio support in SB450 south bridge */
364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
366
367 /* Defines for Nvidia HDA support */
368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
370 #define NVIDIA_HDA_ISTRM_COH          0x4d
371 #define NVIDIA_HDA_OSTRM_COH          0x4c
372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
373
374 /* Defines for Intel SCH HDA snoop control */
375 #define INTEL_SCH_HDA_DEVC      0x78
376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
377
378 /* Define IN stream 0 FIFO size offset in VIA controller */
379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380 /* Define VIA HD Audio Device ID*/
381 #define VIA_HDAC_DEVICE_ID              0x3288
382
383 /* HD Audio class code */
384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
385
386 /*
387  */
388
389 struct azx_dev {
390         struct snd_dma_buffer bdl; /* BDL buffer */
391         u32 *posbuf;            /* position buffer pointer */
392
393         unsigned int bufsize;   /* size of the play buffer in bytes */
394         unsigned int period_bytes; /* size of the period in bytes */
395         unsigned int frags;     /* number for period in the play buffer */
396         unsigned int fifo_size; /* FIFO size */
397         unsigned long start_wallclk;    /* start + minimum wallclk */
398         unsigned long period_wallclk;   /* wallclk for period */
399
400         void __iomem *sd_addr;  /* stream descriptor pointer */
401
402         u32 sd_int_sta_mask;    /* stream int status mask */
403
404         /* pcm support */
405         struct snd_pcm_substream *substream;    /* assigned substream,
406                                                  * set in PCM open
407                                                  */
408         unsigned int format_val;        /* format value to be set in the
409                                          * controller and the codec
410                                          */
411         unsigned char stream_tag;       /* assigned stream */
412         unsigned char index;            /* stream index */
413         int assigned_key;               /* last device# key assigned to */
414
415         unsigned int opened :1;
416         unsigned int running :1;
417         unsigned int irq_pending :1;
418         /*
419          * For VIA:
420          *  A flag to ensure DMA position is 0
421          *  when link position is not greater than FIFO size
422          */
423         unsigned int insufficient :1;
424         unsigned int wc_marked:1;
425         unsigned int no_period_wakeup:1;
426
427         struct timecounter  azx_tc;
428         struct cyclecounter azx_cc;
429 };
430
431 /* CORB/RIRB */
432 struct azx_rb {
433         u32 *buf;               /* CORB/RIRB buffer
434                                  * Each CORB entry is 4byte, RIRB is 8byte
435                                  */
436         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
437         /* for RIRB */
438         unsigned short rp, wp;  /* read/write pointers */
439         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
440         u32 res[AZX_MAX_CODECS];        /* last read value */
441 };
442
443 struct azx_pcm {
444         struct azx *chip;
445         struct snd_pcm *pcm;
446         struct hda_codec *codec;
447         struct hda_pcm_stream *hinfo[2];
448         struct list_head list;
449 };
450
451 struct azx {
452         struct snd_card *card;
453         struct pci_dev *pci;
454         int dev_index;
455
456         /* chip type specific */
457         int driver_type;
458         unsigned int driver_caps;
459         int playback_streams;
460         int playback_index_offset;
461         int capture_streams;
462         int capture_index_offset;
463         int num_streams;
464
465         /* pci resources */
466         unsigned long addr;
467         void __iomem *remap_addr;
468         int irq;
469
470         /* locks */
471         spinlock_t reg_lock;
472         struct mutex open_mutex;
473         struct completion probe_wait;
474
475         /* streams (x num_streams) */
476         struct azx_dev *azx_dev;
477
478         /* PCM */
479         struct list_head pcm_list; /* azx_pcm list */
480
481         /* HD codec */
482         unsigned short codec_mask;
483         int  codec_probe_mask; /* copied from probe_mask option */
484         struct hda_bus *bus;
485         unsigned int beep_mode;
486
487         /* CORB/RIRB */
488         struct azx_rb corb;
489         struct azx_rb rirb;
490
491         /* CORB/RIRB and position buffers */
492         struct snd_dma_buffer rb;
493         struct snd_dma_buffer posbuf;
494
495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
496         const struct firmware *fw;
497 #endif
498
499         /* flags */
500         int position_fix[2]; /* for both playback/capture streams */
501         int poll_count;
502         unsigned int running :1;
503         unsigned int initialized :1;
504         unsigned int single_cmd :1;
505         unsigned int polling_mode :1;
506         unsigned int msi :1;
507         unsigned int irq_pending_warned :1;
508         unsigned int probing :1; /* codec probing phase */
509         unsigned int snoop:1;
510         unsigned int align_buffer_size:1;
511         unsigned int region_requested:1;
512
513         /* VGA-switcheroo setup */
514         unsigned int use_vga_switcheroo:1;
515         unsigned int vga_switcheroo_registered:1;
516         unsigned int init_failed:1; /* delayed init failed */
517         unsigned int disabled:1; /* disabled by VGA-switcher */
518
519         /* for debugging */
520         unsigned int last_cmd[AZX_MAX_CODECS];
521
522         /* for pending irqs */
523         struct work_struct irq_pending_work;
524
525         /* reboot notifier (for mysterious hangup problem at power-down) */
526         struct notifier_block reboot_notifier;
527
528         /* card list (for power_save trigger) */
529         struct list_head list;
530 };
531
532 #define CREATE_TRACE_POINTS
533 #include "hda_intel_trace.h"
534
535 /* driver types */
536 enum {
537         AZX_DRIVER_ICH,
538         AZX_DRIVER_PCH,
539         AZX_DRIVER_SCH,
540         AZX_DRIVER_ATI,
541         AZX_DRIVER_ATIHDMI,
542         AZX_DRIVER_ATIHDMI_NS,
543         AZX_DRIVER_VIA,
544         AZX_DRIVER_SIS,
545         AZX_DRIVER_ULI,
546         AZX_DRIVER_NVIDIA,
547         AZX_DRIVER_TERA,
548         AZX_DRIVER_CTX,
549         AZX_DRIVER_CTHDA,
550         AZX_DRIVER_GENERIC,
551         AZX_NUM_DRIVERS, /* keep this as last entry */
552 };
553
554 /* driver quirks (capabilities) */
555 /* bits 0-7 are used for indicating driver type */
556 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
557 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
558 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
559 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
560 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
561 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
562 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
563 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
564 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
565 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
566 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
567 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
568 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
569 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
570 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
571 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
572 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
573 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
574
575 /* quirks for Intel PCH */
576 #define AZX_DCAPS_INTEL_PCH_NOPM \
577         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
578          AZX_DCAPS_COUNT_LPIB_DELAY)
579
580 #define AZX_DCAPS_INTEL_PCH \
581         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
582
583 /* quirks for ATI SB / AMD Hudson */
584 #define AZX_DCAPS_PRESET_ATI_SB \
585         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
586          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
587
588 /* quirks for ATI/AMD HDMI */
589 #define AZX_DCAPS_PRESET_ATI_HDMI \
590         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
591
592 /* quirks for Nvidia */
593 #define AZX_DCAPS_PRESET_NVIDIA \
594         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
595          AZX_DCAPS_ALIGN_BUFSIZE)
596
597 #define AZX_DCAPS_PRESET_CTHDA \
598         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
599
600 /*
601  * VGA-switcher support
602  */
603 #ifdef SUPPORT_VGA_SWITCHEROO
604 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
605 #else
606 #define use_vga_switcheroo(chip)        0
607 #endif
608
609 static char *driver_short_names[] = {
610         [AZX_DRIVER_ICH] = "HDA Intel",
611         [AZX_DRIVER_PCH] = "HDA Intel PCH",
612         [AZX_DRIVER_SCH] = "HDA Intel MID",
613         [AZX_DRIVER_ATI] = "HDA ATI SB",
614         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
615         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
616         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
617         [AZX_DRIVER_SIS] = "HDA SIS966",
618         [AZX_DRIVER_ULI] = "HDA ULI M5461",
619         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
620         [AZX_DRIVER_TERA] = "HDA Teradici", 
621         [AZX_DRIVER_CTX] = "HDA Creative", 
622         [AZX_DRIVER_CTHDA] = "HDA Creative",
623         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
624 };
625
626 /*
627  * macros for easy use
628  */
629 #define azx_writel(chip,reg,value) \
630         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
631 #define azx_readl(chip,reg) \
632         readl((chip)->remap_addr + ICH6_REG_##reg)
633 #define azx_writew(chip,reg,value) \
634         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
635 #define azx_readw(chip,reg) \
636         readw((chip)->remap_addr + ICH6_REG_##reg)
637 #define azx_writeb(chip,reg,value) \
638         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
639 #define azx_readb(chip,reg) \
640         readb((chip)->remap_addr + ICH6_REG_##reg)
641
642 #define azx_sd_writel(dev,reg,value) \
643         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
644 #define azx_sd_readl(dev,reg) \
645         readl((dev)->sd_addr + ICH6_REG_##reg)
646 #define azx_sd_writew(dev,reg,value) \
647         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
648 #define azx_sd_readw(dev,reg) \
649         readw((dev)->sd_addr + ICH6_REG_##reg)
650 #define azx_sd_writeb(dev,reg,value) \
651         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
652 #define azx_sd_readb(dev,reg) \
653         readb((dev)->sd_addr + ICH6_REG_##reg)
654
655 /* for pcm support */
656 #define get_azx_dev(substream) (substream->runtime->private_data)
657
658 #ifdef CONFIG_X86
659 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
660 {
661         int pages;
662
663         if (azx_snoop(chip))
664                 return;
665         if (!dmab || !dmab->area || !dmab->bytes)
666                 return;
667
668 #ifdef CONFIG_SND_DMA_SGBUF
669         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
670                 struct snd_sg_buf *sgbuf = dmab->private_data;
671                 if (on)
672                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
673                 else
674                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
675                 return;
676         }
677 #endif
678
679         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
680         if (on)
681                 set_memory_wc((unsigned long)dmab->area, pages);
682         else
683                 set_memory_wb((unsigned long)dmab->area, pages);
684 }
685
686 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
687                                  bool on)
688 {
689         __mark_pages_wc(chip, buf, on);
690 }
691 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
692                                    struct snd_pcm_substream *substream, bool on)
693 {
694         if (azx_dev->wc_marked != on) {
695                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
696                 azx_dev->wc_marked = on;
697         }
698 }
699 #else
700 /* NOP for other archs */
701 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
702                                  bool on)
703 {
704 }
705 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
706                                    struct snd_pcm_substream *substream, bool on)
707 {
708 }
709 #endif
710
711 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
712 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
713 /*
714  * Interface for HD codec
715  */
716
717 /*
718  * CORB / RIRB interface
719  */
720 static int azx_alloc_cmd_io(struct azx *chip)
721 {
722         int err;
723
724         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
725         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
726                                   snd_dma_pci_data(chip->pci),
727                                   PAGE_SIZE, &chip->rb);
728         if (err < 0) {
729                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
730                 return err;
731         }
732         mark_pages_wc(chip, &chip->rb, true);
733         return 0;
734 }
735
736 static void azx_init_cmd_io(struct azx *chip)
737 {
738         spin_lock_irq(&chip->reg_lock);
739         /* CORB set up */
740         chip->corb.addr = chip->rb.addr;
741         chip->corb.buf = (u32 *)chip->rb.area;
742         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
743         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
744
745         /* set the corb size to 256 entries (ULI requires explicitly) */
746         azx_writeb(chip, CORBSIZE, 0x02);
747         /* set the corb write pointer to 0 */
748         azx_writew(chip, CORBWP, 0);
749         /* reset the corb hw read pointer */
750         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
751         /* enable corb dma */
752         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
753
754         /* RIRB set up */
755         chip->rirb.addr = chip->rb.addr + 2048;
756         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
757         chip->rirb.wp = chip->rirb.rp = 0;
758         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
759         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
760         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
761
762         /* set the rirb size to 256 entries (ULI requires explicitly) */
763         azx_writeb(chip, RIRBSIZE, 0x02);
764         /* reset the rirb hw write pointer */
765         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
766         /* set N=1, get RIRB response interrupt for new entry */
767         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
768                 azx_writew(chip, RINTCNT, 0xc0);
769         else
770                 azx_writew(chip, RINTCNT, 1);
771         /* enable rirb dma and response irq */
772         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
773         spin_unlock_irq(&chip->reg_lock);
774 }
775
776 static void azx_free_cmd_io(struct azx *chip)
777 {
778         spin_lock_irq(&chip->reg_lock);
779         /* disable ringbuffer DMAs */
780         azx_writeb(chip, RIRBCTL, 0);
781         azx_writeb(chip, CORBCTL, 0);
782         spin_unlock_irq(&chip->reg_lock);
783 }
784
785 static unsigned int azx_command_addr(u32 cmd)
786 {
787         unsigned int addr = cmd >> 28;
788
789         if (addr >= AZX_MAX_CODECS) {
790                 snd_BUG();
791                 addr = 0;
792         }
793
794         return addr;
795 }
796
797 static unsigned int azx_response_addr(u32 res)
798 {
799         unsigned int addr = res & 0xf;
800
801         if (addr >= AZX_MAX_CODECS) {
802                 snd_BUG();
803                 addr = 0;
804         }
805
806         return addr;
807 }
808
809 /* send a command */
810 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
811 {
812         struct azx *chip = bus->private_data;
813         unsigned int addr = azx_command_addr(val);
814         unsigned int wp, rp;
815
816         spin_lock_irq(&chip->reg_lock);
817
818         /* add command to corb */
819         wp = azx_readw(chip, CORBWP);
820         if (wp == 0xffff) {
821                 /* something wrong, controller likely turned to D3 */
822                 spin_unlock_irq(&chip->reg_lock);
823                 return -EIO;
824         }
825         wp++;
826         wp %= ICH6_MAX_CORB_ENTRIES;
827
828         rp = azx_readw(chip, CORBRP);
829         if (wp == rp) {
830                 /* oops, it's full */
831                 spin_unlock_irq(&chip->reg_lock);
832                 return -EAGAIN;
833         }
834
835         chip->rirb.cmds[addr]++;
836         chip->corb.buf[wp] = cpu_to_le32(val);
837         azx_writel(chip, CORBWP, wp);
838
839         spin_unlock_irq(&chip->reg_lock);
840
841         return 0;
842 }
843
844 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
845
846 /* retrieve RIRB entry - called from interrupt handler */
847 static void azx_update_rirb(struct azx *chip)
848 {
849         unsigned int rp, wp;
850         unsigned int addr;
851         u32 res, res_ex;
852
853         wp = azx_readw(chip, RIRBWP);
854         if (wp == 0xffff) {
855                 /* something wrong, controller likely turned to D3 */
856                 return;
857         }
858
859         if (wp == chip->rirb.wp)
860                 return;
861         chip->rirb.wp = wp;
862
863         while (chip->rirb.rp != wp) {
864                 chip->rirb.rp++;
865                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
866
867                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
868                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
869                 res = le32_to_cpu(chip->rirb.buf[rp]);
870                 addr = azx_response_addr(res_ex);
871                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
872                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
873                 else if (chip->rirb.cmds[addr]) {
874                         chip->rirb.res[addr] = res;
875                         smp_wmb();
876                         chip->rirb.cmds[addr]--;
877                 } else
878                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
879                                    "last cmd=%#08x\n",
880                                    pci_name(chip->pci),
881                                    res, res_ex,
882                                    chip->last_cmd[addr]);
883         }
884 }
885
886 /* receive a response */
887 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
888                                           unsigned int addr)
889 {
890         struct azx *chip = bus->private_data;
891         unsigned long timeout;
892         unsigned long loopcounter;
893         int do_poll = 0;
894
895  again:
896         timeout = jiffies + msecs_to_jiffies(1000);
897
898         for (loopcounter = 0;; loopcounter++) {
899                 if (chip->polling_mode || do_poll) {
900                         spin_lock_irq(&chip->reg_lock);
901                         azx_update_rirb(chip);
902                         spin_unlock_irq(&chip->reg_lock);
903                 }
904                 if (!chip->rirb.cmds[addr]) {
905                         smp_rmb();
906                         bus->rirb_error = 0;
907
908                         if (!do_poll)
909                                 chip->poll_count = 0;
910                         return chip->rirb.res[addr]; /* the last value */
911                 }
912                 if (time_after(jiffies, timeout))
913                         break;
914                 if (bus->needs_damn_long_delay || loopcounter > 3000)
915                         msleep(2); /* temporary workaround */
916                 else {
917                         udelay(10);
918                         cond_resched();
919                 }
920         }
921
922         if (!chip->polling_mode && chip->poll_count < 2) {
923                 snd_printdd(SFX "%s: azx_get_response timeout, "
924                            "polling the codec once: last cmd=0x%08x\n",
925                            pci_name(chip->pci), chip->last_cmd[addr]);
926                 do_poll = 1;
927                 chip->poll_count++;
928                 goto again;
929         }
930
931
932         if (!chip->polling_mode) {
933                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
934                            "switching to polling mode: last cmd=0x%08x\n",
935                            pci_name(chip->pci), chip->last_cmd[addr]);
936                 chip->polling_mode = 1;
937                 goto again;
938         }
939
940         if (chip->msi) {
941                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
942                            "disabling MSI: last cmd=0x%08x\n",
943                            pci_name(chip->pci), chip->last_cmd[addr]);
944                 free_irq(chip->irq, chip);
945                 chip->irq = -1;
946                 pci_disable_msi(chip->pci);
947                 chip->msi = 0;
948                 if (azx_acquire_irq(chip, 1) < 0) {
949                         bus->rirb_error = 1;
950                         return -1;
951                 }
952                 goto again;
953         }
954
955         if (chip->probing) {
956                 /* If this critical timeout happens during the codec probing
957                  * phase, this is likely an access to a non-existing codec
958                  * slot.  Better to return an error and reset the system.
959                  */
960                 return -1;
961         }
962
963         /* a fatal communication error; need either to reset or to fallback
964          * to the single_cmd mode
965          */
966         bus->rirb_error = 1;
967         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
968                 bus->response_reset = 1;
969                 return -1; /* give a chance to retry */
970         }
971
972         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
973                    "switching to single_cmd mode: last cmd=0x%08x\n",
974                    chip->last_cmd[addr]);
975         chip->single_cmd = 1;
976         bus->response_reset = 0;
977         /* release CORB/RIRB */
978         azx_free_cmd_io(chip);
979         /* disable unsolicited responses */
980         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
981         return -1;
982 }
983
984 /*
985  * Use the single immediate command instead of CORB/RIRB for simplicity
986  *
987  * Note: according to Intel, this is not preferred use.  The command was
988  *       intended for the BIOS only, and may get confused with unsolicited
989  *       responses.  So, we shouldn't use it for normal operation from the
990  *       driver.
991  *       I left the codes, however, for debugging/testing purposes.
992  */
993
994 /* receive a response */
995 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
996 {
997         int timeout = 50;
998
999         while (timeout--) {
1000                 /* check IRV busy bit */
1001                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1002                         /* reuse rirb.res as the response return value */
1003                         chip->rirb.res[addr] = azx_readl(chip, IR);
1004                         return 0;
1005                 }
1006                 udelay(1);
1007         }
1008         if (printk_ratelimit())
1009                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1010                            pci_name(chip->pci), azx_readw(chip, IRS));
1011         chip->rirb.res[addr] = -1;
1012         return -EIO;
1013 }
1014
1015 /* send a command */
1016 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1017 {
1018         struct azx *chip = bus->private_data;
1019         unsigned int addr = azx_command_addr(val);
1020         int timeout = 50;
1021
1022         bus->rirb_error = 0;
1023         while (timeout--) {
1024                 /* check ICB busy bit */
1025                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1026                         /* Clear IRV valid bit */
1027                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1028                                    ICH6_IRS_VALID);
1029                         azx_writel(chip, IC, val);
1030                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1031                                    ICH6_IRS_BUSY);
1032                         return azx_single_wait_for_response(chip, addr);
1033                 }
1034                 udelay(1);
1035         }
1036         if (printk_ratelimit())
1037                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1038                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1039         return -EIO;
1040 }
1041
1042 /* receive a response */
1043 static unsigned int azx_single_get_response(struct hda_bus *bus,
1044                                             unsigned int addr)
1045 {
1046         struct azx *chip = bus->private_data;
1047         return chip->rirb.res[addr];
1048 }
1049
1050 /*
1051  * The below are the main callbacks from hda_codec.
1052  *
1053  * They are just the skeleton to call sub-callbacks according to the
1054  * current setting of chip->single_cmd.
1055  */
1056
1057 /* send a command */
1058 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1059 {
1060         struct azx *chip = bus->private_data;
1061
1062         if (chip->disabled)
1063                 return 0;
1064         chip->last_cmd[azx_command_addr(val)] = val;
1065         if (chip->single_cmd)
1066                 return azx_single_send_cmd(bus, val);
1067         else
1068                 return azx_corb_send_cmd(bus, val);
1069 }
1070
1071 /* get a response */
1072 static unsigned int azx_get_response(struct hda_bus *bus,
1073                                      unsigned int addr)
1074 {
1075         struct azx *chip = bus->private_data;
1076         if (chip->disabled)
1077                 return 0;
1078         if (chip->single_cmd)
1079                 return azx_single_get_response(bus, addr);
1080         else
1081                 return azx_rirb_get_response(bus, addr);
1082 }
1083
1084 #ifdef CONFIG_PM
1085 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1086 #endif
1087
1088 #ifdef CONFIG_SND_HDA_DSP_LOADER
1089 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1090                                 unsigned int byte_size,
1091                                 struct snd_dma_buffer *bufp);
1092 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1093 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1094                                  struct snd_dma_buffer *dmab);
1095 #endif
1096
1097 /* reset codec link */
1098 static int azx_reset(struct azx *chip, int full_reset)
1099 {
1100         unsigned long timeout;
1101
1102         if (!full_reset)
1103                 goto __skip;
1104
1105         /* clear STATESTS */
1106         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1107
1108         /* reset controller */
1109         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1110
1111         timeout = jiffies + msecs_to_jiffies(100);
1112         while (azx_readb(chip, GCTL) &&
1113                         time_before(jiffies, timeout))
1114                 usleep_range(500, 1000);
1115
1116         /* delay for >= 100us for codec PLL to settle per spec
1117          * Rev 0.9 section 5.5.1
1118          */
1119         usleep_range(500, 1000);
1120
1121         /* Bring controller out of reset */
1122         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1123
1124         timeout = jiffies + msecs_to_jiffies(100);
1125         while (!azx_readb(chip, GCTL) &&
1126                         time_before(jiffies, timeout))
1127                 usleep_range(500, 1000);
1128
1129         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1130         usleep_range(1000, 1200);
1131
1132       __skip:
1133         /* check to see if controller is ready */
1134         if (!azx_readb(chip, GCTL)) {
1135                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1136                 return -EBUSY;
1137         }
1138
1139         /* Accept unsolicited responses */
1140         if (!chip->single_cmd)
1141                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1142                            ICH6_GCTL_UNSOL);
1143
1144         /* detect codecs */
1145         if (!chip->codec_mask) {
1146                 chip->codec_mask = azx_readw(chip, STATESTS);
1147                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1148         }
1149
1150         return 0;
1151 }
1152
1153
1154 /*
1155  * Lowlevel interface
1156  */  
1157
1158 /* enable interrupts */
1159 static void azx_int_enable(struct azx *chip)
1160 {
1161         /* enable controller CIE and GIE */
1162         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1163                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1164 }
1165
1166 /* disable interrupts */
1167 static void azx_int_disable(struct azx *chip)
1168 {
1169         int i;
1170
1171         /* disable interrupts in stream descriptor */
1172         for (i = 0; i < chip->num_streams; i++) {
1173                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1174                 azx_sd_writeb(azx_dev, SD_CTL,
1175                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1176         }
1177
1178         /* disable SIE for all streams */
1179         azx_writeb(chip, INTCTL, 0);
1180
1181         /* disable controller CIE and GIE */
1182         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1183                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1184 }
1185
1186 /* clear interrupts */
1187 static void azx_int_clear(struct azx *chip)
1188 {
1189         int i;
1190
1191         /* clear stream status */
1192         for (i = 0; i < chip->num_streams; i++) {
1193                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1194                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1195         }
1196
1197         /* clear STATESTS */
1198         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1199
1200         /* clear rirb status */
1201         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1202
1203         /* clear int status */
1204         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1205 }
1206
1207 /* start a stream */
1208 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1209 {
1210         /*
1211          * Before stream start, initialize parameter
1212          */
1213         azx_dev->insufficient = 1;
1214
1215         /* enable SIE */
1216         azx_writel(chip, INTCTL,
1217                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1218         /* set DMA start and interrupt mask */
1219         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1220                       SD_CTL_DMA_START | SD_INT_MASK);
1221 }
1222
1223 /* stop DMA */
1224 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1225 {
1226         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1227                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1228         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1229 }
1230
1231 /* stop a stream */
1232 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1233 {
1234         azx_stream_clear(chip, azx_dev);
1235         /* disable SIE */
1236         azx_writel(chip, INTCTL,
1237                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1238 }
1239
1240
1241 /*
1242  * reset and start the controller registers
1243  */
1244 static void azx_init_chip(struct azx *chip, int full_reset)
1245 {
1246         if (chip->initialized)
1247                 return;
1248
1249         /* reset controller */
1250         azx_reset(chip, full_reset);
1251
1252         /* initialize interrupts */
1253         azx_int_clear(chip);
1254         azx_int_enable(chip);
1255
1256         /* initialize the codec command I/O */
1257         if (!chip->single_cmd)
1258                 azx_init_cmd_io(chip);
1259
1260         /* program the position buffer */
1261         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1262         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1263
1264         chip->initialized = 1;
1265 }
1266
1267 /*
1268  * initialize the PCI registers
1269  */
1270 /* update bits in a PCI register byte */
1271 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1272                             unsigned char mask, unsigned char val)
1273 {
1274         unsigned char data;
1275
1276         pci_read_config_byte(pci, reg, &data);
1277         data &= ~mask;
1278         data |= (val & mask);
1279         pci_write_config_byte(pci, reg, data);
1280 }
1281
1282 static void azx_init_pci(struct azx *chip)
1283 {
1284         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1285          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1286          * Ensuring these bits are 0 clears playback static on some HD Audio
1287          * codecs.
1288          * The PCI register TCSEL is defined in the Intel manuals.
1289          */
1290         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1291                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1292                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1293         }
1294
1295         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1296          * we need to enable snoop.
1297          */
1298         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1299                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1300                 update_pci_byte(chip->pci,
1301                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1302                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1303         }
1304
1305         /* For NVIDIA HDA, enable snoop */
1306         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1307                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1308                 update_pci_byte(chip->pci,
1309                                 NVIDIA_HDA_TRANSREG_ADDR,
1310                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1311                 update_pci_byte(chip->pci,
1312                                 NVIDIA_HDA_ISTRM_COH,
1313                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1314                 update_pci_byte(chip->pci,
1315                                 NVIDIA_HDA_OSTRM_COH,
1316                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1317         }
1318
1319         /* Enable SCH/PCH snoop if needed */
1320         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1321                 unsigned short snoop;
1322                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1323                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1324                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1325                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1326                         if (!azx_snoop(chip))
1327                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1328                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1329                         pci_read_config_word(chip->pci,
1330                                 INTEL_SCH_HDA_DEVC, &snoop);
1331                 }
1332                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1333                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1334                                 ? "Disabled" : "Enabled");
1335         }
1336 }
1337
1338
1339 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1340
1341 /*
1342  * interrupt handler
1343  */
1344 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1345 {
1346         struct azx *chip = dev_id;
1347         struct azx_dev *azx_dev;
1348         u32 status;
1349         u8 sd_status;
1350         int i, ok;
1351
1352 #ifdef CONFIG_PM_RUNTIME
1353         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1354                 return IRQ_NONE;
1355 #endif
1356
1357         spin_lock(&chip->reg_lock);
1358
1359         if (chip->disabled) {
1360                 spin_unlock(&chip->reg_lock);
1361                 return IRQ_NONE;
1362         }
1363
1364         status = azx_readl(chip, INTSTS);
1365         if (status == 0) {
1366                 spin_unlock(&chip->reg_lock);
1367                 return IRQ_NONE;
1368         }
1369         
1370         for (i = 0; i < chip->num_streams; i++) {
1371                 azx_dev = &chip->azx_dev[i];
1372                 if (status & azx_dev->sd_int_sta_mask) {
1373                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1374                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1375                         if (!azx_dev->substream || !azx_dev->running ||
1376                             !(sd_status & SD_INT_COMPLETE))
1377                                 continue;
1378                         /* check whether this IRQ is really acceptable */
1379                         ok = azx_position_ok(chip, azx_dev);
1380                         if (ok == 1) {
1381                                 azx_dev->irq_pending = 0;
1382                                 spin_unlock(&chip->reg_lock);
1383                                 snd_pcm_period_elapsed(azx_dev->substream);
1384                                 spin_lock(&chip->reg_lock);
1385                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1386                                 /* bogus IRQ, process it later */
1387                                 azx_dev->irq_pending = 1;
1388                                 queue_work(chip->bus->workq,
1389                                            &chip->irq_pending_work);
1390                         }
1391                 }
1392         }
1393
1394         /* clear rirb int */
1395         status = azx_readb(chip, RIRBSTS);
1396         if (status & RIRB_INT_MASK) {
1397                 if (status & RIRB_INT_RESPONSE) {
1398                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1399                                 udelay(80);
1400                         azx_update_rirb(chip);
1401                 }
1402                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1403         }
1404
1405 #if 0
1406         /* clear state status int */
1407         if (azx_readb(chip, STATESTS) & 0x04)
1408                 azx_writeb(chip, STATESTS, 0x04);
1409 #endif
1410         spin_unlock(&chip->reg_lock);
1411         
1412         return IRQ_HANDLED;
1413 }
1414
1415
1416 /*
1417  * set up a BDL entry
1418  */
1419 static int setup_bdle(struct azx *chip,
1420                       struct snd_dma_buffer *dmab,
1421                       struct azx_dev *azx_dev, u32 **bdlp,
1422                       int ofs, int size, int with_ioc)
1423 {
1424         u32 *bdl = *bdlp;
1425
1426         while (size > 0) {
1427                 dma_addr_t addr;
1428                 int chunk;
1429
1430                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1431                         return -EINVAL;
1432
1433                 addr = snd_sgbuf_get_addr(dmab, ofs);
1434                 /* program the address field of the BDL entry */
1435                 bdl[0] = cpu_to_le32((u32)addr);
1436                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1437                 /* program the size field of the BDL entry */
1438                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1439                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1440                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1441                         u32 remain = 0x1000 - (ofs & 0xfff);
1442                         if (chunk > remain)
1443                                 chunk = remain;
1444                 }
1445                 bdl[2] = cpu_to_le32(chunk);
1446                 /* program the IOC to enable interrupt
1447                  * only when the whole fragment is processed
1448                  */
1449                 size -= chunk;
1450                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1451                 bdl += 4;
1452                 azx_dev->frags++;
1453                 ofs += chunk;
1454         }
1455         *bdlp = bdl;
1456         return ofs;
1457 }
1458
1459 /*
1460  * set up BDL entries
1461  */
1462 static int azx_setup_periods(struct azx *chip,
1463                              struct snd_pcm_substream *substream,
1464                              struct azx_dev *azx_dev)
1465 {
1466         u32 *bdl;
1467         int i, ofs, periods, period_bytes;
1468         int pos_adj;
1469
1470         /* reset BDL address */
1471         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1472         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1473
1474         period_bytes = azx_dev->period_bytes;
1475         periods = azx_dev->bufsize / period_bytes;
1476
1477         /* program the initial BDL entries */
1478         bdl = (u32 *)azx_dev->bdl.area;
1479         ofs = 0;
1480         azx_dev->frags = 0;
1481         pos_adj = bdl_pos_adj[chip->dev_index];
1482         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1483                 struct snd_pcm_runtime *runtime = substream->runtime;
1484                 int pos_align = pos_adj;
1485                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1486                 if (!pos_adj)
1487                         pos_adj = pos_align;
1488                 else
1489                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1490                                 pos_align;
1491                 pos_adj = frames_to_bytes(runtime, pos_adj);
1492                 if (pos_adj >= period_bytes) {
1493                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1494                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1495                         pos_adj = 0;
1496                 } else {
1497                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1498                                          azx_dev,
1499                                          &bdl, ofs, pos_adj, true);
1500                         if (ofs < 0)
1501                                 goto error;
1502                 }
1503         } else
1504                 pos_adj = 0;
1505         for (i = 0; i < periods; i++) {
1506                 if (i == periods - 1 && pos_adj)
1507                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1508                                          azx_dev, &bdl, ofs,
1509                                          period_bytes - pos_adj, 0);
1510                 else
1511                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1512                                          azx_dev, &bdl, ofs,
1513                                          period_bytes,
1514                                          !azx_dev->no_period_wakeup);
1515                 if (ofs < 0)
1516                         goto error;
1517         }
1518         return 0;
1519
1520  error:
1521         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1522                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1523         return -EINVAL;
1524 }
1525
1526 /* reset stream */
1527 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1528 {
1529         unsigned char val;
1530         int timeout;
1531
1532         azx_stream_clear(chip, azx_dev);
1533
1534         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1535                       SD_CTL_STREAM_RESET);
1536         udelay(3);
1537         timeout = 300;
1538         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1539                --timeout)
1540                 ;
1541         val &= ~SD_CTL_STREAM_RESET;
1542         azx_sd_writeb(azx_dev, SD_CTL, val);
1543         udelay(3);
1544
1545         timeout = 300;
1546         /* waiting for hardware to report that the stream is out of reset */
1547         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1548                --timeout)
1549                 ;
1550
1551         /* reset first position - may not be synced with hw at this time */
1552         *azx_dev->posbuf = 0;
1553 }
1554
1555 /*
1556  * set up the SD for streaming
1557  */
1558 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1559 {
1560         unsigned int val;
1561         /* make sure the run bit is zero for SD */
1562         azx_stream_clear(chip, azx_dev);
1563         /* program the stream_tag */
1564         val = azx_sd_readl(azx_dev, SD_CTL);
1565         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1566                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1567         if (!azx_snoop(chip))
1568                 val |= SD_CTL_TRAFFIC_PRIO;
1569         azx_sd_writel(azx_dev, SD_CTL, val);
1570
1571         /* program the length of samples in cyclic buffer */
1572         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1573
1574         /* program the stream format */
1575         /* this value needs to be the same as the one programmed */
1576         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1577
1578         /* program the stream LVI (last valid index) of the BDL */
1579         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1580
1581         /* program the BDL address */
1582         /* lower BDL address */
1583         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1584         /* upper BDL address */
1585         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1586
1587         /* enable the position buffer */
1588         if (chip->position_fix[0] != POS_FIX_LPIB ||
1589             chip->position_fix[1] != POS_FIX_LPIB) {
1590                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1591                         azx_writel(chip, DPLBASE,
1592                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1593         }
1594
1595         /* set the interrupt enable bits in the descriptor control register */
1596         azx_sd_writel(azx_dev, SD_CTL,
1597                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1598
1599         return 0;
1600 }
1601
1602 /*
1603  * Probe the given codec address
1604  */
1605 static int probe_codec(struct azx *chip, int addr)
1606 {
1607         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1608                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1609         unsigned int res;
1610
1611         mutex_lock(&chip->bus->cmd_mutex);
1612         chip->probing = 1;
1613         azx_send_cmd(chip->bus, cmd);
1614         res = azx_get_response(chip->bus, addr);
1615         chip->probing = 0;
1616         mutex_unlock(&chip->bus->cmd_mutex);
1617         if (res == -1)
1618                 return -EIO;
1619         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1620         return 0;
1621 }
1622
1623 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1624                                  struct hda_pcm *cpcm);
1625 static void azx_stop_chip(struct azx *chip);
1626
1627 static void azx_bus_reset(struct hda_bus *bus)
1628 {
1629         struct azx *chip = bus->private_data;
1630
1631         bus->in_reset = 1;
1632         azx_stop_chip(chip);
1633         azx_init_chip(chip, 1);
1634 #ifdef CONFIG_PM
1635         if (chip->initialized) {
1636                 struct azx_pcm *p;
1637                 list_for_each_entry(p, &chip->pcm_list, list)
1638                         snd_pcm_suspend_all(p->pcm);
1639                 snd_hda_suspend(chip->bus);
1640                 snd_hda_resume(chip->bus);
1641         }
1642 #endif
1643         bus->in_reset = 0;
1644 }
1645
1646 static int get_jackpoll_interval(struct azx *chip)
1647 {
1648         int i = jackpoll_ms[chip->dev_index];
1649         unsigned int j;
1650         if (i == 0)
1651                 return 0;
1652         if (i < 50 || i > 60000)
1653                 j = 0;
1654         else
1655                 j = msecs_to_jiffies(i);
1656         if (j == 0)
1657                 snd_printk(KERN_WARNING SFX
1658                            "jackpoll_ms value out of range: %d\n", i);
1659         return j;
1660 }
1661
1662 /*
1663  * Codec initialization
1664  */
1665
1666 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1667 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1668         [AZX_DRIVER_NVIDIA] = 8,
1669         [AZX_DRIVER_TERA] = 1,
1670 };
1671
1672 static int azx_codec_create(struct azx *chip, const char *model)
1673 {
1674         struct hda_bus_template bus_temp;
1675         int c, codecs, err;
1676         int max_slots;
1677
1678         memset(&bus_temp, 0, sizeof(bus_temp));
1679         bus_temp.private_data = chip;
1680         bus_temp.modelname = model;
1681         bus_temp.pci = chip->pci;
1682         bus_temp.ops.command = azx_send_cmd;
1683         bus_temp.ops.get_response = azx_get_response;
1684         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1685         bus_temp.ops.bus_reset = azx_bus_reset;
1686 #ifdef CONFIG_PM
1687         bus_temp.power_save = &power_save;
1688         bus_temp.ops.pm_notify = azx_power_notify;
1689 #endif
1690 #ifdef CONFIG_SND_HDA_DSP_LOADER
1691         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1692         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1693         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1694 #endif
1695
1696         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1697         if (err < 0)
1698                 return err;
1699
1700         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1701                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1702                 chip->bus->needs_damn_long_delay = 1;
1703         }
1704
1705         codecs = 0;
1706         max_slots = azx_max_codecs[chip->driver_type];
1707         if (!max_slots)
1708                 max_slots = AZX_DEFAULT_CODECS;
1709
1710         /* First try to probe all given codec slots */
1711         for (c = 0; c < max_slots; c++) {
1712                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1713                         if (probe_codec(chip, c) < 0) {
1714                                 /* Some BIOSen give you wrong codec addresses
1715                                  * that don't exist
1716                                  */
1717                                 snd_printk(KERN_WARNING SFX
1718                                            "%s: Codec #%d probe error; "
1719                                            "disabling it...\n", pci_name(chip->pci), c);
1720                                 chip->codec_mask &= ~(1 << c);
1721                                 /* More badly, accessing to a non-existing
1722                                  * codec often screws up the controller chip,
1723                                  * and disturbs the further communications.
1724                                  * Thus if an error occurs during probing,
1725                                  * better to reset the controller chip to
1726                                  * get back to the sanity state.
1727                                  */
1728                                 azx_stop_chip(chip);
1729                                 azx_init_chip(chip, 1);
1730                         }
1731                 }
1732         }
1733
1734         /* AMD chipsets often cause the communication stalls upon certain
1735          * sequence like the pin-detection.  It seems that forcing the synced
1736          * access works around the stall.  Grrr...
1737          */
1738         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1739                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1740                         pci_name(chip->pci));
1741                 chip->bus->sync_write = 1;
1742                 chip->bus->allow_bus_reset = 1;
1743         }
1744
1745         /* Then create codec instances */
1746         for (c = 0; c < max_slots; c++) {
1747                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1748                         struct hda_codec *codec;
1749                         err = snd_hda_codec_new(chip->bus, c, &codec);
1750                         if (err < 0)
1751                                 continue;
1752                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1753                         codec->beep_mode = chip->beep_mode;
1754                         codecs++;
1755                 }
1756         }
1757         if (!codecs) {
1758                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1759                 return -ENXIO;
1760         }
1761         return 0;
1762 }
1763
1764 /* configure each codec instance */
1765 static int azx_codec_configure(struct azx *chip)
1766 {
1767         struct hda_codec *codec;
1768         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1769                 snd_hda_codec_configure(codec);
1770         }
1771         return 0;
1772 }
1773
1774
1775 /*
1776  * PCM support
1777  */
1778
1779 /* assign a stream for the PCM */
1780 static inline struct azx_dev *
1781 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1782 {
1783         int dev, i, nums;
1784         struct azx_dev *res = NULL;
1785         /* make a non-zero unique key for the substream */
1786         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1787                 (substream->stream + 1);
1788
1789         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1790                 dev = chip->playback_index_offset;
1791                 nums = chip->playback_streams;
1792         } else {
1793                 dev = chip->capture_index_offset;
1794                 nums = chip->capture_streams;
1795         }
1796         for (i = 0; i < nums; i++, dev++)
1797                 if (!chip->azx_dev[dev].opened) {
1798                         res = &chip->azx_dev[dev];
1799                         if (res->assigned_key == key)
1800                                 break;
1801                 }
1802         if (res) {
1803                 res->opened = 1;
1804                 res->assigned_key = key;
1805         }
1806         return res;
1807 }
1808
1809 /* release the assigned stream */
1810 static inline void azx_release_device(struct azx_dev *azx_dev)
1811 {
1812         azx_dev->opened = 0;
1813 }
1814
1815 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1816 {
1817         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1818         struct snd_pcm_substream *substream = azx_dev->substream;
1819         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1820         struct azx *chip = apcm->chip;
1821
1822         return azx_readl(chip, WALLCLK);
1823 }
1824
1825 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1826                                 bool force, cycle_t last)
1827 {
1828         struct azx_dev *azx_dev = get_azx_dev(substream);
1829         struct timecounter *tc = &azx_dev->azx_tc;
1830         struct cyclecounter *cc = &azx_dev->azx_cc;
1831         u64 nsec;
1832
1833         cc->read = azx_cc_read;
1834         cc->mask = CLOCKSOURCE_MASK(32);
1835
1836         /*
1837          * Converting from 24 MHz to ns means applying a 125/3 factor.
1838          * To avoid any saturation issues in intermediate operations,
1839          * the 125 factor is applied first. The division is applied
1840          * last after reading the timecounter value.
1841          * Applying the 1/3 factor as part of the multiplication
1842          * requires at least 20 bits for a decent precision, however
1843          * overflows occur after about 4 hours or less, not a option.
1844          */
1845
1846         cc->mult = 125; /* saturation after 195 years */
1847         cc->shift = 0;
1848
1849         nsec = 0; /* audio time is elapsed time since trigger */
1850         timecounter_init(tc, cc, nsec);
1851         if (force)
1852                 /*
1853                  * force timecounter to use predefined value,
1854                  * used for synchronized starts
1855                  */
1856                 tc->cycle_last = last;
1857 }
1858
1859 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1860                                 struct timespec *ts)
1861 {
1862         struct azx_dev *azx_dev = get_azx_dev(substream);
1863         u64 nsec;
1864
1865         nsec = timecounter_read(&azx_dev->azx_tc);
1866         nsec = div_u64(nsec, 3); /* can be optimized */
1867
1868         *ts = ns_to_timespec(nsec);
1869
1870         return 0;
1871 }
1872
1873 static struct snd_pcm_hardware azx_pcm_hw = {
1874         .info =                 (SNDRV_PCM_INFO_MMAP |
1875                                  SNDRV_PCM_INFO_INTERLEAVED |
1876                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1877                                  SNDRV_PCM_INFO_MMAP_VALID |
1878                                  /* No full-resume yet implemented */
1879                                  /* SNDRV_PCM_INFO_RESUME |*/
1880                                  SNDRV_PCM_INFO_PAUSE |
1881                                  SNDRV_PCM_INFO_SYNC_START |
1882                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1883                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1884         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1885         .rates =                SNDRV_PCM_RATE_48000,
1886         .rate_min =             48000,
1887         .rate_max =             48000,
1888         .channels_min =         2,
1889         .channels_max =         2,
1890         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1891         .period_bytes_min =     128,
1892         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1893         .periods_min =          2,
1894         .periods_max =          AZX_MAX_FRAG,
1895         .fifo_size =            0,
1896 };
1897
1898 static int azx_pcm_open(struct snd_pcm_substream *substream)
1899 {
1900         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1901         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1902         struct azx *chip = apcm->chip;
1903         struct azx_dev *azx_dev;
1904         struct snd_pcm_runtime *runtime = substream->runtime;
1905         unsigned long flags;
1906         int err;
1907         int buff_step;
1908
1909         mutex_lock(&chip->open_mutex);
1910         azx_dev = azx_assign_device(chip, substream);
1911         if (azx_dev == NULL) {
1912                 mutex_unlock(&chip->open_mutex);
1913                 return -EBUSY;
1914         }
1915         runtime->hw = azx_pcm_hw;
1916         runtime->hw.channels_min = hinfo->channels_min;
1917         runtime->hw.channels_max = hinfo->channels_max;
1918         runtime->hw.formats = hinfo->formats;
1919         runtime->hw.rates = hinfo->rates;
1920         snd_pcm_limit_hw_rates(runtime);
1921         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1922
1923         /* avoid wrap-around with wall-clock */
1924         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1925                                 20,
1926                                 178000000);
1927
1928         if (chip->align_buffer_size)
1929                 /* constrain buffer sizes to be multiple of 128
1930                    bytes. This is more efficient in terms of memory
1931                    access but isn't required by the HDA spec and
1932                    prevents users from specifying exact period/buffer
1933                    sizes. For example for 44.1kHz, a period size set
1934                    to 20ms will be rounded to 19.59ms. */
1935                 buff_step = 128;
1936         else
1937                 /* Don't enforce steps on buffer sizes, still need to
1938                    be multiple of 4 bytes (HDA spec). Tested on Intel
1939                    HDA controllers, may not work on all devices where
1940                    option needs to be disabled */
1941                 buff_step = 4;
1942
1943         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1944                                    buff_step);
1945         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1946                                    buff_step);
1947         snd_hda_power_up_d3wait(apcm->codec);
1948         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1949         if (err < 0) {
1950                 azx_release_device(azx_dev);
1951                 snd_hda_power_down(apcm->codec);
1952                 mutex_unlock(&chip->open_mutex);
1953                 return err;
1954         }
1955         snd_pcm_limit_hw_rates(runtime);
1956         /* sanity check */
1957         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1958             snd_BUG_ON(!runtime->hw.channels_max) ||
1959             snd_BUG_ON(!runtime->hw.formats) ||
1960             snd_BUG_ON(!runtime->hw.rates)) {
1961                 azx_release_device(azx_dev);
1962                 hinfo->ops.close(hinfo, apcm->codec, substream);
1963                 snd_hda_power_down(apcm->codec);
1964                 mutex_unlock(&chip->open_mutex);
1965                 return -EINVAL;
1966         }
1967
1968         /* disable WALLCLOCK timestamps for capture streams
1969            until we figure out how to handle digital inputs */
1970         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1971                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1972
1973         spin_lock_irqsave(&chip->reg_lock, flags);
1974         azx_dev->substream = substream;
1975         azx_dev->running = 0;
1976         spin_unlock_irqrestore(&chip->reg_lock, flags);
1977
1978         runtime->private_data = azx_dev;
1979         snd_pcm_set_sync(substream);
1980         mutex_unlock(&chip->open_mutex);
1981         return 0;
1982 }
1983
1984 static int azx_pcm_close(struct snd_pcm_substream *substream)
1985 {
1986         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1987         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1988         struct azx *chip = apcm->chip;
1989         struct azx_dev *azx_dev = get_azx_dev(substream);
1990         unsigned long flags;
1991
1992         mutex_lock(&chip->open_mutex);
1993         spin_lock_irqsave(&chip->reg_lock, flags);
1994         azx_dev->substream = NULL;
1995         azx_dev->running = 0;
1996         spin_unlock_irqrestore(&chip->reg_lock, flags);
1997         azx_release_device(azx_dev);
1998         hinfo->ops.close(hinfo, apcm->codec, substream);
1999         snd_hda_power_down(apcm->codec);
2000         mutex_unlock(&chip->open_mutex);
2001         return 0;
2002 }
2003
2004 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2005                              struct snd_pcm_hw_params *hw_params)
2006 {
2007         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2008         struct azx *chip = apcm->chip;
2009         struct azx_dev *azx_dev = get_azx_dev(substream);
2010         int ret;
2011
2012         mark_runtime_wc(chip, azx_dev, substream, false);
2013         azx_dev->bufsize = 0;
2014         azx_dev->period_bytes = 0;
2015         azx_dev->format_val = 0;
2016         ret = snd_pcm_lib_malloc_pages(substream,
2017                                         params_buffer_bytes(hw_params));
2018         if (ret < 0)
2019                 return ret;
2020         mark_runtime_wc(chip, azx_dev, substream, true);
2021         return ret;
2022 }
2023
2024 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2025 {
2026         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2027         struct azx_dev *azx_dev = get_azx_dev(substream);
2028         struct azx *chip = apcm->chip;
2029         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2030
2031         /* reset BDL address */
2032         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2033         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2034         azx_sd_writel(azx_dev, SD_CTL, 0);
2035         azx_dev->bufsize = 0;
2036         azx_dev->period_bytes = 0;
2037         azx_dev->format_val = 0;
2038
2039         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2040
2041         mark_runtime_wc(chip, azx_dev, substream, false);
2042         return snd_pcm_lib_free_pages(substream);
2043 }
2044
2045 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2046 {
2047         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2048         struct azx *chip = apcm->chip;
2049         struct azx_dev *azx_dev = get_azx_dev(substream);
2050         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2051         struct snd_pcm_runtime *runtime = substream->runtime;
2052         unsigned int bufsize, period_bytes, format_val, stream_tag;
2053         int err;
2054         struct hda_spdif_out *spdif =
2055                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2056         unsigned short ctls = spdif ? spdif->ctls : 0;
2057
2058         azx_stream_reset(chip, azx_dev);
2059         format_val = snd_hda_calc_stream_format(runtime->rate,
2060                                                 runtime->channels,
2061                                                 runtime->format,
2062                                                 hinfo->maxbps,
2063                                                 ctls);
2064         if (!format_val) {
2065                 snd_printk(KERN_ERR SFX
2066                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2067                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2068                 return -EINVAL;
2069         }
2070
2071         bufsize = snd_pcm_lib_buffer_bytes(substream);
2072         period_bytes = snd_pcm_lib_period_bytes(substream);
2073
2074         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2075                     pci_name(chip->pci), bufsize, format_val);
2076
2077         if (bufsize != azx_dev->bufsize ||
2078             period_bytes != azx_dev->period_bytes ||
2079             format_val != azx_dev->format_val ||
2080             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2081                 azx_dev->bufsize = bufsize;
2082                 azx_dev->period_bytes = period_bytes;
2083                 azx_dev->format_val = format_val;
2084                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2085                 err = azx_setup_periods(chip, substream, azx_dev);
2086                 if (err < 0)
2087                         return err;
2088         }
2089
2090         /* wallclk has 24Mhz clock source */
2091         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2092                                                 runtime->rate) * 1000);
2093         azx_setup_controller(chip, azx_dev);
2094         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2095                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2096         else
2097                 azx_dev->fifo_size = 0;
2098
2099         stream_tag = azx_dev->stream_tag;
2100         /* CA-IBG chips need the playback stream starting from 1 */
2101         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2102             stream_tag > chip->capture_streams)
2103                 stream_tag -= chip->capture_streams;
2104         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2105                                      azx_dev->format_val, substream);
2106 }
2107
2108 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2109 {
2110         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2111         struct azx *chip = apcm->chip;
2112         struct azx_dev *azx_dev;
2113         struct snd_pcm_substream *s;
2114         int rstart = 0, start, nsync = 0, sbits = 0;
2115         int nwait, timeout;
2116
2117         azx_dev = get_azx_dev(substream);
2118         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2119
2120         switch (cmd) {
2121         case SNDRV_PCM_TRIGGER_START:
2122                 rstart = 1;
2123         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2124         case SNDRV_PCM_TRIGGER_RESUME:
2125                 start = 1;
2126                 break;
2127         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2128         case SNDRV_PCM_TRIGGER_SUSPEND:
2129         case SNDRV_PCM_TRIGGER_STOP:
2130                 start = 0;
2131                 break;
2132         default:
2133                 return -EINVAL;
2134         }
2135
2136         snd_pcm_group_for_each_entry(s, substream) {
2137                 if (s->pcm->card != substream->pcm->card)
2138                         continue;
2139                 azx_dev = get_azx_dev(s);
2140                 sbits |= 1 << azx_dev->index;
2141                 nsync++;
2142                 snd_pcm_trigger_done(s, substream);
2143         }
2144
2145         spin_lock(&chip->reg_lock);
2146
2147         /* first, set SYNC bits of corresponding streams */
2148         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2149                 azx_writel(chip, OLD_SSYNC,
2150                         azx_readl(chip, OLD_SSYNC) | sbits);
2151         else
2152                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2153
2154         snd_pcm_group_for_each_entry(s, substream) {
2155                 if (s->pcm->card != substream->pcm->card)
2156                         continue;
2157                 azx_dev = get_azx_dev(s);
2158                 if (start) {
2159                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2160                         if (!rstart)
2161                                 azx_dev->start_wallclk -=
2162                                                 azx_dev->period_wallclk;
2163                         azx_stream_start(chip, azx_dev);
2164                 } else {
2165                         azx_stream_stop(chip, azx_dev);
2166                 }
2167                 azx_dev->running = start;
2168         }
2169         spin_unlock(&chip->reg_lock);
2170         if (start) {
2171                 /* wait until all FIFOs get ready */
2172                 for (timeout = 5000; timeout; timeout--) {
2173                         nwait = 0;
2174                         snd_pcm_group_for_each_entry(s, substream) {
2175                                 if (s->pcm->card != substream->pcm->card)
2176                                         continue;
2177                                 azx_dev = get_azx_dev(s);
2178                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2179                                       SD_STS_FIFO_READY))
2180                                         nwait++;
2181                         }
2182                         if (!nwait)
2183                                 break;
2184                         cpu_relax();
2185                 }
2186         } else {
2187                 /* wait until all RUN bits are cleared */
2188                 for (timeout = 5000; timeout; timeout--) {
2189                         nwait = 0;
2190                         snd_pcm_group_for_each_entry(s, substream) {
2191                                 if (s->pcm->card != substream->pcm->card)
2192                                         continue;
2193                                 azx_dev = get_azx_dev(s);
2194                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2195                                     SD_CTL_DMA_START)
2196                                         nwait++;
2197                         }
2198                         if (!nwait)
2199                                 break;
2200                         cpu_relax();
2201                 }
2202         }
2203         spin_lock(&chip->reg_lock);
2204         /* reset SYNC bits */
2205         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2206                 azx_writel(chip, OLD_SSYNC,
2207                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2208         else
2209                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2210         if (start) {
2211                 azx_timecounter_init(substream, 0, 0);
2212                 if (nsync > 1) {
2213                         cycle_t cycle_last;
2214
2215                         /* same start cycle for master and group */
2216                         azx_dev = get_azx_dev(substream);
2217                         cycle_last = azx_dev->azx_tc.cycle_last;
2218
2219                         snd_pcm_group_for_each_entry(s, substream) {
2220                                 if (s->pcm->card != substream->pcm->card)
2221                                         continue;
2222                                 azx_timecounter_init(s, 1, cycle_last);
2223                         }
2224                 }
2225         }
2226         spin_unlock(&chip->reg_lock);
2227         return 0;
2228 }
2229
2230 /* get the current DMA position with correction on VIA chips */
2231 static unsigned int azx_via_get_position(struct azx *chip,
2232                                          struct azx_dev *azx_dev)
2233 {
2234         unsigned int link_pos, mini_pos, bound_pos;
2235         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2236         unsigned int fifo_size;
2237
2238         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2239         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2240                 /* Playback, no problem using link position */
2241                 return link_pos;
2242         }
2243
2244         /* Capture */
2245         /* For new chipset,
2246          * use mod to get the DMA position just like old chipset
2247          */
2248         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2249         mod_dma_pos %= azx_dev->period_bytes;
2250
2251         /* azx_dev->fifo_size can't get FIFO size of in stream.
2252          * Get from base address + offset.
2253          */
2254         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2255
2256         if (azx_dev->insufficient) {
2257                 /* Link position never gather than FIFO size */
2258                 if (link_pos <= fifo_size)
2259                         return 0;
2260
2261                 azx_dev->insufficient = 0;
2262         }
2263
2264         if (link_pos <= fifo_size)
2265                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2266         else
2267                 mini_pos = link_pos - fifo_size;
2268
2269         /* Find nearest previous boudary */
2270         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2271         mod_link_pos = link_pos % azx_dev->period_bytes;
2272         if (mod_link_pos >= fifo_size)
2273                 bound_pos = link_pos - mod_link_pos;
2274         else if (mod_dma_pos >= mod_mini_pos)
2275                 bound_pos = mini_pos - mod_mini_pos;
2276         else {
2277                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2278                 if (bound_pos >= azx_dev->bufsize)
2279                         bound_pos = 0;
2280         }
2281
2282         /* Calculate real DMA position we want */
2283         return bound_pos + mod_dma_pos;
2284 }
2285
2286 static unsigned int azx_get_position(struct azx *chip,
2287                                      struct azx_dev *azx_dev,
2288                                      bool with_check)
2289 {
2290         unsigned int pos;
2291         int stream = azx_dev->substream->stream;
2292         int delay = 0;
2293
2294         switch (chip->position_fix[stream]) {
2295         case POS_FIX_LPIB:
2296                 /* read LPIB */
2297                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2298                 break;
2299         case POS_FIX_VIACOMBO:
2300                 pos = azx_via_get_position(chip, azx_dev);
2301                 break;
2302         default:
2303                 /* use the position buffer */
2304                 pos = le32_to_cpu(*azx_dev->posbuf);
2305                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2306                         if (!pos || pos == (u32)-1) {
2307                                 printk(KERN_WARNING
2308                                        "hda-intel: Invalid position buffer, "
2309                                        "using LPIB read method instead.\n");
2310                                 chip->position_fix[stream] = POS_FIX_LPIB;
2311                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2312                         } else
2313                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2314                 }
2315                 break;
2316         }
2317
2318         if (pos >= azx_dev->bufsize)
2319                 pos = 0;
2320
2321         /* calculate runtime delay from LPIB */
2322         if (azx_dev->substream->runtime &&
2323             chip->position_fix[stream] == POS_FIX_POSBUF &&
2324             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2325                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2326                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2327                         delay = pos - lpib_pos;
2328                 else
2329                         delay = lpib_pos - pos;
2330                 if (delay < 0)
2331                         delay += azx_dev->bufsize;
2332                 if (delay >= azx_dev->period_bytes) {
2333                         snd_printk(KERN_WARNING SFX
2334                                    "%s: Unstable LPIB (%d >= %d); "
2335                                    "disabling LPIB delay counting\n",
2336                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2337                         delay = 0;
2338                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2339                 }
2340                 azx_dev->substream->runtime->delay =
2341                         bytes_to_frames(azx_dev->substream->runtime, delay);
2342         }
2343         trace_azx_get_position(chip, azx_dev, pos, delay);
2344         return pos;
2345 }
2346
2347 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2348 {
2349         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2350         struct azx *chip = apcm->chip;
2351         struct azx_dev *azx_dev = get_azx_dev(substream);
2352         return bytes_to_frames(substream->runtime,
2353                                azx_get_position(chip, azx_dev, false));
2354 }
2355
2356 /*
2357  * Check whether the current DMA position is acceptable for updating
2358  * periods.  Returns non-zero if it's OK.
2359  *
2360  * Many HD-audio controllers appear pretty inaccurate about
2361  * the update-IRQ timing.  The IRQ is issued before actually the
2362  * data is processed.  So, we need to process it afterwords in a
2363  * workqueue.
2364  */
2365 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2366 {
2367         u32 wallclk;
2368         unsigned int pos;
2369
2370         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2371         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2372                 return -1;      /* bogus (too early) interrupt */
2373
2374         pos = azx_get_position(chip, azx_dev, true);
2375
2376         if (WARN_ONCE(!azx_dev->period_bytes,
2377                       "hda-intel: zero azx_dev->period_bytes"))
2378                 return -1; /* this shouldn't happen! */
2379         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2380             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2381                 /* NG - it's below the first next period boundary */
2382                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2383         azx_dev->start_wallclk += wallclk;
2384         return 1; /* OK, it's fine */
2385 }
2386
2387 /*
2388  * The work for pending PCM period updates.
2389  */
2390 static void azx_irq_pending_work(struct work_struct *work)
2391 {
2392         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2393         int i, pending, ok;
2394
2395         if (!chip->irq_pending_warned) {
2396                 printk(KERN_WARNING
2397                        "hda-intel: IRQ timing workaround is activated "
2398                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2399                        chip->card->number);
2400                 chip->irq_pending_warned = 1;
2401         }
2402
2403         for (;;) {
2404                 pending = 0;
2405                 spin_lock_irq(&chip->reg_lock);
2406                 for (i = 0; i < chip->num_streams; i++) {
2407                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2408                         if (!azx_dev->irq_pending ||
2409                             !azx_dev->substream ||
2410                             !azx_dev->running)
2411                                 continue;
2412                         ok = azx_position_ok(chip, azx_dev);
2413                         if (ok > 0) {
2414                                 azx_dev->irq_pending = 0;
2415                                 spin_unlock(&chip->reg_lock);
2416                                 snd_pcm_period_elapsed(azx_dev->substream);
2417                                 spin_lock(&chip->reg_lock);
2418                         } else if (ok < 0) {
2419                                 pending = 0;    /* too early */
2420                         } else
2421                                 pending++;
2422                 }
2423                 spin_unlock_irq(&chip->reg_lock);
2424                 if (!pending)
2425                         return;
2426                 msleep(1);
2427         }
2428 }
2429
2430 /* clear irq_pending flags and assure no on-going workq */
2431 static void azx_clear_irq_pending(struct azx *chip)
2432 {
2433         int i;
2434
2435         spin_lock_irq(&chip->reg_lock);
2436         for (i = 0; i < chip->num_streams; i++)
2437                 chip->azx_dev[i].irq_pending = 0;
2438         spin_unlock_irq(&chip->reg_lock);
2439 }
2440
2441 #ifdef CONFIG_X86
2442 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2443                         struct vm_area_struct *area)
2444 {
2445         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2446         struct azx *chip = apcm->chip;
2447         if (!azx_snoop(chip))
2448                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2449         return snd_pcm_lib_default_mmap(substream, area);
2450 }
2451 #else
2452 #define azx_pcm_mmap    NULL
2453 #endif
2454
2455 static struct snd_pcm_ops azx_pcm_ops = {
2456         .open = azx_pcm_open,
2457         .close = azx_pcm_close,
2458         .ioctl = snd_pcm_lib_ioctl,
2459         .hw_params = azx_pcm_hw_params,
2460         .hw_free = azx_pcm_hw_free,
2461         .prepare = azx_pcm_prepare,
2462         .trigger = azx_pcm_trigger,
2463         .pointer = azx_pcm_pointer,
2464         .wall_clock =  azx_get_wallclock_tstamp,
2465         .mmap = azx_pcm_mmap,
2466         .page = snd_pcm_sgbuf_ops_page,
2467 };
2468
2469 static void azx_pcm_free(struct snd_pcm *pcm)
2470 {
2471         struct azx_pcm *apcm = pcm->private_data;
2472         if (apcm) {
2473                 list_del(&apcm->list);
2474                 kfree(apcm);
2475         }
2476 }
2477
2478 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2479
2480 static int
2481 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2482                       struct hda_pcm *cpcm)
2483 {
2484         struct azx *chip = bus->private_data;
2485         struct snd_pcm *pcm;
2486         struct azx_pcm *apcm;
2487         int pcm_dev = cpcm->device;
2488         unsigned int size;
2489         int s, err;
2490
2491         list_for_each_entry(apcm, &chip->pcm_list, list) {
2492                 if (apcm->pcm->device == pcm_dev) {
2493                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2494                                    pci_name(chip->pci), pcm_dev);
2495                         return -EBUSY;
2496                 }
2497         }
2498         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2499                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2500                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2501                           &pcm);
2502         if (err < 0)
2503                 return err;
2504         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2505         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2506         if (apcm == NULL)
2507                 return -ENOMEM;
2508         apcm->chip = chip;
2509         apcm->pcm = pcm;
2510         apcm->codec = codec;
2511         pcm->private_data = apcm;
2512         pcm->private_free = azx_pcm_free;
2513         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2514                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2515         list_add_tail(&apcm->list, &chip->pcm_list);
2516         cpcm->pcm = pcm;
2517         for (s = 0; s < 2; s++) {
2518                 apcm->hinfo[s] = &cpcm->stream[s];
2519                 if (cpcm->stream[s].substreams)
2520                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2521         }
2522         /* buffer pre-allocation */
2523         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2524         if (size > MAX_PREALLOC_SIZE)
2525                 size = MAX_PREALLOC_SIZE;
2526         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2527                                               snd_dma_pci_data(chip->pci),
2528                                               size, MAX_PREALLOC_SIZE);
2529         return 0;
2530 }
2531
2532 /*
2533  * mixer creation - all stuff is implemented in hda module
2534  */
2535 static int azx_mixer_create(struct azx *chip)
2536 {
2537         return snd_hda_build_controls(chip->bus);
2538 }
2539
2540
2541 /*
2542  * initialize SD streams
2543  */
2544 static int azx_init_stream(struct azx *chip)
2545 {
2546         int i;
2547
2548         /* initialize each stream (aka device)
2549          * assign the starting bdl address to each stream (device)
2550          * and initialize
2551          */
2552         for (i = 0; i < chip->num_streams; i++) {
2553                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2554                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2555                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2556                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2557                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2558                 azx_dev->sd_int_sta_mask = 1 << i;
2559                 /* stream tag: must be non-zero and unique */
2560                 azx_dev->index = i;
2561                 azx_dev->stream_tag = i + 1;
2562         }
2563
2564         return 0;
2565 }
2566
2567 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2568 {
2569         if (request_irq(chip->pci->irq, azx_interrupt,
2570                         chip->msi ? 0 : IRQF_SHARED,
2571                         KBUILD_MODNAME, chip)) {
2572                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2573                        "disabling device\n", chip->pci->irq);
2574                 if (do_disconnect)
2575                         snd_card_disconnect(chip->card);
2576                 return -1;
2577         }
2578         chip->irq = chip->pci->irq;
2579         pci_intx(chip->pci, !chip->msi);
2580         return 0;
2581 }
2582
2583
2584 static void azx_stop_chip(struct azx *chip)
2585 {
2586         if (!chip->initialized)
2587                 return;
2588
2589         /* disable interrupts */
2590         azx_int_disable(chip);
2591         azx_int_clear(chip);
2592
2593         /* disable CORB/RIRB */
2594         azx_free_cmd_io(chip);
2595
2596         /* disable position buffer */
2597         azx_writel(chip, DPLBASE, 0);
2598         azx_writel(chip, DPUBASE, 0);
2599
2600         chip->initialized = 0;
2601 }
2602
2603 #ifdef CONFIG_SND_HDA_DSP_LOADER
2604 /*
2605  * DSP loading code (e.g. for CA0132)
2606  */
2607
2608 /* use the first stream for loading DSP */
2609 static struct azx_dev *
2610 azx_get_dsp_loader_dev(struct azx *chip)
2611 {
2612         return &chip->azx_dev[chip->playback_index_offset];
2613 }
2614
2615 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2616                                 unsigned int byte_size,
2617                                 struct snd_dma_buffer *bufp)
2618 {
2619         u32 *bdl;
2620         struct azx *chip = bus->private_data;
2621         struct azx_dev *azx_dev;
2622         int err;
2623
2624         if (snd_hda_lock_devices(bus))
2625                 return -EBUSY;
2626
2627         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2628                                   snd_dma_pci_data(chip->pci),
2629                                   byte_size, bufp);
2630         if (err < 0)
2631                 goto error;
2632
2633         azx_dev = azx_get_dsp_loader_dev(chip);
2634         azx_dev->bufsize = byte_size;
2635         azx_dev->period_bytes = byte_size;
2636         azx_dev->format_val = format;
2637
2638         azx_stream_reset(chip, azx_dev);
2639
2640         /* reset BDL address */
2641         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2642         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2643
2644         azx_dev->frags = 0;
2645         bdl = (u32 *)azx_dev->bdl.area;
2646         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2647         if (err < 0)
2648                 goto error;
2649
2650         azx_setup_controller(chip, azx_dev);
2651         return azx_dev->stream_tag;
2652
2653  error:
2654         snd_hda_unlock_devices(bus);
2655         return err;
2656 }
2657
2658 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2659 {
2660         struct azx *chip = bus->private_data;
2661         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2662
2663         if (start)
2664                 azx_stream_start(chip, azx_dev);
2665         else
2666                 azx_stream_stop(chip, azx_dev);
2667         azx_dev->running = start;
2668 }
2669
2670 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2671                                  struct snd_dma_buffer *dmab)
2672 {
2673         struct azx *chip = bus->private_data;
2674         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2675
2676         /* reset BDL address */
2677         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2678         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2679         azx_sd_writel(azx_dev, SD_CTL, 0);
2680         azx_dev->bufsize = 0;
2681         azx_dev->period_bytes = 0;
2682         azx_dev->format_val = 0;
2683
2684         snd_dma_free_pages(dmab);
2685
2686         snd_hda_unlock_devices(bus);
2687 }
2688 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2689
2690 #ifdef CONFIG_PM
2691 /* power-up/down the controller */
2692 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2693 {
2694         struct azx *chip = bus->private_data;
2695
2696         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2697                 return;
2698
2699         if (power_up)
2700                 pm_runtime_get_sync(&chip->pci->dev);
2701         else
2702                 pm_runtime_put_sync(&chip->pci->dev);
2703 }
2704
2705 static DEFINE_MUTEX(card_list_lock);
2706 static LIST_HEAD(card_list);
2707
2708 static void azx_add_card_list(struct azx *chip)
2709 {
2710         mutex_lock(&card_list_lock);
2711         list_add(&chip->list, &card_list);
2712         mutex_unlock(&card_list_lock);
2713 }
2714
2715 static void azx_del_card_list(struct azx *chip)
2716 {
2717         mutex_lock(&card_list_lock);
2718         list_del_init(&chip->list);
2719         mutex_unlock(&card_list_lock);
2720 }
2721
2722 /* trigger power-save check at writing parameter */
2723 static int param_set_xint(const char *val, const struct kernel_param *kp)
2724 {
2725         struct azx *chip;
2726         struct hda_codec *c;
2727         int prev = power_save;
2728         int ret = param_set_int(val, kp);
2729
2730         if (ret || prev == power_save)
2731                 return ret;
2732
2733         mutex_lock(&card_list_lock);
2734         list_for_each_entry(chip, &card_list, list) {
2735                 if (!chip->bus || chip->disabled)
2736                         continue;
2737                 list_for_each_entry(c, &chip->bus->codec_list, list)
2738                         snd_hda_power_sync(c);
2739         }
2740         mutex_unlock(&card_list_lock);
2741         return 0;
2742 }
2743 #else
2744 #define azx_add_card_list(chip) /* NOP */
2745 #define azx_del_card_list(chip) /* NOP */
2746 #endif /* CONFIG_PM */
2747
2748 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2749 /*
2750  * power management
2751  */
2752 static int azx_suspend(struct device *dev)
2753 {
2754         struct pci_dev *pci = to_pci_dev(dev);
2755         struct snd_card *card = dev_get_drvdata(dev);
2756         struct azx *chip = card->private_data;
2757         struct azx_pcm *p;
2758
2759         if (chip->disabled)
2760                 return 0;
2761
2762         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2763         azx_clear_irq_pending(chip);
2764         list_for_each_entry(p, &chip->pcm_list, list)
2765                 snd_pcm_suspend_all(p->pcm);
2766         if (chip->initialized)
2767                 snd_hda_suspend(chip->bus);
2768         azx_stop_chip(chip);
2769         if (chip->irq >= 0) {
2770                 free_irq(chip->irq, chip);
2771                 chip->irq = -1;
2772         }
2773         if (chip->msi)
2774                 pci_disable_msi(chip->pci);
2775         pci_disable_device(pci);
2776         pci_save_state(pci);
2777         pci_set_power_state(pci, PCI_D3hot);
2778         return 0;
2779 }
2780
2781 static int azx_resume(struct device *dev)
2782 {
2783         struct pci_dev *pci = to_pci_dev(dev);
2784         struct snd_card *card = dev_get_drvdata(dev);
2785         struct azx *chip = card->private_data;
2786
2787         if (chip->disabled)
2788                 return 0;
2789
2790         pci_set_power_state(pci, PCI_D0);
2791         pci_restore_state(pci);
2792         if (pci_enable_device(pci) < 0) {
2793                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2794                        "disabling device\n");
2795                 snd_card_disconnect(card);
2796                 return -EIO;
2797         }
2798         pci_set_master(pci);
2799         if (chip->msi)
2800                 if (pci_enable_msi(pci) < 0)
2801                         chip->msi = 0;
2802         if (azx_acquire_irq(chip, 1) < 0)
2803                 return -EIO;
2804         azx_init_pci(chip);
2805
2806         azx_init_chip(chip, 1);
2807
2808         snd_hda_resume(chip->bus);
2809         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2810         return 0;
2811 }
2812 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2813
2814 #ifdef CONFIG_PM_RUNTIME
2815 static int azx_runtime_suspend(struct device *dev)
2816 {
2817         struct snd_card *card = dev_get_drvdata(dev);
2818         struct azx *chip = card->private_data;
2819
2820         azx_stop_chip(chip);
2821         azx_clear_irq_pending(chip);
2822         return 0;
2823 }
2824
2825 static int azx_runtime_resume(struct device *dev)
2826 {
2827         struct snd_card *card = dev_get_drvdata(dev);
2828         struct azx *chip = card->private_data;
2829
2830         azx_init_pci(chip);
2831         azx_init_chip(chip, 1);
2832         return 0;
2833 }
2834
2835 static int azx_runtime_idle(struct device *dev)
2836 {
2837         struct snd_card *card = dev_get_drvdata(dev);
2838         struct azx *chip = card->private_data;
2839
2840         if (power_save_controller > 0)
2841                 return 0;
2842         if (!power_save_controller ||
2843             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2844                 return -EBUSY;
2845
2846         return 0;
2847 }
2848
2849 #endif /* CONFIG_PM_RUNTIME */
2850
2851 #ifdef CONFIG_PM
2852 static const struct dev_pm_ops azx_pm = {
2853         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2854         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2855 };
2856
2857 #define AZX_PM_OPS      &azx_pm
2858 #else
2859 #define AZX_PM_OPS      NULL
2860 #endif /* CONFIG_PM */
2861
2862
2863 /*
2864  * reboot notifier for hang-up problem at power-down
2865  */
2866 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2867 {
2868         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2869         snd_hda_bus_reboot_notify(chip->bus);
2870         azx_stop_chip(chip);
2871         return NOTIFY_OK;
2872 }
2873
2874 static void azx_notifier_register(struct azx *chip)
2875 {
2876         chip->reboot_notifier.notifier_call = azx_halt;
2877         register_reboot_notifier(&chip->reboot_notifier);
2878 }
2879
2880 static void azx_notifier_unregister(struct azx *chip)
2881 {
2882         if (chip->reboot_notifier.notifier_call)
2883                 unregister_reboot_notifier(&chip->reboot_notifier);
2884 }
2885
2886 static int azx_first_init(struct azx *chip);
2887 static int azx_probe_continue(struct azx *chip);
2888
2889 #ifdef SUPPORT_VGA_SWITCHEROO
2890 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2891
2892 static void azx_vs_set_state(struct pci_dev *pci,
2893                              enum vga_switcheroo_state state)
2894 {
2895         struct snd_card *card = pci_get_drvdata(pci);
2896         struct azx *chip = card->private_data;
2897         bool disabled;
2898
2899         wait_for_completion(&chip->probe_wait);
2900         if (chip->init_failed)
2901                 return;
2902
2903         disabled = (state == VGA_SWITCHEROO_OFF);
2904         if (chip->disabled == disabled)
2905                 return;
2906
2907         if (!chip->bus) {
2908                 chip->disabled = disabled;
2909                 if (!disabled) {
2910                         snd_printk(KERN_INFO SFX
2911                                    "%s: Start delayed initialization\n",
2912                                    pci_name(chip->pci));
2913                         if (azx_first_init(chip) < 0 ||
2914                             azx_probe_continue(chip) < 0) {
2915                                 snd_printk(KERN_ERR SFX
2916                                            "%s: initialization error\n",
2917                                            pci_name(chip->pci));
2918                                 chip->init_failed = true;
2919                         }
2920                 }
2921         } else {
2922                 snd_printk(KERN_INFO SFX
2923                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2924                            disabled ? "Disabling" : "Enabling");
2925                 if (disabled) {
2926                         azx_suspend(&pci->dev);
2927                         chip->disabled = true;
2928                         if (snd_hda_lock_devices(chip->bus))
2929                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2930                                            pci_name(chip->pci));
2931                 } else {
2932                         snd_hda_unlock_devices(chip->bus);
2933                         chip->disabled = false;
2934                         azx_resume(&pci->dev);
2935                 }
2936         }
2937 }
2938
2939 static bool azx_vs_can_switch(struct pci_dev *pci)
2940 {
2941         struct snd_card *card = pci_get_drvdata(pci);
2942         struct azx *chip = card->private_data;
2943
2944         wait_for_completion(&chip->probe_wait);
2945         if (chip->init_failed)
2946                 return false;
2947         if (chip->disabled || !chip->bus)
2948                 return true;
2949         if (snd_hda_lock_devices(chip->bus))
2950                 return false;
2951         snd_hda_unlock_devices(chip->bus);
2952         return true;
2953 }
2954
2955 static void init_vga_switcheroo(struct azx *chip)
2956 {
2957         struct pci_dev *p = get_bound_vga(chip->pci);
2958         if (p) {
2959                 snd_printk(KERN_INFO SFX
2960                            "%s: Handle VGA-switcheroo audio client\n",
2961                            pci_name(chip->pci));
2962                 chip->use_vga_switcheroo = 1;
2963                 pci_dev_put(p);
2964         }
2965 }
2966
2967 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2968         .set_gpu_state = azx_vs_set_state,
2969         .can_switch = azx_vs_can_switch,
2970 };
2971
2972 static int register_vga_switcheroo(struct azx *chip)
2973 {
2974         int err;
2975
2976         if (!chip->use_vga_switcheroo)
2977                 return 0;
2978         /* FIXME: currently only handling DIS controller
2979          * is there any machine with two switchable HDMI audio controllers?
2980          */
2981         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2982                                                     VGA_SWITCHEROO_DIS,
2983                                                     chip->bus != NULL);
2984         if (err < 0)
2985                 return err;
2986         chip->vga_switcheroo_registered = 1;
2987         return 0;
2988 }
2989 #else
2990 #define init_vga_switcheroo(chip)               /* NOP */
2991 #define register_vga_switcheroo(chip)           0
2992 #define check_hdmi_disabled(pci)        false
2993 #endif /* SUPPORT_VGA_SWITCHER */
2994
2995 /*
2996  * destructor
2997  */
2998 static int azx_free(struct azx *chip)
2999 {
3000         int i;
3001
3002         azx_del_card_list(chip);
3003
3004         azx_notifier_unregister(chip);
3005
3006         chip->init_failed = 1; /* to be sure */
3007         complete_all(&chip->probe_wait);
3008
3009         if (use_vga_switcheroo(chip)) {
3010                 if (chip->disabled && chip->bus)
3011                         snd_hda_unlock_devices(chip->bus);
3012                 if (chip->vga_switcheroo_registered)
3013                         vga_switcheroo_unregister_client(chip->pci);
3014         }
3015
3016         if (chip->initialized) {
3017                 azx_clear_irq_pending(chip);
3018                 for (i = 0; i < chip->num_streams; i++)
3019                         azx_stream_stop(chip, &chip->azx_dev[i]);
3020                 azx_stop_chip(chip);
3021         }
3022
3023         if (chip->irq >= 0)
3024                 free_irq(chip->irq, (void*)chip);
3025         if (chip->msi)
3026                 pci_disable_msi(chip->pci);
3027         if (chip->remap_addr)
3028                 iounmap(chip->remap_addr);
3029
3030         if (chip->azx_dev) {
3031                 for (i = 0; i < chip->num_streams; i++)
3032                         if (chip->azx_dev[i].bdl.area) {
3033                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3034                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3035                         }
3036         }
3037         if (chip->rb.area) {
3038                 mark_pages_wc(chip, &chip->rb, false);
3039                 snd_dma_free_pages(&chip->rb);
3040         }
3041         if (chip->posbuf.area) {
3042                 mark_pages_wc(chip, &chip->posbuf, false);
3043                 snd_dma_free_pages(&chip->posbuf);
3044         }
3045         if (chip->region_requested)
3046                 pci_release_regions(chip->pci);
3047         pci_disable_device(chip->pci);
3048         kfree(chip->azx_dev);
3049 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3050         if (chip->fw)
3051                 release_firmware(chip->fw);
3052 #endif
3053         kfree(chip);
3054
3055         return 0;
3056 }
3057
3058 static int azx_dev_free(struct snd_device *device)
3059 {
3060         return azx_free(device->device_data);
3061 }
3062
3063 #ifdef SUPPORT_VGA_SWITCHEROO
3064 /*
3065  * Check of disabled HDMI controller by vga-switcheroo
3066  */
3067 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3068 {
3069         struct pci_dev *p;
3070
3071         /* check only discrete GPU */
3072         switch (pci->vendor) {
3073         case PCI_VENDOR_ID_ATI:
3074         case PCI_VENDOR_ID_AMD:
3075         case PCI_VENDOR_ID_NVIDIA:
3076                 if (pci->devfn == 1) {
3077                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3078                                                         pci->bus->number, 0);
3079                         if (p) {
3080                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3081                                         return p;
3082                                 pci_dev_put(p);
3083                         }
3084                 }
3085                 break;
3086         }
3087         return NULL;
3088 }
3089
3090 static bool check_hdmi_disabled(struct pci_dev *pci)
3091 {
3092         bool vga_inactive = false;
3093         struct pci_dev *p = get_bound_vga(pci);
3094
3095         if (p) {
3096                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3097                         vga_inactive = true;
3098                 pci_dev_put(p);
3099         }
3100         return vga_inactive;
3101 }
3102 #endif /* SUPPORT_VGA_SWITCHEROO */
3103
3104 /*
3105  * white/black-listing for position_fix
3106  */
3107 static struct snd_pci_quirk position_fix_list[] = {
3108         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3109         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3110         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3111         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3112         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3113         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3114         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3115         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3116         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3117         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3118         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3119         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3120         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3121         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3122         {}
3123 };
3124
3125 static int check_position_fix(struct azx *chip, int fix)
3126 {
3127         const struct snd_pci_quirk *q;
3128
3129         switch (fix) {
3130         case POS_FIX_AUTO:
3131         case POS_FIX_LPIB:
3132         case POS_FIX_POSBUF:
3133         case POS_FIX_VIACOMBO:
3134         case POS_FIX_COMBO:
3135                 return fix;
3136         }
3137
3138         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3139         if (q) {
3140                 printk(KERN_INFO
3141                        "hda_intel: position_fix set to %d "
3142                        "for device %04x:%04x\n",
3143                        q->value, q->subvendor, q->subdevice);
3144                 return q->value;
3145         }
3146
3147         /* Check VIA/ATI HD Audio Controller exist */
3148         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3149                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3150                 return POS_FIX_VIACOMBO;
3151         }
3152         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3153                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3154                 return POS_FIX_LPIB;
3155         }
3156         return POS_FIX_AUTO;
3157 }
3158
3159 /*
3160  * black-lists for probe_mask
3161  */
3162 static struct snd_pci_quirk probe_mask_list[] = {
3163         /* Thinkpad often breaks the controller communication when accessing
3164          * to the non-working (or non-existing) modem codec slot.
3165          */
3166         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3167         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3168         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3169         /* broken BIOS */
3170         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3171         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3172         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3173         /* forced codec slots */
3174         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3175         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3176         /* WinFast VP200 H (Teradici) user reported broken communication */
3177         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3178         {}
3179 };
3180
3181 #define AZX_FORCE_CODEC_MASK    0x100
3182
3183 static void check_probe_mask(struct azx *chip, int dev)
3184 {
3185         const struct snd_pci_quirk *q;
3186
3187         chip->codec_probe_mask = probe_mask[dev];
3188         if (chip->codec_probe_mask == -1) {
3189                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3190                 if (q) {
3191                         printk(KERN_INFO
3192                                "hda_intel: probe_mask set to 0x%x "
3193                                "for device %04x:%04x\n",
3194                                q->value, q->subvendor, q->subdevice);
3195                         chip->codec_probe_mask = q->value;
3196                 }
3197         }
3198
3199         /* check forced option */
3200         if (chip->codec_probe_mask != -1 &&
3201             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3202                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3203                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3204                        chip->codec_mask);
3205         }
3206 }
3207
3208 /*
3209  * white/black-list for enable_msi
3210  */
3211 static struct snd_pci_quirk msi_black_list[] = {
3212         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3213         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3214         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3215         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3216         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3217         {}
3218 };
3219
3220 static void check_msi(struct azx *chip)
3221 {
3222         const struct snd_pci_quirk *q;
3223
3224         if (enable_msi >= 0) {
3225                 chip->msi = !!enable_msi;
3226                 return;
3227         }
3228         chip->msi = 1;  /* enable MSI as default */
3229         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3230         if (q) {
3231                 printk(KERN_INFO
3232                        "hda_intel: msi for device %04x:%04x set to %d\n",
3233                        q->subvendor, q->subdevice, q->value);
3234                 chip->msi = q->value;
3235                 return;
3236         }
3237
3238         /* NVidia chipsets seem to cause troubles with MSI */
3239         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3240                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3241                 chip->msi = 0;
3242         }
3243 }
3244
3245 /* check the snoop mode availability */
3246 static void azx_check_snoop_available(struct azx *chip)
3247 {
3248         bool snoop = chip->snoop;
3249
3250         switch (chip->driver_type) {
3251         case AZX_DRIVER_VIA:
3252                 /* force to non-snoop mode for a new VIA controller
3253                  * when BIOS is set
3254                  */
3255                 if (snoop) {
3256                         u8 val;
3257                         pci_read_config_byte(chip->pci, 0x42, &val);
3258                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3259                                 snoop = false;
3260                 }
3261                 break;
3262         case AZX_DRIVER_ATIHDMI_NS:
3263                 /* new ATI HDMI requires non-snoop */
3264                 snoop = false;
3265                 break;
3266         }
3267
3268         if (snoop != chip->snoop) {
3269                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3270                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3271                 chip->snoop = snoop;
3272         }
3273 }
3274
3275 /*
3276  * constructor
3277  */
3278 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3279                       int dev, unsigned int driver_caps,
3280                       struct azx **rchip)
3281 {
3282         static struct snd_device_ops ops = {
3283                 .dev_free = azx_dev_free,
3284         };
3285         struct azx *chip;
3286         int err;
3287
3288         *rchip = NULL;
3289
3290         err = pci_enable_device(pci);
3291         if (err < 0)
3292                 return err;
3293
3294         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3295         if (!chip) {
3296                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3297                 pci_disable_device(pci);
3298                 return -ENOMEM;
3299         }
3300
3301         spin_lock_init(&chip->reg_lock);
3302         mutex_init(&chip->open_mutex);
3303         chip->card = card;
3304         chip->pci = pci;
3305         chip->irq = -1;
3306         chip->driver_caps = driver_caps;
3307         chip->driver_type = driver_caps & 0xff;
3308         check_msi(chip);
3309         chip->dev_index = dev;
3310         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3311         INIT_LIST_HEAD(&chip->pcm_list);
3312         INIT_LIST_HEAD(&chip->list);
3313         init_vga_switcheroo(chip);
3314         init_completion(&chip->probe_wait);
3315
3316         chip->position_fix[0] = chip->position_fix[1] =
3317                 check_position_fix(chip, position_fix[dev]);
3318         /* combo mode uses LPIB for playback */
3319         if (chip->position_fix[0] == POS_FIX_COMBO) {
3320