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ALSA: hda - Add support for new AMD HD audio devices
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1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67
68 module_param_array(index, int, NULL, 0444);
69 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
70 module_param_array(id, charp, NULL, 0444);
71 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
74 module_param_array(model, charp, NULL, 0444);
75 MODULE_PARM_DESC(model, "Use the given board model.");
76 module_param_array(position_fix, int, NULL, 0444);
77 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
78                  "(0 = auto, 1 = none, 2 = POSBUF).");
79 module_param_array(bdl_pos_adj, int, NULL, 0644);
80 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
81 module_param_array(probe_mask, int, NULL, 0444);
82 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
83 module_param_array(probe_only, bool, NULL, 0444);
84 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
85 module_param(single_cmd, bool, 0444);
86 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
87                  "(for debugging only).");
88 module_param(enable_msi, int, 0444);
89 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
90 #ifdef CONFIG_SND_HDA_PATCH_LOADER
91 module_param_array(patch, charp, NULL, 0444);
92 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
93 #endif
94
95 #ifdef CONFIG_SND_HDA_POWER_SAVE
96 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
97 module_param(power_save, int, 0644);
98 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
99                  "(in second, 0 = disable).");
100
101 /* reset the HD-audio controller in power save mode.
102  * this may give more power-saving, but will take longer time to
103  * wake up.
104  */
105 static int power_save_controller = 1;
106 module_param(power_save_controller, bool, 0644);
107 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
108 #endif
109
110 MODULE_LICENSE("GPL");
111 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
112                          "{Intel, ICH6M},"
113                          "{Intel, ICH7},"
114                          "{Intel, ESB2},"
115                          "{Intel, ICH8},"
116                          "{Intel, ICH9},"
117                          "{Intel, ICH10},"
118                          "{Intel, PCH},"
119                          "{Intel, SCH},"
120                          "{ATI, SB450},"
121                          "{ATI, SB600},"
122                          "{ATI, RS600},"
123                          "{ATI, RS690},"
124                          "{ATI, RS780},"
125                          "{ATI, R600},"
126                          "{ATI, RV630},"
127                          "{ATI, RV610},"
128                          "{ATI, RV670},"
129                          "{ATI, RV635},"
130                          "{ATI, RV620},"
131                          "{ATI, RV770},"
132                          "{VIA, VT8251},"
133                          "{VIA, VT8237A},"
134                          "{SiS, SIS966},"
135                          "{ULI, M5461}}");
136 MODULE_DESCRIPTION("Intel HDA driver");
137
138 #ifdef CONFIG_SND_VERBOSE_PRINTK
139 #define SFX     /* nop */
140 #else
141 #define SFX     "hda-intel: "
142 #endif
143
144 /*
145  * registers
146  */
147 #define ICH6_REG_GCAP                   0x00
148 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
149 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
150 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
151 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
152 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
153 #define ICH6_REG_VMIN                   0x02
154 #define ICH6_REG_VMAJ                   0x03
155 #define ICH6_REG_OUTPAY                 0x04
156 #define ICH6_REG_INPAY                  0x06
157 #define ICH6_REG_GCTL                   0x08
158 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
159 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
160 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
161 #define ICH6_REG_WAKEEN                 0x0c
162 #define ICH6_REG_STATESTS               0x0e
163 #define ICH6_REG_GSTS                   0x10
164 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
165 #define ICH6_REG_INTCTL                 0x20
166 #define ICH6_REG_INTSTS                 0x24
167 #define ICH6_REG_WALCLK                 0x30
168 #define ICH6_REG_SYNC                   0x34    
169 #define ICH6_REG_CORBLBASE              0x40
170 #define ICH6_REG_CORBUBASE              0x44
171 #define ICH6_REG_CORBWP                 0x48
172 #define ICH6_REG_CORBRP                 0x4a
173 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
174 #define ICH6_REG_CORBCTL                0x4c
175 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
176 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
177 #define ICH6_REG_CORBSTS                0x4d
178 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
179 #define ICH6_REG_CORBSIZE               0x4e
180
181 #define ICH6_REG_RIRBLBASE              0x50
182 #define ICH6_REG_RIRBUBASE              0x54
183 #define ICH6_REG_RIRBWP                 0x58
184 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
185 #define ICH6_REG_RINTCNT                0x5a
186 #define ICH6_REG_RIRBCTL                0x5c
187 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
188 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
189 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
190 #define ICH6_REG_RIRBSTS                0x5d
191 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
192 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
193 #define ICH6_REG_RIRBSIZE               0x5e
194
195 #define ICH6_REG_IC                     0x60
196 #define ICH6_REG_IR                     0x64
197 #define ICH6_REG_IRS                    0x68
198 #define   ICH6_IRS_VALID        (1<<1)
199 #define   ICH6_IRS_BUSY         (1<<0)
200
201 #define ICH6_REG_DPLBASE                0x70
202 #define ICH6_REG_DPUBASE                0x74
203 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
204
205 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
206 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
207
208 /* stream register offsets from stream base */
209 #define ICH6_REG_SD_CTL                 0x00
210 #define ICH6_REG_SD_STS                 0x03
211 #define ICH6_REG_SD_LPIB                0x04
212 #define ICH6_REG_SD_CBL                 0x08
213 #define ICH6_REG_SD_LVI                 0x0c
214 #define ICH6_REG_SD_FIFOW               0x0e
215 #define ICH6_REG_SD_FIFOSIZE            0x10
216 #define ICH6_REG_SD_FORMAT              0x12
217 #define ICH6_REG_SD_BDLPL               0x18
218 #define ICH6_REG_SD_BDLPU               0x1c
219
220 /* PCI space */
221 #define ICH6_PCIREG_TCSEL       0x44
222
223 /*
224  * other constants
225  */
226
227 /* max number of SDs */
228 /* ICH, ATI and VIA have 4 playback and 4 capture */
229 #define ICH6_NUM_CAPTURE        4
230 #define ICH6_NUM_PLAYBACK       4
231
232 /* ULI has 6 playback and 5 capture */
233 #define ULI_NUM_CAPTURE         5
234 #define ULI_NUM_PLAYBACK        6
235
236 /* ATI HDMI has 1 playback and 0 capture */
237 #define ATIHDMI_NUM_CAPTURE     0
238 #define ATIHDMI_NUM_PLAYBACK    1
239
240 /* TERA has 4 playback and 3 capture */
241 #define TERA_NUM_CAPTURE        3
242 #define TERA_NUM_PLAYBACK       4
243
244 /* this number is statically defined for simplicity */
245 #define MAX_AZX_DEV             16
246
247 /* max number of fragments - we may use more if allocating more pages for BDL */
248 #define BDL_SIZE                4096
249 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
250 #define AZX_MAX_FRAG            32
251 /* max buffer size - no h/w limit, you can increase as you like */
252 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
253 /* max number of PCM devics per card */
254 #define AZX_MAX_PCMS            8
255
256 /* RIRB int mask: overrun[2], response[0] */
257 #define RIRB_INT_RESPONSE       0x01
258 #define RIRB_INT_OVERRUN        0x04
259 #define RIRB_INT_MASK           0x05
260
261 /* STATESTS int mask: S3,SD2,SD1,SD0 */
262 #define AZX_MAX_CODECS          4
263 #define STATESTS_INT_MASK       0x0f
264
265 /* SD_CTL bits */
266 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
267 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
268 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
269 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
270 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
271 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
272 #define SD_CTL_STREAM_TAG_SHIFT 20
273
274 /* SD_CTL and SD_STS */
275 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
276 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
277 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
278 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
279                                  SD_INT_COMPLETE)
280
281 /* SD_STS */
282 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
283
284 /* INTCTL and INTSTS */
285 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
286 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
287 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
288
289 /* below are so far hardcoded - should read registers in future */
290 #define ICH6_MAX_CORB_ENTRIES   256
291 #define ICH6_MAX_RIRB_ENTRIES   256
292
293 /* position fix mode */
294 enum {
295         POS_FIX_AUTO,
296         POS_FIX_LPIB,
297         POS_FIX_POSBUF,
298 };
299
300 /* Defines for ATI HD Audio support in SB450 south bridge */
301 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
302 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
303
304 /* Defines for Nvidia HDA support */
305 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
306 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
307 #define NVIDIA_HDA_ISTRM_COH          0x4d
308 #define NVIDIA_HDA_OSTRM_COH          0x4c
309 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
310
311 /* Defines for Intel SCH HDA snoop control */
312 #define INTEL_SCH_HDA_DEVC      0x78
313 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
314
315 /* Define IN stream 0 FIFO size offset in VIA controller */
316 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
317 /* Define VIA HD Audio Device ID*/
318 #define VIA_HDAC_DEVICE_ID              0x3288
319
320 /* HD Audio class code */
321 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
322
323 /*
324  */
325
326 struct azx_dev {
327         struct snd_dma_buffer bdl; /* BDL buffer */
328         u32 *posbuf;            /* position buffer pointer */
329
330         unsigned int bufsize;   /* size of the play buffer in bytes */
331         unsigned int period_bytes; /* size of the period in bytes */
332         unsigned int frags;     /* number for period in the play buffer */
333         unsigned int fifo_size; /* FIFO size */
334         unsigned long start_jiffies;    /* start + minimum jiffies */
335         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
336
337         void __iomem *sd_addr;  /* stream descriptor pointer */
338
339         u32 sd_int_sta_mask;    /* stream int status mask */
340
341         /* pcm support */
342         struct snd_pcm_substream *substream;    /* assigned substream,
343                                                  * set in PCM open
344                                                  */
345         unsigned int format_val;        /* format value to be set in the
346                                          * controller and the codec
347                                          */
348         unsigned char stream_tag;       /* assigned stream */
349         unsigned char index;            /* stream index */
350
351         unsigned int opened :1;
352         unsigned int running :1;
353         unsigned int irq_pending :1;
354         unsigned int start_flag: 1;     /* stream full start flag */
355         /*
356          * For VIA:
357          *  A flag to ensure DMA position is 0
358          *  when link position is not greater than FIFO size
359          */
360         unsigned int insufficient :1;
361 };
362
363 /* CORB/RIRB */
364 struct azx_rb {
365         u32 *buf;               /* CORB/RIRB buffer
366                                  * Each CORB entry is 4byte, RIRB is 8byte
367                                  */
368         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
369         /* for RIRB */
370         unsigned short rp, wp;  /* read/write pointers */
371         int cmds;               /* number of pending requests */
372         u32 res;                /* last read value */
373 };
374
375 struct azx {
376         struct snd_card *card;
377         struct pci_dev *pci;
378         int dev_index;
379
380         /* chip type specific */
381         int driver_type;
382         int playback_streams;
383         int playback_index_offset;
384         int capture_streams;
385         int capture_index_offset;
386         int num_streams;
387
388         /* pci resources */
389         unsigned long addr;
390         void __iomem *remap_addr;
391         int irq;
392
393         /* locks */
394         spinlock_t reg_lock;
395         struct mutex open_mutex;
396
397         /* streams (x num_streams) */
398         struct azx_dev *azx_dev;
399
400         /* PCM */
401         struct snd_pcm *pcm[AZX_MAX_PCMS];
402
403         /* HD codec */
404         unsigned short codec_mask;
405         int  codec_probe_mask; /* copied from probe_mask option */
406         struct hda_bus *bus;
407
408         /* CORB/RIRB */
409         struct azx_rb corb;
410         struct azx_rb rirb;
411
412         /* CORB/RIRB and position buffers */
413         struct snd_dma_buffer rb;
414         struct snd_dma_buffer posbuf;
415
416         /* flags */
417         int position_fix;
418         unsigned int running :1;
419         unsigned int initialized :1;
420         unsigned int single_cmd :1;
421         unsigned int polling_mode :1;
422         unsigned int msi :1;
423         unsigned int irq_pending_warned :1;
424         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
425         unsigned int probing :1; /* codec probing phase */
426
427         /* for debugging */
428         unsigned int last_cmd;  /* last issued command (to sync) */
429
430         /* for pending irqs */
431         struct work_struct irq_pending_work;
432
433         /* reboot notifier (for mysterious hangup problem at power-down) */
434         struct notifier_block reboot_notifier;
435 };
436
437 /* driver types */
438 enum {
439         AZX_DRIVER_ICH,
440         AZX_DRIVER_SCH,
441         AZX_DRIVER_ATI,
442         AZX_DRIVER_ATIHDMI,
443         AZX_DRIVER_VIA,
444         AZX_DRIVER_SIS,
445         AZX_DRIVER_ULI,
446         AZX_DRIVER_NVIDIA,
447         AZX_DRIVER_TERA,
448         AZX_DRIVER_GENERIC,
449         AZX_NUM_DRIVERS, /* keep this as last entry */
450 };
451
452 static char *driver_short_names[] __devinitdata = {
453         [AZX_DRIVER_ICH] = "HDA Intel",
454         [AZX_DRIVER_SCH] = "HDA Intel MID",
455         [AZX_DRIVER_ATI] = "HDA ATI SB",
456         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
457         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
458         [AZX_DRIVER_SIS] = "HDA SIS966",
459         [AZX_DRIVER_ULI] = "HDA ULI M5461",
460         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
461         [AZX_DRIVER_TERA] = "HDA Teradici", 
462         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
463 };
464
465 /*
466  * macros for easy use
467  */
468 #define azx_writel(chip,reg,value) \
469         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
470 #define azx_readl(chip,reg) \
471         readl((chip)->remap_addr + ICH6_REG_##reg)
472 #define azx_writew(chip,reg,value) \
473         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
474 #define azx_readw(chip,reg) \
475         readw((chip)->remap_addr + ICH6_REG_##reg)
476 #define azx_writeb(chip,reg,value) \
477         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
478 #define azx_readb(chip,reg) \
479         readb((chip)->remap_addr + ICH6_REG_##reg)
480
481 #define azx_sd_writel(dev,reg,value) \
482         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
483 #define azx_sd_readl(dev,reg) \
484         readl((dev)->sd_addr + ICH6_REG_##reg)
485 #define azx_sd_writew(dev,reg,value) \
486         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
487 #define azx_sd_readw(dev,reg) \
488         readw((dev)->sd_addr + ICH6_REG_##reg)
489 #define azx_sd_writeb(dev,reg,value) \
490         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
491 #define azx_sd_readb(dev,reg) \
492         readb((dev)->sd_addr + ICH6_REG_##reg)
493
494 /* for pcm support */
495 #define get_azx_dev(substream) (substream->runtime->private_data)
496
497 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
498
499 /*
500  * Interface for HD codec
501  */
502
503 /*
504  * CORB / RIRB interface
505  */
506 static int azx_alloc_cmd_io(struct azx *chip)
507 {
508         int err;
509
510         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
511         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
512                                   snd_dma_pci_data(chip->pci),
513                                   PAGE_SIZE, &chip->rb);
514         if (err < 0) {
515                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
516                 return err;
517         }
518         return 0;
519 }
520
521 static void azx_init_cmd_io(struct azx *chip)
522 {
523         /* CORB set up */
524         chip->corb.addr = chip->rb.addr;
525         chip->corb.buf = (u32 *)chip->rb.area;
526         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
527         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
528
529         /* set the corb size to 256 entries (ULI requires explicitly) */
530         azx_writeb(chip, CORBSIZE, 0x02);
531         /* set the corb write pointer to 0 */
532         azx_writew(chip, CORBWP, 0);
533         /* reset the corb hw read pointer */
534         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
535         /* enable corb dma */
536         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
537
538         /* RIRB set up */
539         chip->rirb.addr = chip->rb.addr + 2048;
540         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
541         chip->rirb.wp = chip->rirb.rp = chip->rirb.cmds = 0;
542         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
543         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
544
545         /* set the rirb size to 256 entries (ULI requires explicitly) */
546         azx_writeb(chip, RIRBSIZE, 0x02);
547         /* reset the rirb hw write pointer */
548         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
549         /* set N=1, get RIRB response interrupt for new entry */
550         azx_writew(chip, RINTCNT, 1);
551         /* enable rirb dma and response irq */
552         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
553 }
554
555 static void azx_free_cmd_io(struct azx *chip)
556 {
557         /* disable ringbuffer DMAs */
558         azx_writeb(chip, RIRBCTL, 0);
559         azx_writeb(chip, CORBCTL, 0);
560 }
561
562 /* send a command */
563 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
564 {
565         struct azx *chip = bus->private_data;
566         unsigned int wp;
567
568         /* add command to corb */
569         wp = azx_readb(chip, CORBWP);
570         wp++;
571         wp %= ICH6_MAX_CORB_ENTRIES;
572
573         spin_lock_irq(&chip->reg_lock);
574         chip->rirb.cmds++;
575         chip->corb.buf[wp] = cpu_to_le32(val);
576         azx_writel(chip, CORBWP, wp);
577         spin_unlock_irq(&chip->reg_lock);
578
579         return 0;
580 }
581
582 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
583
584 /* retrieve RIRB entry - called from interrupt handler */
585 static void azx_update_rirb(struct azx *chip)
586 {
587         unsigned int rp, wp;
588         u32 res, res_ex;
589
590         wp = azx_readb(chip, RIRBWP);
591         if (wp == chip->rirb.wp)
592                 return;
593         chip->rirb.wp = wp;
594                 
595         while (chip->rirb.rp != wp) {
596                 chip->rirb.rp++;
597                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
598
599                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
600                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
601                 res = le32_to_cpu(chip->rirb.buf[rp]);
602                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
603                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
604                 else if (chip->rirb.cmds) {
605                         chip->rirb.res = res;
606                         smp_wmb();
607                         chip->rirb.cmds--;
608                 }
609         }
610 }
611
612 /* receive a response */
613 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
614 {
615         struct azx *chip = bus->private_data;
616         unsigned long timeout;
617
618  again:
619         timeout = jiffies + msecs_to_jiffies(1000);
620         for (;;) {
621                 if (chip->polling_mode) {
622                         spin_lock_irq(&chip->reg_lock);
623                         azx_update_rirb(chip);
624                         spin_unlock_irq(&chip->reg_lock);
625                 }
626                 if (!chip->rirb.cmds) {
627                         smp_rmb();
628                         bus->rirb_error = 0;
629                         return chip->rirb.res; /* the last value */
630                 }
631                 if (time_after(jiffies, timeout))
632                         break;
633                 if (bus->needs_damn_long_delay)
634                         msleep(2); /* temporary workaround */
635                 else {
636                         udelay(10);
637                         cond_resched();
638                 }
639         }
640
641         if (chip->msi) {
642                 snd_printk(KERN_WARNING SFX "No response from codec, "
643                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
644                 free_irq(chip->irq, chip);
645                 chip->irq = -1;
646                 pci_disable_msi(chip->pci);
647                 chip->msi = 0;
648                 if (azx_acquire_irq(chip, 1) < 0) {
649                         bus->rirb_error = 1;
650                         return -1;
651                 }
652                 goto again;
653         }
654
655         if (!chip->polling_mode) {
656                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
657                            "switching to polling mode: last cmd=0x%08x\n",
658                            chip->last_cmd);
659                 chip->polling_mode = 1;
660                 goto again;
661         }
662
663         if (chip->probing) {
664                 /* If this critical timeout happens during the codec probing
665                  * phase, this is likely an access to a non-existing codec
666                  * slot.  Better to return an error and reset the system.
667                  */
668                 return -1;
669         }
670
671         /* a fatal communication error; need either to reset or to fallback
672          * to the single_cmd mode
673          */
674         bus->rirb_error = 1;
675         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
676                 bus->response_reset = 1;
677                 return -1; /* give a chance to retry */
678         }
679
680         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
681                    "switching to single_cmd mode: last cmd=0x%08x\n",
682                    chip->last_cmd);
683         chip->single_cmd = 1;
684         bus->response_reset = 0;
685         /* re-initialize CORB/RIRB */
686         azx_free_cmd_io(chip);
687         azx_init_cmd_io(chip);
688         return -1;
689 }
690
691 /*
692  * Use the single immediate command instead of CORB/RIRB for simplicity
693  *
694  * Note: according to Intel, this is not preferred use.  The command was
695  *       intended for the BIOS only, and may get confused with unsolicited
696  *       responses.  So, we shouldn't use it for normal operation from the
697  *       driver.
698  *       I left the codes, however, for debugging/testing purposes.
699  */
700
701 /* receive a response */
702 static int azx_single_wait_for_response(struct azx *chip)
703 {
704         int timeout = 50;
705
706         while (timeout--) {
707                 /* check IRV busy bit */
708                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
709                         /* reuse rirb.res as the response return value */
710                         chip->rirb.res = azx_readl(chip, IR);
711                         return 0;
712                 }
713                 udelay(1);
714         }
715         if (printk_ratelimit())
716                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
717                            azx_readw(chip, IRS));
718         chip->rirb.res = -1;
719         return -EIO;
720 }
721
722 /* send a command */
723 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
724 {
725         struct azx *chip = bus->private_data;
726         int timeout = 50;
727
728         bus->rirb_error = 0;
729         while (timeout--) {
730                 /* check ICB busy bit */
731                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
732                         /* Clear IRV valid bit */
733                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
734                                    ICH6_IRS_VALID);
735                         azx_writel(chip, IC, val);
736                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
737                                    ICH6_IRS_BUSY);
738                         return azx_single_wait_for_response(chip);
739                 }
740                 udelay(1);
741         }
742         if (printk_ratelimit())
743                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
744                            azx_readw(chip, IRS), val);
745         return -EIO;
746 }
747
748 /* receive a response */
749 static unsigned int azx_single_get_response(struct hda_bus *bus)
750 {
751         struct azx *chip = bus->private_data;
752         return chip->rirb.res;
753 }
754
755 /*
756  * The below are the main callbacks from hda_codec.
757  *
758  * They are just the skeleton to call sub-callbacks according to the
759  * current setting of chip->single_cmd.
760  */
761
762 /* send a command */
763 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
764 {
765         struct azx *chip = bus->private_data;
766
767         chip->last_cmd = val;
768         if (chip->single_cmd)
769                 return azx_single_send_cmd(bus, val);
770         else
771                 return azx_corb_send_cmd(bus, val);
772 }
773
774 /* get a response */
775 static unsigned int azx_get_response(struct hda_bus *bus)
776 {
777         struct azx *chip = bus->private_data;
778         if (chip->single_cmd)
779                 return azx_single_get_response(bus);
780         else
781                 return azx_rirb_get_response(bus);
782 }
783
784 #ifdef CONFIG_SND_HDA_POWER_SAVE
785 static void azx_power_notify(struct hda_bus *bus);
786 #endif
787
788 /* reset codec link */
789 static int azx_reset(struct azx *chip)
790 {
791         int count;
792
793         /* clear STATESTS */
794         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
795
796         /* reset controller */
797         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
798
799         count = 50;
800         while (azx_readb(chip, GCTL) && --count)
801                 msleep(1);
802
803         /* delay for >= 100us for codec PLL to settle per spec
804          * Rev 0.9 section 5.5.1
805          */
806         msleep(1);
807
808         /* Bring controller out of reset */
809         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
810
811         count = 50;
812         while (!azx_readb(chip, GCTL) && --count)
813                 msleep(1);
814
815         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
816         msleep(1);
817
818         /* check to see if controller is ready */
819         if (!azx_readb(chip, GCTL)) {
820                 snd_printd(SFX "azx_reset: controller not ready!\n");
821                 return -EBUSY;
822         }
823
824         /* Accept unsolicited responses */
825         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
826
827         /* detect codecs */
828         if (!chip->codec_mask) {
829                 chip->codec_mask = azx_readw(chip, STATESTS);
830                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
831         }
832
833         return 0;
834 }
835
836
837 /*
838  * Lowlevel interface
839  */  
840
841 /* enable interrupts */
842 static void azx_int_enable(struct azx *chip)
843 {
844         /* enable controller CIE and GIE */
845         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
846                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
847 }
848
849 /* disable interrupts */
850 static void azx_int_disable(struct azx *chip)
851 {
852         int i;
853
854         /* disable interrupts in stream descriptor */
855         for (i = 0; i < chip->num_streams; i++) {
856                 struct azx_dev *azx_dev = &chip->azx_dev[i];
857                 azx_sd_writeb(azx_dev, SD_CTL,
858                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
859         }
860
861         /* disable SIE for all streams */
862         azx_writeb(chip, INTCTL, 0);
863
864         /* disable controller CIE and GIE */
865         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
866                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
867 }
868
869 /* clear interrupts */
870 static void azx_int_clear(struct azx *chip)
871 {
872         int i;
873
874         /* clear stream status */
875         for (i = 0; i < chip->num_streams; i++) {
876                 struct azx_dev *azx_dev = &chip->azx_dev[i];
877                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
878         }
879
880         /* clear STATESTS */
881         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
882
883         /* clear rirb status */
884         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
885
886         /* clear int status */
887         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
888 }
889
890 /* start a stream */
891 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
892 {
893         /*
894          * Before stream start, initialize parameter
895          */
896         azx_dev->insufficient = 1;
897
898         /* enable SIE */
899         azx_writeb(chip, INTCTL,
900                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
901         /* set DMA start and interrupt mask */
902         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
903                       SD_CTL_DMA_START | SD_INT_MASK);
904 }
905
906 /* stop DMA */
907 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
908 {
909         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
910                       ~(SD_CTL_DMA_START | SD_INT_MASK));
911         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
912 }
913
914 /* stop a stream */
915 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
916 {
917         azx_stream_clear(chip, azx_dev);
918         /* disable SIE */
919         azx_writeb(chip, INTCTL,
920                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
921 }
922
923
924 /*
925  * reset and start the controller registers
926  */
927 static void azx_init_chip(struct azx *chip)
928 {
929         if (chip->initialized)
930                 return;
931
932         /* reset controller */
933         azx_reset(chip);
934
935         /* initialize interrupts */
936         azx_int_clear(chip);
937         azx_int_enable(chip);
938
939         /* initialize the codec command I/O */
940         azx_init_cmd_io(chip);
941
942         /* program the position buffer */
943         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
944         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
945
946         chip->initialized = 1;
947 }
948
949 /*
950  * initialize the PCI registers
951  */
952 /* update bits in a PCI register byte */
953 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
954                             unsigned char mask, unsigned char val)
955 {
956         unsigned char data;
957
958         pci_read_config_byte(pci, reg, &data);
959         data &= ~mask;
960         data |= (val & mask);
961         pci_write_config_byte(pci, reg, data);
962 }
963
964 static void azx_init_pci(struct azx *chip)
965 {
966         unsigned short snoop;
967
968         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
969          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
970          * Ensuring these bits are 0 clears playback static on some HD Audio
971          * codecs
972          */
973         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
974
975         switch (chip->driver_type) {
976         case AZX_DRIVER_ATI:
977                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
978                 update_pci_byte(chip->pci,
979                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
980                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
981                 break;
982         case AZX_DRIVER_NVIDIA:
983                 /* For NVIDIA HDA, enable snoop */
984                 update_pci_byte(chip->pci,
985                                 NVIDIA_HDA_TRANSREG_ADDR,
986                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
987                 update_pci_byte(chip->pci,
988                                 NVIDIA_HDA_ISTRM_COH,
989                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
990                 update_pci_byte(chip->pci,
991                                 NVIDIA_HDA_OSTRM_COH,
992                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
993                 break;
994         case AZX_DRIVER_SCH:
995                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
996                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
997                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
998                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
999                         pci_read_config_word(chip->pci,
1000                                 INTEL_SCH_HDA_DEVC, &snoop);
1001                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1002                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1003                                 ? "Failed" : "OK");
1004                 }
1005                 break;
1006
1007         }
1008 }
1009
1010
1011 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1012
1013 /*
1014  * interrupt handler
1015  */
1016 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1017 {
1018         struct azx *chip = dev_id;
1019         struct azx_dev *azx_dev;
1020         u32 status;
1021         int i, ok;
1022
1023         spin_lock(&chip->reg_lock);
1024
1025         status = azx_readl(chip, INTSTS);
1026         if (status == 0) {
1027                 spin_unlock(&chip->reg_lock);
1028                 return IRQ_NONE;
1029         }
1030         
1031         for (i = 0; i < chip->num_streams; i++) {
1032                 azx_dev = &chip->azx_dev[i];
1033                 if (status & azx_dev->sd_int_sta_mask) {
1034                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1035                         if (!azx_dev->substream || !azx_dev->running)
1036                                 continue;
1037                         /* check whether this IRQ is really acceptable */
1038                         ok = azx_position_ok(chip, azx_dev);
1039                         if (ok == 1) {
1040                                 azx_dev->irq_pending = 0;
1041                                 spin_unlock(&chip->reg_lock);
1042                                 snd_pcm_period_elapsed(azx_dev->substream);
1043                                 spin_lock(&chip->reg_lock);
1044                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1045                                 /* bogus IRQ, process it later */
1046                                 azx_dev->irq_pending = 1;
1047                                 queue_work(chip->bus->workq,
1048                                            &chip->irq_pending_work);
1049                         }
1050                 }
1051         }
1052
1053         /* clear rirb int */
1054         status = azx_readb(chip, RIRBSTS);
1055         if (status & RIRB_INT_MASK) {
1056                 if (status & RIRB_INT_RESPONSE)
1057                         azx_update_rirb(chip);
1058                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1059         }
1060
1061 #if 0
1062         /* clear state status int */
1063         if (azx_readb(chip, STATESTS) & 0x04)
1064                 azx_writeb(chip, STATESTS, 0x04);
1065 #endif
1066         spin_unlock(&chip->reg_lock);
1067         
1068         return IRQ_HANDLED;
1069 }
1070
1071
1072 /*
1073  * set up a BDL entry
1074  */
1075 static int setup_bdle(struct snd_pcm_substream *substream,
1076                       struct azx_dev *azx_dev, u32 **bdlp,
1077                       int ofs, int size, int with_ioc)
1078 {
1079         u32 *bdl = *bdlp;
1080
1081         while (size > 0) {
1082                 dma_addr_t addr;
1083                 int chunk;
1084
1085                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1086                         return -EINVAL;
1087
1088                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1089                 /* program the address field of the BDL entry */
1090                 bdl[0] = cpu_to_le32((u32)addr);
1091                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1092                 /* program the size field of the BDL entry */
1093                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1094                 bdl[2] = cpu_to_le32(chunk);
1095                 /* program the IOC to enable interrupt
1096                  * only when the whole fragment is processed
1097                  */
1098                 size -= chunk;
1099                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1100                 bdl += 4;
1101                 azx_dev->frags++;
1102                 ofs += chunk;
1103         }
1104         *bdlp = bdl;
1105         return ofs;
1106 }
1107
1108 /*
1109  * set up BDL entries
1110  */
1111 static int azx_setup_periods(struct azx *chip,
1112                              struct snd_pcm_substream *substream,
1113                              struct azx_dev *azx_dev)
1114 {
1115         u32 *bdl;
1116         int i, ofs, periods, period_bytes;
1117         int pos_adj;
1118
1119         /* reset BDL address */
1120         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1121         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1122
1123         period_bytes = azx_dev->period_bytes;
1124         periods = azx_dev->bufsize / period_bytes;
1125
1126         /* program the initial BDL entries */
1127         bdl = (u32 *)azx_dev->bdl.area;
1128         ofs = 0;
1129         azx_dev->frags = 0;
1130         pos_adj = bdl_pos_adj[chip->dev_index];
1131         if (pos_adj > 0) {
1132                 struct snd_pcm_runtime *runtime = substream->runtime;
1133                 int pos_align = pos_adj;
1134                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1135                 if (!pos_adj)
1136                         pos_adj = pos_align;
1137                 else
1138                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1139                                 pos_align;
1140                 pos_adj = frames_to_bytes(runtime, pos_adj);
1141                 if (pos_adj >= period_bytes) {
1142                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1143                                    bdl_pos_adj[chip->dev_index]);
1144                         pos_adj = 0;
1145                 } else {
1146                         ofs = setup_bdle(substream, azx_dev,
1147                                          &bdl, ofs, pos_adj, 1);
1148                         if (ofs < 0)
1149                                 goto error;
1150                 }
1151         } else
1152                 pos_adj = 0;
1153         for (i = 0; i < periods; i++) {
1154                 if (i == periods - 1 && pos_adj)
1155                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1156                                          period_bytes - pos_adj, 0);
1157                 else
1158                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1159                                          period_bytes, 1);
1160                 if (ofs < 0)
1161                         goto error;
1162         }
1163         return 0;
1164
1165  error:
1166         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1167                    azx_dev->bufsize, period_bytes);
1168         return -EINVAL;
1169 }
1170
1171 /* reset stream */
1172 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1173 {
1174         unsigned char val;
1175         int timeout;
1176
1177         azx_stream_clear(chip, azx_dev);
1178
1179         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1180                       SD_CTL_STREAM_RESET);
1181         udelay(3);
1182         timeout = 300;
1183         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1184                --timeout)
1185                 ;
1186         val &= ~SD_CTL_STREAM_RESET;
1187         azx_sd_writeb(azx_dev, SD_CTL, val);
1188         udelay(3);
1189
1190         timeout = 300;
1191         /* waiting for hardware to report that the stream is out of reset */
1192         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1193                --timeout)
1194                 ;
1195
1196         /* reset first position - may not be synced with hw at this time */
1197         *azx_dev->posbuf = 0;
1198 }
1199
1200 /*
1201  * set up the SD for streaming
1202  */
1203 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1204 {
1205         /* make sure the run bit is zero for SD */
1206         azx_stream_clear(chip, azx_dev);
1207         /* program the stream_tag */
1208         azx_sd_writel(azx_dev, SD_CTL,
1209                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1210                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1211
1212         /* program the length of samples in cyclic buffer */
1213         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1214
1215         /* program the stream format */
1216         /* this value needs to be the same as the one programmed */
1217         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1218
1219         /* program the stream LVI (last valid index) of the BDL */
1220         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1221
1222         /* program the BDL address */
1223         /* lower BDL address */
1224         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1225         /* upper BDL address */
1226         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1227
1228         /* enable the position buffer */
1229         if (chip->position_fix == POS_FIX_POSBUF ||
1230             chip->position_fix == POS_FIX_AUTO ||
1231             chip->via_dmapos_patch) {
1232                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1233                         azx_writel(chip, DPLBASE,
1234                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1235         }
1236
1237         /* set the interrupt enable bits in the descriptor control register */
1238         azx_sd_writel(azx_dev, SD_CTL,
1239                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1240
1241         return 0;
1242 }
1243
1244 /*
1245  * Probe the given codec address
1246  */
1247 static int probe_codec(struct azx *chip, int addr)
1248 {
1249         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1250                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1251         unsigned int res;
1252
1253         chip->probing = 1;
1254         azx_send_cmd(chip->bus, cmd);
1255         res = azx_get_response(chip->bus);
1256         chip->probing = 0;
1257         if (res == -1)
1258                 return -EIO;
1259         snd_printdd(SFX "codec #%d probed OK\n", addr);
1260         return 0;
1261 }
1262
1263 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1264                                  struct hda_pcm *cpcm);
1265 static void azx_stop_chip(struct azx *chip);
1266
1267 static void azx_bus_reset(struct hda_bus *bus)
1268 {
1269         struct azx *chip = bus->private_data;
1270
1271         bus->in_reset = 1;
1272         azx_stop_chip(chip);
1273         azx_init_chip(chip);
1274 #ifdef CONFIG_PM
1275         if (chip->initialized) {
1276                 int i;
1277
1278                 for (i = 0; i < AZX_MAX_PCMS; i++)
1279                         snd_pcm_suspend_all(chip->pcm[i]);
1280                 snd_hda_suspend(chip->bus);
1281                 snd_hda_resume(chip->bus);
1282         }
1283 #endif
1284         bus->in_reset = 0;
1285 }
1286
1287 /*
1288  * Codec initialization
1289  */
1290
1291 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1292 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1293         [AZX_DRIVER_TERA] = 1,
1294 };
1295
1296 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1297 {
1298         struct hda_bus_template bus_temp;
1299         int c, codecs, err;
1300         int max_slots;
1301
1302         memset(&bus_temp, 0, sizeof(bus_temp));
1303         bus_temp.private_data = chip;
1304         bus_temp.modelname = model;
1305         bus_temp.pci = chip->pci;
1306         bus_temp.ops.command = azx_send_cmd;
1307         bus_temp.ops.get_response = azx_get_response;
1308         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1309         bus_temp.ops.bus_reset = azx_bus_reset;
1310 #ifdef CONFIG_SND_HDA_POWER_SAVE
1311         bus_temp.power_save = &power_save;
1312         bus_temp.ops.pm_notify = azx_power_notify;
1313 #endif
1314
1315         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1316         if (err < 0)
1317                 return err;
1318
1319         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1320                 chip->bus->needs_damn_long_delay = 1;
1321
1322         codecs = 0;
1323         max_slots = azx_max_codecs[chip->driver_type];
1324         if (!max_slots)
1325                 max_slots = AZX_MAX_CODECS;
1326
1327         /* First try to probe all given codec slots */
1328         for (c = 0; c < max_slots; c++) {
1329                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1330                         if (probe_codec(chip, c) < 0) {
1331                                 /* Some BIOSen give you wrong codec addresses
1332                                  * that don't exist
1333                                  */
1334                                 snd_printk(KERN_WARNING SFX
1335                                            "Codec #%d probe error; "
1336                                            "disabling it...\n", c);
1337                                 chip->codec_mask &= ~(1 << c);
1338                                 /* More badly, accessing to a non-existing
1339                                  * codec often screws up the controller chip,
1340                                  * and distrubs the further communications.
1341                                  * Thus if an error occurs during probing,
1342                                  * better to reset the controller chip to
1343                                  * get back to the sanity state.
1344                                  */
1345                                 azx_stop_chip(chip);
1346                                 azx_init_chip(chip);
1347                         }
1348                 }
1349         }
1350
1351         /* Then create codec instances */
1352         for (c = 0; c < max_slots; c++) {
1353                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1354                         struct hda_codec *codec;
1355                         err = snd_hda_codec_new(chip->bus, c, &codec);
1356                         if (err < 0)
1357                                 continue;
1358                         codecs++;
1359                 }
1360         }
1361         if (!codecs) {
1362                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1363                 return -ENXIO;
1364         }
1365         return 0;
1366 }
1367
1368 /* configure each codec instance */
1369 static int __devinit azx_codec_configure(struct azx *chip)
1370 {
1371         struct hda_codec *codec;
1372         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1373                 snd_hda_codec_configure(codec);
1374         }
1375         return 0;
1376 }
1377
1378
1379 /*
1380  * PCM support
1381  */
1382
1383 /* assign a stream for the PCM */
1384 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1385 {
1386         int dev, i, nums;
1387         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1388                 dev = chip->playback_index_offset;
1389                 nums = chip->playback_streams;
1390         } else {
1391                 dev = chip->capture_index_offset;
1392                 nums = chip->capture_streams;
1393         }
1394         for (i = 0; i < nums; i++, dev++)
1395                 if (!chip->azx_dev[dev].opened) {
1396                         chip->azx_dev[dev].opened = 1;
1397                         return &chip->azx_dev[dev];
1398                 }
1399         return NULL;
1400 }
1401
1402 /* release the assigned stream */
1403 static inline void azx_release_device(struct azx_dev *azx_dev)
1404 {
1405         azx_dev->opened = 0;
1406 }
1407
1408 static struct snd_pcm_hardware azx_pcm_hw = {
1409         .info =                 (SNDRV_PCM_INFO_MMAP |
1410                                  SNDRV_PCM_INFO_INTERLEAVED |
1411                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1412                                  SNDRV_PCM_INFO_MMAP_VALID |
1413                                  /* No full-resume yet implemented */
1414                                  /* SNDRV_PCM_INFO_RESUME |*/
1415                                  SNDRV_PCM_INFO_PAUSE |
1416                                  SNDRV_PCM_INFO_SYNC_START),
1417         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1418         .rates =                SNDRV_PCM_RATE_48000,
1419         .rate_min =             48000,
1420         .rate_max =             48000,
1421         .channels_min =         2,
1422         .channels_max =         2,
1423         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1424         .period_bytes_min =     128,
1425         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1426         .periods_min =          2,
1427         .periods_max =          AZX_MAX_FRAG,
1428         .fifo_size =            0,
1429 };
1430
1431 struct azx_pcm {
1432         struct azx *chip;
1433         struct hda_codec *codec;
1434         struct hda_pcm_stream *hinfo[2];
1435 };
1436
1437 static int azx_pcm_open(struct snd_pcm_substream *substream)
1438 {
1439         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1440         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1441         struct azx *chip = apcm->chip;
1442         struct azx_dev *azx_dev;
1443         struct snd_pcm_runtime *runtime = substream->runtime;
1444         unsigned long flags;
1445         int err;
1446
1447         mutex_lock(&chip->open_mutex);
1448         azx_dev = azx_assign_device(chip, substream->stream);
1449         if (azx_dev == NULL) {
1450                 mutex_unlock(&chip->open_mutex);
1451                 return -EBUSY;
1452         }
1453         runtime->hw = azx_pcm_hw;
1454         runtime->hw.channels_min = hinfo->channels_min;
1455         runtime->hw.channels_max = hinfo->channels_max;
1456         runtime->hw.formats = hinfo->formats;
1457         runtime->hw.rates = hinfo->rates;
1458         snd_pcm_limit_hw_rates(runtime);
1459         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1460         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1461                                    128);
1462         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1463                                    128);
1464         snd_hda_power_up(apcm->codec);
1465         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1466         if (err < 0) {
1467                 azx_release_device(azx_dev);
1468                 snd_hda_power_down(apcm->codec);
1469                 mutex_unlock(&chip->open_mutex);
1470                 return err;
1471         }
1472         snd_pcm_limit_hw_rates(runtime);
1473         /* sanity check */
1474         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1475             snd_BUG_ON(!runtime->hw.channels_max) ||
1476             snd_BUG_ON(!runtime->hw.formats) ||
1477             snd_BUG_ON(!runtime->hw.rates)) {
1478                 azx_release_device(azx_dev);
1479                 hinfo->ops.close(hinfo, apcm->codec, substream);
1480                 snd_hda_power_down(apcm->codec);
1481                 mutex_unlock(&chip->open_mutex);
1482                 return -EINVAL;
1483         }
1484         spin_lock_irqsave(&chip->reg_lock, flags);
1485         azx_dev->substream = substream;
1486         azx_dev->running = 0;
1487         spin_unlock_irqrestore(&chip->reg_lock, flags);
1488
1489         runtime->private_data = azx_dev;
1490         snd_pcm_set_sync(substream);
1491         mutex_unlock(&chip->open_mutex);
1492         return 0;
1493 }
1494
1495 static int azx_pcm_close(struct snd_pcm_substream *substream)
1496 {
1497         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1498         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1499         struct azx *chip = apcm->chip;
1500         struct azx_dev *azx_dev = get_azx_dev(substream);
1501         unsigned long flags;
1502
1503         mutex_lock(&chip->open_mutex);
1504         spin_lock_irqsave(&chip->reg_lock, flags);
1505         azx_dev->substream = NULL;
1506         azx_dev->running = 0;
1507         spin_unlock_irqrestore(&chip->reg_lock, flags);
1508         azx_release_device(azx_dev);
1509         hinfo->ops.close(hinfo, apcm->codec, substream);
1510         snd_hda_power_down(apcm->codec);
1511         mutex_unlock(&chip->open_mutex);
1512         return 0;
1513 }
1514
1515 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1516                              struct snd_pcm_hw_params *hw_params)
1517 {
1518         struct azx_dev *azx_dev = get_azx_dev(substream);
1519
1520         azx_dev->bufsize = 0;
1521         azx_dev->period_bytes = 0;
1522         azx_dev->format_val = 0;
1523         return snd_pcm_lib_malloc_pages(substream,
1524                                         params_buffer_bytes(hw_params));
1525 }
1526
1527 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1528 {
1529         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1530         struct azx_dev *azx_dev = get_azx_dev(substream);
1531         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1532
1533         /* reset BDL address */
1534         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1535         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1536         azx_sd_writel(azx_dev, SD_CTL, 0);
1537         azx_dev->bufsize = 0;
1538         azx_dev->period_bytes = 0;
1539         azx_dev->format_val = 0;
1540
1541         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1542
1543         return snd_pcm_lib_free_pages(substream);
1544 }
1545
1546 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1547 {
1548         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1549         struct azx *chip = apcm->chip;
1550         struct azx_dev *azx_dev = get_azx_dev(substream);
1551         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1552         struct snd_pcm_runtime *runtime = substream->runtime;
1553         unsigned int bufsize, period_bytes, format_val;
1554         int err;
1555
1556         azx_stream_reset(chip, azx_dev);
1557         format_val = snd_hda_calc_stream_format(runtime->rate,
1558                                                 runtime->channels,
1559                                                 runtime->format,
1560                                                 hinfo->maxbps);
1561         if (!format_val) {
1562                 snd_printk(KERN_ERR SFX
1563                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1564                            runtime->rate, runtime->channels, runtime->format);
1565                 return -EINVAL;
1566         }
1567
1568         bufsize = snd_pcm_lib_buffer_bytes(substream);
1569         period_bytes = snd_pcm_lib_period_bytes(substream);
1570
1571         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1572                     bufsize, format_val);
1573
1574         if (bufsize != azx_dev->bufsize ||
1575             period_bytes != azx_dev->period_bytes ||
1576             format_val != azx_dev->format_val) {
1577                 azx_dev->bufsize = bufsize;
1578                 azx_dev->period_bytes = period_bytes;
1579                 azx_dev->format_val = format_val;
1580                 err = azx_setup_periods(chip, substream, azx_dev);
1581                 if (err < 0)
1582                         return err;
1583         }
1584
1585         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1586                                                 (runtime->rate * 2);
1587         azx_setup_controller(chip, azx_dev);
1588         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1589                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1590         else
1591                 azx_dev->fifo_size = 0;
1592
1593         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1594                                   azx_dev->format_val, substream);
1595 }
1596
1597 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1598 {
1599         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1600         struct azx *chip = apcm->chip;
1601         struct azx_dev *azx_dev;
1602         struct snd_pcm_substream *s;
1603         int rstart = 0, start, nsync = 0, sbits = 0;
1604         int nwait, timeout;
1605
1606         switch (cmd) {
1607         case SNDRV_PCM_TRIGGER_START:
1608                 rstart = 1;
1609         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1610         case SNDRV_PCM_TRIGGER_RESUME:
1611                 start = 1;
1612                 break;
1613         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1614         case SNDRV_PCM_TRIGGER_SUSPEND:
1615         case SNDRV_PCM_TRIGGER_STOP:
1616                 start = 0;
1617                 break;
1618         default:
1619                 return -EINVAL;
1620         }
1621
1622         snd_pcm_group_for_each_entry(s, substream) {
1623                 if (s->pcm->card != substream->pcm->card)
1624                         continue;
1625                 azx_dev = get_azx_dev(s);
1626                 sbits |= 1 << azx_dev->index;
1627                 nsync++;
1628                 snd_pcm_trigger_done(s, substream);
1629         }
1630
1631         spin_lock(&chip->reg_lock);
1632         if (nsync > 1) {
1633                 /* first, set SYNC bits of corresponding streams */
1634                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1635         }
1636         snd_pcm_group_for_each_entry(s, substream) {
1637                 if (s->pcm->card != substream->pcm->card)
1638                         continue;
1639                 azx_dev = get_azx_dev(s);
1640                 if (rstart) {
1641                         azx_dev->start_flag = 1;
1642                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1643                 }
1644                 if (start)
1645                         azx_stream_start(chip, azx_dev);
1646                 else
1647                         azx_stream_stop(chip, azx_dev);
1648                 azx_dev->running = start;
1649         }
1650         spin_unlock(&chip->reg_lock);
1651         if (start) {
1652                 if (nsync == 1)
1653                         return 0;
1654                 /* wait until all FIFOs get ready */
1655                 for (timeout = 5000; timeout; timeout--) {
1656                         nwait = 0;
1657                         snd_pcm_group_for_each_entry(s, substream) {
1658                                 if (s->pcm->card != substream->pcm->card)
1659                                         continue;
1660                                 azx_dev = get_azx_dev(s);
1661                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1662                                       SD_STS_FIFO_READY))
1663                                         nwait++;
1664                         }
1665                         if (!nwait)
1666                                 break;
1667                         cpu_relax();
1668                 }
1669         } else {
1670                 /* wait until all RUN bits are cleared */
1671                 for (timeout = 5000; timeout; timeout--) {
1672                         nwait = 0;
1673                         snd_pcm_group_for_each_entry(s, substream) {
1674                                 if (s->pcm->card != substream->pcm->card)
1675                                         continue;
1676                                 azx_dev = get_azx_dev(s);
1677                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1678                                     SD_CTL_DMA_START)
1679                                         nwait++;
1680                         }
1681                         if (!nwait)
1682                                 break;
1683                         cpu_relax();
1684                 }
1685         }
1686         if (nsync > 1) {
1687                 spin_lock(&chip->reg_lock);
1688                 /* reset SYNC bits */
1689                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1690                 spin_unlock(&chip->reg_lock);
1691         }
1692         return 0;
1693 }
1694
1695 /* get the current DMA position with correction on VIA chips */
1696 static unsigned int azx_via_get_position(struct azx *chip,
1697                                          struct azx_dev *azx_dev)
1698 {
1699         unsigned int link_pos, mini_pos, bound_pos;
1700         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1701         unsigned int fifo_size;
1702
1703         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1704         if (azx_dev->index >= 4) {
1705                 /* Playback, no problem using link position */
1706                 return link_pos;
1707         }
1708
1709         /* Capture */
1710         /* For new chipset,
1711          * use mod to get the DMA position just like old chipset
1712          */
1713         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1714         mod_dma_pos %= azx_dev->period_bytes;
1715
1716         /* azx_dev->fifo_size can't get FIFO size of in stream.
1717          * Get from base address + offset.
1718          */
1719         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1720
1721         if (azx_dev->insufficient) {
1722                 /* Link position never gather than FIFO size */
1723                 if (link_pos <= fifo_size)
1724                         return 0;
1725
1726                 azx_dev->insufficient = 0;
1727         }
1728
1729         if (link_pos <= fifo_size)
1730                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1731         else
1732                 mini_pos = link_pos - fifo_size;
1733
1734         /* Find nearest previous boudary */
1735         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1736         mod_link_pos = link_pos % azx_dev->period_bytes;
1737         if (mod_link_pos >= fifo_size)
1738                 bound_pos = link_pos - mod_link_pos;
1739         else if (mod_dma_pos >= mod_mini_pos)
1740                 bound_pos = mini_pos - mod_mini_pos;
1741         else {
1742                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1743                 if (bound_pos >= azx_dev->bufsize)
1744                         bound_pos = 0;
1745         }
1746
1747         /* Calculate real DMA position we want */
1748         return bound_pos + mod_dma_pos;
1749 }
1750
1751 static unsigned int azx_get_position(struct azx *chip,
1752                                      struct azx_dev *azx_dev)
1753 {
1754         unsigned int pos;
1755
1756         if (chip->via_dmapos_patch)
1757                 pos = azx_via_get_position(chip, azx_dev);
1758         else if (chip->position_fix == POS_FIX_POSBUF ||
1759                  chip->position_fix == POS_FIX_AUTO) {
1760                 /* use the position buffer */
1761                 pos = le32_to_cpu(*azx_dev->posbuf);
1762         } else {
1763                 /* read LPIB */
1764                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1765         }
1766         if (pos >= azx_dev->bufsize)
1767                 pos = 0;
1768         return pos;
1769 }
1770
1771 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1772 {
1773         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1774         struct azx *chip = apcm->chip;
1775         struct azx_dev *azx_dev = get_azx_dev(substream);
1776         return bytes_to_frames(substream->runtime,
1777                                azx_get_position(chip, azx_dev));
1778 }
1779
1780 /*
1781  * Check whether the current DMA position is acceptable for updating
1782  * periods.  Returns non-zero if it's OK.
1783  *
1784  * Many HD-audio controllers appear pretty inaccurate about
1785  * the update-IRQ timing.  The IRQ is issued before actually the
1786  * data is processed.  So, we need to process it afterwords in a
1787  * workqueue.
1788  */
1789 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1790 {
1791         unsigned int pos;
1792
1793         if (azx_dev->start_flag &&
1794             time_before_eq(jiffies, azx_dev->start_jiffies))
1795                 return -1;      /* bogus (too early) interrupt */
1796         azx_dev->start_flag = 0;
1797
1798         pos = azx_get_position(chip, azx_dev);
1799         if (chip->position_fix == POS_FIX_AUTO) {
1800                 if (!pos) {
1801                         printk(KERN_WARNING
1802                                "hda-intel: Invalid position buffer, "
1803                                "using LPIB read method instead.\n");
1804                         chip->position_fix = POS_FIX_LPIB;
1805                         pos = azx_get_position(chip, azx_dev);
1806                 } else
1807                         chip->position_fix = POS_FIX_POSBUF;
1808         }
1809
1810         if (!bdl_pos_adj[chip->dev_index])
1811                 return 1; /* no delayed ack */
1812         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1813                 return 0; /* NG - it's below the period boundary */
1814         return 1; /* OK, it's fine */
1815 }
1816
1817 /*
1818  * The work for pending PCM period updates.
1819  */
1820 static void azx_irq_pending_work(struct work_struct *work)
1821 {
1822         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1823         int i, pending;
1824
1825         if (!chip->irq_pending_warned) {
1826                 printk(KERN_WARNING
1827                        "hda-intel: IRQ timing workaround is activated "
1828                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1829                        chip->card->number);
1830                 chip->irq_pending_warned = 1;
1831         }
1832
1833         for (;;) {
1834                 pending = 0;
1835                 spin_lock_irq(&chip->reg_lock);
1836                 for (i = 0; i < chip->num_streams; i++) {
1837                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1838                         if (!azx_dev->irq_pending ||
1839                             !azx_dev->substream ||
1840                             !azx_dev->running)
1841                                 continue;
1842                         if (azx_position_ok(chip, azx_dev)) {
1843                                 azx_dev->irq_pending = 0;
1844                                 spin_unlock(&chip->reg_lock);
1845                                 snd_pcm_period_elapsed(azx_dev->substream);
1846                                 spin_lock(&chip->reg_lock);
1847                         } else
1848                                 pending++;
1849                 }
1850                 spin_unlock_irq(&chip->reg_lock);
1851                 if (!pending)
1852                         return;
1853                 cond_resched();
1854         }
1855 }
1856
1857 /* clear irq_pending flags and assure no on-going workq */
1858 static void azx_clear_irq_pending(struct azx *chip)
1859 {
1860         int i;
1861
1862         spin_lock_irq(&chip->reg_lock);
1863         for (i = 0; i < chip->num_streams; i++)
1864                 chip->azx_dev[i].irq_pending = 0;
1865         spin_unlock_irq(&chip->reg_lock);
1866 }
1867
1868 static struct snd_pcm_ops azx_pcm_ops = {
1869         .open = azx_pcm_open,
1870         .close = azx_pcm_close,
1871         .ioctl = snd_pcm_lib_ioctl,
1872         .hw_params = azx_pcm_hw_params,
1873         .hw_free = azx_pcm_hw_free,
1874         .prepare = azx_pcm_prepare,
1875         .trigger = azx_pcm_trigger,
1876         .pointer = azx_pcm_pointer,
1877         .page = snd_pcm_sgbuf_ops_page,
1878 };
1879
1880 static void azx_pcm_free(struct snd_pcm *pcm)
1881 {
1882         struct azx_pcm *apcm = pcm->private_data;
1883         if (apcm) {
1884                 apcm->chip->pcm[pcm->device] = NULL;
1885                 kfree(apcm);
1886         }
1887 }
1888
1889 static int
1890 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1891                       struct hda_pcm *cpcm)
1892 {
1893         struct azx *chip = bus->private_data;
1894         struct snd_pcm *pcm;
1895         struct azx_pcm *apcm;
1896         int pcm_dev = cpcm->device;
1897         int s, err;
1898
1899         if (pcm_dev >= AZX_MAX_PCMS) {
1900                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1901                            pcm_dev);
1902                 return -EINVAL;
1903         }
1904         if (chip->pcm[pcm_dev]) {
1905                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1906                 return -EBUSY;
1907         }
1908         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1909                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1910                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1911                           &pcm);
1912         if (err < 0)
1913                 return err;
1914         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1915         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1916         if (apcm == NULL)
1917                 return -ENOMEM;
1918         apcm->chip = chip;
1919         apcm->codec = codec;
1920         pcm->private_data = apcm;
1921         pcm->private_free = azx_pcm_free;
1922         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1923                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1924         chip->pcm[pcm_dev] = pcm;
1925         cpcm->pcm = pcm;
1926         for (s = 0; s < 2; s++) {
1927                 apcm->hinfo[s] = &cpcm->stream[s];
1928                 if (cpcm->stream[s].substreams)
1929                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1930         }
1931         /* buffer pre-allocation */
1932         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1933                                               snd_dma_pci_data(chip->pci),
1934                                               1024 * 64, 32 * 1024 * 1024);
1935         return 0;
1936 }
1937
1938 /*
1939  * mixer creation - all stuff is implemented in hda module
1940  */
1941 static int __devinit azx_mixer_create(struct azx *chip)
1942 {
1943         return snd_hda_build_controls(chip->bus);
1944 }
1945
1946
1947 /*
1948  * initialize SD streams
1949  */
1950 static int __devinit azx_init_stream(struct azx *chip)
1951 {
1952         int i;
1953
1954         /* initialize each stream (aka device)
1955          * assign the starting bdl address to each stream (device)
1956          * and initialize
1957          */
1958         for (i = 0; i < chip->num_streams; i++) {
1959                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1960                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1961                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1962                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1963                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1964                 azx_dev->sd_int_sta_mask = 1 << i;
1965                 /* stream tag: must be non-zero and unique */
1966                 azx_dev->index = i;
1967                 azx_dev->stream_tag = i + 1;
1968         }
1969
1970         return 0;
1971 }
1972
1973 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1974 {
1975         if (request_irq(chip->pci->irq, azx_interrupt,
1976                         chip->msi ? 0 : IRQF_SHARED,
1977                         "HDA Intel", chip)) {
1978                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1979                        "disabling device\n", chip->pci->irq);
1980                 if (do_disconnect)
1981                         snd_card_disconnect(chip->card);
1982                 return -1;
1983         }
1984         chip->irq = chip->pci->irq;
1985         pci_intx(chip->pci, !chip->msi);
1986         return 0;
1987 }
1988
1989
1990 static void azx_stop_chip(struct azx *chip)
1991 {
1992         if (!chip->initialized)
1993                 return;
1994
1995         /* disable interrupts */
1996         azx_int_disable(chip);
1997         azx_int_clear(chip);
1998
1999         /* disable CORB/RIRB */
2000         azx_free_cmd_io(chip);
2001
2002         /* disable position buffer */
2003         azx_writel(chip, DPLBASE, 0);
2004         azx_writel(chip, DPUBASE, 0);
2005
2006         chip->initialized = 0;
2007 }
2008
2009 #ifdef CONFIG_SND_HDA_POWER_SAVE
2010 /* power-up/down the controller */
2011 static void azx_power_notify(struct hda_bus *bus)
2012 {
2013         struct azx *chip = bus->private_data;
2014         struct hda_codec *c;
2015         int power_on = 0;
2016
2017         list_for_each_entry(c, &bus->codec_list, list) {
2018                 if (c->power_on) {
2019                         power_on = 1;
2020                         break;
2021                 }
2022         }
2023         if (power_on)
2024                 azx_init_chip(chip);
2025         else if (chip->running && power_save_controller)
2026                 azx_stop_chip(chip);
2027 }
2028 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2029
2030 #ifdef CONFIG_PM
2031 /*
2032  * power management
2033  */
2034
2035 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2036 {
2037         struct hda_codec *codec;
2038
2039         list_for_each_entry(codec, &bus->codec_list, list) {
2040                 if (snd_hda_codec_needs_resume(codec))
2041                         return 1;
2042         }
2043         return 0;
2044 }
2045
2046 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2047 {
2048         struct snd_card *card = pci_get_drvdata(pci);
2049         struct azx *chip = card->private_data;
2050         int i;
2051
2052         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2053         azx_clear_irq_pending(chip);
2054         for (i = 0; i < AZX_MAX_PCMS; i++)
2055                 snd_pcm_suspend_all(chip->pcm[i]);
2056         if (chip->initialized)
2057                 snd_hda_suspend(chip->bus);
2058         azx_stop_chip(chip);
2059         if (chip->irq >= 0) {
2060                 free_irq(chip->irq, chip);
2061                 chip->irq = -1;
2062         }
2063         if (chip->msi)
2064                 pci_disable_msi(chip->pci);
2065         pci_disable_device(pci);
2066         pci_save_state(pci);
2067         pci_set_power_state(pci, pci_choose_state(pci, state));
2068         return 0;
2069 }
2070
2071 static int azx_resume(struct pci_dev *pci)
2072 {
2073         struct snd_card *card = pci_get_drvdata(pci);
2074         struct azx *chip = card->private_data;
2075
2076         pci_set_power_state(pci, PCI_D0);
2077         pci_restore_state(pci);
2078         if (pci_enable_device(pci) < 0) {
2079                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2080                        "disabling device\n");
2081                 snd_card_disconnect(card);
2082                 return -EIO;
2083         }
2084         pci_set_master(pci);
2085         if (chip->msi)
2086                 if (pci_enable_msi(pci) < 0)
2087                         chip->msi = 0;
2088         if (azx_acquire_irq(chip, 1) < 0)
2089                 return -EIO;
2090         azx_init_pci(chip);
2091
2092         if (snd_hda_codecs_inuse(chip->bus))
2093                 azx_init_chip(chip);
2094
2095         snd_hda_resume(chip->bus);
2096         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2097         return 0;
2098 }
2099 #endif /* CONFIG_PM */
2100
2101
2102 /*
2103  * reboot notifier for hang-up problem at power-down
2104  */
2105 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2106 {
2107         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2108         azx_stop_chip(chip);
2109         return NOTIFY_OK;
2110 }
2111
2112 static void azx_notifier_register(struct azx *chip)
2113 {
2114         chip->reboot_notifier.notifier_call = azx_halt;
2115         register_reboot_notifier(&chip->reboot_notifier);
2116 }
2117
2118 static void azx_notifier_unregister(struct azx *chip)
2119 {
2120         if (chip->reboot_notifier.notifier_call)
2121                 unregister_reboot_notifier(&chip->reboot_notifier);
2122 }
2123
2124 /*
2125  * destructor
2126  */
2127 static int azx_free(struct azx *chip)
2128 {
2129         int i;
2130
2131         azx_notifier_unregister(chip);
2132
2133         if (chip->initialized) {
2134                 azx_clear_irq_pending(chip);
2135                 for (i = 0; i < chip->num_streams; i++)
2136                         azx_stream_stop(chip, &chip->azx_dev[i]);
2137                 azx_stop_chip(chip);
2138         }
2139
2140         if (chip->irq >= 0)
2141                 free_irq(chip->irq, (void*)chip);
2142         if (chip->msi)
2143                 pci_disable_msi(chip->pci);
2144         if (chip->remap_addr)
2145                 iounmap(chip->remap_addr);
2146
2147         if (chip->azx_dev) {
2148                 for (i = 0; i < chip->num_streams; i++)
2149                         if (chip->azx_dev[i].bdl.area)
2150                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2151         }
2152         if (chip->rb.area)
2153                 snd_dma_free_pages(&chip->rb);
2154         if (chip->posbuf.area)
2155                 snd_dma_free_pages(&chip->posbuf);
2156         pci_release_regions(chip->pci);
2157         pci_disable_device(chip->pci);
2158         kfree(chip->azx_dev);
2159         kfree(chip);
2160
2161         return 0;
2162 }
2163
2164 static int azx_dev_free(struct snd_device *device)
2165 {
2166         return azx_free(device->device_data);
2167 }
2168
2169 /*
2170  * white/black-listing for position_fix
2171  */
2172 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2173         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2174         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2175         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2176         {}
2177 };
2178
2179 static int __devinit check_position_fix(struct azx *chip, int fix)
2180 {
2181         const struct snd_pci_quirk *q;
2182
2183         switch (fix) {
2184         case POS_FIX_LPIB:
2185         case POS_FIX_POSBUF:
2186                 return fix;
2187         }
2188
2189         /* Check VIA/ATI HD Audio Controller exist */
2190         switch (chip->driver_type) {
2191         case AZX_DRIVER_VIA:
2192         case AZX_DRIVER_ATI:
2193                 chip->via_dmapos_patch = 1;
2194                 /* Use link position directly, avoid any transfer problem. */
2195                 return POS_FIX_LPIB;
2196         }
2197         chip->via_dmapos_patch = 0;
2198
2199         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2200         if (q) {
2201                 printk(KERN_INFO
2202                        "hda_intel: position_fix set to %d "
2203                        "for device %04x:%04x\n",
2204                        q->value, q->subvendor, q->subdevice);
2205                 return q->value;
2206         }
2207         return POS_FIX_AUTO;
2208 }
2209
2210 /*
2211  * black-lists for probe_mask
2212  */
2213 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2214         /* Thinkpad often breaks the controller communication when accessing
2215          * to the non-working (or non-existing) modem codec slot.
2216          */
2217         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2218         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2219         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2220         /* broken BIOS */
2221         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2222         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2223         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2224         /* forced codec slots */
2225         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2226         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2227         {}
2228 };
2229
2230 #define AZX_FORCE_CODEC_MASK    0x100
2231
2232 static void __devinit check_probe_mask(struct azx *chip, int dev)
2233 {
2234         const struct snd_pci_quirk *q;
2235
2236         chip->codec_probe_mask = probe_mask[dev];
2237         if (chip->codec_probe_mask == -1) {
2238                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2239                 if (q) {
2240                         printk(KERN_INFO
2241                                "hda_intel: probe_mask set to 0x%x "
2242                                "for device %04x:%04x\n",
2243                                q->value, q->subvendor, q->subdevice);
2244                         chip->codec_probe_mask = q->value;
2245                 }
2246         }
2247
2248         /* check forced option */
2249         if (chip->codec_probe_mask != -1 &&
2250             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2251                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2252                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2253                        chip->codec_mask);
2254         }
2255 }
2256
2257
2258 /*
2259  * constructor
2260  */
2261 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2262                                 int dev, int driver_type,
2263                                 struct azx **rchip)
2264 {
2265         struct azx *chip;
2266         int i, err;
2267         unsigned short gcap;
2268         static struct snd_device_ops ops = {
2269                 .dev_free = azx_dev_free,
2270         };
2271
2272         *rchip = NULL;
2273
2274         err = pci_enable_device(pci);
2275         if (err < 0)
2276                 return err;
2277
2278         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2279         if (!chip) {
2280                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2281                 pci_disable_device(pci);
2282                 return -ENOMEM;
2283         }
2284
2285         spin_lock_init(&chip->reg_lock);
2286         mutex_init(&chip->open_mutex);
2287         chip->card = card;
2288         chip->pci = pci;
2289         chip->irq = -1;
2290         chip->driver_type = driver_type;
2291         chip->msi = enable_msi;
2292         chip->dev_index = dev;
2293         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2294
2295         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2296         check_probe_mask(chip, dev);
2297
2298         chip->single_cmd = single_cmd;
2299
2300         if (bdl_pos_adj[dev] < 0) {
2301                 switch (chip->driver_type) {
2302                 case AZX_DRIVER_ICH:
2303                         bdl_pos_adj[dev] = 1;
2304                         break;
2305                 default:
2306                         bdl_pos_adj[dev] = 32;
2307                         break;
2308                 }
2309         }
2310
2311 #if BITS_PER_LONG != 64
2312         /* Fix up base address on ULI M5461 */
2313         if (chip->driver_type == AZX_DRIVER_ULI) {
2314                 u16 tmp3;
2315                 pci_read_config_word(pci, 0x40, &tmp3);
2316                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2317                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2318         }
2319 #endif
2320
2321         err = pci_request_regions(pci, "ICH HD audio");
2322         if (err < 0) {
2323                 kfree(chip);
2324                 pci_disable_device(pci);
2325                 return err;
2326         }
2327
2328         chip->addr = pci_resource_start(pci, 0);
2329         chip->remap_addr = pci_ioremap_bar(pci, 0);
2330         if (chip->remap_addr == NULL) {
2331                 snd_printk(KERN_ERR SFX "ioremap error\n");
2332                 err = -ENXIO;
2333                 goto errout;
2334         }
2335
2336         if (chip->msi)
2337                 if (pci_enable_msi(pci) < 0)
2338                         chip->msi = 0;
2339
2340         if (azx_acquire_irq(chip, 0) < 0) {
2341                 err = -EBUSY;
2342                 goto errout;
2343         }
2344
2345         pci_set_master(pci);
2346         synchronize_irq(chip->irq);
2347
2348         gcap = azx_readw(chip, GCAP);
2349         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2350
2351         /* disable SB600 64bit support for safety */
2352         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2353             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2354                 struct pci_dev *p_smbus;
2355                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2356                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2357                                          NULL);
2358                 if (p_smbus) {
2359                         if (p_smbus->revision < 0x30)
2360                                 gcap &= ~ICH6_GCAP_64OK;
2361                         pci_dev_put(p_smbus);
2362                 }
2363         }
2364
2365         /* allow 64bit DMA address if supported by H/W */
2366         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2367                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2368         else {
2369                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2370                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2371         }
2372
2373         /* read number of streams from GCAP register instead of using
2374          * hardcoded value
2375          */
2376         chip->capture_streams = (gcap >> 8) & 0x0f;
2377         chip->playback_streams = (gcap >> 12) & 0x0f;
2378         if (!chip->playback_streams && !chip->capture_streams) {
2379                 /* gcap didn't give any info, switching to old method */
2380
2381                 switch (chip->driver_type) {
2382                 case AZX_DRIVER_ULI:
2383                         chip->playback_streams = ULI_NUM_PLAYBACK;
2384                         chip->capture_streams = ULI_NUM_CAPTURE;
2385                         break;
2386                 case AZX_DRIVER_ATIHDMI:
2387                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2388                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2389                         break;
2390                 case AZX_DRIVER_GENERIC:
2391                 default:
2392                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2393                         chip->capture_streams = ICH6_NUM_CAPTURE;
2394                         break;
2395                 }
2396         }
2397         chip->capture_index_offset = 0;
2398         chip->playback_index_offset = chip->capture_streams;
2399         chip->num_streams = chip->playback_streams + chip->capture_streams;
2400         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2401                                 GFP_KERNEL);
2402         if (!chip->azx_dev) {
2403                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2404                 goto errout;
2405         }
2406
2407         for (i = 0; i < chip->num_streams; i++) {
2408                 /* allocate memory for the BDL for each stream */
2409                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2410                                           snd_dma_pci_data(chip->pci),
2411                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2412                 if (err < 0) {
2413                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2414                         goto errout;
2415                 }
2416         }
2417         /* allocate memory for the position buffer */
2418         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2419                                   snd_dma_pci_data(chip->pci),
2420                                   chip->num_streams * 8, &chip->posbuf);
2421         if (err < 0) {
2422                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2423                 goto errout;
2424         }
2425         /* allocate CORB/RIRB */
2426         err = azx_alloc_cmd_io(chip);
2427         if (err < 0)
2428                 goto errout;
2429
2430         /* initialize streams */
2431         azx_init_stream(chip);
2432
2433         /* initialize chip */
2434         azx_init_pci(chip);
2435         azx_init_chip(chip);
2436
2437         /* codec detection */
2438         if (!chip->codec_mask) {
2439                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2440                 err = -ENODEV;
2441                 goto errout;
2442         }
2443
2444         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2445         if (err <0) {
2446                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2447                 goto errout;
2448         }
2449
2450         strcpy(card->driver, "HDA-Intel");
2451         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2452                 sizeof(card->shortname));
2453         snprintf(card->longname, sizeof(card->longname),
2454                  "%s at 0x%lx irq %i",
2455                  card->shortname, chip->addr, chip->irq);
2456
2457         *rchip = chip;
2458         return 0;
2459
2460  errout:
2461         azx_free(chip);
2462         return err;
2463 }
2464
2465 static void power_down_all_codecs(struct azx *chip)
2466 {
2467 #ifdef CONFIG_SND_HDA_POWER_SAVE
2468         /* The codecs were powered up in snd_hda_codec_new().
2469          * Now all initialization done, so turn them down if possible
2470          */
2471         struct hda_codec *codec;
2472         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2473                 snd_hda_power_down(codec);
2474         }
2475 #endif
2476 }
2477
2478 static int __devinit azx_probe(struct pci_dev *pci,
2479                                const struct pci_device_id *pci_id)
2480 {
2481         static int dev;
2482         struct snd_card *card;
2483         struct azx *chip;
2484         int err;
2485
2486         if (dev >= SNDRV_CARDS)
2487                 return -ENODEV;
2488         if (!enable[dev]) {
2489                 dev++;
2490                 return -ENOENT;
2491         }
2492
2493         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2494         if (err < 0) {
2495                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2496                 return err;
2497         }
2498
2499         /* set this here since it's referred in snd_hda_load_patch() */
2500         snd_card_set_dev(card, &pci->dev);
2501
2502         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2503         if (err < 0)
2504                 goto out_free;
2505         card->private_data = chip;
2506
2507         /* create codec instances */
2508         err = azx_codec_create(chip, model[dev]);
2509         if (err < 0)
2510                 goto out_free;
2511 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2512         if (patch[dev]) {
2513                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2514                            patch[dev]);
2515                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2516                 if (err < 0)
2517                         goto out_free;
2518         }
2519 #endif
2520         if (!probe_only[dev]) {
2521                 err = azx_codec_configure(chip);
2522                 if (err < 0)
2523                         goto out_free;
2524         }
2525
2526         /* create PCM streams */
2527         err = snd_hda_build_pcms(chip->bus);
2528         if (err < 0)
2529                 goto out_free;
2530
2531         /* create mixer controls */
2532         err = azx_mixer_create(chip);
2533         if (err < 0)
2534                 goto out_free;
2535
2536         err = snd_card_register(card);
2537         if (err < 0)
2538                 goto out_free;
2539
2540         pci_set_drvdata(pci, card);
2541         chip->running = 1;
2542         power_down_all_codecs(chip);
2543         azx_notifier_register(chip);
2544
2545         dev++;
2546         return err;
2547 out_free:
2548         snd_card_free(card);
2549         return err;
2550 }
2551
2552 static void __devexit azx_remove(struct pci_dev *pci)
2553 {
2554         snd_card_free(pci_get_drvdata(pci));
2555         pci_set_drvdata(pci, NULL);
2556 }
2557
2558 /* PCI IDs */
2559 static struct pci_device_id azx_ids[] = {
2560         /* ICH 6..10 */
2561         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2562         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2563         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2564         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2565         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2566         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2567         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2568         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2569         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2570         /* PCH */
2571         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2572         /* SCH */
2573         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2574         /* ATI SB 450/600 */
2575         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2576         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2577         /* ATI HDMI */
2578         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2579         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2580         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2581         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2582         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2583         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2584         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2585         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2586         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2587         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2588         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2589         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2590         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2591         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2592         /* VIA VT8251/VT8237A */
2593         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2594         /* SIS966 */
2595         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2596         /* ULI M5461 */
2597         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2598         /* NVIDIA MCP */
2599         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2600         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2601         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2602         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2603         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2604         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2605         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2606         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2607         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2608         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2609         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2610         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2611         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2612         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2613         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2614         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2615         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2616         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2617         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2618         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2619         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2620         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2621         /* Teradici */
2622         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2623         /* Creative X-Fi (CA0110-IBG) */
2624 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2625         /* the following entry conflicts with snd-ctxfi driver,
2626          * as ctxfi driver mutates from HD-audio to native mode with
2627          * a special command sequence.
2628          */
2629         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2630           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2631           .class_mask = 0xffffff,
2632           .driver_data = AZX_DRIVER_GENERIC },
2633 #else
2634         /* this entry seems still valid -- i.e. without emu20kx chip */
2635         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2636 #endif
2637         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2638         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2639           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2640           .class_mask = 0xffffff,
2641           .driver_data = AZX_DRIVER_GENERIC },
2642         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2643           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2644           .class_mask = 0xffffff,
2645           .driver_data = AZX_DRIVER_GENERIC },
2646         { 0, }
2647 };
2648 MODULE_DEVICE_TABLE(pci, azx_ids);
2649
2650 /* pci_driver definition */
2651 static struct pci_driver driver = {
2652         .name = "HDA Intel",
2653         .id_table = azx_ids,
2654         .probe = azx_probe,
2655         .remove = __devexit_p(azx_remove),
2656 #ifdef CONFIG_PM
2657         .suspend = azx_suspend,
2658         .resume = azx_resume,
2659 #endif
2660 };
2661
2662 static int __init alsa_card_azx_init(void)
2663 {
2664         return pci_register_driver(&driver);
2665 }
2666
2667 static void __exit alsa_card_azx_exit(void)
2668 {
2669         pci_unregister_driver(&driver);
2670 }
2671
2672 module_init(alsa_card_azx_init)
2673 module_exit(alsa_card_azx_exit)