ALSA: hda - Add new Kconfig CONFIG_SND_HDA_CODEC_CA0132_DSP
[~shefty/rdma-dev.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #ifdef CONFIG_X86
51 /* for snoop control */
52 #include <asm/pgtable.h>
53 #include <asm/cacheflush.h>
54 #endif
55 #include <sound/core.h>
56 #include <sound/initval.h>
57 #include <linux/vgaarb.h>
58 #include <linux/vga_switcheroo.h>
59 #include <linux/firmware.h>
60 #include "hda_codec.h"
61
62
63 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
65 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
66 static char *model[SNDRV_CARDS];
67 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
68 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
69 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
70 static int probe_only[SNDRV_CARDS];
71 static bool single_cmd;
72 static int enable_msi = -1;
73 #ifdef CONFIG_SND_HDA_PATCH_LOADER
74 static char *patch[SNDRV_CARDS];
75 #endif
76 #ifdef CONFIG_SND_HDA_INPUT_BEEP
77 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
78                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
79 #endif
80
81 module_param_array(index, int, NULL, 0444);
82 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
83 module_param_array(id, charp, NULL, 0444);
84 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
85 module_param_array(enable, bool, NULL, 0444);
86 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
87 module_param_array(model, charp, NULL, 0444);
88 MODULE_PARM_DESC(model, "Use the given board model.");
89 module_param_array(position_fix, int, NULL, 0444);
90 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
91                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
92 module_param_array(bdl_pos_adj, int, NULL, 0644);
93 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
94 module_param_array(probe_mask, int, NULL, 0444);
95 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
96 module_param_array(probe_only, int, NULL, 0444);
97 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
98 module_param(single_cmd, bool, 0444);
99 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
100                  "(for debugging only).");
101 module_param(enable_msi, bint, 0444);
102 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
103 #ifdef CONFIG_SND_HDA_PATCH_LOADER
104 module_param_array(patch, charp, NULL, 0444);
105 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
106 #endif
107 #ifdef CONFIG_SND_HDA_INPUT_BEEP
108 module_param_array(beep_mode, bool, NULL, 0444);
109 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
110                             "(0=off, 1=on) (default=1).");
111 #endif
112
113 #ifdef CONFIG_PM
114 static int param_set_xint(const char *val, const struct kernel_param *kp);
115 static struct kernel_param_ops param_ops_xint = {
116         .set = param_set_xint,
117         .get = param_get_int,
118 };
119 #define param_check_xint param_check_int
120
121 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
122 module_param(power_save, xint, 0644);
123 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
124                  "(in second, 0 = disable).");
125
126 /* reset the HD-audio controller in power save mode.
127  * this may give more power-saving, but will take longer time to
128  * wake up.
129  */
130 static bool power_save_controller = 1;
131 module_param(power_save_controller, bool, 0644);
132 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
133 #endif /* CONFIG_PM */
134
135 static int align_buffer_size = -1;
136 module_param(align_buffer_size, bint, 0644);
137 MODULE_PARM_DESC(align_buffer_size,
138                 "Force buffer and period sizes to be multiple of 128 bytes.");
139
140 #ifdef CONFIG_X86
141 static bool hda_snoop = true;
142 module_param_named(snoop, hda_snoop, bool, 0444);
143 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
144 #define azx_snoop(chip)         (chip)->snoop
145 #else
146 #define hda_snoop               true
147 #define azx_snoop(chip)         true
148 #endif
149
150
151 MODULE_LICENSE("GPL");
152 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
153                          "{Intel, ICH6M},"
154                          "{Intel, ICH7},"
155                          "{Intel, ESB2},"
156                          "{Intel, ICH8},"
157                          "{Intel, ICH9},"
158                          "{Intel, ICH10},"
159                          "{Intel, PCH},"
160                          "{Intel, CPT},"
161                          "{Intel, PPT},"
162                          "{Intel, LPT},"
163                          "{Intel, LPT_LP},"
164                          "{Intel, HPT},"
165                          "{Intel, PBG},"
166                          "{Intel, SCH},"
167                          "{ATI, SB450},"
168                          "{ATI, SB600},"
169                          "{ATI, RS600},"
170                          "{ATI, RS690},"
171                          "{ATI, RS780},"
172                          "{ATI, R600},"
173                          "{ATI, RV630},"
174                          "{ATI, RV610},"
175                          "{ATI, RV670},"
176                          "{ATI, RV635},"
177                          "{ATI, RV620},"
178                          "{ATI, RV770},"
179                          "{VIA, VT8251},"
180                          "{VIA, VT8237A},"
181                          "{SiS, SIS966},"
182                          "{ULI, M5461}}");
183 MODULE_DESCRIPTION("Intel HDA driver");
184
185 #ifdef CONFIG_SND_VERBOSE_PRINTK
186 #define SFX     /* nop */
187 #else
188 #define SFX     "hda-intel: "
189 #endif
190
191 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
192 #ifdef CONFIG_SND_HDA_CODEC_HDMI
193 #define SUPPORT_VGA_SWITCHEROO
194 #endif
195 #endif
196
197
198 /*
199  * registers
200  */
201 #define ICH6_REG_GCAP                   0x00
202 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
203 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
204 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
205 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
206 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
207 #define ICH6_REG_VMIN                   0x02
208 #define ICH6_REG_VMAJ                   0x03
209 #define ICH6_REG_OUTPAY                 0x04
210 #define ICH6_REG_INPAY                  0x06
211 #define ICH6_REG_GCTL                   0x08
212 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
213 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
214 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
215 #define ICH6_REG_WAKEEN                 0x0c
216 #define ICH6_REG_STATESTS               0x0e
217 #define ICH6_REG_GSTS                   0x10
218 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
219 #define ICH6_REG_INTCTL                 0x20
220 #define ICH6_REG_INTSTS                 0x24
221 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
222 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
223 #define ICH6_REG_SSYNC                  0x38
224 #define ICH6_REG_CORBLBASE              0x40
225 #define ICH6_REG_CORBUBASE              0x44
226 #define ICH6_REG_CORBWP                 0x48
227 #define ICH6_REG_CORBRP                 0x4a
228 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
229 #define ICH6_REG_CORBCTL                0x4c
230 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
231 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
232 #define ICH6_REG_CORBSTS                0x4d
233 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
234 #define ICH6_REG_CORBSIZE               0x4e
235
236 #define ICH6_REG_RIRBLBASE              0x50
237 #define ICH6_REG_RIRBUBASE              0x54
238 #define ICH6_REG_RIRBWP                 0x58
239 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
240 #define ICH6_REG_RINTCNT                0x5a
241 #define ICH6_REG_RIRBCTL                0x5c
242 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
243 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
244 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
245 #define ICH6_REG_RIRBSTS                0x5d
246 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
247 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
248 #define ICH6_REG_RIRBSIZE               0x5e
249
250 #define ICH6_REG_IC                     0x60
251 #define ICH6_REG_IR                     0x64
252 #define ICH6_REG_IRS                    0x68
253 #define   ICH6_IRS_VALID        (1<<1)
254 #define   ICH6_IRS_BUSY         (1<<0)
255
256 #define ICH6_REG_DPLBASE                0x70
257 #define ICH6_REG_DPUBASE                0x74
258 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
259
260 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
261 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
262
263 /* stream register offsets from stream base */
264 #define ICH6_REG_SD_CTL                 0x00
265 #define ICH6_REG_SD_STS                 0x03
266 #define ICH6_REG_SD_LPIB                0x04
267 #define ICH6_REG_SD_CBL                 0x08
268 #define ICH6_REG_SD_LVI                 0x0c
269 #define ICH6_REG_SD_FIFOW               0x0e
270 #define ICH6_REG_SD_FIFOSIZE            0x10
271 #define ICH6_REG_SD_FORMAT              0x12
272 #define ICH6_REG_SD_BDLPL               0x18
273 #define ICH6_REG_SD_BDLPU               0x1c
274
275 /* PCI space */
276 #define ICH6_PCIREG_TCSEL       0x44
277
278 /*
279  * other constants
280  */
281
282 /* max number of SDs */
283 /* ICH, ATI and VIA have 4 playback and 4 capture */
284 #define ICH6_NUM_CAPTURE        4
285 #define ICH6_NUM_PLAYBACK       4
286
287 /* ULI has 6 playback and 5 capture */
288 #define ULI_NUM_CAPTURE         5
289 #define ULI_NUM_PLAYBACK        6
290
291 /* ATI HDMI has 1 playback and 0 capture */
292 #define ATIHDMI_NUM_CAPTURE     0
293 #define ATIHDMI_NUM_PLAYBACK    1
294
295 /* TERA has 4 playback and 3 capture */
296 #define TERA_NUM_CAPTURE        3
297 #define TERA_NUM_PLAYBACK       4
298
299 /* this number is statically defined for simplicity */
300 #define MAX_AZX_DEV             16
301
302 /* max number of fragments - we may use more if allocating more pages for BDL */
303 #define BDL_SIZE                4096
304 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
305 #define AZX_MAX_FRAG            32
306 /* max buffer size - no h/w limit, you can increase as you like */
307 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
308
309 /* RIRB int mask: overrun[2], response[0] */
310 #define RIRB_INT_RESPONSE       0x01
311 #define RIRB_INT_OVERRUN        0x04
312 #define RIRB_INT_MASK           0x05
313
314 /* STATESTS int mask: S3,SD2,SD1,SD0 */
315 #define AZX_MAX_CODECS          8
316 #define AZX_DEFAULT_CODECS      4
317 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
318
319 /* SD_CTL bits */
320 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
321 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
322 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
323 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
324 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
325 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
326 #define SD_CTL_STREAM_TAG_SHIFT 20
327
328 /* SD_CTL and SD_STS */
329 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
330 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
331 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
332 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
333                                  SD_INT_COMPLETE)
334
335 /* SD_STS */
336 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
337
338 /* INTCTL and INTSTS */
339 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
340 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
341 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
342
343 /* below are so far hardcoded - should read registers in future */
344 #define ICH6_MAX_CORB_ENTRIES   256
345 #define ICH6_MAX_RIRB_ENTRIES   256
346
347 /* position fix mode */
348 enum {
349         POS_FIX_AUTO,
350         POS_FIX_LPIB,
351         POS_FIX_POSBUF,
352         POS_FIX_VIACOMBO,
353         POS_FIX_COMBO,
354 };
355
356 /* Defines for ATI HD Audio support in SB450 south bridge */
357 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
358 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
359
360 /* Defines for Nvidia HDA support */
361 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
362 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
363 #define NVIDIA_HDA_ISTRM_COH          0x4d
364 #define NVIDIA_HDA_OSTRM_COH          0x4c
365 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
366
367 /* Defines for Intel SCH HDA snoop control */
368 #define INTEL_SCH_HDA_DEVC      0x78
369 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
370
371 /* Define IN stream 0 FIFO size offset in VIA controller */
372 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
373 /* Define VIA HD Audio Device ID*/
374 #define VIA_HDAC_DEVICE_ID              0x3288
375
376 /* HD Audio class code */
377 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
378
379 /*
380  */
381
382 struct azx_dev {
383         struct snd_dma_buffer bdl; /* BDL buffer */
384         u32 *posbuf;            /* position buffer pointer */
385
386         unsigned int bufsize;   /* size of the play buffer in bytes */
387         unsigned int period_bytes; /* size of the period in bytes */
388         unsigned int frags;     /* number for period in the play buffer */
389         unsigned int fifo_size; /* FIFO size */
390         unsigned long start_wallclk;    /* start + minimum wallclk */
391         unsigned long period_wallclk;   /* wallclk for period */
392
393         void __iomem *sd_addr;  /* stream descriptor pointer */
394
395         u32 sd_int_sta_mask;    /* stream int status mask */
396
397         /* pcm support */
398         struct snd_pcm_substream *substream;    /* assigned substream,
399                                                  * set in PCM open
400                                                  */
401         unsigned int format_val;        /* format value to be set in the
402                                          * controller and the codec
403                                          */
404         unsigned char stream_tag;       /* assigned stream */
405         unsigned char index;            /* stream index */
406         int assigned_key;               /* last device# key assigned to */
407
408         unsigned int opened :1;
409         unsigned int running :1;
410         unsigned int irq_pending :1;
411         /*
412          * For VIA:
413          *  A flag to ensure DMA position is 0
414          *  when link position is not greater than FIFO size
415          */
416         unsigned int insufficient :1;
417         unsigned int wc_marked:1;
418         unsigned int no_period_wakeup:1;
419 };
420
421 /* CORB/RIRB */
422 struct azx_rb {
423         u32 *buf;               /* CORB/RIRB buffer
424                                  * Each CORB entry is 4byte, RIRB is 8byte
425                                  */
426         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
427         /* for RIRB */
428         unsigned short rp, wp;  /* read/write pointers */
429         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
430         u32 res[AZX_MAX_CODECS];        /* last read value */
431 };
432
433 struct azx_pcm {
434         struct azx *chip;
435         struct snd_pcm *pcm;
436         struct hda_codec *codec;
437         struct hda_pcm_stream *hinfo[2];
438         struct list_head list;
439 };
440
441 struct azx {
442         struct snd_card *card;
443         struct pci_dev *pci;
444         int dev_index;
445
446         /* chip type specific */
447         int driver_type;
448         unsigned int driver_caps;
449         int playback_streams;
450         int playback_index_offset;
451         int capture_streams;
452         int capture_index_offset;
453         int num_streams;
454
455         /* pci resources */
456         unsigned long addr;
457         void __iomem *remap_addr;
458         int irq;
459
460         /* locks */
461         spinlock_t reg_lock;
462         struct mutex open_mutex;
463
464         /* streams (x num_streams) */
465         struct azx_dev *azx_dev;
466
467         /* PCM */
468         struct list_head pcm_list; /* azx_pcm list */
469
470         /* HD codec */
471         unsigned short codec_mask;
472         int  codec_probe_mask; /* copied from probe_mask option */
473         struct hda_bus *bus;
474         unsigned int beep_mode;
475
476         /* CORB/RIRB */
477         struct azx_rb corb;
478         struct azx_rb rirb;
479
480         /* CORB/RIRB and position buffers */
481         struct snd_dma_buffer rb;
482         struct snd_dma_buffer posbuf;
483
484 #ifdef CONFIG_SND_HDA_PATCH_LOADER
485         const struct firmware *fw;
486 #endif
487
488         /* flags */
489         int position_fix[2]; /* for both playback/capture streams */
490         int poll_count;
491         unsigned int running :1;
492         unsigned int initialized :1;
493         unsigned int single_cmd :1;
494         unsigned int polling_mode :1;
495         unsigned int msi :1;
496         unsigned int irq_pending_warned :1;
497         unsigned int probing :1; /* codec probing phase */
498         unsigned int snoop:1;
499         unsigned int align_buffer_size:1;
500         unsigned int region_requested:1;
501
502         /* VGA-switcheroo setup */
503         unsigned int use_vga_switcheroo:1;
504         unsigned int vga_switcheroo_registered:1;
505         unsigned int init_failed:1; /* delayed init failed */
506         unsigned int disabled:1; /* disabled by VGA-switcher */
507
508         /* for debugging */
509         unsigned int last_cmd[AZX_MAX_CODECS];
510
511         /* for pending irqs */
512         struct work_struct irq_pending_work;
513
514         /* reboot notifier (for mysterious hangup problem at power-down) */
515         struct notifier_block reboot_notifier;
516
517         /* card list (for power_save trigger) */
518         struct list_head list;
519 };
520
521 /* driver types */
522 enum {
523         AZX_DRIVER_ICH,
524         AZX_DRIVER_PCH,
525         AZX_DRIVER_SCH,
526         AZX_DRIVER_ATI,
527         AZX_DRIVER_ATIHDMI,
528         AZX_DRIVER_ATIHDMI_NS,
529         AZX_DRIVER_VIA,
530         AZX_DRIVER_SIS,
531         AZX_DRIVER_ULI,
532         AZX_DRIVER_NVIDIA,
533         AZX_DRIVER_TERA,
534         AZX_DRIVER_CTX,
535         AZX_DRIVER_CTHDA,
536         AZX_DRIVER_GENERIC,
537         AZX_NUM_DRIVERS, /* keep this as last entry */
538 };
539
540 /* driver quirks (capabilities) */
541 /* bits 0-7 are used for indicating driver type */
542 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
543 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
544 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
545 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
546 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
547 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
548 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
549 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
550 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
551 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
552 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
553 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
554 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
555 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
556 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
557 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
558 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
559
560 /* quirks for ATI SB / AMD Hudson */
561 #define AZX_DCAPS_PRESET_ATI_SB \
562         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
563          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
564
565 /* quirks for ATI/AMD HDMI */
566 #define AZX_DCAPS_PRESET_ATI_HDMI \
567         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
568
569 /* quirks for Nvidia */
570 #define AZX_DCAPS_PRESET_NVIDIA \
571         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
572          AZX_DCAPS_ALIGN_BUFSIZE)
573
574 #define AZX_DCAPS_PRESET_CTHDA \
575         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
576
577 /*
578  * VGA-switcher support
579  */
580 #ifdef SUPPORT_VGA_SWITCHEROO
581 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
582 #else
583 #define use_vga_switcheroo(chip)        0
584 #endif
585
586 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
587 #define DELAYED_INIT_MARK
588 #define DELAYED_INITDATA_MARK
589 #else
590 #define DELAYED_INIT_MARK       __devinit
591 #define DELAYED_INITDATA_MARK   __devinitdata
592 #endif
593
594 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
595         [AZX_DRIVER_ICH] = "HDA Intel",
596         [AZX_DRIVER_PCH] = "HDA Intel PCH",
597         [AZX_DRIVER_SCH] = "HDA Intel MID",
598         [AZX_DRIVER_ATI] = "HDA ATI SB",
599         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
600         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
601         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
602         [AZX_DRIVER_SIS] = "HDA SIS966",
603         [AZX_DRIVER_ULI] = "HDA ULI M5461",
604         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
605         [AZX_DRIVER_TERA] = "HDA Teradici", 
606         [AZX_DRIVER_CTX] = "HDA Creative", 
607         [AZX_DRIVER_CTHDA] = "HDA Creative",
608         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
609 };
610
611 /*
612  * macros for easy use
613  */
614 #define azx_writel(chip,reg,value) \
615         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
616 #define azx_readl(chip,reg) \
617         readl((chip)->remap_addr + ICH6_REG_##reg)
618 #define azx_writew(chip,reg,value) \
619         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
620 #define azx_readw(chip,reg) \
621         readw((chip)->remap_addr + ICH6_REG_##reg)
622 #define azx_writeb(chip,reg,value) \
623         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
624 #define azx_readb(chip,reg) \
625         readb((chip)->remap_addr + ICH6_REG_##reg)
626
627 #define azx_sd_writel(dev,reg,value) \
628         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
629 #define azx_sd_readl(dev,reg) \
630         readl((dev)->sd_addr + ICH6_REG_##reg)
631 #define azx_sd_writew(dev,reg,value) \
632         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
633 #define azx_sd_readw(dev,reg) \
634         readw((dev)->sd_addr + ICH6_REG_##reg)
635 #define azx_sd_writeb(dev,reg,value) \
636         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
637 #define azx_sd_readb(dev,reg) \
638         readb((dev)->sd_addr + ICH6_REG_##reg)
639
640 /* for pcm support */
641 #define get_azx_dev(substream) (substream->runtime->private_data)
642
643 #ifdef CONFIG_X86
644 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
645 {
646         if (azx_snoop(chip))
647                 return;
648         if (addr && size) {
649                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
650                 if (on)
651                         set_memory_wc((unsigned long)addr, pages);
652                 else
653                         set_memory_wb((unsigned long)addr, pages);
654         }
655 }
656
657 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
658                                  bool on)
659 {
660         __mark_pages_wc(chip, buf->area, buf->bytes, on);
661 }
662 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
663                                    struct snd_pcm_runtime *runtime, bool on)
664 {
665         if (azx_dev->wc_marked != on) {
666                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
667                 azx_dev->wc_marked = on;
668         }
669 }
670 #else
671 /* NOP for other archs */
672 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
673                                  bool on)
674 {
675 }
676 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
677                                    struct snd_pcm_runtime *runtime, bool on)
678 {
679 }
680 #endif
681
682 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
683 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
684 /*
685  * Interface for HD codec
686  */
687
688 /*
689  * CORB / RIRB interface
690  */
691 static int azx_alloc_cmd_io(struct azx *chip)
692 {
693         int err;
694
695         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
696         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
697                                   snd_dma_pci_data(chip->pci),
698                                   PAGE_SIZE, &chip->rb);
699         if (err < 0) {
700                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
701                 return err;
702         }
703         mark_pages_wc(chip, &chip->rb, true);
704         return 0;
705 }
706
707 static void azx_init_cmd_io(struct azx *chip)
708 {
709         spin_lock_irq(&chip->reg_lock);
710         /* CORB set up */
711         chip->corb.addr = chip->rb.addr;
712         chip->corb.buf = (u32 *)chip->rb.area;
713         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
714         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
715
716         /* set the corb size to 256 entries (ULI requires explicitly) */
717         azx_writeb(chip, CORBSIZE, 0x02);
718         /* set the corb write pointer to 0 */
719         azx_writew(chip, CORBWP, 0);
720         /* reset the corb hw read pointer */
721         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
722         /* enable corb dma */
723         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
724
725         /* RIRB set up */
726         chip->rirb.addr = chip->rb.addr + 2048;
727         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
728         chip->rirb.wp = chip->rirb.rp = 0;
729         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
730         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
731         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
732
733         /* set the rirb size to 256 entries (ULI requires explicitly) */
734         azx_writeb(chip, RIRBSIZE, 0x02);
735         /* reset the rirb hw write pointer */
736         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
737         /* set N=1, get RIRB response interrupt for new entry */
738         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
739                 azx_writew(chip, RINTCNT, 0xc0);
740         else
741                 azx_writew(chip, RINTCNT, 1);
742         /* enable rirb dma and response irq */
743         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
744         spin_unlock_irq(&chip->reg_lock);
745 }
746
747 static void azx_free_cmd_io(struct azx *chip)
748 {
749         spin_lock_irq(&chip->reg_lock);
750         /* disable ringbuffer DMAs */
751         azx_writeb(chip, RIRBCTL, 0);
752         azx_writeb(chip, CORBCTL, 0);
753         spin_unlock_irq(&chip->reg_lock);
754 }
755
756 static unsigned int azx_command_addr(u32 cmd)
757 {
758         unsigned int addr = cmd >> 28;
759
760         if (addr >= AZX_MAX_CODECS) {
761                 snd_BUG();
762                 addr = 0;
763         }
764
765         return addr;
766 }
767
768 static unsigned int azx_response_addr(u32 res)
769 {
770         unsigned int addr = res & 0xf;
771
772         if (addr >= AZX_MAX_CODECS) {
773                 snd_BUG();
774                 addr = 0;
775         }
776
777         return addr;
778 }
779
780 /* send a command */
781 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
782 {
783         struct azx *chip = bus->private_data;
784         unsigned int addr = azx_command_addr(val);
785         unsigned int wp;
786
787         spin_lock_irq(&chip->reg_lock);
788
789         /* add command to corb */
790         wp = azx_readb(chip, CORBWP);
791         wp++;
792         wp %= ICH6_MAX_CORB_ENTRIES;
793
794         chip->rirb.cmds[addr]++;
795         chip->corb.buf[wp] = cpu_to_le32(val);
796         azx_writel(chip, CORBWP, wp);
797
798         spin_unlock_irq(&chip->reg_lock);
799
800         return 0;
801 }
802
803 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
804
805 /* retrieve RIRB entry - called from interrupt handler */
806 static void azx_update_rirb(struct azx *chip)
807 {
808         unsigned int rp, wp;
809         unsigned int addr;
810         u32 res, res_ex;
811
812         wp = azx_readb(chip, RIRBWP);
813         if (wp == chip->rirb.wp)
814                 return;
815         chip->rirb.wp = wp;
816
817         while (chip->rirb.rp != wp) {
818                 chip->rirb.rp++;
819                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
820
821                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
822                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
823                 res = le32_to_cpu(chip->rirb.buf[rp]);
824                 addr = azx_response_addr(res_ex);
825                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
826                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
827                 else if (chip->rirb.cmds[addr]) {
828                         chip->rirb.res[addr] = res;
829                         smp_wmb();
830                         chip->rirb.cmds[addr]--;
831                 } else
832                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
833                                    "last cmd=%#08x\n",
834                                    res, res_ex,
835                                    chip->last_cmd[addr]);
836         }
837 }
838
839 /* receive a response */
840 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
841                                           unsigned int addr)
842 {
843         struct azx *chip = bus->private_data;
844         unsigned long timeout;
845         unsigned long loopcounter;
846         int do_poll = 0;
847
848  again:
849         timeout = jiffies + msecs_to_jiffies(1000);
850
851         for (loopcounter = 0;; loopcounter++) {
852                 if (chip->polling_mode || do_poll) {
853                         spin_lock_irq(&chip->reg_lock);
854                         azx_update_rirb(chip);
855                         spin_unlock_irq(&chip->reg_lock);
856                 }
857                 if (!chip->rirb.cmds[addr]) {
858                         smp_rmb();
859                         bus->rirb_error = 0;
860
861                         if (!do_poll)
862                                 chip->poll_count = 0;
863                         return chip->rirb.res[addr]; /* the last value */
864                 }
865                 if (time_after(jiffies, timeout))
866                         break;
867                 if (bus->needs_damn_long_delay || loopcounter > 3000)
868                         msleep(2); /* temporary workaround */
869                 else {
870                         udelay(10);
871                         cond_resched();
872                 }
873         }
874
875         if (!chip->polling_mode && chip->poll_count < 2) {
876                 snd_printdd(SFX "azx_get_response timeout, "
877                            "polling the codec once: last cmd=0x%08x\n",
878                            chip->last_cmd[addr]);
879                 do_poll = 1;
880                 chip->poll_count++;
881                 goto again;
882         }
883
884
885         if (!chip->polling_mode) {
886                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
887                            "switching to polling mode: last cmd=0x%08x\n",
888                            chip->last_cmd[addr]);
889                 chip->polling_mode = 1;
890                 goto again;
891         }
892
893         if (chip->msi) {
894                 snd_printk(KERN_WARNING SFX "No response from codec, "
895                            "disabling MSI: last cmd=0x%08x\n",
896                            chip->last_cmd[addr]);
897                 free_irq(chip->irq, chip);
898                 chip->irq = -1;
899                 pci_disable_msi(chip->pci);
900                 chip->msi = 0;
901                 if (azx_acquire_irq(chip, 1) < 0) {
902                         bus->rirb_error = 1;
903                         return -1;
904                 }
905                 goto again;
906         }
907
908         if (chip->probing) {
909                 /* If this critical timeout happens during the codec probing
910                  * phase, this is likely an access to a non-existing codec
911                  * slot.  Better to return an error and reset the system.
912                  */
913                 return -1;
914         }
915
916         /* a fatal communication error; need either to reset or to fallback
917          * to the single_cmd mode
918          */
919         bus->rirb_error = 1;
920         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
921                 bus->response_reset = 1;
922                 return -1; /* give a chance to retry */
923         }
924
925         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
926                    "switching to single_cmd mode: last cmd=0x%08x\n",
927                    chip->last_cmd[addr]);
928         chip->single_cmd = 1;
929         bus->response_reset = 0;
930         /* release CORB/RIRB */
931         azx_free_cmd_io(chip);
932         /* disable unsolicited responses */
933         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
934         return -1;
935 }
936
937 /*
938  * Use the single immediate command instead of CORB/RIRB for simplicity
939  *
940  * Note: according to Intel, this is not preferred use.  The command was
941  *       intended for the BIOS only, and may get confused with unsolicited
942  *       responses.  So, we shouldn't use it for normal operation from the
943  *       driver.
944  *       I left the codes, however, for debugging/testing purposes.
945  */
946
947 /* receive a response */
948 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
949 {
950         int timeout = 50;
951
952         while (timeout--) {
953                 /* check IRV busy bit */
954                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
955                         /* reuse rirb.res as the response return value */
956                         chip->rirb.res[addr] = azx_readl(chip, IR);
957                         return 0;
958                 }
959                 udelay(1);
960         }
961         if (printk_ratelimit())
962                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
963                            azx_readw(chip, IRS));
964         chip->rirb.res[addr] = -1;
965         return -EIO;
966 }
967
968 /* send a command */
969 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
970 {
971         struct azx *chip = bus->private_data;
972         unsigned int addr = azx_command_addr(val);
973         int timeout = 50;
974
975         bus->rirb_error = 0;
976         while (timeout--) {
977                 /* check ICB busy bit */
978                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
979                         /* Clear IRV valid bit */
980                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
981                                    ICH6_IRS_VALID);
982                         azx_writel(chip, IC, val);
983                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
984                                    ICH6_IRS_BUSY);
985                         return azx_single_wait_for_response(chip, addr);
986                 }
987                 udelay(1);
988         }
989         if (printk_ratelimit())
990                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
991                            azx_readw(chip, IRS), val);
992         return -EIO;
993 }
994
995 /* receive a response */
996 static unsigned int azx_single_get_response(struct hda_bus *bus,
997                                             unsigned int addr)
998 {
999         struct azx *chip = bus->private_data;
1000         return chip->rirb.res[addr];
1001 }
1002
1003 /*
1004  * The below are the main callbacks from hda_codec.
1005  *
1006  * They are just the skeleton to call sub-callbacks according to the
1007  * current setting of chip->single_cmd.
1008  */
1009
1010 /* send a command */
1011 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1012 {
1013         struct azx *chip = bus->private_data;
1014
1015         if (chip->disabled)
1016                 return 0;
1017         chip->last_cmd[azx_command_addr(val)] = val;
1018         if (chip->single_cmd)
1019                 return azx_single_send_cmd(bus, val);
1020         else
1021                 return azx_corb_send_cmd(bus, val);
1022 }
1023
1024 /* get a response */
1025 static unsigned int azx_get_response(struct hda_bus *bus,
1026                                      unsigned int addr)
1027 {
1028         struct azx *chip = bus->private_data;
1029         if (chip->disabled)
1030                 return 0;
1031         if (chip->single_cmd)
1032                 return azx_single_get_response(bus, addr);
1033         else
1034                 return azx_rirb_get_response(bus, addr);
1035 }
1036
1037 #ifdef CONFIG_PM
1038 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1039 #endif
1040
1041 #ifdef CONFIG_SND_HDA_DSP_LOADER
1042 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1043                                 unsigned int byte_size,
1044                                 struct snd_dma_buffer *bufp);
1045 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1046 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1047                                  struct snd_dma_buffer *dmab);
1048 #endif
1049
1050 /* reset codec link */
1051 static int azx_reset(struct azx *chip, int full_reset)
1052 {
1053         int count;
1054
1055         if (!full_reset)
1056                 goto __skip;
1057
1058         /* clear STATESTS */
1059         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1060
1061         /* reset controller */
1062         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1063
1064         count = 50;
1065         while (azx_readb(chip, GCTL) && --count)
1066                 msleep(1);
1067
1068         /* delay for >= 100us for codec PLL to settle per spec
1069          * Rev 0.9 section 5.5.1
1070          */
1071         msleep(1);
1072
1073         /* Bring controller out of reset */
1074         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1075
1076         count = 50;
1077         while (!azx_readb(chip, GCTL) && --count)
1078                 msleep(1);
1079
1080         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1081         msleep(1);
1082
1083       __skip:
1084         /* check to see if controller is ready */
1085         if (!azx_readb(chip, GCTL)) {
1086                 snd_printd(SFX "azx_reset: controller not ready!\n");
1087                 return -EBUSY;
1088         }
1089
1090         /* Accept unsolicited responses */
1091         if (!chip->single_cmd)
1092                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1093                            ICH6_GCTL_UNSOL);
1094
1095         /* detect codecs */
1096         if (!chip->codec_mask) {
1097                 chip->codec_mask = azx_readw(chip, STATESTS);
1098                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1099         }
1100
1101         return 0;
1102 }
1103
1104
1105 /*
1106  * Lowlevel interface
1107  */  
1108
1109 /* enable interrupts */
1110 static void azx_int_enable(struct azx *chip)
1111 {
1112         /* enable controller CIE and GIE */
1113         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1114                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1115 }
1116
1117 /* disable interrupts */
1118 static void azx_int_disable(struct azx *chip)
1119 {
1120         int i;
1121
1122         /* disable interrupts in stream descriptor */
1123         for (i = 0; i < chip->num_streams; i++) {
1124                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1125                 azx_sd_writeb(azx_dev, SD_CTL,
1126                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1127         }
1128
1129         /* disable SIE for all streams */
1130         azx_writeb(chip, INTCTL, 0);
1131
1132         /* disable controller CIE and GIE */
1133         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1134                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1135 }
1136
1137 /* clear interrupts */
1138 static void azx_int_clear(struct azx *chip)
1139 {
1140         int i;
1141
1142         /* clear stream status */
1143         for (i = 0; i < chip->num_streams; i++) {
1144                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1145                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1146         }
1147
1148         /* clear STATESTS */
1149         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1150
1151         /* clear rirb status */
1152         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1153
1154         /* clear int status */
1155         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1156 }
1157
1158 /* start a stream */
1159 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1160 {
1161         /*
1162          * Before stream start, initialize parameter
1163          */
1164         azx_dev->insufficient = 1;
1165
1166         /* enable SIE */
1167         azx_writel(chip, INTCTL,
1168                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1169         /* set DMA start and interrupt mask */
1170         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1171                       SD_CTL_DMA_START | SD_INT_MASK);
1172 }
1173
1174 /* stop DMA */
1175 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1176 {
1177         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1178                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1179         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1180 }
1181
1182 /* stop a stream */
1183 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1184 {
1185         azx_stream_clear(chip, azx_dev);
1186         /* disable SIE */
1187         azx_writel(chip, INTCTL,
1188                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1189 }
1190
1191
1192 /*
1193  * reset and start the controller registers
1194  */
1195 static void azx_init_chip(struct azx *chip, int full_reset)
1196 {
1197         if (chip->initialized)
1198                 return;
1199
1200         /* reset controller */
1201         azx_reset(chip, full_reset);
1202
1203         /* initialize interrupts */
1204         azx_int_clear(chip);
1205         azx_int_enable(chip);
1206
1207         /* initialize the codec command I/O */
1208         if (!chip->single_cmd)
1209                 azx_init_cmd_io(chip);
1210
1211         /* program the position buffer */
1212         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1213         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1214
1215         chip->initialized = 1;
1216 }
1217
1218 /*
1219  * initialize the PCI registers
1220  */
1221 /* update bits in a PCI register byte */
1222 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1223                             unsigned char mask, unsigned char val)
1224 {
1225         unsigned char data;
1226
1227         pci_read_config_byte(pci, reg, &data);
1228         data &= ~mask;
1229         data |= (val & mask);
1230         pci_write_config_byte(pci, reg, data);
1231 }
1232
1233 static void azx_init_pci(struct azx *chip)
1234 {
1235         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1236          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1237          * Ensuring these bits are 0 clears playback static on some HD Audio
1238          * codecs.
1239          * The PCI register TCSEL is defined in the Intel manuals.
1240          */
1241         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1242                 snd_printdd(SFX "Clearing TCSEL\n");
1243                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1244         }
1245
1246         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1247          * we need to enable snoop.
1248          */
1249         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1250                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1251                 update_pci_byte(chip->pci,
1252                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1253                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1254         }
1255
1256         /* For NVIDIA HDA, enable snoop */
1257         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1258                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1259                 update_pci_byte(chip->pci,
1260                                 NVIDIA_HDA_TRANSREG_ADDR,
1261                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1262                 update_pci_byte(chip->pci,
1263                                 NVIDIA_HDA_ISTRM_COH,
1264                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1265                 update_pci_byte(chip->pci,
1266                                 NVIDIA_HDA_OSTRM_COH,
1267                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1268         }
1269
1270         /* Enable SCH/PCH snoop if needed */
1271         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1272                 unsigned short snoop;
1273                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1274                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1275                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1276                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1277                         if (!azx_snoop(chip))
1278                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1279                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1280                         pci_read_config_word(chip->pci,
1281                                 INTEL_SCH_HDA_DEVC, &snoop);
1282                 }
1283                 snd_printdd(SFX "SCH snoop: %s\n",
1284                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1285                                 ? "Disabled" : "Enabled");
1286         }
1287 }
1288
1289
1290 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1291
1292 /*
1293  * interrupt handler
1294  */
1295 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1296 {
1297         struct azx *chip = dev_id;
1298         struct azx_dev *azx_dev;
1299         u32 status;
1300         u8 sd_status;
1301         int i, ok;
1302
1303 #ifdef CONFIG_PM_RUNTIME
1304         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1305                 return IRQ_NONE;
1306 #endif
1307
1308         spin_lock(&chip->reg_lock);
1309
1310         if (chip->disabled) {
1311                 spin_unlock(&chip->reg_lock);
1312                 return IRQ_NONE;
1313         }
1314
1315         status = azx_readl(chip, INTSTS);
1316         if (status == 0) {
1317                 spin_unlock(&chip->reg_lock);
1318                 return IRQ_NONE;
1319         }
1320         
1321         for (i = 0; i < chip->num_streams; i++) {
1322                 azx_dev = &chip->azx_dev[i];
1323                 if (status & azx_dev->sd_int_sta_mask) {
1324                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1325                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1326                         if (!azx_dev->substream || !azx_dev->running ||
1327                             !(sd_status & SD_INT_COMPLETE))
1328                                 continue;
1329                         /* check whether this IRQ is really acceptable */
1330                         ok = azx_position_ok(chip, azx_dev);
1331                         if (ok == 1) {
1332                                 azx_dev->irq_pending = 0;
1333                                 spin_unlock(&chip->reg_lock);
1334                                 snd_pcm_period_elapsed(azx_dev->substream);
1335                                 spin_lock(&chip->reg_lock);
1336                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1337                                 /* bogus IRQ, process it later */
1338                                 azx_dev->irq_pending = 1;
1339                                 queue_work(chip->bus->workq,
1340                                            &chip->irq_pending_work);
1341                         }
1342                 }
1343         }
1344
1345         /* clear rirb int */
1346         status = azx_readb(chip, RIRBSTS);
1347         if (status & RIRB_INT_MASK) {
1348                 if (status & RIRB_INT_RESPONSE) {
1349                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1350                                 udelay(80);
1351                         azx_update_rirb(chip);
1352                 }
1353                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1354         }
1355
1356 #if 0
1357         /* clear state status int */
1358         if (azx_readb(chip, STATESTS) & 0x04)
1359                 azx_writeb(chip, STATESTS, 0x04);
1360 #endif
1361         spin_unlock(&chip->reg_lock);
1362         
1363         return IRQ_HANDLED;
1364 }
1365
1366
1367 /*
1368  * set up a BDL entry
1369  */
1370 static int setup_bdle(struct azx *chip,
1371                       struct snd_dma_buffer *dmab,
1372                       struct azx_dev *azx_dev, u32 **bdlp,
1373                       int ofs, int size, int with_ioc)
1374 {
1375         u32 *bdl = *bdlp;
1376
1377         while (size > 0) {
1378                 dma_addr_t addr;
1379                 int chunk;
1380
1381                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1382                         return -EINVAL;
1383
1384                 addr = snd_sgbuf_get_addr(dmab, ofs);
1385                 /* program the address field of the BDL entry */
1386                 bdl[0] = cpu_to_le32((u32)addr);
1387                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1388                 /* program the size field of the BDL entry */
1389                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1390                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1391                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1392                         u32 remain = 0x1000 - (ofs & 0xfff);
1393                         if (chunk > remain)
1394                                 chunk = remain;
1395                 }
1396                 bdl[2] = cpu_to_le32(chunk);
1397                 /* program the IOC to enable interrupt
1398                  * only when the whole fragment is processed
1399                  */
1400                 size -= chunk;
1401                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1402                 bdl += 4;
1403                 azx_dev->frags++;
1404                 ofs += chunk;
1405         }
1406         *bdlp = bdl;
1407         return ofs;
1408 }
1409
1410 /*
1411  * set up BDL entries
1412  */
1413 static int azx_setup_periods(struct azx *chip,
1414                              struct snd_pcm_substream *substream,
1415                              struct azx_dev *azx_dev)
1416 {
1417         u32 *bdl;
1418         int i, ofs, periods, period_bytes;
1419         int pos_adj;
1420
1421         /* reset BDL address */
1422         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1423         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1424
1425         period_bytes = azx_dev->period_bytes;
1426         periods = azx_dev->bufsize / period_bytes;
1427
1428         /* program the initial BDL entries */
1429         bdl = (u32 *)azx_dev->bdl.area;
1430         ofs = 0;
1431         azx_dev->frags = 0;
1432         pos_adj = bdl_pos_adj[chip->dev_index];
1433         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1434                 struct snd_pcm_runtime *runtime = substream->runtime;
1435                 int pos_align = pos_adj;
1436                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1437                 if (!pos_adj)
1438                         pos_adj = pos_align;
1439                 else
1440                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1441                                 pos_align;
1442                 pos_adj = frames_to_bytes(runtime, pos_adj);
1443                 if (pos_adj >= period_bytes) {
1444                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1445                                    bdl_pos_adj[chip->dev_index]);
1446                         pos_adj = 0;
1447                 } else {
1448                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1449                                          azx_dev,
1450                                          &bdl, ofs, pos_adj, true);
1451                         if (ofs < 0)
1452                                 goto error;
1453                 }
1454         } else
1455                 pos_adj = 0;
1456         for (i = 0; i < periods; i++) {
1457                 if (i == periods - 1 && pos_adj)
1458                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1459                                          azx_dev, &bdl, ofs,
1460                                          period_bytes - pos_adj, 0);
1461                 else
1462                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1463                                          azx_dev, &bdl, ofs,
1464                                          period_bytes,
1465                                          !azx_dev->no_period_wakeup);
1466                 if (ofs < 0)
1467                         goto error;
1468         }
1469         return 0;
1470
1471  error:
1472         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1473                    azx_dev->bufsize, period_bytes);
1474         return -EINVAL;
1475 }
1476
1477 /* reset stream */
1478 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1479 {
1480         unsigned char val;
1481         int timeout;
1482
1483         azx_stream_clear(chip, azx_dev);
1484
1485         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1486                       SD_CTL_STREAM_RESET);
1487         udelay(3);
1488         timeout = 300;
1489         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1490                --timeout)
1491                 ;
1492         val &= ~SD_CTL_STREAM_RESET;
1493         azx_sd_writeb(azx_dev, SD_CTL, val);
1494         udelay(3);
1495
1496         timeout = 300;
1497         /* waiting for hardware to report that the stream is out of reset */
1498         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1499                --timeout)
1500                 ;
1501
1502         /* reset first position - may not be synced with hw at this time */
1503         *azx_dev->posbuf = 0;
1504 }
1505
1506 /*
1507  * set up the SD for streaming
1508  */
1509 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1510 {
1511         unsigned int val;
1512         /* make sure the run bit is zero for SD */
1513         azx_stream_clear(chip, azx_dev);
1514         /* program the stream_tag */
1515         val = azx_sd_readl(azx_dev, SD_CTL);
1516         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1517                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1518         if (!azx_snoop(chip))
1519                 val |= SD_CTL_TRAFFIC_PRIO;
1520         azx_sd_writel(azx_dev, SD_CTL, val);
1521
1522         /* program the length of samples in cyclic buffer */
1523         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1524
1525         /* program the stream format */
1526         /* this value needs to be the same as the one programmed */
1527         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1528
1529         /* program the stream LVI (last valid index) of the BDL */
1530         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1531
1532         /* program the BDL address */
1533         /* lower BDL address */
1534         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1535         /* upper BDL address */
1536         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1537
1538         /* enable the position buffer */
1539         if (chip->position_fix[0] != POS_FIX_LPIB ||
1540             chip->position_fix[1] != POS_FIX_LPIB) {
1541                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1542                         azx_writel(chip, DPLBASE,
1543                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1544         }
1545
1546         /* set the interrupt enable bits in the descriptor control register */
1547         azx_sd_writel(azx_dev, SD_CTL,
1548                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1549
1550         return 0;
1551 }
1552
1553 /*
1554  * Probe the given codec address
1555  */
1556 static int probe_codec(struct azx *chip, int addr)
1557 {
1558         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1559                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1560         unsigned int res;
1561
1562         mutex_lock(&chip->bus->cmd_mutex);
1563         chip->probing = 1;
1564         azx_send_cmd(chip->bus, cmd);
1565         res = azx_get_response(chip->bus, addr);
1566         chip->probing = 0;
1567         mutex_unlock(&chip->bus->cmd_mutex);
1568         if (res == -1)
1569                 return -EIO;
1570         snd_printdd(SFX "codec #%d probed OK\n", addr);
1571         return 0;
1572 }
1573
1574 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1575                                  struct hda_pcm *cpcm);
1576 static void azx_stop_chip(struct azx *chip);
1577
1578 static void azx_bus_reset(struct hda_bus *bus)
1579 {
1580         struct azx *chip = bus->private_data;
1581
1582         bus->in_reset = 1;
1583         azx_stop_chip(chip);
1584         azx_init_chip(chip, 1);
1585 #ifdef CONFIG_PM
1586         if (chip->initialized) {
1587                 struct azx_pcm *p;
1588                 list_for_each_entry(p, &chip->pcm_list, list)
1589                         snd_pcm_suspend_all(p->pcm);
1590                 snd_hda_suspend(chip->bus);
1591                 snd_hda_resume(chip->bus);
1592         }
1593 #endif
1594         bus->in_reset = 0;
1595 }
1596
1597 /*
1598  * Codec initialization
1599  */
1600
1601 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1602 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1603         [AZX_DRIVER_NVIDIA] = 8,
1604         [AZX_DRIVER_TERA] = 1,
1605 };
1606
1607 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1608 {
1609         struct hda_bus_template bus_temp;
1610         int c, codecs, err;
1611         int max_slots;
1612
1613         memset(&bus_temp, 0, sizeof(bus_temp));
1614         bus_temp.private_data = chip;
1615         bus_temp.modelname = model;
1616         bus_temp.pci = chip->pci;
1617         bus_temp.ops.command = azx_send_cmd;
1618         bus_temp.ops.get_response = azx_get_response;
1619         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1620         bus_temp.ops.bus_reset = azx_bus_reset;
1621 #ifdef CONFIG_PM
1622         bus_temp.power_save = &power_save;
1623         bus_temp.ops.pm_notify = azx_power_notify;
1624 #endif
1625 #ifdef CONFIG_SND_HDA_DSP_LOADER
1626         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1627         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1628         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1629 #endif
1630
1631         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1632         if (err < 0)
1633                 return err;
1634
1635         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1636                 snd_printd(SFX "Enable delay in RIRB handling\n");
1637                 chip->bus->needs_damn_long_delay = 1;
1638         }
1639
1640         codecs = 0;
1641         max_slots = azx_max_codecs[chip->driver_type];
1642         if (!max_slots)
1643                 max_slots = AZX_DEFAULT_CODECS;
1644
1645         /* First try to probe all given codec slots */
1646         for (c = 0; c < max_slots; c++) {
1647                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1648                         if (probe_codec(chip, c) < 0) {
1649                                 /* Some BIOSen give you wrong codec addresses
1650                                  * that don't exist
1651                                  */
1652                                 snd_printk(KERN_WARNING SFX
1653                                            "Codec #%d probe error; "
1654                                            "disabling it...\n", c);
1655                                 chip->codec_mask &= ~(1 << c);
1656                                 /* More badly, accessing to a non-existing
1657                                  * codec often screws up the controller chip,
1658                                  * and disturbs the further communications.
1659                                  * Thus if an error occurs during probing,
1660                                  * better to reset the controller chip to
1661                                  * get back to the sanity state.
1662                                  */
1663                                 azx_stop_chip(chip);
1664                                 azx_init_chip(chip, 1);
1665                         }
1666                 }
1667         }
1668
1669         /* AMD chipsets often cause the communication stalls upon certain
1670          * sequence like the pin-detection.  It seems that forcing the synced
1671          * access works around the stall.  Grrr...
1672          */
1673         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1674                 snd_printd(SFX "Enable sync_write for stable communication\n");
1675                 chip->bus->sync_write = 1;
1676                 chip->bus->allow_bus_reset = 1;
1677         }
1678
1679         /* Then create codec instances */
1680         for (c = 0; c < max_slots; c++) {
1681                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1682                         struct hda_codec *codec;
1683                         err = snd_hda_codec_new(chip->bus, c, &codec);
1684                         if (err < 0)
1685                                 continue;
1686                         codec->beep_mode = chip->beep_mode;
1687                         codecs++;
1688                 }
1689         }
1690         if (!codecs) {
1691                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1692                 return -ENXIO;
1693         }
1694         return 0;
1695 }
1696
1697 /* configure each codec instance */
1698 static int __devinit azx_codec_configure(struct azx *chip)
1699 {
1700         struct hda_codec *codec;
1701         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1702                 snd_hda_codec_configure(codec);
1703         }
1704         return 0;
1705 }
1706
1707
1708 /*
1709  * PCM support
1710  */
1711
1712 /* assign a stream for the PCM */
1713 static inline struct azx_dev *
1714 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1715 {
1716         int dev, i, nums;
1717         struct azx_dev *res = NULL;
1718         /* make a non-zero unique key for the substream */
1719         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1720                 (substream->stream + 1);
1721
1722         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1723                 dev = chip->playback_index_offset;
1724                 nums = chip->playback_streams;
1725         } else {
1726                 dev = chip->capture_index_offset;
1727                 nums = chip->capture_streams;
1728         }
1729         for (i = 0; i < nums; i++, dev++)
1730                 if (!chip->azx_dev[dev].opened) {
1731                         res = &chip->azx_dev[dev];
1732                         if (res->assigned_key == key)
1733                                 break;
1734                 }
1735         if (res) {
1736                 res->opened = 1;
1737                 res->assigned_key = key;
1738         }
1739         return res;
1740 }
1741
1742 /* release the assigned stream */
1743 static inline void azx_release_device(struct azx_dev *azx_dev)
1744 {
1745         azx_dev->opened = 0;
1746 }
1747
1748 static struct snd_pcm_hardware azx_pcm_hw = {
1749         .info =                 (SNDRV_PCM_INFO_MMAP |
1750                                  SNDRV_PCM_INFO_INTERLEAVED |
1751                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1752                                  SNDRV_PCM_INFO_MMAP_VALID |
1753                                  /* No full-resume yet implemented */
1754                                  /* SNDRV_PCM_INFO_RESUME |*/
1755                                  SNDRV_PCM_INFO_PAUSE |
1756                                  SNDRV_PCM_INFO_SYNC_START |
1757                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1758         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1759         .rates =                SNDRV_PCM_RATE_48000,
1760         .rate_min =             48000,
1761         .rate_max =             48000,
1762         .channels_min =         2,
1763         .channels_max =         2,
1764         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1765         .period_bytes_min =     128,
1766         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1767         .periods_min =          2,
1768         .periods_max =          AZX_MAX_FRAG,
1769         .fifo_size =            0,
1770 };
1771
1772 static int azx_pcm_open(struct snd_pcm_substream *substream)
1773 {
1774         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1775         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1776         struct azx *chip = apcm->chip;
1777         struct azx_dev *azx_dev;
1778         struct snd_pcm_runtime *runtime = substream->runtime;
1779         unsigned long flags;
1780         int err;
1781         int buff_step;
1782
1783         mutex_lock(&chip->open_mutex);
1784         azx_dev = azx_assign_device(chip, substream);
1785         if (azx_dev == NULL) {
1786                 mutex_unlock(&chip->open_mutex);
1787                 return -EBUSY;
1788         }
1789         runtime->hw = azx_pcm_hw;
1790         runtime->hw.channels_min = hinfo->channels_min;
1791         runtime->hw.channels_max = hinfo->channels_max;
1792         runtime->hw.formats = hinfo->formats;
1793         runtime->hw.rates = hinfo->rates;
1794         snd_pcm_limit_hw_rates(runtime);
1795         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1796         if (chip->align_buffer_size)
1797                 /* constrain buffer sizes to be multiple of 128
1798                    bytes. This is more efficient in terms of memory
1799                    access but isn't required by the HDA spec and
1800                    prevents users from specifying exact period/buffer
1801                    sizes. For example for 44.1kHz, a period size set
1802                    to 20ms will be rounded to 19.59ms. */
1803                 buff_step = 128;
1804         else
1805                 /* Don't enforce steps on buffer sizes, still need to
1806                    be multiple of 4 bytes (HDA spec). Tested on Intel
1807                    HDA controllers, may not work on all devices where
1808                    option needs to be disabled */
1809                 buff_step = 4;
1810
1811         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1812                                    buff_step);
1813         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1814                                    buff_step);
1815         snd_hda_power_up_d3wait(apcm->codec);
1816         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1817         if (err < 0) {
1818                 azx_release_device(azx_dev);
1819                 snd_hda_power_down(apcm->codec);
1820                 mutex_unlock(&chip->open_mutex);
1821                 return err;
1822         }
1823         snd_pcm_limit_hw_rates(runtime);
1824         /* sanity check */
1825         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1826             snd_BUG_ON(!runtime->hw.channels_max) ||
1827             snd_BUG_ON(!runtime->hw.formats) ||
1828             snd_BUG_ON(!runtime->hw.rates)) {
1829                 azx_release_device(azx_dev);
1830                 hinfo->ops.close(hinfo, apcm->codec, substream);
1831                 snd_hda_power_down(apcm->codec);
1832                 mutex_unlock(&chip->open_mutex);
1833                 return -EINVAL;
1834         }
1835         spin_lock_irqsave(&chip->reg_lock, flags);
1836         azx_dev->substream = substream;
1837         azx_dev->running = 0;
1838         spin_unlock_irqrestore(&chip->reg_lock, flags);
1839
1840         runtime->private_data = azx_dev;
1841         snd_pcm_set_sync(substream);
1842         mutex_unlock(&chip->open_mutex);
1843         return 0;
1844 }
1845
1846 static int azx_pcm_close(struct snd_pcm_substream *substream)
1847 {
1848         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1849         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1850         struct azx *chip = apcm->chip;
1851         struct azx_dev *azx_dev = get_azx_dev(substream);
1852         unsigned long flags;
1853
1854         mutex_lock(&chip->open_mutex);
1855         spin_lock_irqsave(&chip->reg_lock, flags);
1856         azx_dev->substream = NULL;
1857         azx_dev->running = 0;
1858         spin_unlock_irqrestore(&chip->reg_lock, flags);
1859         azx_release_device(azx_dev);
1860         hinfo->ops.close(hinfo, apcm->codec, substream);
1861         snd_hda_power_down(apcm->codec);
1862         mutex_unlock(&chip->open_mutex);
1863         return 0;
1864 }
1865
1866 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1867                              struct snd_pcm_hw_params *hw_params)
1868 {
1869         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1870         struct azx *chip = apcm->chip;
1871         struct snd_pcm_runtime *runtime = substream->runtime;
1872         struct azx_dev *azx_dev = get_azx_dev(substream);
1873         int ret;
1874
1875         mark_runtime_wc(chip, azx_dev, runtime, false);
1876         azx_dev->bufsize = 0;
1877         azx_dev->period_bytes = 0;
1878         azx_dev->format_val = 0;
1879         ret = snd_pcm_lib_malloc_pages(substream,
1880                                         params_buffer_bytes(hw_params));
1881         if (ret < 0)
1882                 return ret;
1883         mark_runtime_wc(chip, azx_dev, runtime, true);
1884         return ret;
1885 }
1886
1887 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1888 {
1889         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1890         struct azx_dev *azx_dev = get_azx_dev(substream);
1891         struct azx *chip = apcm->chip;
1892         struct snd_pcm_runtime *runtime = substream->runtime;
1893         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1894
1895         /* reset BDL address */
1896         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1897         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1898         azx_sd_writel(azx_dev, SD_CTL, 0);
1899         azx_dev->bufsize = 0;
1900         azx_dev->period_bytes = 0;
1901         azx_dev->format_val = 0;
1902
1903         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1904
1905         mark_runtime_wc(chip, azx_dev, runtime, false);
1906         return snd_pcm_lib_free_pages(substream);
1907 }
1908
1909 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1910 {
1911         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1912         struct azx *chip = apcm->chip;
1913         struct azx_dev *azx_dev = get_azx_dev(substream);
1914         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1915         struct snd_pcm_runtime *runtime = substream->runtime;
1916         unsigned int bufsize, period_bytes, format_val, stream_tag;
1917         int err;
1918         struct hda_spdif_out *spdif =
1919                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1920         unsigned short ctls = spdif ? spdif->ctls : 0;
1921
1922         azx_stream_reset(chip, azx_dev);
1923         format_val = snd_hda_calc_stream_format(runtime->rate,
1924                                                 runtime->channels,
1925                                                 runtime->format,
1926                                                 hinfo->maxbps,
1927                                                 ctls);
1928         if (!format_val) {
1929                 snd_printk(KERN_ERR SFX
1930                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1931                            runtime->rate, runtime->channels, runtime->format);
1932                 return -EINVAL;
1933         }
1934
1935         bufsize = snd_pcm_lib_buffer_bytes(substream);
1936         period_bytes = snd_pcm_lib_period_bytes(substream);
1937
1938         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1939                     bufsize, format_val);
1940
1941         if (bufsize != azx_dev->bufsize ||
1942             period_bytes != azx_dev->period_bytes ||
1943             format_val != azx_dev->format_val ||
1944             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
1945                 azx_dev->bufsize = bufsize;
1946                 azx_dev->period_bytes = period_bytes;
1947                 azx_dev->format_val = format_val;
1948                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
1949                 err = azx_setup_periods(chip, substream, azx_dev);
1950                 if (err < 0)
1951                         return err;
1952         }
1953
1954         /* wallclk has 24Mhz clock source */
1955         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1956                                                 runtime->rate) * 1000);
1957         azx_setup_controller(chip, azx_dev);
1958         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1959                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1960         else
1961                 azx_dev->fifo_size = 0;
1962
1963         stream_tag = azx_dev->stream_tag;
1964         /* CA-IBG chips need the playback stream starting from 1 */
1965         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1966             stream_tag > chip->capture_streams)
1967                 stream_tag -= chip->capture_streams;
1968         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1969                                      azx_dev->format_val, substream);
1970 }
1971
1972 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1973 {
1974         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1975         struct azx *chip = apcm->chip;
1976         struct azx_dev *azx_dev;
1977         struct snd_pcm_substream *s;
1978         int rstart = 0, start, nsync = 0, sbits = 0;
1979         int nwait, timeout;
1980
1981         switch (cmd) {
1982         case SNDRV_PCM_TRIGGER_START:
1983                 rstart = 1;
1984         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1985         case SNDRV_PCM_TRIGGER_RESUME:
1986                 start = 1;
1987                 break;
1988         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1989         case SNDRV_PCM_TRIGGER_SUSPEND:
1990         case SNDRV_PCM_TRIGGER_STOP:
1991                 start = 0;
1992                 break;
1993         default:
1994                 return -EINVAL;
1995         }
1996
1997         snd_pcm_group_for_each_entry(s, substream) {
1998                 if (s->pcm->card != substream->pcm->card)
1999                         continue;
2000                 azx_dev = get_azx_dev(s);
2001                 sbits |= 1 << azx_dev->index;
2002                 nsync++;
2003                 snd_pcm_trigger_done(s, substream);
2004         }
2005
2006         spin_lock(&chip->reg_lock);
2007
2008         /* first, set SYNC bits of corresponding streams */
2009         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2010                 azx_writel(chip, OLD_SSYNC,
2011                         azx_readl(chip, OLD_SSYNC) | sbits);
2012         else
2013                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2014
2015         snd_pcm_group_for_each_entry(s, substream) {
2016                 if (s->pcm->card != substream->pcm->card)
2017                         continue;
2018                 azx_dev = get_azx_dev(s);
2019                 if (start) {
2020                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2021                         if (!rstart)
2022                                 azx_dev->start_wallclk -=
2023                                                 azx_dev->period_wallclk;
2024                         azx_stream_start(chip, azx_dev);
2025                 } else {
2026                         azx_stream_stop(chip, azx_dev);
2027                 }
2028                 azx_dev->running = start;
2029         }
2030         spin_unlock(&chip->reg_lock);
2031         if (start) {
2032                 /* wait until all FIFOs get ready */
2033                 for (timeout = 5000; timeout; timeout--) {
2034                         nwait = 0;
2035                         snd_pcm_group_for_each_entry(s, substream) {
2036                                 if (s->pcm->card != substream->pcm->card)
2037                                         continue;
2038                                 azx_dev = get_azx_dev(s);
2039                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2040                                       SD_STS_FIFO_READY))
2041                                         nwait++;
2042                         }
2043                         if (!nwait)
2044                                 break;
2045                         cpu_relax();
2046                 }
2047         } else {
2048                 /* wait until all RUN bits are cleared */
2049                 for (timeout = 5000; timeout; timeout--) {
2050                         nwait = 0;
2051                         snd_pcm_group_for_each_entry(s, substream) {
2052                                 if (s->pcm->card != substream->pcm->card)
2053                                         continue;
2054                                 azx_dev = get_azx_dev(s);
2055                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2056                                     SD_CTL_DMA_START)
2057                                         nwait++;
2058                         }
2059                         if (!nwait)
2060                                 break;
2061                         cpu_relax();
2062                 }
2063         }
2064         spin_lock(&chip->reg_lock);
2065         /* reset SYNC bits */
2066         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2067                 azx_writel(chip, OLD_SSYNC,
2068                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2069         else
2070                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2071         spin_unlock(&chip->reg_lock);
2072         return 0;
2073 }
2074
2075 /* get the current DMA position with correction on VIA chips */
2076 static unsigned int azx_via_get_position(struct azx *chip,
2077                                          struct azx_dev *azx_dev)
2078 {
2079         unsigned int link_pos, mini_pos, bound_pos;
2080         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2081         unsigned int fifo_size;
2082
2083         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2084         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2085                 /* Playback, no problem using link position */
2086                 return link_pos;
2087         }
2088
2089         /* Capture */
2090         /* For new chipset,
2091          * use mod to get the DMA position just like old chipset
2092          */
2093         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2094         mod_dma_pos %= azx_dev->period_bytes;
2095
2096         /* azx_dev->fifo_size can't get FIFO size of in stream.
2097          * Get from base address + offset.
2098          */
2099         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2100
2101         if (azx_dev->insufficient) {
2102                 /* Link position never gather than FIFO size */
2103                 if (link_pos <= fifo_size)
2104                         return 0;
2105
2106                 azx_dev->insufficient = 0;
2107         }
2108
2109         if (link_pos <= fifo_size)
2110                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2111         else
2112                 mini_pos = link_pos - fifo_size;
2113
2114         /* Find nearest previous boudary */
2115         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2116         mod_link_pos = link_pos % azx_dev->period_bytes;
2117         if (mod_link_pos >= fifo_size)
2118                 bound_pos = link_pos - mod_link_pos;
2119         else if (mod_dma_pos >= mod_mini_pos)
2120                 bound_pos = mini_pos - mod_mini_pos;
2121         else {
2122                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2123                 if (bound_pos >= azx_dev->bufsize)
2124                         bound_pos = 0;
2125         }
2126
2127         /* Calculate real DMA position we want */
2128         return bound_pos + mod_dma_pos;
2129 }
2130
2131 static unsigned int azx_get_position(struct azx *chip,
2132                                      struct azx_dev *azx_dev,
2133                                      bool with_check)
2134 {
2135         unsigned int pos;
2136         int stream = azx_dev->substream->stream;
2137
2138         switch (chip->position_fix[stream]) {
2139         case POS_FIX_LPIB:
2140                 /* read LPIB */
2141                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2142                 break;
2143         case POS_FIX_VIACOMBO:
2144                 pos = azx_via_get_position(chip, azx_dev);
2145                 break;
2146         default:
2147                 /* use the position buffer */
2148                 pos = le32_to_cpu(*azx_dev->posbuf);
2149                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2150                         if (!pos || pos == (u32)-1) {
2151                                 printk(KERN_WARNING
2152                                        "hda-intel: Invalid position buffer, "
2153                                        "using LPIB read method instead.\n");
2154                                 chip->position_fix[stream] = POS_FIX_LPIB;
2155                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2156                         } else
2157                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2158                 }
2159                 break;
2160         }
2161
2162         if (pos >= azx_dev->bufsize)
2163                 pos = 0;
2164
2165         /* calculate runtime delay from LPIB */
2166         if (azx_dev->substream->runtime &&
2167             chip->position_fix[stream] == POS_FIX_POSBUF &&
2168             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2169                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2170                 int delay;
2171                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2172                         delay = pos - lpib_pos;
2173                 else
2174                         delay = lpib_pos - pos;
2175                 if (delay < 0)
2176                         delay += azx_dev->bufsize;
2177                 if (delay >= azx_dev->period_bytes) {
2178                         snd_printk(KERN_WARNING SFX
2179                                    "Unstable LPIB (%d >= %d); "
2180                                    "disabling LPIB delay counting\n",
2181                                    delay, azx_dev->period_bytes);
2182                         delay = 0;
2183                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2184                 }
2185                 azx_dev->substream->runtime->delay =
2186                         bytes_to_frames(azx_dev->substream->runtime, delay);
2187         }
2188         return pos;
2189 }
2190
2191 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2192 {
2193         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2194         struct azx *chip = apcm->chip;
2195         struct azx_dev *azx_dev = get_azx_dev(substream);
2196         return bytes_to_frames(substream->runtime,
2197                                azx_get_position(chip, azx_dev, false));
2198 }
2199
2200 /*
2201  * Check whether the current DMA position is acceptable for updating
2202  * periods.  Returns non-zero if it's OK.
2203  *
2204  * Many HD-audio controllers appear pretty inaccurate about
2205  * the update-IRQ timing.  The IRQ is issued before actually the
2206  * data is processed.  So, we need to process it afterwords in a
2207  * workqueue.
2208  */
2209 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2210 {
2211         u32 wallclk;
2212         unsigned int pos;
2213         int stream;
2214
2215         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2216         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2217                 return -1;      /* bogus (too early) interrupt */
2218
2219         stream = azx_dev->substream->stream;
2220         pos = azx_get_position(chip, azx_dev, true);
2221
2222         if (WARN_ONCE(!azx_dev->period_bytes,
2223                       "hda-intel: zero azx_dev->period_bytes"))
2224                 return -1; /* this shouldn't happen! */
2225         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2226             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2227                 /* NG - it's below the first next period boundary */
2228                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2229         azx_dev->start_wallclk += wallclk;
2230         return 1; /* OK, it's fine */
2231 }
2232
2233 /*
2234  * The work for pending PCM period updates.
2235  */
2236 static void azx_irq_pending_work(struct work_struct *work)
2237 {
2238         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2239         int i, pending, ok;
2240
2241         if (!chip->irq_pending_warned) {
2242                 printk(KERN_WARNING
2243                        "hda-intel: IRQ timing workaround is activated "
2244                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2245                        chip->card->number);
2246                 chip->irq_pending_warned = 1;
2247         }
2248
2249         for (;;) {
2250                 pending = 0;
2251                 spin_lock_irq(&chip->reg_lock);
2252                 for (i = 0; i < chip->num_streams; i++) {
2253                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2254                         if (!azx_dev->irq_pending ||
2255                             !azx_dev->substream ||
2256                             !azx_dev->running)
2257                                 continue;
2258                         ok = azx_position_ok(chip, azx_dev);
2259                         if (ok > 0) {
2260                                 azx_dev->irq_pending = 0;
2261                                 spin_unlock(&chip->reg_lock);
2262                                 snd_pcm_period_elapsed(azx_dev->substream);
2263                                 spin_lock(&chip->reg_lock);
2264                         } else if (ok < 0) {
2265                                 pending = 0;    /* too early */
2266                         } else
2267                                 pending++;
2268                 }
2269                 spin_unlock_irq(&chip->reg_lock);
2270                 if (!pending)
2271                         return;
2272                 msleep(1);
2273         }
2274 }
2275
2276 /* clear irq_pending flags and assure no on-going workq */
2277 static void azx_clear_irq_pending(struct azx *chip)
2278 {
2279         int i;
2280
2281         spin_lock_irq(&chip->reg_lock);
2282         for (i = 0; i < chip->num_streams; i++)
2283                 chip->azx_dev[i].irq_pending = 0;
2284         spin_unlock_irq(&chip->reg_lock);
2285 }
2286
2287 #ifdef CONFIG_X86
2288 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2289                         struct vm_area_struct *area)
2290 {
2291         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2292         struct azx *chip = apcm->chip;
2293         if (!azx_snoop(chip))
2294                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2295         return snd_pcm_lib_default_mmap(substream, area);
2296 }
2297 #else
2298 #define azx_pcm_mmap    NULL
2299 #endif
2300
2301 static struct snd_pcm_ops azx_pcm_ops = {
2302         .open = azx_pcm_open,
2303         .close = azx_pcm_close,
2304         .ioctl = snd_pcm_lib_ioctl,
2305         .hw_params = azx_pcm_hw_params,
2306         .hw_free = azx_pcm_hw_free,
2307         .prepare = azx_pcm_prepare,
2308         .trigger = azx_pcm_trigger,
2309         .pointer = azx_pcm_pointer,
2310         .mmap = azx_pcm_mmap,
2311         .page = snd_pcm_sgbuf_ops_page,
2312 };
2313
2314 static void azx_pcm_free(struct snd_pcm *pcm)
2315 {
2316         struct azx_pcm *apcm = pcm->private_data;
2317         if (apcm) {
2318                 list_del(&apcm->list);
2319                 kfree(apcm);
2320         }
2321 }
2322
2323 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2324
2325 static int
2326 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2327                       struct hda_pcm *cpcm)
2328 {
2329         struct azx *chip = bus->private_data;
2330         struct snd_pcm *pcm;
2331         struct azx_pcm *apcm;
2332         int pcm_dev = cpcm->device;
2333         unsigned int size;
2334         int s, err;
2335
2336         list_for_each_entry(apcm, &chip->pcm_list, list) {
2337                 if (apcm->pcm->device == pcm_dev) {
2338                         snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2339                         return -EBUSY;
2340                 }
2341         }
2342         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2343                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2344                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2345                           &pcm);
2346         if (err < 0)
2347                 return err;
2348         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2349         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2350         if (apcm == NULL)
2351                 return -ENOMEM;
2352         apcm->chip = chip;
2353         apcm->pcm = pcm;
2354         apcm->codec = codec;
2355         pcm->private_data = apcm;
2356         pcm->private_free = azx_pcm_free;
2357         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2358                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2359         list_add_tail(&apcm->list, &chip->pcm_list);
2360         cpcm->pcm = pcm;
2361         for (s = 0; s < 2; s++) {
2362                 apcm->hinfo[s] = &cpcm->stream[s];
2363                 if (cpcm->stream[s].substreams)
2364                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2365         }
2366         /* buffer pre-allocation */
2367         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2368         if (size > MAX_PREALLOC_SIZE)
2369                 size = MAX_PREALLOC_SIZE;
2370         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2371                                               snd_dma_pci_data(chip->pci),
2372                                               size, MAX_PREALLOC_SIZE);
2373         return 0;
2374 }
2375
2376 /*
2377  * mixer creation - all stuff is implemented in hda module
2378  */
2379 static int __devinit azx_mixer_create(struct azx *chip)
2380 {
2381         return snd_hda_build_controls(chip->bus);
2382 }
2383
2384
2385 /*
2386  * initialize SD streams
2387  */
2388 static int __devinit azx_init_stream(struct azx *chip)
2389 {
2390         int i;
2391
2392         /* initialize each stream (aka device)
2393          * assign the starting bdl address to each stream (device)
2394          * and initialize
2395          */
2396         for (i = 0; i < chip->num_streams; i++) {
2397                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2398                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2399                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2400                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2401                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2402                 azx_dev->sd_int_sta_mask = 1 << i;
2403                 /* stream tag: must be non-zero and unique */
2404                 azx_dev->index = i;
2405                 azx_dev->stream_tag = i + 1;
2406         }
2407
2408         return 0;
2409 }
2410
2411 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2412 {
2413         if (request_irq(chip->pci->irq, azx_interrupt,
2414                         chip->msi ? 0 : IRQF_SHARED,
2415                         KBUILD_MODNAME, chip)) {
2416                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2417                        "disabling device\n", chip->pci->irq);
2418                 if (do_disconnect)
2419                         snd_card_disconnect(chip->card);
2420                 return -1;
2421         }
2422         chip->irq = chip->pci->irq;
2423         pci_intx(chip->pci, !chip->msi);
2424         return 0;
2425 }
2426
2427
2428 static void azx_stop_chip(struct azx *chip)
2429 {
2430         if (!chip->initialized)
2431                 return;
2432
2433         /* disable interrupts */
2434         azx_int_disable(chip);
2435         azx_int_clear(chip);
2436
2437         /* disable CORB/RIRB */
2438         azx_free_cmd_io(chip);
2439
2440         /* disable position buffer */
2441         azx_writel(chip, DPLBASE, 0);
2442         azx_writel(chip, DPUBASE, 0);
2443
2444         chip->initialized = 0;
2445 }
2446
2447 #ifdef CONFIG_SND_HDA_DSP_LOADER
2448 /*
2449  * DSP loading code (e.g. for CA0132)
2450  */
2451
2452 /* use the first stream for loading DSP */
2453 static struct azx_dev *
2454 azx_get_dsp_loader_dev(struct azx *chip)
2455 {
2456         return &chip->azx_dev[chip->playback_index_offset];
2457 }
2458
2459 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2460                                 unsigned int byte_size,
2461                                 struct snd_dma_buffer *bufp)
2462 {
2463         u32 *bdl;
2464         struct azx *chip = bus->private_data;
2465         struct azx_dev *azx_dev;
2466         int err;
2467
2468         if (snd_hda_lock_devices(bus))
2469                 return -EBUSY;
2470
2471         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2472                                   snd_dma_pci_data(chip->pci),
2473                                   byte_size, bufp);
2474         if (err < 0)
2475                 goto error;
2476
2477         azx_dev = azx_get_dsp_loader_dev(chip);
2478         azx_dev->bufsize = byte_size;
2479         azx_dev->period_bytes = byte_size;
2480         azx_dev->format_val = format;
2481
2482         azx_stream_reset(chip, azx_dev);
2483
2484         /* reset BDL address */
2485         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2486         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2487
2488         azx_dev->frags = 0;
2489         bdl = (u32 *)azx_dev->bdl.area;
2490         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2491         if (err < 0)
2492                 goto error;
2493
2494         azx_setup_controller(chip, azx_dev);
2495         return azx_dev->stream_tag;
2496
2497  error:
2498         snd_hda_unlock_devices(bus);
2499         return err;
2500 }
2501
2502 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2503 {
2504         struct azx *chip = bus->private_data;
2505         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2506
2507         if (start)
2508                 azx_stream_start(chip, azx_dev);
2509         else
2510                 azx_stream_stop(chip, azx_dev);
2511         azx_dev->running = start;
2512 }
2513
2514 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2515                                  struct snd_dma_buffer *dmab)
2516 {
2517         struct azx *chip = bus->private_data;
2518         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2519
2520         /* reset BDL address */
2521         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2522         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2523         azx_sd_writel(azx_dev, SD_CTL, 0);
2524         azx_dev->bufsize = 0;
2525         azx_dev->period_bytes = 0;
2526         azx_dev->format_val = 0;
2527
2528         snd_dma_free_pages(dmab);
2529
2530         snd_hda_unlock_devices(bus);
2531 }
2532 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2533
2534 #ifdef CONFIG_PM
2535 /* power-up/down the controller */
2536 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2537 {
2538         struct azx *chip = bus->private_data;
2539
2540         if (power_up)
2541                 pm_runtime_get_sync(&chip->pci->dev);
2542         else
2543                 pm_runtime_put_sync(&chip->pci->dev);
2544 }
2545
2546 static DEFINE_MUTEX(card_list_lock);
2547 static LIST_HEAD(card_list);
2548
2549 static void azx_add_card_list(struct azx *chip)
2550 {
2551         mutex_lock(&card_list_lock);
2552         list_add(&chip->list, &card_list);
2553         mutex_unlock(&card_list_lock);
2554 }
2555
2556 static void azx_del_card_list(struct azx *chip)
2557 {
2558         mutex_lock(&card_list_lock);
2559         list_del_init(&chip->list);
2560         mutex_unlock(&card_list_lock);
2561 }
2562
2563 /* trigger power-save check at writing parameter */
2564 static int param_set_xint(const char *val, const struct kernel_param *kp)
2565 {
2566         struct azx *chip;
2567         struct hda_codec *c;
2568         int prev = power_save;
2569         int ret = param_set_int(val, kp);
2570
2571         if (ret || prev == power_save)
2572                 return ret;
2573
2574         mutex_lock(&card_list_lock);
2575         list_for_each_entry(chip, &card_list, list) {
2576                 if (!chip->bus || chip->disabled)
2577                         continue;
2578                 list_for_each_entry(c, &chip->bus->codec_list, list)
2579                         snd_hda_power_sync(c);
2580         }
2581         mutex_unlock(&card_list_lock);
2582         return 0;
2583 }
2584 #else
2585 #define azx_add_card_list(chip) /* NOP */
2586 #define azx_del_card_list(chip) /* NOP */
2587 #endif /* CONFIG_PM */
2588
2589 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2590 /*
2591  * power management
2592  */
2593 static int azx_suspend(struct device *dev)
2594 {
2595         struct pci_dev *pci = to_pci_dev(dev);
2596         struct snd_card *card = dev_get_drvdata(dev);
2597         struct azx *chip = card->private_data;
2598         struct azx_pcm *p;
2599
2600         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2601         azx_clear_irq_pending(chip);
2602         list_for_each_entry(p, &chip->pcm_list, list)
2603                 snd_pcm_suspend_all(p->pcm);
2604         if (chip->initialized)
2605                 snd_hda_suspend(chip->bus);
2606         azx_stop_chip(chip);
2607         if (chip->irq >= 0) {
2608                 free_irq(chip->irq, chip);
2609                 chip->irq = -1;
2610         }
2611         if (chip->msi)
2612                 pci_disable_msi(chip->pci);
2613         pci_disable_device(pci);
2614         pci_save_state(pci);
2615         pci_set_power_state(pci, PCI_D3hot);
2616         return 0;
2617 }
2618
2619 static int azx_resume(struct device *dev)
2620 {
2621         struct pci_dev *pci = to_pci_dev(dev);
2622         struct snd_card *card = dev_get_drvdata(dev);
2623         struct azx *chip = card->private_data;
2624
2625         pci_set_power_state(pci, PCI_D0);
2626         pci_restore_state(pci);
2627         if (pci_enable_device(pci) < 0) {
2628                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2629                        "disabling device\n");
2630                 snd_card_disconnect(card);
2631                 return -EIO;
2632         }
2633         pci_set_master(pci);
2634         if (chip->msi)
2635                 if (pci_enable_msi(pci) < 0)
2636                         chip->msi = 0;
2637         if (azx_acquire_irq(chip, 1) < 0)
2638                 return -EIO;
2639         azx_init_pci(chip);
2640
2641         azx_init_chip(chip, 1);
2642
2643         snd_hda_resume(chip->bus);
2644         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2645         return 0;
2646 }
2647 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2648
2649 #ifdef CONFIG_PM_RUNTIME
2650 static int azx_runtime_suspend(struct device *dev)
2651 {
2652         struct snd_card *card = dev_get_drvdata(dev);
2653         struct azx *chip = card->private_data;
2654
2655         if (!power_save_controller)
2656                 return -EAGAIN;
2657
2658         azx_stop_chip(chip);
2659         azx_clear_irq_pending(chip);
2660         return 0;
2661 }
2662
2663 static int azx_runtime_resume(struct device *dev)
2664 {
2665         struct snd_card *card = dev_get_drvdata(dev);
2666         struct azx *chip = card->private_data;
2667
2668         azx_init_pci(chip);
2669         azx_init_chip(chip, 1);
2670         return 0;
2671 }
2672 #endif /* CONFIG_PM_RUNTIME */
2673
2674 #ifdef CONFIG_PM
2675 static const struct dev_pm_ops azx_pm = {
2676         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2677         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2678 };
2679
2680 #define AZX_PM_OPS      &azx_pm
2681 #else
2682 #define AZX_PM_OPS      NULL
2683 #endif /* CONFIG_PM */
2684
2685
2686 /*
2687  * reboot notifier for hang-up problem at power-down
2688  */
2689 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2690 {
2691         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2692         snd_hda_bus_reboot_notify(chip->bus);
2693         azx_stop_chip(chip);
2694         return NOTIFY_OK;
2695 }
2696
2697 static void azx_notifier_register(struct azx *chip)
2698 {
2699         chip->reboot_notifier.notifier_call = azx_halt;
2700         register_reboot_notifier(&chip->reboot_notifier);
2701 }
2702
2703 static void azx_notifier_unregister(struct azx *chip)
2704 {
2705         if (chip->reboot_notifier.notifier_call)
2706                 unregister_reboot_notifier(&chip->reboot_notifier);
2707 }
2708
2709 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2710 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2711
2712 #ifdef SUPPORT_VGA_SWITCHEROO
2713 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2714
2715 static void azx_vs_set_state(struct pci_dev *pci,
2716                              enum vga_switcheroo_state state)
2717 {
2718         struct snd_card *card = pci_get_drvdata(pci);
2719         struct azx *chip = card->private_data;
2720         bool disabled;
2721
2722         if (chip->init_failed)
2723                 return;
2724
2725         disabled = (state == VGA_SWITCHEROO_OFF);
2726         if (chip->disabled == disabled)
2727                 return;
2728
2729         if (!chip->bus) {
2730                 chip->disabled = disabled;
2731                 if (!disabled) {
2732                         snd_printk(KERN_INFO SFX
2733                                    "%s: Start delayed initialization\n",
2734                                    pci_name(chip->pci));
2735                         if (azx_first_init(chip) < 0 ||
2736                             azx_probe_continue(chip) < 0) {
2737                                 snd_printk(KERN_ERR SFX
2738                                            "%s: initialization error\n",
2739                                            pci_name(chip->pci));
2740                                 chip->init_failed = true;
2741                         }
2742                 }
2743         } else {
2744                 snd_printk(KERN_INFO SFX
2745                            "%s %s via VGA-switcheroo\n",
2746                            disabled ? "Disabling" : "Enabling",
2747                            pci_name(chip->pci));
2748                 if (disabled) {
2749                         azx_suspend(&pci->dev);
2750                         chip->disabled = true;
2751                         if (snd_hda_lock_devices(chip->bus))
2752                                 snd_printk(KERN_WARNING SFX
2753                                            "Cannot lock devices!\n");
2754                 } else {
2755                         snd_hda_unlock_devices(chip->bus);
2756                         chip->disabled = false;
2757                         azx_resume(&pci->dev);
2758                 }
2759         }
2760 }
2761
2762 static bool azx_vs_can_switch(struct pci_dev *pci)
2763 {
2764         struct snd_card *card = pci_get_drvdata(pci);
2765         struct azx *chip = card->private_data;
2766
2767         if (chip->init_failed)
2768                 return false;
2769         if (chip->disabled || !chip->bus)
2770                 return true;
2771         if (snd_hda_lock_devices(chip->bus))
2772                 return false;
2773         snd_hda_unlock_devices(chip->bus);
2774         return true;
2775 }
2776
2777 static void __devinit init_vga_switcheroo(struct azx *chip)
2778 {
2779         struct pci_dev *p = get_bound_vga(chip->pci);
2780         if (p) {
2781                 snd_printk(KERN_INFO SFX
2782                            "%s: Handle VGA-switcheroo audio client\n",
2783                            pci_name(chip->pci));
2784                 chip->use_vga_switcheroo = 1;
2785                 pci_dev_put(p);
2786         }
2787 }
2788
2789 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2790         .set_gpu_state = azx_vs_set_state,
2791         .can_switch = azx_vs_can_switch,
2792 };
2793
2794 static int __devinit register_vga_switcheroo(struct azx *chip)
2795 {
2796         int err;
2797
2798         if (!chip->use_vga_switcheroo)
2799                 return 0;
2800         /* FIXME: currently only handling DIS controller
2801          * is there any machine with two switchable HDMI audio controllers?
2802          */
2803         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2804                                                     VGA_SWITCHEROO_DIS,
2805                                                     chip->bus != NULL);
2806         if (err < 0)
2807                 return err;
2808         chip->vga_switcheroo_registered = 1;
2809         return 0;
2810 }
2811 #else
2812 #define init_vga_switcheroo(chip)               /* NOP */
2813 #define register_vga_switcheroo(chip)           0
2814 #define check_hdmi_disabled(pci)        false
2815 #endif /* SUPPORT_VGA_SWITCHER */
2816
2817 /*
2818  * destructor
2819  */
2820 static int azx_free(struct azx *chip)
2821 {
2822         int i;
2823
2824         azx_del_card_list(chip);
2825
2826         azx_notifier_unregister(chip);
2827
2828         if (use_vga_switcheroo(chip)) {
2829                 if (chip->disabled && chip->bus)
2830                         snd_hda_unlock_devices(chip->bus);
2831                 if (chip->vga_switcheroo_registered)
2832                         vga_switcheroo_unregister_client(chip->pci);
2833         }
2834
2835         if (chip->initialized) {
2836                 azx_clear_irq_pending(chip);
2837                 for (i = 0; i < chip->num_streams; i++)
2838                         azx_stream_stop(chip, &chip->azx_dev[i]);
2839                 azx_stop_chip(chip);
2840         }
2841
2842         if (chip->irq >= 0)
2843                 free_irq(chip->irq, (void*)chip);
2844         if (chip->msi)
2845                 pci_disable_msi(chip->pci);
2846         if (chip->remap_addr)
2847                 iounmap(chip->remap_addr);
2848
2849         if (chip->azx_dev) {
2850                 for (i = 0; i < chip->num_streams; i++)
2851                         if (chip->azx_dev[i].bdl.area) {
2852                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2853                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2854                         }
2855         }
2856         if (chip->rb.area) {
2857                 mark_pages_wc(chip, &chip->rb, false);
2858                 snd_dma_free_pages(&chip->rb);
2859         }
2860         if (chip->posbuf.area) {
2861                 mark_pages_wc(chip, &chip->posbuf, false);
2862                 snd_dma_free_pages(&chip->posbuf);
2863         }
2864         if (chip->region_requested)
2865                 pci_release_regions(chip->pci);
2866         pci_disable_device(chip->pci);
2867         kfree(chip->azx_dev);
2868 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2869         if (chip->fw)
2870                 release_firmware(chip->fw);
2871 #endif
2872         kfree(chip);
2873
2874         return 0;
2875 }
2876
2877 static int azx_dev_free(struct snd_device *device)
2878 {
2879         return azx_free(device->device_data);
2880 }
2881
2882 #ifdef SUPPORT_VGA_SWITCHEROO
2883 /*
2884  * Check of disabled HDMI controller by vga-switcheroo
2885  */
2886 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2887 {
2888         struct pci_dev *p;
2889
2890         /* check only discrete GPU */
2891         switch (pci->vendor) {
2892         case PCI_VENDOR_ID_ATI:
2893         case PCI_VENDOR_ID_AMD:
2894         case PCI_VENDOR_ID_NVIDIA:
2895                 if (pci->devfn == 1) {
2896                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2897                                                         pci->bus->number, 0);
2898                         if (p) {
2899                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2900                                         return p;
2901                                 pci_dev_put(p);
2902                         }
2903                 }
2904                 break;
2905         }
2906         return NULL;
2907 }
2908
2909 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2910 {
2911         bool vga_inactive = false;
2912         struct pci_dev *p = get_bound_vga(pci);
2913
2914         if (p) {
2915                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2916                         vga_inactive = true;
2917                 pci_dev_put(p);
2918         }
2919         return vga_inactive;
2920 }
2921 #endif /* SUPPORT_VGA_SWITCHEROO */
2922
2923 /*
2924  * white/black-listing for position_fix
2925  */
2926 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2927         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2928         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2929         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2930         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2931         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2932         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2933         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2934         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2935         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2936         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2937         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2938         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2939         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2940         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2941         {}
2942 };
2943
2944 static int __devinit check_position_fix(struct azx *chip, int fix)
2945 {
2946         const struct snd_pci_quirk *q;
2947
2948         switch (fix) {
2949         case POS_FIX_AUTO:
2950         case POS_FIX_LPIB:
2951         case POS_FIX_POSBUF:
2952         case POS_FIX_VIACOMBO:
2953         case POS_FIX_COMBO:
2954                 return fix;
2955         }
2956
2957         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2958         if (q) {
2959                 printk(KERN_INFO
2960                        "hda_intel: position_fix set to %d "
2961                        "for device %04x:%04x\n",
2962                        q->value, q->subvendor, q->subdevice);
2963                 return q->value;
2964         }
2965
2966         /* Check VIA/ATI HD Audio Controller exist */
2967         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2968                 snd_printd(SFX "Using VIACOMBO position fix\n");
2969                 return POS_FIX_VIACOMBO;
2970         }
2971         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2972                 snd_printd(SFX "Using LPIB position fix\n");
2973                 return POS_FIX_LPIB;
2974         }
2975         return POS_FIX_AUTO;
2976 }
2977
2978 /*
2979  * black-lists for probe_mask
2980  */
2981 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2982         /* Thinkpad often breaks the controller communication when accessing
2983          * to the non-working (or non-existing) modem codec slot.
2984          */
2985         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2986         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2987         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2988         /* broken BIOS */
2989         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2990         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2991         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2992         /* forced codec slots */
2993         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2994         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2995         /* WinFast VP200 H (Teradici) user reported broken communication */
2996         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2997         {}
2998 };
2999
3000 #define AZX_FORCE_CODEC_MASK    0x100
3001
3002 static void __devinit check_probe_mask(struct azx *chip, int dev)
3003 {
3004         const struct snd_pci_quirk *q;
3005
3006         chip->codec_probe_mask = probe_mask[dev];
3007         if (chip->codec_probe_mask == -1) {
3008                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3009                 if (q) {
3010                         printk(KERN_INFO
3011                                "hda_intel: probe_mask set to 0x%x "
3012                                "for device %04x:%04x\n",
3013                                q->value, q->subvendor, q->subdevice);
3014                         chip->codec_probe_mask = q->value;
3015                 }
3016         }
3017
3018         /* check forced option */
3019         if (chip->codec_probe_mask != -1 &&
3020             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3021                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3022                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3023                        chip->codec_mask);
3024         }
3025 }
3026
3027 /*
3028  * white/black-list for enable_msi
3029  */
3030 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
3031         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3032         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3033         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3034         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3035         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3036         {}
3037 };
3038
3039 static void __devinit check_msi(struct azx *chip)
3040 {
3041         const struct snd_pci_quirk *q;
3042
3043         if (enable_msi >= 0) {
3044                 chip->msi = !!enable_msi;
3045                 return;
3046         }
3047         chip->msi = 1;  /* enable MSI as default */
3048         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3049         if (q) {
3050                 printk(KERN_INFO
3051                        "hda_intel: msi for device %04x:%04x set to %d\n",
3052                        q->subvendor, q->subdevice, q->value);
3053                 chip->msi = q->value;
3054                 return;
3055         }
3056
3057         /* NVidia chipsets seem to cause troubles with MSI */
3058         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3059                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3060                 chip->msi = 0;
3061         }
3062 }
3063
3064 /* check the snoop mode availability */
3065 static void __devinit azx_check_snoop_available(struct azx *chip)
3066 {
3067         bool snoop = chip->snoop;
3068
3069         switch (chip->driver_type) {
3070         case AZX_DRIVER_VIA:
3071                 /* force to non-snoop mode for a new VIA controller
3072                  * when BIOS is set
3073                  */
3074                 if (snoop) {
3075                         u8 val;
3076                         pci_read_config_byte(chip->pci, 0x42, &val);
3077                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3078                                 snoop = false;
3079                 }
3080                 break;
3081         case AZX_DRIVER_ATIHDMI_NS:
3082                 /* new ATI HDMI requires non-snoop */
3083                 snoop = false;
3084                 break;
3085         }
3086
3087         if (snoop != chip->snoop) {
3088                 snd_printk(KERN_INFO SFX "Force to %s mode\n",
3089                            snoop ? "snoop" : "non-snoop");
3090                 chip->snoop = snoop;
3091         }
3092 }
3093
3094 /*
3095  * constructor
3096  */
3097 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
3098                                 int dev, unsigned int driver_caps,
3099                                 struct azx **rchip)
3100 {
3101         static struct snd_device_ops ops = {
3102                 .dev_free = azx_dev_free,
3103         };
3104         struct azx *chip;
3105         int err;
3106
3107         *rchip = NULL;
3108
3109         err = pci_enable_device(pci);
3110         if (err < 0)
3111                 return err;
3112
3113         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3114         if (!chip) {
3115                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3116                 pci_disable_device(pci);
3117                 return -ENOMEM;
3118         }
3119
3120         spin_lock_init(&chip->reg_lock);
3121         mutex_init(&chip->open_mutex);
3122         chip->card = card;
3123         chip->pci = pci;
3124         chip->irq = -1;
3125         chip->driver_caps = driver_caps;
3126         chip->driver_type = driver_caps & 0xff;
3127         check_msi(chip);
3128         chip->dev_index = dev;
3129         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3130         INIT_LIST_HEAD(&chip->pcm_list);
3131         INIT_LIST_HEAD(&chip->list);
3132         init_vga_switcheroo(chip);
3133
3134         chip->position_fix[0] = chip->position_fix[1] =
3135                 check_position_fix(chip, position_fix[dev]);
3136         /* combo mode uses LPIB for playback */
3137         if (chip->position_fix[0] == POS_FIX_COMBO) {
3138                 chip->position_fix[0] = POS_FIX_LPIB;
3139                 chip->position_fix[1] = POS_FIX_AUTO;
3140         }
3141
3142         check_probe_mask(chip, dev);
3143
3144         chip->single_cmd = single_cmd;
3145         chip->snoop = hda_snoop;
3146         azx_check_snoop_available(chip);
3147
3148         if (bdl_pos_adj[dev] < 0) {
3149                 switch (chip->driver_type) {
3150                 case AZX_DRIVER_ICH:
3151                 case AZX_DRIVER_PCH:
3152                         bdl_pos_adj[dev] = 1;
3153                         break;
3154                 default:
3155                         bdl_pos_adj[dev] = 32;
3156                         break;
3157                 }
3158         }
3159
3160         if (check_hdmi_disabled(pci)) {
3161                 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3162                            pci_name(pci));
3163                 if (use_vga_switcheroo(chip)) {
3164                         snd_printk(KERN_INFO SFX "Delaying initialization\n");
3165                         chip->disabled = true;
3166                         goto ok;
3167                 }
3168                 kfree(chip);
3169                 pci_disable_device(pci);
3170                 return -ENXIO;
3171         }
3172
3173         err = azx_first_init(chip);
3174         if (err < 0) {
3175                 azx_free(chip);
3176                 return err;
3177         }
3178
3179  ok:
3180         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3181         if (err < 0) {
3182                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3183                 azx_free(chip);
3184                 return err;
3185         }
3186
3187         *rchip = chip;
3188         return 0;
3189 }
3190
3191 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3192 {
3193         int dev = chip->dev_index;
3194         struct pci_dev *pci = chip->pci;
3195         struct snd_card *card = chip->card;
3196         int i, err;
3197         unsigned short gcap;
3198
3199 #if BITS_PER_LONG != 64
3200         /* Fix up base address on ULI M5461 */
3201         if (chip->driver_type == AZX_DRIVER_ULI) {
3202                 u16 tmp3;
3203                 pci_read_config_word(pci, 0x40, &tmp3);
3204                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3205                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3206         }
3207 #endif
3208
3209         err = pci_request_regions(pci, "ICH HD audio");
3210         if (err < 0)
3211                 return err;
3212         chip->region_requested = 1;
3213
3214         chip->addr = pci_resource_start(pci, 0);
3215         chip->remap_addr = pci_ioremap_bar(pci, 0);
3216         if (chip->remap_addr == NULL) {
3217                 snd_printk(KERN_ERR SFX "ioremap error\n");
3218                 return -ENXIO;
3219         }
3220
3221         if (chip->msi)
3222                 if (pci_enable_msi(pci) < 0)
3223                         chip->msi = 0;
3224
3225         if (azx_acquire_irq(chip, 0) < 0)
3226                 return -EBUSY;
3227
3228         pci_set_master(pci);
3229         synchronize_irq(chip->irq);
3230
3231         gcap = azx_readw(chip, GCAP);
3232         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3233
3234         /* disable SB600 64bit support for safety */
3235         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3236                 struct pci_dev *p_smbus;
3237                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3238                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3239                                          NULL);
3240                 if (p_smbus) {
3241                         if (p_smbus->revision < 0x30)
3242                                 gcap &= ~ICH6_GCAP_64OK;
3243                         pci_dev_put(p_smbus);
3244                 }
3245         }
3246
3247         /* disable 64bit DMA address on some devices */
3248         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3249                 snd_printd(SFX "Disabling 64bit DMA\n");
3250                 gcap &= ~ICH6_GCAP_64OK;
3251         }
3252
3253         /* disable buffer size rounding to 128-byte multiples if supported */
3254         if (align_buffer_size >= 0)
3255                 chip->align_buffer_size = !!align_buffer_size;
3256         else {
3257                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3258                         chip->align_buffer_size = 0;
3259                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3260                         chip->align_buffer_size = 1;
3261                 else
3262                         chip->align_buffer_size = 1;
3263         }
3264
3265         /* allow 64bit DMA address if supported by H/W */
3266         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3267                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3268         else {
3269                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3270                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3271         }
3272
3273         /* read number of streams from GCAP register instead of using
3274          * hardcoded value
3275          */
3276         chip->capture_streams = (gcap >> 8) & 0x0f;
3277         chip->playback_streams = (gcap >> 12) & 0x0f;
3278         if (!chip->playback_streams && !chip->capture_streams) {
3279                 /* gcap didn't give any info, switching to old method */
3280
3281                 switch (chip->driver_type) {
3282                 case AZX_DRIVER_ULI:
3283                         chip->playback_streams = ULI_NUM_PLAYBACK;
3284                         chip->capture_streams = ULI_NUM_CAPTURE;
3285                         break;
3286                 case AZX_DRIVER_ATIHDMI:
3287                 case AZX_DRIVER_ATIHDMI_NS:
3288                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3289                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3290                         break;
3291                 case AZX_DRIVER_GENERIC:
3292                 default:
3293                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3294                         chip->capture_streams = ICH6_NUM_CAPTURE;
3295                         break;
3296                 }
3297         }
3298         chip->capture_index_offset = 0;
3299         chip->playback_index_offset = chip->capture_streams;
3300         chip->num_streams = chip->playback_streams + chip->capture_streams;
3301         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3302                                 GFP_KERNEL);
3303         if (!chip->azx_dev) {
3304                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3305                 return -ENOMEM;
3306         }
3307
3308         for (i = 0; i < chip->num_streams; i++) {
3309                 /* allocate memory for the BDL for each stream */
3310                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3311                                           snd_dma_pci_data(chip->pci),
3312                                           BDL_SIZE, &chip->a