ALSA: hda - Enable LPIB delay count for Poulsbo / Oaktrail
[~shefty/rdma-dev.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
70 static char *model[SNDRV_CARDS];
71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_only[SNDRV_CARDS];
75 static int jackpoll_ms[SNDRV_CARDS];
76 static bool single_cmd;
77 static int enable_msi = -1;
78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
79 static char *patch[SNDRV_CARDS];
80 #endif
81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
84 #endif
85
86 module_param_array(index, int, NULL, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
88 module_param_array(id, charp, NULL, 0444);
89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
90 module_param_array(enable, bool, NULL, 0444);
91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92 module_param_array(model, charp, NULL, 0444);
93 MODULE_PARM_DESC(model, "Use the given board model.");
94 module_param_array(position_fix, int, NULL, 0444);
95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
97 module_param_array(bdl_pos_adj, int, NULL, 0644);
98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
99 module_param_array(probe_mask, int, NULL, 0444);
100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
101 module_param_array(probe_only, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
103 module_param_array(jackpoll_ms, int, NULL, 0444);
104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
105 module_param(single_cmd, bool, 0444);
106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107                  "(for debugging only).");
108 module_param(enable_msi, bint, 0444);
109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
111 module_param_array(patch, charp, NULL, 0444);
112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113 #endif
114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
115 module_param_array(beep_mode, bool, NULL, 0444);
116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
117                             "(0=off, 1=on) (default=1).");
118 #endif
119
120 #ifdef CONFIG_PM
121 static int param_set_xint(const char *val, const struct kernel_param *kp);
122 static struct kernel_param_ops param_ops_xint = {
123         .set = param_set_xint,
124         .get = param_get_int,
125 };
126 #define param_check_xint param_check_int
127
128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
129 module_param(power_save, xint, 0644);
130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131                  "(in second, 0 = disable).");
132
133 /* reset the HD-audio controller in power save mode.
134  * this may give more power-saving, but will take longer time to
135  * wake up.
136  */
137 static bool power_save_controller = 1;
138 module_param(power_save_controller, bool, 0644);
139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
140 #endif /* CONFIG_PM */
141
142 static int align_buffer_size = -1;
143 module_param(align_buffer_size, bint, 0644);
144 MODULE_PARM_DESC(align_buffer_size,
145                 "Force buffer and period sizes to be multiple of 128 bytes.");
146
147 #ifdef CONFIG_X86
148 static bool hda_snoop = true;
149 module_param_named(snoop, hda_snoop, bool, 0444);
150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151 #define azx_snoop(chip)         (chip)->snoop
152 #else
153 #define hda_snoop               true
154 #define azx_snoop(chip)         true
155 #endif
156
157
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160                          "{Intel, ICH6M},"
161                          "{Intel, ICH7},"
162                          "{Intel, ESB2},"
163                          "{Intel, ICH8},"
164                          "{Intel, ICH9},"
165                          "{Intel, ICH10},"
166                          "{Intel, PCH},"
167                          "{Intel, CPT},"
168                          "{Intel, PPT},"
169                          "{Intel, LPT},"
170                          "{Intel, LPT_LP},"
171                          "{Intel, HPT},"
172                          "{Intel, PBG},"
173                          "{Intel, SCH},"
174                          "{ATI, SB450},"
175                          "{ATI, SB600},"
176                          "{ATI, RS600},"
177                          "{ATI, RS690},"
178                          "{ATI, RS780},"
179                          "{ATI, R600},"
180                          "{ATI, RV630},"
181                          "{ATI, RV610},"
182                          "{ATI, RV670},"
183                          "{ATI, RV635},"
184                          "{ATI, RV620},"
185                          "{ATI, RV770},"
186                          "{VIA, VT8251},"
187                          "{VIA, VT8237A},"
188                          "{SiS, SIS966},"
189                          "{ULI, M5461}}");
190 MODULE_DESCRIPTION("Intel HDA driver");
191
192 #ifdef CONFIG_SND_VERBOSE_PRINTK
193 #define SFX     /* nop */
194 #else
195 #define SFX     "hda-intel "
196 #endif
197
198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
200 #define SUPPORT_VGA_SWITCHEROO
201 #endif
202 #endif
203
204
205 /*
206  * registers
207  */
208 #define ICH6_REG_GCAP                   0x00
209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
214 #define ICH6_REG_VMIN                   0x02
215 #define ICH6_REG_VMAJ                   0x03
216 #define ICH6_REG_OUTPAY                 0x04
217 #define ICH6_REG_INPAY                  0x06
218 #define ICH6_REG_GCTL                   0x08
219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
222 #define ICH6_REG_WAKEEN                 0x0c
223 #define ICH6_REG_STATESTS               0x0e
224 #define ICH6_REG_GSTS                   0x10
225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
226 #define ICH6_REG_INTCTL                 0x20
227 #define ICH6_REG_INTSTS                 0x24
228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
230 #define ICH6_REG_SSYNC                  0x38
231 #define ICH6_REG_CORBLBASE              0x40
232 #define ICH6_REG_CORBUBASE              0x44
233 #define ICH6_REG_CORBWP                 0x48
234 #define ICH6_REG_CORBRP                 0x4a
235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
236 #define ICH6_REG_CORBCTL                0x4c
237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
239 #define ICH6_REG_CORBSTS                0x4d
240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
241 #define ICH6_REG_CORBSIZE               0x4e
242
243 #define ICH6_REG_RIRBLBASE              0x50
244 #define ICH6_REG_RIRBUBASE              0x54
245 #define ICH6_REG_RIRBWP                 0x58
246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
247 #define ICH6_REG_RINTCNT                0x5a
248 #define ICH6_REG_RIRBCTL                0x5c
249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
252 #define ICH6_REG_RIRBSTS                0x5d
253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
255 #define ICH6_REG_RIRBSIZE               0x5e
256
257 #define ICH6_REG_IC                     0x60
258 #define ICH6_REG_IR                     0x64
259 #define ICH6_REG_IRS                    0x68
260 #define   ICH6_IRS_VALID        (1<<1)
261 #define   ICH6_IRS_BUSY         (1<<0)
262
263 #define ICH6_REG_DPLBASE                0x70
264 #define ICH6_REG_DPUBASE                0x74
265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
266
267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270 /* stream register offsets from stream base */
271 #define ICH6_REG_SD_CTL                 0x00
272 #define ICH6_REG_SD_STS                 0x03
273 #define ICH6_REG_SD_LPIB                0x04
274 #define ICH6_REG_SD_CBL                 0x08
275 #define ICH6_REG_SD_LVI                 0x0c
276 #define ICH6_REG_SD_FIFOW               0x0e
277 #define ICH6_REG_SD_FIFOSIZE            0x10
278 #define ICH6_REG_SD_FORMAT              0x12
279 #define ICH6_REG_SD_BDLPL               0x18
280 #define ICH6_REG_SD_BDLPU               0x1c
281
282 /* PCI space */
283 #define ICH6_PCIREG_TCSEL       0x44
284
285 /*
286  * other constants
287  */
288
289 /* max number of SDs */
290 /* ICH, ATI and VIA have 4 playback and 4 capture */
291 #define ICH6_NUM_CAPTURE        4
292 #define ICH6_NUM_PLAYBACK       4
293
294 /* ULI has 6 playback and 5 capture */
295 #define ULI_NUM_CAPTURE         5
296 #define ULI_NUM_PLAYBACK        6
297
298 /* ATI HDMI has 1 playback and 0 capture */
299 #define ATIHDMI_NUM_CAPTURE     0
300 #define ATIHDMI_NUM_PLAYBACK    1
301
302 /* TERA has 4 playback and 3 capture */
303 #define TERA_NUM_CAPTURE        3
304 #define TERA_NUM_PLAYBACK       4
305
306 /* this number is statically defined for simplicity */
307 #define MAX_AZX_DEV             16
308
309 /* max number of fragments - we may use more if allocating more pages for BDL */
310 #define BDL_SIZE                4096
311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
312 #define AZX_MAX_FRAG            32
313 /* max buffer size - no h/w limit, you can increase as you like */
314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
315
316 /* RIRB int mask: overrun[2], response[0] */
317 #define RIRB_INT_RESPONSE       0x01
318 #define RIRB_INT_OVERRUN        0x04
319 #define RIRB_INT_MASK           0x05
320
321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
322 #define AZX_MAX_CODECS          8
323 #define AZX_DEFAULT_CODECS      4
324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
325
326 /* SD_CTL bits */
327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
333 #define SD_CTL_STREAM_TAG_SHIFT 20
334
335 /* SD_CTL and SD_STS */
336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340                                  SD_INT_COMPLETE)
341
342 /* SD_STS */
343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
344
345 /* INTCTL and INTSTS */
346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
349
350 /* below are so far hardcoded - should read registers in future */
351 #define ICH6_MAX_CORB_ENTRIES   256
352 #define ICH6_MAX_RIRB_ENTRIES   256
353
354 /* position fix mode */
355 enum {
356         POS_FIX_AUTO,
357         POS_FIX_LPIB,
358         POS_FIX_POSBUF,
359         POS_FIX_VIACOMBO,
360         POS_FIX_COMBO,
361 };
362
363 /* Defines for ATI HD Audio support in SB450 south bridge */
364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
366
367 /* Defines for Nvidia HDA support */
368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
370 #define NVIDIA_HDA_ISTRM_COH          0x4d
371 #define NVIDIA_HDA_OSTRM_COH          0x4c
372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
373
374 /* Defines for Intel SCH HDA snoop control */
375 #define INTEL_SCH_HDA_DEVC      0x78
376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
377
378 /* Define IN stream 0 FIFO size offset in VIA controller */
379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380 /* Define VIA HD Audio Device ID*/
381 #define VIA_HDAC_DEVICE_ID              0x3288
382
383 /* HD Audio class code */
384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
385
386 /*
387  */
388
389 struct azx_dev {
390         struct snd_dma_buffer bdl; /* BDL buffer */
391         u32 *posbuf;            /* position buffer pointer */
392
393         unsigned int bufsize;   /* size of the play buffer in bytes */
394         unsigned int period_bytes; /* size of the period in bytes */
395         unsigned int frags;     /* number for period in the play buffer */
396         unsigned int fifo_size; /* FIFO size */
397         unsigned long start_wallclk;    /* start + minimum wallclk */
398         unsigned long period_wallclk;   /* wallclk for period */
399
400         void __iomem *sd_addr;  /* stream descriptor pointer */
401
402         u32 sd_int_sta_mask;    /* stream int status mask */
403
404         /* pcm support */
405         struct snd_pcm_substream *substream;    /* assigned substream,
406                                                  * set in PCM open
407                                                  */
408         unsigned int format_val;        /* format value to be set in the
409                                          * controller and the codec
410                                          */
411         unsigned char stream_tag;       /* assigned stream */
412         unsigned char index;            /* stream index */
413         int assigned_key;               /* last device# key assigned to */
414
415         unsigned int opened :1;
416         unsigned int running :1;
417         unsigned int irq_pending :1;
418         /*
419          * For VIA:
420          *  A flag to ensure DMA position is 0
421          *  when link position is not greater than FIFO size
422          */
423         unsigned int insufficient :1;
424         unsigned int wc_marked:1;
425         unsigned int no_period_wakeup:1;
426
427         struct timecounter  azx_tc;
428         struct cyclecounter azx_cc;
429 };
430
431 /* CORB/RIRB */
432 struct azx_rb {
433         u32 *buf;               /* CORB/RIRB buffer
434                                  * Each CORB entry is 4byte, RIRB is 8byte
435                                  */
436         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
437         /* for RIRB */
438         unsigned short rp, wp;  /* read/write pointers */
439         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
440         u32 res[AZX_MAX_CODECS];        /* last read value */
441 };
442
443 struct azx_pcm {
444         struct azx *chip;
445         struct snd_pcm *pcm;
446         struct hda_codec *codec;
447         struct hda_pcm_stream *hinfo[2];
448         struct list_head list;
449 };
450
451 struct azx {
452         struct snd_card *card;
453         struct pci_dev *pci;
454         int dev_index;
455
456         /* chip type specific */
457         int driver_type;
458         unsigned int driver_caps;
459         int playback_streams;
460         int playback_index_offset;
461         int capture_streams;
462         int capture_index_offset;
463         int num_streams;
464
465         /* pci resources */
466         unsigned long addr;
467         void __iomem *remap_addr;
468         int irq;
469
470         /* locks */
471         spinlock_t reg_lock;
472         struct mutex open_mutex;
473         struct completion probe_wait;
474
475         /* streams (x num_streams) */
476         struct azx_dev *azx_dev;
477
478         /* PCM */
479         struct list_head pcm_list; /* azx_pcm list */
480
481         /* HD codec */
482         unsigned short codec_mask;
483         int  codec_probe_mask; /* copied from probe_mask option */
484         struct hda_bus *bus;
485         unsigned int beep_mode;
486
487         /* CORB/RIRB */
488         struct azx_rb corb;
489         struct azx_rb rirb;
490
491         /* CORB/RIRB and position buffers */
492         struct snd_dma_buffer rb;
493         struct snd_dma_buffer posbuf;
494
495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
496         const struct firmware *fw;
497 #endif
498
499         /* flags */
500         int position_fix[2]; /* for both playback/capture streams */
501         int poll_count;
502         unsigned int running :1;
503         unsigned int initialized :1;
504         unsigned int single_cmd :1;
505         unsigned int polling_mode :1;
506         unsigned int msi :1;
507         unsigned int irq_pending_warned :1;
508         unsigned int probing :1; /* codec probing phase */
509         unsigned int snoop:1;
510         unsigned int align_buffer_size:1;
511         unsigned int region_requested:1;
512
513         /* VGA-switcheroo setup */
514         unsigned int use_vga_switcheroo:1;
515         unsigned int vga_switcheroo_registered:1;
516         unsigned int init_failed:1; /* delayed init failed */
517         unsigned int disabled:1; /* disabled by VGA-switcher */
518
519         /* for debugging */
520         unsigned int last_cmd[AZX_MAX_CODECS];
521
522         /* for pending irqs */
523         struct work_struct irq_pending_work;
524
525         /* reboot notifier (for mysterious hangup problem at power-down) */
526         struct notifier_block reboot_notifier;
527
528         /* card list (for power_save trigger) */
529         struct list_head list;
530 };
531
532 #define CREATE_TRACE_POINTS
533 #include "hda_intel_trace.h"
534
535 /* driver types */
536 enum {
537         AZX_DRIVER_ICH,
538         AZX_DRIVER_PCH,
539         AZX_DRIVER_SCH,
540         AZX_DRIVER_ATI,
541         AZX_DRIVER_ATIHDMI,
542         AZX_DRIVER_ATIHDMI_NS,
543         AZX_DRIVER_VIA,
544         AZX_DRIVER_SIS,
545         AZX_DRIVER_ULI,
546         AZX_DRIVER_NVIDIA,
547         AZX_DRIVER_TERA,
548         AZX_DRIVER_CTX,
549         AZX_DRIVER_CTHDA,
550         AZX_DRIVER_GENERIC,
551         AZX_NUM_DRIVERS, /* keep this as last entry */
552 };
553
554 /* driver quirks (capabilities) */
555 /* bits 0-7 are used for indicating driver type */
556 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
557 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
558 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
559 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
560 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
561 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
562 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
563 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
564 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
565 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
566 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
567 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
568 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
569 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
570 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
571 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
572 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
573 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
574
575 /* quirks for Intel PCH */
576 #define AZX_DCAPS_INTEL_PCH_NOPM \
577         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
578          AZX_DCAPS_COUNT_LPIB_DELAY)
579
580 #define AZX_DCAPS_INTEL_PCH \
581         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
582
583 /* quirks for ATI SB / AMD Hudson */
584 #define AZX_DCAPS_PRESET_ATI_SB \
585         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
586          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
587
588 /* quirks for ATI/AMD HDMI */
589 #define AZX_DCAPS_PRESET_ATI_HDMI \
590         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
591
592 /* quirks for Nvidia */
593 #define AZX_DCAPS_PRESET_NVIDIA \
594         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
595          AZX_DCAPS_ALIGN_BUFSIZE)
596
597 #define AZX_DCAPS_PRESET_CTHDA \
598         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
599
600 /*
601  * VGA-switcher support
602  */
603 #ifdef SUPPORT_VGA_SWITCHEROO
604 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
605 #else
606 #define use_vga_switcheroo(chip)        0
607 #endif
608
609 static char *driver_short_names[] = {
610         [AZX_DRIVER_ICH] = "HDA Intel",
611         [AZX_DRIVER_PCH] = "HDA Intel PCH",
612         [AZX_DRIVER_SCH] = "HDA Intel MID",
613         [AZX_DRIVER_ATI] = "HDA ATI SB",
614         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
615         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
616         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
617         [AZX_DRIVER_SIS] = "HDA SIS966",
618         [AZX_DRIVER_ULI] = "HDA ULI M5461",
619         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
620         [AZX_DRIVER_TERA] = "HDA Teradici", 
621         [AZX_DRIVER_CTX] = "HDA Creative", 
622         [AZX_DRIVER_CTHDA] = "HDA Creative",
623         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
624 };
625
626 /*
627  * macros for easy use
628  */
629 #define azx_writel(chip,reg,value) \
630         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
631 #define azx_readl(chip,reg) \
632         readl((chip)->remap_addr + ICH6_REG_##reg)
633 #define azx_writew(chip,reg,value) \
634         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
635 #define azx_readw(chip,reg) \
636         readw((chip)->remap_addr + ICH6_REG_##reg)
637 #define azx_writeb(chip,reg,value) \
638         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
639 #define azx_readb(chip,reg) \
640         readb((chip)->remap_addr + ICH6_REG_##reg)
641
642 #define azx_sd_writel(dev,reg,value) \
643         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
644 #define azx_sd_readl(dev,reg) \
645         readl((dev)->sd_addr + ICH6_REG_##reg)
646 #define azx_sd_writew(dev,reg,value) \
647         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
648 #define azx_sd_readw(dev,reg) \
649         readw((dev)->sd_addr + ICH6_REG_##reg)
650 #define azx_sd_writeb(dev,reg,value) \
651         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
652 #define azx_sd_readb(dev,reg) \
653         readb((dev)->sd_addr + ICH6_REG_##reg)
654
655 /* for pcm support */
656 #define get_azx_dev(substream) (substream->runtime->private_data)
657
658 #ifdef CONFIG_X86
659 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
660 {
661         if (azx_snoop(chip))
662                 return;
663         if (addr && size) {
664                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
665                 if (on)
666                         set_memory_wc((unsigned long)addr, pages);
667                 else
668                         set_memory_wb((unsigned long)addr, pages);
669         }
670 }
671
672 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
673                                  bool on)
674 {
675         __mark_pages_wc(chip, buf->area, buf->bytes, on);
676 }
677 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
678                                    struct snd_pcm_runtime *runtime, bool on)
679 {
680         if (azx_dev->wc_marked != on) {
681                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
682                 azx_dev->wc_marked = on;
683         }
684 }
685 #else
686 /* NOP for other archs */
687 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
688                                  bool on)
689 {
690 }
691 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
692                                    struct snd_pcm_runtime *runtime, bool on)
693 {
694 }
695 #endif
696
697 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
698 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
699 /*
700  * Interface for HD codec
701  */
702
703 /*
704  * CORB / RIRB interface
705  */
706 static int azx_alloc_cmd_io(struct azx *chip)
707 {
708         int err;
709
710         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
711         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
712                                   snd_dma_pci_data(chip->pci),
713                                   PAGE_SIZE, &chip->rb);
714         if (err < 0) {
715                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
716                 return err;
717         }
718         mark_pages_wc(chip, &chip->rb, true);
719         return 0;
720 }
721
722 static void azx_init_cmd_io(struct azx *chip)
723 {
724         spin_lock_irq(&chip->reg_lock);
725         /* CORB set up */
726         chip->corb.addr = chip->rb.addr;
727         chip->corb.buf = (u32 *)chip->rb.area;
728         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
729         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
730
731         /* set the corb size to 256 entries (ULI requires explicitly) */
732         azx_writeb(chip, CORBSIZE, 0x02);
733         /* set the corb write pointer to 0 */
734         azx_writew(chip, CORBWP, 0);
735         /* reset the corb hw read pointer */
736         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
737         /* enable corb dma */
738         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
739
740         /* RIRB set up */
741         chip->rirb.addr = chip->rb.addr + 2048;
742         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
743         chip->rirb.wp = chip->rirb.rp = 0;
744         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
745         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
746         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
747
748         /* set the rirb size to 256 entries (ULI requires explicitly) */
749         azx_writeb(chip, RIRBSIZE, 0x02);
750         /* reset the rirb hw write pointer */
751         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
752         /* set N=1, get RIRB response interrupt for new entry */
753         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
754                 azx_writew(chip, RINTCNT, 0xc0);
755         else
756                 azx_writew(chip, RINTCNT, 1);
757         /* enable rirb dma and response irq */
758         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
759         spin_unlock_irq(&chip->reg_lock);
760 }
761
762 static void azx_free_cmd_io(struct azx *chip)
763 {
764         spin_lock_irq(&chip->reg_lock);
765         /* disable ringbuffer DMAs */
766         azx_writeb(chip, RIRBCTL, 0);
767         azx_writeb(chip, CORBCTL, 0);
768         spin_unlock_irq(&chip->reg_lock);
769 }
770
771 static unsigned int azx_command_addr(u32 cmd)
772 {
773         unsigned int addr = cmd >> 28;
774
775         if (addr >= AZX_MAX_CODECS) {
776                 snd_BUG();
777                 addr = 0;
778         }
779
780         return addr;
781 }
782
783 static unsigned int azx_response_addr(u32 res)
784 {
785         unsigned int addr = res & 0xf;
786
787         if (addr >= AZX_MAX_CODECS) {
788                 snd_BUG();
789                 addr = 0;
790         }
791
792         return addr;
793 }
794
795 /* send a command */
796 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
797 {
798         struct azx *chip = bus->private_data;
799         unsigned int addr = azx_command_addr(val);
800         unsigned int wp;
801
802         spin_lock_irq(&chip->reg_lock);
803
804         /* add command to corb */
805         wp = azx_readw(chip, CORBWP);
806         if (wp == 0xffff) {
807                 /* something wrong, controller likely turned to D3 */
808                 spin_unlock_irq(&chip->reg_lock);
809                 return -1;
810         }
811         wp++;
812         wp %= ICH6_MAX_CORB_ENTRIES;
813
814         chip->rirb.cmds[addr]++;
815         chip->corb.buf[wp] = cpu_to_le32(val);
816         azx_writel(chip, CORBWP, wp);
817
818         spin_unlock_irq(&chip->reg_lock);
819
820         return 0;
821 }
822
823 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
824
825 /* retrieve RIRB entry - called from interrupt handler */
826 static void azx_update_rirb(struct azx *chip)
827 {
828         unsigned int rp, wp;
829         unsigned int addr;
830         u32 res, res_ex;
831
832         wp = azx_readw(chip, RIRBWP);
833         if (wp == 0xffff) {
834                 /* something wrong, controller likely turned to D3 */
835                 return;
836         }
837
838         if (wp == chip->rirb.wp)
839                 return;
840         chip->rirb.wp = wp;
841
842         while (chip->rirb.rp != wp) {
843                 chip->rirb.rp++;
844                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
845
846                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
847                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
848                 res = le32_to_cpu(chip->rirb.buf[rp]);
849                 addr = azx_response_addr(res_ex);
850                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
851                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
852                 else if (chip->rirb.cmds[addr]) {
853                         chip->rirb.res[addr] = res;
854                         smp_wmb();
855                         chip->rirb.cmds[addr]--;
856                 } else
857                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
858                                    "last cmd=%#08x\n",
859                                    pci_name(chip->pci),
860                                    res, res_ex,
861                                    chip->last_cmd[addr]);
862         }
863 }
864
865 /* receive a response */
866 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
867                                           unsigned int addr)
868 {
869         struct azx *chip = bus->private_data;
870         unsigned long timeout;
871         unsigned long loopcounter;
872         int do_poll = 0;
873
874  again:
875         timeout = jiffies + msecs_to_jiffies(1000);
876
877         for (loopcounter = 0;; loopcounter++) {
878                 if (chip->polling_mode || do_poll) {
879                         spin_lock_irq(&chip->reg_lock);
880                         azx_update_rirb(chip);
881                         spin_unlock_irq(&chip->reg_lock);
882                 }
883                 if (!chip->rirb.cmds[addr]) {
884                         smp_rmb();
885                         bus->rirb_error = 0;
886
887                         if (!do_poll)
888                                 chip->poll_count = 0;
889                         return chip->rirb.res[addr]; /* the last value */
890                 }
891                 if (time_after(jiffies, timeout))
892                         break;
893                 if (bus->needs_damn_long_delay || loopcounter > 3000)
894                         msleep(2); /* temporary workaround */
895                 else {
896                         udelay(10);
897                         cond_resched();
898                 }
899         }
900
901         if (!chip->polling_mode && chip->poll_count < 2) {
902                 snd_printdd(SFX "%s: azx_get_response timeout, "
903                            "polling the codec once: last cmd=0x%08x\n",
904                            pci_name(chip->pci), chip->last_cmd[addr]);
905                 do_poll = 1;
906                 chip->poll_count++;
907                 goto again;
908         }
909
910
911         if (!chip->polling_mode) {
912                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
913                            "switching to polling mode: last cmd=0x%08x\n",
914                            pci_name(chip->pci), chip->last_cmd[addr]);
915                 chip->polling_mode = 1;
916                 goto again;
917         }
918
919         if (chip->msi) {
920                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
921                            "disabling MSI: last cmd=0x%08x\n",
922                            pci_name(chip->pci), chip->last_cmd[addr]);
923                 free_irq(chip->irq, chip);
924                 chip->irq = -1;
925                 pci_disable_msi(chip->pci);
926                 chip->msi = 0;
927                 if (azx_acquire_irq(chip, 1) < 0) {
928                         bus->rirb_error = 1;
929                         return -1;
930                 }
931                 goto again;
932         }
933
934         if (chip->probing) {
935                 /* If this critical timeout happens during the codec probing
936                  * phase, this is likely an access to a non-existing codec
937                  * slot.  Better to return an error and reset the system.
938                  */
939                 return -1;
940         }
941
942         /* a fatal communication error; need either to reset or to fallback
943          * to the single_cmd mode
944          */
945         bus->rirb_error = 1;
946         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
947                 bus->response_reset = 1;
948                 return -1; /* give a chance to retry */
949         }
950
951         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
952                    "switching to single_cmd mode: last cmd=0x%08x\n",
953                    chip->last_cmd[addr]);
954         chip->single_cmd = 1;
955         bus->response_reset = 0;
956         /* release CORB/RIRB */
957         azx_free_cmd_io(chip);
958         /* disable unsolicited responses */
959         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
960         return -1;
961 }
962
963 /*
964  * Use the single immediate command instead of CORB/RIRB for simplicity
965  *
966  * Note: according to Intel, this is not preferred use.  The command was
967  *       intended for the BIOS only, and may get confused with unsolicited
968  *       responses.  So, we shouldn't use it for normal operation from the
969  *       driver.
970  *       I left the codes, however, for debugging/testing purposes.
971  */
972
973 /* receive a response */
974 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
975 {
976         int timeout = 50;
977
978         while (timeout--) {
979                 /* check IRV busy bit */
980                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
981                         /* reuse rirb.res as the response return value */
982                         chip->rirb.res[addr] = azx_readl(chip, IR);
983                         return 0;
984                 }
985                 udelay(1);
986         }
987         if (printk_ratelimit())
988                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
989                            pci_name(chip->pci), azx_readw(chip, IRS));
990         chip->rirb.res[addr] = -1;
991         return -EIO;
992 }
993
994 /* send a command */
995 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
996 {
997         struct azx *chip = bus->private_data;
998         unsigned int addr = azx_command_addr(val);
999         int timeout = 50;
1000
1001         bus->rirb_error = 0;
1002         while (timeout--) {
1003                 /* check ICB busy bit */
1004                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1005                         /* Clear IRV valid bit */
1006                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1007                                    ICH6_IRS_VALID);
1008                         azx_writel(chip, IC, val);
1009                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1010                                    ICH6_IRS_BUSY);
1011                         return azx_single_wait_for_response(chip, addr);
1012                 }
1013                 udelay(1);
1014         }
1015         if (printk_ratelimit())
1016                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1017                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1018         return -EIO;
1019 }
1020
1021 /* receive a response */
1022 static unsigned int azx_single_get_response(struct hda_bus *bus,
1023                                             unsigned int addr)
1024 {
1025         struct azx *chip = bus->private_data;
1026         return chip->rirb.res[addr];
1027 }
1028
1029 /*
1030  * The below are the main callbacks from hda_codec.
1031  *
1032  * They are just the skeleton to call sub-callbacks according to the
1033  * current setting of chip->single_cmd.
1034  */
1035
1036 /* send a command */
1037 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1038 {
1039         struct azx *chip = bus->private_data;
1040
1041         if (chip->disabled)
1042                 return 0;
1043         chip->last_cmd[azx_command_addr(val)] = val;
1044         if (chip->single_cmd)
1045                 return azx_single_send_cmd(bus, val);
1046         else
1047                 return azx_corb_send_cmd(bus, val);
1048 }
1049
1050 /* get a response */
1051 static unsigned int azx_get_response(struct hda_bus *bus,
1052                                      unsigned int addr)
1053 {
1054         struct azx *chip = bus->private_data;
1055         if (chip->disabled)
1056                 return 0;
1057         if (chip->single_cmd)
1058                 return azx_single_get_response(bus, addr);
1059         else
1060                 return azx_rirb_get_response(bus, addr);
1061 }
1062
1063 #ifdef CONFIG_PM
1064 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1065 #endif
1066
1067 /* reset codec link */
1068 static int azx_reset(struct azx *chip, int full_reset)
1069 {
1070         unsigned long timeout;
1071
1072         if (!full_reset)
1073                 goto __skip;
1074
1075         /* clear STATESTS */
1076         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1077
1078         /* reset controller */
1079         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1080
1081         timeout = jiffies + msecs_to_jiffies(100);
1082         while (azx_readb(chip, GCTL) &&
1083                         time_before(jiffies, timeout))
1084                 usleep_range(500, 1000);
1085
1086         /* delay for >= 100us for codec PLL to settle per spec
1087          * Rev 0.9 section 5.5.1
1088          */
1089         usleep_range(500, 1000);
1090
1091         /* Bring controller out of reset */
1092         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1093
1094         timeout = jiffies + msecs_to_jiffies(100);
1095         while (!azx_readb(chip, GCTL) &&
1096                         time_before(jiffies, timeout))
1097                 usleep_range(500, 1000);
1098
1099         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1100         usleep_range(1000, 1200);
1101
1102       __skip:
1103         /* check to see if controller is ready */
1104         if (!azx_readb(chip, GCTL)) {
1105                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1106                 return -EBUSY;
1107         }
1108
1109         /* Accept unsolicited responses */
1110         if (!chip->single_cmd)
1111                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1112                            ICH6_GCTL_UNSOL);
1113
1114         /* detect codecs */
1115         if (!chip->codec_mask) {
1116                 chip->codec_mask = azx_readw(chip, STATESTS);
1117                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1118         }
1119
1120         return 0;
1121 }
1122
1123
1124 /*
1125  * Lowlevel interface
1126  */  
1127
1128 /* enable interrupts */
1129 static void azx_int_enable(struct azx *chip)
1130 {
1131         /* enable controller CIE and GIE */
1132         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1133                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1134 }
1135
1136 /* disable interrupts */
1137 static void azx_int_disable(struct azx *chip)
1138 {
1139         int i;
1140
1141         /* disable interrupts in stream descriptor */
1142         for (i = 0; i < chip->num_streams; i++) {
1143                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1144                 azx_sd_writeb(azx_dev, SD_CTL,
1145                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1146         }
1147
1148         /* disable SIE for all streams */
1149         azx_writeb(chip, INTCTL, 0);
1150
1151         /* disable controller CIE and GIE */
1152         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1153                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1154 }
1155
1156 /* clear interrupts */
1157 static void azx_int_clear(struct azx *chip)
1158 {
1159         int i;
1160
1161         /* clear stream status */
1162         for (i = 0; i < chip->num_streams; i++) {
1163                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1164                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1165         }
1166
1167         /* clear STATESTS */
1168         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1169
1170         /* clear rirb status */
1171         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1172
1173         /* clear int status */
1174         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1175 }
1176
1177 /* start a stream */
1178 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1179 {
1180         /*
1181          * Before stream start, initialize parameter
1182          */
1183         azx_dev->insufficient = 1;
1184
1185         /* enable SIE */
1186         azx_writel(chip, INTCTL,
1187                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1188         /* set DMA start and interrupt mask */
1189         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1190                       SD_CTL_DMA_START | SD_INT_MASK);
1191 }
1192
1193 /* stop DMA */
1194 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1195 {
1196         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1197                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1198         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1199 }
1200
1201 /* stop a stream */
1202 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1203 {
1204         azx_stream_clear(chip, azx_dev);
1205         /* disable SIE */
1206         azx_writel(chip, INTCTL,
1207                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1208 }
1209
1210
1211 /*
1212  * reset and start the controller registers
1213  */
1214 static void azx_init_chip(struct azx *chip, int full_reset)
1215 {
1216         if (chip->initialized)
1217                 return;
1218
1219         /* reset controller */
1220         azx_reset(chip, full_reset);
1221
1222         /* initialize interrupts */
1223         azx_int_clear(chip);
1224         azx_int_enable(chip);
1225
1226         /* initialize the codec command I/O */
1227         if (!chip->single_cmd)
1228                 azx_init_cmd_io(chip);
1229
1230         /* program the position buffer */
1231         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1232         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1233
1234         chip->initialized = 1;
1235 }
1236
1237 /*
1238  * initialize the PCI registers
1239  */
1240 /* update bits in a PCI register byte */
1241 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1242                             unsigned char mask, unsigned char val)
1243 {
1244         unsigned char data;
1245
1246         pci_read_config_byte(pci, reg, &data);
1247         data &= ~mask;
1248         data |= (val & mask);
1249         pci_write_config_byte(pci, reg, data);
1250 }
1251
1252 static void azx_init_pci(struct azx *chip)
1253 {
1254         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1255          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1256          * Ensuring these bits are 0 clears playback static on some HD Audio
1257          * codecs.
1258          * The PCI register TCSEL is defined in the Intel manuals.
1259          */
1260         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1261                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1262                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1263         }
1264
1265         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1266          * we need to enable snoop.
1267          */
1268         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1269                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1270                 update_pci_byte(chip->pci,
1271                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1272                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1273         }
1274
1275         /* For NVIDIA HDA, enable snoop */
1276         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1277                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1278                 update_pci_byte(chip->pci,
1279                                 NVIDIA_HDA_TRANSREG_ADDR,
1280                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1281                 update_pci_byte(chip->pci,
1282                                 NVIDIA_HDA_ISTRM_COH,
1283                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1284                 update_pci_byte(chip->pci,
1285                                 NVIDIA_HDA_OSTRM_COH,
1286                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1287         }
1288
1289         /* Enable SCH/PCH snoop if needed */
1290         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1291                 unsigned short snoop;
1292                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1293                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1294                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1295                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1296                         if (!azx_snoop(chip))
1297                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1298                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1299                         pci_read_config_word(chip->pci,
1300                                 INTEL_SCH_HDA_DEVC, &snoop);
1301                 }
1302                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1303                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1304                                 ? "Disabled" : "Enabled");
1305         }
1306 }
1307
1308
1309 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1310
1311 /*
1312  * interrupt handler
1313  */
1314 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1315 {
1316         struct azx *chip = dev_id;
1317         struct azx_dev *azx_dev;
1318         u32 status;
1319         u8 sd_status;
1320         int i, ok;
1321
1322 #ifdef CONFIG_PM_RUNTIME
1323         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1324                 return IRQ_NONE;
1325 #endif
1326
1327         spin_lock(&chip->reg_lock);
1328
1329         if (chip->disabled) {
1330                 spin_unlock(&chip->reg_lock);
1331                 return IRQ_NONE;
1332         }
1333
1334         status = azx_readl(chip, INTSTS);
1335         if (status == 0) {
1336                 spin_unlock(&chip->reg_lock);
1337                 return IRQ_NONE;
1338         }
1339         
1340         for (i = 0; i < chip->num_streams; i++) {
1341                 azx_dev = &chip->azx_dev[i];
1342                 if (status & azx_dev->sd_int_sta_mask) {
1343                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1344                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1345                         if (!azx_dev->substream || !azx_dev->running ||
1346                             !(sd_status & SD_INT_COMPLETE))
1347                                 continue;
1348                         /* check whether this IRQ is really acceptable */
1349                         ok = azx_position_ok(chip, azx_dev);
1350                         if (ok == 1) {
1351                                 azx_dev->irq_pending = 0;
1352                                 spin_unlock(&chip->reg_lock);
1353                                 snd_pcm_period_elapsed(azx_dev->substream);
1354                                 spin_lock(&chip->reg_lock);
1355                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1356                                 /* bogus IRQ, process it later */
1357                                 azx_dev->irq_pending = 1;
1358                                 queue_work(chip->bus->workq,
1359                                            &chip->irq_pending_work);
1360                         }
1361                 }
1362         }
1363
1364         /* clear rirb int */
1365         status = azx_readb(chip, RIRBSTS);
1366         if (status & RIRB_INT_MASK) {
1367                 if (status & RIRB_INT_RESPONSE) {
1368                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1369                                 udelay(80);
1370                         azx_update_rirb(chip);
1371                 }
1372                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1373         }
1374
1375 #if 0
1376         /* clear state status int */
1377         if (azx_readb(chip, STATESTS) & 0x04)
1378                 azx_writeb(chip, STATESTS, 0x04);
1379 #endif
1380         spin_unlock(&chip->reg_lock);
1381         
1382         return IRQ_HANDLED;
1383 }
1384
1385
1386 /*
1387  * set up a BDL entry
1388  */
1389 static int setup_bdle(struct azx *chip,
1390                       struct snd_pcm_substream *substream,
1391                       struct azx_dev *azx_dev, u32 **bdlp,
1392                       int ofs, int size, int with_ioc)
1393 {
1394         u32 *bdl = *bdlp;
1395
1396         while (size > 0) {
1397                 dma_addr_t addr;
1398                 int chunk;
1399
1400                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1401                         return -EINVAL;
1402
1403                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1404                 /* program the address field of the BDL entry */
1405                 bdl[0] = cpu_to_le32((u32)addr);
1406                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1407                 /* program the size field of the BDL entry */
1408                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1409                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1410                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1411                         u32 remain = 0x1000 - (ofs & 0xfff);
1412                         if (chunk > remain)
1413                                 chunk = remain;
1414                 }
1415                 bdl[2] = cpu_to_le32(chunk);
1416                 /* program the IOC to enable interrupt
1417                  * only when the whole fragment is processed
1418                  */
1419                 size -= chunk;
1420                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1421                 bdl += 4;
1422                 azx_dev->frags++;
1423                 ofs += chunk;
1424         }
1425         *bdlp = bdl;
1426         return ofs;
1427 }
1428
1429 /*
1430  * set up BDL entries
1431  */
1432 static int azx_setup_periods(struct azx *chip,
1433                              struct snd_pcm_substream *substream,
1434                              struct azx_dev *azx_dev)
1435 {
1436         u32 *bdl;
1437         int i, ofs, periods, period_bytes;
1438         int pos_adj;
1439
1440         /* reset BDL address */
1441         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1442         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1443
1444         period_bytes = azx_dev->period_bytes;
1445         periods = azx_dev->bufsize / period_bytes;
1446
1447         /* program the initial BDL entries */
1448         bdl = (u32 *)azx_dev->bdl.area;
1449         ofs = 0;
1450         azx_dev->frags = 0;
1451         pos_adj = bdl_pos_adj[chip->dev_index];
1452         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1453                 struct snd_pcm_runtime *runtime = substream->runtime;
1454                 int pos_align = pos_adj;
1455                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1456                 if (!pos_adj)
1457                         pos_adj = pos_align;
1458                 else
1459                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1460                                 pos_align;
1461                 pos_adj = frames_to_bytes(runtime, pos_adj);
1462                 if (pos_adj >= period_bytes) {
1463                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1464                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1465                         pos_adj = 0;
1466                 } else {
1467                         ofs = setup_bdle(chip, substream, azx_dev,
1468                                          &bdl, ofs, pos_adj, true);
1469                         if (ofs < 0)
1470                                 goto error;
1471                 }
1472         } else
1473                 pos_adj = 0;
1474         for (i = 0; i < periods; i++) {
1475                 if (i == periods - 1 && pos_adj)
1476                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1477                                          period_bytes - pos_adj, 0);
1478                 else
1479                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1480                                          period_bytes,
1481                                          !azx_dev->no_period_wakeup);
1482                 if (ofs < 0)
1483                         goto error;
1484         }
1485         return 0;
1486
1487  error:
1488         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1489                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1490         return -EINVAL;
1491 }
1492
1493 /* reset stream */
1494 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1495 {
1496         unsigned char val;
1497         int timeout;
1498
1499         azx_stream_clear(chip, azx_dev);
1500
1501         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1502                       SD_CTL_STREAM_RESET);
1503         udelay(3);
1504         timeout = 300;
1505         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1506                --timeout)
1507                 ;
1508         val &= ~SD_CTL_STREAM_RESET;
1509         azx_sd_writeb(azx_dev, SD_CTL, val);
1510         udelay(3);
1511
1512         timeout = 300;
1513         /* waiting for hardware to report that the stream is out of reset */
1514         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1515                --timeout)
1516                 ;
1517
1518         /* reset first position - may not be synced with hw at this time */
1519         *azx_dev->posbuf = 0;
1520 }
1521
1522 /*
1523  * set up the SD for streaming
1524  */
1525 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1526 {
1527         unsigned int val;
1528         /* make sure the run bit is zero for SD */
1529         azx_stream_clear(chip, azx_dev);
1530         /* program the stream_tag */
1531         val = azx_sd_readl(azx_dev, SD_CTL);
1532         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1533                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1534         if (!azx_snoop(chip))
1535                 val |= SD_CTL_TRAFFIC_PRIO;
1536         azx_sd_writel(azx_dev, SD_CTL, val);
1537
1538         /* program the length of samples in cyclic buffer */
1539         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1540
1541         /* program the stream format */
1542         /* this value needs to be the same as the one programmed */
1543         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1544
1545         /* program the stream LVI (last valid index) of the BDL */
1546         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1547
1548         /* program the BDL address */
1549         /* lower BDL address */
1550         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1551         /* upper BDL address */
1552         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1553
1554         /* enable the position buffer */
1555         if (chip->position_fix[0] != POS_FIX_LPIB ||
1556             chip->position_fix[1] != POS_FIX_LPIB) {
1557                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1558                         azx_writel(chip, DPLBASE,
1559                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1560         }
1561
1562         /* set the interrupt enable bits in the descriptor control register */
1563         azx_sd_writel(azx_dev, SD_CTL,
1564                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1565
1566         return 0;
1567 }
1568
1569 /*
1570  * Probe the given codec address
1571  */
1572 static int probe_codec(struct azx *chip, int addr)
1573 {
1574         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1575                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1576         unsigned int res;
1577
1578         mutex_lock(&chip->bus->cmd_mutex);
1579         chip->probing = 1;
1580         azx_send_cmd(chip->bus, cmd);
1581         res = azx_get_response(chip->bus, addr);
1582         chip->probing = 0;
1583         mutex_unlock(&chip->bus->cmd_mutex);
1584         if (res == -1)
1585                 return -EIO;
1586         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1587         return 0;
1588 }
1589
1590 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1591                                  struct hda_pcm *cpcm);
1592 static void azx_stop_chip(struct azx *chip);
1593
1594 static void azx_bus_reset(struct hda_bus *bus)
1595 {
1596         struct azx *chip = bus->private_data;
1597
1598         bus->in_reset = 1;
1599         azx_stop_chip(chip);
1600         azx_init_chip(chip, 1);
1601 #ifdef CONFIG_PM
1602         if (chip->initialized) {
1603                 struct azx_pcm *p;
1604                 list_for_each_entry(p, &chip->pcm_list, list)
1605                         snd_pcm_suspend_all(p->pcm);
1606                 snd_hda_suspend(chip->bus);
1607                 snd_hda_resume(chip->bus);
1608         }
1609 #endif
1610         bus->in_reset = 0;
1611 }
1612
1613 static int get_jackpoll_interval(struct azx *chip)
1614 {
1615         int i = jackpoll_ms[chip->dev_index];
1616         unsigned int j;
1617         if (i == 0)
1618                 return 0;
1619         if (i < 50 || i > 60000)
1620                 j = 0;
1621         else
1622                 j = msecs_to_jiffies(i);
1623         if (j == 0)
1624                 snd_printk(KERN_WARNING SFX
1625                            "jackpoll_ms value out of range: %d\n", i);
1626         return j;
1627 }
1628
1629 /*
1630  * Codec initialization
1631  */
1632
1633 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1634 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1635         [AZX_DRIVER_NVIDIA] = 8,
1636         [AZX_DRIVER_TERA] = 1,
1637 };
1638
1639 static int azx_codec_create(struct azx *chip, const char *model)
1640 {
1641         struct hda_bus_template bus_temp;
1642         int c, codecs, err;
1643         int max_slots;
1644
1645         memset(&bus_temp, 0, sizeof(bus_temp));
1646         bus_temp.private_data = chip;
1647         bus_temp.modelname = model;
1648         bus_temp.pci = chip->pci;
1649         bus_temp.ops.command = azx_send_cmd;
1650         bus_temp.ops.get_response = azx_get_response;
1651         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1652         bus_temp.ops.bus_reset = azx_bus_reset;
1653 #ifdef CONFIG_PM
1654         bus_temp.power_save = &power_save;
1655         bus_temp.ops.pm_notify = azx_power_notify;
1656 #endif
1657
1658         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1659         if (err < 0)
1660                 return err;
1661
1662         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1663                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1664                 chip->bus->needs_damn_long_delay = 1;
1665         }
1666
1667         codecs = 0;
1668         max_slots = azx_max_codecs[chip->driver_type];
1669         if (!max_slots)
1670                 max_slots = AZX_DEFAULT_CODECS;
1671
1672         /* First try to probe all given codec slots */
1673         for (c = 0; c < max_slots; c++) {
1674                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1675                         if (probe_codec(chip, c) < 0) {
1676                                 /* Some BIOSen give you wrong codec addresses
1677                                  * that don't exist
1678                                  */
1679                                 snd_printk(KERN_WARNING SFX
1680                                            "%s: Codec #%d probe error; "
1681                                            "disabling it...\n", pci_name(chip->pci), c);
1682                                 chip->codec_mask &= ~(1 << c);
1683                                 /* More badly, accessing to a non-existing
1684                                  * codec often screws up the controller chip,
1685                                  * and disturbs the further communications.
1686                                  * Thus if an error occurs during probing,
1687                                  * better to reset the controller chip to
1688                                  * get back to the sanity state.
1689                                  */
1690                                 azx_stop_chip(chip);
1691                                 azx_init_chip(chip, 1);
1692                         }
1693                 }
1694         }
1695
1696         /* AMD chipsets often cause the communication stalls upon certain
1697          * sequence like the pin-detection.  It seems that forcing the synced
1698          * access works around the stall.  Grrr...
1699          */
1700         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1701                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1702                         pci_name(chip->pci));
1703                 chip->bus->sync_write = 1;
1704                 chip->bus->allow_bus_reset = 1;
1705         }
1706
1707         /* Then create codec instances */
1708         for (c = 0; c < max_slots; c++) {
1709                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1710                         struct hda_codec *codec;
1711                         err = snd_hda_codec_new(chip->bus, c, &codec);
1712                         if (err < 0)
1713                                 continue;
1714                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1715                         codec->beep_mode = chip->beep_mode;
1716                         codecs++;
1717                 }
1718         }
1719         if (!codecs) {
1720                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1721                 return -ENXIO;
1722         }
1723         return 0;
1724 }
1725
1726 /* configure each codec instance */
1727 static int azx_codec_configure(struct azx *chip)
1728 {
1729         struct hda_codec *codec;
1730         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1731                 snd_hda_codec_configure(codec);
1732         }
1733         return 0;
1734 }
1735
1736
1737 /*
1738  * PCM support
1739  */
1740
1741 /* assign a stream for the PCM */
1742 static inline struct azx_dev *
1743 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1744 {
1745         int dev, i, nums;
1746         struct azx_dev *res = NULL;
1747         /* make a non-zero unique key for the substream */
1748         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1749                 (substream->stream + 1);
1750
1751         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1752                 dev = chip->playback_index_offset;
1753                 nums = chip->playback_streams;
1754         } else {
1755                 dev = chip->capture_index_offset;
1756                 nums = chip->capture_streams;
1757         }
1758         for (i = 0; i < nums; i++, dev++)
1759                 if (!chip->azx_dev[dev].opened) {
1760                         res = &chip->azx_dev[dev];
1761                         if (res->assigned_key == key)
1762                                 break;
1763                 }
1764         if (res) {
1765                 res->opened = 1;
1766                 res->assigned_key = key;
1767         }
1768         return res;
1769 }
1770
1771 /* release the assigned stream */
1772 static inline void azx_release_device(struct azx_dev *azx_dev)
1773 {
1774         azx_dev->opened = 0;
1775 }
1776
1777 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1778 {
1779         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1780         struct snd_pcm_substream *substream = azx_dev->substream;
1781         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1782         struct azx *chip = apcm->chip;
1783
1784         return azx_readl(chip, WALLCLK);
1785 }
1786
1787 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1788                                 bool force, cycle_t last)
1789 {
1790         struct azx_dev *azx_dev = get_azx_dev(substream);
1791         struct timecounter *tc = &azx_dev->azx_tc;
1792         struct cyclecounter *cc = &azx_dev->azx_cc;
1793         u64 nsec;
1794
1795         cc->read = azx_cc_read;
1796         cc->mask = CLOCKSOURCE_MASK(32);
1797
1798         /*
1799          * Converting from 24 MHz to ns means applying a 125/3 factor.
1800          * To avoid any saturation issues in intermediate operations,
1801          * the 125 factor is applied first. The division is applied
1802          * last after reading the timecounter value.
1803          * Applying the 1/3 factor as part of the multiplication
1804          * requires at least 20 bits for a decent precision, however
1805          * overflows occur after about 4 hours or less, not a option.
1806          */
1807
1808         cc->mult = 125; /* saturation after 195 years */
1809         cc->shift = 0;
1810
1811         nsec = 0; /* audio time is elapsed time since trigger */
1812         timecounter_init(tc, cc, nsec);
1813         if (force)
1814                 /*
1815                  * force timecounter to use predefined value,
1816                  * used for synchronized starts
1817                  */
1818                 tc->cycle_last = last;
1819 }
1820
1821 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1822                                 struct timespec *ts)
1823 {
1824         struct azx_dev *azx_dev = get_azx_dev(substream);
1825         u64 nsec;
1826
1827         nsec = timecounter_read(&azx_dev->azx_tc);
1828         nsec = div_u64(nsec, 3); /* can be optimized */
1829
1830         *ts = ns_to_timespec(nsec);
1831
1832         return 0;
1833 }
1834
1835 static struct snd_pcm_hardware azx_pcm_hw = {
1836         .info =                 (SNDRV_PCM_INFO_MMAP |
1837                                  SNDRV_PCM_INFO_INTERLEAVED |
1838                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1839                                  SNDRV_PCM_INFO_MMAP_VALID |
1840                                  /* No full-resume yet implemented */
1841                                  /* SNDRV_PCM_INFO_RESUME |*/
1842                                  SNDRV_PCM_INFO_PAUSE |
1843                                  SNDRV_PCM_INFO_SYNC_START |
1844                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1845                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1846         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1847         .rates =                SNDRV_PCM_RATE_48000,
1848         .rate_min =             48000,
1849         .rate_max =             48000,
1850         .channels_min =         2,
1851         .channels_max =         2,
1852         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1853         .period_bytes_min =     128,
1854         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1855         .periods_min =          2,
1856         .periods_max =          AZX_MAX_FRAG,
1857         .fifo_size =            0,
1858 };
1859
1860 static int azx_pcm_open(struct snd_pcm_substream *substream)
1861 {
1862         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1863         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1864         struct azx *chip = apcm->chip;
1865         struct azx_dev *azx_dev;
1866         struct snd_pcm_runtime *runtime = substream->runtime;
1867         unsigned long flags;
1868         int err;
1869         int buff_step;
1870
1871         mutex_lock(&chip->open_mutex);
1872         azx_dev = azx_assign_device(chip, substream);
1873         if (azx_dev == NULL) {
1874                 mutex_unlock(&chip->open_mutex);
1875                 return -EBUSY;
1876         }
1877         runtime->hw = azx_pcm_hw;
1878         runtime->hw.channels_min = hinfo->channels_min;
1879         runtime->hw.channels_max = hinfo->channels_max;
1880         runtime->hw.formats = hinfo->formats;
1881         runtime->hw.rates = hinfo->rates;
1882         snd_pcm_limit_hw_rates(runtime);
1883         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1884
1885         /* avoid wrap-around with wall-clock */
1886         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1887                                 20,
1888                                 178000000);
1889
1890         if (chip->align_buffer_size)
1891                 /* constrain buffer sizes to be multiple of 128
1892                    bytes. This is more efficient in terms of memory
1893                    access but isn't required by the HDA spec and
1894                    prevents users from specifying exact period/buffer
1895                    sizes. For example for 44.1kHz, a period size set
1896                    to 20ms will be rounded to 19.59ms. */
1897                 buff_step = 128;
1898         else
1899                 /* Don't enforce steps on buffer sizes, still need to
1900                    be multiple of 4 bytes (HDA spec). Tested on Intel
1901                    HDA controllers, may not work on all devices where
1902                    option needs to be disabled */
1903                 buff_step = 4;
1904
1905         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1906                                    buff_step);
1907         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1908                                    buff_step);
1909         snd_hda_power_up_d3wait(apcm->codec);
1910         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1911         if (err < 0) {
1912                 azx_release_device(azx_dev);
1913                 snd_hda_power_down(apcm->codec);
1914                 mutex_unlock(&chip->open_mutex);
1915                 return err;
1916         }
1917         snd_pcm_limit_hw_rates(runtime);
1918         /* sanity check */
1919         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1920             snd_BUG_ON(!runtime->hw.channels_max) ||
1921             snd_BUG_ON(!runtime->hw.formats) ||
1922             snd_BUG_ON(!runtime->hw.rates)) {
1923                 azx_release_device(azx_dev);
1924                 hinfo->ops.close(hinfo, apcm->codec, substream);
1925                 snd_hda_power_down(apcm->codec);
1926                 mutex_unlock(&chip->open_mutex);
1927                 return -EINVAL;
1928         }
1929
1930         /* disable WALLCLOCK timestamps for capture streams
1931            until we figure out how to handle digital inputs */
1932         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1933                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1934
1935         spin_lock_irqsave(&chip->reg_lock, flags);
1936         azx_dev->substream = substream;
1937         azx_dev->running = 0;
1938         spin_unlock_irqrestore(&chip->reg_lock, flags);
1939
1940         runtime->private_data = azx_dev;
1941         snd_pcm_set_sync(substream);
1942         mutex_unlock(&chip->open_mutex);
1943         return 0;
1944 }
1945
1946 static int azx_pcm_close(struct snd_pcm_substream *substream)
1947 {
1948         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1949         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1950         struct azx *chip = apcm->chip;
1951         struct azx_dev *azx_dev = get_azx_dev(substream);
1952         unsigned long flags;
1953
1954         mutex_lock(&chip->open_mutex);
1955         spin_lock_irqsave(&chip->reg_lock, flags);
1956         azx_dev->substream = NULL;
1957         azx_dev->running = 0;
1958         spin_unlock_irqrestore(&chip->reg_lock, flags);
1959         azx_release_device(azx_dev);
1960         hinfo->ops.close(hinfo, apcm->codec, substream);
1961         snd_hda_power_down(apcm->codec);
1962         mutex_unlock(&chip->open_mutex);
1963         return 0;
1964 }
1965
1966 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1967                              struct snd_pcm_hw_params *hw_params)
1968 {
1969         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1970         struct azx *chip = apcm->chip;
1971         struct snd_pcm_runtime *runtime = substream->runtime;
1972         struct azx_dev *azx_dev = get_azx_dev(substream);
1973         int ret;
1974
1975         mark_runtime_wc(chip, azx_dev, runtime, false);
1976         azx_dev->bufsize = 0;
1977         azx_dev->period_bytes = 0;
1978         azx_dev->format_val = 0;
1979         ret = snd_pcm_lib_malloc_pages(substream,
1980                                         params_buffer_bytes(hw_params));
1981         if (ret < 0)
1982                 return ret;
1983         mark_runtime_wc(chip, azx_dev, runtime, true);
1984         return ret;
1985 }
1986
1987 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1988 {
1989         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1990         struct azx_dev *azx_dev = get_azx_dev(substream);
1991         struct azx *chip = apcm->chip;
1992         struct snd_pcm_runtime *runtime = substream->runtime;
1993         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1994
1995         /* reset BDL address */
1996         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1997         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1998         azx_sd_writel(azx_dev, SD_CTL, 0);
1999         azx_dev->bufsize = 0;
2000         azx_dev->period_bytes = 0;
2001         azx_dev->format_val = 0;
2002
2003         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2004
2005         mark_runtime_wc(chip, azx_dev, runtime, false);
2006         return snd_pcm_lib_free_pages(substream);
2007 }
2008
2009 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2010 {
2011         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2012         struct azx *chip = apcm->chip;
2013         struct azx_dev *azx_dev = get_azx_dev(substream);
2014         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2015         struct snd_pcm_runtime *runtime = substream->runtime;
2016         unsigned int bufsize, period_bytes, format_val, stream_tag;
2017         int err;
2018         struct hda_spdif_out *spdif =
2019                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2020         unsigned short ctls = spdif ? spdif->ctls : 0;
2021
2022         azx_stream_reset(chip, azx_dev);
2023         format_val = snd_hda_calc_stream_format(runtime->rate,
2024                                                 runtime->channels,
2025                                                 runtime->format,
2026                                                 hinfo->maxbps,
2027                                                 ctls);
2028         if (!format_val) {
2029                 snd_printk(KERN_ERR SFX
2030                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2031                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2032                 return -EINVAL;
2033         }
2034
2035         bufsize = snd_pcm_lib_buffer_bytes(substream);
2036         period_bytes = snd_pcm_lib_period_bytes(substream);
2037
2038         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2039                     pci_name(chip->pci), bufsize, format_val);
2040
2041         if (bufsize != azx_dev->bufsize ||
2042             period_bytes != azx_dev->period_bytes ||
2043             format_val != azx_dev->format_val ||
2044             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2045                 azx_dev->bufsize = bufsize;
2046                 azx_dev->period_bytes = period_bytes;
2047                 azx_dev->format_val = format_val;
2048                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2049                 err = azx_setup_periods(chip, substream, azx_dev);
2050                 if (err < 0)
2051                         return err;
2052         }
2053
2054         /* wallclk has 24Mhz clock source */
2055         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2056                                                 runtime->rate) * 1000);
2057         azx_setup_controller(chip, azx_dev);
2058         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2059                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2060         else
2061                 azx_dev->fifo_size = 0;
2062
2063         stream_tag = azx_dev->stream_tag;
2064         /* CA-IBG chips need the playback stream starting from 1 */
2065         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2066             stream_tag > chip->capture_streams)
2067                 stream_tag -= chip->capture_streams;
2068         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2069                                      azx_dev->format_val, substream);
2070 }
2071
2072 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2073 {
2074         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2075         struct azx *chip = apcm->chip;
2076         struct azx_dev *azx_dev;
2077         struct snd_pcm_substream *s;
2078         int rstart = 0, start, nsync = 0, sbits = 0;
2079         int nwait, timeout;
2080
2081         azx_dev = get_azx_dev(substream);
2082         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2083
2084         switch (cmd) {
2085         case SNDRV_PCM_TRIGGER_START:
2086                 rstart = 1;
2087         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2088         case SNDRV_PCM_TRIGGER_RESUME:
2089                 start = 1;
2090                 break;
2091         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2092         case SNDRV_PCM_TRIGGER_SUSPEND:
2093         case SNDRV_PCM_TRIGGER_STOP:
2094                 start = 0;
2095                 break;
2096         default:
2097                 return -EINVAL;
2098         }
2099
2100         snd_pcm_group_for_each_entry(s, substream) {
2101                 if (s->pcm->card != substream->pcm->card)
2102                         continue;
2103                 azx_dev = get_azx_dev(s);
2104                 sbits |= 1 << azx_dev->index;
2105                 nsync++;
2106                 snd_pcm_trigger_done(s, substream);
2107         }
2108
2109         spin_lock(&chip->reg_lock);
2110
2111         /* first, set SYNC bits of corresponding streams */
2112         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2113                 azx_writel(chip, OLD_SSYNC,
2114                         azx_readl(chip, OLD_SSYNC) | sbits);
2115         else
2116                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2117
2118         snd_pcm_group_for_each_entry(s, substream) {
2119                 if (s->pcm->card != substream->pcm->card)
2120                         continue;
2121                 azx_dev = get_azx_dev(s);
2122                 if (start) {
2123                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2124                         if (!rstart)
2125                                 azx_dev->start_wallclk -=
2126                                                 azx_dev->period_wallclk;
2127                         azx_stream_start(chip, azx_dev);
2128                 } else {
2129                         azx_stream_stop(chip, azx_dev);
2130                 }
2131                 azx_dev->running = start;
2132         }
2133         spin_unlock(&chip->reg_lock);
2134         if (start) {
2135                 /* wait until all FIFOs get ready */
2136                 for (timeout = 5000; timeout; timeout--) {
2137                         nwait = 0;
2138                         snd_pcm_group_for_each_entry(s, substream) {
2139                                 if (s->pcm->card != substream->pcm->card)
2140                                         continue;
2141                                 azx_dev = get_azx_dev(s);
2142                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2143                                       SD_STS_FIFO_READY))
2144                                         nwait++;
2145                         }
2146                         if (!nwait)
2147                                 break;
2148                         cpu_relax();
2149                 }
2150         } else {
2151                 /* wait until all RUN bits are cleared */
2152                 for (timeout = 5000; timeout; timeout--) {
2153                         nwait = 0;
2154                         snd_pcm_group_for_each_entry(s, substream) {
2155                                 if (s->pcm->card != substream->pcm->card)
2156                                         continue;
2157                                 azx_dev = get_azx_dev(s);
2158                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2159                                     SD_CTL_DMA_START)
2160                                         nwait++;
2161                         }
2162                         if (!nwait)
2163                                 break;
2164                         cpu_relax();
2165                 }
2166         }
2167         spin_lock(&chip->reg_lock);
2168         /* reset SYNC bits */
2169         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2170                 azx_writel(chip, OLD_SSYNC,
2171                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2172         else
2173                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2174         if (start) {
2175                 azx_timecounter_init(substream, 0, 0);
2176                 if (nsync > 1) {
2177                         cycle_t cycle_last;
2178
2179                         /* same start cycle for master and group */
2180                         azx_dev = get_azx_dev(substream);
2181                         cycle_last = azx_dev->azx_tc.cycle_last;
2182
2183                         snd_pcm_group_for_each_entry(s, substream) {
2184                                 if (s->pcm->card != substream->pcm->card)
2185                                         continue;
2186                                 azx_timecounter_init(s, 1, cycle_last);
2187                         }
2188                 }
2189         }
2190         spin_unlock(&chip->reg_lock);
2191         return 0;
2192 }
2193
2194 /* get the current DMA position with correction on VIA chips */
2195 static unsigned int azx_via_get_position(struct azx *chip,
2196                                          struct azx_dev *azx_dev)
2197 {
2198         unsigned int link_pos, mini_pos, bound_pos;
2199         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2200         unsigned int fifo_size;
2201
2202         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2203         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2204                 /* Playback, no problem using link position */
2205                 return link_pos;
2206         }
2207
2208         /* Capture */
2209         /* For new chipset,
2210          * use mod to get the DMA position just like old chipset
2211          */
2212         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2213         mod_dma_pos %= azx_dev->period_bytes;
2214
2215         /* azx_dev->fifo_size can't get FIFO size of in stream.
2216          * Get from base address + offset.
2217          */
2218         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2219
2220         if (azx_dev->insufficient) {
2221                 /* Link position never gather than FIFO size */
2222                 if (link_pos <= fifo_size)
2223                         return 0;
2224
2225                 azx_dev->insufficient = 0;
2226         }
2227
2228         if (link_pos <= fifo_size)
2229                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2230         else
2231                 mini_pos = link_pos - fifo_size;
2232
2233         /* Find nearest previous boudary */
2234         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2235         mod_link_pos = link_pos % azx_dev->period_bytes;
2236         if (mod_link_pos >= fifo_size)
2237                 bound_pos = link_pos - mod_link_pos;
2238         else if (mod_dma_pos >= mod_mini_pos)
2239                 bound_pos = mini_pos - mod_mini_pos;
2240         else {
2241                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2242                 if (bound_pos >= azx_dev->bufsize)
2243                         bound_pos = 0;
2244         }
2245
2246         /* Calculate real DMA position we want */
2247         return bound_pos + mod_dma_pos;
2248 }
2249
2250 static unsigned int azx_get_position(struct azx *chip,
2251                                      struct azx_dev *azx_dev,
2252                                      bool with_check)
2253 {
2254         unsigned int pos;
2255         int stream = azx_dev->substream->stream;
2256         int delay = 0;
2257
2258         switch (chip->position_fix[stream]) {
2259         case POS_FIX_LPIB:
2260                 /* read LPIB */
2261                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2262                 break;
2263         case POS_FIX_VIACOMBO:
2264                 pos = azx_via_get_position(chip, azx_dev);
2265                 break;
2266         default:
2267                 /* use the position buffer */
2268                 pos = le32_to_cpu(*azx_dev->posbuf);
2269                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2270                         if (!pos || pos == (u32)-1) {
2271                                 printk(KERN_WARNING
2272                                        "hda-intel: Invalid position buffer, "
2273                                        "using LPIB read method instead.\n");
2274                                 chip->position_fix[stream] = POS_FIX_LPIB;
2275                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2276                         } else
2277                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2278                 }
2279                 break;
2280         }
2281
2282         if (pos >= azx_dev->bufsize)
2283                 pos = 0;
2284
2285         /* calculate runtime delay from LPIB */
2286         if (azx_dev->substream->runtime &&
2287             chip->position_fix[stream] == POS_FIX_POSBUF &&
2288             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2289                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2290                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2291                         delay = pos - lpib_pos;
2292                 else
2293                         delay = lpib_pos - pos;
2294                 if (delay < 0)
2295                         delay += azx_dev->bufsize;
2296                 if (delay >= azx_dev->period_bytes) {
2297                         snd_printk(KERN_WARNING SFX
2298                                    "%s: Unstable LPIB (%d >= %d); "
2299                                    "disabling LPIB delay counting\n",
2300                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2301                         delay = 0;
2302                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2303                 }
2304                 azx_dev->substream->runtime->delay =
2305                         bytes_to_frames(azx_dev->substream->runtime, delay);
2306         }
2307         trace_azx_get_position(chip, azx_dev, pos, delay);
2308         return pos;
2309 }
2310
2311 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2312 {
2313         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2314         struct azx *chip = apcm->chip;
2315         struct azx_dev *azx_dev = get_azx_dev(substream);
2316         return bytes_to_frames(substream->runtime,
2317                                azx_get_position(chip, azx_dev, false));
2318 }
2319
2320 /*
2321  * Check whether the current DMA position is acceptable for updating
2322  * periods.  Returns non-zero if it's OK.
2323  *
2324  * Many HD-audio controllers appear pretty inaccurate about
2325  * the update-IRQ timing.  The IRQ is issued before actually the
2326  * data is processed.  So, we need to process it afterwords in a
2327  * workqueue.
2328  */
2329 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2330 {
2331         u32 wallclk;
2332         unsigned int pos;
2333
2334         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2335         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2336                 return -1;      /* bogus (too early) interrupt */
2337
2338         pos = azx_get_position(chip, azx_dev, true);
2339
2340         if (WARN_ONCE(!azx_dev->period_bytes,
2341                       "hda-intel: zero azx_dev->period_bytes"))
2342                 return -1; /* this shouldn't happen! */
2343         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2344             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2345                 /* NG - it's below the first next period boundary */
2346                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2347         azx_dev->start_wallclk += wallclk;
2348         return 1; /* OK, it's fine */
2349 }
2350
2351 /*
2352  * The work for pending PCM period updates.
2353  */
2354 static void azx_irq_pending_work(struct work_struct *work)
2355 {
2356         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2357         int i, pending, ok;
2358
2359         if (!chip->irq_pending_warned) {
2360                 printk(KERN_WARNING
2361                        "hda-intel: IRQ timing workaround is activated "
2362                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2363                        chip->card->number);
2364                 chip->irq_pending_warned = 1;
2365         }
2366
2367         for (;;) {
2368                 pending = 0;
2369                 spin_lock_irq(&chip->reg_lock);
2370                 for (i = 0; i < chip->num_streams; i++) {
2371                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2372                         if (!azx_dev->irq_pending ||
2373                             !azx_dev->substream ||
2374                             !azx_dev->running)
2375                                 continue;
2376                         ok = azx_position_ok(chip, azx_dev);
2377                         if (ok > 0) {
2378                                 azx_dev->irq_pending = 0;
2379                                 spin_unlock(&chip->reg_lock);
2380                                 snd_pcm_period_elapsed(azx_dev->substream);
2381                                 spin_lock(&chip->reg_lock);
2382                         } else if (ok < 0) {
2383                                 pending = 0;    /* too early */
2384                         } else
2385                                 pending++;
2386                 }
2387                 spin_unlock_irq(&chip->reg_lock);
2388                 if (!pending)
2389                         return;
2390                 msleep(1);
2391         }
2392 }
2393
2394 /* clear irq_pending flags and assure no on-going workq */
2395 static void azx_clear_irq_pending(struct azx *chip)
2396 {
2397         int i;
2398
2399         spin_lock_irq(&chip->reg_lock);
2400         for (i = 0; i < chip->num_streams; i++)
2401                 chip->azx_dev[i].irq_pending = 0;
2402         spin_unlock_irq(&chip->reg_lock);
2403 }
2404
2405 #ifdef CONFIG_X86
2406 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2407                         struct vm_area_struct *area)
2408 {
2409         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2410         struct azx *chip = apcm->chip;
2411         if (!azx_snoop(chip))
2412                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2413         return snd_pcm_lib_default_mmap(substream, area);
2414 }
2415 #else
2416 #define azx_pcm_mmap    NULL
2417 #endif
2418
2419 static struct snd_pcm_ops azx_pcm_ops = {
2420         .open = azx_pcm_open,
2421         .close = azx_pcm_close,
2422         .ioctl = snd_pcm_lib_ioctl,
2423         .hw_params = azx_pcm_hw_params,
2424         .hw_free = azx_pcm_hw_free,
2425         .prepare = azx_pcm_prepare,
2426         .trigger = azx_pcm_trigger,
2427         .pointer = azx_pcm_pointer,
2428         .wall_clock =  azx_get_wallclock_tstamp,
2429         .mmap = azx_pcm_mmap,
2430         .page = snd_pcm_sgbuf_ops_page,
2431 };
2432
2433 static void azx_pcm_free(struct snd_pcm *pcm)
2434 {
2435         struct azx_pcm *apcm = pcm->private_data;
2436         if (apcm) {
2437                 list_del(&apcm->list);
2438                 kfree(apcm);
2439         }
2440 }
2441
2442 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2443
2444 static int
2445 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2446                       struct hda_pcm *cpcm)
2447 {
2448         struct azx *chip = bus->private_data;
2449         struct snd_pcm *pcm;
2450         struct azx_pcm *apcm;
2451         int pcm_dev = cpcm->device;
2452         unsigned int size;
2453         int s, err;
2454
2455         list_for_each_entry(apcm, &chip->pcm_list, list) {
2456                 if (apcm->pcm->device == pcm_dev) {
2457                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2458                                    pci_name(chip->pci), pcm_dev);
2459                         return -EBUSY;
2460                 }
2461         }
2462         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2463                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2464                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2465                           &pcm);
2466         if (err < 0)
2467                 return err;
2468         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2469         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2470         if (apcm == NULL)
2471                 return -ENOMEM;
2472         apcm->chip = chip;
2473         apcm->pcm = pcm;
2474         apcm->codec = codec;
2475         pcm->private_data = apcm;
2476         pcm->private_free = azx_pcm_free;
2477         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2478                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2479         list_add_tail(&apcm->list, &chip->pcm_list);
2480         cpcm->pcm = pcm;
2481         for (s = 0; s < 2; s++) {
2482                 apcm->hinfo[s] = &cpcm->stream[s];
2483                 if (cpcm->stream[s].substreams)
2484                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2485         }
2486         /* buffer pre-allocation */
2487         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2488         if (size > MAX_PREALLOC_SIZE)
2489                 size = MAX_PREALLOC_SIZE;
2490         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2491                                               snd_dma_pci_data(chip->pci),
2492                                               size, MAX_PREALLOC_SIZE);
2493         return 0;
2494 }
2495
2496 /*
2497  * mixer creation - all stuff is implemented in hda module
2498  */
2499 static int azx_mixer_create(struct azx *chip)
2500 {
2501         return snd_hda_build_controls(chip->bus);
2502 }
2503
2504
2505 /*
2506  * initialize SD streams
2507  */
2508 static int azx_init_stream(struct azx *chip)
2509 {
2510         int i;
2511
2512         /* initialize each stream (aka device)
2513          * assign the starting bdl address to each stream (device)
2514          * and initialize
2515          */
2516         for (i = 0; i < chip->num_streams; i++) {
2517                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2518                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2519                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2520                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2521                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2522                 azx_dev->sd_int_sta_mask = 1 << i;
2523                 /* stream tag: must be non-zero and unique */
2524                 azx_dev->index = i;
2525                 azx_dev->stream_tag = i + 1;
2526         }
2527
2528         return 0;
2529 }
2530
2531 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2532 {
2533         if (request_irq(chip->pci->irq, azx_interrupt,
2534                         chip->msi ? 0 : IRQF_SHARED,
2535                         KBUILD_MODNAME, chip)) {
2536                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2537                        "disabling device\n", chip->pci->irq);
2538                 if (do_disconnect)
2539                         snd_card_disconnect(chip->card);
2540                 return -1;
2541         }
2542         chip->irq = chip->pci->irq;
2543         pci_intx(chip->pci, !chip->msi);
2544         return 0;
2545 }
2546
2547
2548 static void azx_stop_chip(struct azx *chip)
2549 {
2550         if (!chip->initialized)
2551                 return;
2552
2553         /* disable interrupts */
2554         azx_int_disable(chip);
2555         azx_int_clear(chip);
2556
2557         /* disable CORB/RIRB */
2558         azx_free_cmd_io(chip);
2559
2560         /* disable position buffer */
2561         azx_writel(chip, DPLBASE, 0);
2562         azx_writel(chip, DPUBASE, 0);
2563
2564         chip->initialized = 0;
2565 }
2566
2567 #ifdef CONFIG_PM
2568 /* power-up/down the controller */
2569 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2570 {
2571         struct azx *chip = bus->private_data;
2572
2573         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2574                 return;
2575
2576         if (power_up)
2577                 pm_runtime_get_sync(&chip->pci->dev);
2578         else
2579                 pm_runtime_put_sync(&chip->pci->dev);
2580 }
2581
2582 static DEFINE_MUTEX(card_list_lock);
2583 static LIST_HEAD(card_list);
2584
2585 static void azx_add_card_list(struct azx *chip)
2586 {
2587         mutex_lock(&card_list_lock);
2588         list_add(&chip->list, &card_list);
2589         mutex_unlock(&card_list_lock);
2590 }
2591
2592 static void azx_del_card_list(struct azx *chip)
2593 {
2594         mutex_lock(&card_list_lock);
2595         list_del_init(&chip->list);
2596         mutex_unlock(&card_list_lock);
2597 }
2598
2599 /* trigger power-save check at writing parameter */
2600 static int param_set_xint(const char *val, const struct kernel_param *kp)
2601 {
2602         struct azx *chip;
2603         struct hda_codec *c;
2604         int prev = power_save;
2605         int ret = param_set_int(val, kp);
2606
2607         if (ret || prev == power_save)
2608                 return ret;
2609
2610         mutex_lock(&card_list_lock);
2611         list_for_each_entry(chip, &card_list, list) {
2612                 if (!chip->bus || chip->disabled)
2613                         continue;
2614                 list_for_each_entry(c, &chip->bus->codec_list, list)
2615                         snd_hda_power_sync(c);
2616         }
2617         mutex_unlock(&card_list_lock);
2618         return 0;
2619 }
2620 #else
2621 #define azx_add_card_list(chip) /* NOP */
2622 #define azx_del_card_list(chip) /* NOP */
2623 #endif /* CONFIG_PM */
2624
2625 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2626 /*
2627  * power management
2628  */
2629 static int azx_suspend(struct device *dev)
2630 {
2631         struct pci_dev *pci = to_pci_dev(dev);
2632         struct snd_card *card = dev_get_drvdata(dev);
2633         struct azx *chip = card->private_data;
2634         struct azx_pcm *p;
2635
2636         if (chip->disabled)
2637                 return 0;
2638
2639         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2640         azx_clear_irq_pending(chip);
2641         list_for_each_entry(p, &chip->pcm_list, list)
2642                 snd_pcm_suspend_all(p->pcm);
2643         if (chip->initialized)
2644                 snd_hda_suspend(chip->bus);
2645         azx_stop_chip(chip);
2646         if (chip->irq >= 0) {
2647                 free_irq(chip->irq, chip);
2648                 chip->irq = -1;
2649         }
2650         if (chip->msi)
2651                 pci_disable_msi(chip->pci);
2652         pci_disable_device(pci);
2653         pci_save_state(pci);
2654         pci_set_power_state(pci, PCI_D3hot);
2655         return 0;
2656 }
2657
2658 static int azx_resume(struct device *dev)
2659 {
2660         struct pci_dev *pci = to_pci_dev(dev);
2661         struct snd_card *card = dev_get_drvdata(dev);
2662         struct azx *chip = card->private_data;
2663
2664         if (chip->disabled)
2665                 return 0;
2666
2667         pci_set_power_state(pci, PCI_D0);
2668         pci_restore_state(pci);
2669         if (pci_enable_device(pci) < 0) {
2670                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2671                        "disabling device\n");
2672                 snd_card_disconnect(card);
2673                 return -EIO;
2674         }
2675         pci_set_master(pci);
2676         if (chip->msi)
2677                 if (pci_enable_msi(pci) < 0)
2678                         chip->msi = 0;
2679         if (azx_acquire_irq(chip, 1) < 0)
2680                 return -EIO;
2681         azx_init_pci(chip);
2682
2683         azx_init_chip(chip, 1);
2684
2685         snd_hda_resume(chip->bus);
2686         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2687         return 0;
2688 }
2689 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2690
2691 #ifdef CONFIG_PM_RUNTIME
2692 static int azx_runtime_suspend(struct device *dev)
2693 {
2694         struct snd_card *card = dev_get_drvdata(dev);
2695         struct azx *chip = card->private_data;
2696
2697         azx_stop_chip(chip);
2698         azx_clear_irq_pending(chip);
2699         return 0;
2700 }
2701
2702 static int azx_runtime_resume(struct device *dev)
2703 {
2704         struct snd_card *card = dev_get_drvdata(dev);
2705         struct azx *chip = card->private_data;
2706
2707         azx_init_pci(chip);
2708         azx_init_chip(chip, 1);
2709         return 0;
2710 }
2711
2712 static int azx_runtime_idle(struct device *dev)
2713 {
2714         struct snd_card *card = dev_get_drvdata(dev);
2715         struct azx *chip = card->private_data;
2716
2717         if (!power_save_controller ||
2718             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2719                 return -EBUSY;
2720
2721         return 0;
2722 }
2723
2724 #endif /* CONFIG_PM_RUNTIME */
2725
2726 #ifdef CONFIG_PM
2727 static const struct dev_pm_ops azx_pm = {
2728         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2729         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2730 };
2731
2732 #define AZX_PM_OPS      &azx_pm
2733 #else
2734 #define AZX_PM_OPS      NULL
2735 #endif /* CONFIG_PM */
2736
2737
2738 /*
2739  * reboot notifier for hang-up problem at power-down
2740  */
2741 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2742 {
2743         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2744         snd_hda_bus_reboot_notify(chip->bus);
2745         azx_stop_chip(chip);
2746         return NOTIFY_OK;
2747 }
2748
2749 static void azx_notifier_register(struct azx *chip)
2750 {
2751         chip->reboot_notifier.notifier_call = azx_halt;
2752         register_reboot_notifier(&chip->reboot_notifier);
2753 }
2754
2755 static void azx_notifier_unregister(struct azx *chip)
2756 {
2757         if (chip->reboot_notifier.notifier_call)
2758                 unregister_reboot_notifier(&chip->reboot_notifier);
2759 }
2760
2761 static int azx_first_init(struct azx *chip);
2762 static int azx_probe_continue(struct azx *chip);
2763
2764 #ifdef SUPPORT_VGA_SWITCHEROO
2765 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2766
2767 static void azx_vs_set_state(struct pci_dev *pci,
2768                              enum vga_switcheroo_state state)
2769 {
2770         struct snd_card *card = pci_get_drvdata(pci);
2771         struct azx *chip = card->private_data;
2772         bool disabled;
2773
2774         wait_for_completion(&chip->probe_wait);
2775         if (chip->init_failed)
2776                 return;
2777
2778         disabled = (state == VGA_SWITCHEROO_OFF);
2779         if (chip->disabled == disabled)
2780                 return;
2781
2782         if (!chip->bus) {
2783                 chip->disabled = disabled;
2784                 if (!disabled) {
2785                         snd_printk(KERN_INFO SFX
2786                                    "%s: Start delayed initialization\n",
2787                                    pci_name(chip->pci));
2788                         if (azx_first_init(chip) < 0 ||
2789                             azx_probe_continue(chip) < 0) {
2790                                 snd_printk(KERN_ERR SFX
2791                                            "%s: initialization error\n",
2792                                            pci_name(chip->pci));
2793                                 chip->init_failed = true;
2794                         }
2795                 }
2796         } else {
2797                 snd_printk(KERN_INFO SFX
2798                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2799                            disabled ? "Disabling" : "Enabling");
2800                 if (disabled) {
2801                         azx_suspend(&pci->dev);
2802                         chip->disabled = true;
2803                         if (snd_hda_lock_devices(chip->bus))
2804                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2805                                            pci_name(chip->pci));
2806                 } else {
2807                         snd_hda_unlock_devices(chip->bus);
2808                         chip->disabled = false;
2809                         azx_resume(&pci->dev);
2810                 }
2811         }
2812 }
2813
2814 static bool azx_vs_can_switch(struct pci_dev *pci)
2815 {
2816         struct snd_card *card = pci_get_drvdata(pci);
2817         struct azx *chip = card->private_data;
2818
2819         wait_for_completion(&chip->probe_wait);
2820         if (chip->init_failed)
2821                 return false;
2822         if (chip->disabled || !chip->bus)
2823                 return true;
2824         if (snd_hda_lock_devices(chip->bus))
2825                 return false;
2826         snd_hda_unlock_devices(chip->bus);
2827         return true;
2828 }
2829
2830 static void init_vga_switcheroo(struct azx *chip)
2831 {
2832         struct pci_dev *p = get_bound_vga(chip->pci);
2833         if (p) {
2834                 snd_printk(KERN_INFO SFX
2835                            "%s: Handle VGA-switcheroo audio client\n",
2836                            pci_name(chip->pci));
2837                 chip->use_vga_switcheroo = 1;
2838                 pci_dev_put(p);
2839         }
2840 }
2841
2842 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2843         .set_gpu_state = azx_vs_set_state,
2844         .can_switch = azx_vs_can_switch,
2845 };
2846
2847 static int register_vga_switcheroo(struct azx *chip)
2848 {
2849         int err;
2850
2851         if (!chip->use_vga_switcheroo)
2852                 return 0;
2853         /* FIXME: currently only handling DIS controller
2854          * is there any machine with two switchable HDMI audio controllers?
2855          */
2856         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2857                                                     VGA_SWITCHEROO_DIS,
2858                                                     chip->bus != NULL);
2859         if (err < 0)
2860                 return err;
2861         chip->vga_switcheroo_registered = 1;
2862         return 0;
2863 }
2864 #else
2865 #define init_vga_switcheroo(chip)               /* NOP */
2866 #define register_vga_switcheroo(chip)           0
2867 #define check_hdmi_disabled(pci)        false
2868 #endif /* SUPPORT_VGA_SWITCHER */
2869
2870 /*
2871  * destructor
2872  */
2873 static int azx_free(struct azx *chip)
2874 {
2875         int i;
2876
2877         azx_del_card_list(chip);
2878
2879         azx_notifier_unregister(chip);
2880
2881         chip->init_failed = 1; /* to be sure */
2882         complete_all(&chip->probe_wait);
2883
2884         if (use_vga_switcheroo(chip)) {
2885                 if (chip->disabled && chip->bus)
2886                         snd_hda_unlock_devices(chip->bus);
2887                 if (chip->vga_switcheroo_registered)
2888                         vga_switcheroo_unregister_client(chip->pci);
2889         }
2890
2891         if (chip->initialized) {
2892                 azx_clear_irq_pending(chip);
2893                 for (i = 0; i < chip->num_streams; i++)
2894                         azx_stream_stop(chip, &chip->azx_dev[i]);
2895                 azx_stop_chip(chip);
2896         }
2897
2898         if (chip->irq >= 0)
2899                 free_irq(chip->irq, (void*)chip);
2900         if (chip->msi)
2901                 pci_disable_msi(chip->pci);
2902         if (chip->remap_addr)
2903                 iounmap(chip->remap_addr);
2904
2905         if (chip->azx_dev) {
2906                 for (i = 0; i < chip->num_streams; i++)
2907                         if (chip->azx_dev[i].bdl.area) {
2908                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2909                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2910                         }
2911         }
2912         if (chip->rb.area) {
2913                 mark_pages_wc(chip, &chip->rb, false);
2914                 snd_dma_free_pages(&chip->rb);
2915         }
2916         if (chip->posbuf.area) {
2917                 mark_pages_wc(chip, &chip->posbuf, false);
2918                 snd_dma_free_pages(&chip->posbuf);
2919         }
2920         if (chip->region_requested)
2921                 pci_release_regions(chip->pci);
2922         pci_disable_device(chip->pci);
2923         kfree(chip->azx_dev);
2924 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2925         if (chip->fw)
2926                 release_firmware(chip->fw);
2927 #endif
2928         kfree(chip);
2929
2930         return 0;
2931 }
2932
2933 static int azx_dev_free(struct snd_device *device)
2934 {
2935         return azx_free(device->device_data);
2936 }
2937
2938 #ifdef SUPPORT_VGA_SWITCHEROO
2939 /*
2940  * Check of disabled HDMI controller by vga-switcheroo
2941  */
2942 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2943 {
2944         struct pci_dev *p;
2945
2946         /* check only discrete GPU */
2947         switch (pci->vendor) {
2948         case PCI_VENDOR_ID_ATI:
2949         case PCI_VENDOR_ID_AMD:
2950         case PCI_VENDOR_ID_NVIDIA:
2951                 if (pci->devfn == 1) {
2952                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2953                                                         pci->bus->number, 0);
2954                         if (p) {
2955                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2956                                         return p;
2957                                 pci_dev_put(p);
2958                         }
2959                 }
2960                 break;
2961         }
2962         return NULL;
2963 }
2964
2965 static bool check_hdmi_disabled(struct pci_dev *pci)
2966 {
2967         bool vga_inactive = false;
2968         struct pci_dev *p = get_bound_vga(pci);
2969
2970         if (p) {
2971                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2972                         vga_inactive = true;
2973                 pci_dev_put(p);
2974         }
2975         return vga_inactive;
2976 }
2977 #endif /* SUPPORT_VGA_SWITCHEROO */
2978
2979 /*
2980  * white/black-listing for position_fix
2981  */
2982 static struct snd_pci_quirk position_fix_list[] = {
2983         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2984         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2985         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2986         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2987         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2988         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2989         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2990         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2991         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2992         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2993         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2994         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2995         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2996         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2997         {}
2998 };
2999
3000 static int check_position_fix(struct azx *chip, int fix)
3001 {
3002         const struct snd_pci_quirk *q;
3003
3004         switch (fix) {
3005         case POS_FIX_AUTO:
3006         case POS_FIX_LPIB:
3007         case POS_FIX_POSBUF:
3008         case POS_FIX_VIACOMBO:
3009         case POS_FIX_COMBO:
3010                 return fix;
3011         }
3012
3013         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3014         if (q) {
3015                 printk(KERN_INFO
3016                        "hda_intel: position_fix set to %d "
3017                        "for device %04x:%04x\n",
3018                        q->value, q->subvendor, q->subdevice);
3019                 return q->value;
3020         }
3021
3022         /* Check VIA/ATI HD Audio Controller exist */
3023         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3024                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3025                 return POS_FIX_VIACOMBO;
3026         }
3027         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3028                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3029                 return POS_FIX_LPIB;
3030         }
3031         return POS_FIX_AUTO;
3032 }
3033
3034 /*
3035  * black-lists for probe_mask
3036  */
3037 static struct snd_pci_quirk probe_mask_list[] = {
3038         /* Thinkpad often breaks the controller communication when accessing
3039          * to the non-working (or non-existing) modem codec slot.
3040          */
3041         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3042         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3043         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3044         /* broken BIOS */
3045         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3046         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3047         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3048         /* forced codec slots */
3049         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3050         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3051         /* WinFast VP200 H (Teradici) user reported broken communication */
3052         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3053         {}
3054 };
3055
3056 #define AZX_FORCE_CODEC_MASK    0x100
3057
3058 static void check_probe_mask(struct azx *chip, int dev)
3059 {
3060         const struct snd_pci_quirk *q;
3061
3062         chip->codec_probe_mask = probe_mask[dev];
3063         if (chip->codec_probe_mask == -1) {
3064                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3065                 if (q) {
3066                         printk(KERN_INFO
3067                                "hda_intel: probe_mask set to 0x%x "
3068                                "for device %04x:%04x\n",
3069                                q->value, q->subvendor, q->subdevice);
3070                         chip->codec_probe_mask = q->value;
3071                 }
3072         }
3073
3074         /* check forced option */
3075         if (chip->codec_probe_mask != -1 &&
3076             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3077                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3078                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3079                        chip->codec_mask);
3080         }
3081 }
3082
3083 /*
3084  * white/black-list for enable_msi
3085  */
3086 static struct snd_pci_quirk msi_black_list[] = {
3087         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3088         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3089         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3090         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3091         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3092         {}
3093 };
3094
3095 static void check_msi(struct azx *chip)
3096 {
3097         const struct snd_pci_quirk *q;
3098
3099         if (enable_msi >= 0) {
3100                 chip->msi = !!enable_msi;
3101                 return;
3102         }
3103         chip->msi = 1;  /* enable MSI as default */
3104         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3105         if (q) {
3106                 printk(KERN_INFO
3107                        "hda_intel: msi for device %04x:%04x set to %d\n",
3108                        q->subvendor, q->subdevice, q->value);
3109                 chip->msi = q->value;
3110                 return;
3111         }
3112
3113         /* NVidia chipsets seem to cause troubles with MSI */
3114         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3115                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3116                 chip->msi = 0;
3117         }
3118 }
3119
3120 /* check the snoop mode availability */
3121 static void azx_check_snoop_available(struct azx *chip)
3122 {
3123         bool snoop = chip->snoop;
3124
3125         switch (chip->driver_type) {
3126         case AZX_DRIVER_VIA:
3127                 /* force to non-snoop mode for a new VIA controller
3128                  * when BIOS is set
3129                  */
3130                 if (snoop) {
3131                         u8 val;
3132                         pci_read_config_byte(chip->pci, 0x42, &val);
3133                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3134                                 snoop = false;
3135                 }
3136                 break;
3137         case AZX_DRIVER_ATIHDMI_NS:
3138                 /* new ATI HDMI requires non-snoop */
3139                 snoop = false;
3140                 break;
3141         }
3142
3143         if (snoop != chip->snoop) {
3144                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3145                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3146                 chip->snoop = snoop;
3147         }
3148 }
3149
3150 /*
3151  * constructor
3152  */
3153 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3154                       int dev, unsigned int driver_caps,
3155                       struct azx **rchip)
3156 {
3157         static struct snd_device_ops ops = {
3158                 .dev_free = azx_dev_free,
3159         };
3160         struct azx *chip;
3161         int err;
3162
3163         *rchip = NULL;
3164
3165         err = pci_enable_device(pci);
3166         if (err < 0)
3167                 return err;
3168
3169         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3170         if (!chip) {
3171                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3172                 pci_disable_device(pci);
3173                 return -ENOMEM;
3174         }
3175
3176         spin_lock_init(&chip->reg_lock);
3177         mutex_init(&chip->open_mutex);
3178         chip->card = card;
3179         chip->pci = pci;
3180         chip->irq = -1;
3181         chip->driver_caps = driver_caps;
3182         chip->driver_type = driver_caps & 0xff;
3183         check_msi(chip);
3184         chip->dev_index = dev;
3185         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3186         INIT_LIST_HEAD(&chip->pcm_list);
3187         INIT_LIST_HEAD(&chip->list);
3188         init_vga_switcheroo(chip);
3189         init_completion(&chip->probe_wait);
3190
3191         chip->position_fix[0] = chip->position_fix[1] =
3192                 check_position_fix(chip, position_fix[dev]);
3193         /* combo mode uses LPIB for playback */
3194         if (chip->position_fix[0] == POS_FIX_COMBO) {
3195                 chip->position_fix[0] = POS_FIX_LPIB;
3196                 chip->position_fix[1] = POS_FIX_AUTO;
3197         }
3198
3199         check_probe_mask(chip, dev);
3200
3201         chip->single_cmd = single_cmd;
3202         chip->snoop = hda_snoop;
3203         azx_check_snoop_available(chip);
3204
3205         if (bdl_pos_adj[dev] < 0) {
3206                 switch (chip->driver_type) {
3207                 case AZX_DRIVER_ICH:
3208                 case AZX_DRIVER_PCH:
3209                         bdl_pos_adj[dev] = 1;
3210                         break;
3211                 default:
3212                         bdl_pos_adj[dev] = 32;
3213                         break;
3214                 }
3215         }
3216
3217         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3218         if (err < 0) {
3219                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3220                    pci_name(chip->pci));
3221                 azx_free(chip);
3222                 return err;
3223         }
3224
3225         *rchip = chip;
3226         return 0;
3227 }
3228
3229 static int azx_first_init(struct azx *chip)
3230 {
3231         int dev = chip->dev_index;
3232         struct pci_dev *pci = chip->pci;
3233         struct snd_card *card = chip->card;
3234         int i, err;
3235         unsigned short gcap;
3236
3237 #if BITS_PER_LONG != 64
3238         /* Fix up base address on ULI M5461 */
3239         if (chip->driver_type == AZX_DRIVER_ULI) {
3240                 u16 tmp3;
3241                 pci_read_config_word(pci, 0x40, &tmp3);
3242                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3243                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3244         }
3245 #endif
3246
3247         err = pci_request_regions(pci, "ICH HD audio");
3248         if (err < 0)
3249                 return err;
3250         chip->region_requested = 1;
3251
3252         chip->addr = pci_resource_start(pci, 0);
3253         chip->remap_addr = pci_ioremap_bar(pci, 0);
3254         if (chip->remap_addr == NULL) {
3255                 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3256                 return -ENXIO;
3257         }
3258
3259         if (chip->msi)
3260                 if (pci_enable_msi(pci) < 0)
3261                         chip->msi = 0;
3262
3263         if (azx_acquire_irq(chip, 0) < 0)
3264                 return -EBUSY;
3265
3266         pci_set_master(pci);
3267         synchronize_irq(chip->irq);
3268
3269         gcap = azx_readw(chip, GCAP);
3270         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3271
3272         /* disable SB600 64bit support for safety */
3273         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3274                 struct pci_dev *p_smbus;
3275                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3276                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3277                                          NULL);
3278                 if (p_smbus) {
3279                         if (p_smbus->revision < 0x30)
3280                                 gcap &= ~ICH6_GCAP_64OK;
3281                         pci_dev_put(p_smbus);
3282                 }
3283         }
3284
3285         /* disable 64bit DMA address on some devices */
3286         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3287                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3288                 gcap &= ~ICH6_GCAP_64OK;
3289         }
3290
3291         /* disable buffer size rounding to 128-byte multiples if supported */
3292         if (align_buffer_size >= 0)
3293                 chip->align_buffer_size = !!align_buffer_size;
3294         else {
3295                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3296                         chip->align_buffer_size = 0;
3297                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3298                         chip->align_buffer_size = 1;
3299                 else
3300                         chip->align_buffer_size = 1;
3301         }
3302
3303         /* allow 64bit DMA address if supported by H/W */
3304         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3305                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3306         else {
3307                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3308                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3309         }
3310
3311         /* read number of streams from GCAP register instead of using