ALSA: hda - Fix non-snoop page handling
[~shefty/rdma-dev.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
70 static char *model[SNDRV_CARDS];
71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_only[SNDRV_CARDS];
75 static int jackpoll_ms[SNDRV_CARDS];
76 static bool single_cmd;
77 static int enable_msi = -1;
78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
79 static char *patch[SNDRV_CARDS];
80 #endif
81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
84 #endif
85
86 module_param_array(index, int, NULL, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
88 module_param_array(id, charp, NULL, 0444);
89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
90 module_param_array(enable, bool, NULL, 0444);
91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92 module_param_array(model, charp, NULL, 0444);
93 MODULE_PARM_DESC(model, "Use the given board model.");
94 module_param_array(position_fix, int, NULL, 0444);
95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
97 module_param_array(bdl_pos_adj, int, NULL, 0644);
98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
99 module_param_array(probe_mask, int, NULL, 0444);
100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
101 module_param_array(probe_only, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
103 module_param_array(jackpoll_ms, int, NULL, 0444);
104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
105 module_param(single_cmd, bool, 0444);
106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107                  "(for debugging only).");
108 module_param(enable_msi, bint, 0444);
109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
111 module_param_array(patch, charp, NULL, 0444);
112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113 #endif
114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
115 module_param_array(beep_mode, bool, NULL, 0444);
116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
117                             "(0=off, 1=on) (default=1).");
118 #endif
119
120 #ifdef CONFIG_PM
121 static int param_set_xint(const char *val, const struct kernel_param *kp);
122 static struct kernel_param_ops param_ops_xint = {
123         .set = param_set_xint,
124         .get = param_get_int,
125 };
126 #define param_check_xint param_check_int
127
128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
129 module_param(power_save, xint, 0644);
130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131                  "(in second, 0 = disable).");
132
133 /* reset the HD-audio controller in power save mode.
134  * this may give more power-saving, but will take longer time to
135  * wake up.
136  */
137 static bool power_save_controller = 1;
138 module_param(power_save_controller, bool, 0644);
139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
140 #endif /* CONFIG_PM */
141
142 static int align_buffer_size = -1;
143 module_param(align_buffer_size, bint, 0644);
144 MODULE_PARM_DESC(align_buffer_size,
145                 "Force buffer and period sizes to be multiple of 128 bytes.");
146
147 #ifdef CONFIG_X86
148 static bool hda_snoop = true;
149 module_param_named(snoop, hda_snoop, bool, 0444);
150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151 #define azx_snoop(chip)         (chip)->snoop
152 #else
153 #define hda_snoop               true
154 #define azx_snoop(chip)         true
155 #endif
156
157
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160                          "{Intel, ICH6M},"
161                          "{Intel, ICH7},"
162                          "{Intel, ESB2},"
163                          "{Intel, ICH8},"
164                          "{Intel, ICH9},"
165                          "{Intel, ICH10},"
166                          "{Intel, PCH},"
167                          "{Intel, CPT},"
168                          "{Intel, PPT},"
169                          "{Intel, LPT},"
170                          "{Intel, LPT_LP},"
171                          "{Intel, HPT},"
172                          "{Intel, PBG},"
173                          "{Intel, SCH},"
174                          "{ATI, SB450},"
175                          "{ATI, SB600},"
176                          "{ATI, RS600},"
177                          "{ATI, RS690},"
178                          "{ATI, RS780},"
179                          "{ATI, R600},"
180                          "{ATI, RV630},"
181                          "{ATI, RV610},"
182                          "{ATI, RV670},"
183                          "{ATI, RV635},"
184                          "{ATI, RV620},"
185                          "{ATI, RV770},"
186                          "{VIA, VT8251},"
187                          "{VIA, VT8237A},"
188                          "{SiS, SIS966},"
189                          "{ULI, M5461}}");
190 MODULE_DESCRIPTION("Intel HDA driver");
191
192 #ifdef CONFIG_SND_VERBOSE_PRINTK
193 #define SFX     /* nop */
194 #else
195 #define SFX     "hda-intel "
196 #endif
197
198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
200 #define SUPPORT_VGA_SWITCHEROO
201 #endif
202 #endif
203
204
205 /*
206  * registers
207  */
208 #define ICH6_REG_GCAP                   0x00
209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
214 #define ICH6_REG_VMIN                   0x02
215 #define ICH6_REG_VMAJ                   0x03
216 #define ICH6_REG_OUTPAY                 0x04
217 #define ICH6_REG_INPAY                  0x06
218 #define ICH6_REG_GCTL                   0x08
219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
222 #define ICH6_REG_WAKEEN                 0x0c
223 #define ICH6_REG_STATESTS               0x0e
224 #define ICH6_REG_GSTS                   0x10
225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
226 #define ICH6_REG_INTCTL                 0x20
227 #define ICH6_REG_INTSTS                 0x24
228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
230 #define ICH6_REG_SSYNC                  0x38
231 #define ICH6_REG_CORBLBASE              0x40
232 #define ICH6_REG_CORBUBASE              0x44
233 #define ICH6_REG_CORBWP                 0x48
234 #define ICH6_REG_CORBRP                 0x4a
235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
236 #define ICH6_REG_CORBCTL                0x4c
237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
239 #define ICH6_REG_CORBSTS                0x4d
240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
241 #define ICH6_REG_CORBSIZE               0x4e
242
243 #define ICH6_REG_RIRBLBASE              0x50
244 #define ICH6_REG_RIRBUBASE              0x54
245 #define ICH6_REG_RIRBWP                 0x58
246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
247 #define ICH6_REG_RINTCNT                0x5a
248 #define ICH6_REG_RIRBCTL                0x5c
249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
252 #define ICH6_REG_RIRBSTS                0x5d
253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
255 #define ICH6_REG_RIRBSIZE               0x5e
256
257 #define ICH6_REG_IC                     0x60
258 #define ICH6_REG_IR                     0x64
259 #define ICH6_REG_IRS                    0x68
260 #define   ICH6_IRS_VALID        (1<<1)
261 #define   ICH6_IRS_BUSY         (1<<0)
262
263 #define ICH6_REG_DPLBASE                0x70
264 #define ICH6_REG_DPUBASE                0x74
265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
266
267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270 /* stream register offsets from stream base */
271 #define ICH6_REG_SD_CTL                 0x00
272 #define ICH6_REG_SD_STS                 0x03
273 #define ICH6_REG_SD_LPIB                0x04
274 #define ICH6_REG_SD_CBL                 0x08
275 #define ICH6_REG_SD_LVI                 0x0c
276 #define ICH6_REG_SD_FIFOW               0x0e
277 #define ICH6_REG_SD_FIFOSIZE            0x10
278 #define ICH6_REG_SD_FORMAT              0x12
279 #define ICH6_REG_SD_BDLPL               0x18
280 #define ICH6_REG_SD_BDLPU               0x1c
281
282 /* PCI space */
283 #define ICH6_PCIREG_TCSEL       0x44
284
285 /*
286  * other constants
287  */
288
289 /* max number of SDs */
290 /* ICH, ATI and VIA have 4 playback and 4 capture */
291 #define ICH6_NUM_CAPTURE        4
292 #define ICH6_NUM_PLAYBACK       4
293
294 /* ULI has 6 playback and 5 capture */
295 #define ULI_NUM_CAPTURE         5
296 #define ULI_NUM_PLAYBACK        6
297
298 /* ATI HDMI has 1 playback and 0 capture */
299 #define ATIHDMI_NUM_CAPTURE     0
300 #define ATIHDMI_NUM_PLAYBACK    1
301
302 /* TERA has 4 playback and 3 capture */
303 #define TERA_NUM_CAPTURE        3
304 #define TERA_NUM_PLAYBACK       4
305
306 /* this number is statically defined for simplicity */
307 #define MAX_AZX_DEV             16
308
309 /* max number of fragments - we may use more if allocating more pages for BDL */
310 #define BDL_SIZE                4096
311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
312 #define AZX_MAX_FRAG            32
313 /* max buffer size - no h/w limit, you can increase as you like */
314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
315
316 /* RIRB int mask: overrun[2], response[0] */
317 #define RIRB_INT_RESPONSE       0x01
318 #define RIRB_INT_OVERRUN        0x04
319 #define RIRB_INT_MASK           0x05
320
321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
322 #define AZX_MAX_CODECS          8
323 #define AZX_DEFAULT_CODECS      4
324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
325
326 /* SD_CTL bits */
327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
333 #define SD_CTL_STREAM_TAG_SHIFT 20
334
335 /* SD_CTL and SD_STS */
336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340                                  SD_INT_COMPLETE)
341
342 /* SD_STS */
343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
344
345 /* INTCTL and INTSTS */
346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
349
350 /* below are so far hardcoded - should read registers in future */
351 #define ICH6_MAX_CORB_ENTRIES   256
352 #define ICH6_MAX_RIRB_ENTRIES   256
353
354 /* position fix mode */
355 enum {
356         POS_FIX_AUTO,
357         POS_FIX_LPIB,
358         POS_FIX_POSBUF,
359         POS_FIX_VIACOMBO,
360         POS_FIX_COMBO,
361 };
362
363 /* Defines for ATI HD Audio support in SB450 south bridge */
364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
366
367 /* Defines for Nvidia HDA support */
368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
370 #define NVIDIA_HDA_ISTRM_COH          0x4d
371 #define NVIDIA_HDA_OSTRM_COH          0x4c
372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
373
374 /* Defines for Intel SCH HDA snoop control */
375 #define INTEL_SCH_HDA_DEVC      0x78
376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
377
378 /* Define IN stream 0 FIFO size offset in VIA controller */
379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380 /* Define VIA HD Audio Device ID*/
381 #define VIA_HDAC_DEVICE_ID              0x3288
382
383 /* HD Audio class code */
384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
385
386 /*
387  */
388
389 struct azx_dev {
390         struct snd_dma_buffer bdl; /* BDL buffer */
391         u32 *posbuf;            /* position buffer pointer */
392
393         unsigned int bufsize;   /* size of the play buffer in bytes */
394         unsigned int period_bytes; /* size of the period in bytes */
395         unsigned int frags;     /* number for period in the play buffer */
396         unsigned int fifo_size; /* FIFO size */
397         unsigned long start_wallclk;    /* start + minimum wallclk */
398         unsigned long period_wallclk;   /* wallclk for period */
399
400         void __iomem *sd_addr;  /* stream descriptor pointer */
401
402         u32 sd_int_sta_mask;    /* stream int status mask */
403
404         /* pcm support */
405         struct snd_pcm_substream *substream;    /* assigned substream,
406                                                  * set in PCM open
407                                                  */
408         unsigned int format_val;        /* format value to be set in the
409                                          * controller and the codec
410                                          */
411         unsigned char stream_tag;       /* assigned stream */
412         unsigned char index;            /* stream index */
413         int assigned_key;               /* last device# key assigned to */
414
415         unsigned int opened :1;
416         unsigned int running :1;
417         unsigned int irq_pending :1;
418         /*
419          * For VIA:
420          *  A flag to ensure DMA position is 0
421          *  when link position is not greater than FIFO size
422          */
423         unsigned int insufficient :1;
424         unsigned int wc_marked:1;
425         unsigned int no_period_wakeup:1;
426
427         struct timecounter  azx_tc;
428         struct cyclecounter azx_cc;
429 };
430
431 /* CORB/RIRB */
432 struct azx_rb {
433         u32 *buf;               /* CORB/RIRB buffer
434                                  * Each CORB entry is 4byte, RIRB is 8byte
435                                  */
436         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
437         /* for RIRB */
438         unsigned short rp, wp;  /* read/write pointers */
439         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
440         u32 res[AZX_MAX_CODECS];        /* last read value */
441 };
442
443 struct azx_pcm {
444         struct azx *chip;
445         struct snd_pcm *pcm;
446         struct hda_codec *codec;
447         struct hda_pcm_stream *hinfo[2];
448         struct list_head list;
449 };
450
451 struct azx {
452         struct snd_card *card;
453         struct pci_dev *pci;
454         int dev_index;
455
456         /* chip type specific */
457         int driver_type;
458         unsigned int driver_caps;
459         int playback_streams;
460         int playback_index_offset;
461         int capture_streams;
462         int capture_index_offset;
463         int num_streams;
464
465         /* pci resources */
466         unsigned long addr;
467         void __iomem *remap_addr;
468         int irq;
469
470         /* locks */
471         spinlock_t reg_lock;
472         struct mutex open_mutex;
473         struct completion probe_wait;
474
475         /* streams (x num_streams) */
476         struct azx_dev *azx_dev;
477
478         /* PCM */
479         struct list_head pcm_list; /* azx_pcm list */
480
481         /* HD codec */
482         unsigned short codec_mask;
483         int  codec_probe_mask; /* copied from probe_mask option */
484         struct hda_bus *bus;
485         unsigned int beep_mode;
486
487         /* CORB/RIRB */
488         struct azx_rb corb;
489         struct azx_rb rirb;
490
491         /* CORB/RIRB and position buffers */
492         struct snd_dma_buffer rb;
493         struct snd_dma_buffer posbuf;
494
495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
496         const struct firmware *fw;
497 #endif
498
499         /* flags */
500         int position_fix[2]; /* for both playback/capture streams */
501         int poll_count;
502         unsigned int running :1;
503         unsigned int initialized :1;
504         unsigned int single_cmd :1;
505         unsigned int polling_mode :1;
506         unsigned int msi :1;
507         unsigned int irq_pending_warned :1;
508         unsigned int probing :1; /* codec probing phase */
509         unsigned int snoop:1;
510         unsigned int align_buffer_size:1;
511         unsigned int region_requested:1;
512
513         /* VGA-switcheroo setup */
514         unsigned int use_vga_switcheroo:1;
515         unsigned int vga_switcheroo_registered:1;
516         unsigned int init_failed:1; /* delayed init failed */
517         unsigned int disabled:1; /* disabled by VGA-switcher */
518
519         /* for debugging */
520         unsigned int last_cmd[AZX_MAX_CODECS];
521
522         /* for pending irqs */
523         struct work_struct irq_pending_work;
524
525         /* reboot notifier (for mysterious hangup problem at power-down) */
526         struct notifier_block reboot_notifier;
527
528         /* card list (for power_save trigger) */
529         struct list_head list;
530 };
531
532 #define CREATE_TRACE_POINTS
533 #include "hda_intel_trace.h"
534
535 /* driver types */
536 enum {
537         AZX_DRIVER_ICH,
538         AZX_DRIVER_PCH,
539         AZX_DRIVER_SCH,
540         AZX_DRIVER_ATI,
541         AZX_DRIVER_ATIHDMI,
542         AZX_DRIVER_ATIHDMI_NS,
543         AZX_DRIVER_VIA,
544         AZX_DRIVER_SIS,
545         AZX_DRIVER_ULI,
546         AZX_DRIVER_NVIDIA,
547         AZX_DRIVER_TERA,
548         AZX_DRIVER_CTX,
549         AZX_DRIVER_CTHDA,
550         AZX_DRIVER_GENERIC,
551         AZX_NUM_DRIVERS, /* keep this as last entry */
552 };
553
554 /* driver quirks (capabilities) */
555 /* bits 0-7 are used for indicating driver type */
556 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
557 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
558 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
559 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
560 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
561 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
562 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
563 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
564 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
565 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
566 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
567 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
568 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
569 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
570 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
571 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
572 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
573 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
574
575 /* quirks for Intel PCH */
576 #define AZX_DCAPS_INTEL_PCH_NOPM \
577         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
578          AZX_DCAPS_COUNT_LPIB_DELAY)
579
580 #define AZX_DCAPS_INTEL_PCH \
581         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
582
583 /* quirks for ATI SB / AMD Hudson */
584 #define AZX_DCAPS_PRESET_ATI_SB \
585         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
586          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
587
588 /* quirks for ATI/AMD HDMI */
589 #define AZX_DCAPS_PRESET_ATI_HDMI \
590         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
591
592 /* quirks for Nvidia */
593 #define AZX_DCAPS_PRESET_NVIDIA \
594         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
595          AZX_DCAPS_ALIGN_BUFSIZE)
596
597 #define AZX_DCAPS_PRESET_CTHDA \
598         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
599
600 /*
601  * VGA-switcher support
602  */
603 #ifdef SUPPORT_VGA_SWITCHEROO
604 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
605 #else
606 #define use_vga_switcheroo(chip)        0
607 #endif
608
609 static char *driver_short_names[] = {
610         [AZX_DRIVER_ICH] = "HDA Intel",
611         [AZX_DRIVER_PCH] = "HDA Intel PCH",
612         [AZX_DRIVER_SCH] = "HDA Intel MID",
613         [AZX_DRIVER_ATI] = "HDA ATI SB",
614         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
615         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
616         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
617         [AZX_DRIVER_SIS] = "HDA SIS966",
618         [AZX_DRIVER_ULI] = "HDA ULI M5461",
619         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
620         [AZX_DRIVER_TERA] = "HDA Teradici", 
621         [AZX_DRIVER_CTX] = "HDA Creative", 
622         [AZX_DRIVER_CTHDA] = "HDA Creative",
623         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
624 };
625
626 /*
627  * macros for easy use
628  */
629 #define azx_writel(chip,reg,value) \
630         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
631 #define azx_readl(chip,reg) \
632         readl((chip)->remap_addr + ICH6_REG_##reg)
633 #define azx_writew(chip,reg,value) \
634         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
635 #define azx_readw(chip,reg) \
636         readw((chip)->remap_addr + ICH6_REG_##reg)
637 #define azx_writeb(chip,reg,value) \
638         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
639 #define azx_readb(chip,reg) \
640         readb((chip)->remap_addr + ICH6_REG_##reg)
641
642 #define azx_sd_writel(dev,reg,value) \
643         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
644 #define azx_sd_readl(dev,reg) \
645         readl((dev)->sd_addr + ICH6_REG_##reg)
646 #define azx_sd_writew(dev,reg,value) \
647         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
648 #define azx_sd_readw(dev,reg) \
649         readw((dev)->sd_addr + ICH6_REG_##reg)
650 #define azx_sd_writeb(dev,reg,value) \
651         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
652 #define azx_sd_readb(dev,reg) \
653         readb((dev)->sd_addr + ICH6_REG_##reg)
654
655 /* for pcm support */
656 #define get_azx_dev(substream) (substream->runtime->private_data)
657
658 #ifdef CONFIG_X86
659 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
660 {
661         int pages;
662
663         if (azx_snoop(chip))
664                 return;
665         if (!dmab || !dmab->area || !dmab->bytes)
666                 return;
667
668 #ifdef CONFIG_SND_DMA_SGBUF
669         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
670                 struct snd_sg_buf *sgbuf = dmab->private_data;
671                 if (on)
672                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
673                 else
674                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
675                 return;
676         }
677 #endif
678
679         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
680         if (on)
681                 set_memory_wc((unsigned long)dmab->area, pages);
682         else
683                 set_memory_wb((unsigned long)dmab->area, pages);
684 }
685
686 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
687                                  bool on)
688 {
689         __mark_pages_wc(chip, buf, on);
690 }
691 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
692                                    struct snd_pcm_substream *substream, bool on)
693 {
694         if (azx_dev->wc_marked != on) {
695                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
696                 azx_dev->wc_marked = on;
697         }
698 }
699 #else
700 /* NOP for other archs */
701 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
702                                  bool on)
703 {
704 }
705 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
706                                    struct snd_pcm_substream *substream, bool on)
707 {
708 }
709 #endif
710
711 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
712 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
713 /*
714  * Interface for HD codec
715  */
716
717 /*
718  * CORB / RIRB interface
719  */
720 static int azx_alloc_cmd_io(struct azx *chip)
721 {
722         int err;
723
724         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
725         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
726                                   snd_dma_pci_data(chip->pci),
727                                   PAGE_SIZE, &chip->rb);
728         if (err < 0) {
729                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
730                 return err;
731         }
732         mark_pages_wc(chip, &chip->rb, true);
733         return 0;
734 }
735
736 static void azx_init_cmd_io(struct azx *chip)
737 {
738         spin_lock_irq(&chip->reg_lock);
739         /* CORB set up */
740         chip->corb.addr = chip->rb.addr;
741         chip->corb.buf = (u32 *)chip->rb.area;
742         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
743         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
744
745         /* set the corb size to 256 entries (ULI requires explicitly) */
746         azx_writeb(chip, CORBSIZE, 0x02);
747         /* set the corb write pointer to 0 */
748         azx_writew(chip, CORBWP, 0);
749         /* reset the corb hw read pointer */
750         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
751         /* enable corb dma */
752         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
753
754         /* RIRB set up */
755         chip->rirb.addr = chip->rb.addr + 2048;
756         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
757         chip->rirb.wp = chip->rirb.rp = 0;
758         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
759         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
760         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
761
762         /* set the rirb size to 256 entries (ULI requires explicitly) */
763         azx_writeb(chip, RIRBSIZE, 0x02);
764         /* reset the rirb hw write pointer */
765         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
766         /* set N=1, get RIRB response interrupt for new entry */
767         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
768                 azx_writew(chip, RINTCNT, 0xc0);
769         else
770                 azx_writew(chip, RINTCNT, 1);
771         /* enable rirb dma and response irq */
772         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
773         spin_unlock_irq(&chip->reg_lock);
774 }
775
776 static void azx_free_cmd_io(struct azx *chip)
777 {
778         spin_lock_irq(&chip->reg_lock);
779         /* disable ringbuffer DMAs */
780         azx_writeb(chip, RIRBCTL, 0);
781         azx_writeb(chip, CORBCTL, 0);
782         spin_unlock_irq(&chip->reg_lock);
783 }
784
785 static unsigned int azx_command_addr(u32 cmd)
786 {
787         unsigned int addr = cmd >> 28;
788
789         if (addr >= AZX_MAX_CODECS) {
790                 snd_BUG();
791                 addr = 0;
792         }
793
794         return addr;
795 }
796
797 static unsigned int azx_response_addr(u32 res)
798 {
799         unsigned int addr = res & 0xf;
800
801         if (addr >= AZX_MAX_CODECS) {
802                 snd_BUG();
803                 addr = 0;
804         }
805
806         return addr;
807 }
808
809 /* send a command */
810 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
811 {
812         struct azx *chip = bus->private_data;
813         unsigned int addr = azx_command_addr(val);
814         unsigned int wp;
815
816         spin_lock_irq(&chip->reg_lock);
817
818         /* add command to corb */
819         wp = azx_readw(chip, CORBWP);
820         if (wp == 0xffff) {
821                 /* something wrong, controller likely turned to D3 */
822                 spin_unlock_irq(&chip->reg_lock);
823                 return -1;
824         }
825         wp++;
826         wp %= ICH6_MAX_CORB_ENTRIES;
827
828         chip->rirb.cmds[addr]++;
829         chip->corb.buf[wp] = cpu_to_le32(val);
830         azx_writel(chip, CORBWP, wp);
831
832         spin_unlock_irq(&chip->reg_lock);
833
834         return 0;
835 }
836
837 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
838
839 /* retrieve RIRB entry - called from interrupt handler */
840 static void azx_update_rirb(struct azx *chip)
841 {
842         unsigned int rp, wp;
843         unsigned int addr;
844         u32 res, res_ex;
845
846         wp = azx_readw(chip, RIRBWP);
847         if (wp == 0xffff) {
848                 /* something wrong, controller likely turned to D3 */
849                 return;
850         }
851
852         if (wp == chip->rirb.wp)
853                 return;
854         chip->rirb.wp = wp;
855
856         while (chip->rirb.rp != wp) {
857                 chip->rirb.rp++;
858                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
859
860                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
861                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
862                 res = le32_to_cpu(chip->rirb.buf[rp]);
863                 addr = azx_response_addr(res_ex);
864                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
865                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
866                 else if (chip->rirb.cmds[addr]) {
867                         chip->rirb.res[addr] = res;
868                         smp_wmb();
869                         chip->rirb.cmds[addr]--;
870                 } else
871                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
872                                    "last cmd=%#08x\n",
873                                    pci_name(chip->pci),
874                                    res, res_ex,
875                                    chip->last_cmd[addr]);
876         }
877 }
878
879 /* receive a response */
880 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
881                                           unsigned int addr)
882 {
883         struct azx *chip = bus->private_data;
884         unsigned long timeout;
885         unsigned long loopcounter;
886         int do_poll = 0;
887
888  again:
889         timeout = jiffies + msecs_to_jiffies(1000);
890
891         for (loopcounter = 0;; loopcounter++) {
892                 if (chip->polling_mode || do_poll) {
893                         spin_lock_irq(&chip->reg_lock);
894                         azx_update_rirb(chip);
895                         spin_unlock_irq(&chip->reg_lock);
896                 }
897                 if (!chip->rirb.cmds[addr]) {
898                         smp_rmb();
899                         bus->rirb_error = 0;
900
901                         if (!do_poll)
902                                 chip->poll_count = 0;
903                         return chip->rirb.res[addr]; /* the last value */
904                 }
905                 if (time_after(jiffies, timeout))
906                         break;
907                 if (bus->needs_damn_long_delay || loopcounter > 3000)
908                         msleep(2); /* temporary workaround */
909                 else {
910                         udelay(10);
911                         cond_resched();
912                 }
913         }
914
915         if (!chip->polling_mode && chip->poll_count < 2) {
916                 snd_printdd(SFX "%s: azx_get_response timeout, "
917                            "polling the codec once: last cmd=0x%08x\n",
918                            pci_name(chip->pci), chip->last_cmd[addr]);
919                 do_poll = 1;
920                 chip->poll_count++;
921                 goto again;
922         }
923
924
925         if (!chip->polling_mode) {
926                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
927                            "switching to polling mode: last cmd=0x%08x\n",
928                            pci_name(chip->pci), chip->last_cmd[addr]);
929                 chip->polling_mode = 1;
930                 goto again;
931         }
932
933         if (chip->msi) {
934                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
935                            "disabling MSI: last cmd=0x%08x\n",
936                            pci_name(chip->pci), chip->last_cmd[addr]);
937                 free_irq(chip->irq, chip);
938                 chip->irq = -1;
939                 pci_disable_msi(chip->pci);
940                 chip->msi = 0;
941                 if (azx_acquire_irq(chip, 1) < 0) {
942                         bus->rirb_error = 1;
943                         return -1;
944                 }
945                 goto again;
946         }
947
948         if (chip->probing) {
949                 /* If this critical timeout happens during the codec probing
950                  * phase, this is likely an access to a non-existing codec
951                  * slot.  Better to return an error and reset the system.
952                  */
953                 return -1;
954         }
955
956         /* a fatal communication error; need either to reset or to fallback
957          * to the single_cmd mode
958          */
959         bus->rirb_error = 1;
960         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
961                 bus->response_reset = 1;
962                 return -1; /* give a chance to retry */
963         }
964
965         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
966                    "switching to single_cmd mode: last cmd=0x%08x\n",
967                    chip->last_cmd[addr]);
968         chip->single_cmd = 1;
969         bus->response_reset = 0;
970         /* release CORB/RIRB */
971         azx_free_cmd_io(chip);
972         /* disable unsolicited responses */
973         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
974         return -1;
975 }
976
977 /*
978  * Use the single immediate command instead of CORB/RIRB for simplicity
979  *
980  * Note: according to Intel, this is not preferred use.  The command was
981  *       intended for the BIOS only, and may get confused with unsolicited
982  *       responses.  So, we shouldn't use it for normal operation from the
983  *       driver.
984  *       I left the codes, however, for debugging/testing purposes.
985  */
986
987 /* receive a response */
988 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
989 {
990         int timeout = 50;
991
992         while (timeout--) {
993                 /* check IRV busy bit */
994                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
995                         /* reuse rirb.res as the response return value */
996                         chip->rirb.res[addr] = azx_readl(chip, IR);
997                         return 0;
998                 }
999                 udelay(1);
1000         }
1001         if (printk_ratelimit())
1002                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1003                            pci_name(chip->pci), azx_readw(chip, IRS));
1004         chip->rirb.res[addr] = -1;
1005         return -EIO;
1006 }
1007
1008 /* send a command */
1009 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1010 {
1011         struct azx *chip = bus->private_data;
1012         unsigned int addr = azx_command_addr(val);
1013         int timeout = 50;
1014
1015         bus->rirb_error = 0;
1016         while (timeout--) {
1017                 /* check ICB busy bit */
1018                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1019                         /* Clear IRV valid bit */
1020                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1021                                    ICH6_IRS_VALID);
1022                         azx_writel(chip, IC, val);
1023                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1024                                    ICH6_IRS_BUSY);
1025                         return azx_single_wait_for_response(chip, addr);
1026                 }
1027                 udelay(1);
1028         }
1029         if (printk_ratelimit())
1030                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1031                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1032         return -EIO;
1033 }
1034
1035 /* receive a response */
1036 static unsigned int azx_single_get_response(struct hda_bus *bus,
1037                                             unsigned int addr)
1038 {
1039         struct azx *chip = bus->private_data;
1040         return chip->rirb.res[addr];
1041 }
1042
1043 /*
1044  * The below are the main callbacks from hda_codec.
1045  *
1046  * They are just the skeleton to call sub-callbacks according to the
1047  * current setting of chip->single_cmd.
1048  */
1049
1050 /* send a command */
1051 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1052 {
1053         struct azx *chip = bus->private_data;
1054
1055         if (chip->disabled)
1056                 return 0;
1057         chip->last_cmd[azx_command_addr(val)] = val;
1058         if (chip->single_cmd)
1059                 return azx_single_send_cmd(bus, val);
1060         else
1061                 return azx_corb_send_cmd(bus, val);
1062 }
1063
1064 /* get a response */
1065 static unsigned int azx_get_response(struct hda_bus *bus,
1066                                      unsigned int addr)
1067 {
1068         struct azx *chip = bus->private_data;
1069         if (chip->disabled)
1070                 return 0;
1071         if (chip->single_cmd)
1072                 return azx_single_get_response(bus, addr);
1073         else
1074                 return azx_rirb_get_response(bus, addr);
1075 }
1076
1077 #ifdef CONFIG_PM
1078 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1079 #endif
1080
1081 /* reset codec link */
1082 static int azx_reset(struct azx *chip, int full_reset)
1083 {
1084         unsigned long timeout;
1085
1086         if (!full_reset)
1087                 goto __skip;
1088
1089         /* clear STATESTS */
1090         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1091
1092         /* reset controller */
1093         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1094
1095         timeout = jiffies + msecs_to_jiffies(100);
1096         while (azx_readb(chip, GCTL) &&
1097                         time_before(jiffies, timeout))
1098                 usleep_range(500, 1000);
1099
1100         /* delay for >= 100us for codec PLL to settle per spec
1101          * Rev 0.9 section 5.5.1
1102          */
1103         usleep_range(500, 1000);
1104
1105         /* Bring controller out of reset */
1106         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1107
1108         timeout = jiffies + msecs_to_jiffies(100);
1109         while (!azx_readb(chip, GCTL) &&
1110                         time_before(jiffies, timeout))
1111                 usleep_range(500, 1000);
1112
1113         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1114         usleep_range(1000, 1200);
1115
1116       __skip:
1117         /* check to see if controller is ready */
1118         if (!azx_readb(chip, GCTL)) {
1119                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1120                 return -EBUSY;
1121         }
1122
1123         /* Accept unsolicited responses */
1124         if (!chip->single_cmd)
1125                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1126                            ICH6_GCTL_UNSOL);
1127
1128         /* detect codecs */
1129         if (!chip->codec_mask) {
1130                 chip->codec_mask = azx_readw(chip, STATESTS);
1131                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1132         }
1133
1134         return 0;
1135 }
1136
1137
1138 /*
1139  * Lowlevel interface
1140  */  
1141
1142 /* enable interrupts */
1143 static void azx_int_enable(struct azx *chip)
1144 {
1145         /* enable controller CIE and GIE */
1146         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1147                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1148 }
1149
1150 /* disable interrupts */
1151 static void azx_int_disable(struct azx *chip)
1152 {
1153         int i;
1154
1155         /* disable interrupts in stream descriptor */
1156         for (i = 0; i < chip->num_streams; i++) {
1157                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1158                 azx_sd_writeb(azx_dev, SD_CTL,
1159                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1160         }
1161
1162         /* disable SIE for all streams */
1163         azx_writeb(chip, INTCTL, 0);
1164
1165         /* disable controller CIE and GIE */
1166         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1167                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1168 }
1169
1170 /* clear interrupts */
1171 static void azx_int_clear(struct azx *chip)
1172 {
1173         int i;
1174
1175         /* clear stream status */
1176         for (i = 0; i < chip->num_streams; i++) {
1177                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1178                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1179         }
1180
1181         /* clear STATESTS */
1182         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1183
1184         /* clear rirb status */
1185         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1186
1187         /* clear int status */
1188         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1189 }
1190
1191 /* start a stream */
1192 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1193 {
1194         /*
1195          * Before stream start, initialize parameter
1196          */
1197         azx_dev->insufficient = 1;
1198
1199         /* enable SIE */
1200         azx_writel(chip, INTCTL,
1201                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1202         /* set DMA start and interrupt mask */
1203         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1204                       SD_CTL_DMA_START | SD_INT_MASK);
1205 }
1206
1207 /* stop DMA */
1208 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1209 {
1210         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1211                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1212         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1213 }
1214
1215 /* stop a stream */
1216 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1217 {
1218         azx_stream_clear(chip, azx_dev);
1219         /* disable SIE */
1220         azx_writel(chip, INTCTL,
1221                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1222 }
1223
1224
1225 /*
1226  * reset and start the controller registers
1227  */
1228 static void azx_init_chip(struct azx *chip, int full_reset)
1229 {
1230         if (chip->initialized)
1231                 return;
1232
1233         /* reset controller */
1234         azx_reset(chip, full_reset);
1235
1236         /* initialize interrupts */
1237         azx_int_clear(chip);
1238         azx_int_enable(chip);
1239
1240         /* initialize the codec command I/O */
1241         if (!chip->single_cmd)
1242                 azx_init_cmd_io(chip);
1243
1244         /* program the position buffer */
1245         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1246         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1247
1248         chip->initialized = 1;
1249 }
1250
1251 /*
1252  * initialize the PCI registers
1253  */
1254 /* update bits in a PCI register byte */
1255 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1256                             unsigned char mask, unsigned char val)
1257 {
1258         unsigned char data;
1259
1260         pci_read_config_byte(pci, reg, &data);
1261         data &= ~mask;
1262         data |= (val & mask);
1263         pci_write_config_byte(pci, reg, data);
1264 }
1265
1266 static void azx_init_pci(struct azx *chip)
1267 {
1268         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1269          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1270          * Ensuring these bits are 0 clears playback static on some HD Audio
1271          * codecs.
1272          * The PCI register TCSEL is defined in the Intel manuals.
1273          */
1274         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1275                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1276                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1277         }
1278
1279         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1280          * we need to enable snoop.
1281          */
1282         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1283                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1284                 update_pci_byte(chip->pci,
1285                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1286                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1287         }
1288
1289         /* For NVIDIA HDA, enable snoop */
1290         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1291                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1292                 update_pci_byte(chip->pci,
1293                                 NVIDIA_HDA_TRANSREG_ADDR,
1294                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1295                 update_pci_byte(chip->pci,
1296                                 NVIDIA_HDA_ISTRM_COH,
1297                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1298                 update_pci_byte(chip->pci,
1299                                 NVIDIA_HDA_OSTRM_COH,
1300                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1301         }
1302
1303         /* Enable SCH/PCH snoop if needed */
1304         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1305                 unsigned short snoop;
1306                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1307                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1308                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1309                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1310                         if (!azx_snoop(chip))
1311                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1312                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1313                         pci_read_config_word(chip->pci,
1314                                 INTEL_SCH_HDA_DEVC, &snoop);
1315                 }
1316                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1317                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1318                                 ? "Disabled" : "Enabled");
1319         }
1320 }
1321
1322
1323 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1324
1325 /*
1326  * interrupt handler
1327  */
1328 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1329 {
1330         struct azx *chip = dev_id;
1331         struct azx_dev *azx_dev;
1332         u32 status;
1333         u8 sd_status;
1334         int i, ok;
1335
1336 #ifdef CONFIG_PM_RUNTIME
1337         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1338                 return IRQ_NONE;
1339 #endif
1340
1341         spin_lock(&chip->reg_lock);
1342
1343         if (chip->disabled) {
1344                 spin_unlock(&chip->reg_lock);
1345                 return IRQ_NONE;
1346         }
1347
1348         status = azx_readl(chip, INTSTS);
1349         if (status == 0) {
1350                 spin_unlock(&chip->reg_lock);
1351                 return IRQ_NONE;
1352         }
1353         
1354         for (i = 0; i < chip->num_streams; i++) {
1355                 azx_dev = &chip->azx_dev[i];
1356                 if (status & azx_dev->sd_int_sta_mask) {
1357                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1358                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1359                         if (!azx_dev->substream || !azx_dev->running ||
1360                             !(sd_status & SD_INT_COMPLETE))
1361                                 continue;
1362                         /* check whether this IRQ is really acceptable */
1363                         ok = azx_position_ok(chip, azx_dev);
1364                         if (ok == 1) {
1365                                 azx_dev->irq_pending = 0;
1366                                 spin_unlock(&chip->reg_lock);
1367                                 snd_pcm_period_elapsed(azx_dev->substream);
1368                                 spin_lock(&chip->reg_lock);
1369                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1370                                 /* bogus IRQ, process it later */
1371                                 azx_dev->irq_pending = 1;
1372                                 queue_work(chip->bus->workq,
1373                                            &chip->irq_pending_work);
1374                         }
1375                 }
1376         }
1377
1378         /* clear rirb int */
1379         status = azx_readb(chip, RIRBSTS);
1380         if (status & RIRB_INT_MASK) {
1381                 if (status & RIRB_INT_RESPONSE) {
1382                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1383                                 udelay(80);
1384                         azx_update_rirb(chip);
1385                 }
1386                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1387         }
1388
1389 #if 0
1390         /* clear state status int */
1391         if (azx_readb(chip, STATESTS) & 0x04)
1392                 azx_writeb(chip, STATESTS, 0x04);
1393 #endif
1394         spin_unlock(&chip->reg_lock);
1395         
1396         return IRQ_HANDLED;
1397 }
1398
1399
1400 /*
1401  * set up a BDL entry
1402  */
1403 static int setup_bdle(struct azx *chip,
1404                       struct snd_pcm_substream *substream,
1405                       struct azx_dev *azx_dev, u32 **bdlp,
1406                       int ofs, int size, int with_ioc)
1407 {
1408         u32 *bdl = *bdlp;
1409
1410         while (size > 0) {
1411                 dma_addr_t addr;
1412                 int chunk;
1413
1414                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1415                         return -EINVAL;
1416
1417                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1418                 /* program the address field of the BDL entry */
1419                 bdl[0] = cpu_to_le32((u32)addr);
1420                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1421                 /* program the size field of the BDL entry */
1422                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1423                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1424                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1425                         u32 remain = 0x1000 - (ofs & 0xfff);
1426                         if (chunk > remain)
1427                                 chunk = remain;
1428                 }
1429                 bdl[2] = cpu_to_le32(chunk);
1430                 /* program the IOC to enable interrupt
1431                  * only when the whole fragment is processed
1432                  */
1433                 size -= chunk;
1434                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1435                 bdl += 4;
1436                 azx_dev->frags++;
1437                 ofs += chunk;
1438         }
1439         *bdlp = bdl;
1440         return ofs;
1441 }
1442
1443 /*
1444  * set up BDL entries
1445  */
1446 static int azx_setup_periods(struct azx *chip,
1447                              struct snd_pcm_substream *substream,
1448                              struct azx_dev *azx_dev)
1449 {
1450         u32 *bdl;
1451         int i, ofs, periods, period_bytes;
1452         int pos_adj;
1453
1454         /* reset BDL address */
1455         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1456         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1457
1458         period_bytes = azx_dev->period_bytes;
1459         periods = azx_dev->bufsize / period_bytes;
1460
1461         /* program the initial BDL entries */
1462         bdl = (u32 *)azx_dev->bdl.area;
1463         ofs = 0;
1464         azx_dev->frags = 0;
1465         pos_adj = bdl_pos_adj[chip->dev_index];
1466         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1467                 struct snd_pcm_runtime *runtime = substream->runtime;
1468                 int pos_align = pos_adj;
1469                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1470                 if (!pos_adj)
1471                         pos_adj = pos_align;
1472                 else
1473                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1474                                 pos_align;
1475                 pos_adj = frames_to_bytes(runtime, pos_adj);
1476                 if (pos_adj >= period_bytes) {
1477                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1478                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1479                         pos_adj = 0;
1480                 } else {
1481                         ofs = setup_bdle(chip, substream, azx_dev,
1482                                          &bdl, ofs, pos_adj, true);
1483                         if (ofs < 0)
1484                                 goto error;
1485                 }
1486         } else
1487                 pos_adj = 0;
1488         for (i = 0; i < periods; i++) {
1489                 if (i == periods - 1 && pos_adj)
1490                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1491                                          period_bytes - pos_adj, 0);
1492                 else
1493                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1494                                          period_bytes,
1495                                          !azx_dev->no_period_wakeup);
1496                 if (ofs < 0)
1497                         goto error;
1498         }
1499         return 0;
1500
1501  error:
1502         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1503                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1504         return -EINVAL;
1505 }
1506
1507 /* reset stream */
1508 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1509 {
1510         unsigned char val;
1511         int timeout;
1512
1513         azx_stream_clear(chip, azx_dev);
1514
1515         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1516                       SD_CTL_STREAM_RESET);
1517         udelay(3);
1518         timeout = 300;
1519         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1520                --timeout)
1521                 ;
1522         val &= ~SD_CTL_STREAM_RESET;
1523         azx_sd_writeb(azx_dev, SD_CTL, val);
1524         udelay(3);
1525
1526         timeout = 300;
1527         /* waiting for hardware to report that the stream is out of reset */
1528         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1529                --timeout)
1530                 ;
1531
1532         /* reset first position - may not be synced with hw at this time */
1533         *azx_dev->posbuf = 0;
1534 }
1535
1536 /*
1537  * set up the SD for streaming
1538  */
1539 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1540 {
1541         unsigned int val;
1542         /* make sure the run bit is zero for SD */
1543         azx_stream_clear(chip, azx_dev);
1544         /* program the stream_tag */
1545         val = azx_sd_readl(azx_dev, SD_CTL);
1546         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1547                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1548         if (!azx_snoop(chip))
1549                 val |= SD_CTL_TRAFFIC_PRIO;
1550         azx_sd_writel(azx_dev, SD_CTL, val);
1551
1552         /* program the length of samples in cyclic buffer */
1553         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1554
1555         /* program the stream format */
1556         /* this value needs to be the same as the one programmed */
1557         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1558
1559         /* program the stream LVI (last valid index) of the BDL */
1560         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1561
1562         /* program the BDL address */
1563         /* lower BDL address */
1564         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1565         /* upper BDL address */
1566         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1567
1568         /* enable the position buffer */
1569         if (chip->position_fix[0] != POS_FIX_LPIB ||
1570             chip->position_fix[1] != POS_FIX_LPIB) {
1571                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1572                         azx_writel(chip, DPLBASE,
1573                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1574         }
1575
1576         /* set the interrupt enable bits in the descriptor control register */
1577         azx_sd_writel(azx_dev, SD_CTL,
1578                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1579
1580         return 0;
1581 }
1582
1583 /*
1584  * Probe the given codec address
1585  */
1586 static int probe_codec(struct azx *chip, int addr)
1587 {
1588         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1589                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1590         unsigned int res;
1591
1592         mutex_lock(&chip->bus->cmd_mutex);
1593         chip->probing = 1;
1594         azx_send_cmd(chip->bus, cmd);
1595         res = azx_get_response(chip->bus, addr);
1596         chip->probing = 0;
1597         mutex_unlock(&chip->bus->cmd_mutex);
1598         if (res == -1)
1599                 return -EIO;
1600         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1601         return 0;
1602 }
1603
1604 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1605                                  struct hda_pcm *cpcm);
1606 static void azx_stop_chip(struct azx *chip);
1607
1608 static void azx_bus_reset(struct hda_bus *bus)
1609 {
1610         struct azx *chip = bus->private_data;
1611
1612         bus->in_reset = 1;
1613         azx_stop_chip(chip);
1614         azx_init_chip(chip, 1);
1615 #ifdef CONFIG_PM
1616         if (chip->initialized) {
1617                 struct azx_pcm *p;
1618                 list_for_each_entry(p, &chip->pcm_list, list)
1619                         snd_pcm_suspend_all(p->pcm);
1620                 snd_hda_suspend(chip->bus);
1621                 snd_hda_resume(chip->bus);
1622         }
1623 #endif
1624         bus->in_reset = 0;
1625 }
1626
1627 static int get_jackpoll_interval(struct azx *chip)
1628 {
1629         int i = jackpoll_ms[chip->dev_index];
1630         unsigned int j;
1631         if (i == 0)
1632                 return 0;
1633         if (i < 50 || i > 60000)
1634                 j = 0;
1635         else
1636                 j = msecs_to_jiffies(i);
1637         if (j == 0)
1638                 snd_printk(KERN_WARNING SFX
1639                            "jackpoll_ms value out of range: %d\n", i);
1640         return j;
1641 }
1642
1643 /*
1644  * Codec initialization
1645  */
1646
1647 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1648 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1649         [AZX_DRIVER_NVIDIA] = 8,
1650         [AZX_DRIVER_TERA] = 1,
1651 };
1652
1653 static int azx_codec_create(struct azx *chip, const char *model)
1654 {
1655         struct hda_bus_template bus_temp;
1656         int c, codecs, err;
1657         int max_slots;
1658
1659         memset(&bus_temp, 0, sizeof(bus_temp));
1660         bus_temp.private_data = chip;
1661         bus_temp.modelname = model;
1662         bus_temp.pci = chip->pci;
1663         bus_temp.ops.command = azx_send_cmd;
1664         bus_temp.ops.get_response = azx_get_response;
1665         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1666         bus_temp.ops.bus_reset = azx_bus_reset;
1667 #ifdef CONFIG_PM
1668         bus_temp.power_save = &power_save;
1669         bus_temp.ops.pm_notify = azx_power_notify;
1670 #endif
1671
1672         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1673         if (err < 0)
1674                 return err;
1675
1676         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1677                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1678                 chip->bus->needs_damn_long_delay = 1;
1679         }
1680
1681         codecs = 0;
1682         max_slots = azx_max_codecs[chip->driver_type];
1683         if (!max_slots)
1684                 max_slots = AZX_DEFAULT_CODECS;
1685
1686         /* First try to probe all given codec slots */
1687         for (c = 0; c < max_slots; c++) {
1688                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1689                         if (probe_codec(chip, c) < 0) {
1690                                 /* Some BIOSen give you wrong codec addresses
1691                                  * that don't exist
1692                                  */
1693                                 snd_printk(KERN_WARNING SFX
1694                                            "%s: Codec #%d probe error; "
1695                                            "disabling it...\n", pci_name(chip->pci), c);
1696                                 chip->codec_mask &= ~(1 << c);
1697                                 /* More badly, accessing to a non-existing
1698                                  * codec often screws up the controller chip,
1699                                  * and disturbs the further communications.
1700                                  * Thus if an error occurs during probing,
1701                                  * better to reset the controller chip to
1702                                  * get back to the sanity state.
1703                                  */
1704                                 azx_stop_chip(chip);
1705                                 azx_init_chip(chip, 1);
1706                         }
1707                 }
1708         }
1709
1710         /* AMD chipsets often cause the communication stalls upon certain
1711          * sequence like the pin-detection.  It seems that forcing the synced
1712          * access works around the stall.  Grrr...
1713          */
1714         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1715                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1716                         pci_name(chip->pci));
1717                 chip->bus->sync_write = 1;
1718                 chip->bus->allow_bus_reset = 1;
1719         }
1720
1721         /* Then create codec instances */
1722         for (c = 0; c < max_slots; c++) {
1723                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1724                         struct hda_codec *codec;
1725                         err = snd_hda_codec_new(chip->bus, c, &codec);
1726                         if (err < 0)
1727                                 continue;
1728                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1729                         codec->beep_mode = chip->beep_mode;
1730                         codecs++;
1731                 }
1732         }
1733         if (!codecs) {
1734                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1735                 return -ENXIO;
1736         }
1737         return 0;
1738 }
1739
1740 /* configure each codec instance */
1741 static int azx_codec_configure(struct azx *chip)
1742 {
1743         struct hda_codec *codec;
1744         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1745                 snd_hda_codec_configure(codec);
1746         }
1747         return 0;
1748 }
1749
1750
1751 /*
1752  * PCM support
1753  */
1754
1755 /* assign a stream for the PCM */
1756 static inline struct azx_dev *
1757 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1758 {
1759         int dev, i, nums;
1760         struct azx_dev *res = NULL;
1761         /* make a non-zero unique key for the substream */
1762         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1763                 (substream->stream + 1);
1764
1765         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1766                 dev = chip->playback_index_offset;
1767                 nums = chip->playback_streams;
1768         } else {
1769                 dev = chip->capture_index_offset;
1770                 nums = chip->capture_streams;
1771         }
1772         for (i = 0; i < nums; i++, dev++)
1773                 if (!chip->azx_dev[dev].opened) {
1774                         res = &chip->azx_dev[dev];
1775                         if (res->assigned_key == key)
1776                                 break;
1777                 }
1778         if (res) {
1779                 res->opened = 1;
1780                 res->assigned_key = key;
1781         }
1782         return res;
1783 }
1784
1785 /* release the assigned stream */
1786 static inline void azx_release_device(struct azx_dev *azx_dev)
1787 {
1788         azx_dev->opened = 0;
1789 }
1790
1791 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1792 {
1793         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1794         struct snd_pcm_substream *substream = azx_dev->substream;
1795         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1796         struct azx *chip = apcm->chip;
1797
1798         return azx_readl(chip, WALLCLK);
1799 }
1800
1801 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1802                                 bool force, cycle_t last)
1803 {
1804         struct azx_dev *azx_dev = get_azx_dev(substream);
1805         struct timecounter *tc = &azx_dev->azx_tc;
1806         struct cyclecounter *cc = &azx_dev->azx_cc;
1807         u64 nsec;
1808
1809         cc->read = azx_cc_read;
1810         cc->mask = CLOCKSOURCE_MASK(32);
1811
1812         /*
1813          * Converting from 24 MHz to ns means applying a 125/3 factor.
1814          * To avoid any saturation issues in intermediate operations,
1815          * the 125 factor is applied first. The division is applied
1816          * last after reading the timecounter value.
1817          * Applying the 1/3 factor as part of the multiplication
1818          * requires at least 20 bits for a decent precision, however
1819          * overflows occur after about 4 hours or less, not a option.
1820          */
1821
1822         cc->mult = 125; /* saturation after 195 years */
1823         cc->shift = 0;
1824
1825         nsec = 0; /* audio time is elapsed time since trigger */
1826         timecounter_init(tc, cc, nsec);
1827         if (force)
1828                 /*
1829                  * force timecounter to use predefined value,
1830                  * used for synchronized starts
1831                  */
1832                 tc->cycle_last = last;
1833 }
1834
1835 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1836                                 struct timespec *ts)
1837 {
1838         struct azx_dev *azx_dev = get_azx_dev(substream);
1839         u64 nsec;
1840
1841         nsec = timecounter_read(&azx_dev->azx_tc);
1842         nsec = div_u64(nsec, 3); /* can be optimized */
1843
1844         *ts = ns_to_timespec(nsec);
1845
1846         return 0;
1847 }
1848
1849 static struct snd_pcm_hardware azx_pcm_hw = {
1850         .info =                 (SNDRV_PCM_INFO_MMAP |
1851                                  SNDRV_PCM_INFO_INTERLEAVED |
1852                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1853                                  SNDRV_PCM_INFO_MMAP_VALID |
1854                                  /* No full-resume yet implemented */
1855                                  /* SNDRV_PCM_INFO_RESUME |*/
1856                                  SNDRV_PCM_INFO_PAUSE |
1857                                  SNDRV_PCM_INFO_SYNC_START |
1858                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1859                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1860         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1861         .rates =                SNDRV_PCM_RATE_48000,
1862         .rate_min =             48000,
1863         .rate_max =             48000,
1864         .channels_min =         2,
1865         .channels_max =         2,
1866         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1867         .period_bytes_min =     128,
1868         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1869         .periods_min =          2,
1870         .periods_max =          AZX_MAX_FRAG,
1871         .fifo_size =            0,
1872 };
1873
1874 static int azx_pcm_open(struct snd_pcm_substream *substream)
1875 {
1876         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1877         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1878         struct azx *chip = apcm->chip;
1879         struct azx_dev *azx_dev;
1880         struct snd_pcm_runtime *runtime = substream->runtime;
1881         unsigned long flags;
1882         int err;
1883         int buff_step;
1884
1885         mutex_lock(&chip->open_mutex);
1886         azx_dev = azx_assign_device(chip, substream);
1887         if (azx_dev == NULL) {
1888                 mutex_unlock(&chip->open_mutex);
1889                 return -EBUSY;
1890         }
1891         runtime->hw = azx_pcm_hw;
1892         runtime->hw.channels_min = hinfo->channels_min;
1893         runtime->hw.channels_max = hinfo->channels_max;
1894         runtime->hw.formats = hinfo->formats;
1895         runtime->hw.rates = hinfo->rates;
1896         snd_pcm_limit_hw_rates(runtime);
1897         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1898
1899         /* avoid wrap-around with wall-clock */
1900         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1901                                 20,
1902                                 178000000);
1903
1904         if (chip->align_buffer_size)
1905                 /* constrain buffer sizes to be multiple of 128
1906                    bytes. This is more efficient in terms of memory
1907                    access but isn't required by the HDA spec and
1908                    prevents users from specifying exact period/buffer
1909                    sizes. For example for 44.1kHz, a period size set
1910                    to 20ms will be rounded to 19.59ms. */
1911                 buff_step = 128;
1912         else
1913                 /* Don't enforce steps on buffer sizes, still need to
1914                    be multiple of 4 bytes (HDA spec). Tested on Intel
1915                    HDA controllers, may not work on all devices where
1916                    option needs to be disabled */
1917                 buff_step = 4;
1918
1919         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1920                                    buff_step);
1921         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1922                                    buff_step);
1923         snd_hda_power_up_d3wait(apcm->codec);
1924         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1925         if (err < 0) {
1926                 azx_release_device(azx_dev);
1927                 snd_hda_power_down(apcm->codec);
1928                 mutex_unlock(&chip->open_mutex);
1929                 return err;
1930         }
1931         snd_pcm_limit_hw_rates(runtime);
1932         /* sanity check */
1933         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1934             snd_BUG_ON(!runtime->hw.channels_max) ||
1935             snd_BUG_ON(!runtime->hw.formats) ||
1936             snd_BUG_ON(!runtime->hw.rates)) {
1937                 azx_release_device(azx_dev);
1938                 hinfo->ops.close(hinfo, apcm->codec, substream);
1939                 snd_hda_power_down(apcm->codec);
1940                 mutex_unlock(&chip->open_mutex);
1941                 return -EINVAL;
1942         }
1943
1944         /* disable WALLCLOCK timestamps for capture streams
1945            until we figure out how to handle digital inputs */
1946         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1947                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1948
1949         spin_lock_irqsave(&chip->reg_lock, flags);
1950         azx_dev->substream = substream;
1951         azx_dev->running = 0;
1952         spin_unlock_irqrestore(&chip->reg_lock, flags);
1953
1954         runtime->private_data = azx_dev;
1955         snd_pcm_set_sync(substream);
1956         mutex_unlock(&chip->open_mutex);
1957         return 0;
1958 }
1959
1960 static int azx_pcm_close(struct snd_pcm_substream *substream)
1961 {
1962         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1963         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1964         struct azx *chip = apcm->chip;
1965         struct azx_dev *azx_dev = get_azx_dev(substream);
1966         unsigned long flags;
1967
1968         mutex_lock(&chip->open_mutex);
1969         spin_lock_irqsave(&chip->reg_lock, flags);
1970         azx_dev->substream = NULL;
1971         azx_dev->running = 0;
1972         spin_unlock_irqrestore(&chip->reg_lock, flags);
1973         azx_release_device(azx_dev);
1974         hinfo->ops.close(hinfo, apcm->codec, substream);
1975         snd_hda_power_down(apcm->codec);
1976         mutex_unlock(&chip->open_mutex);
1977         return 0;
1978 }
1979
1980 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1981                              struct snd_pcm_hw_params *hw_params)
1982 {
1983         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1984         struct azx *chip = apcm->chip;
1985         struct azx_dev *azx_dev = get_azx_dev(substream);
1986         int ret;
1987
1988         mark_runtime_wc(chip, azx_dev, substream, false);
1989         azx_dev->bufsize = 0;
1990         azx_dev->period_bytes = 0;
1991         azx_dev->format_val = 0;
1992         ret = snd_pcm_lib_malloc_pages(substream,
1993                                         params_buffer_bytes(hw_params));
1994         if (ret < 0)
1995                 return ret;
1996         mark_runtime_wc(chip, azx_dev, substream, true);
1997         return ret;
1998 }
1999
2000 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2001 {
2002         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2003         struct azx_dev *azx_dev = get_azx_dev(substream);
2004         struct azx *chip = apcm->chip;
2005         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2006
2007         /* reset BDL address */
2008         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2009         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2010         azx_sd_writel(azx_dev, SD_CTL, 0);
2011         azx_dev->bufsize = 0;
2012         azx_dev->period_bytes = 0;
2013         azx_dev->format_val = 0;
2014
2015         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2016
2017         mark_runtime_wc(chip, azx_dev, substream, false);
2018         return snd_pcm_lib_free_pages(substream);
2019 }
2020
2021 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2022 {
2023         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2024         struct azx *chip = apcm->chip;
2025         struct azx_dev *azx_dev = get_azx_dev(substream);
2026         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2027         struct snd_pcm_runtime *runtime = substream->runtime;
2028         unsigned int bufsize, period_bytes, format_val, stream_tag;
2029         int err;
2030         struct hda_spdif_out *spdif =
2031                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2032         unsigned short ctls = spdif ? spdif->ctls : 0;
2033
2034         azx_stream_reset(chip, azx_dev);
2035         format_val = snd_hda_calc_stream_format(runtime->rate,
2036                                                 runtime->channels,
2037                                                 runtime->format,
2038                                                 hinfo->maxbps,
2039                                                 ctls);
2040         if (!format_val) {
2041                 snd_printk(KERN_ERR SFX
2042                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2043                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2044                 return -EINVAL;
2045         }
2046
2047         bufsize = snd_pcm_lib_buffer_bytes(substream);
2048         period_bytes = snd_pcm_lib_period_bytes(substream);
2049
2050         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2051                     pci_name(chip->pci), bufsize, format_val);
2052
2053         if (bufsize != azx_dev->bufsize ||
2054             period_bytes != azx_dev->period_bytes ||
2055             format_val != azx_dev->format_val ||
2056             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2057                 azx_dev->bufsize = bufsize;
2058                 azx_dev->period_bytes = period_bytes;
2059                 azx_dev->format_val = format_val;
2060                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2061                 err = azx_setup_periods(chip, substream, azx_dev);
2062                 if (err < 0)
2063                         return err;
2064         }
2065
2066         /* wallclk has 24Mhz clock source */
2067         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2068                                                 runtime->rate) * 1000);
2069         azx_setup_controller(chip, azx_dev);
2070         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2071                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2072         else
2073                 azx_dev->fifo_size = 0;
2074
2075         stream_tag = azx_dev->stream_tag;
2076         /* CA-IBG chips need the playback stream starting from 1 */
2077         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2078             stream_tag > chip->capture_streams)
2079                 stream_tag -= chip->capture_streams;
2080         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2081                                      azx_dev->format_val, substream);
2082 }
2083
2084 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2085 {
2086         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2087         struct azx *chip = apcm->chip;
2088         struct azx_dev *azx_dev;
2089         struct snd_pcm_substream *s;
2090         int rstart = 0, start, nsync = 0, sbits = 0;
2091         int nwait, timeout;
2092
2093         azx_dev = get_azx_dev(substream);
2094         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2095
2096         switch (cmd) {
2097         case SNDRV_PCM_TRIGGER_START:
2098                 rstart = 1;
2099         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2100         case SNDRV_PCM_TRIGGER_RESUME:
2101                 start = 1;
2102                 break;
2103         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2104         case SNDRV_PCM_TRIGGER_SUSPEND:
2105         case SNDRV_PCM_TRIGGER_STOP:
2106                 start = 0;
2107                 break;
2108         default:
2109                 return -EINVAL;
2110         }
2111
2112         snd_pcm_group_for_each_entry(s, substream) {
2113                 if (s->pcm->card != substream->pcm->card)
2114                         continue;
2115                 azx_dev = get_azx_dev(s);
2116                 sbits |= 1 << azx_dev->index;
2117                 nsync++;
2118                 snd_pcm_trigger_done(s, substream);
2119         }
2120
2121         spin_lock(&chip->reg_lock);
2122
2123         /* first, set SYNC bits of corresponding streams */
2124         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2125                 azx_writel(chip, OLD_SSYNC,
2126                         azx_readl(chip, OLD_SSYNC) | sbits);
2127         else
2128                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2129
2130         snd_pcm_group_for_each_entry(s, substream) {
2131                 if (s->pcm->card != substream->pcm->card)
2132                         continue;
2133                 azx_dev = get_azx_dev(s);
2134                 if (start) {
2135                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2136                         if (!rstart)
2137                                 azx_dev->start_wallclk -=
2138                                                 azx_dev->period_wallclk;
2139                         azx_stream_start(chip, azx_dev);
2140                 } else {
2141                         azx_stream_stop(chip, azx_dev);
2142                 }
2143                 azx_dev->running = start;
2144         }
2145         spin_unlock(&chip->reg_lock);
2146         if (start) {
2147                 /* wait until all FIFOs get ready */
2148                 for (timeout = 5000; timeout; timeout--) {
2149                         nwait = 0;
2150                         snd_pcm_group_for_each_entry(s, substream) {
2151                                 if (s->pcm->card != substream->pcm->card)
2152                                         continue;
2153                                 azx_dev = get_azx_dev(s);
2154                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2155                                       SD_STS_FIFO_READY))
2156                                         nwait++;
2157                         }
2158                         if (!nwait)
2159                                 break;
2160                         cpu_relax();
2161                 }
2162         } else {
2163                 /* wait until all RUN bits are cleared */
2164                 for (timeout = 5000; timeout; timeout--) {
2165                         nwait = 0;
2166                         snd_pcm_group_for_each_entry(s, substream) {
2167                                 if (s->pcm->card != substream->pcm->card)
2168                                         continue;
2169                                 azx_dev = get_azx_dev(s);
2170                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2171                                     SD_CTL_DMA_START)
2172                                         nwait++;
2173                         }
2174                         if (!nwait)
2175                                 break;
2176                         cpu_relax();
2177                 }
2178         }
2179         spin_lock(&chip->reg_lock);
2180         /* reset SYNC bits */
2181         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2182                 azx_writel(chip, OLD_SSYNC,
2183                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2184         else
2185                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2186         if (start) {
2187                 azx_timecounter_init(substream, 0, 0);
2188                 if (nsync > 1) {
2189                         cycle_t cycle_last;
2190
2191                         /* same start cycle for master and group */
2192                         azx_dev = get_azx_dev(substream);
2193                         cycle_last = azx_dev->azx_tc.cycle_last;
2194
2195                         snd_pcm_group_for_each_entry(s, substream) {
2196                                 if (s->pcm->card != substream->pcm->card)
2197                                         continue;
2198                                 azx_timecounter_init(s, 1, cycle_last);
2199                         }
2200                 }
2201         }
2202         spin_unlock(&chip->reg_lock);
2203         return 0;
2204 }
2205
2206 /* get the current DMA position with correction on VIA chips */
2207 static unsigned int azx_via_get_position(struct azx *chip,
2208                                          struct azx_dev *azx_dev)
2209 {
2210         unsigned int link_pos, mini_pos, bound_pos;
2211         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2212         unsigned int fifo_size;
2213
2214         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2215         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2216                 /* Playback, no problem using link position */
2217                 return link_pos;
2218         }
2219
2220         /* Capture */
2221         /* For new chipset,
2222          * use mod to get the DMA position just like old chipset
2223          */
2224         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2225         mod_dma_pos %= azx_dev->period_bytes;
2226
2227         /* azx_dev->fifo_size can't get FIFO size of in stream.
2228          * Get from base address + offset.
2229          */
2230         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2231
2232         if (azx_dev->insufficient) {
2233                 /* Link position never gather than FIFO size */
2234                 if (link_pos <= fifo_size)
2235                         return 0;
2236
2237                 azx_dev->insufficient = 0;
2238         }
2239
2240         if (link_pos <= fifo_size)
2241                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2242         else
2243                 mini_pos = link_pos - fifo_size;
2244
2245         /* Find nearest previous boudary */
2246         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2247         mod_link_pos = link_pos % azx_dev->period_bytes;
2248         if (mod_link_pos >= fifo_size)
2249                 bound_pos = link_pos - mod_link_pos;
2250         else if (mod_dma_pos >= mod_mini_pos)
2251                 bound_pos = mini_pos - mod_mini_pos;
2252         else {
2253                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2254                 if (bound_pos >= azx_dev->bufsize)
2255                         bound_pos = 0;
2256         }
2257
2258         /* Calculate real DMA position we want */
2259         return bound_pos + mod_dma_pos;
2260 }
2261
2262 static unsigned int azx_get_position(struct azx *chip,
2263                                      struct azx_dev *azx_dev,
2264                                      bool with_check)
2265 {
2266         unsigned int pos;
2267         int stream = azx_dev->substream->stream;
2268         int delay = 0;
2269
2270         switch (chip->position_fix[stream]) {
2271         case POS_FIX_LPIB:
2272                 /* read LPIB */
2273                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2274                 break;
2275         case POS_FIX_VIACOMBO:
2276                 pos = azx_via_get_position(chip, azx_dev);
2277                 break;
2278         default:
2279                 /* use the position buffer */
2280                 pos = le32_to_cpu(*azx_dev->posbuf);
2281                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2282                         if (!pos || pos == (u32)-1) {
2283                                 printk(KERN_WARNING
2284                                        "hda-intel: Invalid position buffer, "
2285                                        "using LPIB read method instead.\n");
2286                                 chip->position_fix[stream] = POS_FIX_LPIB;
2287                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2288                         } else
2289                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2290                 }
2291                 break;
2292         }
2293
2294         if (pos >= azx_dev->bufsize)
2295                 pos = 0;
2296
2297         /* calculate runtime delay from LPIB */
2298         if (azx_dev->substream->runtime &&
2299             chip->position_fix[stream] == POS_FIX_POSBUF &&
2300             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2301                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2302                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2303                         delay = pos - lpib_pos;
2304                 else
2305                         delay = lpib_pos - pos;
2306                 if (delay < 0)
2307                         delay += azx_dev->bufsize;
2308                 if (delay >= azx_dev->period_bytes) {
2309                         snd_printk(KERN_WARNING SFX
2310                                    "%s: Unstable LPIB (%d >= %d); "
2311                                    "disabling LPIB delay counting\n",
2312                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2313                         delay = 0;
2314                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2315                 }
2316                 azx_dev->substream->runtime->delay =
2317                         bytes_to_frames(azx_dev->substream->runtime, delay);
2318         }
2319         trace_azx_get_position(chip, azx_dev, pos, delay);
2320         return pos;
2321 }
2322
2323 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2324 {
2325         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2326         struct azx *chip = apcm->chip;
2327         struct azx_dev *azx_dev = get_azx_dev(substream);
2328         return bytes_to_frames(substream->runtime,
2329                                azx_get_position(chip, azx_dev, false));
2330 }
2331
2332 /*
2333  * Check whether the current DMA position is acceptable for updating
2334  * periods.  Returns non-zero if it's OK.
2335  *
2336  * Many HD-audio controllers appear pretty inaccurate about
2337  * the update-IRQ timing.  The IRQ is issued before actually the
2338  * data is processed.  So, we need to process it afterwords in a
2339  * workqueue.
2340  */
2341 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2342 {
2343         u32 wallclk;
2344         unsigned int pos;
2345
2346         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2347         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2348                 return -1;      /* bogus (too early) interrupt */
2349
2350         pos = azx_get_position(chip, azx_dev, true);
2351
2352         if (WARN_ONCE(!azx_dev->period_bytes,
2353                       "hda-intel: zero azx_dev->period_bytes"))
2354                 return -1; /* this shouldn't happen! */
2355         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2356             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2357                 /* NG - it's below the first next period boundary */
2358                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2359         azx_dev->start_wallclk += wallclk;
2360         return 1; /* OK, it's fine */
2361 }
2362
2363 /*
2364  * The work for pending PCM period updates.
2365  */
2366 static void azx_irq_pending_work(struct work_struct *work)
2367 {
2368         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2369         int i, pending, ok;
2370
2371         if (!chip->irq_pending_warned) {
2372                 printk(KERN_WARNING
2373                        "hda-intel: IRQ timing workaround is activated "
2374                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2375                        chip->card->number);
2376                 chip->irq_pending_warned = 1;
2377         }
2378
2379         for (;;) {
2380                 pending = 0;
2381                 spin_lock_irq(&chip->reg_lock);
2382                 for (i = 0; i < chip->num_streams; i++) {
2383                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2384                         if (!azx_dev->irq_pending ||
2385                             !azx_dev->substream ||
2386                             !azx_dev->running)
2387                                 continue;
2388                         ok = azx_position_ok(chip, azx_dev);
2389                         if (ok > 0) {
2390                                 azx_dev->irq_pending = 0;
2391                                 spin_unlock(&chip->reg_lock);
2392                                 snd_pcm_period_elapsed(azx_dev->substream);
2393                                 spin_lock(&chip->reg_lock);
2394                         } else if (ok < 0) {
2395                                 pending = 0;    /* too early */
2396                         } else
2397                                 pending++;
2398                 }
2399                 spin_unlock_irq(&chip->reg_lock);
2400                 if (!pending)
2401                         return;
2402                 msleep(1);
2403         }
2404 }
2405
2406 /* clear irq_pending flags and assure no on-going workq */
2407 static void azx_clear_irq_pending(struct azx *chip)
2408 {
2409         int i;
2410
2411         spin_lock_irq(&chip->reg_lock);
2412         for (i = 0; i < chip->num_streams; i++)
2413                 chip->azx_dev[i].irq_pending = 0;
2414         spin_unlock_irq(&chip->reg_lock);
2415 }
2416
2417 #ifdef CONFIG_X86
2418 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2419                         struct vm_area_struct *area)
2420 {
2421         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2422         struct azx *chip = apcm->chip;
2423         if (!azx_snoop(chip))
2424                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2425         return snd_pcm_lib_default_mmap(substream, area);
2426 }
2427 #else
2428 #define azx_pcm_mmap    NULL
2429 #endif
2430
2431 static struct snd_pcm_ops azx_pcm_ops = {
2432         .open = azx_pcm_open,
2433         .close = azx_pcm_close,
2434         .ioctl = snd_pcm_lib_ioctl,
2435         .hw_params = azx_pcm_hw_params,
2436         .hw_free = azx_pcm_hw_free,
2437         .prepare = azx_pcm_prepare,
2438         .trigger = azx_pcm_trigger,
2439         .pointer = azx_pcm_pointer,
2440         .wall_clock =  azx_get_wallclock_tstamp,
2441         .mmap = azx_pcm_mmap,
2442         .page = snd_pcm_sgbuf_ops_page,
2443 };
2444
2445 static void azx_pcm_free(struct snd_pcm *pcm)
2446 {
2447         struct azx_pcm *apcm = pcm->private_data;
2448         if (apcm) {
2449                 list_del(&apcm->list);
2450                 kfree(apcm);
2451         }
2452 }
2453
2454 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2455
2456 static int
2457 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2458                       struct hda_pcm *cpcm)
2459 {
2460         struct azx *chip = bus->private_data;
2461         struct snd_pcm *pcm;
2462         struct azx_pcm *apcm;
2463         int pcm_dev = cpcm->device;
2464         unsigned int size;
2465         int s, err;
2466
2467         list_for_each_entry(apcm, &chip->pcm_list, list) {
2468                 if (apcm->pcm->device == pcm_dev) {
2469                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2470                                    pci_name(chip->pci), pcm_dev);
2471                         return -EBUSY;
2472                 }
2473         }
2474         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2475                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2476                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2477                           &pcm);
2478         if (err < 0)
2479                 return err;
2480         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2481         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2482         if (apcm == NULL)
2483                 return -ENOMEM;
2484         apcm->chip = chip;
2485         apcm->pcm = pcm;
2486         apcm->codec = codec;
2487         pcm->private_data = apcm;
2488         pcm->private_free = azx_pcm_free;
2489         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2490                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2491         list_add_tail(&apcm->list, &chip->pcm_list);
2492         cpcm->pcm = pcm;
2493         for (s = 0; s < 2; s++) {
2494                 apcm->hinfo[s] = &cpcm->stream[s];
2495                 if (cpcm->stream[s].substreams)
2496                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2497         }
2498         /* buffer pre-allocation */
2499         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2500         if (size > MAX_PREALLOC_SIZE)
2501                 size = MAX_PREALLOC_SIZE;
2502         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2503                                               snd_dma_pci_data(chip->pci),
2504                                               size, MAX_PREALLOC_SIZE);
2505         return 0;
2506 }
2507
2508 /*
2509  * mixer creation - all stuff is implemented in hda module
2510  */
2511 static int azx_mixer_create(struct azx *chip)
2512 {
2513         return snd_hda_build_controls(chip->bus);
2514 }
2515
2516
2517 /*
2518  * initialize SD streams
2519  */
2520 static int azx_init_stream(struct azx *chip)
2521 {
2522         int i;
2523
2524         /* initialize each stream (aka device)
2525          * assign the starting bdl address to each stream (device)
2526          * and initialize
2527          */
2528         for (i = 0; i < chip->num_streams; i++) {
2529                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2530                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2531                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2532                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2533                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2534                 azx_dev->sd_int_sta_mask = 1 << i;
2535                 /* stream tag: must be non-zero and unique */
2536                 azx_dev->index = i;
2537                 azx_dev->stream_tag = i + 1;
2538         }
2539
2540         return 0;
2541 }
2542
2543 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2544 {
2545         if (request_irq(chip->pci->irq, azx_interrupt,
2546                         chip->msi ? 0 : IRQF_SHARED,
2547                         KBUILD_MODNAME, chip)) {
2548                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2549                        "disabling device\n", chip->pci->irq);
2550                 if (do_disconnect)
2551                         snd_card_disconnect(chip->card);
2552                 return -1;
2553         }
2554         chip->irq = chip->pci->irq;
2555         pci_intx(chip->pci, !chip->msi);
2556         return 0;
2557 }
2558
2559
2560 static void azx_stop_chip(struct azx *chip)
2561 {
2562         if (!chip->initialized)
2563                 return;
2564
2565         /* disable interrupts */
2566         azx_int_disable(chip);
2567         azx_int_clear(chip);
2568
2569         /* disable CORB/RIRB */
2570         azx_free_cmd_io(chip);
2571
2572         /* disable position buffer */
2573         azx_writel(chip, DPLBASE, 0);
2574         azx_writel(chip, DPUBASE, 0);
2575
2576         chip->initialized = 0;
2577 }
2578
2579 #ifdef CONFIG_PM
2580 /* power-up/down the controller */
2581 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2582 {
2583         struct azx *chip = bus->private_data;
2584
2585         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2586                 return;
2587
2588         if (power_up)
2589                 pm_runtime_get_sync(&chip->pci->dev);
2590         else
2591                 pm_runtime_put_sync(&chip->pci->dev);
2592 }
2593
2594 static DEFINE_MUTEX(card_list_lock);
2595 static LIST_HEAD(card_list);
2596
2597 static void azx_add_card_list(struct azx *chip)
2598 {
2599         mutex_lock(&card_list_lock);
2600         list_add(&chip->list, &card_list);
2601         mutex_unlock(&card_list_lock);
2602 }
2603
2604 static void azx_del_card_list(struct azx *chip)
2605 {
2606         mutex_lock(&card_list_lock);
2607         list_del_init(&chip->list);
2608         mutex_unlock(&card_list_lock);
2609 }
2610
2611 /* trigger power-save check at writing parameter */
2612 static int param_set_xint(const char *val, const struct kernel_param *kp)
2613 {
2614         struct azx *chip;
2615         struct hda_codec *c;
2616         int prev = power_save;
2617         int ret = param_set_int(val, kp);
2618
2619         if (ret || prev == power_save)
2620                 return ret;
2621
2622         mutex_lock(&card_list_lock);
2623         list_for_each_entry(chip, &card_list, list) {
2624                 if (!chip->bus || chip->disabled)
2625                         continue;
2626                 list_for_each_entry(c, &chip->bus->codec_list, list)
2627                         snd_hda_power_sync(c);
2628         }
2629         mutex_unlock(&card_list_lock);
2630         return 0;
2631 }
2632 #else
2633 #define azx_add_card_list(chip) /* NOP */
2634 #define azx_del_card_list(chip) /* NOP */
2635 #endif /* CONFIG_PM */
2636
2637 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2638 /*
2639  * power management
2640  */
2641 static int azx_suspend(struct device *dev)
2642 {
2643         struct pci_dev *pci = to_pci_dev(dev);
2644         struct snd_card *card = dev_get_drvdata(dev);
2645         struct azx *chip = card->private_data;
2646         struct azx_pcm *p;
2647
2648         if (chip->disabled)
2649                 return 0;
2650
2651         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2652         azx_clear_irq_pending(chip);
2653         list_for_each_entry(p, &chip->pcm_list, list)
2654                 snd_pcm_suspend_all(p->pcm);
2655         if (chip->initialized)
2656                 snd_hda_suspend(chip->bus);
2657         azx_stop_chip(chip);
2658         if (chip->irq >= 0) {
2659                 free_irq(chip->irq, chip);
2660                 chip->irq = -1;
2661         }
2662         if (chip->msi)
2663                 pci_disable_msi(chip->pci);
2664         pci_disable_device(pci);
2665         pci_save_state(pci);
2666         pci_set_power_state(pci, PCI_D3hot);
2667         return 0;
2668 }
2669
2670 static int azx_resume(struct device *dev)
2671 {
2672         struct pci_dev *pci = to_pci_dev(dev);
2673         struct snd_card *card = dev_get_drvdata(dev);
2674         struct azx *chip = card->private_data;
2675
2676         if (chip->disabled)
2677                 return 0;
2678
2679         pci_set_power_state(pci, PCI_D0);
2680         pci_restore_state(pci);
2681         if (pci_enable_device(pci) < 0) {
2682                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2683                        "disabling device\n");
2684                 snd_card_disconnect(card);
2685                 return -EIO;
2686         }
2687         pci_set_master(pci);
2688         if (chip->msi)
2689                 if (pci_enable_msi(pci) < 0)
2690                         chip->msi = 0;
2691         if (azx_acquire_irq(chip, 1) < 0)
2692                 return -EIO;
2693         azx_init_pci(chip);
2694
2695         azx_init_chip(chip, 1);
2696
2697         snd_hda_resume(chip->bus);
2698         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2699         return 0;
2700 }
2701 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2702
2703 #ifdef CONFIG_PM_RUNTIME
2704 static int azx_runtime_suspend(struct device *dev)
2705 {
2706         struct snd_card *card = dev_get_drvdata(dev);
2707         struct azx *chip = card->private_data;
2708
2709         azx_stop_chip(chip);
2710         azx_clear_irq_pending(chip);
2711         return 0;
2712 }
2713
2714 static int azx_runtime_resume(struct device *dev)
2715 {
2716         struct snd_card *card = dev_get_drvdata(dev);
2717         struct azx *chip = card->private_data;
2718
2719         azx_init_pci(chip);
2720         azx_init_chip(chip, 1);
2721         return 0;
2722 }
2723
2724 static int azx_runtime_idle(struct device *dev)
2725 {
2726         struct snd_card *card = dev_get_drvdata(dev);
2727         struct azx *chip = card->private_data;
2728
2729         if (!power_save_controller ||
2730             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2731                 return -EBUSY;
2732
2733         return 0;
2734 }
2735
2736 #endif /* CONFIG_PM_RUNTIME */
2737
2738 #ifdef CONFIG_PM
2739 static const struct dev_pm_ops azx_pm = {
2740         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2741         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2742 };
2743
2744 #define AZX_PM_OPS      &azx_pm
2745 #else
2746 #define AZX_PM_OPS      NULL
2747 #endif /* CONFIG_PM */
2748
2749
2750 /*
2751  * reboot notifier for hang-up problem at power-down
2752  */
2753 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2754 {
2755         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2756         snd_hda_bus_reboot_notify(chip->bus);
2757         azx_stop_chip(chip);
2758         return NOTIFY_OK;
2759 }
2760
2761 static void azx_notifier_register(struct azx *chip)
2762 {
2763         chip->reboot_notifier.notifier_call = azx_halt;
2764         register_reboot_notifier(&chip->reboot_notifier);
2765 }
2766
2767 static void azx_notifier_unregister(struct azx *chip)
2768 {
2769         if (chip->reboot_notifier.notifier_call)
2770                 unregister_reboot_notifier(&chip->reboot_notifier);
2771 }
2772
2773 static int azx_first_init(struct azx *chip);
2774 static int azx_probe_continue(struct azx *chip);
2775
2776 #ifdef SUPPORT_VGA_SWITCHEROO
2777 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2778
2779 static void azx_vs_set_state(struct pci_dev *pci,
2780                              enum vga_switcheroo_state state)
2781 {
2782         struct snd_card *card = pci_get_drvdata(pci);
2783         struct azx *chip = card->private_data;
2784         bool disabled;
2785
2786         wait_for_completion(&chip->probe_wait);
2787         if (chip->init_failed)
2788                 return;
2789
2790         disabled = (state == VGA_SWITCHEROO_OFF);
2791         if (chip->disabled == disabled)
2792                 return;
2793
2794         if (!chip->bus) {
2795                 chip->disabled = disabled;
2796                 if (!disabled) {
2797                         snd_printk(KERN_INFO SFX
2798                                    "%s: Start delayed initialization\n",
2799                                    pci_name(chip->pci));
2800                         if (azx_first_init(chip) < 0 ||
2801                             azx_probe_continue(chip) < 0) {
2802                                 snd_printk(KERN_ERR SFX
2803                                            "%s: initialization error\n",
2804                                            pci_name(chip->pci));
2805                                 chip->init_failed = true;
2806                         }
2807                 }
2808         } else {
2809                 snd_printk(KERN_INFO SFX
2810                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2811                            disabled ? "Disabling" : "Enabling");
2812                 if (disabled) {
2813                         azx_suspend(&pci->dev);
2814                         chip->disabled = true;
2815                         if (snd_hda_lock_devices(chip->bus))
2816                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2817                                            pci_name(chip->pci));
2818                 } else {
2819                         snd_hda_unlock_devices(chip->bus);
2820                         chip->disabled = false;
2821                         azx_resume(&pci->dev);
2822                 }
2823         }
2824 }
2825
2826 static bool azx_vs_can_switch(struct pci_dev *pci)
2827 {
2828         struct snd_card *card = pci_get_drvdata(pci);
2829         struct azx *chip = card->private_data;
2830
2831         wait_for_completion(&chip->probe_wait);
2832         if (chip->init_failed)
2833                 return false;
2834         if (chip->disabled || !chip->bus)
2835                 return true;
2836         if (snd_hda_lock_devices(chip->bus))
2837                 return false;
2838         snd_hda_unlock_devices(chip->bus);
2839         return true;
2840 }
2841
2842 static void init_vga_switcheroo(struct azx *chip)
2843 {
2844         struct pci_dev *p = get_bound_vga(chip->pci);
2845         if (p) {
2846                 snd_printk(KERN_INFO SFX
2847                            "%s: Handle VGA-switcheroo audio client\n",
2848                            pci_name(chip->pci));
2849                 chip->use_vga_switcheroo = 1;
2850                 pci_dev_put(p);
2851         }
2852 }
2853
2854 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2855         .set_gpu_state = azx_vs_set_state,
2856         .can_switch = azx_vs_can_switch,
2857 };
2858
2859 static int register_vga_switcheroo(struct azx *chip)
2860 {
2861         int err;
2862
2863         if (!chip->use_vga_switcheroo)
2864                 return 0;
2865         /* FIXME: currently only handling DIS controller
2866          * is there any machine with two switchable HDMI audio controllers?
2867          */
2868         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2869                                                     VGA_SWITCHEROO_DIS,
2870                                                     chip->bus != NULL);
2871         if (err < 0)
2872                 return err;
2873         chip->vga_switcheroo_registered = 1;
2874         return 0;
2875 }
2876 #else
2877 #define init_vga_switcheroo(chip)               /* NOP */
2878 #define register_vga_switcheroo(chip)           0
2879 #define check_hdmi_disabled(pci)        false
2880 #endif /* SUPPORT_VGA_SWITCHER */
2881
2882 /*
2883  * destructor
2884  */
2885 static int azx_free(struct azx *chip)
2886 {
2887         int i;
2888
2889         azx_del_card_list(chip);
2890
2891         azx_notifier_unregister(chip);
2892
2893         chip->init_failed = 1; /* to be sure */
2894         complete_all(&chip->probe_wait);
2895
2896         if (use_vga_switcheroo(chip)) {
2897                 if (chip->disabled && chip->bus)
2898                         snd_hda_unlock_devices(chip->bus);
2899                 if (chip->vga_switcheroo_registered)
2900                         vga_switcheroo_unregister_client(chip->pci);
2901         }
2902
2903         if (chip->initialized) {
2904                 azx_clear_irq_pending(chip);
2905                 for (i = 0; i < chip->num_streams; i++)
2906                         azx_stream_stop(chip, &chip->azx_dev[i]);
2907                 azx_stop_chip(chip);
2908         }
2909
2910         if (chip->irq >= 0)
2911                 free_irq(chip->irq, (void*)chip);
2912         if (chip->msi)
2913                 pci_disable_msi(chip->pci);
2914         if (chip->remap_addr)
2915                 iounmap(chip->remap_addr);
2916
2917         if (chip->azx_dev) {
2918                 for (i = 0; i < chip->num_streams; i++)
2919                         if (chip->azx_dev[i].bdl.area) {
2920                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2921                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2922                         }
2923         }
2924         if (chip->rb.area) {
2925                 mark_pages_wc(chip, &chip->rb, false);
2926                 snd_dma_free_pages(&chip->rb);
2927         }
2928         if (chip->posbuf.area) {
2929                 mark_pages_wc(chip, &chip->posbuf, false);
2930                 snd_dma_free_pages(&chip->posbuf);
2931         }
2932         if (chip->region_requested)
2933                 pci_release_regions(chip->pci);
2934         pci_disable_device(chip->pci);
2935         kfree(chip->azx_dev);
2936 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2937         if (chip->fw)
2938                 release_firmware(chip->fw);
2939 #endif
2940         kfree(chip);
2941
2942         return 0;
2943 }
2944
2945 static int azx_dev_free(struct snd_device *device)
2946 {
2947         return azx_free(device->device_data);
2948 }
2949
2950 #ifdef SUPPORT_VGA_SWITCHEROO
2951 /*
2952  * Check of disabled HDMI controller by vga-switcheroo
2953  */
2954 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2955 {
2956         struct pci_dev *p;
2957
2958         /* check only discrete GPU */
2959         switch (pci->vendor) {
2960         case PCI_VENDOR_ID_ATI:
2961         case PCI_VENDOR_ID_AMD:
2962         case PCI_VENDOR_ID_NVIDIA:
2963                 if (pci->devfn == 1) {
2964                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2965                                                         pci->bus->number, 0);
2966                         if (p) {
2967                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2968                                         return p;
2969                                 pci_dev_put(p);
2970                         }
2971                 }
2972                 break;
2973         }
2974         return NULL;
2975 }
2976
2977 static bool check_hdmi_disabled(struct pci_dev *pci)
2978 {
2979         bool vga_inactive = false;
2980         struct pci_dev *p = get_bound_vga(pci);
2981
2982         if (p) {
2983                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2984                         vga_inactive = true;
2985                 pci_dev_put(p);
2986         }
2987         return vga_inactive;
2988 }
2989 #endif /* SUPPORT_VGA_SWITCHEROO */
2990
2991 /*
2992  * white/black-listing for position_fix
2993  */
2994 static struct snd_pci_quirk position_fix_list[] = {
2995         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2996         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2997         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2998         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2999         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3000         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3001         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3002         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3003         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3004         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3005         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3006         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3007         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3008         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3009         {}
3010 };
3011
3012 static int check_position_fix(struct azx *chip, int fix)
3013 {
3014         const struct snd_pci_quirk *q;
3015
3016         switch (fix) {
3017         case POS_FIX_AUTO:
3018         case POS_FIX_LPIB:
3019         case POS_FIX_POSBUF:
3020         case POS_FIX_VIACOMBO:
3021         case POS_FIX_COMBO:
3022                 return fix;
3023         }
3024
3025         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3026         if (q) {
3027                 printk(KERN_INFO
3028                        "hda_intel: position_fix set to %d "
3029                        "for device %04x:%04x\n",
3030                        q->value, q->subvendor, q->subdevice);
3031                 return q->value;
3032         }
3033
3034         /* Check VIA/ATI HD Audio Controller exist */
3035         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3036                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3037                 return POS_FIX_VIACOMBO;
3038         }
3039         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3040                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3041                 return POS_FIX_LPIB;
3042         }
3043         return POS_FIX_AUTO;
3044 }
3045
3046 /*
3047  * black-lists for probe_mask
3048  */
3049 static struct snd_pci_quirk probe_mask_list[] = {
3050         /* Thinkpad often breaks the controller communication when accessing
3051          * to the non-working (or non-existing) modem codec slot.
3052          */
3053         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3054         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3055         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3056         /* broken BIOS */
3057         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3058         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3059         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3060         /* forced codec slots */
3061         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3062         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3063         /* WinFast VP200 H (Teradici) user reported broken communication */
3064         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3065         {}
3066 };
3067
3068 #define AZX_FORCE_CODEC_MASK    0x100
3069
3070 static void check_probe_mask(struct azx *chip, int dev)
3071 {
3072         const struct snd_pci_quirk *q;
3073
3074         chip->codec_probe_mask = probe_mask[dev];
3075         if (chip->codec_probe_mask == -1) {
3076                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3077                 if (q) {
3078                         printk(KERN_INFO
3079                                "hda_intel: probe_mask set to 0x%x "
3080                                "for device %04x:%04x\n",
3081                                q->value, q->subvendor, q->subdevice);
3082                         chip->codec_probe_mask = q->value;
3083                 }
3084         }
3085
3086         /* check forced option */
3087         if (chip->codec_probe_mask != -1 &&
3088             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3089                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3090                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3091                        chip->codec_mask);
3092         }
3093 }
3094
3095 /*
3096  * white/black-list for enable_msi
3097  */
3098 static struct snd_pci_quirk msi_black_list[] = {
3099         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3100         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3101         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3102         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3103         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3104         {}
3105 };
3106
3107 static void check_msi(struct azx *chip)
3108 {
3109         const struct snd_pci_quirk *q;
3110
3111         if (enable_msi >= 0) {
3112                 chip->msi = !!enable_msi;
3113                 return;
3114         }
3115         chip->msi = 1;  /* enable MSI as default */
3116         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3117         if (q) {
3118                 printk(KERN_INFO
3119                        "hda_intel: msi for device %04x:%04x set to %d\n",
3120                        q->subvendor, q->subdevice, q->value);
3121                 chip->msi = q->value;
3122                 return;
3123         }
3124
3125         /* NVidia chipsets seem to cause troubles with MSI */
3126         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3127                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3128                 chip->msi = 0;
3129         }
3130 }
3131
3132 /* check the snoop mode availability */
3133 static void azx_check_snoop_available(struct azx *chip)
3134 {
3135         bool snoop = chip->snoop;
3136
3137         switch (chip->driver_type) {
3138         case AZX_DRIVER_VIA:
3139                 /* force to non-snoop mode for a new VIA controller
3140                  * when BIOS is set
3141                  */
3142                 if (snoop) {
3143                         u8 val;
3144                         pci_read_config_byte(chip->pci, 0x42, &val);
3145                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3146                                 snoop = false;
3147                 }
3148                 break;
3149         case AZX_DRIVER_ATIHDMI_NS:
3150                 /* new ATI HDMI requires non-snoop */
3151                 snoop = false;
3152                 break;
3153         }
3154
3155         if (snoop != chip->snoop) {
3156                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3157                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3158                 chip->snoop = snoop;
3159         }
3160 }
3161
3162 /*
3163  * constructor
3164  */
3165 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3166                       int dev, unsigned int driver_caps,
3167                       struct azx **rchip)
3168 {
3169         static struct snd_device_ops ops = {
3170                 .dev_free = azx_dev_free,
3171         };
3172         struct azx *chip;
3173         int err;
3174
3175         *rchip = NULL;
3176
3177         err = pci_enable_device(pci);
3178         if (err < 0)
3179                 return err;
3180
3181         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3182         if (!chip) {
3183                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3184                 pci_disable_device(pci);
3185                 return -ENOMEM;
3186         }
3187
3188         spin_lock_init(&chip->reg_lock);
3189         mutex_init(&chip->open_mutex);
3190         chip->card = card;
3191         chip->pci = pci;
3192         chip->irq = -1;
3193         chip->driver_caps = driver_caps;
3194         chip->driver_type = driver_caps & 0xff;
3195         check_msi(chip);
3196         chip->dev_index = dev;
3197         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3198         INIT_LIST_HEAD(&chip->pcm_list);
3199         INIT_LIST_HEAD(&chip->list);
3200         init_vga_switcheroo(chip);
3201         init_completion(&chip->probe_wait);
3202
3203         chip->position_fix[0] = chip->position_fix[1] =
3204                 check_position_fix(chip, position_fix[dev]);
3205         /* combo mode uses LPIB for playback */
3206         if (chip->position_fix[0] == POS_FIX_COMBO) {
3207                 chip->position_fix[0] = POS_FIX_LPIB;
3208                 chip->position_fix[1] = POS_FIX_AUTO;
3209         }
3210
3211         check_probe_mask(chip, dev);
3212
3213         chip->single_cmd = single_cmd;
3214         chip->snoop = hda_snoop;
3215         azx_check_snoop_available(chip);
3216
3217         if (bdl_pos_adj[dev] < 0) {
3218                 switch (chip->driver_type) {
3219                 case AZX_DRIVER_ICH:
3220                 case AZX_DRIVER_PCH:
3221                         bdl_pos_adj[dev] = 1;
3222                         break;
3223                 default:
3224                         bdl_pos_adj[dev] = 32;
3225                         break;
3226                 }
3227         }
3228
3229         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3230         if (err < 0) {
3231                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3232                    pci_name(chip->pci));
3233                 azx_free(chip);
3234                 return err;
3235         }
3236
3237         *rchip = chip;
3238         return 0;
3239 }
3240
3241 static int azx_first_init(struct azx *chip)
3242 {
3243         int dev = chip->dev_index;
3244         struct pci_dev *pci = chip->pci;
3245         struct snd_card *card = chip->card;
3246         int i, err;
3247         unsigned short gcap;
3248
3249 #if BITS_PER_LONG != 64
3250         /* Fix up base address on ULI M5461 */
3251         if (chip->driver_type == AZX_DRIVER_ULI) {
3252                 u16 tmp3;
3253                 pci_read_config_word(pci, 0x40, &tmp3);
3254                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3255                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3256         }
3257 #endif
3258
3259         err = pci_request_regions(pci, "ICH HD audio");
3260         if (err < 0)
3261                 return err;
3262         chip->region_requested = 1;
3263
3264         chip->addr = pci_resource_start(pci, 0);
3265         chip->remap_addr = pci_ioremap_bar(pci, 0);
3266         if (chip->remap_addr == NULL) {
3267                 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3268                 return -ENXIO;
3269         }
3270
3271         if (chip->msi)
3272                 if (pci_enable_msi(pci) < 0)
3273                         chip->msi = 0;
3274
3275         if (azx_acquire_irq(chip, 0) < 0)
3276                 return -EBUSY;
3277
3278         pci_set_master(pci);
3279         synchronize_irq(chip->irq);
3280
3281         gcap = azx_readw(chip, GCAP);
3282         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3283
3284         /* disable SB600 64bit support for safety */
3285         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3286                 struct pci_dev *p_smbus;
3287                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3288                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3289                                          NULL);
3290                 if (p_smbus) {
3291                         if (p_smbus->revision < 0x30)
3292                                 gcap &= ~ICH6_GCAP_64OK;
3293                         pci_dev_put(p_smbus);
3294                 }
3295         }
3296
3297         /* disable 64bit DMA address on some devices */
3298         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3299                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3300                 gcap &= ~ICH6_GCAP_64OK;
3301         }
3302
3303         /* disable buffer size rounding to 128-byte multiples if supported */
3304         if (align_buffer_size >= 0)
3305                 chip->align_buffer_size = !!align_buffer_size;
3306         else {
3307                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3308                         chip->align_buffer_size = 0;
3309                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3310                         chip->align_buffer_size = 1;
3311                 else
3312                         chip->align_buffer_size = 1;
3313   &nbs