ALSA: hda - Use generic array for loopback list management
[~shefty/rdma-dev.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
70 static char *model[SNDRV_CARDS];
71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_only[SNDRV_CARDS];
75 static int jackpoll_ms[SNDRV_CARDS];
76 static bool single_cmd;
77 static int enable_msi = -1;
78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
79 static char *patch[SNDRV_CARDS];
80 #endif
81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
84 #endif
85
86 module_param_array(index, int, NULL, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
88 module_param_array(id, charp, NULL, 0444);
89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
90 module_param_array(enable, bool, NULL, 0444);
91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92 module_param_array(model, charp, NULL, 0444);
93 MODULE_PARM_DESC(model, "Use the given board model.");
94 module_param_array(position_fix, int, NULL, 0444);
95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
97 module_param_array(bdl_pos_adj, int, NULL, 0644);
98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
99 module_param_array(probe_mask, int, NULL, 0444);
100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
101 module_param_array(probe_only, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
103 module_param_array(jackpoll_ms, int, NULL, 0444);
104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
105 module_param(single_cmd, bool, 0444);
106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107                  "(for debugging only).");
108 module_param(enable_msi, bint, 0444);
109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
111 module_param_array(patch, charp, NULL, 0444);
112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113 #endif
114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
115 module_param_array(beep_mode, bool, NULL, 0444);
116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
117                             "(0=off, 1=on) (default=1).");
118 #endif
119
120 #ifdef CONFIG_PM
121 static int param_set_xint(const char *val, const struct kernel_param *kp);
122 static struct kernel_param_ops param_ops_xint = {
123         .set = param_set_xint,
124         .get = param_get_int,
125 };
126 #define param_check_xint param_check_int
127
128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
129 module_param(power_save, xint, 0644);
130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131                  "(in second, 0 = disable).");
132
133 /* reset the HD-audio controller in power save mode.
134  * this may give more power-saving, but will take longer time to
135  * wake up.
136  */
137 static int power_save_controller = -1;
138 module_param(power_save_controller, bint, 0644);
139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
140 #endif /* CONFIG_PM */
141
142 static int align_buffer_size = -1;
143 module_param(align_buffer_size, bint, 0644);
144 MODULE_PARM_DESC(align_buffer_size,
145                 "Force buffer and period sizes to be multiple of 128 bytes.");
146
147 #ifdef CONFIG_X86
148 static bool hda_snoop = true;
149 module_param_named(snoop, hda_snoop, bool, 0444);
150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151 #define azx_snoop(chip)         (chip)->snoop
152 #else
153 #define hda_snoop               true
154 #define azx_snoop(chip)         true
155 #endif
156
157
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160                          "{Intel, ICH6M},"
161                          "{Intel, ICH7},"
162                          "{Intel, ESB2},"
163                          "{Intel, ICH8},"
164                          "{Intel, ICH9},"
165                          "{Intel, ICH10},"
166                          "{Intel, PCH},"
167                          "{Intel, CPT},"
168                          "{Intel, PPT},"
169                          "{Intel, LPT},"
170                          "{Intel, LPT_LP},"
171                          "{Intel, HPT},"
172                          "{Intel, PBG},"
173                          "{Intel, SCH},"
174                          "{ATI, SB450},"
175                          "{ATI, SB600},"
176                          "{ATI, RS600},"
177                          "{ATI, RS690},"
178                          "{ATI, RS780},"
179                          "{ATI, R600},"
180                          "{ATI, RV630},"
181                          "{ATI, RV610},"
182                          "{ATI, RV670},"
183                          "{ATI, RV635},"
184                          "{ATI, RV620},"
185                          "{ATI, RV770},"
186                          "{VIA, VT8251},"
187                          "{VIA, VT8237A},"
188                          "{SiS, SIS966},"
189                          "{ULI, M5461}}");
190 MODULE_DESCRIPTION("Intel HDA driver");
191
192 #ifdef CONFIG_SND_VERBOSE_PRINTK
193 #define SFX     /* nop */
194 #else
195 #define SFX     "hda-intel "
196 #endif
197
198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
200 #define SUPPORT_VGA_SWITCHEROO
201 #endif
202 #endif
203
204
205 /*
206  * registers
207  */
208 #define ICH6_REG_GCAP                   0x00
209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
214 #define ICH6_REG_VMIN                   0x02
215 #define ICH6_REG_VMAJ                   0x03
216 #define ICH6_REG_OUTPAY                 0x04
217 #define ICH6_REG_INPAY                  0x06
218 #define ICH6_REG_GCTL                   0x08
219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
222 #define ICH6_REG_WAKEEN                 0x0c
223 #define ICH6_REG_STATESTS               0x0e
224 #define ICH6_REG_GSTS                   0x10
225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
226 #define ICH6_REG_INTCTL                 0x20
227 #define ICH6_REG_INTSTS                 0x24
228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
230 #define ICH6_REG_SSYNC                  0x38
231 #define ICH6_REG_CORBLBASE              0x40
232 #define ICH6_REG_CORBUBASE              0x44
233 #define ICH6_REG_CORBWP                 0x48
234 #define ICH6_REG_CORBRP                 0x4a
235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
236 #define ICH6_REG_CORBCTL                0x4c
237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
239 #define ICH6_REG_CORBSTS                0x4d
240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
241 #define ICH6_REG_CORBSIZE               0x4e
242
243 #define ICH6_REG_RIRBLBASE              0x50
244 #define ICH6_REG_RIRBUBASE              0x54
245 #define ICH6_REG_RIRBWP                 0x58
246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
247 #define ICH6_REG_RINTCNT                0x5a
248 #define ICH6_REG_RIRBCTL                0x5c
249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
252 #define ICH6_REG_RIRBSTS                0x5d
253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
255 #define ICH6_REG_RIRBSIZE               0x5e
256
257 #define ICH6_REG_IC                     0x60
258 #define ICH6_REG_IR                     0x64
259 #define ICH6_REG_IRS                    0x68
260 #define   ICH6_IRS_VALID        (1<<1)
261 #define   ICH6_IRS_BUSY         (1<<0)
262
263 #define ICH6_REG_DPLBASE                0x70
264 #define ICH6_REG_DPUBASE                0x74
265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
266
267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270 /* stream register offsets from stream base */
271 #define ICH6_REG_SD_CTL                 0x00
272 #define ICH6_REG_SD_STS                 0x03
273 #define ICH6_REG_SD_LPIB                0x04
274 #define ICH6_REG_SD_CBL                 0x08
275 #define ICH6_REG_SD_LVI                 0x0c
276 #define ICH6_REG_SD_FIFOW               0x0e
277 #define ICH6_REG_SD_FIFOSIZE            0x10
278 #define ICH6_REG_SD_FORMAT              0x12
279 #define ICH6_REG_SD_BDLPL               0x18
280 #define ICH6_REG_SD_BDLPU               0x1c
281
282 /* PCI space */
283 #define ICH6_PCIREG_TCSEL       0x44
284
285 /*
286  * other constants
287  */
288
289 /* max number of SDs */
290 /* ICH, ATI and VIA have 4 playback and 4 capture */
291 #define ICH6_NUM_CAPTURE        4
292 #define ICH6_NUM_PLAYBACK       4
293
294 /* ULI has 6 playback and 5 capture */
295 #define ULI_NUM_CAPTURE         5
296 #define ULI_NUM_PLAYBACK        6
297
298 /* ATI HDMI has 1 playback and 0 capture */
299 #define ATIHDMI_NUM_CAPTURE     0
300 #define ATIHDMI_NUM_PLAYBACK    1
301
302 /* TERA has 4 playback and 3 capture */
303 #define TERA_NUM_CAPTURE        3
304 #define TERA_NUM_PLAYBACK       4
305
306 /* this number is statically defined for simplicity */
307 #define MAX_AZX_DEV             16
308
309 /* max number of fragments - we may use more if allocating more pages for BDL */
310 #define BDL_SIZE                4096
311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
312 #define AZX_MAX_FRAG            32
313 /* max buffer size - no h/w limit, you can increase as you like */
314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
315
316 /* RIRB int mask: overrun[2], response[0] */
317 #define RIRB_INT_RESPONSE       0x01
318 #define RIRB_INT_OVERRUN        0x04
319 #define RIRB_INT_MASK           0x05
320
321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
322 #define AZX_MAX_CODECS          8
323 #define AZX_DEFAULT_CODECS      4
324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
325
326 /* SD_CTL bits */
327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
333 #define SD_CTL_STREAM_TAG_SHIFT 20
334
335 /* SD_CTL and SD_STS */
336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340                                  SD_INT_COMPLETE)
341
342 /* SD_STS */
343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
344
345 /* INTCTL and INTSTS */
346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
349
350 /* below are so far hardcoded - should read registers in future */
351 #define ICH6_MAX_CORB_ENTRIES   256
352 #define ICH6_MAX_RIRB_ENTRIES   256
353
354 /* position fix mode */
355 enum {
356         POS_FIX_AUTO,
357         POS_FIX_LPIB,
358         POS_FIX_POSBUF,
359         POS_FIX_VIACOMBO,
360         POS_FIX_COMBO,
361 };
362
363 /* Defines for ATI HD Audio support in SB450 south bridge */
364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
366
367 /* Defines for Nvidia HDA support */
368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
370 #define NVIDIA_HDA_ISTRM_COH          0x4d
371 #define NVIDIA_HDA_OSTRM_COH          0x4c
372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
373
374 /* Defines for Intel SCH HDA snoop control */
375 #define INTEL_SCH_HDA_DEVC      0x78
376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
377
378 /* Define IN stream 0 FIFO size offset in VIA controller */
379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380 /* Define VIA HD Audio Device ID*/
381 #define VIA_HDAC_DEVICE_ID              0x3288
382
383 /* HD Audio class code */
384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
385
386 /*
387  */
388
389 struct azx_dev {
390         struct snd_dma_buffer bdl; /* BDL buffer */
391         u32 *posbuf;            /* position buffer pointer */
392
393         unsigned int bufsize;   /* size of the play buffer in bytes */
394         unsigned int period_bytes; /* size of the period in bytes */
395         unsigned int frags;     /* number for period in the play buffer */
396         unsigned int fifo_size; /* FIFO size */
397         unsigned long start_wallclk;    /* start + minimum wallclk */
398         unsigned long period_wallclk;   /* wallclk for period */
399
400         void __iomem *sd_addr;  /* stream descriptor pointer */
401
402         u32 sd_int_sta_mask;    /* stream int status mask */
403
404         /* pcm support */
405         struct snd_pcm_substream *substream;    /* assigned substream,
406                                                  * set in PCM open
407                                                  */
408         unsigned int format_val;        /* format value to be set in the
409                                          * controller and the codec
410                                          */
411         unsigned char stream_tag;       /* assigned stream */
412         unsigned char index;            /* stream index */
413         int assigned_key;               /* last device# key assigned to */
414
415         unsigned int opened :1;
416         unsigned int running :1;
417         unsigned int irq_pending :1;
418         /*
419          * For VIA:
420          *  A flag to ensure DMA position is 0
421          *  when link position is not greater than FIFO size
422          */
423         unsigned int insufficient :1;
424         unsigned int wc_marked:1;
425         unsigned int no_period_wakeup:1;
426
427         struct timecounter  azx_tc;
428         struct cyclecounter azx_cc;
429 };
430
431 /* CORB/RIRB */
432 struct azx_rb {
433         u32 *buf;               /* CORB/RIRB buffer
434                                  * Each CORB entry is 4byte, RIRB is 8byte
435                                  */
436         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
437         /* for RIRB */
438         unsigned short rp, wp;  /* read/write pointers */
439         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
440         u32 res[AZX_MAX_CODECS];        /* last read value */
441 };
442
443 struct azx_pcm {
444         struct azx *chip;
445         struct snd_pcm *pcm;
446         struct hda_codec *codec;
447         struct hda_pcm_stream *hinfo[2];
448         struct list_head list;
449 };
450
451 struct azx {
452         struct snd_card *card;
453         struct pci_dev *pci;
454         int dev_index;
455
456         /* chip type specific */
457         int driver_type;
458         unsigned int driver_caps;
459         int playback_streams;
460         int playback_index_offset;
461         int capture_streams;
462         int capture_index_offset;
463         int num_streams;
464
465         /* pci resources */
466         unsigned long addr;
467         void __iomem *remap_addr;
468         int irq;
469
470         /* locks */
471         spinlock_t reg_lock;
472         struct mutex open_mutex;
473         struct completion probe_wait;
474
475         /* streams (x num_streams) */
476         struct azx_dev *azx_dev;
477
478         /* PCM */
479         struct list_head pcm_list; /* azx_pcm list */
480
481         /* HD codec */
482         unsigned short codec_mask;
483         int  codec_probe_mask; /* copied from probe_mask option */
484         struct hda_bus *bus;
485         unsigned int beep_mode;
486
487         /* CORB/RIRB */
488         struct azx_rb corb;
489         struct azx_rb rirb;
490
491         /* CORB/RIRB and position buffers */
492         struct snd_dma_buffer rb;
493         struct snd_dma_buffer posbuf;
494
495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
496         const struct firmware *fw;
497 #endif
498
499         /* flags */
500         int position_fix[2]; /* for both playback/capture streams */
501         int poll_count;
502         unsigned int running :1;
503         unsigned int initialized :1;
504         unsigned int single_cmd :1;
505         unsigned int polling_mode :1;
506         unsigned int msi :1;
507         unsigned int irq_pending_warned :1;
508         unsigned int probing :1; /* codec probing phase */
509         unsigned int snoop:1;
510         unsigned int align_buffer_size:1;
511         unsigned int region_requested:1;
512
513         /* VGA-switcheroo setup */
514         unsigned int use_vga_switcheroo:1;
515         unsigned int vga_switcheroo_registered:1;
516         unsigned int init_failed:1; /* delayed init failed */
517         unsigned int disabled:1; /* disabled by VGA-switcher */
518
519         /* for debugging */
520         unsigned int last_cmd[AZX_MAX_CODECS];
521
522         /* for pending irqs */
523         struct work_struct irq_pending_work;
524
525         /* reboot notifier (for mysterious hangup problem at power-down) */
526         struct notifier_block reboot_notifier;
527
528         /* card list (for power_save trigger) */
529         struct list_head list;
530 };
531
532 #define CREATE_TRACE_POINTS
533 #include "hda_intel_trace.h"
534
535 /* driver types */
536 enum {
537         AZX_DRIVER_ICH,
538         AZX_DRIVER_PCH,
539         AZX_DRIVER_SCH,
540         AZX_DRIVER_ATI,
541         AZX_DRIVER_ATIHDMI,
542         AZX_DRIVER_ATIHDMI_NS,
543         AZX_DRIVER_VIA,
544         AZX_DRIVER_SIS,
545         AZX_DRIVER_ULI,
546         AZX_DRIVER_NVIDIA,
547         AZX_DRIVER_TERA,
548         AZX_DRIVER_CTX,
549         AZX_DRIVER_CTHDA,
550         AZX_DRIVER_GENERIC,
551         AZX_NUM_DRIVERS, /* keep this as last entry */
552 };
553
554 /* driver quirks (capabilities) */
555 /* bits 0-7 are used for indicating driver type */
556 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
557 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
558 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
559 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
560 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
561 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
562 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
563 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
564 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
565 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
566 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
567 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
568 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
569 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
570 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
571 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
572 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
573 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
574
575 /* quirks for Intel PCH */
576 #define AZX_DCAPS_INTEL_PCH_NOPM \
577         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
578          AZX_DCAPS_COUNT_LPIB_DELAY)
579
580 #define AZX_DCAPS_INTEL_PCH \
581         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
582
583 /* quirks for ATI SB / AMD Hudson */
584 #define AZX_DCAPS_PRESET_ATI_SB \
585         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
586          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
587
588 /* quirks for ATI/AMD HDMI */
589 #define AZX_DCAPS_PRESET_ATI_HDMI \
590         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
591
592 /* quirks for Nvidia */
593 #define AZX_DCAPS_PRESET_NVIDIA \
594         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
595          AZX_DCAPS_ALIGN_BUFSIZE)
596
597 #define AZX_DCAPS_PRESET_CTHDA \
598         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
599
600 /*
601  * VGA-switcher support
602  */
603 #ifdef SUPPORT_VGA_SWITCHEROO
604 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
605 #else
606 #define use_vga_switcheroo(chip)        0
607 #endif
608
609 static char *driver_short_names[] = {
610         [AZX_DRIVER_ICH] = "HDA Intel",
611         [AZX_DRIVER_PCH] = "HDA Intel PCH",
612         [AZX_DRIVER_SCH] = "HDA Intel MID",
613         [AZX_DRIVER_ATI] = "HDA ATI SB",
614         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
615         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
616         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
617         [AZX_DRIVER_SIS] = "HDA SIS966",
618         [AZX_DRIVER_ULI] = "HDA ULI M5461",
619         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
620         [AZX_DRIVER_TERA] = "HDA Teradici", 
621         [AZX_DRIVER_CTX] = "HDA Creative", 
622         [AZX_DRIVER_CTHDA] = "HDA Creative",
623         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
624 };
625
626 /*
627  * macros for easy use
628  */
629 #define azx_writel(chip,reg,value) \
630         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
631 #define azx_readl(chip,reg) \
632         readl((chip)->remap_addr + ICH6_REG_##reg)
633 #define azx_writew(chip,reg,value) \
634         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
635 #define azx_readw(chip,reg) \
636         readw((chip)->remap_addr + ICH6_REG_##reg)
637 #define azx_writeb(chip,reg,value) \
638         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
639 #define azx_readb(chip,reg) \
640         readb((chip)->remap_addr + ICH6_REG_##reg)
641
642 #define azx_sd_writel(dev,reg,value) \
643         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
644 #define azx_sd_readl(dev,reg) \
645         readl((dev)->sd_addr + ICH6_REG_##reg)
646 #define azx_sd_writew(dev,reg,value) \
647         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
648 #define azx_sd_readw(dev,reg) \
649         readw((dev)->sd_addr + ICH6_REG_##reg)
650 #define azx_sd_writeb(dev,reg,value) \
651         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
652 #define azx_sd_readb(dev,reg) \
653         readb((dev)->sd_addr + ICH6_REG_##reg)
654
655 /* for pcm support */
656 #define get_azx_dev(substream) (substream->runtime->private_data)
657
658 #ifdef CONFIG_X86
659 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
660 {
661         int pages;
662
663         if (azx_snoop(chip))
664                 return;
665         if (!dmab || !dmab->area || !dmab->bytes)
666                 return;
667
668 #ifdef CONFIG_SND_DMA_SGBUF
669         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
670                 struct snd_sg_buf *sgbuf = dmab->private_data;
671                 if (on)
672                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
673                 else
674                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
675                 return;
676         }
677 #endif
678
679         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
680         if (on)
681                 set_memory_wc((unsigned long)dmab->area, pages);
682         else
683                 set_memory_wb((unsigned long)dmab->area, pages);
684 }
685
686 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
687                                  bool on)
688 {
689         __mark_pages_wc(chip, buf, on);
690 }
691 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
692                                    struct snd_pcm_substream *substream, bool on)
693 {
694         if (azx_dev->wc_marked != on) {
695                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
696                 azx_dev->wc_marked = on;
697         }
698 }
699 #else
700 /* NOP for other archs */
701 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
702                                  bool on)
703 {
704 }
705 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
706                                    struct snd_pcm_substream *substream, bool on)
707 {
708 }
709 #endif
710
711 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
712 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
713 /*
714  * Interface for HD codec
715  */
716
717 /*
718  * CORB / RIRB interface
719  */
720 static int azx_alloc_cmd_io(struct azx *chip)
721 {
722         int err;
723
724         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
725         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
726                                   snd_dma_pci_data(chip->pci),
727                                   PAGE_SIZE, &chip->rb);
728         if (err < 0) {
729                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
730                 return err;
731         }
732         mark_pages_wc(chip, &chip->rb, true);
733         return 0;
734 }
735
736 static void azx_init_cmd_io(struct azx *chip)
737 {
738         spin_lock_irq(&chip->reg_lock);
739         /* CORB set up */
740         chip->corb.addr = chip->rb.addr;
741         chip->corb.buf = (u32 *)chip->rb.area;
742         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
743         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
744
745         /* set the corb size to 256 entries (ULI requires explicitly) */
746         azx_writeb(chip, CORBSIZE, 0x02);
747         /* set the corb write pointer to 0 */
748         azx_writew(chip, CORBWP, 0);
749         /* reset the corb hw read pointer */
750         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
751         /* enable corb dma */
752         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
753
754         /* RIRB set up */
755         chip->rirb.addr = chip->rb.addr + 2048;
756         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
757         chip->rirb.wp = chip->rirb.rp = 0;
758         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
759         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
760         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
761
762         /* set the rirb size to 256 entries (ULI requires explicitly) */
763         azx_writeb(chip, RIRBSIZE, 0x02);
764         /* reset the rirb hw write pointer */
765         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
766         /* set N=1, get RIRB response interrupt for new entry */
767         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
768                 azx_writew(chip, RINTCNT, 0xc0);
769         else
770                 azx_writew(chip, RINTCNT, 1);
771         /* enable rirb dma and response irq */
772         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
773         spin_unlock_irq(&chip->reg_lock);
774 }
775
776 static void azx_free_cmd_io(struct azx *chip)
777 {
778         spin_lock_irq(&chip->reg_lock);
779         /* disable ringbuffer DMAs */
780         azx_writeb(chip, RIRBCTL, 0);
781         azx_writeb(chip, CORBCTL, 0);
782         spin_unlock_irq(&chip->reg_lock);
783 }
784
785 static unsigned int azx_command_addr(u32 cmd)
786 {
787         unsigned int addr = cmd >> 28;
788
789         if (addr >= AZX_MAX_CODECS) {
790                 snd_BUG();
791                 addr = 0;
792         }
793
794         return addr;
795 }
796
797 static unsigned int azx_response_addr(u32 res)
798 {
799         unsigned int addr = res & 0xf;
800
801         if (addr >= AZX_MAX_CODECS) {
802                 snd_BUG();
803                 addr = 0;
804         }
805
806         return addr;
807 }
808
809 /* send a command */
810 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
811 {
812         struct azx *chip = bus->private_data;
813         unsigned int addr = azx_command_addr(val);
814         unsigned int wp, rp;
815
816         spin_lock_irq(&chip->reg_lock);
817
818         /* add command to corb */
819         wp = azx_readw(chip, CORBWP);
820         if (wp == 0xffff) {
821                 /* something wrong, controller likely turned to D3 */
822                 spin_unlock_irq(&chip->reg_lock);
823                 return -EIO;
824         }
825         wp++;
826         wp %= ICH6_MAX_CORB_ENTRIES;
827
828         rp = azx_readw(chip, CORBRP);
829         if (wp == rp) {
830                 /* oops, it's full */
831                 spin_unlock_irq(&chip->reg_lock);
832                 return -EAGAIN;
833         }
834
835         chip->rirb.cmds[addr]++;
836         chip->corb.buf[wp] = cpu_to_le32(val);
837         azx_writel(chip, CORBWP, wp);
838
839         spin_unlock_irq(&chip->reg_lock);
840
841         return 0;
842 }
843
844 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
845
846 /* retrieve RIRB entry - called from interrupt handler */
847 static void azx_update_rirb(struct azx *chip)
848 {
849         unsigned int rp, wp;
850         unsigned int addr;
851         u32 res, res_ex;
852
853         wp = azx_readw(chip, RIRBWP);
854         if (wp == 0xffff) {
855                 /* something wrong, controller likely turned to D3 */
856                 return;
857         }
858
859         if (wp == chip->rirb.wp)
860                 return;
861         chip->rirb.wp = wp;
862
863         while (chip->rirb.rp != wp) {
864                 chip->rirb.rp++;
865                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
866
867                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
868                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
869                 res = le32_to_cpu(chip->rirb.buf[rp]);
870                 addr = azx_response_addr(res_ex);
871                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
872                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
873                 else if (chip->rirb.cmds[addr]) {
874                         chip->rirb.res[addr] = res;
875                         smp_wmb();
876                         chip->rirb.cmds[addr]--;
877                 } else
878                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
879                                    "last cmd=%#08x\n",
880                                    pci_name(chip->pci),
881                                    res, res_ex,
882                                    chip->last_cmd[addr]);
883         }
884 }
885
886 /* receive a response */
887 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
888                                           unsigned int addr)
889 {
890         struct azx *chip = bus->private_data;
891         unsigned long timeout;
892         unsigned long loopcounter;
893         int do_poll = 0;
894
895  again:
896         timeout = jiffies + msecs_to_jiffies(1000);
897
898         for (loopcounter = 0;; loopcounter++) {
899                 if (chip->polling_mode || do_poll) {
900                         spin_lock_irq(&chip->reg_lock);
901                         azx_update_rirb(chip);
902                         spin_unlock_irq(&chip->reg_lock);
903                 }
904                 if (!chip->rirb.cmds[addr]) {
905                         smp_rmb();
906                         bus->rirb_error = 0;
907
908                         if (!do_poll)
909                                 chip->poll_count = 0;
910                         return chip->rirb.res[addr]; /* the last value */
911                 }
912                 if (time_after(jiffies, timeout))
913                         break;
914                 if (bus->needs_damn_long_delay || loopcounter > 3000)
915                         msleep(2); /* temporary workaround */
916                 else {
917                         udelay(10);
918                         cond_resched();
919                 }
920         }
921
922         if (!chip->polling_mode && chip->poll_count < 2) {
923                 snd_printdd(SFX "%s: azx_get_response timeout, "
924                            "polling the codec once: last cmd=0x%08x\n",
925                            pci_name(chip->pci), chip->last_cmd[addr]);
926                 do_poll = 1;
927                 chip->poll_count++;
928                 goto again;
929         }
930
931
932         if (!chip->polling_mode) {
933                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
934                            "switching to polling mode: last cmd=0x%08x\n",
935                            pci_name(chip->pci), chip->last_cmd[addr]);
936                 chip->polling_mode = 1;
937                 goto again;
938         }
939
940         if (chip->msi) {
941                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
942                            "disabling MSI: last cmd=0x%08x\n",
943                            pci_name(chip->pci), chip->last_cmd[addr]);
944                 free_irq(chip->irq, chip);
945                 chip->irq = -1;
946                 pci_disable_msi(chip->pci);
947                 chip->msi = 0;
948                 if (azx_acquire_irq(chip, 1) < 0) {
949                         bus->rirb_error = 1;
950                         return -1;
951                 }
952                 goto again;
953         }
954
955         if (chip->probing) {
956                 /* If this critical timeout happens during the codec probing
957                  * phase, this is likely an access to a non-existing codec
958                  * slot.  Better to return an error and reset the system.
959                  */
960                 return -1;
961         }
962
963         /* a fatal communication error; need either to reset or to fallback
964          * to the single_cmd mode
965          */
966         bus->rirb_error = 1;
967         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
968                 bus->response_reset = 1;
969                 return -1; /* give a chance to retry */
970         }
971
972         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
973                    "switching to single_cmd mode: last cmd=0x%08x\n",
974                    chip->last_cmd[addr]);
975         chip->single_cmd = 1;
976         bus->response_reset = 0;
977         /* release CORB/RIRB */
978         azx_free_cmd_io(chip);
979         /* disable unsolicited responses */
980         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
981         return -1;
982 }
983
984 /*
985  * Use the single immediate command instead of CORB/RIRB for simplicity
986  *
987  * Note: according to Intel, this is not preferred use.  The command was
988  *       intended for the BIOS only, and may get confused with unsolicited
989  *       responses.  So, we shouldn't use it for normal operation from the
990  *       driver.
991  *       I left the codes, however, for debugging/testing purposes.
992  */
993
994 /* receive a response */
995 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
996 {
997         int timeout = 50;
998
999         while (timeout--) {
1000                 /* check IRV busy bit */
1001                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1002                         /* reuse rirb.res as the response return value */
1003                         chip->rirb.res[addr] = azx_readl(chip, IR);
1004                         return 0;
1005                 }
1006                 udelay(1);
1007         }
1008         if (printk_ratelimit())
1009                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1010                            pci_name(chip->pci), azx_readw(chip, IRS));
1011         chip->rirb.res[addr] = -1;
1012         return -EIO;
1013 }
1014
1015 /* send a command */
1016 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1017 {
1018         struct azx *chip = bus->private_data;
1019         unsigned int addr = azx_command_addr(val);
1020         int timeout = 50;
1021
1022         bus->rirb_error = 0;
1023         while (timeout--) {
1024                 /* check ICB busy bit */
1025                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1026                         /* Clear IRV valid bit */
1027                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1028                                    ICH6_IRS_VALID);
1029                         azx_writel(chip, IC, val);
1030                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1031                                    ICH6_IRS_BUSY);
1032                         return azx_single_wait_for_response(chip, addr);
1033                 }
1034                 udelay(1);
1035         }
1036         if (printk_ratelimit())
1037                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1038                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1039         return -EIO;
1040 }
1041
1042 /* receive a response */
1043 static unsigned int azx_single_get_response(struct hda_bus *bus,
1044                                             unsigned int addr)
1045 {
1046         struct azx *chip = bus->private_data;
1047         return chip->rirb.res[addr];
1048 }
1049
1050 /*
1051  * The below are the main callbacks from hda_codec.
1052  *
1053  * They are just the skeleton to call sub-callbacks according to the
1054  * current setting of chip->single_cmd.
1055  */
1056
1057 /* send a command */
1058 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1059 {
1060         struct azx *chip = bus->private_data;
1061
1062         if (chip->disabled)
1063                 return 0;
1064         chip->last_cmd[azx_command_addr(val)] = val;
1065         if (chip->single_cmd)
1066                 return azx_single_send_cmd(bus, val);
1067         else
1068                 return azx_corb_send_cmd(bus, val);
1069 }
1070
1071 /* get a response */
1072 static unsigned int azx_get_response(struct hda_bus *bus,
1073                                      unsigned int addr)
1074 {
1075         struct azx *chip = bus->private_data;
1076         if (chip->disabled)
1077                 return 0;
1078         if (chip->single_cmd)
1079                 return azx_single_get_response(bus, addr);
1080         else
1081                 return azx_rirb_get_response(bus, addr);
1082 }
1083
1084 #ifdef CONFIG_PM
1085 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1086 #endif
1087
1088 /* reset codec link */
1089 static int azx_reset(struct azx *chip, int full_reset)
1090 {
1091         unsigned long timeout;
1092
1093         if (!full_reset)
1094                 goto __skip;
1095
1096         /* clear STATESTS */
1097         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1098
1099         /* reset controller */
1100         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1101
1102         timeout = jiffies + msecs_to_jiffies(100);
1103         while (azx_readb(chip, GCTL) &&
1104                         time_before(jiffies, timeout))
1105                 usleep_range(500, 1000);
1106
1107         /* delay for >= 100us for codec PLL to settle per spec
1108          * Rev 0.9 section 5.5.1
1109          */
1110         usleep_range(500, 1000);
1111
1112         /* Bring controller out of reset */
1113         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1114
1115         timeout = jiffies + msecs_to_jiffies(100);
1116         while (!azx_readb(chip, GCTL) &&
1117                         time_before(jiffies, timeout))
1118                 usleep_range(500, 1000);
1119
1120         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1121         usleep_range(1000, 1200);
1122
1123       __skip:
1124         /* check to see if controller is ready */
1125         if (!azx_readb(chip, GCTL)) {
1126                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1127                 return -EBUSY;
1128         }
1129
1130         /* Accept unsolicited responses */
1131         if (!chip->single_cmd)
1132                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1133                            ICH6_GCTL_UNSOL);
1134
1135         /* detect codecs */
1136         if (!chip->codec_mask) {
1137                 chip->codec_mask = azx_readw(chip, STATESTS);
1138                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1139         }
1140
1141         return 0;
1142 }
1143
1144
1145 /*
1146  * Lowlevel interface
1147  */  
1148
1149 /* enable interrupts */
1150 static void azx_int_enable(struct azx *chip)
1151 {
1152         /* enable controller CIE and GIE */
1153         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1154                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1155 }
1156
1157 /* disable interrupts */
1158 static void azx_int_disable(struct azx *chip)
1159 {
1160         int i;
1161
1162         /* disable interrupts in stream descriptor */
1163         for (i = 0; i < chip->num_streams; i++) {
1164                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1165                 azx_sd_writeb(azx_dev, SD_CTL,
1166                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1167         }
1168
1169         /* disable SIE for all streams */
1170         azx_writeb(chip, INTCTL, 0);
1171
1172         /* disable controller CIE and GIE */
1173         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1174                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1175 }
1176
1177 /* clear interrupts */
1178 static void azx_int_clear(struct azx *chip)
1179 {
1180         int i;
1181
1182         /* clear stream status */
1183         for (i = 0; i < chip->num_streams; i++) {
1184                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1185                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1186         }
1187
1188         /* clear STATESTS */
1189         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1190
1191         /* clear rirb status */
1192         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1193
1194         /* clear int status */
1195         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1196 }
1197
1198 /* start a stream */
1199 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1200 {
1201         /*
1202          * Before stream start, initialize parameter
1203          */
1204         azx_dev->insufficient = 1;
1205
1206         /* enable SIE */
1207         azx_writel(chip, INTCTL,
1208                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1209         /* set DMA start and interrupt mask */
1210         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1211                       SD_CTL_DMA_START | SD_INT_MASK);
1212 }
1213
1214 /* stop DMA */
1215 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1216 {
1217         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1218                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1219         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1220 }
1221
1222 /* stop a stream */
1223 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1224 {
1225         azx_stream_clear(chip, azx_dev);
1226         /* disable SIE */
1227         azx_writel(chip, INTCTL,
1228                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1229 }
1230
1231
1232 /*
1233  * reset and start the controller registers
1234  */
1235 static void azx_init_chip(struct azx *chip, int full_reset)
1236 {
1237         if (chip->initialized)
1238                 return;
1239
1240         /* reset controller */
1241         azx_reset(chip, full_reset);
1242
1243         /* initialize interrupts */
1244         azx_int_clear(chip);
1245         azx_int_enable(chip);
1246
1247         /* initialize the codec command I/O */
1248         if (!chip->single_cmd)
1249                 azx_init_cmd_io(chip);
1250
1251         /* program the position buffer */
1252         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1253         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1254
1255         chip->initialized = 1;
1256 }
1257
1258 /*
1259  * initialize the PCI registers
1260  */
1261 /* update bits in a PCI register byte */
1262 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1263                             unsigned char mask, unsigned char val)
1264 {
1265         unsigned char data;
1266
1267         pci_read_config_byte(pci, reg, &data);
1268         data &= ~mask;
1269         data |= (val & mask);
1270         pci_write_config_byte(pci, reg, data);
1271 }
1272
1273 static void azx_init_pci(struct azx *chip)
1274 {
1275         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1276          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1277          * Ensuring these bits are 0 clears playback static on some HD Audio
1278          * codecs.
1279          * The PCI register TCSEL is defined in the Intel manuals.
1280          */
1281         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1282                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1283                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1284         }
1285
1286         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1287          * we need to enable snoop.
1288          */
1289         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1290                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1291                 update_pci_byte(chip->pci,
1292                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1293                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1294         }
1295
1296         /* For NVIDIA HDA, enable snoop */
1297         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1298                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1299                 update_pci_byte(chip->pci,
1300                                 NVIDIA_HDA_TRANSREG_ADDR,
1301                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1302                 update_pci_byte(chip->pci,
1303                                 NVIDIA_HDA_ISTRM_COH,
1304                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1305                 update_pci_byte(chip->pci,
1306                                 NVIDIA_HDA_OSTRM_COH,
1307                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1308         }
1309
1310         /* Enable SCH/PCH snoop if needed */
1311         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1312                 unsigned short snoop;
1313                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1314                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1315                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1316                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1317                         if (!azx_snoop(chip))
1318                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1319                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1320                         pci_read_config_word(chip->pci,
1321                                 INTEL_SCH_HDA_DEVC, &snoop);
1322                 }
1323                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1324                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1325                                 ? "Disabled" : "Enabled");
1326         }
1327 }
1328
1329
1330 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1331
1332 /*
1333  * interrupt handler
1334  */
1335 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1336 {
1337         struct azx *chip = dev_id;
1338         struct azx_dev *azx_dev;
1339         u32 status;
1340         u8 sd_status;
1341         int i, ok;
1342
1343 #ifdef CONFIG_PM_RUNTIME
1344         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1345                 return IRQ_NONE;
1346 #endif
1347
1348         spin_lock(&chip->reg_lock);
1349
1350         if (chip->disabled) {
1351                 spin_unlock(&chip->reg_lock);
1352                 return IRQ_NONE;
1353         }
1354
1355         status = azx_readl(chip, INTSTS);
1356         if (status == 0) {
1357                 spin_unlock(&chip->reg_lock);
1358                 return IRQ_NONE;
1359         }
1360         
1361         for (i = 0; i < chip->num_streams; i++) {
1362                 azx_dev = &chip->azx_dev[i];
1363                 if (status & azx_dev->sd_int_sta_mask) {
1364                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1365                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1366                         if (!azx_dev->substream || !azx_dev->running ||
1367                             !(sd_status & SD_INT_COMPLETE))
1368                                 continue;
1369                         /* check whether this IRQ is really acceptable */
1370                         ok = azx_position_ok(chip, azx_dev);
1371                         if (ok == 1) {
1372                                 azx_dev->irq_pending = 0;
1373                                 spin_unlock(&chip->reg_lock);
1374                                 snd_pcm_period_elapsed(azx_dev->substream);
1375                                 spin_lock(&chip->reg_lock);
1376                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1377                                 /* bogus IRQ, process it later */
1378                                 azx_dev->irq_pending = 1;
1379                                 queue_work(chip->bus->workq,
1380                                            &chip->irq_pending_work);
1381                         }
1382                 }
1383         }
1384
1385         /* clear rirb int */
1386         status = azx_readb(chip, RIRBSTS);
1387         if (status & RIRB_INT_MASK) {
1388                 if (status & RIRB_INT_RESPONSE) {
1389                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1390                                 udelay(80);
1391                         azx_update_rirb(chip);
1392                 }
1393                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1394         }
1395
1396 #if 0
1397         /* clear state status int */
1398         if (azx_readb(chip, STATESTS) & 0x04)
1399                 azx_writeb(chip, STATESTS, 0x04);
1400 #endif
1401         spin_unlock(&chip->reg_lock);
1402         
1403         return IRQ_HANDLED;
1404 }
1405
1406
1407 /*
1408  * set up a BDL entry
1409  */
1410 static int setup_bdle(struct azx *chip,
1411                       struct snd_pcm_substream *substream,
1412                       struct azx_dev *azx_dev, u32 **bdlp,
1413                       int ofs, int size, int with_ioc)
1414 {
1415         u32 *bdl = *bdlp;
1416
1417         while (size > 0) {
1418                 dma_addr_t addr;
1419                 int chunk;
1420
1421                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1422                         return -EINVAL;
1423
1424                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1425                 /* program the address field of the BDL entry */
1426                 bdl[0] = cpu_to_le32((u32)addr);
1427                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1428                 /* program the size field of the BDL entry */
1429                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1430                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1431                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1432                         u32 remain = 0x1000 - (ofs & 0xfff);
1433                         if (chunk > remain)
1434                                 chunk = remain;
1435                 }
1436                 bdl[2] = cpu_to_le32(chunk);
1437                 /* program the IOC to enable interrupt
1438                  * only when the whole fragment is processed
1439                  */
1440                 size -= chunk;
1441                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1442                 bdl += 4;
1443                 azx_dev->frags++;
1444                 ofs += chunk;
1445         }
1446         *bdlp = bdl;
1447         return ofs;
1448 }
1449
1450 /*
1451  * set up BDL entries
1452  */
1453 static int azx_setup_periods(struct azx *chip,
1454                              struct snd_pcm_substream *substream,
1455                              struct azx_dev *azx_dev)
1456 {
1457         u32 *bdl;
1458         int i, ofs, periods, period_bytes;
1459         int pos_adj;
1460
1461         /* reset BDL address */
1462         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1463         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1464
1465         period_bytes = azx_dev->period_bytes;
1466         periods = azx_dev->bufsize / period_bytes;
1467
1468         /* program the initial BDL entries */
1469         bdl = (u32 *)azx_dev->bdl.area;
1470         ofs = 0;
1471         azx_dev->frags = 0;
1472         pos_adj = bdl_pos_adj[chip->dev_index];
1473         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1474                 struct snd_pcm_runtime *runtime = substream->runtime;
1475                 int pos_align = pos_adj;
1476                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1477                 if (!pos_adj)
1478                         pos_adj = pos_align;
1479                 else
1480                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1481                                 pos_align;
1482                 pos_adj = frames_to_bytes(runtime, pos_adj);
1483                 if (pos_adj >= period_bytes) {
1484                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1485                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1486                         pos_adj = 0;
1487                 } else {
1488                         ofs = setup_bdle(chip, substream, azx_dev,
1489                                          &bdl, ofs, pos_adj, true);
1490                         if (ofs < 0)
1491                                 goto error;
1492                 }
1493         } else
1494                 pos_adj = 0;
1495         for (i = 0; i < periods; i++) {
1496                 if (i == periods - 1 && pos_adj)
1497                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1498                                          period_bytes - pos_adj, 0);
1499                 else
1500                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1501                                          period_bytes,
1502                                          !azx_dev->no_period_wakeup);
1503                 if (ofs < 0)
1504                         goto error;
1505         }
1506         return 0;
1507
1508  error:
1509         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1510                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1511         return -EINVAL;
1512 }
1513
1514 /* reset stream */
1515 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1516 {
1517         unsigned char val;
1518         int timeout;
1519
1520         azx_stream_clear(chip, azx_dev);
1521
1522         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1523                       SD_CTL_STREAM_RESET);
1524         udelay(3);
1525         timeout = 300;
1526         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1527                --timeout)
1528                 ;
1529         val &= ~SD_CTL_STREAM_RESET;
1530         azx_sd_writeb(azx_dev, SD_CTL, val);
1531         udelay(3);
1532
1533         timeout = 300;
1534         /* waiting for hardware to report that the stream is out of reset */
1535         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1536                --timeout)
1537                 ;
1538
1539         /* reset first position - may not be synced with hw at this time */
1540         *azx_dev->posbuf = 0;
1541 }
1542
1543 /*
1544  * set up the SD for streaming
1545  */
1546 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1547 {
1548         unsigned int val;
1549         /* make sure the run bit is zero for SD */
1550         azx_stream_clear(chip, azx_dev);
1551         /* program the stream_tag */
1552         val = azx_sd_readl(azx_dev, SD_CTL);
1553         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1554                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1555         if (!azx_snoop(chip))
1556                 val |= SD_CTL_TRAFFIC_PRIO;
1557         azx_sd_writel(azx_dev, SD_CTL, val);
1558
1559         /* program the length of samples in cyclic buffer */
1560         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1561
1562         /* program the stream format */
1563         /* this value needs to be the same as the one programmed */
1564         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1565
1566         /* program the stream LVI (last valid index) of the BDL */
1567         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1568
1569         /* program the BDL address */
1570         /* lower BDL address */
1571         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1572         /* upper BDL address */
1573         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1574
1575         /* enable the position buffer */
1576         if (chip->position_fix[0] != POS_FIX_LPIB ||
1577             chip->position_fix[1] != POS_FIX_LPIB) {
1578                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1579                         azx_writel(chip, DPLBASE,
1580                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1581         }
1582
1583         /* set the interrupt enable bits in the descriptor control register */
1584         azx_sd_writel(azx_dev, SD_CTL,
1585                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1586
1587         return 0;
1588 }
1589
1590 /*
1591  * Probe the given codec address
1592  */
1593 static int probe_codec(struct azx *chip, int addr)
1594 {
1595         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1596                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1597         unsigned int res;
1598
1599         mutex_lock(&chip->bus->cmd_mutex);
1600         chip->probing = 1;
1601         azx_send_cmd(chip->bus, cmd);
1602         res = azx_get_response(chip->bus, addr);
1603         chip->probing = 0;
1604         mutex_unlock(&chip->bus->cmd_mutex);
1605         if (res == -1)
1606                 return -EIO;
1607         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1608         return 0;
1609 }
1610
1611 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1612                                  struct hda_pcm *cpcm);
1613 static void azx_stop_chip(struct azx *chip);
1614
1615 static void azx_bus_reset(struct hda_bus *bus)
1616 {
1617         struct azx *chip = bus->private_data;
1618
1619         bus->in_reset = 1;
1620         azx_stop_chip(chip);
1621         azx_init_chip(chip, 1);
1622 #ifdef CONFIG_PM
1623         if (chip->initialized) {
1624                 struct azx_pcm *p;
1625                 list_for_each_entry(p, &chip->pcm_list, list)
1626                         snd_pcm_suspend_all(p->pcm);
1627                 snd_hda_suspend(chip->bus);
1628                 snd_hda_resume(chip->bus);
1629         }
1630 #endif
1631         bus->in_reset = 0;
1632 }
1633
1634 static int get_jackpoll_interval(struct azx *chip)
1635 {
1636         int i = jackpoll_ms[chip->dev_index];
1637         unsigned int j;
1638         if (i == 0)
1639                 return 0;
1640         if (i < 50 || i > 60000)
1641                 j = 0;
1642         else
1643                 j = msecs_to_jiffies(i);
1644         if (j == 0)
1645                 snd_printk(KERN_WARNING SFX
1646                            "jackpoll_ms value out of range: %d\n", i);
1647         return j;
1648 }
1649
1650 /*
1651  * Codec initialization
1652  */
1653
1654 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1655 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1656         [AZX_DRIVER_NVIDIA] = 8,
1657         [AZX_DRIVER_TERA] = 1,
1658 };
1659
1660 static int azx_codec_create(struct azx *chip, const char *model)
1661 {
1662         struct hda_bus_template bus_temp;
1663         int c, codecs, err;
1664         int max_slots;
1665
1666         memset(&bus_temp, 0, sizeof(bus_temp));
1667         bus_temp.private_data = chip;
1668         bus_temp.modelname = model;
1669         bus_temp.pci = chip->pci;
1670         bus_temp.ops.command = azx_send_cmd;
1671         bus_temp.ops.get_response = azx_get_response;
1672         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1673         bus_temp.ops.bus_reset = azx_bus_reset;
1674 #ifdef CONFIG_PM
1675         bus_temp.power_save = &power_save;
1676         bus_temp.ops.pm_notify = azx_power_notify;
1677 #endif
1678
1679         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1680         if (err < 0)
1681                 return err;
1682
1683         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1684                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1685                 chip->bus->needs_damn_long_delay = 1;
1686         }
1687
1688         codecs = 0;
1689         max_slots = azx_max_codecs[chip->driver_type];
1690         if (!max_slots)
1691                 max_slots = AZX_DEFAULT_CODECS;
1692
1693         /* First try to probe all given codec slots */
1694         for (c = 0; c < max_slots; c++) {
1695                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1696                         if (probe_codec(chip, c) < 0) {
1697                                 /* Some BIOSen give you wrong codec addresses
1698                                  * that don't exist
1699                                  */
1700                                 snd_printk(KERN_WARNING SFX
1701                                            "%s: Codec #%d probe error; "
1702                                            "disabling it...\n", pci_name(chip->pci), c);
1703                                 chip->codec_mask &= ~(1 << c);
1704                                 /* More badly, accessing to a non-existing
1705                                  * codec often screws up the controller chip,
1706                                  * and disturbs the further communications.
1707                                  * Thus if an error occurs during probing,
1708                                  * better to reset the controller chip to
1709                                  * get back to the sanity state.
1710                                  */
1711                                 azx_stop_chip(chip);
1712                                 azx_init_chip(chip, 1);
1713                         }
1714                 }
1715         }
1716
1717         /* AMD chipsets often cause the communication stalls upon certain
1718          * sequence like the pin-detection.  It seems that forcing the synced
1719          * access works around the stall.  Grrr...
1720          */
1721         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1722                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1723                         pci_name(chip->pci));
1724                 chip->bus->sync_write = 1;
1725                 chip->bus->allow_bus_reset = 1;
1726         }
1727
1728         /* Then create codec instances */
1729         for (c = 0; c < max_slots; c++) {
1730                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1731                         struct hda_codec *codec;
1732                         err = snd_hda_codec_new(chip->bus, c, &codec);
1733                         if (err < 0)
1734                                 continue;
1735                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1736                         codec->beep_mode = chip->beep_mode;
1737                         codecs++;
1738                 }
1739         }
1740         if (!codecs) {
1741                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1742                 return -ENXIO;
1743         }
1744         return 0;
1745 }
1746
1747 /* configure each codec instance */
1748 static int azx_codec_configure(struct azx *chip)
1749 {
1750         struct hda_codec *codec;
1751         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1752                 snd_hda_codec_configure(codec);
1753         }
1754         return 0;
1755 }
1756
1757
1758 /*
1759  * PCM support
1760  */
1761
1762 /* assign a stream for the PCM */
1763 static inline struct azx_dev *
1764 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1765 {
1766         int dev, i, nums;
1767         struct azx_dev *res = NULL;
1768         /* make a non-zero unique key for the substream */
1769         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1770                 (substream->stream + 1);
1771
1772         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1773                 dev = chip->playback_index_offset;
1774                 nums = chip->playback_streams;
1775         } else {
1776                 dev = chip->capture_index_offset;
1777                 nums = chip->capture_streams;
1778         }
1779         for (i = 0; i < nums; i++, dev++)
1780                 if (!chip->azx_dev[dev].opened) {
1781                         res = &chip->azx_dev[dev];
1782                         if (res->assigned_key == key)
1783                                 break;
1784                 }
1785         if (res) {
1786                 res->opened = 1;
1787                 res->assigned_key = key;
1788         }
1789         return res;
1790 }
1791
1792 /* release the assigned stream */
1793 static inline void azx_release_device(struct azx_dev *azx_dev)
1794 {
1795         azx_dev->opened = 0;
1796 }
1797
1798 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1799 {
1800         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1801         struct snd_pcm_substream *substream = azx_dev->substream;
1802         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1803         struct azx *chip = apcm->chip;
1804
1805         return azx_readl(chip, WALLCLK);
1806 }
1807
1808 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1809                                 bool force, cycle_t last)
1810 {
1811         struct azx_dev *azx_dev = get_azx_dev(substream);
1812         struct timecounter *tc = &azx_dev->azx_tc;
1813         struct cyclecounter *cc = &azx_dev->azx_cc;
1814         u64 nsec;
1815
1816         cc->read = azx_cc_read;
1817         cc->mask = CLOCKSOURCE_MASK(32);
1818
1819         /*
1820          * Converting from 24 MHz to ns means applying a 125/3 factor.
1821          * To avoid any saturation issues in intermediate operations,
1822          * the 125 factor is applied first. The division is applied
1823          * last after reading the timecounter value.
1824          * Applying the 1/3 factor as part of the multiplication
1825          * requires at least 20 bits for a decent precision, however
1826          * overflows occur after about 4 hours or less, not a option.
1827          */
1828
1829         cc->mult = 125; /* saturation after 195 years */
1830         cc->shift = 0;
1831
1832         nsec = 0; /* audio time is elapsed time since trigger */
1833         timecounter_init(tc, cc, nsec);
1834         if (force)
1835                 /*
1836                  * force timecounter to use predefined value,
1837                  * used for synchronized starts
1838                  */
1839                 tc->cycle_last = last;
1840 }
1841
1842 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1843                                 struct timespec *ts)
1844 {
1845         struct azx_dev *azx_dev = get_azx_dev(substream);
1846         u64 nsec;
1847
1848         nsec = timecounter_read(&azx_dev->azx_tc);
1849         nsec = div_u64(nsec, 3); /* can be optimized */
1850
1851         *ts = ns_to_timespec(nsec);
1852
1853         return 0;
1854 }
1855
1856 static struct snd_pcm_hardware azx_pcm_hw = {
1857         .info =                 (SNDRV_PCM_INFO_MMAP |
1858                                  SNDRV_PCM_INFO_INTERLEAVED |
1859                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1860                                  SNDRV_PCM_INFO_MMAP_VALID |
1861                                  /* No full-resume yet implemented */
1862                                  /* SNDRV_PCM_INFO_RESUME |*/
1863                                  SNDRV_PCM_INFO_PAUSE |
1864                                  SNDRV_PCM_INFO_SYNC_START |
1865                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1866                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1867         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1868         .rates =                SNDRV_PCM_RATE_48000,
1869         .rate_min =             48000,
1870         .rate_max =             48000,
1871         .channels_min =         2,
1872         .channels_max =         2,
1873         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1874         .period_bytes_min =     128,
1875         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1876         .periods_min =          2,
1877         .periods_max =          AZX_MAX_FRAG,
1878         .fifo_size =            0,
1879 };
1880
1881 static int azx_pcm_open(struct snd_pcm_substream *substream)
1882 {
1883         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1884         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1885         struct azx *chip = apcm->chip;
1886         struct azx_dev *azx_dev;
1887         struct snd_pcm_runtime *runtime = substream->runtime;
1888         unsigned long flags;
1889         int err;
1890         int buff_step;
1891
1892         mutex_lock(&chip->open_mutex);
1893         azx_dev = azx_assign_device(chip, substream);
1894         if (azx_dev == NULL) {
1895                 mutex_unlock(&chip->open_mutex);
1896                 return -EBUSY;
1897         }
1898         runtime->hw = azx_pcm_hw;
1899         runtime->hw.channels_min = hinfo->channels_min;
1900         runtime->hw.channels_max = hinfo->channels_max;
1901         runtime->hw.formats = hinfo->formats;
1902         runtime->hw.rates = hinfo->rates;
1903         snd_pcm_limit_hw_rates(runtime);
1904         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1905
1906         /* avoid wrap-around with wall-clock */
1907         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1908                                 20,
1909                                 178000000);
1910
1911         if (chip->align_buffer_size)
1912                 /* constrain buffer sizes to be multiple of 128
1913                    bytes. This is more efficient in terms of memory
1914                    access but isn't required by the HDA spec and
1915                    prevents users from specifying exact period/buffer
1916                    sizes. For example for 44.1kHz, a period size set
1917                    to 20ms will be rounded to 19.59ms. */
1918                 buff_step = 128;
1919         else
1920                 /* Don't enforce steps on buffer sizes, still need to
1921                    be multiple of 4 bytes (HDA spec). Tested on Intel
1922                    HDA controllers, may not work on all devices where
1923                    option needs to be disabled */
1924                 buff_step = 4;
1925
1926         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1927                                    buff_step);
1928         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1929                                    buff_step);
1930         snd_hda_power_up_d3wait(apcm->codec);
1931         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1932         if (err < 0) {
1933                 azx_release_device(azx_dev);
1934                 snd_hda_power_down(apcm->codec);
1935                 mutex_unlock(&chip->open_mutex);
1936                 return err;
1937         }
1938         snd_pcm_limit_hw_rates(runtime);
1939         /* sanity check */
1940         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1941             snd_BUG_ON(!runtime->hw.channels_max) ||
1942             snd_BUG_ON(!runtime->hw.formats) ||
1943             snd_BUG_ON(!runtime->hw.rates)) {
1944                 azx_release_device(azx_dev);
1945                 hinfo->ops.close(hinfo, apcm->codec, substream);
1946                 snd_hda_power_down(apcm->codec);
1947                 mutex_unlock(&chip->open_mutex);
1948                 return -EINVAL;
1949         }
1950
1951         /* disable WALLCLOCK timestamps for capture streams
1952            until we figure out how to handle digital inputs */
1953         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1954                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1955
1956         spin_lock_irqsave(&chip->reg_lock, flags);
1957         azx_dev->substream = substream;
1958         azx_dev->running = 0;
1959         spin_unlock_irqrestore(&chip->reg_lock, flags);
1960
1961         runtime->private_data = azx_dev;
1962         snd_pcm_set_sync(substream);
1963         mutex_unlock(&chip->open_mutex);
1964         return 0;
1965 }
1966
1967 static int azx_pcm_close(struct snd_pcm_substream *substream)
1968 {
1969         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1970         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1971         struct azx *chip = apcm->chip;
1972         struct azx_dev *azx_dev = get_azx_dev(substream);
1973         unsigned long flags;
1974
1975         mutex_lock(&chip->open_mutex);
1976         spin_lock_irqsave(&chip->reg_lock, flags);
1977         azx_dev->substream = NULL;
1978         azx_dev->running = 0;
1979         spin_unlock_irqrestore(&chip->reg_lock, flags);
1980         azx_release_device(azx_dev);
1981         hinfo->ops.close(hinfo, apcm->codec, substream);
1982         snd_hda_power_down(apcm->codec);
1983         mutex_unlock(&chip->open_mutex);
1984         return 0;
1985 }
1986
1987 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1988                              struct snd_pcm_hw_params *hw_params)
1989 {
1990         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1991         struct azx *chip = apcm->chip;
1992         struct azx_dev *azx_dev = get_azx_dev(substream);
1993         int ret;
1994
1995         mark_runtime_wc(chip, azx_dev, substream, false);
1996         azx_dev->bufsize = 0;
1997         azx_dev->period_bytes = 0;
1998         azx_dev->format_val = 0;
1999         ret = snd_pcm_lib_malloc_pages(substream,
2000                                         params_buffer_bytes(hw_params));
2001         if (ret < 0)
2002                 return ret;
2003         mark_runtime_wc(chip, azx_dev, substream, true);
2004         return ret;
2005 }
2006
2007 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2008 {
2009         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2010         struct azx_dev *azx_dev = get_azx_dev(substream);
2011         struct azx *chip = apcm->chip;
2012         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2013
2014         /* reset BDL address */
2015         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2016         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2017         azx_sd_writel(azx_dev, SD_CTL, 0);
2018         azx_dev->bufsize = 0;
2019         azx_dev->period_bytes = 0;
2020         azx_dev->format_val = 0;
2021
2022         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2023
2024         mark_runtime_wc(chip, azx_dev, substream, false);
2025         return snd_pcm_lib_free_pages(substream);
2026 }
2027
2028 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2029 {
2030         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2031         struct azx *chip = apcm->chip;
2032         struct azx_dev *azx_dev = get_azx_dev(substream);
2033         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2034         struct snd_pcm_runtime *runtime = substream->runtime;
2035         unsigned int bufsize, period_bytes, format_val, stream_tag;
2036         int err;
2037         struct hda_spdif_out *spdif =
2038                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2039         unsigned short ctls = spdif ? spdif->ctls : 0;
2040
2041         azx_stream_reset(chip, azx_dev);
2042         format_val = snd_hda_calc_stream_format(runtime->rate,
2043                                                 runtime->channels,
2044                                                 runtime->format,
2045                                                 hinfo->maxbps,
2046                                                 ctls);
2047         if (!format_val) {
2048                 snd_printk(KERN_ERR SFX
2049                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2050                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2051                 return -EINVAL;
2052         }
2053
2054         bufsize = snd_pcm_lib_buffer_bytes(substream);
2055         period_bytes = snd_pcm_lib_period_bytes(substream);
2056
2057         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2058                     pci_name(chip->pci), bufsize, format_val);
2059
2060         if (bufsize != azx_dev->bufsize ||
2061             period_bytes != azx_dev->period_bytes ||
2062             format_val != azx_dev->format_val ||
2063             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2064                 azx_dev->bufsize = bufsize;
2065                 azx_dev->period_bytes = period_bytes;
2066                 azx_dev->format_val = format_val;
2067                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2068                 err = azx_setup_periods(chip, substream, azx_dev);
2069                 if (err < 0)
2070                         return err;
2071         }
2072
2073         /* wallclk has 24Mhz clock source */
2074         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2075                                                 runtime->rate) * 1000);
2076         azx_setup_controller(chip, azx_dev);
2077         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2078                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2079         else
2080                 azx_dev->fifo_size = 0;
2081
2082         stream_tag = azx_dev->stream_tag;
2083         /* CA-IBG chips need the playback stream starting from 1 */
2084         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2085             stream_tag > chip->capture_streams)
2086                 stream_tag -= chip->capture_streams;
2087         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2088                                      azx_dev->format_val, substream);
2089 }
2090
2091 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2092 {
2093         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2094         struct azx *chip = apcm->chip;
2095         struct azx_dev *azx_dev;
2096         struct snd_pcm_substream *s;
2097         int rstart = 0, start, nsync = 0, sbits = 0;
2098         int nwait, timeout;
2099
2100         azx_dev = get_azx_dev(substream);
2101         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2102
2103         switch (cmd) {
2104         case SNDRV_PCM_TRIGGER_START:
2105                 rstart = 1;
2106         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2107         case SNDRV_PCM_TRIGGER_RESUME:
2108                 start = 1;
2109                 break;
2110         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2111         case SNDRV_PCM_TRIGGER_SUSPEND:
2112         case SNDRV_PCM_TRIGGER_STOP:
2113                 start = 0;
2114                 break;
2115         default:
2116                 return -EINVAL;
2117         }
2118
2119         snd_pcm_group_for_each_entry(s, substream) {
2120                 if (s->pcm->card != substream->pcm->card)
2121                         continue;
2122                 azx_dev = get_azx_dev(s);
2123                 sbits |= 1 << azx_dev->index;
2124                 nsync++;
2125                 snd_pcm_trigger_done(s, substream);
2126         }
2127
2128         spin_lock(&chip->reg_lock);
2129
2130         /* first, set SYNC bits of corresponding streams */
2131         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2132                 azx_writel(chip, OLD_SSYNC,
2133                         azx_readl(chip, OLD_SSYNC) | sbits);
2134         else
2135                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2136
2137         snd_pcm_group_for_each_entry(s, substream) {
2138                 if (s->pcm->card != substream->pcm->card)
2139                         continue;
2140                 azx_dev = get_azx_dev(s);
2141                 if (start) {
2142                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2143                         if (!rstart)
2144                                 azx_dev->start_wallclk -=
2145                                                 azx_dev->period_wallclk;
2146                         azx_stream_start(chip, azx_dev);
2147                 } else {
2148                         azx_stream_stop(chip, azx_dev);
2149                 }
2150                 azx_dev->running = start;
2151         }
2152         spin_unlock(&chip->reg_lock);
2153         if (start) {
2154                 /* wait until all FIFOs get ready */
2155                 for (timeout = 5000; timeout; timeout--) {
2156                         nwait = 0;
2157                         snd_pcm_group_for_each_entry(s, substream) {
2158                                 if (s->pcm->card != substream->pcm->card)
2159                                         continue;
2160                                 azx_dev = get_azx_dev(s);
2161                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2162                                       SD_STS_FIFO_READY))
2163                                         nwait++;
2164                         }
2165                         if (!nwait)
2166                                 break;
2167                         cpu_relax();
2168                 }
2169         } else {
2170                 /* wait until all RUN bits are cleared */
2171                 for (timeout = 5000; timeout; timeout--) {
2172                         nwait = 0;
2173                         snd_pcm_group_for_each_entry(s, substream) {
2174                                 if (s->pcm->card != substream->pcm->card)
2175                                         continue;
2176                                 azx_dev = get_azx_dev(s);
2177                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2178                                     SD_CTL_DMA_START)
2179                                         nwait++;
2180                         }
2181                         if (!nwait)
2182                                 break;
2183                         cpu_relax();
2184                 }
2185         }
2186         spin_lock(&chip->reg_lock);
2187         /* reset SYNC bits */
2188         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2189                 azx_writel(chip, OLD_SSYNC,
2190                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2191         else
2192                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2193         if (start) {
2194                 azx_timecounter_init(substream, 0, 0);
2195                 if (nsync > 1) {
2196                         cycle_t cycle_last;
2197
2198                         /* same start cycle for master and group */
2199                         azx_dev = get_azx_dev(substream);
2200                         cycle_last = azx_dev->azx_tc.cycle_last;
2201
2202                         snd_pcm_group_for_each_entry(s, substream) {
2203                                 if (s->pcm->card != substream->pcm->card)
2204                                         continue;
2205                                 azx_timecounter_init(s, 1, cycle_last);
2206                         }
2207                 }
2208         }
2209         spin_unlock(&chip->reg_lock);
2210         return 0;
2211 }
2212
2213 /* get the current DMA position with correction on VIA chips */
2214 static unsigned int azx_via_get_position(struct azx *chip,
2215                                          struct azx_dev *azx_dev)
2216 {
2217         unsigned int link_pos, mini_pos, bound_pos;
2218         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2219         unsigned int fifo_size;
2220
2221         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2222         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2223                 /* Playback, no problem using link position */
2224                 return link_pos;
2225         }
2226
2227         /* Capture */
2228         /* For new chipset,
2229          * use mod to get the DMA position just like old chipset
2230          */
2231         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2232         mod_dma_pos %= azx_dev->period_bytes;
2233
2234         /* azx_dev->fifo_size can't get FIFO size of in stream.
2235          * Get from base address + offset.
2236          */
2237         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2238
2239         if (azx_dev->insufficient) {
2240                 /* Link position never gather than FIFO size */
2241                 if (link_pos <= fifo_size)
2242                         return 0;
2243
2244                 azx_dev->insufficient = 0;
2245         }
2246
2247         if (link_pos <= fifo_size)
2248                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2249         else
2250                 mini_pos = link_pos - fifo_size;
2251
2252         /* Find nearest previous boudary */
2253         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2254         mod_link_pos = link_pos % azx_dev->period_bytes;
2255         if (mod_link_pos >= fifo_size)
2256                 bound_pos = link_pos - mod_link_pos;
2257         else if (mod_dma_pos >= mod_mini_pos)
2258                 bound_pos = mini_pos - mod_mini_pos;
2259         else {
2260                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2261                 if (bound_pos >= azx_dev->bufsize)
2262                         bound_pos = 0;
2263         }
2264
2265         /* Calculate real DMA position we want */
2266         return bound_pos + mod_dma_pos;
2267 }
2268
2269 static unsigned int azx_get_position(struct azx *chip,
2270                                      struct azx_dev *azx_dev,
2271                                      bool with_check)
2272 {
2273         unsigned int pos;
2274         int stream = azx_dev->substream->stream;
2275         int delay = 0;
2276
2277         switch (chip->position_fix[stream]) {
2278         case POS_FIX_LPIB:
2279                 /* read LPIB */
2280                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2281                 break;
2282         case POS_FIX_VIACOMBO:
2283                 pos = azx_via_get_position(chip, azx_dev);
2284                 break;
2285         default:
2286                 /* use the position buffer */
2287                 pos = le32_to_cpu(*azx_dev->posbuf);
2288                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2289                         if (!pos || pos == (u32)-1) {
2290                                 printk(KERN_WARNING
2291                                        "hda-intel: Invalid position buffer, "
2292                                        "using LPIB read method instead.\n");
2293                                 chip->position_fix[stream] = POS_FIX_LPIB;
2294                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2295                         } else
2296                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2297                 }
2298                 break;
2299         }
2300
2301         if (pos >= azx_dev->bufsize)
2302                 pos = 0;
2303
2304         /* calculate runtime delay from LPIB */
2305         if (azx_dev->substream->runtime &&
2306             chip->position_fix[stream] == POS_FIX_POSBUF &&
2307             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2308                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2309                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2310                         delay = pos - lpib_pos;
2311                 else
2312                         delay = lpib_pos - pos;
2313                 if (delay < 0)
2314                         delay += azx_dev->bufsize;
2315                 if (delay >= azx_dev->period_bytes) {
2316                         snd_printk(KERN_WARNING SFX
2317                                    "%s: Unstable LPIB (%d >= %d); "
2318                                    "disabling LPIB delay counting\n",
2319                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2320                         delay = 0;
2321                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2322                 }
2323                 azx_dev->substream->runtime->delay =
2324                         bytes_to_frames(azx_dev->substream->runtime, delay);
2325         }
2326         trace_azx_get_position(chip, azx_dev, pos, delay);
2327         return pos;
2328 }
2329
2330 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2331 {
2332         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2333         struct azx *chip = apcm->chip;
2334         struct azx_dev *azx_dev = get_azx_dev(substream);
2335         return bytes_to_frames(substream->runtime,
2336                                azx_get_position(chip, azx_dev, false));
2337 }
2338
2339 /*
2340  * Check whether the current DMA position is acceptable for updating
2341  * periods.  Returns non-zero if it's OK.
2342  *
2343  * Many HD-audio controllers appear pretty inaccurate about
2344  * the update-IRQ timing.  The IRQ is issued before actually the
2345  * data is processed.  So, we need to process it afterwords in a
2346  * workqueue.
2347  */
2348 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2349 {
2350         u32 wallclk;
2351         unsigned int pos;
2352
2353         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2354         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2355                 return -1;      /* bogus (too early) interrupt */
2356
2357         pos = azx_get_position(chip, azx_dev, true);
2358
2359         if (WARN_ONCE(!azx_dev->period_bytes,
2360                       "hda-intel: zero azx_dev->period_bytes"))
2361                 return -1; /* this shouldn't happen! */
2362         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2363             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2364                 /* NG - it's below the first next period boundary */
2365                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2366         azx_dev->start_wallclk += wallclk;
2367         return 1; /* OK, it's fine */
2368 }
2369
2370 /*
2371  * The work for pending PCM period updates.
2372  */
2373 static void azx_irq_pending_work(struct work_struct *work)
2374 {
2375         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2376         int i, pending, ok;
2377
2378         if (!chip->irq_pending_warned) {
2379                 printk(KERN_WARNING
2380                        "hda-intel: IRQ timing workaround is activated "
2381                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2382                        chip->card->number);
2383                 chip->irq_pending_warned = 1;
2384         }
2385
2386         for (;;) {
2387                 pending = 0;
2388                 spin_lock_irq(&chip->reg_lock);
2389                 for (i = 0; i < chip->num_streams; i++) {
2390                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2391                         if (!azx_dev->irq_pending ||
2392                             !azx_dev->substream ||
2393                             !azx_dev->running)
2394                                 continue;
2395                         ok = azx_position_ok(chip, azx_dev);
2396                         if (ok > 0) {
2397                                 azx_dev->irq_pending = 0;
2398                                 spin_unlock(&chip->reg_lock);
2399                                 snd_pcm_period_elapsed(azx_dev->substream);
2400                                 spin_lock(&chip->reg_lock);
2401                         } else if (ok < 0) {
2402                                 pending = 0;    /* too early */
2403                         } else
2404                                 pending++;
2405                 }
2406                 spin_unlock_irq(&chip->reg_lock);
2407                 if (!pending)
2408                         return;
2409                 msleep(1);
2410         }
2411 }
2412
2413 /* clear irq_pending flags and assure no on-going workq */
2414 static void azx_clear_irq_pending(struct azx *chip)
2415 {
2416         int i;
2417
2418         spin_lock_irq(&chip->reg_lock);
2419         for (i = 0; i < chip->num_streams; i++)
2420                 chip->azx_dev[i].irq_pending = 0;
2421         spin_unlock_irq(&chip->reg_lock);
2422 }
2423
2424 #ifdef CONFIG_X86
2425 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2426                         struct vm_area_struct *area)
2427 {
2428         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2429         struct azx *chip = apcm->chip;
2430         if (!azx_snoop(chip))
2431                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2432         return snd_pcm_lib_default_mmap(substream, area);
2433 }
2434 #else
2435 #define azx_pcm_mmap    NULL
2436 #endif
2437
2438 static struct snd_pcm_ops azx_pcm_ops = {
2439         .open = azx_pcm_open,
2440         .close = azx_pcm_close,
2441         .ioctl = snd_pcm_lib_ioctl,
2442         .hw_params = azx_pcm_hw_params,
2443         .hw_free = azx_pcm_hw_free,
2444         .prepare = azx_pcm_prepare,
2445         .trigger = azx_pcm_trigger,
2446         .pointer = azx_pcm_pointer,
2447         .wall_clock =  azx_get_wallclock_tstamp,
2448         .mmap = azx_pcm_mmap,
2449         .page = snd_pcm_sgbuf_ops_page,
2450 };
2451
2452 static void azx_pcm_free(struct snd_pcm *pcm)
2453 {
2454         struct azx_pcm *apcm = pcm->private_data;
2455         if (apcm) {
2456                 list_del(&apcm->list);
2457                 kfree(apcm);
2458         }
2459 }
2460
2461 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2462
2463 static int
2464 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2465                       struct hda_pcm *cpcm)
2466 {
2467         struct azx *chip = bus->private_data;
2468         struct snd_pcm *pcm;
2469         struct azx_pcm *apcm;
2470         int pcm_dev = cpcm->device;
2471         unsigned int size;
2472         int s, err;
2473
2474         list_for_each_entry(apcm, &chip->pcm_list, list) {
2475                 if (apcm->pcm->device == pcm_dev) {
2476                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2477                                    pci_name(chip->pci), pcm_dev);
2478                         return -EBUSY;
2479                 }
2480         }
2481         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2482                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2483                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2484                           &pcm);
2485         if (err < 0)
2486                 return err;
2487         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2488         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2489         if (apcm == NULL)
2490                 return -ENOMEM;
2491         apcm->chip = chip;
2492         apcm->pcm = pcm;
2493         apcm->codec = codec;
2494         pcm->private_data = apcm;
2495         pcm->private_free = azx_pcm_free;
2496         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2497                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2498         list_add_tail(&apcm->list, &chip->pcm_list);
2499         cpcm->pcm = pcm;
2500         for (s = 0; s < 2; s++) {
2501                 apcm->hinfo[s] = &cpcm->stream[s];
2502                 if (cpcm->stream[s].substreams)
2503                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2504         }
2505         /* buffer pre-allocation */
2506         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2507         if (size > MAX_PREALLOC_SIZE)
2508                 size = MAX_PREALLOC_SIZE;
2509         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2510                                               snd_dma_pci_data(chip->pci),
2511                                               size, MAX_PREALLOC_SIZE);
2512         return 0;
2513 }
2514
2515 /*
2516  * mixer creation - all stuff is implemented in hda module
2517  */
2518 static int azx_mixer_create(struct azx *chip)
2519 {
2520         return snd_hda_build_controls(chip->bus);
2521 }
2522
2523
2524 /*
2525  * initialize SD streams
2526  */
2527 static int azx_init_stream(struct azx *chip)
2528 {
2529         int i;
2530
2531         /* initialize each stream (aka device)
2532          * assign the starting bdl address to each stream (device)
2533          * and initialize
2534          */
2535         for (i = 0; i < chip->num_streams; i++) {
2536                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2537                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2538                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2539                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2540                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2541                 azx_dev->sd_int_sta_mask = 1 << i;
2542                 /* stream tag: must be non-zero and unique */
2543                 azx_dev->index = i;
2544                 azx_dev->stream_tag = i + 1;
2545         }
2546
2547         return 0;
2548 }
2549
2550 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2551 {
2552         if (request_irq(chip->pci->irq, azx_interrupt,
2553                         chip->msi ? 0 : IRQF_SHARED,
2554                         KBUILD_MODNAME, chip)) {
2555                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2556                        "disabling device\n", chip->pci->irq);
2557                 if (do_disconnect)
2558                         snd_card_disconnect(chip->card);
2559                 return -1;
2560         }
2561         chip->irq = chip->pci->irq;
2562         pci_intx(chip->pci, !chip->msi);
2563         return 0;
2564 }
2565
2566
2567 static void azx_stop_chip(struct azx *chip)
2568 {
2569         if (!chip->initialized)
2570                 return;
2571
2572         /* disable interrupts */
2573         azx_int_disable(chip);
2574         azx_int_clear(chip);
2575
2576         /* disable CORB/RIRB */
2577         azx_free_cmd_io(chip);
2578
2579         /* disable position buffer */
2580         azx_writel(chip, DPLBASE, 0);
2581         azx_writel(chip, DPUBASE, 0);
2582
2583         chip->initialized = 0;
2584 }
2585
2586 #ifdef CONFIG_PM
2587 /* power-up/down the controller */
2588 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2589 {
2590         struct azx *chip = bus->private_data;
2591
2592         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2593                 return;
2594
2595         if (power_up)
2596                 pm_runtime_get_sync(&chip->pci->dev);
2597         else
2598                 pm_runtime_put_sync(&chip->pci->dev);
2599 }
2600
2601 static DEFINE_MUTEX(card_list_lock);
2602 static LIST_HEAD(card_list);
2603
2604 static void azx_add_card_list(struct azx *chip)
2605 {
2606         mutex_lock(&card_list_lock);
2607         list_add(&chip->list, &card_list);
2608         mutex_unlock(&card_list_lock);
2609 }
2610
2611 static void azx_del_card_list(struct azx *chip)
2612 {
2613         mutex_lock(&card_list_lock);
2614         list_del_init(&chip->list);
2615         mutex_unlock(&card_list_lock);
2616 }
2617
2618 /* trigger power-save check at writing parameter */
2619 static int param_set_xint(const char *val, const struct kernel_param *kp)
2620 {
2621         struct azx *chip;
2622         struct hda_codec *c;
2623         int prev = power_save;
2624         int ret = param_set_int(val, kp);
2625
2626         if (ret || prev == power_save)
2627                 return ret;
2628
2629         mutex_lock(&card_list_lock);
2630         list_for_each_entry(chip, &card_list, list) {
2631                 if (!chip->bus || chip->disabled)
2632                         continue;
2633                 list_for_each_entry(c, &chip->bus->codec_list, list)
2634                         snd_hda_power_sync(c);
2635         }
2636         mutex_unlock(&card_list_lock);
2637         return 0;
2638 }
2639 #else
2640 #define azx_add_card_list(chip) /* NOP */
2641 #define azx_del_card_list(chip) /* NOP */
2642 #endif /* CONFIG_PM */
2643
2644 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2645 /*
2646  * power management
2647  */
2648 static int azx_suspend(struct device *dev)
2649 {
2650         struct pci_dev *pci = to_pci_dev(dev);
2651         struct snd_card *card = dev_get_drvdata(dev);
2652         struct azx *chip = card->private_data;
2653         struct azx_pcm *p;
2654
2655         if (chip->disabled)
2656                 return 0;
2657
2658         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2659         azx_clear_irq_pending(chip);
2660         list_for_each_entry(p, &chip->pcm_list, list)
2661                 snd_pcm_suspend_all(p->pcm);
2662         if (chip->initialized)
2663                 snd_hda_suspend(chip->bus);
2664         azx_stop_chip(chip);
2665         if (chip->irq >= 0) {
2666                 free_irq(chip->irq, chip);
2667                 chip->irq = -1;
2668         }
2669         if (chip->msi)
2670                 pci_disable_msi(chip->pci);
2671         pci_disable_device(pci);
2672         pci_save_state(pci);
2673         pci_set_power_state(pci, PCI_D3hot);
2674         return 0;
2675 }
2676
2677 static int azx_resume(struct device *dev)
2678 {
2679         struct pci_dev *pci = to_pci_dev(dev);
2680         struct snd_card *card = dev_get_drvdata(dev);
2681         struct azx *chip = card->private_data;
2682
2683         if (chip->disabled)
2684                 return 0;
2685
2686         pci_set_power_state(pci, PCI_D0);
2687         pci_restore_state(pci);
2688         if (pci_enable_device(pci) < 0) {
2689                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2690                        "disabling device\n");
2691                 snd_card_disconnect(card);
2692                 return -EIO;
2693         }
2694         pci_set_master(pci);
2695         if (chip->msi)
2696                 if (pci_enable_msi(pci) < 0)
2697                         chip->msi = 0;
2698         if (azx_acquire_irq(chip, 1) < 0)
2699                 return -EIO;
2700         azx_init_pci(chip);
2701
2702         azx_init_chip(chip, 1);
2703
2704         snd_hda_resume(chip->bus);
2705         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2706         return 0;
2707 }
2708 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2709
2710 #ifdef CONFIG_PM_RUNTIME
2711 static int azx_runtime_suspend(struct device *dev)
2712 {
2713         struct snd_card *card = dev_get_drvdata(dev);
2714         struct azx *chip = card->private_data;
2715
2716         azx_stop_chip(chip);
2717         azx_clear_irq_pending(chip);
2718         return 0;
2719 }
2720
2721 static int azx_runtime_resume(struct device *dev)
2722 {
2723         struct snd_card *card = dev_get_drvdata(dev);
2724         struct azx *chip = card->private_data;
2725
2726         azx_init_pci(chip);
2727         azx_init_chip(chip, 1);
2728         return 0;
2729 }
2730
2731 static int azx_runtime_idle(struct device *dev)
2732 {
2733         struct snd_card *card = dev_get_drvdata(dev);
2734         struct azx *chip = card->private_data;
2735
2736         if (power_save_controller > 0)
2737                 return 0;
2738         if (!power_save_controller ||
2739             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2740                 return -EBUSY;
2741
2742         return 0;
2743 }
2744
2745 #endif /* CONFIG_PM_RUNTIME */
2746
2747 #ifdef CONFIG_PM
2748 static const struct dev_pm_ops azx_pm = {
2749         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2750         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2751 };
2752
2753 #define AZX_PM_OPS      &azx_pm
2754 #else
2755 #define AZX_PM_OPS      NULL
2756 #endif /* CONFIG_PM */
2757
2758
2759 /*
2760  * reboot notifier for hang-up problem at power-down
2761  */
2762 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2763 {
2764         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2765         snd_hda_bus_reboot_notify(chip->bus);
2766         azx_stop_chip(chip);
2767         return NOTIFY_OK;
2768 }
2769
2770 static void azx_notifier_register(struct azx *chip)
2771 {
2772         chip->reboot_notifier.notifier_call = azx_halt;
2773         register_reboot_notifier(&chip->reboot_notifier);
2774 }
2775
2776 static void azx_notifier_unregister(struct azx *chip)
2777 {
2778         if (chip->reboot_notifier.notifier_call)
2779                 unregister_reboot_notifier(&chip->reboot_notifier);
2780 }
2781
2782 static int azx_first_init(struct azx *chip);
2783 static int azx_probe_continue(struct azx *chip);
2784
2785 #ifdef SUPPORT_VGA_SWITCHEROO
2786 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2787
2788 static void azx_vs_set_state(struct pci_dev *pci,
2789                              enum vga_switcheroo_state state)
2790 {
2791         struct snd_card *card = pci_get_drvdata(pci);
2792         struct azx *chip = card->private_data;
2793         bool disabled;
2794
2795         wait_for_completion(&chip->probe_wait);
2796         if (chip->init_failed)
2797                 return;
2798
2799         disabled = (state == VGA_SWITCHEROO_OFF);
2800         if (chip->disabled == disabled)
2801                 return;
2802
2803         if (!chip->bus) {
2804                 chip->disabled = disabled;
2805                 if (!disabled) {
2806                         snd_printk(KERN_INFO SFX
2807                                    "%s: Start delayed initialization\n",
2808                                    pci_name(chip->pci));
2809                         if (azx_first_init(chip) < 0 ||
2810                             azx_probe_continue(chip) < 0) {
2811                                 snd_printk(KERN_ERR SFX
2812                                            "%s: initialization error\n",
2813                                            pci_name(chip->pci));
2814                                 chip->init_failed = true;
2815                         }
2816                 }
2817         } else {
2818                 snd_printk(KERN_INFO SFX
2819                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2820                            disabled ? "Disabling" : "Enabling");
2821                 if (disabled) {
2822                         azx_suspend(&pci->dev);
2823                         chip->disabled = true;
2824                         if (snd_hda_lock_devices(chip->bus))
2825                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2826                                            pci_name(chip->pci));
2827                 } else {
2828                         snd_hda_unlock_devices(chip->bus);
2829                         chip->disabled = false;
2830                         azx_resume(&pci->dev);
2831                 }
2832         }
2833 }
2834
2835 static bool azx_vs_can_switch(struct pci_dev *pci)
2836 {
2837         struct snd_card *card = pci_get_drvdata(pci);
2838         struct azx *chip = card->private_data;
2839
2840         wait_for_completion(&chip->probe_wait);
2841         if (chip->init_failed)
2842                 return false;
2843         if (chip->disabled || !chip->bus)
2844                 return true;
2845         if (snd_hda_lock_devices(chip->bus))
2846                 return false;
2847         snd_hda_unlock_devices(chip->bus);
2848         return true;
2849 }
2850
2851 static void init_vga_switcheroo(struct azx *chip)
2852 {
2853         struct pci_dev *p = get_bound_vga(chip->pci);
2854         if (p) {
2855                 snd_printk(KERN_INFO SFX
2856                            "%s: Handle VGA-switcheroo audio client\n",
2857                            pci_name(chip->pci));
2858                 chip->use_vga_switcheroo = 1;
2859                 pci_dev_put(p);
2860         }
2861 }
2862
2863 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2864         .set_gpu_state = azx_vs_set_state,
2865         .can_switch = azx_vs_can_switch,
2866 };
2867
2868 static int register_vga_switcheroo(struct azx *chip)
2869 {
2870         int err;
2871
2872         if (!chip->use_vga_switcheroo)
2873                 return 0;
2874         /* FIXME: currently only handling DIS controller
2875          * is there any machine with two switchable HDMI audio controllers?
2876          */
2877         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2878                                                     VGA_SWITCHEROO_DIS,
2879                                                     chip->bus != NULL);
2880         if (err < 0)
2881                 return err;
2882         chip->vga_switcheroo_registered = 1;
2883         return 0;
2884 }
2885 #else
2886 #define init_vga_switcheroo(chip)               /* NOP */
2887 #define register_vga_switcheroo(chip)           0
2888 #define check_hdmi_disabled(pci)        false
2889 #endif /* SUPPORT_VGA_SWITCHER */
2890
2891 /*
2892  * destructor
2893  */
2894 static int azx_free(struct azx *chip)
2895 {
2896         int i;
2897
2898         azx_del_card_list(chip);
2899
2900         azx_notifier_unregister(chip);
2901
2902         chip->init_failed = 1; /* to be sure */
2903         complete_all(&chip->probe_wait);
2904
2905         if (use_vga_switcheroo(chip)) {
2906                 if (chip->disabled && chip->bus)
2907                         snd_hda_unlock_devices(chip->bus);
2908                 if (chip->vga_switcheroo_registered)
2909                         vga_switcheroo_unregister_client(chip->pci);
2910         }
2911
2912         if (chip->initialized) {
2913                 azx_clear_irq_pending(chip);
2914                 for (i = 0; i < chip->num_streams; i++)
2915                         azx_stream_stop(chip, &chip->azx_dev[i]);
2916                 azx_stop_chip(chip);
2917         }
2918
2919         if (chip->irq >= 0)
2920                 free_irq(chip->irq, (void*)chip);
2921         if (chip->msi)
2922                 pci_disable_msi(chip->pci);
2923         if (chip->remap_addr)
2924                 iounmap(chip->remap_addr);
2925
2926         if (chip->azx_dev) {
2927                 for (i = 0; i < chip->num_streams; i++)
2928                         if (chip->azx_dev[i].bdl.area) {
2929                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2930                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2931                         }
2932         }
2933         if (chip->rb.area) {
2934                 mark_pages_wc(chip, &chip->rb, false);
2935                 snd_dma_free_pages(&chip->rb);
2936         }
2937         if (chip->posbuf.area) {
2938                 mark_pages_wc(chip, &chip->posbuf, false);
2939                 snd_dma_free_pages(&chip->posbuf);
2940         }
2941         if (chip->region_requested)
2942                 pci_release_regions(chip->pci);
2943         pci_disable_device(chip->pci);
2944         kfree(chip->azx_dev);
2945 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2946         if (chip->fw)
2947                 release_firmware(chip->fw);
2948 #endif
2949         kfree(chip);
2950
2951         return 0;
2952 }
2953
2954 static int azx_dev_free(struct snd_device *device)
2955 {
2956         return azx_free(device->device_data);
2957 }
2958
2959 #ifdef SUPPORT_VGA_SWITCHEROO
2960 /*
2961  * Check of disabled HDMI controller by vga-switcheroo
2962  */
2963 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2964 {
2965         struct pci_dev *p;
2966
2967         /* check only discrete GPU */
2968         switch (pci->vendor) {
2969         case PCI_VENDOR_ID_ATI:
2970         case PCI_VENDOR_ID_AMD:
2971         case PCI_VENDOR_ID_NVIDIA:
2972                 if (pci->devfn == 1) {
2973                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2974                                                         pci->bus->number, 0);
2975                         if (p) {
2976                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2977                                         return p;
2978                                 pci_dev_put(p);
2979                         }
2980                 }
2981                 break;
2982         }
2983         return NULL;
2984 }
2985
2986 static bool check_hdmi_disabled(struct pci_dev *pci)
2987 {
2988         bool vga_inactive = false;
2989         struct pci_dev *p = get_bound_vga(pci);
2990
2991         if (p) {
2992                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2993                         vga_inactive = true;
2994                 pci_dev_put(p);
2995         }
2996         return vga_inactive;
2997 }
2998 #endif /* SUPPORT_VGA_SWITCHEROO */
2999
3000 /*
3001  * white/black-listing for position_fix
3002  */
3003 static struct snd_pci_quirk position_fix_list[] = {
3004         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3005         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3006         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3007         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3008         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3009         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3010         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3011         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3012         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3013         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3014         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3015         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3016         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3017         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3018         {}
3019 };
3020
3021 static int check_position_fix(struct azx *chip, int fix)
3022 {
3023         const struct snd_pci_quirk *q;
3024
3025         switch (fix) {
3026         case POS_FIX_AUTO:
3027         case POS_FIX_LPIB:
3028         case POS_FIX_POSBUF:
3029         case POS_FIX_VIACOMBO:
3030         case POS_FIX_COMBO:
3031                 return fix;
3032         }
3033
3034         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3035         if (q) {
3036                 printk(KERN_INFO
3037                        "hda_intel: position_fix set to %d "
3038                        "for device %04x:%04x\n",
3039                        q->value, q->subvendor, q->subdevice);
3040                 return q->value;
3041         }
3042
3043         /* Check VIA/ATI HD Audio Controller exist */
3044         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3045                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3046                 return POS_FIX_VIACOMBO;
3047         }
3048         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3049                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3050                 return POS_FIX_LPIB;
3051         }
3052         return POS_FIX_AUTO;
3053 }
3054
3055 /*
3056  * black-lists for probe_mask
3057  */
3058 static struct snd_pci_quirk probe_mask_list[] = {
3059         /* Thinkpad often breaks the controller communication when accessing
3060          * to the non-working (or non-existing) modem codec slot.
3061          */
3062         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3063         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3064         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3065         /* broken BIOS */
3066         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3067         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3068         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3069         /* forced codec slots */
3070         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3071         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3072         /* WinFast VP200 H (Teradici) user reported broken communication */
3073         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3074         {}
3075 };
3076
3077 #define AZX_FORCE_CODEC_MASK    0x100
3078
3079 static void check_probe_mask(struct azx *chip, int dev)
3080 {
3081         const struct snd_pci_quirk *q;
3082
3083         chip->codec_probe_mask = probe_mask[dev];
3084         if (chip->codec_probe_mask == -1) {
3085                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3086                 if (q) {
3087                         printk(KERN_INFO
3088                                "hda_intel: probe_mask set to 0x%x "
3089                                "for device %04x:%04x\n",
3090                                q->value, q->subvendor, q->subdevice);
3091                         chip->codec_probe_mask = q->value;
3092                 }
3093         }
3094
3095         /* check forced option */
3096         if (chip->codec_probe_mask != -1 &&
3097             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3098                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3099                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3100                        chip->codec_mask);
3101         }
3102 }
3103
3104 /*
3105  * white/black-list for enable_msi
3106  */
3107 static struct snd_pci_quirk msi_black_list[] = {
3108         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3109         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3110         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3111         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3112         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3113         {}
3114 };
3115
3116 static void check_msi(struct azx *chip)
3117 {
3118         const struct snd_pci_quirk *q;
3119
3120         if (enable_msi >= 0) {
3121                 chip->msi = !!enable_msi;
3122                 return;
3123         }
3124         chip->msi = 1;  /* enable MSI as default */
3125         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3126         if (q) {
3127                 printk(KERN_INFO
3128                        "hda_intel: msi for device %04x:%04x set to %d\n",
3129                        q->subvendor, q->subdevice, q->value);
3130                 chip->msi = q->value;
3131                 return;
3132         }
3133
3134         /* NVidia chipsets seem to cause troubles with MSI */
3135         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3136                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3137                 chip->msi = 0;
3138         }
3139 }
3140
3141 /* check the snoop mode availability */
3142 static void azx_check_snoop_available(struct azx *chip)
3143 {
3144         bool snoop = chip->snoop;
3145
3146         switch (chip->driver_type) {
3147         case AZX_DRIVER_VIA:
3148                 /* force to non-snoop mode for a new VIA controller
3149                  * when BIOS is set
3150                  */
3151                 if (snoop) {
3152                         u8 val;
3153                         pci_read_config_byte(chip->pci, 0x42, &val);
3154                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3155                                 snoop = false;
3156                 }
3157                 break;
3158         case AZX_DRIVER_ATIHDMI_NS:
3159                 /* new ATI HDMI requires non-snoop */
3160                 snoop = false;
3161                 break;
3162         }
3163
3164         if (snoop != chip->snoop) {
3165                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3166                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3167                 chip->snoop = snoop;
3168         }
3169 }
3170
3171 /*
3172  * constructor
3173  */
3174 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3175                       int dev, unsigned int driver_caps,
3176                       struct azx **rchip)
3177 {
3178         static struct snd_device_ops ops = {
3179                 .dev_free = azx_dev_free,
3180         };
3181         struct azx *chip;
3182         int err;
3183
3184         *rchip = NULL;
3185
3186         err = pci_enable_device(pci);
3187         if (err < 0)
3188                 return err;
3189
3190         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3191         if (!chip) {
3192                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3193                 pci_disable_device(pci);
3194                 return -ENOMEM;
3195         }
3196
3197         spin_lock_init(&chip->reg_lock);
3198         mutex_init(&chip->open_mutex);
3199         chip->card = card;
3200         chip->pci = pci;
3201         chip->irq = -1;
3202         chip->driver_caps = driver_caps;
3203         chip->driver_type = driver_caps & 0xff;
3204         check_msi(chip);
3205         chip->dev_index = dev;
3206         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3207         INIT_LIST_HEAD(&chip->pcm_list);
3208         INIT_LIST_HEAD(&chip->list);
3209         init_vga_switcheroo(chip);
3210         init_completion(&chip->probe_wait);
3211
3212         chip->position_fix[0] = chip->position_fix[1] =
3213                 check_position_fix(chip, position_fix[dev]);
3214         /* combo mode uses LPIB for playback */
3215         if (chip->position_fix[0] == POS_FIX_COMBO) {
3216                 chip->position_fix[0] = POS_FIX_LPIB;
3217                 chip->position_fix[1] = POS_FIX_AUTO;
3218         }
3219
3220         check_probe_mask(chip, dev);
3221
3222         chip->single_cmd = single_cmd;
3223         chip->snoop = hda_snoop;
3224         azx_check_snoop_available(chip);
3225
3226         if (bdl_pos_adj[dev] < 0) {
3227                 switch (chip->driver_type) {
3228                 case AZX_DRIVER_ICH:
3229                 case AZX_DRIVER_PCH:
3230                         bdl_pos_adj[dev] = 1;
3231                         break;
3232                 default:
3233                         bdl_pos_adj[dev] = 32;
3234                         break;
3235                 }
3236         }
3237
3238         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3239         if (err < 0) {
3240                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3241                    pci_name(chip->pci));
3242                 azx_free(chip);
3243                 return err;
3244         }
3245
3246         *rchip = chip;
3247         return 0;
3248 }
3249
3250 static int azx_first_init(struct azx *chip)
3251 {
3252         int dev = chip->dev_index;
3253         struct pci_dev *pci = chip->pci;
3254         struct snd_card *card = chip->card;
3255         int i, err;
3256         unsigned short gcap;
3257
3258 #if BITS_PER_LONG != 64
3259         /* Fix up base address on ULI M5461 */
3260         if (chip->driver_type == AZX_DRIVER_ULI) {
3261                 u16 tmp3;
3262                 pci_read_config_word(pci, 0x40, &tmp3);
3263                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3264                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3265         }
3266 #endif
3267
3268         err = pci_request_regions(pci, "ICH HD audio");
3269         if (err < 0)
3270                 return err;
3271         chip->region_requested = 1;
3272
3273         chip->addr = pci_resource_start(pci, 0);
3274         chip->remap_addr = pci_ioremap_bar(pci, 0);
3275         if (chip->remap_addr == NULL) {
3276                 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3277                 return -ENXIO;
3278         }
3279
3280         if (chip->msi)
3281                 if (pci_enable_msi(pci) < 0)
3282                         chip->msi = 0;
3283
3284         if (azx_acquire_irq(chip, 0) < 0)
3285                 return -EBUSY;
3286
3287         pci_set_master(pci);
3288         synchronize_irq(chip->irq);
3289
3290         gcap = azx_readw(chip, GCAP);
3291         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3292
3293         /* disable SB600 64bit support for safety */
3294         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3295                 struct pci_dev *p_smbus;
3296                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3297                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3298                                          NULL);
3299                 if (p_smbus) {
3300                         if (p_smbus->revision < 0x30)
3301                                 gcap &= ~ICH6_GCAP_64OK;
3302                         pci_dev_put(p_smbus);
3303                 }
3304         }
3305
3306         /* disable 64bit DMA address on some devices */
3307         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3308                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3309                 gcap &= ~ICH6_GCAP_64OK;
3310         }
3311
3312         /* disable buffer size rounding to 128-byte multiples if supported */
3313         if (align_buffer_size >= 0)
3314                 chip->align_buffer_size = !!align_buf