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ASoC: wm8994: Only enable extra BCLK cycles when required
[~shefty/rdma-dev.git] / sound / soc / codecs / wm8994.c
1 /*
2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
3  *
4  * Copyright 2009-12 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE  0x0000
42 #define WM1811_JACKDET_MODE_JACK  0x0100
43 #define WM1811_JACKDET_MODE_MIC   0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ  3
48
49 static struct {
50         unsigned int reg;
51         unsigned int mask;
52 } wm8994_vu_bits[] = {
53         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80 };
81
82 static int wm8994_drc_base[] = {
83         WM8994_AIF1_DRC1_1,
84         WM8994_AIF1_DRC2_1,
85         WM8994_AIF2_DRC_1,
86 };
87
88 static int wm8994_retune_mobile_base[] = {
89         WM8994_AIF1_DAC1_EQ_GAINS_1,
90         WM8994_AIF1_DAC2_EQ_GAINS_1,
91         WM8994_AIF2_EQ_GAINS_1,
92 };
93
94 static void wm8958_default_micdet(u16 status, void *data);
95
96 static const struct wm8958_micd_rate micdet_rates[] = {
97         { 32768,       true,  1, 4 },
98         { 32768,       false, 1, 1 },
99         { 44100 * 256, true,  7, 10 },
100         { 44100 * 256, false, 7, 10 },
101 };
102
103 static const struct wm8958_micd_rate jackdet_rates[] = {
104         { 32768,       true,  0, 1 },
105         { 32768,       false, 0, 1 },
106         { 44100 * 256, true,  10, 10 },
107         { 44100 * 256, false, 7, 8 },
108 };
109
110 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
111 {
112         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
113         int best, i, sysclk, val;
114         bool idle;
115         const struct wm8958_micd_rate *rates;
116         int num_rates;
117
118         if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
119             wm8994->jack_cb != wm8958_default_micdet)
120                 return;
121
122         idle = !wm8994->jack_mic;
123
124         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
125         if (sysclk & WM8994_SYSCLK_SRC)
126                 sysclk = wm8994->aifclk[1];
127         else
128                 sysclk = wm8994->aifclk[0];
129
130         if (wm8994->pdata && wm8994->pdata->micd_rates) {
131                 rates = wm8994->pdata->micd_rates;
132                 num_rates = wm8994->pdata->num_micd_rates;
133         } else if (wm8994->jackdet) {
134                 rates = jackdet_rates;
135                 num_rates = ARRAY_SIZE(jackdet_rates);
136         } else {
137                 rates = micdet_rates;
138                 num_rates = ARRAY_SIZE(micdet_rates);
139         }
140
141         best = 0;
142         for (i = 0; i < num_rates; i++) {
143                 if (rates[i].idle != idle)
144                         continue;
145                 if (abs(rates[i].sysclk - sysclk) <
146                     abs(rates[best].sysclk - sysclk))
147                         best = i;
148                 else if (rates[best].idle != idle)
149                         best = i;
150         }
151
152         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
153                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
154
155         dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
156                 rates[best].start, rates[best].rate, sysclk,
157                 idle ? "idle" : "active");
158
159         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
160                             WM8958_MICD_BIAS_STARTTIME_MASK |
161                             WM8958_MICD_RATE_MASK, val);
162 }
163
164 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
165 {
166         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
167         int rate;
168         int reg1 = 0;
169         int offset;
170
171         if (aif)
172                 offset = 4;
173         else
174                 offset = 0;
175
176         switch (wm8994->sysclk[aif]) {
177         case WM8994_SYSCLK_MCLK1:
178                 rate = wm8994->mclk[0];
179                 break;
180
181         case WM8994_SYSCLK_MCLK2:
182                 reg1 |= 0x8;
183                 rate = wm8994->mclk[1];
184                 break;
185
186         case WM8994_SYSCLK_FLL1:
187                 reg1 |= 0x10;
188                 rate = wm8994->fll[0].out;
189                 break;
190
191         case WM8994_SYSCLK_FLL2:
192                 reg1 |= 0x18;
193                 rate = wm8994->fll[1].out;
194                 break;
195
196         default:
197                 return -EINVAL;
198         }
199
200         if (rate >= 13500000) {
201                 rate /= 2;
202                 reg1 |= WM8994_AIF1CLK_DIV;
203
204                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
205                         aif + 1, rate);
206         }
207
208         wm8994->aifclk[aif] = rate;
209
210         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
211                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
212                             reg1);
213
214         return 0;
215 }
216
217 static int configure_clock(struct snd_soc_codec *codec)
218 {
219         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
220         int change, new;
221
222         /* Bring up the AIF clocks first */
223         configure_aif_clock(codec, 0);
224         configure_aif_clock(codec, 1);
225
226         /* Then switch CLK_SYS over to the higher of them; a change
227          * can only happen as a result of a clocking change which can
228          * only be made outside of DAPM so we can safely redo the
229          * clocking.
230          */
231
232         /* If they're equal it doesn't matter which is used */
233         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
234                 wm8958_micd_set_rate(codec);
235                 return 0;
236         }
237
238         if (wm8994->aifclk[0] < wm8994->aifclk[1])
239                 new = WM8994_SYSCLK_SRC;
240         else
241                 new = 0;
242
243         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
244                                      WM8994_SYSCLK_SRC, new);
245         if (change)
246                 snd_soc_dapm_sync(&codec->dapm);
247
248         wm8958_micd_set_rate(codec);
249
250         return 0;
251 }
252
253 static int check_clk_sys(struct snd_soc_dapm_widget *source,
254                          struct snd_soc_dapm_widget *sink)
255 {
256         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
257         const char *clk;
258
259         /* Check what we're currently using for CLK_SYS */
260         if (reg & WM8994_SYSCLK_SRC)
261                 clk = "AIF2CLK";
262         else
263                 clk = "AIF1CLK";
264
265         return strcmp(source->name, clk) == 0;
266 }
267
268 static const char *sidetone_hpf_text[] = {
269         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
270 };
271
272 static const struct soc_enum sidetone_hpf =
273         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
274
275 static const char *adc_hpf_text[] = {
276         "HiFi", "Voice 1", "Voice 2", "Voice 3"
277 };
278
279 static const struct soc_enum aif1adc1_hpf =
280         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
281
282 static const struct soc_enum aif1adc2_hpf =
283         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
284
285 static const struct soc_enum aif2adc_hpf =
286         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
287
288 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
289 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
290 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
292 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
293 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
295
296 #define WM8994_DRC_SWITCH(xname, reg, shift) \
297 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
298         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
299         .put = wm8994_put_drc_sw, \
300         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
301
302 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
303                              struct snd_ctl_elem_value *ucontrol)
304 {
305         struct soc_mixer_control *mc =
306                 (struct soc_mixer_control *)kcontrol->private_value;
307         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
308         int mask, ret;
309
310         /* Can't enable both ADC and DAC paths simultaneously */
311         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
312                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
313                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
314         else
315                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
316
317         ret = snd_soc_read(codec, mc->reg);
318         if (ret < 0)
319                 return ret;
320         if (ret & mask)
321                 return -EINVAL;
322
323         return snd_soc_put_volsw(kcontrol, ucontrol);
324 }
325
326 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
327 {
328         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
329         struct wm8994_pdata *pdata = wm8994->pdata;
330         int base = wm8994_drc_base[drc];
331         int cfg = wm8994->drc_cfg[drc];
332         int save, i;
333
334         /* Save any enables; the configuration should clear them. */
335         save = snd_soc_read(codec, base);
336         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
337                 WM8994_AIF1ADC1R_DRC_ENA;
338
339         for (i = 0; i < WM8994_DRC_REGS; i++)
340                 snd_soc_update_bits(codec, base + i, 0xffff,
341                                     pdata->drc_cfgs[cfg].regs[i]);
342
343         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
344                              WM8994_AIF1ADC1L_DRC_ENA |
345                              WM8994_AIF1ADC1R_DRC_ENA, save);
346 }
347
348 /* Icky as hell but saves code duplication */
349 static int wm8994_get_drc(const char *name)
350 {
351         if (strcmp(name, "AIF1DRC1 Mode") == 0)
352                 return 0;
353         if (strcmp(name, "AIF1DRC2 Mode") == 0)
354                 return 1;
355         if (strcmp(name, "AIF2DRC Mode") == 0)
356                 return 2;
357         return -EINVAL;
358 }
359
360 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
361                                struct snd_ctl_elem_value *ucontrol)
362 {
363         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
364         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
365         struct wm8994_pdata *pdata = wm8994->pdata;
366         int drc = wm8994_get_drc(kcontrol->id.name);
367         int value = ucontrol->value.integer.value[0];
368
369         if (drc < 0)
370                 return drc;
371
372         if (value >= pdata->num_drc_cfgs)
373                 return -EINVAL;
374
375         wm8994->drc_cfg[drc] = value;
376
377         wm8994_set_drc(codec, drc);
378
379         return 0;
380 }
381
382 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
383                                struct snd_ctl_elem_value *ucontrol)
384 {
385         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
386         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
387         int drc = wm8994_get_drc(kcontrol->id.name);
388
389         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
390
391         return 0;
392 }
393
394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
395 {
396         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
397         struct wm8994_pdata *pdata = wm8994->pdata;
398         int base = wm8994_retune_mobile_base[block];
399         int iface, best, best_val, save, i, cfg;
400
401         if (!pdata || !wm8994->num_retune_mobile_texts)
402                 return;
403
404         switch (block) {
405         case 0:
406         case 1:
407                 iface = 0;
408                 break;
409         case 2:
410                 iface = 1;
411                 break;
412         default:
413                 return;
414         }
415
416         /* Find the version of the currently selected configuration
417          * with the nearest sample rate. */
418         cfg = wm8994->retune_mobile_cfg[block];
419         best = 0;
420         best_val = INT_MAX;
421         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
422                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
423                            wm8994->retune_mobile_texts[cfg]) == 0 &&
424                     abs(pdata->retune_mobile_cfgs[i].rate
425                         - wm8994->dac_rates[iface]) < best_val) {
426                         best = i;
427                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
428                                        - wm8994->dac_rates[iface]);
429                 }
430         }
431
432         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
433                 block,
434                 pdata->retune_mobile_cfgs[best].name,
435                 pdata->retune_mobile_cfgs[best].rate,
436                 wm8994->dac_rates[iface]);
437
438         /* The EQ will be disabled while reconfiguring it, remember the
439          * current configuration.
440          */
441         save = snd_soc_read(codec, base);
442         save &= WM8994_AIF1DAC1_EQ_ENA;
443
444         for (i = 0; i < WM8994_EQ_REGS; i++)
445                 snd_soc_update_bits(codec, base + i, 0xffff,
446                                 pdata->retune_mobile_cfgs[best].regs[i]);
447
448         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
449 }
450
451 /* Icky as hell but saves code duplication */
452 static int wm8994_get_retune_mobile_block(const char *name)
453 {
454         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
455                 return 0;
456         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
457                 return 1;
458         if (strcmp(name, "AIF2 EQ Mode") == 0)
459                 return 2;
460         return -EINVAL;
461 }
462
463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
464                                          struct snd_ctl_elem_value *ucontrol)
465 {
466         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
467         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
468         struct wm8994_pdata *pdata = wm8994->pdata;
469         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470         int value = ucontrol->value.integer.value[0];
471
472         if (block < 0)
473                 return block;
474
475         if (value >= pdata->num_retune_mobile_cfgs)
476                 return -EINVAL;
477
478         wm8994->retune_mobile_cfg[block] = value;
479
480         wm8994_set_retune_mobile(codec, block);
481
482         return 0;
483 }
484
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486                                          struct snd_ctl_elem_value *ucontrol)
487 {
488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
493
494         return 0;
495 }
496
497 static const char *aif_chan_src_text[] = {
498         "Left", "Right"
499 };
500
501 static const struct soc_enum aif1adcl_src =
502         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
503
504 static const struct soc_enum aif1adcr_src =
505         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
506
507 static const struct soc_enum aif2adcl_src =
508         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
509
510 static const struct soc_enum aif2adcr_src =
511         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
512
513 static const struct soc_enum aif1dacl_src =
514         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
515
516 static const struct soc_enum aif1dacr_src =
517         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
518
519 static const struct soc_enum aif2dacl_src =
520         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
521
522 static const struct soc_enum aif2dacr_src =
523         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
524
525 static const char *osr_text[] = {
526         "Low Power", "High Performance",
527 };
528
529 static const struct soc_enum dac_osr =
530         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
531
532 static const struct soc_enum adc_osr =
533         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
534
535 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
538                  1, 119, 0, digital_tlv),
539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
540                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
541                  1, 119, 0, digital_tlv),
542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
543                  WM8994_AIF2_ADC_RIGHT_VOLUME,
544                  1, 119, 0, digital_tlv),
545
546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
550
551 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
552 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
553 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
554 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
555
556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
557                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
559                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
569
570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
573
574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
577
578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
581
582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
583                5, 12, 0, st_tlv),
584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
585                0, 12, 0, st_tlv),
586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
587                5, 12, 0, st_tlv),
588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
589                0, 12, 0, st_tlv),
590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
592
593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
595
596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
598
599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
601
602 SOC_ENUM("ADC OSR", adc_osr),
603 SOC_ENUM("DAC OSR", dac_osr),
604
605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
606                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
608              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
609
610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
611                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
613              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
614
615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
616                6, 1, 1, wm_hubs_spkmix_tlv),
617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
618                2, 1, 1, wm_hubs_spkmix_tlv),
619
620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
621                6, 1, 1, wm_hubs_spkmix_tlv),
622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
623                2, 1, 1, wm_hubs_spkmix_tlv),
624
625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
626                10, 15, 0, wm8994_3d_tlv),
627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
628            8, 1, 0),
629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
630                10, 15, 0, wm8994_3d_tlv),
631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
632            8, 1, 0),
633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
634                10, 15, 0, wm8994_3d_tlv),
635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
636            8, 1, 0),
637 };
638
639 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
641                eq_tlv),
642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
643                eq_tlv),
644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
645                eq_tlv),
646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
647                eq_tlv),
648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
649                eq_tlv),
650
651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
652                eq_tlv),
653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
654                eq_tlv),
655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
656                eq_tlv),
657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
658                eq_tlv),
659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
660                eq_tlv),
661
662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
663                eq_tlv),
664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
665                eq_tlv),
666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
667                eq_tlv),
668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
669                eq_tlv),
670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
671                eq_tlv),
672 };
673
674 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
675 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
676                    WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
677                    WM8994_AIF1ADC1R_DRC_ENA),
678 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
679                    WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
680                    WM8994_AIF1ADC2R_DRC_ENA),
681 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
682                    WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
683                    WM8994_AIF2ADCR_DRC_ENA),
684 };
685
686 static const char *wm8958_ng_text[] = {
687         "30ms", "125ms", "250ms", "500ms",
688 };
689
690 static const struct soc_enum wm8958_aif1dac1_ng_hold =
691         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
692                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
693
694 static const struct soc_enum wm8958_aif1dac2_ng_hold =
695         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
696                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
697
698 static const struct soc_enum wm8958_aif2dac_ng_hold =
699         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
700                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
701
702 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
703 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
704
705 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
706            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
707 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
708 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
709                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
710                7, 1, ng_tlv),
711
712 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
713            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
714 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
715 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
716                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
717                7, 1, ng_tlv),
718
719 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
720            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
721 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
722 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
723                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
724                7, 1, ng_tlv),
725 };
726
727 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
728 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
729                mixin_boost_tlv),
730 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
731                mixin_boost_tlv),
732 };
733
734 /* We run all mode setting through a function to enforce audio mode */
735 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
736 {
737         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
738
739         if (!wm8994->jackdet || !wm8994->jack_cb)
740                 return;
741
742         if (wm8994->active_refcount)
743                 mode = WM1811_JACKDET_MODE_AUDIO;
744
745         if (mode == wm8994->jackdet_mode)
746                 return;
747
748         wm8994->jackdet_mode = mode;
749
750         /* Always use audio mode to detect while the system is active */
751         if (mode != WM1811_JACKDET_MODE_NONE)
752                 mode = WM1811_JACKDET_MODE_AUDIO;
753
754         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
755                             WM1811_JACKDET_MODE_MASK, mode);
756 }
757
758 static void active_reference(struct snd_soc_codec *codec)
759 {
760         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
761
762         mutex_lock(&wm8994->accdet_lock);
763
764         wm8994->active_refcount++;
765
766         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
767                 wm8994->active_refcount);
768
769         /* If we're using jack detection go into audio mode */
770         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
771
772         mutex_unlock(&wm8994->accdet_lock);
773 }
774
775 static void active_dereference(struct snd_soc_codec *codec)
776 {
777         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
778         u16 mode;
779
780         mutex_lock(&wm8994->accdet_lock);
781
782         wm8994->active_refcount--;
783
784         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
785                 wm8994->active_refcount);
786
787         if (wm8994->active_refcount == 0) {
788                 /* Go into appropriate detection only mode */
789                 if (wm8994->jack_mic || wm8994->mic_detecting)
790                         mode = WM1811_JACKDET_MODE_MIC;
791                 else
792                         mode = WM1811_JACKDET_MODE_JACK;
793
794                 wm1811_jackdet_set_mode(codec, mode);
795         }
796
797         mutex_unlock(&wm8994->accdet_lock);
798 }
799
800 static int clk_sys_event(struct snd_soc_dapm_widget *w,
801                          struct snd_kcontrol *kcontrol, int event)
802 {
803         struct snd_soc_codec *codec = w->codec;
804         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
805
806         switch (event) {
807         case SND_SOC_DAPM_PRE_PMU:
808                 return configure_clock(codec);
809
810         case SND_SOC_DAPM_POST_PMU:
811                 /*
812                  * JACKDET won't run until we start the clock and it
813                  * only reports deltas, make sure we notify the state
814                  * up the stack on startup.  Use a *very* generous
815                  * timeout for paranoia, there's no urgency and we
816                  * don't want false reports.
817                  */
818                 if (wm8994->jackdet && !wm8994->clk_has_run) {
819                         schedule_delayed_work(&wm8994->jackdet_bootstrap,
820                                               msecs_to_jiffies(1000));
821                         wm8994->clk_has_run = true;
822                 }
823                 break;
824
825         case SND_SOC_DAPM_POST_PMD:
826                 configure_clock(codec);
827                 break;
828         }
829
830         return 0;
831 }
832
833 static void vmid_reference(struct snd_soc_codec *codec)
834 {
835         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
836
837         pm_runtime_get_sync(codec->dev);
838
839         wm8994->vmid_refcount++;
840
841         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
842                 wm8994->vmid_refcount);
843
844         if (wm8994->vmid_refcount == 1) {
845                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
846                                     WM8994_LINEOUT1_DISCH |
847                                     WM8994_LINEOUT2_DISCH, 0);
848
849                 wm_hubs_vmid_ena(codec);
850
851                 switch (wm8994->vmid_mode) {
852                 default:
853                         WARN_ON(NULL == "Invalid VMID mode");
854                 case WM8994_VMID_NORMAL:
855                         /* Startup bias, VMID ramp & buffer */
856                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
857                                             WM8994_BIAS_SRC |
858                                             WM8994_VMID_DISCH |
859                                             WM8994_STARTUP_BIAS_ENA |
860                                             WM8994_VMID_BUF_ENA |
861                                             WM8994_VMID_RAMP_MASK,
862                                             WM8994_BIAS_SRC |
863                                             WM8994_STARTUP_BIAS_ENA |
864                                             WM8994_VMID_BUF_ENA |
865                                             (0x3 << WM8994_VMID_RAMP_SHIFT));
866
867                         /* Main bias enable, VMID=2x40k */
868                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
869                                             WM8994_BIAS_ENA |
870                                             WM8994_VMID_SEL_MASK,
871                                             WM8994_BIAS_ENA | 0x2);
872
873                         msleep(50);
874
875                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
876                                             WM8994_VMID_RAMP_MASK |
877                                             WM8994_BIAS_SRC,
878                                             0);
879                         break;
880
881                 case WM8994_VMID_FORCE:
882                         /* Startup bias, slow VMID ramp & buffer */
883                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
884                                             WM8994_BIAS_SRC |
885                                             WM8994_VMID_DISCH |
886                                             WM8994_STARTUP_BIAS_ENA |
887                                             WM8994_VMID_BUF_ENA |
888                                             WM8994_VMID_RAMP_MASK,
889                                             WM8994_BIAS_SRC |
890                                             WM8994_STARTUP_BIAS_ENA |
891                                             WM8994_VMID_BUF_ENA |
892                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
893
894                         /* Main bias enable, VMID=2x40k */
895                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
896                                             WM8994_BIAS_ENA |
897                                             WM8994_VMID_SEL_MASK,
898                                             WM8994_BIAS_ENA | 0x2);
899
900                         msleep(400);
901
902                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
903                                             WM8994_VMID_RAMP_MASK |
904                                             WM8994_BIAS_SRC,
905                                             0);
906                         break;
907                 }
908         }
909 }
910
911 static void vmid_dereference(struct snd_soc_codec *codec)
912 {
913         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
914
915         wm8994->vmid_refcount--;
916
917         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
918                 wm8994->vmid_refcount);
919
920         if (wm8994->vmid_refcount == 0) {
921                 if (wm8994->hubs.lineout1_se)
922                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
923                                             WM8994_LINEOUT1N_ENA |
924                                             WM8994_LINEOUT1P_ENA,
925                                             WM8994_LINEOUT1N_ENA |
926                                             WM8994_LINEOUT1P_ENA);
927
928                 if (wm8994->hubs.lineout2_se)
929                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930                                             WM8994_LINEOUT2N_ENA |
931                                             WM8994_LINEOUT2P_ENA,
932                                             WM8994_LINEOUT2N_ENA |
933                                             WM8994_LINEOUT2P_ENA);
934
935                 /* Start discharging VMID */
936                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
937                                     WM8994_BIAS_SRC |
938                                     WM8994_VMID_DISCH,
939                                     WM8994_BIAS_SRC |
940                                     WM8994_VMID_DISCH);
941
942                 switch (wm8994->vmid_mode) {
943                 case WM8994_VMID_FORCE:
944                         msleep(350);
945                         break;
946                 default:
947                         break;
948                 }
949
950                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
951                                     WM8994_VROI, WM8994_VROI);
952
953                 /* Active discharge */
954                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
955                                     WM8994_LINEOUT1_DISCH |
956                                     WM8994_LINEOUT2_DISCH,
957                                     WM8994_LINEOUT1_DISCH |
958                                     WM8994_LINEOUT2_DISCH);
959
960                 msleep(150);
961
962                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
963                                     WM8994_LINEOUT1N_ENA |
964                                     WM8994_LINEOUT1P_ENA |
965                                     WM8994_LINEOUT2N_ENA |
966                                     WM8994_LINEOUT2P_ENA, 0);
967
968                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
969                                     WM8994_VROI, 0);
970
971                 /* Switch off startup biases */
972                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
973                                     WM8994_BIAS_SRC |
974                                     WM8994_STARTUP_BIAS_ENA |
975                                     WM8994_VMID_BUF_ENA |
976                                     WM8994_VMID_RAMP_MASK, 0);
977
978                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
979                                     WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
980
981                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
982                                     WM8994_VMID_RAMP_MASK, 0);
983         }
984
985         pm_runtime_put(codec->dev);
986 }
987
988 static int vmid_event(struct snd_soc_dapm_widget *w,
989                       struct snd_kcontrol *kcontrol, int event)
990 {
991         struct snd_soc_codec *codec = w->codec;
992
993         switch (event) {
994         case SND_SOC_DAPM_PRE_PMU:
995                 vmid_reference(codec);
996                 break;
997
998         case SND_SOC_DAPM_POST_PMD:
999                 vmid_dereference(codec);
1000                 break;
1001         }
1002
1003         return 0;
1004 }
1005
1006 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
1007 {
1008         int source = 0;  /* GCC flow analysis can't track enable */
1009         int reg, reg_r;
1010
1011         /* We also need the same AIF source for L/R and only one path */
1012         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1013         switch (reg) {
1014         case WM8994_AIF2DACL_TO_DAC1L:
1015                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1016                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1017                 break;
1018         case WM8994_AIF1DAC2L_TO_DAC1L:
1019                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1020                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1021                 break;
1022         case WM8994_AIF1DAC1L_TO_DAC1L:
1023                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1024                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1025                 break;
1026         default:
1027                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1028                 return false;
1029         }
1030
1031         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1032         if (reg_r != reg) {
1033                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1034                 return false;
1035         }
1036
1037         /* Set the source up */
1038         snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1039                             WM8994_CP_DYN_SRC_SEL_MASK, source);
1040
1041         return true;
1042 }
1043
1044 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1045                       struct snd_kcontrol *kcontrol, int event)
1046 {
1047         struct snd_soc_codec *codec = w->codec;
1048         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1049         struct wm8994 *control = codec->control_data;
1050         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1051         int i;
1052         int dac;
1053         int adc;
1054         int val;
1055
1056         switch (control->type) {
1057         case WM8994:
1058         case WM8958:
1059                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1060                 break;
1061         default:
1062                 break;
1063         }
1064
1065         switch (event) {
1066         case SND_SOC_DAPM_PRE_PMU:
1067                 /* Don't enable timeslot 2 if not in use */
1068                 if (wm8994->channels[0] <= 2)
1069                         mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1070
1071                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1072                 if ((val & WM8994_AIF1ADCL_SRC) &&
1073                     (val & WM8994_AIF1ADCR_SRC))
1074                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1075                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1076                          !(val & WM8994_AIF1ADCR_SRC))
1077                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1078                 else
1079                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1080                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1081
1082                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1083                 if ((val & WM8994_AIF1DACL_SRC) &&
1084                     (val & WM8994_AIF1DACR_SRC))
1085                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1086                 else if (!(val & WM8994_AIF1DACL_SRC) &&
1087                          !(val & WM8994_AIF1DACR_SRC))
1088                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1089                 else
1090                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1091                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1092
1093                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1094                                     mask, adc);
1095                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1096                                     mask, dac);
1097                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1098                                     WM8994_AIF1DSPCLK_ENA |
1099                                     WM8994_SYSDSPCLK_ENA,
1100                                     WM8994_AIF1DSPCLK_ENA |
1101                                     WM8994_SYSDSPCLK_ENA);
1102                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1103                                     WM8994_AIF1ADC1R_ENA |
1104                                     WM8994_AIF1ADC1L_ENA |
1105                                     WM8994_AIF1ADC2R_ENA |
1106                                     WM8994_AIF1ADC2L_ENA);
1107                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1108                                     WM8994_AIF1DAC1R_ENA |
1109                                     WM8994_AIF1DAC1L_ENA |
1110                                     WM8994_AIF1DAC2R_ENA |
1111                                     WM8994_AIF1DAC2L_ENA);
1112                 break;
1113
1114         case SND_SOC_DAPM_POST_PMU:
1115                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1116                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1117                                       snd_soc_read(codec,
1118                                                    wm8994_vu_bits[i].reg));
1119                 break;
1120
1121         case SND_SOC_DAPM_PRE_PMD:
1122         case SND_SOC_DAPM_POST_PMD:
1123                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1124                                     mask, 0);
1125                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1126                                     mask, 0);
1127
1128                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1129                 if (val & WM8994_AIF2DSPCLK_ENA)
1130                         val = WM8994_SYSDSPCLK_ENA;
1131                 else
1132                         val = 0;
1133                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1134                                     WM8994_SYSDSPCLK_ENA |
1135                                     WM8994_AIF1DSPCLK_ENA, val);
1136                 break;
1137         }
1138
1139         return 0;
1140 }
1141
1142 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1143                       struct snd_kcontrol *kcontrol, int event)
1144 {
1145         struct snd_soc_codec *codec = w->codec;
1146         int i;
1147         int dac;
1148         int adc;
1149         int val;
1150
1151         switch (event) {
1152         case SND_SOC_DAPM_PRE_PMU:
1153                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1154                 if ((val & WM8994_AIF2ADCL_SRC) &&
1155                     (val & WM8994_AIF2ADCR_SRC))
1156                         adc = WM8994_AIF2ADCR_ENA;
1157                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1158                          !(val & WM8994_AIF2ADCR_SRC))
1159                         adc = WM8994_AIF2ADCL_ENA;
1160                 else
1161                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1162
1163
1164                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1165                 if ((val & WM8994_AIF2DACL_SRC) &&
1166                     (val & WM8994_AIF2DACR_SRC))
1167                         dac = WM8994_AIF2DACR_ENA;
1168                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1169                          !(val & WM8994_AIF2DACR_SRC))
1170                         dac = WM8994_AIF2DACL_ENA;
1171                 else
1172                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1173
1174                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1175                                     WM8994_AIF2ADCL_ENA |
1176                                     WM8994_AIF2ADCR_ENA, adc);
1177                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1178                                     WM8994_AIF2DACL_ENA |
1179                                     WM8994_AIF2DACR_ENA, dac);
1180                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1181                                     WM8994_AIF2DSPCLK_ENA |
1182                                     WM8994_SYSDSPCLK_ENA,
1183                                     WM8994_AIF2DSPCLK_ENA |
1184                                     WM8994_SYSDSPCLK_ENA);
1185                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1186                                     WM8994_AIF2ADCL_ENA |
1187                                     WM8994_AIF2ADCR_ENA,
1188                                     WM8994_AIF2ADCL_ENA |
1189                                     WM8994_AIF2ADCR_ENA);
1190                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1191                                     WM8994_AIF2DACL_ENA |
1192                                     WM8994_AIF2DACR_ENA,
1193                                     WM8994_AIF2DACL_ENA |
1194                                     WM8994_AIF2DACR_ENA);
1195                 break;
1196
1197         case SND_SOC_DAPM_POST_PMU:
1198                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1199                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1200                                       snd_soc_read(codec,
1201                                                    wm8994_vu_bits[i].reg));
1202                 break;
1203
1204         case SND_SOC_DAPM_PRE_PMD:
1205         case SND_SOC_DAPM_POST_PMD:
1206                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1207                                     WM8994_AIF2DACL_ENA |
1208                                     WM8994_AIF2DACR_ENA, 0);
1209                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1210                                     WM8994_AIF2ADCL_ENA |
1211                                     WM8994_AIF2ADCR_ENA, 0);
1212
1213                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1214                 if (val & WM8994_AIF1DSPCLK_ENA)
1215                         val = WM8994_SYSDSPCLK_ENA;
1216                 else
1217                         val = 0;
1218                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1219                                     WM8994_SYSDSPCLK_ENA |
1220                                     WM8994_AIF2DSPCLK_ENA, val);
1221                 break;
1222         }
1223
1224         return 0;
1225 }
1226
1227 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1228                            struct snd_kcontrol *kcontrol, int event)
1229 {
1230         struct snd_soc_codec *codec = w->codec;
1231         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1232
1233         switch (event) {
1234         case SND_SOC_DAPM_PRE_PMU:
1235                 wm8994->aif1clk_enable = 1;
1236                 break;
1237         case SND_SOC_DAPM_POST_PMD:
1238                 wm8994->aif1clk_disable = 1;
1239                 break;
1240         }
1241
1242         return 0;
1243 }
1244
1245 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1246                            struct snd_kcontrol *kcontrol, int event)
1247 {
1248         struct snd_soc_codec *codec = w->codec;
1249         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1250
1251         switch (event) {
1252         case SND_SOC_DAPM_PRE_PMU:
1253                 wm8994->aif2clk_enable = 1;
1254                 break;
1255         case SND_SOC_DAPM_POST_PMD:
1256                 wm8994->aif2clk_disable = 1;
1257                 break;
1258         }
1259
1260         return 0;
1261 }
1262
1263 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1264                           struct snd_kcontrol *kcontrol, int event)
1265 {
1266         struct snd_soc_codec *codec = w->codec;
1267         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1268
1269         switch (event) {
1270         case SND_SOC_DAPM_PRE_PMU:
1271                 if (wm8994->aif1clk_enable) {
1272                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1273                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1274                                             WM8994_AIF1CLK_ENA_MASK,
1275                                             WM8994_AIF1CLK_ENA);
1276                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1277                         wm8994->aif1clk_enable = 0;
1278                 }
1279                 if (wm8994->aif2clk_enable) {
1280                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1281                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1282                                             WM8994_AIF2CLK_ENA_MASK,
1283                                             WM8994_AIF2CLK_ENA);
1284                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1285                         wm8994->aif2clk_enable = 0;
1286                 }
1287                 break;
1288         }
1289
1290         /* We may also have postponed startup of DSP, handle that. */
1291         wm8958_aif_ev(w, kcontrol, event);
1292
1293         return 0;
1294 }
1295
1296 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1297                            struct snd_kcontrol *kcontrol, int event)
1298 {
1299         struct snd_soc_codec *codec = w->codec;
1300         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1301
1302         switch (event) {
1303         case SND_SOC_DAPM_POST_PMD:
1304                 if (wm8994->aif1clk_disable) {
1305                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1306                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1307                                             WM8994_AIF1CLK_ENA_MASK, 0);
1308                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1309                         wm8994->aif1clk_disable = 0;
1310                 }
1311                 if (wm8994->aif2clk_disable) {
1312                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1313                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1314                                             WM8994_AIF2CLK_ENA_MASK, 0);
1315                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1316                         wm8994->aif2clk_disable = 0;
1317                 }
1318                 break;
1319         }
1320
1321         return 0;
1322 }
1323
1324 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1325                       struct snd_kcontrol *kcontrol, int event)
1326 {
1327         late_enable_ev(w, kcontrol, event);
1328         return 0;
1329 }
1330
1331 static int micbias_ev(struct snd_soc_dapm_widget *w,
1332                       struct snd_kcontrol *kcontrol, int event)
1333 {
1334         late_enable_ev(w, kcontrol, event);
1335         return 0;
1336 }
1337
1338 static int dac_ev(struct snd_soc_dapm_widget *w,
1339                   struct snd_kcontrol *kcontrol, int event)
1340 {
1341         struct snd_soc_codec *codec = w->codec;
1342         unsigned int mask = 1 << w->shift;
1343
1344         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1345                             mask, mask);
1346         return 0;
1347 }
1348
1349 static const char *adc_mux_text[] = {
1350         "ADC",
1351         "DMIC",
1352 };
1353
1354 static const struct soc_enum adc_enum =
1355         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1356
1357 static const struct snd_kcontrol_new adcl_mux =
1358         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1359
1360 static const struct snd_kcontrol_new adcr_mux =
1361         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1362
1363 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1364 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1365 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1366 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1367 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1368 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1369 };
1370
1371 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1372 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1373 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1374 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1375 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1376 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1377 };
1378
1379 /* Debugging; dump chip status after DAPM transitions */
1380 static int post_ev(struct snd_soc_dapm_widget *w,
1381             struct snd_kcontrol *kcontrol, int event)
1382 {
1383         struct snd_soc_codec *codec = w->codec;
1384         dev_dbg(codec->dev, "SRC status: %x\n",
1385                 snd_soc_read(codec,
1386                              WM8994_RATE_STATUS));
1387         return 0;
1388 }
1389
1390 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1391 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1392                 1, 1, 0),
1393 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1394                 0, 1, 0),
1395 };
1396
1397 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1398 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1399                 1, 1, 0),
1400 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1401                 0, 1, 0),
1402 };
1403
1404 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1405 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1406                 1, 1, 0),
1407 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1408                 0, 1, 0),
1409 };
1410
1411 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1412 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1413                 1, 1, 0),
1414 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1415                 0, 1, 0),
1416 };
1417
1418 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1419 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1420                 5, 1, 0),
1421 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1422                 4, 1, 0),
1423 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1424                 2, 1, 0),
1425 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1426                 1, 1, 0),
1427 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1428                 0, 1, 0),
1429 };
1430
1431 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1432 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1433                 5, 1, 0),
1434 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1435                 4, 1, 0),
1436 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1437                 2, 1, 0),
1438 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1439                 1, 1, 0),
1440 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1441                 0, 1, 0),
1442 };
1443
1444 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1445 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1446         .info = snd_soc_info_volsw, \
1447         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1448         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1449
1450 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1451                               struct snd_ctl_elem_value *ucontrol)
1452 {
1453         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1454         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1455         struct snd_soc_codec *codec = w->codec;
1456         int ret;
1457
1458         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1459
1460         wm_hubs_update_class_w(codec);
1461
1462         return ret;
1463 }
1464
1465 static const struct snd_kcontrol_new dac1l_mix[] = {
1466 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1467                       5, 1, 0),
1468 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1469                       4, 1, 0),
1470 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1471                       2, 1, 0),
1472 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1473                       1, 1, 0),
1474 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1475                       0, 1, 0),
1476 };
1477
1478 static const struct snd_kcontrol_new dac1r_mix[] = {
1479 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1480                       5, 1, 0),
1481 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1482                       4, 1, 0),
1483 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1484                       2, 1, 0),
1485 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1486                       1, 1, 0),
1487 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1488                       0, 1, 0),
1489 };
1490
1491 static const char *sidetone_text[] = {
1492         "ADC/DMIC1", "DMIC2",
1493 };
1494
1495 static const struct soc_enum sidetone1_enum =
1496         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1497
1498 static const struct snd_kcontrol_new sidetone1_mux =
1499         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1500
1501 static const struct soc_enum sidetone2_enum =
1502         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1503
1504 static const struct snd_kcontrol_new sidetone2_mux =
1505         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1506
1507 static const char *aif1dac_text[] = {
1508         "AIF1DACDAT", "AIF3DACDAT",
1509 };
1510
1511 static const struct soc_enum aif1dac_enum =
1512         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1513
1514 static const struct snd_kcontrol_new aif1dac_mux =
1515         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1516
1517 static const char *aif2dac_text[] = {
1518         "AIF2DACDAT", "AIF3DACDAT",
1519 };
1520
1521 static const struct soc_enum aif2dac_enum =
1522         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1523
1524 static const struct snd_kcontrol_new aif2dac_mux =
1525         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1526
1527 static const char *aif2adc_text[] = {
1528         "AIF2ADCDAT", "AIF3DACDAT",
1529 };
1530
1531 static const struct soc_enum aif2adc_enum =
1532         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1533
1534 static const struct snd_kcontrol_new aif2adc_mux =
1535         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1536
1537 static const char *aif3adc_text[] = {
1538         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1539 };
1540
1541 static const struct soc_enum wm8994_aif3adc_enum =
1542         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1543
1544 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1545         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1546
1547 static const struct soc_enum wm8958_aif3adc_enum =
1548         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1549
1550 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1551         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1552
1553 static const char *mono_pcm_out_text[] = {
1554         "None", "AIF2ADCL", "AIF2ADCR",
1555 };
1556
1557 static const struct soc_enum mono_pcm_out_enum =
1558         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1559
1560 static const struct snd_kcontrol_new mono_pcm_out_mux =
1561         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1562
1563 static const char *aif2dac_src_text[] = {
1564         "AIF2", "AIF3",
1565 };
1566
1567 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1568 static const struct soc_enum aif2dacl_src_enum =
1569         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1570
1571 static const struct snd_kcontrol_new aif2dacl_src_mux =
1572         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1573
1574 static const struct soc_enum aif2dacr_src_enum =
1575         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1576
1577 static const struct snd_kcontrol_new aif2dacr_src_mux =
1578         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1579
1580 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1581 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1582         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1583 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1584         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1585
1586 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1587         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1588 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1589         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1590 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1591         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1592 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1593         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1594 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1595         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1596
1597 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1598                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1599                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1600 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1601                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1602                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1603 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1604                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1605 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1606                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1607
1608 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1609 };
1610
1611 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1612 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1613                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1614                     SND_SOC_DAPM_PRE_PMD),
1615 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1616                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1617                     SND_SOC_DAPM_PRE_PMD),
1618 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1619 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1620                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1621 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1622                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1623 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1624 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1625 };
1626
1627 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1628 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1629         dac_ev, SND_SOC_DAPM_PRE_PMU),
1630 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1631         dac_ev, SND_SOC_DAPM_PRE_PMU),
1632 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1633         dac_ev, SND_SOC_DAPM_PRE_PMU),
1634 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1635         dac_ev, SND_SOC_DAPM_PRE_PMU),
1636 };
1637
1638 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1639 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1640 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1641 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1642 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1643 };
1644
1645 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1646 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1647                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1648 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1649                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1650 };
1651
1652 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1653 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1654 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1655 };
1656
1657 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1658 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1659 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1660 SND_SOC_DAPM_INPUT("Clock"),
1661
1662 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1663                       SND_SOC_DAPM_PRE_PMU),
1664 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1665                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1666
1667 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1668                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1669                     SND_SOC_DAPM_PRE_PMD),
1670
1671 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1672 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1673 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1674
1675 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1676                      0, SND_SOC_NOPM, 9, 0),
1677 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1678                      0, SND_SOC_NOPM, 8, 0),
1679 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1680                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1681                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1682 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1683                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1684                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1685
1686 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1687                      0, SND_SOC_NOPM, 11, 0),
1688 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1689                      0, SND_SOC_NOPM, 10, 0),
1690 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1691                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1692                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1693 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1694                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1695                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1696
1697 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1698                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1699 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1700                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1701
1702 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1703                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1704 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1705                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1706
1707 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1708                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1709 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1710                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1711
1712 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1713 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1714
1715 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1716                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1717 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1718                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1719
1720 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1721                      SND_SOC_NOPM, 13, 0),
1722 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1723                      SND_SOC_NOPM, 12, 0),
1724 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1725                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1726                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1727 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1728                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1729                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1730
1731 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1732 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1733 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1734 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1735
1736 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1737 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1738 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1739
1740 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1742
1743 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1744
1745 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1746 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1747 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1748 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1749
1750 /* Power is done with the muxes since the ADC power also controls the
1751  * downsampling chain, the chip will automatically manage the analogue
1752  * specific portions.
1753  */
1754 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1755 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1756
1757 SND_SOC_DAPM_POST("Debug log", post_ev),
1758 };
1759
1760 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1761 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1762 };
1763
1764 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1765 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1766 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1767 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1768 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1769 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1770 };
1771
1772 static const struct snd_soc_dapm_route intercon[] = {
1773         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1774         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1775
1776         { "DSP1CLK", NULL, "CLK_SYS" },
1777         { "DSP2CLK", NULL, "CLK_SYS" },
1778         { "DSPINTCLK", NULL, "CLK_SYS" },
1779
1780         { "AIF1ADC1L", NULL, "AIF1CLK" },
1781         { "AIF1ADC1L", NULL, "DSP1CLK" },
1782         { "AIF1ADC1R", NULL, "AIF1CLK" },
1783         { "AIF1ADC1R", NULL, "DSP1CLK" },
1784         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1785
1786         { "AIF1DAC1L", NULL, "AIF1CLK" },
1787         { "AIF1DAC1L", NULL, "DSP1CLK" },
1788         { "AIF1DAC1R", NULL, "AIF1CLK" },
1789         { "AIF1DAC1R", NULL, "DSP1CLK" },
1790         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1791
1792         { "AIF1ADC2L", NULL, "AIF1CLK" },
1793         { "AIF1ADC2L", NULL, "DSP1CLK" },
1794         { "AIF1ADC2R", NULL, "AIF1CLK" },
1795         { "AIF1ADC2R", NULL, "DSP1CLK" },
1796         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1797
1798         { "AIF1DAC2L", NULL, "AIF1CLK" },
1799         { "AIF1DAC2L", NULL, "DSP1CLK" },
1800         { "AIF1DAC2R", NULL, "AIF1CLK" },
1801         { "AIF1DAC2R", NULL, "DSP1CLK" },
1802         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1803
1804         { "AIF2ADCL", NULL, "AIF2CLK" },
1805         { "AIF2ADCL", NULL, "DSP2CLK" },
1806         { "AIF2ADCR", NULL, "AIF2CLK" },
1807         { "AIF2ADCR", NULL, "DSP2CLK" },
1808         { "AIF2ADCR", NULL, "DSPINTCLK" },
1809
1810         { "AIF2DACL", NULL, "AIF2CLK" },
1811         { "AIF2DACL", NULL, "DSP2CLK" },
1812         { "AIF2DACR", NULL, "AIF2CLK" },
1813         { "AIF2DACR", NULL, "DSP2CLK" },
1814         { "AIF2DACR", NULL, "DSPINTCLK" },
1815
1816         { "DMIC1L", NULL, "DMIC1DAT" },
1817         { "DMIC1L", NULL, "CLK_SYS" },
1818         { "DMIC1R", NULL, "DMIC1DAT" },
1819         { "DMIC1R", NULL, "CLK_SYS" },
1820         { "DMIC2L", NULL, "DMIC2DAT" },
1821         { "DMIC2L", NULL, "CLK_SYS" },
1822         { "DMIC2R", NULL, "DMIC2DAT" },
1823         { "DMIC2R", NULL, "CLK_SYS" },
1824
1825         { "ADCL", NULL, "AIF1CLK" },
1826         { "ADCL", NULL, "DSP1CLK" },
1827         { "ADCL", NULL, "DSPINTCLK" },
1828
1829         { "ADCR", NULL, "AIF1CLK" },
1830         { "ADCR", NULL, "DSP1CLK" },
1831         { "ADCR", NULL, "DSPINTCLK" },
1832
1833         { "ADCL Mux", "ADC", "ADCL" },
1834         { "ADCL Mux", "DMIC", "DMIC1L" },
1835         { "ADCR Mux", "ADC", "ADCR" },
1836         { "ADCR Mux", "DMIC", "DMIC1R" },
1837
1838         { "DAC1L", NULL, "AIF1CLK" },
1839         { "DAC1L", NULL, "DSP1CLK" },
1840         { "DAC1L", NULL, "DSPINTCLK" },
1841
1842         { "DAC1R", NULL, "AIF1CLK" },
1843         { "DAC1R", NULL, "DSP1CLK" },
1844         { "DAC1R", NULL, "DSPINTCLK" },
1845
1846         { "DAC2L", NULL, "AIF2CLK" },
1847         { "DAC2L", NULL, "DSP2CLK" },
1848         { "DAC2L", NULL, "DSPINTCLK" },
1849
1850         { "DAC2R", NULL, "AIF2DACR" },
1851         { "DAC2R", NULL, "AIF2CLK" },
1852         { "DAC2R", NULL, "DSP2CLK" },
1853         { "DAC2R", NULL, "DSPINTCLK" },
1854
1855         { "TOCLK", NULL, "CLK_SYS" },
1856
1857         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1858         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1859         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1860
1861         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1862         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1863         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1864
1865         /* AIF1 outputs */
1866         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1867         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1868         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1869
1870         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1871         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1872         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1873
1874         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1875         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1876         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1877
1878         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1879         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1880         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1881
1882         /* Pin level routing for AIF3 */
1883         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1884         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1885         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1886         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1887
1888         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1889         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1890         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1891         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1892         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1893         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1894         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1895
1896         /* DAC1 inputs */
1897         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1898         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1899         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1900         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1901         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1902
1903         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1904         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1905         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1906         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1907         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1908
1909         /* DAC2/AIF2 outputs  */
1910         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1911         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1912         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1913         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1914         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1915         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1916
1917         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1918         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1919         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1920         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1921         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1922         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1923
1924         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1925         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1926         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1927         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1928
1929         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1930
1931         /* AIF3 output */
1932         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1933         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1934         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1935         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1936         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1937         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1938         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1939         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1940
1941         /* Sidetone */
1942         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1943         { "Left Sidetone", "DMIC2", "DMIC2L" },
1944         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1945         { "Right Sidetone", "DMIC2", "DMIC2R" },
1946
1947         /* Output stages */
1948         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1949         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1950
1951         { "SPKL", "DAC1 Switch", "DAC1L" },
1952         { "SPKL", "DAC2 Switch", "DAC2L" },
1953
1954         { "SPKR", "DAC1 Switch", "DAC1R" },
1955         { "SPKR", "DAC2 Switch", "DAC2R" },
1956
1957         { "Left Headphone Mux", "DAC", "DAC1L" },
1958         { "Right Headphone Mux", "DAC", "DAC1R" },
1959 };
1960
1961 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1962         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1963         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1964         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1965         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1966         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1967         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1968         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1969         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1970 };
1971
1972 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1973         { "DAC1L", NULL, "DAC1L Mixer" },
1974         { "DAC1R", NULL, "DAC1R Mixer" },
1975         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1976         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1977 };
1978
1979 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1980         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1981         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1982         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1983         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1984         { "MICBIAS1", NULL, "CLK_SYS" },
1985         { "MICBIAS1", NULL, "MICBIAS Supply" },
1986         { "MICBIAS2", NULL, "CLK_SYS" },
1987         { "MICBIAS2", NULL, "MICBIAS Supply" },
1988 };
1989
1990 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1991         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1992         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1993         { "MICBIAS1", NULL, "VMID" },
1994         { "MICBIAS2", NULL, "VMID" },
1995 };
1996
1997 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1998         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1999         { "AIF2DACR", NULL, "AIF2DACR Mux" },
2000
2001         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2002         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2003         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2004         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2005
2006         { "AIF3DACDAT", NULL, "AIF3" },
2007         { "AIF3ADCDAT", NULL, "AIF3" },
2008
2009         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2010         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2011
2012         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2013 };
2014
2015 /* The size in bits of the FLL divide multiplied by 10
2016  * to allow rounding later */
2017 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2018
2019 struct fll_div {
2020         u16 outdiv;
2021         u16 n;
2022         u16 k;
2023         u16 clk_ref_div;
2024         u16 fll_fratio;
2025 };
2026
2027 static int wm8994_get_fll_config(struct fll_div *fll,
2028                                  int freq_in, int freq_out)
2029 {
2030         u64 Kpart;
2031         unsigned int K, Ndiv, Nmod;
2032
2033         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2034
2035         /* Scale the input frequency down to <= 13.5MHz */
2036         fll->clk_ref_div = 0;
2037         while (freq_in > 13500000) {
2038                 fll->clk_ref_div++;
2039                 freq_in /= 2;
2040
2041                 if (fll->clk_ref_div > 3)
2042                         return -EINVAL;
2043         }
2044         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2045
2046         /* Scale the output to give 90MHz<=Fvco<=100MHz */
2047         fll->outdiv = 3;
2048         while (freq_out * (fll->outdiv + 1) < 90000000) {
2049                 fll->outdiv++;
2050                 if (fll->outdiv > 63)
2051                         return -EINVAL;
2052         }
2053         freq_out *= fll->outdiv + 1;
2054         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2055
2056         if (freq_in > 1000000) {
2057                 fll->fll_fratio = 0;
2058         } else if (freq_in > 256000) {
2059                 fll->fll_fratio = 1;
2060                 freq_in *= 2;
2061         } else if (freq_in > 128000) {
2062                 fll->fll_fratio = 2;
2063                 freq_in *= 4;
2064         } else if (freq_in > 64000) {
2065                 fll->fll_fratio = 3;
2066                 freq_in *= 8;
2067         } else {
2068                 fll->fll_fratio = 4;
2069                 freq_in *= 16;
2070         }
2071         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2072
2073         /* Now, calculate N.K */
2074         Ndiv = freq_out / freq_in;
2075
2076         fll->n = Ndiv;
2077         Nmod = freq_out % freq_in;
2078         pr_debug("Nmod=%d\n", Nmod);
2079
2080         /* Calculate fractional part - scale up so we can round. */
2081         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2082
2083         do_div(Kpart, freq_in);
2084
2085         K = Kpart & 0xFFFFFFFF;
2086
2087         if ((K % 10) >= 5)
2088                 K += 5;
2089
2090         /* Move down to proper range now rounding is done */
2091         fll->k = K / 10;
2092
2093         pr_debug("N=%x K=%x\n", fll->n, fll->k);
2094
2095         return 0;
2096 }
2097
2098 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2099                           unsigned int freq_in, unsigned int freq_out)
2100 {
2101         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2102         struct wm8994 *control = wm8994->wm8994;
2103         int reg_offset, ret;
2104         struct fll_div fll;
2105         u16 reg, clk1, aif_reg, aif_src;
2106         unsigned long timeout;
2107         bool was_enabled;
2108
2109         switch (id) {
2110         case WM8994_FLL1:
2111                 reg_offset = 0;
2112                 id = 0;
2113                 aif_src = 0x10;
2114                 break;
2115         case WM8994_FLL2:
2116                 reg_offset = 0x20;
2117                 id = 1;
2118                 aif_src = 0x18;
2119                 break;
2120         default:
2121                 return -EINVAL;
2122         }
2123
2124         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2125         was_enabled = reg & WM8994_FLL1_ENA;
2126
2127         switch (src) {
2128         case 0:
2129                 /* Allow no source specification when stopping */
2130                 if (freq_out)
2131                         return -EINVAL;
2132                 src = wm8994->fll[id].src;
2133                 break;
2134         case WM8994_FLL_SRC_MCLK1:
2135         case WM8994_FLL_SRC_MCLK2:
2136         case WM8994_FLL_SRC_LRCLK:
2137         case WM8994_FLL_SRC_BCLK:
2138                 break;
2139         case WM8994_FLL_SRC_INTERNAL:
2140                 freq_in = 12000000;
2141                 freq_out = 12000000;
2142                 break;
2143         default:
2144                 return -EINVAL;
2145         }
2146
2147         /* Are we changing anything? */
2148         if (wm8994->fll[id].src == src &&
2149             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2150                 return 0;
2151
2152         /* If we're stopping the FLL redo the old config - no
2153          * registers will actually be written but we avoid GCC flow
2154          * analysis bugs spewing warnings.
2155          */
2156         if (freq_out)
2157                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2158         else
2159                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2160                                             wm8994->fll[id].out);
2161         if (ret < 0)
2162                 return ret;
2163
2164         /* Make sure that we're not providing SYSCLK right now */
2165         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2166         if (clk1 & WM8994_SYSCLK_SRC)
2167                 aif_reg = WM8994_AIF2_CLOCKING_1;
2168         else
2169                 aif_reg = WM8994_AIF1_CLOCKING_1;
2170         reg = snd_soc_read(codec, aif_reg);
2171
2172         if ((reg & WM8994_AIF1CLK_ENA) &&
2173             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2174                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2175                         id + 1);
2176                 return -EBUSY;
2177         }
2178
2179         /* We always need to disable the FLL while reconfiguring */
2180         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2181                             WM8994_FLL1_ENA, 0);
2182
2183         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2184             freq_in == freq_out && freq_out) {
2185                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2186                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2187                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2188                 goto out;
2189         }
2190
2191         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2192                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2193         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2194                             WM8994_FLL1_OUTDIV_MASK |
2195                             WM8994_FLL1_FRATIO_MASK, reg);
2196
2197         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2198                             WM8994_FLL1_K_MASK, fll.k);
2199
2200         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2201                             WM8994_FLL1_N_MASK,
2202                             fll.n << WM8994_FLL1_N_SHIFT);
2203
2204         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2205                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2206                             WM8994_FLL1_REFCLK_DIV_MASK |
2207                             WM8994_FLL1_REFCLK_SRC_MASK,
2208                             ((src == WM8994_FLL_SRC_INTERNAL)
2209                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2210                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2211                             (src - 1));
2212
2213         /* Clear any pending completion from a previous failure */
2214         try_wait_for_completion(&wm8994->fll_locked[id]);
2215
2216         /* Enable (with fractional mode if required) */
2217         if (freq_out) {
2218                 /* Enable VMID if we need it */
2219                 if (!was_enabled) {
2220                         active_reference(codec);
2221
2222                         switch (control->type) {
2223                         case WM8994:
2224                                 vmid_reference(codec);
2225                                 break;
2226                         case WM8958:
2227                                 if (wm8994->revision < 1)
2228                                         vmid_reference(codec);
2229                                 break;
2230                         default:
2231                                 break;
2232                         }
2233                 }
2234
2235                 reg = WM8994_FLL1_ENA;
2236
2237                 if (fll.k)
2238                         reg |= WM8994_FLL1_FRAC;
2239                 if (src == WM8994_FLL_SRC_INTERNAL)
2240                         reg |= WM8994_FLL1_OSC_ENA;
2241
2242                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2243                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2244                                     WM8994_FLL1_FRAC, reg);
2245
2246                 if (wm8994->fll_locked_irq) {
2247                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2248                                                               msecs_to_jiffies(10));
2249                         if (timeout == 0)
2250                                 dev_warn(codec->dev,
2251                                          "Timed out waiting for FLL lock\n");
2252                 } else {
2253                         msleep(5);
2254                 }
2255         } else {
2256                 if (was_enabled) {
2257                         switch (control->type) {
2258                         case WM8994:
2259                                 vmid_dereference(codec);
2260                                 break;
2261                         case WM8958:
2262                                 if (wm8994->revision < 1)
2263                                         vmid_dereference(codec);
2264                                 break;
2265                         default:
2266                                 break;
2267                         }
2268
2269                         active_dereference(codec);
2270                 }
2271         }
2272
2273 out:
2274         wm8994->fll[id].in = freq_in;
2275         wm8994->fll[id].out = freq_out;
2276         wm8994->fll[id].src = src;
2277
2278         configure_clock(codec);
2279
2280         return 0;
2281 }
2282
2283 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2284 {
2285         struct completion *completion = data;
2286
2287         complete(completion);
2288
2289         return IRQ_HANDLED;
2290 }
2291
2292 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2293
2294 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2295                           unsigned int freq_in, unsigned int freq_out)
2296 {
2297         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2298 }
2299
2300 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2301                 int clk_id, unsigned int freq, int dir)
2302 {
2303         struct snd_soc_codec *codec = dai->codec;
2304         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2305         int i;
2306
2307         switch (dai->id) {
2308         case 1:
2309         case 2:
2310                 break;
2311
2312         default:
2313                 /* AIF3 shares clocking with AIF1/2 */
2314                 return -EINVAL;
2315         }
2316
2317         switch (clk_id) {
2318         case WM8994_SYSCLK_MCLK1:
2319                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2320                 wm8994->mclk[0] = freq;
2321                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2322                         dai->id, freq);
2323                 break;
2324
2325         case WM8994_SYSCLK_MCLK2:
2326                 /* TODO: Set GPIO AF */
2327                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2328                 wm8994->mclk[1] = freq;
2329                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2330                         dai->id, freq);
2331                 break;
2332
2333         case WM8994_SYSCLK_FLL1:
2334                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2335                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2336                 break;
2337
2338         case WM8994_SYSCLK_FLL2:
2339                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2340                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2341                 break;
2342
2343         case WM8994_SYSCLK_OPCLK:
2344                 /* Special case - a division (times 10) is given and
2345                  * no effect on main clocking.
2346                  */
2347                 if (freq) {
2348                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2349                                 if (opclk_divs[i] == freq)
2350                                         break;
2351                         if (i == ARRAY_SIZE(opclk_divs))
2352                                 return -EINVAL;
2353                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2354                                             WM8994_OPCLK_DIV_MASK, i);
2355                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2356                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2357                 } else {
2358                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2359                                             WM8994_OPCLK_ENA, 0);
2360                 }
2361
2362         default:
2363                 return -EINVAL;
2364         }
2365
2366         configure_clock(codec);
2367
2368         return 0;
2369 }
2370
2371 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2372                                  enum snd_soc_bias_level level)
2373 {
2374         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2375         struct wm8994 *control = wm8994->wm8994;
2376
2377         wm_hubs_set_bias_level(codec, level);
2378
2379         switch (level) {
2380         case SND_SOC_BIAS_ON:
2381                 break;
2382
2383         case SND_SOC_BIAS_PREPARE:
2384                 /* MICBIAS into regulating mode */
2385                 switch (control->type) {
2386                 case WM8958:
2387                 case WM1811:
2388                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2389                                             WM8958_MICB1_MODE, 0);
2390                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2391                                             WM8958_MICB2_MODE, 0);
2392                         break;
2393                 default:
2394                         break;
2395                 }
2396
2397                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2398                         active_reference(codec);
2399                 break;
2400
2401         case SND_SOC_BIAS_STANDBY:
2402                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2403                         switch (control->type) {
2404                         case WM8958:
2405                                 if (wm8994->revision == 0) {
2406                                         /* Optimise performance for rev A */
2407                                         snd_soc_update_bits(codec,
2408                                                             WM8958_CHARGE_PUMP_2,
2409                                                             WM8958_CP_DISCH,
2410                                                             WM8958_CP_DISCH);
2411                                 }
2412                                 break;
2413
2414                         default:
2415                                 break;
2416                         }
2417
2418                         /* Discharge LINEOUT1 & 2 */
2419                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2420                                             WM8994_LINEOUT1_DISCH |
2421                                             WM8994_LINEOUT2_DISCH,
2422                                             WM8994_LINEOUT1_DISCH |
2423                                             WM8994_LINEOUT2_DISCH);
2424                 }
2425
2426                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2427                         active_dereference(codec);
2428
2429                 /* MICBIAS into bypass mode on newer devices */
2430                 switch (control->type) {
2431                 case WM8958:
2432                 case WM1811:
2433                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2434                                             WM8958_MICB1_MODE,
2435                                             WM8958_MICB1_MODE);
2436                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2437                                             WM8958_MICB2_MODE,
2438                                             WM8958_MICB2_MODE);
2439                         break;
2440                 default:
2441                         break;
2442                 }
2443                 break;
2444
2445         case SND_SOC_BIAS_OFF:
2446                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2447                         wm8994->cur_fw = NULL;
2448                 break;
2449         }
2450
2451         codec->dapm.bias_level = level;
2452
2453         return 0;
2454 }
2455
2456 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2457 {
2458         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2459
2460         switch (mode) {
2461         case WM8994_VMID_NORMAL:
2462                 if (wm8994->hubs.lineout1_se) {
2463                         snd_soc_dapm_disable_pin(&codec->dapm,
2464                                                  "LINEOUT1N Driver");
2465                         snd_soc_dapm_disable_pin(&codec->dapm,
2466                                                  "LINEOUT1P Driver");
2467                 }
2468                 if (wm8994->hubs.lineout2_se) {
2469                         snd_soc_dapm_disable_pin(&codec->dapm,
2470                                                  "LINEOUT2N Driver");
2471                         snd_soc_dapm_disable_pin(&codec->dapm,
2472                                                  "LINEOUT2P Driver");
2473                 }
2474
2475                 /* Do the sync with the old mode to allow it to clean up */
2476                 snd_soc_dapm_sync(&codec->dapm);
2477                 wm8994->vmid_mode = mode;
2478                 break;
2479
2480         case WM8994_VMID_FORCE:
2481                 if (wm8994->hubs.lineout1_se) {
2482                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2483                                                       "LINEOUT1N Driver");
2484                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2485                                                       "LINEOUT1P Driver");
2486                 }
2487                 if (wm8994->hubs.lineout2_se) {
2488                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2489                                                       "LINEOUT2N Driver");
2490                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2491                                                       "LINEOUT2P Driver");
2492                 }
2493
2494                 wm8994->vmid_mode = mode;
2495                 snd_soc_dapm_sync(&codec->dapm);
2496                 break;
2497
2498         default:
2499                 return -EINVAL;
2500         }
2501
2502         return 0;
2503 }
2504
2505 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2506 {
2507         struct snd_soc_codec *codec = dai->codec;
2508         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2509         struct wm8994 *control = wm8994->wm8994;
2510         int ms_reg;
2511         int aif1_reg;
2512         int ms = 0;
2513         int aif1 = 0;
2514
2515         switch (dai->id) {
2516         case 1:
2517                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2518                 aif1_reg = WM8994_AIF1_CONTROL_1;
2519                 break;
2520         case 2:
2521                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2522                 aif1_reg = WM8994_AIF2_CONTROL_1;
2523                 break;
2524         default:
2525                 return -EINVAL;
2526         }
2527
2528         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2529         case SND_SOC_DAIFMT_CBS_CFS:
2530                 break;
2531         case SND_SOC_DAIFMT_CBM_CFM:
2532                 ms = WM8994_AIF1_MSTR;
2533                 break;
2534         default:
2535                 return -EINVAL;
2536         }
2537
2538         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2539         case SND_SOC_DAIFMT_DSP_B:
2540                 aif1 |= WM8994_AIF1_LRCLK_INV;
2541         case SND_SOC_DAIFMT_DSP_A:
2542                 aif1 |= 0x18;
2543                 break;
2544         case SND_SOC_DAIFMT_I2S:
2545                 aif1 |= 0x10;
2546                 break;
2547         case SND_SOC_DAIFMT_RIGHT_J:
2548                 break;
2549         case SND_SOC_DAIFMT_LEFT_J:
2550                 aif1 |= 0x8;
2551                 break;
2552         default:
2553                 return -EINVAL;
2554         }
2555
2556         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2557         case SND_SOC_DAIFMT_DSP_A:
2558         case SND_SOC_DAIFMT_DSP_B:
2559                 /* frame inversion not valid for DSP modes */
2560                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2561                 case SND_SOC_DAIFMT_NB_NF:
2562                         break;
2563                 case SND_SOC_DAIFMT_IB_NF:
2564                         aif1 |= WM8994_AIF1_BCLK_INV;
2565                         break;
2566                 default:
2567                         return -EINVAL;
2568                 }
2569                 break;
2570
2571         case SND_SOC_DAIFMT_I2S:
2572         case SND_SOC_DAIFMT_RIGHT_J:
2573         case SND_SOC_DAIFMT_LEFT_J:
2574                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2575                 case SND_SOC_DAIFMT_NB_NF:
2576                         break;
2577                 case SND_SOC_DAIFMT_IB_IF:
2578                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2579                         break;
2580                 case SND_SOC_DAIFMT_IB_NF:
2581                         aif1 |= WM8994_AIF1_BCLK_INV;
2582                         break;
2583                 case SND_SOC_DAIFMT_NB_IF:
2584                         aif1 |= WM8994_AIF1_LRCLK_INV;
2585                         break;
2586                 default:
2587                         return -EINVAL;
2588                 }
2589                 break;
2590         default:
2591                 return -EINVAL;
2592         }
2593
2594         /* The AIF2 format configuration needs to be mirrored to AIF3
2595          * on WM8958 if it's in use so just do it all the time. */
2596         switch (control->type) {
2597         case WM1811:
2598         case WM8958:
2599                 if (dai->id == 2)
2600                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2601                                             WM8994_AIF1_LRCLK_INV |
2602                                             WM8958_AIF3_FMT_MASK, aif1);
2603                 break;
2604
2605         default:
2606                 break;
2607         }
2608
2609         snd_soc_update_bits(codec, aif1_reg,
2610                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2611                             WM8994_AIF1_FMT_MASK,
2612                             aif1);
2613         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2614                             ms);
2615
2616         return 0;
2617 }
2618
2619 static struct {
2620         int val, rate;
2621 } srs[] = {
2622         { 0,   8000 },
2623         { 1,  11025 },
2624         { 2,  12000 },
2625         { 3,  16000 },
2626         { 4,  22050 },
2627         { 5,  24000 },
2628         { 6,  32000 },
2629         { 7,  44100 },
2630         { 8,  48000 },
2631         { 9,  88200 },
2632         { 10, 96000 },
2633 };
2634
2635 static int fs_ratios[] = {
2636         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2637 };
2638
2639 static int bclk_divs[] = {
2640         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2641         640, 880, 960, 1280, 1760, 1920
2642 };
2643
2644 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2645                             struct snd_pcm_hw_params *params,
2646                             struct snd_soc_dai *dai)
2647 {
2648         struct snd_soc_codec *codec = dai->codec;
2649         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2650         int aif1_reg;
2651         int aif2_reg;
2652         int bclk_reg;
2653         int lrclk_reg;
2654         int rate_reg;
2655         int aif1 = 0;
2656         int aif2 = 0;
2657         int bclk = 0;
2658         int lrclk = 0;
2659         int rate_val = 0;
2660         int id = dai->id - 1;
2661
2662         int i, cur_val, best_val, bclk_rate, best;
2663
2664         switch (dai->id) {
2665         case 1:
2666                 aif1_reg = WM8994_AIF1_CONTROL_1;
2667                 aif2_reg = WM8994_AIF1_CONTROL_2;
2668                 bclk_reg = WM8994_AIF1_BCLK;
2669                 rate_reg = WM8994_AIF1_RATE;
2670                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2671                     wm8994->lrclk_shared[0]) {
2672                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2673                 } else {
2674                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2675                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2676                 }
2677                 break;
2678         case 2:
2679                 aif1_reg = WM8994_AIF2_CONTROL_1;
2680                 aif2_reg = WM8994_AIF2_CONTROL_2;
2681                 bclk_reg = WM8994_AIF2_BCLK;
2682                 rate_reg = WM8994_AIF2_RATE;
2683                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2684                     wm8994->lrclk_shared[1]) {
2685                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2686                 } else {
2687                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2688                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2689                 }
2690                 break;
2691         default:
2692                 return -EINVAL;
2693         }
2694
2695         bclk_rate = params_rate(params);
2696         switch (params_format(params)) {
2697         case SNDRV_PCM_FORMAT_S16_LE:
2698                 bclk_rate *= 16;
2699                 break;
2700         case SNDRV_PCM_FORMAT_S20_3LE:
2701                 bclk_rate *= 20;
2702                 aif1 |= 0x20;
2703                 break;
2704         case SNDRV_PCM_FORMAT_S24_LE:
2705                 bclk_rate *= 24;
2706                 aif1 |= 0x40;
2707                 break;
2708         case SNDRV_PCM_FORMAT_S32_LE:
2709                 bclk_rate *= 32;
2710                 aif1 |= 0x60;
2711                 break;
2712         default:
2713                 return -EINVAL;
2714         }
2715
2716         wm8994->channels[id] = params_channels(params);
2717         switch (params_channels(params)) {
2718         case 1:
2719         case 2:
2720                 bclk_rate *= 2;
2721                 break;
2722         default:
2723                 bclk_rate *= 4;
2724                 break;
2725         }
2726
2727         /* Try to find an appropriate sample rate; look for an exact match. */
2728         for (i = 0; i < ARRAY_SIZE(srs); i++)
2729                 if (srs[i].rate == params_rate(params))
2730                         break;
2731         if (i == ARRAY_SIZE(srs))
2732                 return -EINVAL;
2733         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2734
2735         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2736         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2737                 dai->id, wm8994->aifclk[id], bclk_rate);
2738
2739         if (params_channels(params) == 1 &&
2740             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2741                 aif2 |= WM8994_AIF1_MONO;
2742
2743         if (wm8994->aifclk[id] == 0) {
2744                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2745                 return -EINVAL;
2746         }
2747
2748         /* AIFCLK/fs ratio; look for a close match in either direction */
2749         best = 0;
2750         best_val = abs((fs_ratios[0] * params_rate(params))
2751                        - wm8994->aifclk[id]);
2752         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2753                 cur_val = abs((fs_ratios[i] * params_rate(params))
2754                               - wm8994->aifclk[id]);
2755                 if (cur_val >= best_val)
2756                         continue;
2757                 best = i;
2758                 best_val = cur_val;
2759         }
2760         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2761                 dai->id, fs_ratios[best]);
2762         rate_val |= best;
2763
2764         /* We may not get quite the right frequency if using
2765          * approximate clocks so look for the closest match that is
2766          * higher than the target (we need to ensure that there enough
2767          * BCLKs to clock out the samples).
2768          */
2769         best = 0;
2770         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2771                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2772                 if (cur_val < 0) /* BCLK table is sorted */
2773                         break;
2774                 best = i;
2775         }
2776         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2777         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2778                 bclk_divs[best], bclk_rate);
2779         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2780
2781         lrclk = bclk_rate / params_rate(params);
2782         if (!lrclk) {
2783                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2784                         bclk_rate);
2785                 return -EINVAL;
2786         }
2787         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2788                 lrclk, bclk_rate / lrclk);
2789
2790         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2791         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2792         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2793         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2794                             lrclk);
2795         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2796                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2797
2798         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2799                 switch (dai->id) {
2800                 case 1:
2801                         wm8994->dac_rates[0] = params_rate(params);
2802                         wm8994_set_retune_mobile(codec, 0);
2803                         wm8994_set_retune_mobile(codec, 1);
2804                         break;
2805                 case 2:
2806                         wm8994->dac_rates[1] = params_rate(params);
2807                         wm8994_set_retune_mobile(codec, 2);
2808                         break;
2809                 }
2810         }
2811
2812         return 0;
2813 }
2814
2815 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2816                                  struct snd_pcm_hw_params *params,
2817                                  struct snd_soc_dai *dai)
2818 {
2819         struct snd_soc_codec *codec = dai->codec;
2820         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2821         struct wm8994 *control = wm8994->wm8994;
2822         int aif1_reg;
2823         int aif1 = 0;
2824
2825         switch (dai->id) {
2826         case 3:
2827                 switch (control->type) {
2828                 case WM1811:
2829                 case WM8958:
2830                         aif1_reg = WM8958_AIF3_CONTROL_1;
2831                         break;
2832                 default:
2833                         return 0;
2834                 }
2835         default:
2836                 return 0;
2837         }
2838
2839         switch (params_format(params)) {
2840         case SNDRV_PCM_FORMAT_S16_LE:
2841                 break;
2842         case SNDRV_PCM_FORMAT_S20_3LE:
2843                 aif1 |= 0x20;
2844                 break;
2845         case SNDRV_PCM_FORMAT_S24_LE:
2846                 aif1 |= 0x40;
2847                 break;
2848         case SNDRV_PCM_FORMAT_S32_LE:
2849                 aif1 |= 0x60;
2850                 break;
2851         default:
2852                 return -EINVAL;
2853         }
2854
2855         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2856 }
2857
2858 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2859 {
2860         struct snd_soc_codec *codec = codec_dai->codec;
2861         int mute_reg;
2862         int reg;
2863
2864         switch (codec_dai->id) {
2865         case 1:
2866                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2867                 break;
2868         case 2:
2869                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2870                 break;
2871         default:
2872                 return -EINVAL;
2873         }
2874
2875         if (mute)
2876                 reg = WM8994_AIF1DAC1_MUTE;
2877         else
2878                 reg = 0;
2879
2880         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2881
2882         return 0;
2883 }
2884
2885 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2886 {
2887         struct snd_soc_codec *codec = codec_dai->codec;
2888         int reg, val, mask;
2889
2890         switch (codec_dai->id) {
2891         case 1:
2892                 reg = WM8994_AIF1_MASTER_SLAVE;
2893                 mask = WM8994_AIF1_TRI;
2894                 break;
2895         case 2:
2896                 reg = WM8994_AIF2_MASTER_SLAVE;
2897                 mask = WM8994_AIF2_TRI;
2898                 break;
2899         default:
2900                 return -EINVAL;
2901         }
2902
2903         if (tristate)
2904                 val = mask;
2905         else
2906                 val = 0;
2907
2908         return snd_soc_update_bits(codec, reg, mask, val);
2909 }
2910
2911 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2912 {
2913         struct snd_soc_codec *codec = dai->codec;
2914
2915         /* Disable the pulls on the AIF if we're using it to save power. */
2916         snd_soc_update_bits(codec, WM8994_GPIO_3,
2917                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2918         snd_soc_update_bits(codec, WM8994_GPIO_4,
2919                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2920         snd_soc_update_bits(codec, WM8994_GPIO_5,
2921                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2922
2923         return 0;
2924 }
2925
2926 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2927
2928 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2929                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2930
2931 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2932         .set_sysclk     = wm8994_set_dai_sysclk,
2933         .set_fmt        = wm8994_set_dai_fmt,
2934         .hw_params      = wm8994_hw_params,
2935         .digital_mute   = wm8994_aif_mute,
2936         .set_pll        = wm8994_set_fll,
2937         .set_tristate   = wm8994_set_tristate,
2938 };
2939
2940 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2941         .set_sysclk     = wm8994_set_dai_sysclk,
2942         .set_fmt        = wm8994_set_dai_fmt,
2943         .hw_params      = wm8994_hw_params,
2944         .digital_mute   = wm8994_aif_mute,
2945         .set_pll        = wm8994_set_fll,
2946         .set_tristate   = wm8994_set_tristate,
2947 };
2948
2949 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2950         .hw_params      = wm8994_aif3_hw_params,
2951 };
2952
2953 static struct snd_soc_dai_driver wm8994_dai[] = {
2954         {
2955                 .name = "wm8994-aif1",
2956                 .id = 1,
2957                 .playback = {
2958                         .stream_name = "AIF1 Playback",
2959                         .channels_min = 1,
2960                         .channels_max = 2,
2961                         .rates = WM8994_RATES,
2962                         .formats = WM8994_FORMATS,
2963                         .sig_bits = 24,
2964                 },
2965                 .capture = {
2966                         .stream_name = "AIF1 Capture",
2967                         .channels_min = 1,
2968                         .channels_max = 2,
2969                         .rates = WM8994_RATES,
2970                         .formats = WM8994_FORMATS,
2971                         .sig_bits = 24,
2972                  },
2973                 .ops = &wm8994_aif1_dai_ops,
2974         },
2975         {
2976                 .name = "wm8994-aif2",
2977                 .id = 2,
2978                 .playback = {
2979                         .stream_name = "AIF2 Playback",
2980                         .channels_min = 1,
2981                         .channels_max = 2,
2982                         .rates = WM8994_RATES,
2983                         .formats = WM8994_FORMATS,
2984                         .sig_bits = 24,
2985                 },
2986                 .capture = {
2987                         .stream_name = "AIF2 Capture",
2988                         .channels_min = 1,
2989                         .channels_max = 2,
2990                         .rates = WM8994_RATES,
2991                         .formats = WM8994_FORMATS,
2992                         .sig_bits = 24,
2993                 },
2994                 .probe = wm8994_aif2_probe,
2995                 .ops = &wm8994_aif2_dai_ops,
2996         },
2997         {
2998                 .name = "wm8994-aif3",
2999                 .id = 3,
3000                 .playback = {
3001                         .stream_name = "AIF3 Playback",
3002                         .channels_min = 1,
3003                         .channels_max = 2,
3004                         .rates = WM8994_RATES,
3005                         .formats = WM8994_FORMATS,
3006                         .sig_bits = 24,
3007                 },
3008                 .capture = {
3009                         .stream_name = "AIF3 Capture",
3010                         .channels_min = 1,
3011                         .channels_max = 2,
3012                         .rates = WM8994_RATES,
3013                         .formats = WM8994_FORMATS,
3014                         .sig_bits = 24,
3015                  },
3016                 .ops = &wm8994_aif3_dai_ops,
3017         }
3018 };
3019
3020 #ifdef CONFIG_PM
3021 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3022 {
3023         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3024         int i, ret;
3025
3026         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3027                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3028                        sizeof(struct wm8994_fll_config));
3029                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3030                 if (ret < 0)
3031                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3032                                  i + 1, ret);
3033         }
3034
3035         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3036
3037         return 0;
3038 }
3039
3040 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3041 {
3042         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3043         struct wm8994 *control = wm8994->wm8994;
3044         int i, ret;
3045         unsigned int val, mask;
3046
3047         if (wm8994->revision < 4) {
3048                 /* force a HW read */
3049                 ret = regmap_read(control->regmap,
3050                                   WM8994_POWER_MANAGEMENT_5, &val);
3051
3052                 /* modify the cache only */
3053                 codec->cache_only = 1;
3054                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3055                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3056                 val &= mask;
3057                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3058                                     mask, val);
3059                 codec->cache_only = 0;
3060         }
3061
3062         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3063                 if (!wm8994->fll_suspend[i].out)
3064                         continue;
3065
3066                 ret = _wm8994_set_fll(codec, i + 1,
3067                                      wm8994->fll_suspend[i].src,
3068                                      wm8994->fll_suspend[i].in,
3069                                      wm8994->fll_suspend[i].out);
3070                 if (ret < 0)
3071                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3072                                  i + 1, ret);
3073         }
3074
3075         return 0;
3076 }
3077 #else
3078 #define wm8994_codec_suspend NULL
3079 #define wm8994_codec_resume NULL
3080 #endif
3081
3082 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3083 {
3084         struct snd_soc_codec *codec = wm8994->hubs.codec;
3085         struct wm8994_pdata *pdata = wm8994->pdata;
3086         struct snd_kcontrol_new controls[] = {
3087                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3088                              wm8994->retune_mobile_enum,
3089                              wm8994_get_retune_mobile_enum,
3090                              wm8994_put_retune_mobile_enum),
3091                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3092                              wm8994->retune_mobile_enum,
3093                              wm8994_get_retune_mobile_enum,
3094                              wm8994_put_retune_mobile_enum),
3095                 SOC_ENUM_EXT("AIF2 EQ Mode",
3096                              wm8994->retune_mobile_enum,
3097                              wm8994_get_retune_mobile_enum,
3098                              wm8994_put_retune_mobile_enum),
3099         };
3100         int ret, i, j;
3101         const char **t;
3102
3103         /* We need an array of texts for the enum API but the number
3104          * of texts is likely to be less than the number of
3105          * configurations due to the sample rate dependency of the
3106          * configurations. */
3107         wm8994->num_retune_mobile_texts = 0;
3108         wm8994->retune_mobile_texts = NULL;
3109         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3110                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3111                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
3112                                    wm8994->retune_mobile_texts[j]) == 0)
3113                                 break;
3114                 }
3115
3116                 if (j != wm8994->num_retune_mobile_texts)
3117                         continue;
3118
3119                 /* Expand the array... */
3120                 t = krealloc(wm8994->retune_mobile_texts,
3121                              sizeof(char *) *
3122                              (wm8994->num_retune_mobile_texts + 1),
3123                              GFP_KERNEL);
3124                 if (t == NULL)
3125                         continue;
3126
3127                 /* ...store the new entry... */
3128                 t[wm8994->num_retune_mobile_texts] =
3129                         pdata->retune_mobile_cfgs[i].name;
3130
3131                 /* ...and remember the new version. */
3132                 wm8994->num_retune_mobile_texts++;
3133                 wm8994->retune_mobile_texts = t;
3134         }
3135
3136         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3137                 wm8994->num_retune_mobile_texts);
3138
3139         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3140         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3141
3142         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3143                                    ARRAY_SIZE(controls));
3144         if (ret != 0)
3145                 dev_err(wm8994->hubs.codec->dev,
3146                         "Failed to add ReTune Mobile controls: %d\n", ret);
3147 }
3148
3149 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3150 {
3151         struct snd_soc_codec *codec = wm8994->hubs.codec;
3152         struct wm8994_pdata *pdata = wm8994->pdata;
3153         int ret, i;
3154
3155         if (!pdata)
3156                 return;
3157
3158         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3159                                       pdata->lineout2_diff,
3160                                       pdata->lineout1fb,
3161                                       pdata->lineout2fb,
3162                                       pdata->jd_scthr,
3163                                       pdata->jd_thr,
3164                                       pdata->micb1_delay,
3165                                       pdata->micb2_delay,
3166                                       pdata->micbias1_lvl,
3167                                       pdata->micbias2_lvl);
3168
3169         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3170
3171         if (pdata->num_drc_cfgs) {
3172                 struct snd_kcontrol_new controls[] = {
3173                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3174                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3175                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3176                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3177                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3178                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3179                 };
3180
3181                 /* We need an array of texts for the enum API */
3182                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3183                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3184                 if (!wm8994->drc_texts) {
3185                         dev_err(wm8994->hubs.codec->dev,
3186                                 "Failed to allocate %d DRC config texts\n",
3187                                 pdata->num_drc_cfgs);
3188                         return;
3189                 }
3190
3191                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3192                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3193
3194                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3195                 wm8994->drc_enum.texts = wm8994->drc_texts;
3196
3197                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3198                                            ARRAY_SIZE(controls));
3199                 for (i = 0; i < WM8994_NUM_DRC; i++)
3200                         wm8994_set_drc(codec, i);
3201         } else {
3202                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3203                                                  wm8994_drc_controls,
3204                                                  ARRAY_SIZE(wm8994_drc_controls));
3205         }
3206
3207         if (ret != 0)
3208                 dev_err(wm8994->hubs.codec->dev,
3209                         "Failed to add DRC mode controls: %d\n", ret);
3210
3211
3212         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3213                 pdata->num_retune_mobile_cfgs);
3214
3215         if (pdata->num_retune_mobile_cfgs)
3216                 wm8994_handle_retune_mobile_pdata(wm8994);
3217         else
3218                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3219                                      ARRAY_SIZE(wm8994_eq_controls));
3220
3221         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3222                 if (pdata->micbias[i]) {
3223