9685dff44dd8a9a9cc87d2ddb7173e2d26ba7e7c
[~shefty/rdma-dev.git] / sound / soc / codecs / wm8994.c
1 /*
2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
3  *
4  * Copyright 2009 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE  0x0000
42 #define WM1811_JACKDET_MODE_JACK  0x0100
43 #define WM1811_JACKDET_MODE_MIC   0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ  3
48
49 static int wm8994_drc_base[] = {
50         WM8994_AIF1_DRC1_1,
51         WM8994_AIF1_DRC2_1,
52         WM8994_AIF2_DRC_1,
53 };
54
55 static int wm8994_retune_mobile_base[] = {
56         WM8994_AIF1_DAC1_EQ_GAINS_1,
57         WM8994_AIF1_DAC2_EQ_GAINS_1,
58         WM8994_AIF2_EQ_GAINS_1,
59 };
60
61 static void wm8958_default_micdet(u16 status, void *data);
62
63 static const struct wm8958_micd_rate micdet_rates[] = {
64         { 32768,       true,  1, 4 },
65         { 32768,       false, 1, 1 },
66         { 44100 * 256, true,  7, 10 },
67         { 44100 * 256, false, 7, 10 },
68 };
69
70 static const struct wm8958_micd_rate jackdet_rates[] = {
71         { 32768,       true,  0, 1 },
72         { 32768,       false, 0, 1 },
73         { 44100 * 256, true,  7, 10 },
74         { 44100 * 256, false, 7, 10 },
75 };
76
77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78 {
79         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80         int best, i, sysclk, val;
81         bool idle;
82         const struct wm8958_micd_rate *rates;
83         int num_rates;
84
85         if (wm8994->jack_cb != wm8958_default_micdet)
86                 return;
87
88         idle = !wm8994->jack_mic;
89
90         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91         if (sysclk & WM8994_SYSCLK_SRC)
92                 sysclk = wm8994->aifclk[1];
93         else
94                 sysclk = wm8994->aifclk[0];
95
96         if (wm8994->pdata && wm8994->pdata->micd_rates) {
97                 rates = wm8994->pdata->micd_rates;
98                 num_rates = wm8994->pdata->num_micd_rates;
99         } else if (wm8994->jackdet) {
100                 rates = jackdet_rates;
101                 num_rates = ARRAY_SIZE(jackdet_rates);
102         } else {
103                 rates = micdet_rates;
104                 num_rates = ARRAY_SIZE(micdet_rates);
105         }
106
107         best = 0;
108         for (i = 0; i < num_rates; i++) {
109                 if (rates[i].idle != idle)
110                         continue;
111                 if (abs(rates[i].sysclk - sysclk) <
112                     abs(rates[best].sysclk - sysclk))
113                         best = i;
114                 else if (rates[best].idle != idle)
115                         best = i;
116         }
117
118         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
120
121         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122                             WM8958_MICD_BIAS_STARTTIME_MASK |
123                             WM8958_MICD_RATE_MASK, val);
124 }
125
126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127 {
128         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
129         int rate;
130         int reg1 = 0;
131         int offset;
132
133         if (aif)
134                 offset = 4;
135         else
136                 offset = 0;
137
138         switch (wm8994->sysclk[aif]) {
139         case WM8994_SYSCLK_MCLK1:
140                 rate = wm8994->mclk[0];
141                 break;
142
143         case WM8994_SYSCLK_MCLK2:
144                 reg1 |= 0x8;
145                 rate = wm8994->mclk[1];
146                 break;
147
148         case WM8994_SYSCLK_FLL1:
149                 reg1 |= 0x10;
150                 rate = wm8994->fll[0].out;
151                 break;
152
153         case WM8994_SYSCLK_FLL2:
154                 reg1 |= 0x18;
155                 rate = wm8994->fll[1].out;
156                 break;
157
158         default:
159                 return -EINVAL;
160         }
161
162         if (rate >= 13500000) {
163                 rate /= 2;
164                 reg1 |= WM8994_AIF1CLK_DIV;
165
166                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167                         aif + 1, rate);
168         }
169
170         wm8994->aifclk[aif] = rate;
171
172         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174                             reg1);
175
176         return 0;
177 }
178
179 static int configure_clock(struct snd_soc_codec *codec)
180 {
181         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
182         int change, new;
183
184         /* Bring up the AIF clocks first */
185         configure_aif_clock(codec, 0);
186         configure_aif_clock(codec, 1);
187
188         /* Then switch CLK_SYS over to the higher of them; a change
189          * can only happen as a result of a clocking change which can
190          * only be made outside of DAPM so we can safely redo the
191          * clocking.
192          */
193
194         /* If they're equal it doesn't matter which is used */
195         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196                 wm8958_micd_set_rate(codec);
197                 return 0;
198         }
199
200         if (wm8994->aifclk[0] < wm8994->aifclk[1])
201                 new = WM8994_SYSCLK_SRC;
202         else
203                 new = 0;
204
205         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206                                      WM8994_SYSCLK_SRC, new);
207         if (change)
208                 snd_soc_dapm_sync(&codec->dapm);
209
210         wm8958_micd_set_rate(codec);
211
212         return 0;
213 }
214
215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
216                          struct snd_soc_dapm_widget *sink)
217 {
218         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219         const char *clk;
220
221         /* Check what we're currently using for CLK_SYS */
222         if (reg & WM8994_SYSCLK_SRC)
223                 clk = "AIF2CLK";
224         else
225                 clk = "AIF1CLK";
226
227         return strcmp(source->name, clk) == 0;
228 }
229
230 static const char *sidetone_hpf_text[] = {
231         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232 };
233
234 static const struct soc_enum sidetone_hpf =
235         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
237 static const char *adc_hpf_text[] = {
238         "HiFi", "Voice 1", "Voice 2", "Voice 3"
239 };
240
241 static const struct soc_enum aif1adc1_hpf =
242         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244 static const struct soc_enum aif1adc2_hpf =
245         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247 static const struct soc_enum aif2adc_hpf =
248         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
257
258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
259 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261         .put = wm8994_put_drc_sw, \
262         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265                              struct snd_ctl_elem_value *ucontrol)
266 {
267         struct soc_mixer_control *mc =
268                 (struct soc_mixer_control *)kcontrol->private_value;
269         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270         int mask, ret;
271
272         /* Can't enable both ADC and DAC paths simultaneously */
273         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
276         else
277                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279         ret = snd_soc_read(codec, mc->reg);
280         if (ret < 0)
281                 return ret;
282         if (ret & mask)
283                 return -EINVAL;
284
285         return snd_soc_put_volsw(kcontrol, ucontrol);
286 }
287
288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289 {
290         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
291         struct wm8994_pdata *pdata = wm8994->pdata;
292         int base = wm8994_drc_base[drc];
293         int cfg = wm8994->drc_cfg[drc];
294         int save, i;
295
296         /* Save any enables; the configuration should clear them. */
297         save = snd_soc_read(codec, base);
298         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299                 WM8994_AIF1ADC1R_DRC_ENA;
300
301         for (i = 0; i < WM8994_DRC_REGS; i++)
302                 snd_soc_update_bits(codec, base + i, 0xffff,
303                                     pdata->drc_cfgs[cfg].regs[i]);
304
305         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306                              WM8994_AIF1ADC1L_DRC_ENA |
307                              WM8994_AIF1ADC1R_DRC_ENA, save);
308 }
309
310 /* Icky as hell but saves code duplication */
311 static int wm8994_get_drc(const char *name)
312 {
313         if (strcmp(name, "AIF1DRC1 Mode") == 0)
314                 return 0;
315         if (strcmp(name, "AIF1DRC2 Mode") == 0)
316                 return 1;
317         if (strcmp(name, "AIF2DRC Mode") == 0)
318                 return 2;
319         return -EINVAL;
320 }
321
322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323                                struct snd_ctl_elem_value *ucontrol)
324 {
325         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
326         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
327         struct wm8994_pdata *pdata = wm8994->pdata;
328         int drc = wm8994_get_drc(kcontrol->id.name);
329         int value = ucontrol->value.integer.value[0];
330
331         if (drc < 0)
332                 return drc;
333
334         if (value >= pdata->num_drc_cfgs)
335                 return -EINVAL;
336
337         wm8994->drc_cfg[drc] = value;
338
339         wm8994_set_drc(codec, drc);
340
341         return 0;
342 }
343
344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345                                struct snd_ctl_elem_value *ucontrol)
346 {
347         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
348         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
349         int drc = wm8994_get_drc(kcontrol->id.name);
350
351         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353         return 0;
354 }
355
356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357 {
358         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
359         struct wm8994_pdata *pdata = wm8994->pdata;
360         int base = wm8994_retune_mobile_base[block];
361         int iface, best, best_val, save, i, cfg;
362
363         if (!pdata || !wm8994->num_retune_mobile_texts)
364                 return;
365
366         switch (block) {
367         case 0:
368         case 1:
369                 iface = 0;
370                 break;
371         case 2:
372                 iface = 1;
373                 break;
374         default:
375                 return;
376         }
377
378         /* Find the version of the currently selected configuration
379          * with the nearest sample rate. */
380         cfg = wm8994->retune_mobile_cfg[block];
381         best = 0;
382         best_val = INT_MAX;
383         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385                            wm8994->retune_mobile_texts[cfg]) == 0 &&
386                     abs(pdata->retune_mobile_cfgs[i].rate
387                         - wm8994->dac_rates[iface]) < best_val) {
388                         best = i;
389                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
390                                        - wm8994->dac_rates[iface]);
391                 }
392         }
393
394         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395                 block,
396                 pdata->retune_mobile_cfgs[best].name,
397                 pdata->retune_mobile_cfgs[best].rate,
398                 wm8994->dac_rates[iface]);
399
400         /* The EQ will be disabled while reconfiguring it, remember the
401          * current configuration. 
402          */
403         save = snd_soc_read(codec, base);
404         save &= WM8994_AIF1DAC1_EQ_ENA;
405
406         for (i = 0; i < WM8994_EQ_REGS; i++)
407                 snd_soc_update_bits(codec, base + i, 0xffff,
408                                 pdata->retune_mobile_cfgs[best].regs[i]);
409
410         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411 }
412
413 /* Icky as hell but saves code duplication */
414 static int wm8994_get_retune_mobile_block(const char *name)
415 {
416         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417                 return 0;
418         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419                 return 1;
420         if (strcmp(name, "AIF2 EQ Mode") == 0)
421                 return 2;
422         return -EINVAL;
423 }
424
425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426                                          struct snd_ctl_elem_value *ucontrol)
427 {
428         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
430         struct wm8994_pdata *pdata = wm8994->pdata;
431         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432         int value = ucontrol->value.integer.value[0];
433
434         if (block < 0)
435                 return block;
436
437         if (value >= pdata->num_retune_mobile_cfgs)
438                 return -EINVAL;
439
440         wm8994->retune_mobile_cfg[block] = value;
441
442         wm8994_set_retune_mobile(codec, block);
443
444         return 0;
445 }
446
447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448                                          struct snd_ctl_elem_value *ucontrol)
449 {
450         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
451         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
452         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456         return 0;
457 }
458
459 static const char *aif_chan_src_text[] = {
460         "Left", "Right"
461 };
462
463 static const struct soc_enum aif1adcl_src =
464         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466 static const struct soc_enum aif1adcr_src =
467         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469 static const struct soc_enum aif2adcl_src =
470         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472 static const struct soc_enum aif2adcr_src =
473         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
475 static const struct soc_enum aif1dacl_src =
476         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
477
478 static const struct soc_enum aif1dacr_src =
479         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
480
481 static const struct soc_enum aif2dacl_src =
482         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
483
484 static const struct soc_enum aif2dacr_src =
485         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
486
487 static const char *osr_text[] = {
488         "Low Power", "High Performance",
489 };
490
491 static const struct soc_enum dac_osr =
492         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494 static const struct soc_enum adc_osr =
495         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
500                  1, 119, 0, digital_tlv),
501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
503                  1, 119, 0, digital_tlv),
504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505                  WM8994_AIF2_ADC_RIGHT_VOLUME,
506                  1, 119, 0, digital_tlv),
507
508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
512
513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
517
518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545                5, 12, 0, st_tlv),
546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547                0, 12, 0, st_tlv),
548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549                5, 12, 0, st_tlv),
550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551                0, 12, 0, st_tlv),
552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
564 SOC_ENUM("ADC OSR", adc_osr),
565 SOC_ENUM("DAC OSR", dac_osr),
566
567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578                6, 1, 1, wm_hubs_spkmix_tlv),
579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580                2, 1, 1, wm_hubs_spkmix_tlv),
581
582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583                6, 1, 1, wm_hubs_spkmix_tlv),
584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585                2, 1, 1, wm_hubs_spkmix_tlv),
586
587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588                10, 15, 0, wm8994_3d_tlv),
589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
590            8, 1, 0),
591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592                10, 15, 0, wm8994_3d_tlv),
593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594            8, 1, 0),
595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
596                10, 15, 0, wm8994_3d_tlv),
597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
598            8, 1, 0),
599 };
600
601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603                eq_tlv),
604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605                eq_tlv),
606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607                eq_tlv),
608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609                eq_tlv),
610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611                eq_tlv),
612
613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614                eq_tlv),
615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616                eq_tlv),
617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618                eq_tlv),
619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620                eq_tlv),
621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622                eq_tlv),
623
624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625                eq_tlv),
626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627                eq_tlv),
628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629                eq_tlv),
630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631                eq_tlv),
632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633                eq_tlv),
634 };
635
636 static const char *wm8958_ng_text[] = {
637         "30ms", "125ms", "250ms", "500ms",
638 };
639
640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
641         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
645         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648 static const struct soc_enum wm8958_aif2dac_ng_hold =
649         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
654
655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660                7, 1, ng_tlv),
661
662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667                7, 1, ng_tlv),
668
669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674                7, 1, ng_tlv),
675 };
676
677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679                mixin_boost_tlv),
680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681                mixin_boost_tlv),
682 };
683
684 /* We run all mode setting through a function to enforce audio mode */
685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686 {
687         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689         if (!wm8994->jackdet || !wm8994->jack_cb)
690                 return;
691
692         if (wm8994->active_refcount)
693                 mode = WM1811_JACKDET_MODE_AUDIO;
694
695         if (mode == wm8994->jackdet_mode)
696                 return;
697
698         wm8994->jackdet_mode = mode;
699
700         /* Always use audio mode to detect while the system is active */
701         if (mode != WM1811_JACKDET_MODE_NONE)
702                 mode = WM1811_JACKDET_MODE_AUDIO;
703
704         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
705                             WM1811_JACKDET_MODE_MASK, mode);
706 }
707
708 static void active_reference(struct snd_soc_codec *codec)
709 {
710         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
711
712         mutex_lock(&wm8994->accdet_lock);
713
714         wm8994->active_refcount++;
715
716         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
717                 wm8994->active_refcount);
718
719         /* If we're using jack detection go into audio mode */
720         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
721
722         mutex_unlock(&wm8994->accdet_lock);
723 }
724
725 static void active_dereference(struct snd_soc_codec *codec)
726 {
727         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
728         u16 mode;
729
730         mutex_lock(&wm8994->accdet_lock);
731
732         wm8994->active_refcount--;
733
734         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
735                 wm8994->active_refcount);
736
737         if (wm8994->active_refcount == 0) {
738                 /* Go into appropriate detection only mode */
739                 if (wm8994->jack_mic || wm8994->mic_detecting)
740                         mode = WM1811_JACKDET_MODE_MIC;
741                 else
742                         mode = WM1811_JACKDET_MODE_JACK;
743
744                 wm1811_jackdet_set_mode(codec, mode);
745         }
746
747         mutex_unlock(&wm8994->accdet_lock);
748 }
749
750 static int clk_sys_event(struct snd_soc_dapm_widget *w,
751                          struct snd_kcontrol *kcontrol, int event)
752 {
753         struct snd_soc_codec *codec = w->codec;
754
755         switch (event) {
756         case SND_SOC_DAPM_PRE_PMU:
757                 return configure_clock(codec);
758
759         case SND_SOC_DAPM_POST_PMD:
760                 configure_clock(codec);
761                 break;
762         }
763
764         return 0;
765 }
766
767 static void vmid_reference(struct snd_soc_codec *codec)
768 {
769         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
770
771         pm_runtime_get_sync(codec->dev);
772
773         wm8994->vmid_refcount++;
774
775         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
776                 wm8994->vmid_refcount);
777
778         if (wm8994->vmid_refcount == 1) {
779                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
780                                     WM8994_LINEOUT1_DISCH |
781                                     WM8994_LINEOUT2_DISCH, 0);
782
783                 wm_hubs_vmid_ena(codec);
784
785                 switch (wm8994->vmid_mode) {
786                 default:
787                         WARN_ON(0 == "Invalid VMID mode");
788                 case WM8994_VMID_NORMAL:
789                         /* Startup bias, VMID ramp & buffer */
790                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
791                                             WM8994_BIAS_SRC |
792                                             WM8994_VMID_DISCH |
793                                             WM8994_STARTUP_BIAS_ENA |
794                                             WM8994_VMID_BUF_ENA |
795                                             WM8994_VMID_RAMP_MASK,
796                                             WM8994_BIAS_SRC |
797                                             WM8994_STARTUP_BIAS_ENA |
798                                             WM8994_VMID_BUF_ENA |
799                                             (0x3 << WM8994_VMID_RAMP_SHIFT));
800
801                         /* Main bias enable, VMID=2x40k */
802                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
803                                             WM8994_BIAS_ENA |
804                                             WM8994_VMID_SEL_MASK,
805                                             WM8994_BIAS_ENA | 0x2);
806
807                         msleep(50);
808
809                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
810                                             WM8994_VMID_RAMP_MASK |
811                                             WM8994_BIAS_SRC,
812                                             0);
813                         break;
814
815                 case WM8994_VMID_FORCE:
816                         /* Startup bias, slow VMID ramp & buffer */
817                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
818                                             WM8994_BIAS_SRC |
819                                             WM8994_VMID_DISCH |
820                                             WM8994_STARTUP_BIAS_ENA |
821                                             WM8994_VMID_BUF_ENA |
822                                             WM8994_VMID_RAMP_MASK,
823                                             WM8994_BIAS_SRC |
824                                             WM8994_STARTUP_BIAS_ENA |
825                                             WM8994_VMID_BUF_ENA |
826                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
827
828                         /* Main bias enable, VMID=2x40k */
829                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
830                                             WM8994_BIAS_ENA |
831                                             WM8994_VMID_SEL_MASK,
832                                             WM8994_BIAS_ENA | 0x2);
833
834                         msleep(400);
835
836                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
837                                             WM8994_VMID_RAMP_MASK |
838                                             WM8994_BIAS_SRC,
839                                             0);
840                         break;
841                 }
842         }
843 }
844
845 static void vmid_dereference(struct snd_soc_codec *codec)
846 {
847         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
848
849         wm8994->vmid_refcount--;
850
851         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
852                 wm8994->vmid_refcount);
853
854         if (wm8994->vmid_refcount == 0) {
855                 if (wm8994->hubs.lineout1_se)
856                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
857                                             WM8994_LINEOUT1N_ENA |
858                                             WM8994_LINEOUT1P_ENA,
859                                             WM8994_LINEOUT1N_ENA |
860                                             WM8994_LINEOUT1P_ENA);
861
862                 if (wm8994->hubs.lineout2_se)
863                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
864                                             WM8994_LINEOUT2N_ENA |
865                                             WM8994_LINEOUT2P_ENA,
866                                             WM8994_LINEOUT2N_ENA |
867                                             WM8994_LINEOUT2P_ENA);
868
869                 /* Start discharging VMID */
870                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
871                                     WM8994_BIAS_SRC |
872                                     WM8994_VMID_DISCH,
873                                     WM8994_BIAS_SRC |
874                                     WM8994_VMID_DISCH);
875
876                 switch (wm8994->vmid_mode) {
877                 case WM8994_VMID_FORCE:
878                         msleep(350);
879                         break;
880                 default:
881                         break;
882                 }
883
884                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
885                                     WM8994_VROI, WM8994_VROI);
886
887                 /* Active discharge */
888                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
889                                     WM8994_LINEOUT1_DISCH |
890                                     WM8994_LINEOUT2_DISCH,
891                                     WM8994_LINEOUT1_DISCH |
892                                     WM8994_LINEOUT2_DISCH);
893
894                 msleep(150);
895
896                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
897                                     WM8994_LINEOUT1N_ENA |
898                                     WM8994_LINEOUT1P_ENA |
899                                     WM8994_LINEOUT2N_ENA |
900                                     WM8994_LINEOUT2P_ENA, 0);
901
902                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
903                                     WM8994_VROI, 0);
904
905                 /* Switch off startup biases */
906                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
907                                     WM8994_BIAS_SRC |
908                                     WM8994_STARTUP_BIAS_ENA |
909                                     WM8994_VMID_BUF_ENA |
910                                     WM8994_VMID_RAMP_MASK, 0);
911
912                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
913                                     WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
914
915                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
916                                     WM8994_VMID_RAMP_MASK, 0);
917         }
918
919         pm_runtime_put(codec->dev);
920 }
921
922 static int vmid_event(struct snd_soc_dapm_widget *w,
923                       struct snd_kcontrol *kcontrol, int event)
924 {
925         struct snd_soc_codec *codec = w->codec;
926
927         switch (event) {
928         case SND_SOC_DAPM_PRE_PMU:
929                 vmid_reference(codec);
930                 break;
931
932         case SND_SOC_DAPM_POST_PMD:
933                 vmid_dereference(codec);
934                 break;
935         }
936
937         return 0;
938 }
939
940 static void wm8994_update_class_w(struct snd_soc_codec *codec)
941 {
942         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
943         int enable = 1;
944         int source = 0;  /* GCC flow analysis can't track enable */
945         int reg, reg_r;
946
947         /* Only support direct DAC->headphone paths */
948         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
949         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
950                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
951                 enable = 0;
952         }
953
954         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
955         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
956                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
957                 enable = 0;
958         }
959
960         /* We also need the same setting for L/R and only one path */
961         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
962         switch (reg) {
963         case WM8994_AIF2DACL_TO_DAC1L:
964                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
965                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
966                 break;
967         case WM8994_AIF1DAC2L_TO_DAC1L:
968                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
969                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
970                 break;
971         case WM8994_AIF1DAC1L_TO_DAC1L:
972                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
973                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
974                 break;
975         default:
976                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
977                 enable = 0;
978                 break;
979         }
980
981         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
982         if (reg_r != reg) {
983                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
984                 enable = 0;
985         }
986
987         if (enable) {
988                 dev_dbg(codec->dev, "Class W enabled\n");
989                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
990                                     WM8994_CP_DYN_PWR |
991                                     WM8994_CP_DYN_SRC_SEL_MASK,
992                                     source | WM8994_CP_DYN_PWR);
993                 wm8994->hubs.class_w = true;
994                 
995         } else {
996                 dev_dbg(codec->dev, "Class W disabled\n");
997                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
998                                     WM8994_CP_DYN_PWR, 0);
999                 wm8994->hubs.class_w = false;
1000         }
1001 }
1002
1003 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1004                           struct snd_kcontrol *kcontrol, int event)
1005 {
1006         struct snd_soc_codec *codec = w->codec;
1007         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1008
1009         switch (event) {
1010         case SND_SOC_DAPM_PRE_PMU:
1011                 if (wm8994->aif1clk_enable) {
1012                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1013                                             WM8994_AIF1CLK_ENA_MASK,
1014                                             WM8994_AIF1CLK_ENA);
1015                         wm8994->aif1clk_enable = 0;
1016                 }
1017                 if (wm8994->aif2clk_enable) {
1018                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1019                                             WM8994_AIF2CLK_ENA_MASK,
1020                                             WM8994_AIF2CLK_ENA);
1021                         wm8994->aif2clk_enable = 0;
1022                 }
1023                 break;
1024         }
1025
1026         /* We may also have postponed startup of DSP, handle that. */
1027         wm8958_aif_ev(w, kcontrol, event);
1028
1029         return 0;
1030 }
1031
1032 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1033                            struct snd_kcontrol *kcontrol, int event)
1034 {
1035         struct snd_soc_codec *codec = w->codec;
1036         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1037
1038         switch (event) {
1039         case SND_SOC_DAPM_POST_PMD:
1040                 if (wm8994->aif1clk_disable) {
1041                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1042                                             WM8994_AIF1CLK_ENA_MASK, 0);
1043                         wm8994->aif1clk_disable = 0;
1044                 }
1045                 if (wm8994->aif2clk_disable) {
1046                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1047                                             WM8994_AIF2CLK_ENA_MASK, 0);
1048                         wm8994->aif2clk_disable = 0;
1049                 }
1050                 break;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1057                       struct snd_kcontrol *kcontrol, int event)
1058 {
1059         struct snd_soc_codec *codec = w->codec;
1060         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1061
1062         switch (event) {
1063         case SND_SOC_DAPM_PRE_PMU:
1064                 wm8994->aif1clk_enable = 1;
1065                 break;
1066         case SND_SOC_DAPM_POST_PMD:
1067                 wm8994->aif1clk_disable = 1;
1068                 break;
1069         }
1070
1071         return 0;
1072 }
1073
1074 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1075                       struct snd_kcontrol *kcontrol, int event)
1076 {
1077         struct snd_soc_codec *codec = w->codec;
1078         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1079
1080         switch (event) {
1081         case SND_SOC_DAPM_PRE_PMU:
1082                 wm8994->aif2clk_enable = 1;
1083                 break;
1084         case SND_SOC_DAPM_POST_PMD:
1085                 wm8994->aif2clk_disable = 1;
1086                 break;
1087         }
1088
1089         return 0;
1090 }
1091
1092 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1093                       struct snd_kcontrol *kcontrol, int event)
1094 {
1095         late_enable_ev(w, kcontrol, event);
1096         return 0;
1097 }
1098
1099 static int micbias_ev(struct snd_soc_dapm_widget *w,
1100                       struct snd_kcontrol *kcontrol, int event)
1101 {
1102         late_enable_ev(w, kcontrol, event);
1103         return 0;
1104 }
1105
1106 static int dac_ev(struct snd_soc_dapm_widget *w,
1107                   struct snd_kcontrol *kcontrol, int event)
1108 {
1109         struct snd_soc_codec *codec = w->codec;
1110         unsigned int mask = 1 << w->shift;
1111
1112         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1113                             mask, mask);
1114         return 0;
1115 }
1116
1117 static const char *hp_mux_text[] = {
1118         "Mixer",
1119         "DAC",
1120 };
1121
1122 #define WM8994_HP_ENUM(xname, xenum) \
1123 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1124         .info = snd_soc_info_enum_double, \
1125         .get = snd_soc_dapm_get_enum_double, \
1126         .put = wm8994_put_hp_enum, \
1127         .private_value = (unsigned long)&xenum }
1128
1129 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1130                               struct snd_ctl_elem_value *ucontrol)
1131 {
1132         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1133         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1134         struct snd_soc_codec *codec = w->codec;
1135         int ret;
1136
1137         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1138
1139         wm8994_update_class_w(codec);
1140
1141         return ret;
1142 }
1143
1144 static const struct soc_enum hpl_enum =
1145         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1146
1147 static const struct snd_kcontrol_new hpl_mux =
1148         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1149
1150 static const struct soc_enum hpr_enum =
1151         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1152
1153 static const struct snd_kcontrol_new hpr_mux =
1154         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1155
1156 static const char *adc_mux_text[] = {
1157         "ADC",
1158         "DMIC",
1159 };
1160
1161 static const struct soc_enum adc_enum =
1162         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1163
1164 static const struct snd_kcontrol_new adcl_mux =
1165         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1166
1167 static const struct snd_kcontrol_new adcr_mux =
1168         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1169
1170 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1171 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1172 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1173 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1174 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1175 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1176 };
1177
1178 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1179 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1180 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1181 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1182 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1183 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1184 };
1185
1186 /* Debugging; dump chip status after DAPM transitions */
1187 static int post_ev(struct snd_soc_dapm_widget *w,
1188             struct snd_kcontrol *kcontrol, int event)
1189 {
1190         struct snd_soc_codec *codec = w->codec;
1191         dev_dbg(codec->dev, "SRC status: %x\n",
1192                 snd_soc_read(codec,
1193                              WM8994_RATE_STATUS));
1194         return 0;
1195 }
1196
1197 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1198 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1199                 1, 1, 0),
1200 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1201                 0, 1, 0),
1202 };
1203
1204 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1205 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1206                 1, 1, 0),
1207 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1208                 0, 1, 0),
1209 };
1210
1211 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1212 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1213                 1, 1, 0),
1214 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1215                 0, 1, 0),
1216 };
1217
1218 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1219 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1220                 1, 1, 0),
1221 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1222                 0, 1, 0),
1223 };
1224
1225 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1226 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1227                 5, 1, 0),
1228 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1229                 4, 1, 0),
1230 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1231                 2, 1, 0),
1232 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1233                 1, 1, 0),
1234 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1235                 0, 1, 0),
1236 };
1237
1238 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1239 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1240                 5, 1, 0),
1241 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1242                 4, 1, 0),
1243 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1244                 2, 1, 0),
1245 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1246                 1, 1, 0),
1247 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1248                 0, 1, 0),
1249 };
1250
1251 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1252 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1253         .info = snd_soc_info_volsw, \
1254         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1255         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1256
1257 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1258                               struct snd_ctl_elem_value *ucontrol)
1259 {
1260         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1261         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1262         struct snd_soc_codec *codec = w->codec;
1263         int ret;
1264
1265         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1266
1267         wm8994_update_class_w(codec);
1268
1269         return ret;
1270 }
1271
1272 static const struct snd_kcontrol_new dac1l_mix[] = {
1273 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1274                       5, 1, 0),
1275 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1276                       4, 1, 0),
1277 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1278                       2, 1, 0),
1279 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1280                       1, 1, 0),
1281 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1282                       0, 1, 0),
1283 };
1284
1285 static const struct snd_kcontrol_new dac1r_mix[] = {
1286 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1287                       5, 1, 0),
1288 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1289                       4, 1, 0),
1290 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1291                       2, 1, 0),
1292 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1293                       1, 1, 0),
1294 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1295                       0, 1, 0),
1296 };
1297
1298 static const char *sidetone_text[] = {
1299         "ADC/DMIC1", "DMIC2",
1300 };
1301
1302 static const struct soc_enum sidetone1_enum =
1303         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1304
1305 static const struct snd_kcontrol_new sidetone1_mux =
1306         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1307
1308 static const struct soc_enum sidetone2_enum =
1309         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1310
1311 static const struct snd_kcontrol_new sidetone2_mux =
1312         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1313
1314 static const char *aif1dac_text[] = {
1315         "AIF1DACDAT", "AIF3DACDAT",
1316 };
1317
1318 static const struct soc_enum aif1dac_enum =
1319         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1320
1321 static const struct snd_kcontrol_new aif1dac_mux =
1322         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1323
1324 static const char *aif2dac_text[] = {
1325         "AIF2DACDAT", "AIF3DACDAT",
1326 };
1327
1328 static const struct soc_enum aif2dac_enum =
1329         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1330
1331 static const struct snd_kcontrol_new aif2dac_mux =
1332         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1333
1334 static const char *aif2adc_text[] = {
1335         "AIF2ADCDAT", "AIF3DACDAT",
1336 };
1337
1338 static const struct soc_enum aif2adc_enum =
1339         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1340
1341 static const struct snd_kcontrol_new aif2adc_mux =
1342         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1343
1344 static const char *aif3adc_text[] = {
1345         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1346 };
1347
1348 static const struct soc_enum wm8994_aif3adc_enum =
1349         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1350
1351 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1352         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1353
1354 static const struct soc_enum wm8958_aif3adc_enum =
1355         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1356
1357 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1358         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1359
1360 static const char *mono_pcm_out_text[] = {
1361         "None", "AIF2ADCL", "AIF2ADCR", 
1362 };
1363
1364 static const struct soc_enum mono_pcm_out_enum =
1365         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1366
1367 static const struct snd_kcontrol_new mono_pcm_out_mux =
1368         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1369
1370 static const char *aif2dac_src_text[] = {
1371         "AIF2", "AIF3",
1372 };
1373
1374 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1375 static const struct soc_enum aif2dacl_src_enum =
1376         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1377
1378 static const struct snd_kcontrol_new aif2dacl_src_mux =
1379         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1380
1381 static const struct soc_enum aif2dacr_src_enum =
1382         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1383
1384 static const struct snd_kcontrol_new aif2dacr_src_mux =
1385         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1386
1387 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1388 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1389         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1390 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1391         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1392
1393 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1394         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1395 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1396         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1397 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1398         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1399 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1400         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1401 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1402         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1403
1404 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1405                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1406                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1407 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1408                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1409                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1410 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1411                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1412 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1413                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1414
1415 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1416 };
1417
1418 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1419 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1420 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1421 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1422 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1423                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1424 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1425                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1426 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1427 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1428 };
1429
1430 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1431 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1432         dac_ev, SND_SOC_DAPM_PRE_PMU),
1433 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1434         dac_ev, SND_SOC_DAPM_PRE_PMU),
1435 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1436         dac_ev, SND_SOC_DAPM_PRE_PMU),
1437 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1438         dac_ev, SND_SOC_DAPM_PRE_PMU),
1439 };
1440
1441 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1442 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1443 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1444 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1445 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1446 };
1447
1448 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1449 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1450                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1451 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1452                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1453 };
1454
1455 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1456 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1457 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1458 };
1459
1460 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1461 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1462 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1463 SND_SOC_DAPM_INPUT("Clock"),
1464
1465 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1466                       SND_SOC_DAPM_PRE_PMU),
1467 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1468                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1469
1470 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1471                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1472
1473 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1474 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1475 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1476
1477 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1478                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1479 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1480                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1481 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1482                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1483                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1484 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1485                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1486                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1487
1488 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1489                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1490 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1491                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1492 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1493                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1494                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1495 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1496                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1497                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1498
1499 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1500                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1501 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1502                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1503
1504 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1505                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1506 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1507                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1508
1509 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1510                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1511 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1512                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1513
1514 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1515 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1516
1517 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1518                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1519 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1520                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1521
1522 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1523                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1524 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1525                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1526 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1527                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1528                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1529 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1530                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1531                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1532
1533 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1534 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1535 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1536 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1537
1538 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1539 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1540 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1541
1542 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1543 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1544
1545 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1546
1547 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1548 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1549 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1550 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1551
1552 /* Power is done with the muxes since the ADC power also controls the
1553  * downsampling chain, the chip will automatically manage the analogue
1554  * specific portions.
1555  */
1556 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1557 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1558
1559 SND_SOC_DAPM_POST("Debug log", post_ev),
1560 };
1561
1562 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1563 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1564 };
1565
1566 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1567 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1568 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1569 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1570 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1571 };
1572
1573 static const struct snd_soc_dapm_route intercon[] = {
1574         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1575         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1576
1577         { "DSP1CLK", NULL, "CLK_SYS" },
1578         { "DSP2CLK", NULL, "CLK_SYS" },
1579         { "DSPINTCLK", NULL, "CLK_SYS" },
1580
1581         { "AIF1ADC1L", NULL, "AIF1CLK" },
1582         { "AIF1ADC1L", NULL, "DSP1CLK" },
1583         { "AIF1ADC1R", NULL, "AIF1CLK" },
1584         { "AIF1ADC1R", NULL, "DSP1CLK" },
1585         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1586
1587         { "AIF1DAC1L", NULL, "AIF1CLK" },
1588         { "AIF1DAC1L", NULL, "DSP1CLK" },
1589         { "AIF1DAC1R", NULL, "AIF1CLK" },
1590         { "AIF1DAC1R", NULL, "DSP1CLK" },
1591         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1592
1593         { "AIF1ADC2L", NULL, "AIF1CLK" },
1594         { "AIF1ADC2L", NULL, "DSP1CLK" },
1595         { "AIF1ADC2R", NULL, "AIF1CLK" },
1596         { "AIF1ADC2R", NULL, "DSP1CLK" },
1597         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1598
1599         { "AIF1DAC2L", NULL, "AIF1CLK" },
1600         { "AIF1DAC2L", NULL, "DSP1CLK" },
1601         { "AIF1DAC2R", NULL, "AIF1CLK" },
1602         { "AIF1DAC2R", NULL, "DSP1CLK" },
1603         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1604
1605         { "AIF2ADCL", NULL, "AIF2CLK" },
1606         { "AIF2ADCL", NULL, "DSP2CLK" },
1607         { "AIF2ADCR", NULL, "AIF2CLK" },
1608         { "AIF2ADCR", NULL, "DSP2CLK" },
1609         { "AIF2ADCR", NULL, "DSPINTCLK" },
1610
1611         { "AIF2DACL", NULL, "AIF2CLK" },
1612         { "AIF2DACL", NULL, "DSP2CLK" },
1613         { "AIF2DACR", NULL, "AIF2CLK" },
1614         { "AIF2DACR", NULL, "DSP2CLK" },
1615         { "AIF2DACR", NULL, "DSPINTCLK" },
1616
1617         { "DMIC1L", NULL, "DMIC1DAT" },
1618         { "DMIC1L", NULL, "CLK_SYS" },
1619         { "DMIC1R", NULL, "DMIC1DAT" },
1620         { "DMIC1R", NULL, "CLK_SYS" },
1621         { "DMIC2L", NULL, "DMIC2DAT" },
1622         { "DMIC2L", NULL, "CLK_SYS" },
1623         { "DMIC2R", NULL, "DMIC2DAT" },
1624         { "DMIC2R", NULL, "CLK_SYS" },
1625
1626         { "ADCL", NULL, "AIF1CLK" },
1627         { "ADCL", NULL, "DSP1CLK" },
1628         { "ADCL", NULL, "DSPINTCLK" },
1629
1630         { "ADCR", NULL, "AIF1CLK" },
1631         { "ADCR", NULL, "DSP1CLK" },
1632         { "ADCR", NULL, "DSPINTCLK" },
1633
1634         { "ADCL Mux", "ADC", "ADCL" },
1635         { "ADCL Mux", "DMIC", "DMIC1L" },
1636         { "ADCR Mux", "ADC", "ADCR" },
1637         { "ADCR Mux", "DMIC", "DMIC1R" },
1638
1639         { "DAC1L", NULL, "AIF1CLK" },
1640         { "DAC1L", NULL, "DSP1CLK" },
1641         { "DAC1L", NULL, "DSPINTCLK" },
1642
1643         { "DAC1R", NULL, "AIF1CLK" },
1644         { "DAC1R", NULL, "DSP1CLK" },
1645         { "DAC1R", NULL, "DSPINTCLK" },
1646
1647         { "DAC2L", NULL, "AIF2CLK" },
1648         { "DAC2L", NULL, "DSP2CLK" },
1649         { "DAC2L", NULL, "DSPINTCLK" },
1650
1651         { "DAC2R", NULL, "AIF2DACR" },
1652         { "DAC2R", NULL, "AIF2CLK" },
1653         { "DAC2R", NULL, "DSP2CLK" },
1654         { "DAC2R", NULL, "DSPINTCLK" },
1655
1656         { "TOCLK", NULL, "CLK_SYS" },
1657
1658         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1659         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1660         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1661
1662         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1663         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1664         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1665
1666         /* AIF1 outputs */
1667         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1668         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1669         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1670
1671         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1672         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1673         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1674
1675         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1676         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1677         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1678
1679         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1680         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1681         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1682
1683         /* Pin level routing for AIF3 */
1684         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1685         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1686         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1687         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1688
1689         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1690         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1691         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1692         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1693         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1694         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1695         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1696
1697         /* DAC1 inputs */
1698         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1699         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1700         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1701         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1702         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1703
1704         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1705         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1706         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1707         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1708         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1709
1710         /* DAC2/AIF2 outputs  */
1711         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1712         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1713         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1714         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1715         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1716         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1717
1718         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1719         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1720         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1721         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1722         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1723         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1724
1725         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1726         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1727         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1728         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1729
1730         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1731
1732         /* AIF3 output */
1733         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1734         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1735         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1736         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1737         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1738         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1739         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1740         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1741
1742         /* Sidetone */
1743         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1744         { "Left Sidetone", "DMIC2", "DMIC2L" },
1745         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1746         { "Right Sidetone", "DMIC2", "DMIC2R" },
1747
1748         /* Output stages */
1749         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1750         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1751
1752         { "SPKL", "DAC1 Switch", "DAC1L" },
1753         { "SPKL", "DAC2 Switch", "DAC2L" },
1754
1755         { "SPKR", "DAC1 Switch", "DAC1R" },
1756         { "SPKR", "DAC2 Switch", "DAC2R" },
1757
1758         { "Left Headphone Mux", "DAC", "DAC1L" },
1759         { "Right Headphone Mux", "DAC", "DAC1R" },
1760 };
1761
1762 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1763         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1764         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1765         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1766         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1767         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1768         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1769         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1770         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1771 };
1772
1773 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1774         { "DAC1L", NULL, "DAC1L Mixer" },
1775         { "DAC1R", NULL, "DAC1R Mixer" },
1776         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1777         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1778 };
1779
1780 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1781         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1782         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1783         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1784         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1785         { "MICBIAS1", NULL, "CLK_SYS" },
1786         { "MICBIAS1", NULL, "MICBIAS Supply" },
1787         { "MICBIAS2", NULL, "CLK_SYS" },
1788         { "MICBIAS2", NULL, "MICBIAS Supply" },
1789 };
1790
1791 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1792         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1793         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1794         { "MICBIAS1", NULL, "VMID" },
1795         { "MICBIAS2", NULL, "VMID" },
1796 };
1797
1798 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1799         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1800         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1801
1802         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1803         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1804         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1805         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1806
1807         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1808         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1809
1810         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1811 };
1812
1813 /* The size in bits of the FLL divide multiplied by 10
1814  * to allow rounding later */
1815 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1816
1817 struct fll_div {
1818         u16 outdiv;
1819         u16 n;
1820         u16 k;
1821         u16 clk_ref_div;
1822         u16 fll_fratio;
1823 };
1824
1825 static int wm8994_get_fll_config(struct fll_div *fll,
1826                                  int freq_in, int freq_out)
1827 {
1828         u64 Kpart;
1829         unsigned int K, Ndiv, Nmod;
1830
1831         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1832
1833         /* Scale the input frequency down to <= 13.5MHz */
1834         fll->clk_ref_div = 0;
1835         while (freq_in > 13500000) {
1836                 fll->clk_ref_div++;
1837                 freq_in /= 2;
1838
1839                 if (fll->clk_ref_div > 3)
1840                         return -EINVAL;
1841         }
1842         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1843
1844         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1845         fll->outdiv = 3;
1846         while (freq_out * (fll->outdiv + 1) < 90000000) {
1847                 fll->outdiv++;
1848                 if (fll->outdiv > 63)
1849                         return -EINVAL;
1850         }
1851         freq_out *= fll->outdiv + 1;
1852         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1853
1854         if (freq_in > 1000000) {
1855                 fll->fll_fratio = 0;
1856         } else if (freq_in > 256000) {
1857                 fll->fll_fratio = 1;
1858                 freq_in *= 2;
1859         } else if (freq_in > 128000) {
1860                 fll->fll_fratio = 2;
1861                 freq_in *= 4;
1862         } else if (freq_in > 64000) {
1863                 fll->fll_fratio = 3;
1864                 freq_in *= 8;
1865         } else {
1866                 fll->fll_fratio = 4;
1867                 freq_in *= 16;
1868         }
1869         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1870
1871         /* Now, calculate N.K */
1872         Ndiv = freq_out / freq_in;
1873
1874         fll->n = Ndiv;
1875         Nmod = freq_out % freq_in;
1876         pr_debug("Nmod=%d\n", Nmod);
1877
1878         /* Calculate fractional part - scale up so we can round. */
1879         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1880
1881         do_div(Kpart, freq_in);
1882
1883         K = Kpart & 0xFFFFFFFF;
1884
1885         if ((K % 10) >= 5)
1886                 K += 5;
1887
1888         /* Move down to proper range now rounding is done */
1889         fll->k = K / 10;
1890
1891         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1892
1893         return 0;
1894 }
1895
1896 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1897                           unsigned int freq_in, unsigned int freq_out)
1898 {
1899         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1900         struct wm8994 *control = wm8994->wm8994;
1901         int reg_offset, ret;
1902         struct fll_div fll;
1903         u16 reg, aif1, aif2;
1904         unsigned long timeout;
1905         bool was_enabled;
1906
1907         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1908                 & WM8994_AIF1CLK_ENA;
1909
1910         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1911                 & WM8994_AIF2CLK_ENA;
1912
1913         switch (id) {
1914         case WM8994_FLL1:
1915                 reg_offset = 0;
1916                 id = 0;
1917                 break;
1918         case WM8994_FLL2:
1919                 reg_offset = 0x20;
1920                 id = 1;
1921                 break;
1922         default:
1923                 return -EINVAL;
1924         }
1925
1926         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1927         was_enabled = reg & WM8994_FLL1_ENA;
1928
1929         switch (src) {
1930         case 0:
1931                 /* Allow no source specification when stopping */
1932                 if (freq_out)
1933                         return -EINVAL;
1934                 src = wm8994->fll[id].src;
1935                 break;
1936         case WM8994_FLL_SRC_MCLK1:
1937         case WM8994_FLL_SRC_MCLK2:
1938         case WM8994_FLL_SRC_LRCLK:
1939         case WM8994_FLL_SRC_BCLK:
1940                 break;
1941         default:
1942                 return -EINVAL;
1943         }
1944
1945         /* Are we changing anything? */
1946         if (wm8994->fll[id].src == src &&
1947             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1948                 return 0;
1949
1950         /* If we're stopping the FLL redo the old config - no
1951          * registers will actually be written but we avoid GCC flow
1952          * analysis bugs spewing warnings.
1953          */
1954         if (freq_out)
1955                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1956         else
1957                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1958                                             wm8994->fll[id].out);
1959         if (ret < 0)
1960                 return ret;
1961
1962         /* Gate the AIF clocks while we reclock */
1963         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1964                             WM8994_AIF1CLK_ENA, 0);
1965         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1966                             WM8994_AIF2CLK_ENA, 0);
1967
1968         /* We always need to disable the FLL while reconfiguring */
1969         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1970                             WM8994_FLL1_ENA, 0);
1971
1972         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1973                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1974         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1975                             WM8994_FLL1_OUTDIV_MASK |
1976                             WM8994_FLL1_FRATIO_MASK, reg);
1977
1978         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1979                             WM8994_FLL1_K_MASK, fll.k);
1980
1981         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1982                             WM8994_FLL1_N_MASK,
1983                                     fll.n << WM8994_FLL1_N_SHIFT);
1984
1985         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1986                             WM8994_FLL1_REFCLK_DIV_MASK |
1987                             WM8994_FLL1_REFCLK_SRC_MASK,
1988                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1989                             (src - 1));
1990
1991         /* Clear any pending completion from a previous failure */
1992         try_wait_for_completion(&wm8994->fll_locked[id]);
1993
1994         /* Enable (with fractional mode if required) */
1995         if (freq_out) {
1996                 /* Enable VMID if we need it */
1997                 if (!was_enabled) {
1998                         active_reference(codec);
1999
2000                         switch (control->type) {
2001                         case WM8994:
2002                                 vmid_reference(codec);
2003                                 break;
2004                         case WM8958:
2005                                 if (wm8994->revision < 1)
2006                                         vmid_reference(codec);
2007                                 break;
2008                         default:
2009                                 break;
2010                         }
2011                 }
2012
2013                 if (fll.k)
2014                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2015                 else
2016                         reg = WM8994_FLL1_ENA;
2017                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2018                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2019                                     reg);
2020
2021                 if (wm8994->fll_locked_irq) {
2022                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2023                                                               msecs_to_jiffies(10));
2024                         if (timeout == 0)
2025                                 dev_warn(codec->dev,
2026                                          "Timed out waiting for FLL lock\n");
2027                 } else {
2028                         msleep(5);
2029                 }
2030         } else {
2031                 if (was_enabled) {
2032                         switch (control->type) {
2033                         case WM8994:
2034                                 vmid_dereference(codec);
2035                                 break;
2036                         case WM8958:
2037                                 if (wm8994->revision < 1)
2038                                         vmid_dereference(codec);
2039                                 break;
2040                         default:
2041                                 break;
2042                         }
2043
2044                         active_dereference(codec);
2045                 }
2046         }
2047
2048         wm8994->fll[id].in = freq_in;
2049         wm8994->fll[id].out = freq_out;
2050         wm8994->fll[id].src = src;
2051
2052         /* Enable any gated AIF clocks */
2053         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2054                             WM8994_AIF1CLK_ENA, aif1);
2055         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2056                             WM8994_AIF2CLK_ENA, aif2);
2057
2058         configure_clock(codec);
2059
2060         return 0;
2061 }
2062
2063 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2064 {
2065         struct completion *completion = data;
2066
2067         complete(completion);
2068
2069         return IRQ_HANDLED;
2070 }
2071
2072 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2073
2074 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2075                           unsigned int freq_in, unsigned int freq_out)
2076 {
2077         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2078 }
2079
2080 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2081                 int clk_id, unsigned int freq, int dir)
2082 {
2083         struct snd_soc_codec *codec = dai->codec;
2084         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2085         int i;
2086
2087         switch (dai->id) {
2088         case 1:
2089         case 2:
2090                 break;
2091
2092         default:
2093                 /* AIF3 shares clocking with AIF1/2 */
2094                 return -EINVAL;
2095         }
2096
2097         switch (clk_id) {
2098         case WM8994_SYSCLK_MCLK1:
2099                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2100                 wm8994->mclk[0] = freq;
2101                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2102                         dai->id, freq);
2103                 break;
2104
2105         case WM8994_SYSCLK_MCLK2:
2106                 /* TODO: Set GPIO AF */
2107                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2108                 wm8994->mclk[1] = freq;
2109                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2110                         dai->id, freq);
2111                 break;
2112
2113         case WM8994_SYSCLK_FLL1:
2114                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2115                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2116                 break;
2117
2118         case WM8994_SYSCLK_FLL2:
2119                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2120                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2121                 break;
2122
2123         case WM8994_SYSCLK_OPCLK:
2124                 /* Special case - a division (times 10) is given and
2125                  * no effect on main clocking. 
2126                  */
2127                 if (freq) {
2128                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2129                                 if (opclk_divs[i] == freq)
2130                                         break;
2131                         if (i == ARRAY_SIZE(opclk_divs))
2132                                 return -EINVAL;
2133                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2134                                             WM8994_OPCLK_DIV_MASK, i);
2135                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2136                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2137                 } else {
2138                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2139                                             WM8994_OPCLK_ENA, 0);
2140                 }
2141
2142         default:
2143                 return -EINVAL;
2144         }
2145
2146         configure_clock(codec);
2147
2148         return 0;
2149 }
2150
2151 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2152                                  enum snd_soc_bias_level level)
2153 {
2154         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2155         struct wm8994 *control = wm8994->wm8994;
2156
2157         wm_hubs_set_bias_level(codec, level);
2158
2159         switch (level) {
2160         case SND_SOC_BIAS_ON:
2161                 break;
2162
2163         case SND_SOC_BIAS_PREPARE:
2164                 /* MICBIAS into regulating mode */
2165                 switch (control->type) {
2166                 case WM8958:
2167                 case WM1811:
2168                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2169                                             WM8958_MICB1_MODE, 0);
2170                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2171                                             WM8958_MICB2_MODE, 0);
2172                         break;
2173                 default:
2174                         break;
2175                 }
2176
2177                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2178                         active_reference(codec);
2179                 break;
2180
2181         case SND_SOC_BIAS_STANDBY:
2182                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2183                         switch (control->type) {
2184                         case WM8994:
2185                                 if (wm8994->revision < 4) {
2186                                         /* Tweak DC servo and DSP
2187                                          * configuration for improved
2188                                          * performance. */
2189                                         snd_soc_write(codec, 0x102, 0x3);
2190                                         snd_soc_write(codec, 0x56, 0x3);
2191                                         snd_soc_write(codec, 0x817, 0);
2192                                         snd_soc_write(codec, 0x102, 0);
2193                                 }
2194                                 break;
2195
2196                         case WM8958:
2197                                 if (wm8994->revision == 0) {
2198                                         /* Optimise performance for rev A */
2199                                         snd_soc_write(codec, 0x102, 0x3);
2200                                         snd_soc_write(codec, 0xcb, 0x81);
2201                                         snd_soc_write(codec, 0x817, 0);
2202                                         snd_soc_write(codec, 0x102, 0);
2203
2204                                         snd_soc_update_bits(codec,
2205                                                             WM8958_CHARGE_PUMP_2,
2206                                                             WM8958_CP_DISCH,
2207                                                             WM8958_CP_DISCH);
2208                                 }
2209                                 break;
2210
2211                         case WM1811:
2212                                 if (wm8994->revision < 2) {
2213                                         snd_soc_write(codec, 0x102, 0x3);
2214                                         snd_soc_write(codec, 0x5d, 0x7e);
2215                                         snd_soc_write(codec, 0x5e, 0x0);
2216                                         snd_soc_write(codec, 0x102, 0x0);
2217                                 }
2218                                 break;
2219                         }
2220
2221                         /* Discharge LINEOUT1 & 2 */
2222                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2223                                             WM8994_LINEOUT1_DISCH |
2224                                             WM8994_LINEOUT2_DISCH,
2225                                             WM8994_LINEOUT1_DISCH |
2226                                             WM8994_LINEOUT2_DISCH);
2227                 }
2228
2229                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2230                         active_dereference(codec);
2231
2232                 /* MICBIAS into bypass mode on newer devices */
2233                 switch (control->type) {
2234                 case WM8958:
2235                 case WM1811:
2236                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2237                                             WM8958_MICB1_MODE,
2238                                             WM8958_MICB1_MODE);
2239                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2240                                             WM8958_MICB2_MODE,
2241                                             WM8958_MICB2_MODE);
2242                         break;
2243                 default:
2244                         break;
2245                 }
2246                 break;
2247
2248         case SND_SOC_BIAS_OFF:
2249                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2250                         wm8994->cur_fw = NULL;
2251                 break;
2252         }
2253
2254         codec->dapm.bias_level = level;
2255
2256         return 0;
2257 }
2258
2259 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2260 {
2261         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2262
2263         switch (mode) {
2264         case WM8994_VMID_NORMAL:
2265                 if (wm8994->hubs.lineout1_se) {
2266                         snd_soc_dapm_disable_pin(&codec->dapm,
2267                                                  "LINEOUT1N Driver");
2268                         snd_soc_dapm_disable_pin(&codec->dapm,
2269                                                  "LINEOUT1P Driver");
2270                 }
2271                 if (wm8994->hubs.lineout2_se) {
2272                         snd_soc_dapm_disable_pin(&codec->dapm,
2273                                                  "LINEOUT2N Driver");
2274                         snd_soc_dapm_disable_pin(&codec->dapm,
2275                                                  "LINEOUT2P Driver");
2276                 }
2277
2278                 /* Do the sync with the old mode to allow it to clean up */
2279                 snd_soc_dapm_sync(&codec->dapm);
2280                 wm8994->vmid_mode = mode;
2281                 break;
2282
2283         case WM8994_VMID_FORCE:
2284                 if (wm8994->hubs.lineout1_se) {
2285                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2286                                                       "LINEOUT1N Driver");
2287                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2288                                                       "LINEOUT1P Driver");
2289                 }
2290                 if (wm8994->hubs.lineout2_se) {
2291                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2292                                                       "LINEOUT2N Driver");
2293                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2294                                                       "LINEOUT2P Driver");
2295                 }
2296
2297                 wm8994->vmid_mode = mode;
2298                 snd_soc_dapm_sync(&codec->dapm);
2299                 break;
2300
2301         default:
2302                 return -EINVAL;
2303         }
2304
2305         return 0;
2306 }
2307
2308 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2309 {
2310         struct snd_soc_codec *codec = dai->codec;
2311         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2312         struct wm8994 *control = wm8994->wm8994;
2313         int ms_reg;
2314         int aif1_reg;
2315         int ms = 0;
2316         int aif1 = 0;
2317
2318         switch (dai->id) {
2319         case 1:
2320                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2321                 aif1_reg = WM8994_AIF1_CONTROL_1;
2322                 break;
2323         case 2:
2324                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2325                 aif1_reg = WM8994_AIF2_CONTROL_1;
2326                 break;
2327         default:
2328                 return -EINVAL;
2329         }
2330
2331         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2332         case SND_SOC_DAIFMT_CBS_CFS:
2333                 break;
2334         case SND_SOC_DAIFMT_CBM_CFM:
2335                 ms = WM8994_AIF1_MSTR;
2336                 break;
2337         default:
2338                 return -EINVAL;
2339         }
2340
2341         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2342         case SND_SOC_DAIFMT_DSP_B:
2343                 aif1 |= WM8994_AIF1_LRCLK_INV;
2344         case SND_SOC_DAIFMT_DSP_A:
2345                 aif1 |= 0x18;
2346                 break;
2347         case SND_SOC_DAIFMT_I2S:
2348                 aif1 |= 0x10;
2349                 break;
2350         case SND_SOC_DAIFMT_RIGHT_J:
2351                 break;
2352         case SND_SOC_DAIFMT_LEFT_J:
2353                 aif1 |= 0x8;
2354                 break;
2355         default:
2356                 return -EINVAL;
2357         }
2358
2359         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2360         case SND_SOC_DAIFMT_DSP_A:
2361         case SND_SOC_DAIFMT_DSP_B:
2362                 /* frame inversion not valid for DSP modes */
2363                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2364                 case SND_SOC_DAIFMT_NB_NF:
2365                         break;
2366                 case SND_SOC_DAIFMT_IB_NF:
2367                         aif1 |= WM8994_AIF1_BCLK_INV;
2368                         break;
2369                 default:
2370                         return -EINVAL;
2371                 }
2372                 break;
2373
2374         case SND_SOC_DAIFMT_I2S:
2375         case SND_SOC_DAIFMT_RIGHT_J:
2376         case SND_SOC_DAIFMT_LEFT_J:
2377                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2378                 case SND_SOC_DAIFMT_NB_NF:
2379                         break;
2380                 case SND_SOC_DAIFMT_IB_IF:
2381                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2382                         break;
2383                 case SND_SOC_DAIFMT_IB_NF:
2384                         aif1 |= WM8994_AIF1_BCLK_INV;
2385                         break;
2386                 case SND_SOC_DAIFMT_NB_IF:
2387                         aif1 |= WM8994_AIF1_LRCLK_INV;
2388                         break;
2389                 default:
2390                         return -EINVAL;
2391                 }
2392                 break;
2393         default:
2394                 return -EINVAL;
2395         }
2396
2397         /* The AIF2 format configuration needs to be mirrored to AIF3
2398          * on WM8958 if it's in use so just do it all the time. */
2399         switch (control->type) {
2400         case WM1811:
2401         case WM8958:
2402                 if (dai->id == 2)
2403                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2404                                             WM8994_AIF1_LRCLK_INV |
2405                                             WM8958_AIF3_FMT_MASK, aif1);
2406                 break;
2407
2408         default:
2409                 break;
2410         }
2411
2412         snd_soc_update_bits(codec, aif1_reg,
2413                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2414                             WM8994_AIF1_FMT_MASK,
2415                             aif1);
2416         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2417                             ms);
2418
2419         return 0;
2420 }
2421
2422 static struct {
2423         int val, rate;
2424 } srs[] = {
2425         { 0,   8000 },
2426         { 1,  11025 },
2427         { 2,  12000 },
2428         { 3,  16000 },
2429         { 4,  22050 },
2430         { 5,  24000 },
2431         { 6,  32000 },
2432         { 7,  44100 },
2433         { 8,  48000 },
2434         { 9,  88200 },
2435         { 10, 96000 },
2436 };
2437
2438 static int fs_ratios[] = {
2439         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2440 };
2441
2442 static int bclk_divs[] = {
2443         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2444         640, 880, 960, 1280, 1760, 1920
2445 };
2446
2447 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2448                             struct snd_pcm_hw_params *params,
2449                             struct snd_soc_dai *dai)
2450 {
2451         struct snd_soc_codec *codec = dai->codec;
2452         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2453         int aif1_reg;
2454         int aif2_reg;
2455         int bclk_reg;
2456         int lrclk_reg;
2457         int rate_reg;
2458         int aif1 = 0;
2459         int aif2 = 0;
2460         int bclk = 0;
2461         int lrclk = 0;
2462         int rate_val = 0;
2463         int id = dai->id - 1;
2464
2465         int i, cur_val, best_val, bclk_rate, best;
2466
2467         switch (dai->id) {
2468         case 1:
2469                 aif1_reg = WM8994_AIF1_CONTROL_1;
2470                 aif2_reg = WM8994_AIF1_CONTROL_2;
2471                 bclk_reg = WM8994_AIF1_BCLK;
2472                 rate_reg = WM8994_AIF1_RATE;
2473                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2474                     wm8994->lrclk_shared[0]) {
2475                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2476                 } else {
2477                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2478                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2479                 }
2480                 break;
2481         case 2:
2482                 aif1_reg = WM8994_AIF2_CONTROL_1;
2483                 aif2_reg = WM8994_AIF2_CONTROL_2;
2484                 bclk_reg = WM8994_AIF2_BCLK;
2485                 rate_reg = WM8994_AIF2_RATE;
2486                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2487                     wm8994->lrclk_shared[1]) {
2488                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2489                 } else {
2490                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2491                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2492                 }
2493                 break;
2494         default:
2495                 return -EINVAL;
2496         }
2497
2498         bclk_rate = params_rate(params) * 2;
2499         switch (params_format(params)) {
2500         case SNDRV_PCM_FORMAT_S16_LE:
2501                 bclk_rate *= 16;
2502                 break;
2503         case SNDRV_PCM_FORMAT_S20_3LE:
2504                 bclk_rate *= 20;
2505                 aif1 |= 0x20;
2506                 break;
2507         case SNDRV_PCM_FORMAT_S24_LE:
2508                 bclk_rate *= 24;
2509                 aif1 |= 0x40;
2510                 break;
2511         case SNDRV_PCM_FORMAT_S32_LE:
2512                 bclk_rate *= 32;
2513                 aif1 |= 0x60;
2514                 break;
2515         default:
2516                 return -EINVAL;
2517         }
2518
2519         /* Try to find an appropriate sample rate; look for an exact match. */
2520         for (i = 0; i < ARRAY_SIZE(srs); i++)
2521                 if (srs[i].rate == params_rate(params))
2522                         break;
2523         if (i == ARRAY_SIZE(srs))
2524                 return -EINVAL;
2525         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2526
2527         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2528         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2529                 dai->id, wm8994->aifclk[id], bclk_rate);
2530
2531         if (params_channels(params) == 1 &&
2532             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2533                 aif2 |= WM8994_AIF1_MONO;
2534
2535         if (wm8994->aifclk[id] == 0) {
2536                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2537                 return -EINVAL;
2538         }
2539
2540         /* AIFCLK/fs ratio; look for a close match in either direction */
2541         best = 0;
2542         best_val = abs((fs_ratios[0] * params_rate(params))
2543                        - wm8994->aifclk[id]);
2544         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2545                 cur_val = abs((fs_ratios[i] * params_rate(params))
2546                               - wm8994->aifclk[id]);
2547                 if (cur_val >= best_val)
2548                         continue;
2549                 best = i;
2550                 best_val = cur_val;
2551         }
2552         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2553                 dai->id, fs_ratios[best]);
2554         rate_val |= best;
2555
2556         /* We may not get quite the right frequency if using
2557          * approximate clocks so look for the closest match that is
2558          * higher than the target (we need to ensure that there enough
2559          * BCLKs to clock out the samples).
2560          */
2561         best = 0;
2562         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2563                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2564                 if (cur_val < 0) /* BCLK table is sorted */
2565                         break;
2566                 best = i;
2567         }
2568         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2569         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2570                 bclk_divs[best], bclk_rate);
2571         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2572
2573         lrclk = bclk_rate / params_rate(params);
2574         if (!lrclk) {
2575                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2576                         bclk_rate);
2577                 return -EINVAL;
2578         }
2579         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2580                 lrclk, bclk_rate / lrclk);
2581
2582         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2583         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2584         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2585         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2586                             lrclk);
2587         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2588                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2589
2590         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2591                 switch (dai->id) {
2592                 case 1:
2593                         wm8994->dac_rates[0] = params_rate(params);
2594                         wm8994_set_retune_mobile(codec, 0);
2595                         wm8994_set_retune_mobile(codec, 1);
2596                         break;
2597                 case 2:
2598                         wm8994->dac_rates[1] = params_rate(params);
2599                         wm8994_set_retune_mobile(codec, 2);
2600                         break;
2601                 }
2602         }
2603
2604         return 0;
2605 }
2606
2607 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2608                                  struct snd_pcm_hw_params *params,
2609                                  struct snd_soc_dai *dai)
2610 {
2611         struct snd_soc_codec *codec = dai->codec;
2612         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2613         struct wm8994 *control = wm8994->wm8994;
2614         int aif1_reg;
2615         int aif1 = 0;
2616
2617         switch (dai->id) {
2618         case 3:
2619                 switch (control->type) {
2620                 case WM1811:
2621                 case WM8958:
2622                         aif1_reg = WM8958_AIF3_CONTROL_1;
2623                         break;
2624                 default:
2625                         return 0;
2626                 }
2627         default:
2628                 return 0;
2629         }
2630
2631         switch (params_format(params)) {
2632         case SNDRV_PCM_FORMAT_S16_LE:
2633                 break;
2634         case SNDRV_PCM_FORMAT_S20_3LE:
2635                 aif1 |= 0x20;
2636                 break;
2637         case SNDRV_PCM_FORMAT_S24_LE:
2638                 aif1 |= 0x40;
2639                 break;
2640         case SNDRV_PCM_FORMAT_S32_LE:
2641                 aif1 |= 0x60;
2642                 break;
2643         default:
2644                 return -EINVAL;
2645         }
2646
2647         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2648 }
2649
2650 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2651                                 struct snd_soc_dai *dai)
2652 {
2653         struct snd_soc_codec *codec = dai->codec;
2654         int rate_reg = 0;
2655
2656         switch (dai->id) {
2657         case 1:
2658                 rate_reg = WM8994_AIF1_RATE;
2659                 break;
2660         case 2:
2661                 rate_reg = WM8994_AIF2_RATE;
2662                 break;
2663         default:
2664                 break;
2665         }
2666
2667         /* If the DAI is idle then configure the divider tree for the
2668          * lowest output rate to save a little power if the clock is
2669          * still active (eg, because it is system clock).
2670          */
2671         if (rate_reg && !dai->playback_active && !dai->capture_active)
2672                 snd_soc_update_bits(codec, rate_reg,
2673                                     WM8994_AIF1_SR_MASK |
2674                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2675 }
2676
2677 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2678 {
2679         struct snd_soc_codec *codec = codec_dai->codec;
2680         int mute_reg;
2681         int reg;
2682
2683         switch (codec_dai->id) {
2684         case 1:
2685                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2686                 break;
2687         case 2:
2688                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2689                 break;
2690         default:
2691                 return -EINVAL;
2692         }
2693
2694         if (mute)
2695                 reg = WM8994_AIF1DAC1_MUTE;
2696         else
2697                 reg = 0;
2698
2699         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2700
2701         return 0;
2702 }
2703
2704 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2705 {
2706         struct snd_soc_codec *codec = codec_dai->codec;
2707         int reg, val, mask;
2708
2709         switch (codec_dai->id) {
2710         case 1:
2711                 reg = WM8994_AIF1_MASTER_SLAVE;
2712                 mask = WM8994_AIF1_TRI;
2713                 break;
2714         case 2:
2715                 reg = WM8994_AIF2_MASTER_SLAVE;
2716                 mask = WM8994_AIF2_TRI;
2717                 break;
2718         case 3:
2719                 reg = WM8994_POWER_MANAGEMENT_6;
2720                 mask = WM8994_AIF3_TRI;
2721                 break;
2722         default:
2723                 return -EINVAL;
2724         }
2725
2726         if (tristate)
2727                 val = mask;
2728         else
2729                 val = 0;
2730
2731         return snd_soc_update_bits(codec, reg, mask, val);
2732 }
2733
2734 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2735 {
2736         struct snd_soc_codec *codec = dai->codec;
2737
2738         /* Disable the pulls on the AIF if we're using it to save power. */
2739         snd_soc_update_bits(codec, WM8994_GPIO_3,
2740                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2741         snd_soc_update_bits(codec, WM8994_GPIO_4,
2742                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2743         snd_soc_update_bits(codec, WM8994_GPIO_5,
2744                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2745
2746         return 0;
2747 }
2748
2749 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2750
2751 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2752                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2753
2754 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2755         .set_sysclk     = wm8994_set_dai_sysclk,
2756         .set_fmt        = wm8994_set_dai_fmt,
2757         .hw_params      = wm8994_hw_params,
2758         .shutdown       = wm8994_aif_shutdown,
2759         .digital_mute   = wm8994_aif_mute,
2760         .set_pll        = wm8994_set_fll,
2761         .set_tristate   = wm8994_set_tristate,
2762 };
2763
2764 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2765         .set_sysclk     = wm8994_set_dai_sysclk,
2766         .set_fmt        = wm8994_set_dai_fmt,
2767         .hw_params      = wm8994_hw_params,
2768         .shutdown       = wm8994_aif_shutdown,
2769         .digital_mute   = wm8994_aif_mute,
2770         .set_pll        = wm8994_set_fll,
2771         .set_tristate   = wm8994_set_tristate,
2772 };
2773
2774 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2775         .hw_params      = wm8994_aif3_hw_params,
2776         .set_tristate   = wm8994_set_tristate,
2777 };
2778
2779 static struct snd_soc_dai_driver wm8994_dai[] = {
2780         {
2781                 .name = "wm8994-aif1",
2782                 .id = 1,
2783                 .playback = {
2784                         .stream_name = "AIF1 Playback",
2785                         .channels_min = 1,
2786                         .channels_max = 2,
2787                         .rates = WM8994_RATES,
2788                         .formats = WM8994_FORMATS,
2789                         .sig_bits = 24,
2790                 },
2791                 .capture = {
2792                         .stream_name = "AIF1 Capture",
2793                         .channels_min = 1,
2794                         .channels_max = 2,
2795                         .rates = WM8994_RATES,
2796                         .formats = WM8994_FORMATS,
2797                         .sig_bits = 24,
2798                  },
2799                 .ops = &wm8994_aif1_dai_ops,
2800         },
2801         {
2802                 .name = "wm8994-aif2",
2803                 .id = 2,
2804                 .playback = {
2805                         .stream_name = "AIF2 Playback",
2806                         .channels_min = 1,
2807                         .channels_max = 2,
2808                         .rates = WM8994_RATES,
2809                         .formats = WM8994_FORMATS,
2810                         .sig_bits = 24,
2811                 },
2812                 .capture = {
2813                         .stream_name = "AIF2 Capture",
2814                         .channels_min = 1,
2815                         .channels_max = 2,
2816                         .rates = WM8994_RATES,
2817                         .formats = WM8994_FORMATS,
2818                         .sig_bits = 24,
2819                 },
2820                 .probe = wm8994_aif2_probe,
2821                 .ops = &wm8994_aif2_dai_ops,
2822         },
2823         {
2824                 .name = "wm8994-aif3",
2825                 .id = 3,
2826                 .playback = {
2827                         .stream_name = "AIF3 Playback",
2828                         .channels_min = 1,
2829                         .channels_max = 2,
2830                         .rates = WM8994_RATES,
2831                         .formats = WM8994_FORMATS,
2832                         .sig_bits = 24,
2833                 },
2834                 .capture = {
2835                         .stream_name = "AIF3 Capture",
2836                         .channels_min = 1,
2837                         .channels_max = 2,
2838                         .rates = WM8994_RATES,
2839                         .formats = WM8994_FORMATS,
2840                         .sig_bits = 24,
2841                  },
2842                 .ops = &wm8994_aif3_dai_ops,
2843         }
2844 };
2845
2846 #ifdef CONFIG_PM
2847 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2848 {
2849         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2850         struct wm8994 *control = wm8994->wm8994;
2851         int i, ret;
2852
2853         switch (control->type) {
2854         case WM8994:
2855                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2856                 break;
2857         case WM1811:
2858                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2859                                     WM1811_JACKDET_MODE_MASK, 0);
2860                 /* Fall through */
2861         case WM8958:
2862                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2863                                     WM8958_MICD_ENA, 0);
2864                 break;
2865         }
2866
2867         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2868                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2869                        sizeof(struct wm8994_fll_config));
2870                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2871                 if (ret < 0)
2872                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2873                                  i + 1, ret);
2874         }
2875
2876         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2877
2878         return 0;
2879 }
2880
2881 static int wm8994_codec_resume(struct snd_soc_codec *codec)
2882 {
2883         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2884         struct wm8994 *control = wm8994->wm8994;
2885         int i, ret;
2886         unsigned int val, mask;
2887
2888         if (wm8994->revision < 4) {
2889                 /* force a HW read */
2890                 ret = regmap_read(control->regmap,
2891                                   WM8994_POWER_MANAGEMENT_5, &val);
2892
2893                 /* modify the cache only */
2894                 codec->cache_only = 1;
2895                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2896                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2897                 val &= mask;
2898                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2899                                     mask, val);
2900                 codec->cache_only = 0;
2901         }
2902
2903         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2904                 if (!wm8994->fll_suspend[i].out)
2905                         continue;
2906
2907                 ret = _wm8994_set_fll(codec, i + 1,
2908                                      wm8994->fll_suspend[i].src,
2909                                      wm8994->fll_suspend[i].in,
2910                                      wm8994->fll_suspend[i].out);
2911                 if (ret < 0)
2912                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2913                                  i + 1, ret);
2914         }
2915
2916         switch (control->type) {
2917         case WM8994:
2918                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2919                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2920                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2921                 break;
2922         case WM1811:
2923                 if (wm8994->jackdet && wm8994->jack_cb) {
2924                         /* Restart from idle */
2925                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2926                                             WM1811_JACKDET_MODE_MASK,
2927                                             WM1811_JACKDET_MODE_JACK);
2928                         break;
2929                 }
2930                 break;
2931         case WM8958:
2932                 if (wm8994->jack_cb)
2933                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2934                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2935                 break;
2936         }
2937
2938         return 0;
2939 }
2940 #else
2941 #define wm8994_codec_suspend NULL
2942 #define wm8994_codec_resume NULL
2943 #endif
2944
2945 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2946 {
2947         struct snd_soc_codec *codec = wm8994->codec;
2948         struct wm8994_pdata *pdata = wm8994->pdata;
2949         struct snd_kcontrol_new controls[] = {
2950                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2951                              wm8994->retune_mobile_enum,
2952                              wm8994_get_retune_mobile_enum,
2953                              wm8994_put_retune_mobile_enum),
2954                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2955                              wm8994->retune_mobile_enum,
2956                              wm8994_get_retune_mobile_enum,
2957                              wm8994_put_retune_mobile_enum),
2958                 SOC_ENUM_EXT("AIF2 EQ Mode",
2959                              wm8994->retune_mobile_enum,
2960                              wm8994_get_retune_mobile_enum,
2961                              wm8994_put_retune_mobile_enum),
2962         };
2963         int ret, i, j;
2964         const char **t;
2965
2966         /* We need an array of texts for the enum API but the number
2967          * of texts is likely to be less than the number of
2968          * configurations due to the sample rate dependency of the
2969          * configurations. */
2970         wm8994->num_retune_mobile_texts = 0;
2971         wm8994->retune_mobile_texts = NULL;
2972         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2973                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2974                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2975                                    wm8994->retune_mobile_texts[j]) == 0)
2976                                 break;
2977                 }
2978
2979                 if (j != wm8994->num_retune_mobile_texts)
2980                         continue;
2981
2982                 /* Expand the array... */
2983                 t = krealloc(wm8994->retune_mobile_texts,
2984                              sizeof(char *) * 
2985                              (wm8994->num_retune_mobile_texts + 1),
2986                              GFP_KERNEL);
2987                 if (t == NULL)
2988                         continue;
2989
2990                 /* ...store the new entry... */
2991                 t[wm8994->num_retune_mobile_texts] = 
2992                         pdata->retune_mobile_cfgs[i].name;
2993
2994                 /* ...and remember the new version. */
2995                 wm8994->num_retune_mobile_texts++;
2996                 wm8994->retune_mobile_texts = t;
2997         }
2998
2999         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3000                 wm8994->num_retune_mobile_texts);
3001
3002         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3003         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3004
3005         ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3006                                    ARRAY_SIZE(controls));
3007         if (ret != 0)
3008                 dev_err(wm8994->codec->dev,
3009                         "Failed to add ReTune Mobile controls: %d\n", ret);
3010 }
3011
3012 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3013 {
3014         struct snd_soc_codec *codec = wm8994->codec;
3015         struct wm8994_pdata *pdata = wm8994->pdata;
3016         int ret, i;
3017
3018         if (!pdata)
3019                 return;
3020
3021         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3022                                       pdata->lineout2_diff,
3023                                       pdata->lineout1fb,
3024                                       pdata->lineout2fb,
3025                                       pdata->jd_scthr,
3026                                       pdata->jd_thr,
3027                                       pdata->micbias1_lvl,
3028                                       pdata->micbias2_lvl);
3029
3030         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3031
3032         if (pdata->num_drc_cfgs) {
3033                 struct snd_kcontrol_new controls[] = {
3034                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3035                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3036                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3037                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3038                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3039                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3040                 };
3041
3042                 /* We need an array of texts for the enum API */
3043                 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3044                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3045                 if (!wm8994->drc_texts) {
3046                         dev_err(wm8994->codec->dev,
3047                                 "Failed to allocate %d DRC config texts\n",
3048                                 pdata->num_drc_cfgs);
3049                         return;
3050                 }
3051
3052                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3053                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3054
3055                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3056                 wm8994->drc_enum.texts = wm8994->drc_texts;
3057
3058                 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3059                                            ARRAY_SIZE(controls));
3060                 if (ret != 0)
3061                         dev_err(wm8994->codec->dev,
3062                                 "Failed to add DRC mode controls: %d\n", ret);
3063
3064                 for (i = 0; i < WM8994_NUM_DRC; i++)
3065                         wm8994_set_drc(codec, i);
3066         }
3067
3068         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3069                 pdata->num_retune_mobile_cfgs);
3070
3071         if (pdata->num_retune_mobile_cfgs)
3072                 wm8994_handle_retune_mobile_pdata(wm8994);
3073         else
3074                 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
3075                                      ARRAY_SIZE(wm8994_eq_controls));
3076
3077         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3078                 if (pdata->micbias[i]) {
3079                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3080                                 pdata->micbias[i] & 0xffff);
3081                 }
3082         }
3083 }
3084
3085 /**
3086  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3087  *
3088  * @codec:   WM8994 codec
3089  * @jack:    jack to report detection events on
3090  * @micbias: microphone bias to detect on
3091  *
3092  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3093  * being used to bring out signals to the processor then only platform
3094  * data configuration is needed for WM8994 and processor GPIOs should
3095  * be configured using snd_soc_jack_add_gpios() instead.
3096  *
3097  * Configuration of detection levels is available via the micbias1_lvl
3098  * and micbias2_lvl platform data members.
3099  */
3100 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3101                       int micbias)
3102 {
3103         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3104         struct wm8994_micdet *micdet;
3105         struct wm8994 *control = wm8994->wm8994;
3106         int reg, ret;
3107
3108         if (control->type != WM8994) {
3109                 dev_warn(codec->dev, "Not a WM8994\n");
3110                 return -EINVAL;
3111         }
3112
3113         switch (micbias) {
3114         case 1:
3115                 micdet = &wm8994->micdet[0];
3116                 if (jack)
3117                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3118                                                             "MICBIAS1");
3119                 else
3120                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3121                                                        "MICBIAS1");
3122                 break;
3123         case 2:
3124                 micdet = &wm8994->micdet[1];
3125                 if (jack)
3126                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3127                                                             "MICBIAS1");
3128                 else
3129                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3130                                                        "MICBIAS1");
3131                 break;
3132         default:
3133                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3134                 return -EINVAL;
3135         }
3136
3137         if (ret != 0)
3138                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3139                          micbias, ret);
3140
3141         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3142                 micbias, jack);
3143
3144         /* Store the configuration */
3145         micdet->jack = jack;
3146         micdet->detecting = true;
3147
3148         /* If either of the jacks is set up then enable detection */
3149         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3150                 reg = WM8994_MICD_ENA;
3151         else
3152                 reg = 0;
3153
3154         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3155
3156         snd_soc_dapm_sync(&codec->dapm);
3157
3158         return 0;
3159 }
3160 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3161
3162 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3163 {
3164         struct wm8994_priv *priv = data;
3165         struct snd_soc_codec *codec = priv->codec;
3166         int reg;
3167         int report;
3168
3169 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3170         trace_snd_soc_jack_irq(dev_name(codec->dev));
3171 #endif
3172
3173         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3174         if (reg < 0) {
3175                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3176                         reg);
3177                 return IRQ_HANDLED;
3178         }
3179
3180         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3181
3182         report = 0;
3183         if (reg & WM8994_MIC1_DET_STS) {
3184                 if (priv->micdet[0].detecting)
3185                         report = SND_JACK_HEADSET;
3186         }
3187         if (reg & WM8994_MIC1_SHRT_STS) {
3188                 if (priv->micdet[0].detecting)
3189                         report = SND_JACK_HEADPHONE;
3190                 else
3191                         report |= SND_JACK_BTN_0;
3192         }
3193         if (report)
3194                 priv->micdet[0].detecting = false;
3195         else
3196                 priv->micdet[0].detecting = true;
3197
3198         snd_soc_jack_report(priv->micdet[0].jack, report,
3199                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3200
3201         report = 0;
3202         if (reg & WM8994_MIC2_DET_STS) {
3203                 if (priv->micdet[1].detecting)
3204                         report = SND_JACK_HEADSET;
3205         }
3206         if (reg & WM8994_MIC2_SHRT_STS) {
3207                 if (priv->micdet[1].detecting)
3208                         report = SND_JACK_HEADPHONE;
3209                 else
3210                         report |= SND_JACK_BTN_0;
3211         }
3212         if (report)
3213                 priv->micdet[1].detecting = false;
3214         else
3215                 priv->micdet[1].detecting = true;
3216
3217         snd_soc_jack_report(priv->micdet[1].jack, report,
3218                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3219
3220         return IRQ_HANDLED;
3221 }
3222
3223 /* Default microphone detection handler for WM8958 - the user can
3224  * override this if they wish.
3225  */
3226 static void wm8958_default_micdet(u16 status, void *data)
3227 {
3228         struct snd_soc_codec *codec = data;
3229         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3230         int report;
3231
3232         dev_dbg(codec->dev, "MICDET %x\n", status);
3233
3234         /* Either nothing present or just starting detection */
3235         if (!(status & WM8958_MICD_STS)) {
3236                 if (!wm8994->jackdet) {
3237                         /* If nothing present then clear our statuses */
3238                         dev_dbg(codec->dev, "Detected open circuit\n");
3239                         wm8994->jack_mic = false;
3240                         wm8994->mic_detecting = true;
3241
3242                         wm8958_micd_set_rate(codec);
3243
3244                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3245                                             wm8994->btn_mask |
3246                                              SND_JACK_HEADSET);
3247                 }
3248              &nb