.script_addrs = &imx53_sdma_script,
};
+static const struct resource imx50_audmux_res[] __initconst = {
+ DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
+static const struct resource imx51_audmux_res[] __initconst = {
+ DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
+static const struct resource imx53_audmux_res[] __initconst = {
+ DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
void __init imx50_soc_init(void)
{
/* i.mx50 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+
+ /* i.mx50 has the i.mx31 type audmux */
+ platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
+ ARRAY_SIZE(imx50_audmux_res));
}
void __init imx51_soc_init(void)
/* Setup AIPS registers */
imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
+
+ /* i.mx51 has the i.mx31 type audmux */
+ platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
+ ARRAY_SIZE(imx51_audmux_res));
}
void __init imx53_soc_init(void)
/* Setup AIPS registers */
imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
+
+ /* i.mx53 has the i.mx31 type audmux */
+ platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
+ ARRAY_SIZE(imx53_audmux_res));
}