Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[~shefty/rdma-dev.git] / drivers / net / wireless / ath / ath9k / mac.c
index c996963ab33927c027f3fb019200261c0ac07d18..e3d2ebf00e2ed58b1c67540bdb28023f4c25958f 100644 (file)
 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
                                        struct ath9k_tx_queue_info *qi)
 {
-       ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
-                 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
-                 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
-                 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
-                 ah->txurn_interrupt_mask);
+       ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
+               "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
+               ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
+               ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
+               ah->txurn_interrupt_mask);
 
        ENABLE_REGWRITE_BUFFER(ah);
 
@@ -56,8 +56,8 @@ EXPORT_SYMBOL(ath9k_hw_puttxbuf);
 
 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
 {
-       ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
-                 "Enable TXE on queue: %u\n", q);
+       ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
+               "Enable TXE on queue: %u\n", q);
        REG_WRITE(ah, AR_Q_TXE, 1 << q);
 }
 EXPORT_SYMBOL(ath9k_hw_txstart);
@@ -117,12 +117,11 @@ EXPORT_SYMBOL(ath9k_hw_numtxpending);
 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
 {
        u32 txcfg, curLevel, newLevel;
-       enum ath9k_int omask;
 
        if (ah->tx_trig_level >= ah->config.max_txtrig_level)
                return false;
 
-       omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
+       ath9k_hw_disable_interrupts(ah);
 
        txcfg = REG_READ(ah, AR_TXCFG);
        curLevel = MS(txcfg, AR_FTRIG);
@@ -136,7 +135,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
                REG_WRITE(ah, AR_TXCFG,
                          (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
 
-       ath9k_hw_set_interrupts(ah, omask);
+       ath9k_hw_enable_interrupts(ah);
 
        ah->tx_trig_level = newLevel;
 
@@ -155,15 +154,15 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
        u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
 
        if (q >= pCap->total_queues) {
-               ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
-                         "invalid queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Stopping TX DMA, invalid queue: %u\n", q);
                return false;
        }
 
        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-               ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
-                         "inactive queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Stopping TX DMA, inactive queue: %u\n", q);
                return false;
        }
 
@@ -176,9 +175,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
        }
 
        if (ath9k_hw_numtxpending(ah, q)) {
-               ath_print(common, ATH_DBG_QUEUE,
-                         "%s: Num of pending TX Frames %d on Q %d\n",
-                         __func__, ath9k_hw_numtxpending(ah, q), q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "%s: Num of pending TX Frames %d on Q %d\n",
+                       __func__, ath9k_hw_numtxpending(ah, q), q);
 
                for (j = 0; j < 2; j++) {
                        tsfLow = REG_READ(ah, AR_TSF_L32);
@@ -192,9 +191,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
                        if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
                                break;
 
-                       ath_print(common, ATH_DBG_QUEUE,
-                                 "TSF has moved while trying to set "
-                                 "quiet time TSF: 0x%08x\n", tsfLow);
+                       ath_dbg(common, ATH_DBG_QUEUE,
+                               "TSF has moved while trying to set quiet time TSF: 0x%08x\n",
+                               tsfLow);
                }
 
                REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
@@ -205,9 +204,8 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
                wait = wait_time;
                while (ath9k_hw_numtxpending(ah, q)) {
                        if ((--wait) == 0) {
-                               ath_print(common, ATH_DBG_FATAL,
-                                         "Failed to stop TX DMA in 100 "
-                                         "msec after killing last frame\n");
+                               ath_err(common,
+                                       "Failed to stop TX DMA in 100 msec after killing last frame\n");
                                break;
                        }
                        udelay(ATH9K_TIME_QUANTUM);
@@ -240,19 +238,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
        struct ath9k_tx_queue_info *qi;
 
        if (q >= pCap->total_queues) {
-               ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
-                         "invalid queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Set TXQ properties, invalid queue: %u\n", q);
                return false;
        }
 
        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-               ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
-                         "inactive queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Set TXQ properties, inactive queue: %u\n", q);
                return false;
        }
 
-       ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
+       ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
 
        qi->tqi_ver = qinfo->tqi_ver;
        qi->tqi_subtype = qinfo->tqi_subtype;
@@ -311,15 +309,15 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
        struct ath9k_tx_queue_info *qi;
 
        if (q >= pCap->total_queues) {
-               ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
-                         "invalid queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Get TXQ properties, invalid queue: %u\n", q);
                return false;
        }
 
        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-               ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
-                         "inactive queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Get TXQ properties, inactive queue: %u\n", q);
                return false;
        }
 
@@ -369,23 +367,20 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
                            ATH9K_TX_QUEUE_INACTIVE)
                                break;
                if (q == pCap->total_queues) {
-                       ath_print(common, ATH_DBG_FATAL,
-                                 "No available TX queue\n");
+                       ath_err(common, "No available TX queue\n");
                        return -1;
                }
                break;
        default:
-               ath_print(common, ATH_DBG_FATAL,
-                         "Invalid TX queue type: %u\n", type);
+               ath_err(common, "Invalid TX queue type: %u\n", type);
                return -1;
        }
 
-       ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
+       ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
 
        qi = &ah->txq[q];
        if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
-               ath_print(common, ATH_DBG_FATAL,
-                         "TX queue: %u already active\n", q);
+               ath_err(common, "TX queue: %u already active\n", q);
                return -1;
        }
        memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -417,18 +412,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
        struct ath9k_tx_queue_info *qi;
 
        if (q >= pCap->total_queues) {
-               ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
-                         "invalid queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Release TXQ, invalid queue: %u\n", q);
                return false;
        }
        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-               ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
-                         "inactive queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Release TXQ, inactive queue: %u\n", q);
                return false;
        }
 
-       ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
+       ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
 
        qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
        ah->txok_interrupt_mask &= ~(1 << q);
@@ -451,19 +446,19 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
        u32 cwMin, chanCwMin, value;
 
        if (q >= pCap->total_queues) {
-               ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
-                         "invalid queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Reset TXQ, invalid queue: %u\n", q);
                return false;
        }
 
        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-               ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
-                         "inactive queue: %u\n", q);
+               ath_dbg(common, ATH_DBG_QUEUE,
+                       "Reset TXQ, inactive queue: %u\n", q);
                return true;
        }
 
-       ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
+       ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
 
        if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
                if (chan && IS_CHAN_B(chan))
@@ -735,9 +730,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
                                     AR_DIAG_RX_ABORT));
 
                        reg = REG_READ(ah, AR_OBS_BUS_1);
-                       ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                 "RX failed to go idle in 10 ms RXSM=0x%x\n",
-                                 reg);
+                       ath_err(ath9k_hw_common(ah),
+                               "RX failed to go idle in 10 ms RXSM=0x%x\n",
+                               reg);
 
                        return false;
                }
@@ -766,14 +761,6 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
 }
 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
 
-void ath9k_hw_stoppcurecv(struct ath_hw *ah)
-{
-       REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
-
-       ath9k_hw_disable_mib_counters(ah);
-}
-EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
-
 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
 {
        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
@@ -799,12 +786,11 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
        }
 
        if (i == 0) {
-               ath_print(common, ATH_DBG_FATAL,
-                         "DMA failed to stop in %d ms "
-                         "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
-                         AH_RX_STOP_DMA_TIMEOUT / 1000,
-                         REG_READ(ah, AR_CR),
-                         REG_READ(ah, AR_DIAG_SW));
+               ath_err(common,
+                       "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
+                       AH_RX_STOP_DMA_TIMEOUT / 1000,
+                       REG_READ(ah, AR_CR),
+                       REG_READ(ah, AR_DIAG_SW));
                return false;
        } else {
                return true;
@@ -848,28 +834,59 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_intrpend);
 
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
-                                             enum ath9k_int ints)
+void ath9k_hw_disable_interrupts(struct ath_hw *ah)
+{
+       struct ath_common *common = ath9k_hw_common(ah);
+
+       ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
+       REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+       (void) REG_READ(ah, AR_IER);
+       if (!AR_SREV_9100(ah)) {
+               REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
+               (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+
+               REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+               (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
+       }
+}
+EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
+
+void ath9k_hw_enable_interrupts(struct ath_hw *ah)
+{
+       struct ath_common *common = ath9k_hw_common(ah);
+
+       if (!(ah->imask & ATH9K_INT_GLOBAL))
+               return;
+
+       ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
+       REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+       if (!AR_SREV_9100(ah)) {
+               REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
+                         AR_INTR_MAC_IRQ);
+               REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+
+
+               REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
+                         AR_INTR_SYNC_DEFAULT);
+               REG_WRITE(ah, AR_INTR_SYNC_MASK,
+                         AR_INTR_SYNC_DEFAULT);
+       }
+       ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+               REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
+}
+EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
+
+void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
 {
        enum ath9k_int omask = ah->imask;
        u32 mask, mask2;
        struct ath9k_hw_capabilities *pCap = &ah->caps;
        struct ath_common *common = ath9k_hw_common(ah);
 
-       ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
+       if (!(ints & ATH9K_INT_GLOBAL))
+               ath9k_hw_enable_interrupts(ah);
 
-       if (omask & ATH9K_INT_GLOBAL) {
-               ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
-               REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
-               (void) REG_READ(ah, AR_IER);
-               if (!AR_SREV_9100(ah)) {
-                       REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
-                       (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
-
-                       REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
-                       (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
-               }
-       }
+       ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
 
        /* TODO: global int Ref count */
        mask = ints & ATH9K_INT_COMMON;
@@ -930,7 +947,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                        mask2 |= AR_IMR_S2_CST;
        }
 
-       ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
+       ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
        REG_WRITE(ah, AR_IMR, mask);
        ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
                           AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
@@ -945,24 +962,8 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                        REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
        }
 
-       if (ints & ATH9K_INT_GLOBAL) {
-               ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
-               REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
-               if (!AR_SREV_9100(ah)) {
-                       REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
-                                 AR_INTR_MAC_IRQ);
-                       REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
-
-
-                       REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
-                                 AR_INTR_SYNC_DEFAULT);
-                       REG_WRITE(ah, AR_INTR_SYNC_MASK,
-                                 AR_INTR_SYNC_DEFAULT);
-               }
-               ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
-                         REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
-       }
+       ath9k_hw_enable_interrupts(ah);
 
-       return omask;
+       return;
 }
 EXPORT_SYMBOL(ath9k_hw_set_interrupts);