Merge branch 'common/dma' into rmobile-latest
authorPaul Mundt <lethal@linux-sh.org>
Fri, 7 Jan 2011 02:03:37 +0000 (11:03 +0900)
committerPaul Mundt <lethal@linux-sh.org>
Fri, 7 Jan 2011 02:03:37 +0000 (11:03 +0900)
39 files changed:
.mailmap
arch/arm/Kconfig
arch/arm/configs/ag5evm_defconfig [new file with mode: 0644]
arch/arm/configs/mackerel_defconfig [new file with mode: 0644]
arch/arm/mach-shmobile/Kconfig
arch/arm/mach-shmobile/Makefile
arch/arm/mach-shmobile/board-ag5evm.c [new file with mode: 0644]
arch/arm/mach-shmobile/board-ap4evb.c
arch/arm/mach-shmobile/board-g3evm.c
arch/arm/mach-shmobile/board-g4evm.c
arch/arm/mach-shmobile/board-mackerel.c [new file with mode: 0644]
arch/arm/mach-shmobile/clock-sh73a0.c [new file with mode: 0644]
arch/arm/mach-shmobile/entry-gic.S [new file with mode: 0644]
arch/arm/mach-shmobile/entry-intc.S [new file with mode: 0644]
arch/arm/mach-shmobile/headsmp.S [new file with mode: 0644]
arch/arm/mach-shmobile/hotplug.c [new file with mode: 0644]
arch/arm/mach-shmobile/include/mach/common.h
arch/arm/mach-shmobile/include/mach/entry-macro.S
arch/arm/mach-shmobile/include/mach/hardware.h
arch/arm/mach-shmobile/include/mach/head-mackerel.txt [new file with mode: 0644]
arch/arm/mach-shmobile/include/mach/irqs.h
arch/arm/mach-shmobile/include/mach/sh7372.h
arch/arm/mach-shmobile/include/mach/sh73a0.h [new file with mode: 0644]
arch/arm/mach-shmobile/include/mach/smp.h [new file with mode: 0644]
arch/arm/mach-shmobile/include/mach/zboot.h
arch/arm/mach-shmobile/intc-sh73a0.c [new file with mode: 0644]
arch/arm/mach-shmobile/localtimer.c [new file with mode: 0644]
arch/arm/mach-shmobile/pfc-sh73a0.c [new file with mode: 0644]
arch/arm/mach-shmobile/platsmp.c [new file with mode: 0644]
arch/arm/mach-shmobile/setup-sh7372.c
arch/arm/mach-shmobile/setup-sh73a0.c [new file with mode: 0644]
arch/arm/mach-shmobile/smp-sh73a0.c [new file with mode: 0644]
arch/arm/mm/Kconfig
arch/sh/include/mach-common/mach/romimage.h
arch/sh/include/mach-ecovec24/mach/romimage.h
arch/sh/include/mach-kfr2r09/mach/romimage.h
drivers/mmc/host/sh_mmcif.c
drivers/serial/sh-sci.h
include/linux/mmc/sh_mmcif.h

index a62e6a84fd1e6fadb21e823a788f41ac00a5d9a0..581fd39193a26d2932c696d21f0b78c28f4bdc92 100644 (file)
--- a/.mailmap
+++ b/.mailmap
@@ -105,3 +105,4 @@ Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
 Uwe Kleine-König <ukl@pengutronix.de>
 Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
 Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
+Takashi YOSHII <takashi.yoshii.zj@renesas.com>
index a3fb23be87f3100daf1c5fa9800c756e7cb2821b..e2f801167593e3fd7428ae38eb634eaeadcde225 100644 (file)
@@ -632,9 +632,15 @@ config ARCH_MSM
          (clock and power control, etc).
 
 config ARCH_SHMOBILE
-       bool "Renesas SH-Mobile"
+       bool "Renesas SH-Mobile / R-Mobile"
+       select HAVE_CLK
+       select CLKDEV_LOOKUP
+       select GENERIC_CLOCKEVENTS
+       select NO_IOPORT
+       select SPARSE_IRQ
+       select MULTI_IRQ_HANDLER
        help
-         Support for Renesas's SH-Mobile ARM platforms
+         Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 
 config ARCH_RPC
        bool "RiscPC"
@@ -1252,7 +1258,7 @@ config SMP
        depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
                 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
-                ARCH_MSM_SCORPIONMP
+                ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
        select USE_GENERIC_SMP_HELPERS
        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
        help
diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig
new file mode 100644 (file)
index 0000000..2b9cf56
--- /dev/null
@@ -0,0 +1,83 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SH73A0=y
+CONFIG_MACH_AG5EVM=y
+CONFIG_MEMORY_SIZE=0x10000000
+CONFIG_CPU_BPREDICT_DISABLE=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_458693=y
+CONFIG_NO_HZ=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=tty0 console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM=y
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_SPARSEKMAP=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
new file mode 100644 (file)
index 0000000..306a2e2
--- /dev/null
@@ -0,0 +1,138 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SH7372=y
+CONFIG_MACH_MACKEREL=y
+CONFIG_MEMORY_SIZE=0x10000000
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_FORCE_MAX_ZONEORDER=15
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp memchunk.vpu=64m memchunk.veu0=8m memchunk.spu0=2m mem=240m"
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=8
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
index 6329333572427ec97d1c168aeca2e76c896f965c..4d1b4c5c938931065166555dffa9f5b7779f7cfe 100644 (file)
@@ -5,26 +5,27 @@ comment "SH-Mobile System Type"
 config ARCH_SH7367
        bool "SH-Mobile G3 (SH7367)"
        select CPU_V6
-       select HAVE_CLK
-       select CLKDEV_LOOKUP
        select SH_CLK_CPG
-       select GENERIC_CLOCKEVENTS
+       select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config ARCH_SH7377
        bool "SH-Mobile G4 (SH7377)"
        select CPU_V7
-       select HAVE_CLK
-       select CLKDEV_LOOKUP
        select SH_CLK_CPG
-       select GENERIC_CLOCKEVENTS
+       select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config ARCH_SH7372
        bool "SH-Mobile AP4 (SH7372)"
        select CPU_V7
-       select HAVE_CLK
-       select CLKDEV_LOOKUP
        select SH_CLK_CPG
-       select GENERIC_CLOCKEVENTS
+       select ARCH_WANT_OPTIONAL_GPIOLIB
+
+config ARCH_SH73A0
+       bool "SH-Mobile AG5 (R8A73A00)"
+       select CPU_V7
+       select SH_CLK_CPG
+       select ARCH_WANT_OPTIONAL_GPIOLIB
+       select ARM_GIC
 
 comment "SH-Mobile Board Type"
 
@@ -57,6 +58,15 @@ config AP4EVB_WVGA
 
 endchoice
 
+config MACH_AG5EVM
+       bool "AG5EVM board"
+       depends on ARCH_SH73A0
+
+config MACH_MACKEREL
+       bool "mackerel board"
+       depends on ARCH_SH7372
+       select ARCH_REQUIRE_GPIOLIB
+
 comment "SH-Mobile System Configuration"
 
 menu "Memory configuration"
@@ -64,8 +74,8 @@ menu "Memory configuration"
 config MEMORY_START
        hex "Physical memory start address"
        default "0x50000000" if MACH_G3EVM
-       default "0x40000000" if MACH_G4EVM
-       default "0x40000000" if MACH_AP4EVB
+       default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
+                               MACH_MACKEREL
        default "0x00000000"
        ---help---
          Tweak this only when porting to a new machine which does not
@@ -76,7 +86,8 @@ config MEMORY_SIZE
        hex "Physical memory size"
        default "0x08000000" if MACH_G3EVM
        default "0x08000000" if MACH_G4EVM
-       default "0x10000000" if MACH_AP4EVB
+       default "0x20000000" if MACH_AG5EVM
+       default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
        default "0x04000000"
        help
          This sets the default memory size assumed by your kernel. It can
index ae416fe7daf2e61b09f683c9be36ebc57c105c62..e2507f66f9d5b8f68c9beab25c738e3891c43f3c 100644 (file)
@@ -9,14 +9,34 @@ obj-y                         := timer.o console.o clock.o pm_runtime.o
 obj-$(CONFIG_ARCH_SH7367)      += setup-sh7367.o clock-sh7367.o intc-sh7367.o
 obj-$(CONFIG_ARCH_SH7377)      += setup-sh7377.o clock-sh7377.o intc-sh7377.o
 obj-$(CONFIG_ARCH_SH7372)      += setup-sh7372.o clock-sh7372.o intc-sh7372.o
+obj-$(CONFIG_ARCH_SH73A0)      += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
+
+# SMP objects
+smp-y                          := platsmp.o headsmp.o
+smp-$(CONFIG_HOTPLUG_CPU)      += hotplug.o
+smp-$(CONFIG_LOCAL_TIMERS)     += localtimer.o
+smp-$(CONFIG_ARCH_SH73A0)      += smp-sh73a0.o
 
 # Pinmux setup
-pfc-$(CONFIG_ARCH_SH7367)      := pfc-sh7367.o
-pfc-$(CONFIG_ARCH_SH7377)      := pfc-sh7377.o
-pfc-$(CONFIG_ARCH_SH7372)      := pfc-sh7372.o
-obj-$(CONFIG_GENERIC_GPIO)     += $(pfc-y)
+pfc-y                          :=
+pfc-$(CONFIG_ARCH_SH7367)      += pfc-sh7367.o
+pfc-$(CONFIG_ARCH_SH7377)      += pfc-sh7377.o
+pfc-$(CONFIG_ARCH_SH7372)      += pfc-sh7372.o
+pfc-$(CONFIG_ARCH_SH73A0)      += pfc-sh73a0.o
+
+# IRQ objects
+obj-$(CONFIG_ARCH_SH7367)      += entry-intc.o
+obj-$(CONFIG_ARCH_SH7377)      += entry-intc.o
+obj-$(CONFIG_ARCH_SH7372)      += entry-intc.o
+obj-$(CONFIG_ARCH_SH73A0)      += entry-gic.o
 
 # Board objects
 obj-$(CONFIG_MACH_G3EVM)       += board-g3evm.o
 obj-$(CONFIG_MACH_G4EVM)       += board-g4evm.o
 obj-$(CONFIG_MACH_AP4EVB)      += board-ap4evb.o
+obj-$(CONFIG_MACH_AG5EVM)      += board-ag5evm.o
+obj-$(CONFIG_MACH_MACKEREL)    += board-mackerel.o
+
+# Framework support
+obj-$(CONFIG_SMP)              += $(smp-y)
+obj-$(CONFIG_GENERIC_GPIO)     += $(pfc-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
new file mode 100644 (file)
index 0000000..c18a740
--- /dev/null
@@ -0,0 +1,315 @@
+/*
+ * arch/arm/mach-shmobile/board-ag5evm.c
+ *
+ * Copyright (C) 2010  Takashi Yoshii <yoshii.takashi.zj@renesas.com>
+ * Copyright (C) 2009  Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_sci.h>
+#include <linux/smsc911x.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/input/sh_keysc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+
+#include <sound/sh_fsi.h>
+
+#include <mach/hardware.h>
+#include <mach/sh73a0.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/traps.h>
+
+static struct resource smsc9220_resources[] = {
+       [0] = {
+               .start          = 0x14000000,
+               .end            = 0x14000000 + SZ_64K - 1,
+               .flags          = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start          = gic_spi(33), /* PINT1 */
+               .flags          = IORESOURCE_IRQ,
+       },
+};
+
+static struct smsc911x_platform_config smsc9220_platdata = {
+       .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
+       .phy_interface  = PHY_INTERFACE_MODE_MII,
+       .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+       .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device eth_device = {
+       .name           = "smsc911x",
+       .id             = 0,
+       .dev  = {
+               .platform_data = &smsc9220_platdata,
+       },
+       .resource       = smsc9220_resources,
+       .num_resources  = ARRAY_SIZE(smsc9220_resources),
+};
+
+static struct sh_keysc_info keysc_platdata = {
+       .mode           = SH_KEYSC_MODE_6,
+       .scan_timing    = 3,
+       .delay          = 100,
+       .keycodes       = {
+               KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
+               KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
+               KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
+               KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
+               KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \
+               KEY_COFFEE,
+               KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP,
+               KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \
+               KEY_COMPUTER,
+       },
+};
+
+static struct resource keysc_resources[] = {
+       [0] = {
+               .name   = "KEYSC",
+               .start  = 0xe61b0000,
+               .end    = 0xe61b0098 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(71),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device keysc_device = {
+       .name           = "sh_keysc",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(keysc_resources),
+       .resource       = keysc_resources,
+       .dev            = {
+               .platform_data  = &keysc_platdata,
+       },
+};
+
+/* FSI A */
+static struct sh_fsi_platform_info fsi_info = {
+       .porta_flags = SH_FSI_OUT_SLAVE_MODE    |
+                      SH_FSI_IN_SLAVE_MODE     |
+                      SH_FSI_OFMT(I2S)         |
+                      SH_FSI_IFMT(I2S),
+};
+
+static struct resource fsi_resources[] = {
+       [0] = {
+               .name   = "FSI",
+               .start  = 0xEC230000,
+               .end    = 0xEC230400 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(146),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device fsi_device = {
+       .name           = "sh_fsi2",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(fsi_resources),
+       .resource       = fsi_resources,
+       .dev    = {
+               .platform_data  = &fsi_info,
+       },
+};
+
+static struct resource sh_mmcif_resources[] = {
+       [0] = {
+               .name   = "MMCIF",
+               .start  = 0xe6bd0000,
+               .end    = 0xe6bd00ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(141),
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = gic_spi(140),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_platdata = {
+       .sup_pclk       = 0,
+       .ocr            = MMC_VDD_165_195,
+       .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+};
+
+static struct platform_device mmc_device = {
+       .name           = "sh_mmcif",
+       .id             = 0,
+       .dev            = {
+               .dma_mask               = NULL,
+               .coherent_dma_mask      = 0xffffffff,
+               .platform_data          = &sh_mmcif_platdata,
+       },
+       .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+       .resource       = sh_mmcif_resources,
+};
+
+static struct platform_device *ag5evm_devices[] __initdata = {
+       &eth_device,
+       &keysc_device,
+       &fsi_device,
+       &mmc_device,
+};
+
+static struct map_desc ag5evm_io_desc[] __initdata = {
+       /* create a 1:1 entity map for 0xe6xxxxxx
+        * used by CPGA, INTC and PFC.
+        */
+       {
+               .virtual        = 0xe6000000,
+               .pfn            = __phys_to_pfn(0xe6000000),
+               .length         = 256 << 20,
+               .type           = MT_DEVICE_NONSHARED
+       },
+};
+
+static void __init ag5evm_map_io(void)
+{
+       iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
+
+       /* setup early devices and console here as well */
+       sh73a0_add_early_devices();
+       shmobile_setup_console();
+}
+
+#define PINTC_ADDR     0xe6900000
+#define PINTER0A       (PINTC_ADDR + 0xa0)
+#define PINTCR0A       (PINTC_ADDR + 0xb0)
+
+void __init ag5evm_init_irq(void)
+{
+       sh73a0_init_irq();
+
+       /* setup PINT: enable PINTA2 as active low */
+       __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
+       __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
+}
+
+static void __init ag5evm_init(void)
+{
+       sh73a0_pinmux_init();
+
+       /* enable SCIFA2 */
+       gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
+       gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
+       gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
+       gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
+
+       /* enable KEYSC */
+       gpio_request(GPIO_FN_KEYIN0_PU, NULL);
+       gpio_request(GPIO_FN_KEYIN1_PU, NULL);
+       gpio_request(GPIO_FN_KEYIN2_PU, NULL);
+       gpio_request(GPIO_FN_KEYIN3_PU, NULL);
+       gpio_request(GPIO_FN_KEYIN4_PU, NULL);
+       gpio_request(GPIO_FN_KEYIN5_PU, NULL);
+       gpio_request(GPIO_FN_KEYIN6_PU, NULL);
+       gpio_request(GPIO_FN_KEYIN7_PU, NULL);
+       gpio_request(GPIO_FN_KEYOUT0, NULL);
+       gpio_request(GPIO_FN_KEYOUT1, NULL);
+       gpio_request(GPIO_FN_KEYOUT2, NULL);
+       gpio_request(GPIO_FN_KEYOUT3, NULL);
+       gpio_request(GPIO_FN_KEYOUT4, NULL);
+       gpio_request(GPIO_FN_KEYOUT5, NULL);
+       gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
+       gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
+       gpio_request(GPIO_FN_KEYOUT8, NULL);
+       gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
+
+       /* enable I2C channel 2 and 3 */
+       gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
+       gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
+       gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
+       gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
+
+       /* enable MMCIF */
+       gpio_request(GPIO_FN_MMCCLK0, NULL);
+       gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
+       gpio_request(GPIO_FN_MMCD0_0, NULL);
+       gpio_request(GPIO_FN_MMCD0_1, NULL);
+       gpio_request(GPIO_FN_MMCD0_2, NULL);
+       gpio_request(GPIO_FN_MMCD0_3, NULL);
+       gpio_request(GPIO_FN_MMCD0_4, NULL);
+       gpio_request(GPIO_FN_MMCD0_5, NULL);
+       gpio_request(GPIO_FN_MMCD0_6, NULL);
+       gpio_request(GPIO_FN_MMCD0_7, NULL);
+       gpio_request(GPIO_PORT208, NULL); /* Reset */
+       gpio_direction_output(GPIO_PORT208, 1);
+
+       /* enable SMSC911X */
+       gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
+       gpio_direction_input(GPIO_PORT144);
+       gpio_request(GPIO_PORT145, NULL); /* RESET */
+       gpio_direction_output(GPIO_PORT145, 1);
+
+       /* FSI A */
+       gpio_request(GPIO_FN_FSIACK, NULL);
+       gpio_request(GPIO_FN_FSIAILR, NULL);
+       gpio_request(GPIO_FN_FSIAIBT, NULL);
+       gpio_request(GPIO_FN_FSIAISLD, NULL);
+       gpio_request(GPIO_FN_FSIAOSLD, NULL);
+
+#ifdef CONFIG_CACHE_L2X0
+       /* Shared attribute override enable, 64K*8way */
+       l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
+#endif
+       sh73a0_add_standard_devices();
+       platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
+}
+
+static void __init ag5evm_timer_init(void)
+{
+       sh73a0_clock_init();
+       shmobile_timer.init();
+       return;
+}
+
+struct sys_timer ag5evm_timer = {
+       .init   = ag5evm_timer_init,
+};
+
+MACHINE_START(AG5EVM, "ag5evm")
+       .map_io         = ag5evm_map_io,
+       .init_irq       = ag5evm_init_irq,
+       .handle_irq     = shmobile_handle_irq_gic,
+       .init_machine   = ag5evm_init,
+       .timer          = &ag5evm_timer,
+MACHINE_END
index f92dbd0c06d553a1a9f8bdae0e1315d05f178081..cd79d7c1ba0d9e5cf58b655dc6a7d10324575f24 100644 (file)
@@ -273,6 +273,15 @@ static struct resource sh_mmcif_resources[] = {
        },
 };
 
+static struct sh_mmcif_dma sh_mmcif_dma = {
+       .chan_priv_rx   = {
+               .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+       },
+       .chan_priv_tx   = {
+               .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+       },
+};
+
 static struct sh_mmcif_plat_data sh_mmcif_plat = {
        .sup_pclk       = 0,
        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -280,6 +289,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
                          MMC_CAP_8_BIT_DATA |
                          MMC_CAP_NEEDS_POLL,
        .get_cd         = slot_cn7_get_cd,
+       .dma            = &sh_mmcif_dma,
 };
 
 static struct platform_device sh_mmcif_device = {
@@ -633,9 +643,8 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
                return -EIO;
 
        ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
-       clk_put(fsib_clk);
        if (ret < 0)
-               return ret;
+               goto fsi_set_rate_end;
 
        /* FSI DIV setting */
        ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
@@ -643,10 +652,14 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
                /* disable FSI B */
                if (enable)
                        __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
-               return ret;
+               goto fsi_set_rate_end;
        }
 
-       return ackmd_bpfmd;
+       ret = ackmd_bpfmd;
+
+fsi_set_rate_end:
+       clk_put(fsib_clk);
+       return ret;
 }
 
 static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
@@ -1174,7 +1187,7 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_OVCN2_1,    NULL);
 
        /* setup USB phy */
-       __raw_writew(0x8a0a, 0xE6058130);       /* USBCR2 */
+       __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
 
        /* enable FSI2 port A (ak4643) */
        gpio_request(GPIO_FN_FSIAIBT,   NULL);
@@ -1348,6 +1361,7 @@ static struct sys_timer ap4evb_timer = {
 MACHINE_START(AP4EVB, "ap4evb")
        .map_io         = ap4evb_map_io,
        .init_irq       = sh7372_init_irq,
+       .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = ap4evb_init,
        .timer          = &ap4evb_timer,
 MACHINE_END
index 3b83d6320bec808d5f4259fc4308c307f7e62f2e..686b304a7708793b42084840bd900234cac82f1c 100644 (file)
@@ -367,6 +367,7 @@ static struct sys_timer g3evm_timer = {
 MACHINE_START(G3EVM, "g3evm")
        .map_io         = g3evm_map_io,
        .init_irq       = sh7367_init_irq,
+       .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = g3evm_init,
        .timer          = &g3evm_timer,
 MACHINE_END
index 5b3b582ef3f25fefd4430c071e89f42355832fb1..c13f01280b7ed85e6a5054d632129dfab85d056d 100644 (file)
@@ -394,6 +394,7 @@ static struct sys_timer g4evm_timer = {
 MACHINE_START(G4EVM, "g4evm")
        .map_io         = g4evm_map_io,
        .init_irq       = sh7377_init_irq,
+       .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = g4evm_init,
        .timer          = &g4evm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
new file mode 100644 (file)
index 0000000..5bcf5c1
--- /dev/null
@@ -0,0 +1,1200 @@
+/*
+ * mackerel board support
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * based on ap4evb
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/leds.h>
+#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/smsc911x.h>
+#include <linux/sh_intc.h>
+#include <linux/tca6416_keypad.h>
+#include <linux/usb/r8a66597.h>
+
+#include <video/sh_mobile_hdmi.h>
+#include <video/sh_mobile_lcdc.h>
+#include <media/sh_mobile_ceu.h>
+#include <media/soc_camera.h>
+#include <media/soc_camera_platform.h>
+#include <sound/sh_fsi.h>
+
+#include <mach/common.h>
+#include <mach/sh7372.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+/*
+ * Address     Interface               BusWidth        note
+ * ------------------------------------------------------------------
+ * 0x0000_0000 NOR Flash ROM (MCP)     16bit           SW7 : bit1 = ON
+ * 0x0800_0000 user area               -
+ * 0x1000_0000 NOR Flash ROM (MCP)     16bit           SW7 : bit1 = OFF
+ * 0x1400_0000 Ether (LAN9220)         16bit
+ * 0x1600_0000 user area               -               cannot use with NAND
+ * 0x1800_0000 user area               -
+ * 0x1A00_0000 -
+ * 0x4000_0000 LPDDR2-SDRAM (POP)      32bit
+ */
+
+/*
+ * CPU mode
+ *
+ * SW4                                     | Boot Area| Master   | Remarks
+ *  1  | 2   | 3   | 4   | 5   | 6   | 8   |          | Processor|
+ * ----+-----+-----+-----+-----+-----+-----+----------+----------+--------------
+ * ON  | ON  | OFF | ON  | ON  | OFF | OFF | External | System   | External ROM
+ * ON  | ON  | ON  | ON  | ON  | OFF | OFF | External | System   | ROM Debug
+ * ON  | ON  | X   | ON  | OFF | OFF | OFF | Built-in | System   | ROM Debug
+ * X   | OFF | X   | X   | X   | X   | OFF | Built-in | System   | MaskROM
+ * OFF | X   | X   | X   | X   | X   | OFF | Built-in | System   | MaskROM
+ * X   | X   | X   | OFF | X   | X   | OFF | Built-in | System   | MaskROM
+ * OFF | ON  | OFF | X   | X   | OFF | ON  | External | System   | Standalone
+ * ON  | OFF | OFF | X   | X   | OFF | ON  | External | Realtime | Standalone
+*/
+
+/*
+ * NOR Flash ROM
+ *
+ *  SW1  |     SW2    | SW7  | NOR Flash ROM
+ *  bit1 | bit1  bit2 | bit1 | Memory allocation
+ * ------+------------+------+------------------
+ *  OFF  | ON     OFF | ON   |    Area 0
+ *  OFF  | ON     OFF | OFF  |    Area 4
+ */
+
+/*
+ * SMSC 9220
+ *
+ *  SW1                SMSC 9220
+ * -----------------------
+ *  ON         access disable
+ *  OFF                access enable
+ */
+
+/*
+ * NAND Flash ROM
+ *
+ *  SW1  |     SW2    | SW7  | NAND Flash ROM
+ *  bit1 | bit1  bit2 | bit2 | Memory allocation
+ * ------+------------+------+------------------
+ *  OFF  | ON     OFF | ON   |    FCE 0
+ *  OFF  | ON     OFF | OFF  |    FCE 1
+ */
+
+/*
+ * External interrupt pin settings
+ *
+ * IRQX  | pin setting        | device             | level
+ * ------+--------------------+--------------------+-------
+ * IRQ0  | ICR1A.IRQ0SA=0010  | SDHI2 card detect  | Low
+ * IRQ6  | ICR1A.IRQ6SA=0011  | Ether(LAN9220)     | High
+ * IRQ7  | ICR1A.IRQ7SA=0010  | LCD Tuch Panel     | Low
+ * IRQ8  | ICR2A.IRQ8SA=0010  | MMC/SD card detect | Low
+ * IRQ9  | ICR2A.IRQ9SA=0010  | KEY(TCA6408)       | Low
+ * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345)    | High
+ * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975)     | High
+ */
+
+/*
+ * USB
+ *
+ * USB0 : CN22 : Function
+ * USB1 : CN31 : Function/Host *1
+ *
+ * J30 (for CN31) *1
+ * ----------+---------------+-------------
+ * 1-2 short | VBUS 5V       | Host
+ * open      | external VBUS | Function
+ *
+ * *1
+ * CN31 is used as Host in Linux.
+ */
+
+/*
+ * SDHI0 (CN12)
+ *
+ * SW56 : OFF
+ *
+ */
+
+/* MMC /SDHI1 (CN7)
+ *
+ * I/O voltage : 1.8v
+ *
+ * Power voltage : 1.8v or 3.3v
+ *  J22 : select power voltage *1
+ *     1-2 pin : 1.8v
+ *     2-3 pin : 3.3v
+ *
+ * *1
+ * Please change J22 depends the card to be used.
+ * MMC's OCR field set to support either voltage for the card inserted.
+ *
+ *     SW1     |       SW33
+ *             | bit1 | bit2 | bit3 | bit4
+ * -------------+------+------+------+-------
+ * MMC0          OFF   |  OFF |  ON  |  ON  |  X
+ * MMC1          ON    |  OFF |  ON  |  X   | ON
+ * SDHI1  OFF  |  ON  |   X  |  OFF | ON
+ *
+ */
+
+/*
+ * SDHI2 (CN23)
+ *
+ * microSD card sloct
+ *
+ */
+
+/*
+ * FIXME !!
+ *
+ * gpio_no_direction
+ * are quick_hack.
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static void __init gpio_no_direction(u32 addr)
+{
+       __raw_writeb(0x00, addr);
+}
+
+/* MTD */
+static struct mtd_partition nor_flash_partitions[] = {
+       {
+               .name           = "loader",
+               .offset         = 0x00000000,
+               .size           = 512 * 1024,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "bootenv",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 512 * 1024,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "kernel_ro",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 8 * 1024 * 1024,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "kernel",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 8 * 1024 * 1024,
+       },
+       {
+               .name           = "data",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = MTDPART_SIZ_FULL,
+       },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+       .width          = 2,
+       .parts          = nor_flash_partitions,
+       .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+       [0]     = {
+               .start  = 0x00000000,
+               .end    = 0x08000000 - 1,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct platform_device nor_flash_device = {
+       .name           = "physmap-flash",
+       .dev            = {
+               .platform_data  = &nor_flash_data,
+       },
+       .num_resources  = ARRAY_SIZE(nor_flash_resources),
+       .resource       = nor_flash_resources,
+};
+
+/* SMSC */
+static struct resource smc911x_resources[] = {
+       {
+               .start  = 0x14000000,
+               .end    = 0x16000000 - 1,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = evt2irq(0x02c0) /* IRQ6A */,
+               .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+       },
+};
+
+static struct smsc911x_platform_config smsc911x_info = {
+       .flags          = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
+       .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+       .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device smc911x_device = {
+       .name           = "smsc911x",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(smc911x_resources),
+       .resource       = smc911x_resources,
+       .dev            = {
+               .platform_data = &smsc911x_info,
+       },
+};
+
+/* LCDC */
+static struct fb_videomode mackerel_lcdc_modes[] = {
+       {
+               .name           = "WVGA Panel",
+               .xres           = 800,
+               .yres           = 480,
+               .left_margin    = 220,
+               .right_margin   = 110,
+               .hsync_len      = 70,
+               .upper_margin   = 20,
+               .lower_margin   = 5,
+               .vsync_len      = 5,
+               .sync           = 0,
+       },
+};
+
+static struct sh_mobile_lcdc_info lcdc_info = {
+       .clock_source = LCDC_CLK_BUS,
+       .ch[0] = {
+               .chan = LCDC_CHAN_MAINLCD,
+               .bpp = 16,
+               .lcd_cfg = mackerel_lcdc_modes,
+               .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
+               .interface_type         = RGB24,
+               .clock_divider          = 2,
+               .flags                  = 0,
+               .lcd_size_cfg.width     = 152,
+               .lcd_size_cfg.height    = 91,
+       }
+};
+
+static struct resource lcdc_resources[] = {
+       [0] = {
+               .name   = "LCDC",
+               .start  = 0xfe940000,
+               .end    = 0xfe943fff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = intcs_evt2irq(0x580),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device lcdc_device = {
+       .name           = "sh_mobile_lcdc_fb",
+       .num_resources  = ARRAY_SIZE(lcdc_resources),
+       .resource       = lcdc_resources,
+       .dev    = {
+               .platform_data  = &lcdc_info,
+               .coherent_dma_mask = ~0,
+       },
+};
+
+/* HDMI */
+static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
+       .clock_source = LCDC_CLK_EXTERNAL,
+       .ch[0] = {
+               .chan = LCDC_CHAN_MAINLCD,
+               .bpp = 16,
+               .interface_type = RGB24,
+               .clock_divider = 1,
+               .flags = LCDC_FLAGS_DWPOL,
+       }
+};
+
+static struct resource hdmi_lcdc_resources[] = {
+       [0] = {
+               .name   = "LCDC1",
+               .start  = 0xfe944000,
+               .end    = 0xfe947fff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = intcs_evt2irq(0x1780),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device hdmi_lcdc_device = {
+       .name           = "sh_mobile_lcdc_fb",
+       .num_resources  = ARRAY_SIZE(hdmi_lcdc_resources),
+       .resource       = hdmi_lcdc_resources,
+       .id             = 1,
+       .dev    = {
+               .platform_data  = &hdmi_lcdc_info,
+               .coherent_dma_mask = ~0,
+       },
+};
+
+static struct sh_mobile_hdmi_info hdmi_info = {
+       .lcd_chan       = &hdmi_lcdc_info.ch[0],
+       .lcd_dev        = &hdmi_lcdc_device.dev,
+       .flags          = HDMI_SND_SRC_SPDIF,
+};
+
+static struct resource hdmi_resources[] = {
+       [0] = {
+               .name   = "HDMI",
+               .start  = 0xe6be0000,
+               .end    = 0xe6be00ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
+               .start  = evt2irq(0x17e0),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device hdmi_device = {
+       .name           = "sh-mobile-hdmi",
+       .num_resources  = ARRAY_SIZE(hdmi_resources),
+       .resource       = hdmi_resources,
+       .id             = -1,
+       .dev    = {
+               .platform_data  = &hdmi_info,
+       },
+};
+
+static int __init hdmi_init_pm_clock(void)
+{
+       struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+       int ret;
+       long rate;
+
+       if (IS_ERR(hdmi_ick)) {
+               ret = PTR_ERR(hdmi_ick);
+               pr_err("Cannot get HDMI ICK: %d\n", ret);
+               goto out;
+       }
+
+       ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
+       if (ret < 0) {
+               pr_err("Cannot set PLLC2 parent: %d, %d users\n",
+                      ret, sh7372_pllc2_clk.usecount);
+               goto out;
+       }
+
+       pr_debug("PLLC2 initial frequency %lu\n",
+                clk_get_rate(&sh7372_pllc2_clk));
+
+       rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
+       if (rate < 0) {
+               pr_err("Cannot get suitable rate: %ld\n", rate);
+               ret = rate;
+               goto out;
+       }
+
+       ret = clk_set_rate(&sh7372_pllc2_clk, rate);
+       if (ret < 0) {
+               pr_err("Cannot set rate %ld: %d\n", rate, ret);
+               goto out;
+       }
+
+       ret = clk_enable(&sh7372_pllc2_clk);
+       if (ret < 0) {
+               pr_err("Cannot enable pllc2 clock\n");
+               goto out;
+       }
+
+       pr_debug("PLLC2 set frequency %lu\n", rate);
+
+       ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
+       if (ret < 0) {
+               pr_err("Cannot set HDMI parent: %d\n", ret);
+               goto out;
+       }
+
+out:
+       if (!IS_ERR(hdmi_ick))
+               clk_put(hdmi_ick);
+       return ret;
+}
+device_initcall(hdmi_init_pm_clock);
+
+/* USB1 (Host) */
+static void usb1_host_port_power(int port, int power)
+{
+       if (!power) /* only power-on is supported for now */
+               return;
+
+       /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
+       __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+}
+
+static struct r8a66597_platdata usb1_host_data = {
+       .on_chip        = 1,
+       .port_power     = usb1_host_port_power,
+};
+
+static struct resource usb1_host_resources[] = {
+       [0] = {
+               .name   = "USBHS",
+               .start  = 0xE68B0000,
+               .end    = 0xE68B00E6 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device usb1_host_device = {
+       .name   = "r8a66597_hcd",
+       .id     = 1,
+       .dev = {
+               .dma_mask               = NULL,         /*  not use dma */
+               .coherent_dma_mask      = 0xffffffff,
+               .platform_data          = &usb1_host_data,
+       },
+       .num_resources  = ARRAY_SIZE(usb1_host_resources),
+       .resource       = usb1_host_resources,
+};
+
+/* LED */
+static struct gpio_led mackerel_leds[] = {
+       {
+               .name           = "led0",
+               .gpio           = GPIO_PORT0,
+               .default_state  = LEDS_GPIO_DEFSTATE_ON,
+       },
+       {
+               .name           = "led1",
+               .gpio           = GPIO_PORT1,
+               .default_state  = LEDS_GPIO_DEFSTATE_ON,
+       },
+       {
+               .name           = "led2",
+               .gpio           = GPIO_PORT2,
+               .default_state  = LEDS_GPIO_DEFSTATE_ON,
+       },
+       {
+               .name           = "led3",
+               .gpio           = GPIO_PORT159,
+               .default_state  = LEDS_GPIO_DEFSTATE_ON,
+       }
+};
+
+static struct gpio_led_platform_data mackerel_leds_pdata = {
+       .leds = mackerel_leds,
+       .num_leds = ARRAY_SIZE(mackerel_leds),
+};
+
+static struct platform_device leds_device = {
+       .name = "leds-gpio",
+       .id = 0,
+       .dev = {
+               .platform_data  = &mackerel_leds_pdata,
+       },
+};
+
+/* FSI */
+#define IRQ_FSI evt2irq(0x1840)
+static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
+{
+       int ret;
+
+       if (rate <= 0)
+               return 0;
+
+       if (!enable) {
+               clk_disable(clk);
+               return 0;
+       }
+
+       ret = clk_set_rate(clk, clk_round_rate(clk, rate));
+       if (ret < 0)
+               return ret;
+
+       return clk_enable(clk);
+}
+
+static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
+{
+       struct clk *fsib_clk;
+       struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+       long fsib_rate = 0;
+       long fdiv_rate = 0;
+       int ackmd_bpfmd;
+       int ret;
+
+       /* FSIA is slave mode. nothing to do here */
+       if (is_porta)
+               return 0;
+
+       /* clock start */
+       switch (rate) {
+       case 44100:
+               fsib_rate       = rate * 256;
+               ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+               break;
+       case 48000:
+               fsib_rate       = 85428000; /* around 48kHz x 256 x 7 */
+               fdiv_rate       = rate * 256;
+               ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+               break;
+       default:
+               pr_err("unsupported rate in FSI2 port B\n");
+               return -EINVAL;
+       }
+
+       /* FSI B setting */
+       fsib_clk = clk_get(dev, "ickb");
+       if (IS_ERR(fsib_clk))
+               return -EIO;
+
+       /* fsib */
+       ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
+       if (ret < 0)
+               goto fsi_set_rate_end;
+
+       /* FSI DIV */
+       ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
+       if (ret < 0) {
+               /* disable FSI B */
+               if (enable)
+                       __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
+               goto fsi_set_rate_end;
+       }
+
+       ret = ackmd_bpfmd;
+
+fsi_set_rate_end:
+       clk_put(fsib_clk);
+       return ret;
+}
+
+static struct sh_fsi_platform_info fsi_info = {
+       .porta_flags =  SH_FSI_BRS_INV          |
+                       SH_FSI_OUT_SLAVE_MODE   |
+                       SH_FSI_IN_SLAVE_MODE    |
+                       SH_FSI_OFMT(PCM)        |
+                       SH_FSI_IFMT(PCM),
+
+       .portb_flags =  SH_FSI_BRS_INV  |
+                       SH_FSI_BRM_INV  |
+                       SH_FSI_LRS_INV  |
+                       SH_FSI_OFMT(SPDIF),
+
+       .set_rate = fsi_set_rate,
+};
+
+static struct resource fsi_resources[] = {
+       [0] = {
+               .name   = "FSI",
+               .start  = 0xFE3C0000,
+               .end    = 0xFE3C0400 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_FSI,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device fsi_device = {
+       .name           = "sh_fsi2",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(fsi_resources),
+       .resource       = fsi_resources,
+       .dev    = {
+               .platform_data  = &fsi_info,
+       },
+};
+
+static struct platform_device fsi_ak4643_device = {
+       .name           = "sh_fsi2_a_ak4643",
+};
+
+/*
+ * The card detect pin of the top SD/MMC slot (CN7) is active low and is
+ * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ */
+static int slot_cn7_get_cd(struct platform_device *pdev)
+{
+       if (gpio_is_valid(GPIO_PORT41))
+               return !gpio_get_value(GPIO_PORT41);
+       else
+               return -ENXIO;
+}
+
+/* SDHI0 */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+       .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+       .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+       .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+};
+
+static struct resource sdhi0_resources[] = {
+       [0] = {
+               .name   = "SDHI0",
+               .start  = 0xe6850000,
+               .end    = 0xe68501ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x0e00) /* SDHI0 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi0_device = {
+       .name           = "sh_mobile_sdhi",
+       .num_resources  = ARRAY_SIZE(sdhi0_resources),
+       .resource       = sdhi0_resources,
+       .id             = 0,
+       .dev    = {
+               .platform_data  = &sdhi0_info,
+       },
+};
+
+#if !defined(CONFIG_MMC_SH_MMCIF)
+/* SDHI1 */
+static struct sh_mobile_sdhi_info sdhi1_info = {
+       .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
+       .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+       .tmio_ocr_mask  = MMC_VDD_165_195,
+       .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+       .tmio_caps      = MMC_CAP_SD_HIGHSPEED |
+                         MMC_CAP_NEEDS_POLL,
+       .get_cd         = slot_cn7_get_cd,
+};
+
+static struct resource sdhi1_resources[] = {
+       [0] = {
+               .name   = "SDHI1",
+               .start  = 0xe6860000,
+               .end    = 0xe68601ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x0e80),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi1_device = {
+       .name           = "sh_mobile_sdhi",
+       .num_resources  = ARRAY_SIZE(sdhi1_resources),
+       .resource       = sdhi1_resources,
+       .id             = 1,
+       .dev    = {
+               .platform_data  = &sdhi1_info,
+       },
+};
+#endif
+
+/* SDHI2 */
+static struct sh_mobile_sdhi_info sdhi2_info = {
+       .dma_slave_tx   = SHDMA_SLAVE_SDHI2_TX,
+       .dma_slave_rx   = SHDMA_SLAVE_SDHI2_RX,
+       .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+       .tmio_caps      = MMC_CAP_SD_HIGHSPEED |
+                         MMC_CAP_NEEDS_POLL,
+};
+
+static struct resource sdhi2_resources[] = {
+       [0] = {
+               .name   = "SDHI2",
+               .start  = 0xe6870000,
+               .end    = 0xe68701ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x1200),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi2_device = {
+       .name   = "sh_mobile_sdhi",
+       .num_resources  = ARRAY_SIZE(sdhi2_resources),
+       .resource       = sdhi2_resources,
+       .id             = 2,
+       .dev    = {
+               .platform_data  = &sdhi2_info,
+       },
+};
+
+/* SH_MMCIF */
+static struct resource sh_mmcif_resources[] = {
+       [0] = {
+               .name   = "MMCIF",
+               .start  = 0xE6BD0000,
+               .end    = 0xE6BD00FF,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               /* MMC ERR */
+               .start  = evt2irq(0x1ac0),
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               /* MMC NOR */
+               .start  = evt2irq(0x1ae0),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+       .sup_pclk       = 0,
+       .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+       .caps           = MMC_CAP_4_BIT_DATA |
+                         MMC_CAP_8_BIT_DATA |
+                         MMC_CAP_NEEDS_POLL,
+       .get_cd         = slot_cn7_get_cd,
+};
+
+static struct platform_device sh_mmcif_device = {
+       .name           = "sh_mmcif",
+       .id             = 0,
+       .dev            = {
+               .dma_mask               = NULL,
+               .coherent_dma_mask      = 0xffffffff,
+               .platform_data          = &sh_mmcif_plat,
+       },
+       .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+       .resource       = sh_mmcif_resources,
+};
+
+
+static int mackerel_camera_add(struct soc_camera_link *icl, struct device *dev);
+static void mackerel_camera_del(struct soc_camera_link *icl);
+
+static int camera_set_capture(struct soc_camera_platform_info *info,
+                             int enable)
+{
+       return 0; /* camera sensor always enabled */
+}
+
+static struct soc_camera_platform_info camera_info = {
+       .format_name = "UYVY",
+       .format_depth = 16,
+       .format = {
+               .code = V4L2_MBUS_FMT_UYVY8_2X8,
+               .colorspace = V4L2_COLORSPACE_SMPTE170M,
+               .field = V4L2_FIELD_NONE,
+               .width = 640,
+               .height = 480,
+       },
+       .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
+       SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 |
+       SOCAM_DATA_ACTIVE_HIGH,
+       .set_capture = camera_set_capture,
+};
+
+static struct soc_camera_link camera_link = {
+       .bus_id         = 0,
+       .add_device     = mackerel_camera_add,
+       .del_device     = mackerel_camera_del,
+       .module_name    = "soc_camera_platform",
+       .priv           = &camera_info,
+};
+
+static void dummy_release(struct device *dev)
+{
+}
+
+static struct platform_device camera_device = {
+       .name           = "soc_camera_platform",
+       .dev            = {
+               .platform_data  = &camera_info,
+               .release        = dummy_release,
+       },
+};
+
+static int mackerel_camera_add(struct soc_camera_link *icl,
+                              struct device *dev)
+{
+       if (icl != &camera_link)
+               return -ENODEV;
+
+       camera_info.dev = dev;
+
+       return platform_device_register(&camera_device);
+}
+
+static void mackerel_camera_del(struct soc_camera_link *icl)
+{
+       if (icl != &camera_link)
+               return;
+
+       platform_device_unregister(&camera_device);
+       memset(&camera_device.dev.kobj, 0,
+              sizeof(camera_device.dev.kobj));
+}
+
+static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
+       .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+};
+
+static struct resource ceu_resources[] = {
+       [0] = {
+               .name   = "CEU",
+               .start  = 0xfe910000,
+               .end    = 0xfe91009f,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = intcs_evt2irq(0x880),
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               /* place holder for contiguous memory */
+       },
+};
+
+static struct platform_device ceu_device = {
+       .name           = "sh_mobile_ceu",
+       .id             = 0, /* "ceu0" clock */
+       .num_resources  = ARRAY_SIZE(ceu_resources),
+       .resource       = ceu_resources,
+       .dev            = {
+               .platform_data  = &sh_mobile_ceu_info,
+       },
+};
+
+static struct platform_device mackerel_camera = {
+       .name   = "soc-camera-pdrv",
+       .id     = 0,
+       .dev    = {
+               .platform_data = &camera_link,
+       },
+};
+
+static struct platform_device *mackerel_devices[] __initdata = {
+       &nor_flash_device,
+       &smc911x_device,
+       &lcdc_device,
+       &usb1_host_device,
+       &leds_device,
+       &fsi_device,
+       &fsi_ak4643_device,
+       &sdhi0_device,
+#if !defined(CONFIG_MMC_SH_MMCIF)
+       &sdhi1_device,
+#endif
+       &sdhi2_device,
+       &sh_mmcif_device,
+       &ceu_device,
+       &mackerel_camera,
+       &hdmi_lcdc_device,
+       &hdmi_device,
+};
+
+/* Keypad Initialization */
+#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
+{                                                              \
+       .type           = ev_type,                              \
+       .code           = ev_code,                              \
+       .active_low     = act_low,                              \
+}
+
+#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
+
+static struct tca6416_button mackerel_gpio_keys[] = {
+       KEYPAD_BUTTON_LOW(KEY_HOME),
+       KEYPAD_BUTTON_LOW(KEY_MENU),
+       KEYPAD_BUTTON_LOW(KEY_BACK),
+       KEYPAD_BUTTON_LOW(KEY_POWER),
+};
+
+static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
+       .buttons        = mackerel_gpio_keys,
+       .nbuttons       = ARRAY_SIZE(mackerel_gpio_keys),
+       .rep            = 1,
+       .use_polling    = 0,
+       .pinmask        = 0x000F,
+};
+
+/* I2C */
+#define IRQ9 evt2irq(0x0320)
+
+static struct i2c_board_info i2c0_devices[] = {
+       {
+               I2C_BOARD_INFO("ak4643", 0x13),
+       },
+       /* Keypad */
+       {
+               I2C_BOARD_INFO("tca6408-keys", 0x20),
+               .platform_data = &mackerel_tca6416_keys_info,
+               .irq = IRQ9,
+       },
+};
+
+#define IRQ21 evt2irq(0x32a0)
+
+static struct i2c_board_info i2c1_devices[] = {
+       /* Accelerometer */
+       {
+               I2C_BOARD_INFO("adxl34x", 0x53),
+               .irq = IRQ21,
+       },
+};
+
+static struct map_desc mackerel_io_desc[] __initdata = {
+       /* create a 1:1 entity map for 0xe6xxxxxx
+        * used by CPGA, INTC and PFC.
+        */
+       {
+               .virtual        = 0xe6000000,
+               .pfn            = __phys_to_pfn(0xe6000000),
+               .length         = 256 << 20,
+               .type           = MT_DEVICE_NONSHARED
+       },
+};
+
+static void __init mackerel_map_io(void)
+{
+       iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
+
+       /* setup early devices and console here as well */
+       sh7372_add_early_devices();
+       shmobile_setup_console();
+}
+
+#define GPIO_PORT9CR   0xE6051009
+#define GPIO_PORT10CR  0xE605100A
+#define SRCR4          0xe61580bc
+#define USCCR1         0xE6058144
+static void __init mackerel_init(void)
+{
+       u32 srcr4;
+       struct clk *clk;
+
+       sh7372_pinmux_init();
+
+       /* enable SCIFA0 */
+       gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
+       gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
+
+       /* enable SMSC911X */
+       gpio_request(GPIO_FN_CS5A,      NULL);
+       gpio_request(GPIO_FN_IRQ6_39,   NULL);
+
+       /* LCDC */
+       gpio_request(GPIO_FN_LCDD23,   NULL);
+       gpio_request(GPIO_FN_LCDD22,   NULL);
+       gpio_request(GPIO_FN_LCDD21,   NULL);
+       gpio_request(GPIO_FN_LCDD20,   NULL);
+       gpio_request(GPIO_FN_LCDD19,   NULL);
+       gpio_request(GPIO_FN_LCDD18,   NULL);
+       gpio_request(GPIO_FN_LCDD17,   NULL);
+       gpio_request(GPIO_FN_LCDD16,   NULL);
+       gpio_request(GPIO_FN_LCDD15,   NULL);
+       gpio_request(GPIO_FN_LCDD14,   NULL);
+       gpio_request(GPIO_FN_LCDD13,   NULL);
+       gpio_request(GPIO_FN_LCDD12,   NULL);
+       gpio_request(GPIO_FN_LCDD11,   NULL);
+       gpio_request(GPIO_FN_LCDD10,   NULL);
+       gpio_request(GPIO_FN_LCDD9,    NULL);
+       gpio_request(GPIO_FN_LCDD8,    NULL);
+       gpio_request(GPIO_FN_LCDD7,    NULL);
+       gpio_request(GPIO_FN_LCDD6,    NULL);
+       gpio_request(GPIO_FN_LCDD5,    NULL);
+       gpio_request(GPIO_FN_LCDD4,    NULL);
+       gpio_request(GPIO_FN_LCDD3,    NULL);
+       gpio_request(GPIO_FN_LCDD2,    NULL);
+       gpio_request(GPIO_FN_LCDD1,    NULL);
+       gpio_request(GPIO_FN_LCDD0,    NULL);
+       gpio_request(GPIO_FN_LCDDISP,  NULL);
+       gpio_request(GPIO_FN_LCDDCK,   NULL);
+
+       gpio_request(GPIO_PORT31, NULL); /* backlight */
+       gpio_direction_output(GPIO_PORT31, 1);
+
+       gpio_request(GPIO_PORT151, NULL); /* LCDDON */
+       gpio_direction_output(GPIO_PORT151, 1);
+
+       /* USB enable */
+       gpio_request(GPIO_FN_VBUS0_1,    NULL);
+       gpio_request(GPIO_FN_IDIN_1_18,  NULL);
+       gpio_request(GPIO_FN_PWEN_1_115, NULL);
+       gpio_request(GPIO_FN_OVCN_1_114, NULL);
+       gpio_request(GPIO_FN_EXTLP_1,    NULL);
+       gpio_request(GPIO_FN_OVCN2_1,    NULL);
+
+       /* setup USB phy */
+       __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
+
+       /* enable FSI2 port A (ak4643) */
+       gpio_request(GPIO_FN_FSIAIBT,   NULL);
+       gpio_request(GPIO_FN_FSIAILR,   NULL);
+       gpio_request(GPIO_FN_FSIAISLD,  NULL);
+       gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+       gpio_request(GPIO_PORT161,      NULL);
+       gpio_direction_output(GPIO_PORT161, 0); /* slave */
+
+       gpio_request(GPIO_PORT9,  NULL);
+       gpio_request(GPIO_PORT10, NULL);
+       gpio_no_direction(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
+       gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
+
+       intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
+
+       /* setup FSI2 port B (HDMI) */
+       gpio_request(GPIO_FN_FSIBCK, NULL);
+       __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
+
+       /* set SPU2 clock to 119.6 MHz */
+       clk = clk_get(NULL, "spu_clk");
+       if (!IS_ERR(clk)) {
+               clk_set_rate(clk, clk_round_rate(clk, 119600000));
+               clk_put(clk);
+       }
+
+       /* enable Keypad */
+       gpio_request(GPIO_FN_IRQ9_42,   NULL);
+       set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
+
+       /* enable Accelerometer */
+       gpio_request(GPIO_FN_IRQ21,     NULL);
+       set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
+
+       /* enable SDHI0 */
+       gpio_request(GPIO_FN_SDHICD0, NULL);
+       gpio_request(GPIO_FN_SDHIWP0, NULL);
+       gpio_request(GPIO_FN_SDHICMD0, NULL);
+       gpio_request(GPIO_FN_SDHICLK0, NULL);
+       gpio_request(GPIO_FN_SDHID0_3, NULL);
+       gpio_request(GPIO_FN_SDHID0_2, NULL);
+       gpio_request(GPIO_FN_SDHID0_1, NULL);
+       gpio_request(GPIO_FN_SDHID0_0, NULL);
+
+#if !defined(CONFIG_MMC_SH_MMCIF)
+       /* enable SDHI1 */
+       gpio_request(GPIO_FN_SDHICMD1, NULL);
+       gpio_request(GPIO_FN_SDHICLK1, NULL);
+       gpio_request(GPIO_FN_SDHID1_3, NULL);
+       gpio_request(GPIO_FN_SDHID1_2, NULL);
+       gpio_request(GPIO_FN_SDHID1_1, NULL);
+       gpio_request(GPIO_FN_SDHID1_0, NULL);
+#endif
+       /* card detect pin for MMC slot (CN7) */
+       gpio_request(GPIO_PORT41, NULL);
+       gpio_direction_input(GPIO_PORT41);
+
+       /* enable SDHI2 */
+       gpio_request(GPIO_FN_SDHICMD2, NULL);
+       gpio_request(GPIO_FN_SDHICLK2, NULL);
+       gpio_request(GPIO_FN_SDHID2_3, NULL);
+       gpio_request(GPIO_FN_SDHID2_2, NULL);
+       gpio_request(GPIO_FN_SDHID2_1, NULL);
+       gpio_request(GPIO_FN_SDHID2_0, NULL);
+
+       /* MMCIF */
+       gpio_request(GPIO_FN_MMCD0_0, NULL);
+       gpio_request(GPIO_FN_MMCD0_1, NULL);
+       gpio_request(GPIO_FN_MMCD0_2, NULL);
+       gpio_request(GPIO_FN_MMCD0_3, NULL);
+       gpio_request(GPIO_FN_MMCD0_4, NULL);
+       gpio_request(GPIO_FN_MMCD0_5, NULL);
+       gpio_request(GPIO_FN_MMCD0_6, NULL);
+       gpio_request(GPIO_FN_MMCD0_7, NULL);
+       gpio_request(GPIO_FN_MMCCMD0, NULL);
+       gpio_request(GPIO_FN_MMCCLK0, NULL);
+
+       /* enable GPS module (GT-720F) */
+       gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
+       gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
+
+       /* CEU */
+       gpio_request(GPIO_FN_VIO_CLK, NULL);
+       gpio_request(GPIO_FN_VIO_VD, NULL);
+       gpio_request(GPIO_FN_VIO_HD, NULL);
+       gpio_request(GPIO_FN_VIO_FIELD, NULL);
+       gpio_request(GPIO_FN_VIO_CKO, NULL);
+       gpio_request(GPIO_FN_VIO_D7, NULL);
+       gpio_request(GPIO_FN_VIO_D6, NULL);
+       gpio_request(GPIO_FN_VIO_D5, NULL);
+       gpio_request(GPIO_FN_VIO_D4, NULL);
+       gpio_request(GPIO_FN_VIO_D3, NULL);
+       gpio_request(GPIO_FN_VIO_D2, NULL);
+       gpio_request(GPIO_FN_VIO_D1, NULL);
+       gpio_request(GPIO_FN_VIO_D0, NULL);
+
+       /* HDMI */
+       gpio_request(GPIO_FN_HDMI_HPD, NULL);
+       gpio_request(GPIO_FN_HDMI_CEC, NULL);
+
+       /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
+       srcr4 = __raw_readl(SRCR4);
+       __raw_writel(srcr4 | (1 << 13), SRCR4);
+       udelay(50);
+       __raw_writel(srcr4 & ~(1 << 13), SRCR4);
+
+       i2c_register_board_info(0, i2c0_devices,
+                               ARRAY_SIZE(i2c0_devices));
+       i2c_register_board_info(1, i2c1_devices,
+                               ARRAY_SIZE(i2c1_devices));
+
+       sh7372_add_standard_devices();
+
+       platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
+}
+
+static void __init mackerel_timer_init(void)
+{
+       sh7372_clock_init();
+       shmobile_timer.init();
+
+       /* External clock source */
+       clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+}
+
+static struct sys_timer mackerel_timer = {
+       .init           = mackerel_timer_init,
+};
+
+MACHINE_START(MACKEREL, "mackerel")
+       .map_io         = mackerel_map_io,
+       .init_irq       = sh7372_init_irq,
+       .handle_irq     = shmobile_handle_irq_intc,
+       .init_machine   = mackerel_init,
+       .timer          = &mackerel_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
new file mode 100644 (file)
index 0000000..c196a28
--- /dev/null
@@ -0,0 +1,356 @@
+/*
+ * sh73a0 clock framework support
+ *
+ * Copyright (C) 2010 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <mach/common.h>
+#include <asm/clkdev.h>
+
+#define FRQCRA         0xe6150000
+#define FRQCRB         0xe6150004
+#define FRQCRD         0xe61500e4
+#define VCLKCR1                0xe6150008
+#define VCLKCR2                0xe615000C
+#define VCLKCR3                0xe615001C
+#define ZBCKCR         0xe6150010
+#define FLCKCR         0xe6150014
+#define SD0CKCR                0xe6150074
+#define SD1CKCR                0xe6150078
+#define SD2CKCR                0xe615007C
+#define FSIACKCR       0xe6150018
+#define FSIBCKCR       0xe6150090
+#define SUBCKCR                0xe6150080
+#define SPUACKCR       0xe6150084
+#define SPUVCKCR       0xe6150094
+#define MSUCKCR                0xe6150088
+#define HSICKCR                0xe615008C
+#define MFCK1CR                0xe6150098
+#define MFCK2CR                0xe615009C
+#define DSITCKCR       0xe6150060
+#define DSI0PCKCR      0xe6150064
+#define DSI1PCKCR      0xe6150068
+#define DSI0PHYCR      0xe615006C
+#define DSI1PHYCR      0xe6150070
+#define PLLECR         0xe61500d0
+#define PLL0CR         0xe61500d8
+#define PLL1CR         0xe6150028
+#define PLL2CR         0xe615002c
+#define PLL3CR         0xe61500dc
+#define SMSTPCR0       0xe6150130
+#define SMSTPCR1       0xe6150134
+#define SMSTPCR2       0xe6150138
+#define SMSTPCR3       0xe615013c
+#define SMSTPCR4       0xe6150140
+#define SMSTPCR5       0xe6150144
+#define CKSCR          0xe61500c0
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+       .rate           = 32768,
+};
+
+/*
+ * 26MHz default rate for the EXTAL1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh73a0_extal1_clk = {
+       .rate           = 26000000,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh73a0_extal2_clk = {
+       .rate           = 48000000,
+};
+
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
+{
+       return clk->parent->rate / 2;
+}
+
+static struct clk_ops div2_clk_ops = {
+       .recalc         = div2_recalc,
+};
+
+/* Divide extal1 by two */
+static struct clk extal1_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &sh73a0_extal1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &sh73a0_extal2_clk,
+};
+
+static struct clk_ops main_clk_ops = {
+       .recalc         = followparent_recalc,
+};
+
+/* Main clock */
+static struct clk main_clk = {
+       .ops            = &main_clk_ops,
+};
+
+/* PLL0, PLL1, PLL2, PLL3 */
+static unsigned long pll_recalc(struct clk *clk)
+{
+       unsigned long mult = 1;
+
+       if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
+               mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
+
+       return clk->parent->rate * mult;
+}
+
+static struct clk_ops pll_clk_ops = {
+       .recalc         = pll_recalc,
+};
+
+static struct clk pll0_clk = {
+       .ops            = &pll_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &main_clk,
+       .enable_reg     = (void __iomem *)PLL0CR,
+       .enable_bit     = 0,
+};
+
+static struct clk pll1_clk = {
+       .ops            = &pll_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &main_clk,
+       .enable_reg     = (void __iomem *)PLL1CR,
+       .enable_bit     = 1,
+};
+
+static struct clk pll2_clk = {
+       .ops            = &pll_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &main_clk,
+       .enable_reg     = (void __iomem *)PLL2CR,
+       .enable_bit     = 2,
+};
+
+static struct clk pll3_clk = {
+       .ops            = &pll_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &main_clk,
+       .enable_reg     = (void __iomem *)PLL3CR,
+       .enable_bit     = 3,
+};
+
+/* Divide PLL1 by two */
+static struct clk pll1_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &pll1_clk,
+};
+
+static struct clk *main_clks[] = {
+       &r_clk,
+       &sh73a0_extal1_clk,
+       &sh73a0_extal2_clk,
+       &extal1_div2_clk,
+       &extal2_div2_clk,
+       &main_clk,
+       &pll0_clk,
+       &pll1_clk,
+       &pll2_clk,
+       &pll3_clk,
+       &pll1_div2_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+       unsigned long value;
+
+       /* set KICK bit in FRQCRB to update hardware setting */
+       value = __raw_readl(FRQCRB);
+       value |= (1 << 31);
+       __raw_writel(value, FRQCRB);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                         24, 0, 36, 48, 7 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+       .divisors = divisors,
+       .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+       .div_mult_table = &div4_div_mult_table,
+       .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+       DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+       SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+       [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
+       [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
+       [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+       [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+       [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
+       [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
+       [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
+       [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
+       [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
+       [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
+       [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
+};
+
+enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
+       DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+       DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
+       DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
+       DIV6_HSI,  DIV6_MFG1, DIV6_MFG2,
+       DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
+       DIV6_NR };
+
+static struct clk div6_clks[DIV6_NR] = {
+       [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
+       [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
+       [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
+       [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0),
+       [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
+       [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
+       [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
+       [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+       [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
+       [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
+       [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
+       [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
+       [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
+       [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
+       [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
+       [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
+       [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
+       [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
+       [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
+       [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
+};
+
+enum { MSTP001,
+       MSTP125, MSTP116,
+       MSTP219,
+       MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP331, MSTP329, MSTP323, MSTP312,
+       MSTP411, MSTP410, MSTP403,
+       MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+       SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[MSTP_NR] = {
+       [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
+       [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
+       [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+       [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
+       [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
+       [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+       [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
+       [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
+       [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
+       [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
+       [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
+       [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
+       [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+       [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
+       [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
+       [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
+       [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
+       [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+       /* main clocks */
+       CLKDEV_CON_ID("r_clk", &r_clk),
+
+       /* MSTP32 clocks */
+       CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
+       CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
+       CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
+       CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
+       CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
+       CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+       CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
+       CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+       CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+       CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+       CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+       CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+       CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
+       CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
+       CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+       CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
+       CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
+       CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
+       CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+};
+
+void __init sh73a0_clock_init(void)
+{
+       int k, ret = 0;
+
+       /* detect main clock parent */
+       switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
+       case 0:
+               main_clk.parent = &sh73a0_extal1_clk;
+               break;
+       case 1:
+               main_clk.parent = &extal1_div2_clk;
+               break;
+       case 2:
+               main_clk.parent = &sh73a0_extal2_clk;
+               break;
+       case 3:
+               main_clk.parent = &extal2_div2_clk;
+               break;
+       }
+
+       for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+               ret = clk_register(main_clks[k]);
+
+       if (!ret)
+               ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+       if (!ret)
+               ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+       if (!ret)
+               ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+       if (!ret)
+               clk_init();
+       else
+               panic("failed to setup sh73a0 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S
new file mode 100644 (file)
index 0000000..6e4fa47
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * ARM Interrupt demux handler using GIC
+ *
+ * Copyright (C) 2010 Magnus Damm
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/entry-macro-multi.S>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
+
+       .macro  get_irqnr_preamble, base, tmp
+       ldr     \base, =(0xf0000100)
+       .endm
+
+       arch_irq_handler shmobile_handle_irq_gic
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
new file mode 100644 (file)
index 0000000..cac0a7a
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * ARM Interrupt demux handler using INTC
+ *
+ * Copyright (C) 2010 Magnus Damm
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/entry-macro-multi.S>
+
+#define INTCA_BASE     0xe6980000
+#define INTFLGA_OFFS   0x00000018 /* accept pending interrupt */
+#define INTEVTA_OFFS   0x00000020 /* vector number of accepted interrupt */
+#define INTLVLA_OFFS   0x00000030 /* priority level of accepted interrupt */
+#define INTLVLB_OFFS   0x00000034 /* previous priority level */
+
+       .macro  get_irqnr_preamble, base, tmp
+       ldr     \base, =INTCA_BASE
+       .endm
+
+       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+       /* The single INTFLGA read access below results in the following:
+        *
+        * 1. INTLVLB is updated with old priority value from INTLVLA
+        * 2. Highest priority interrupt is accepted
+        * 3. INTLVLA is updated to contain priority of accepted interrupt
+        * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
+        */
+       ldr     \irqnr, [\base, #INTFLGA_OFFS]
+
+       /* Restore INTLVLA with the value saved in INTLVLB.
+        * This is required to support interrupt priorities properly.
+        */
+       ldrb    \tmp, [\base, #INTLVLB_OFFS]
+       strb    \tmp, [\base, #INTLVLA_OFFS]
+
+       /* Handle invalid vector number case */
+       cmp     \irqnr, #0
+       beq     1000f
+
+       /* Convert vector to irq number, same as the evt2irq() macro */
+       lsr     \irqnr, \irqnr, #0x5
+       subs    \irqnr, \irqnr, #16
+
+1000:
+       .endm
+
+       .macro  test_for_ipi, irqnr, irqstat, base, tmp
+       .endm
+
+       .macro  test_for_ltirq, irqnr, irqstat, base, tmp
+       .endm
+
+       arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
new file mode 100644 (file)
index 0000000..d4cec6b
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2010  Takashi Yoshii
+ *
+ * Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+
+       __INIT
+
+/*
+ * Reset vector for secondary CPUs.
+ * This will be mapped at address 0 by SBAR register.
+ * We need _long_ jump to the physical address.
+ */
+       .align  12
+ENTRY(shmobile_secondary_vector)
+       ldr     pc, 1f
+1:     .long   secondary_startup - PAGE_OFFSET + PHYS_OFFSET
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
new file mode 100644 (file)
index 0000000..238a0d9
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+int platform_cpu_kill(unsigned int cpu)
+{
+       return 1;
+}
+
+void platform_cpu_die(unsigned int cpu)
+{
+       while (1) {
+               /*
+                * here's the WFI
+                */
+               asm(".word      0xe320f003\n"
+                   :
+                   :
+                   : "memory", "cc");
+       }
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+       /*
+        * we don't allow CPU 0 to be shutdown (it is still too special
+        * e.g. clock tick interrupts)
+        */
+       return cpu == 0 ? -EPERM : 0;
+}
index efeef778a875fa0f20c934090f6fc6fda1663862..013ac0ee8256acd4dfd8eda35f770860ef289cdc 100644 (file)
@@ -3,8 +3,11 @@
 
 extern struct sys_timer shmobile_timer;
 extern void shmobile_setup_console(void);
+extern void shmobile_secondary_vector(void);
 struct clk;
 extern int clk_init(void);
+extern void shmobile_handle_irq_intc(struct pt_regs *);
+extern void shmobile_handle_irq_gic(struct pt_regs *);
 
 extern void sh7367_init_irq(void);
 extern void sh7367_add_early_devices(void);
@@ -30,4 +33,17 @@ extern void sh7372_pinmux_init(void);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
+extern void sh73a0_init_irq(void);
+extern void sh73a0_add_early_devices(void);
+extern void sh73a0_add_standard_devices(void);
+extern void sh73a0_clock_init(void);
+extern void sh73a0_pinmux_init(void);
+extern struct clk sh73a0_extal1_clk;
+extern struct clk sh73a0_extal2_clk;
+
+extern unsigned int sh73a0_get_core_count(void);
+extern void sh73a0_secondary_init(unsigned int cpu);
+extern int sh73a0_boot_secondary(unsigned int cpu);
+extern void sh73a0_smp_prepare_cpus(void);
+
 #endif /* __ARCH_MACH_COMMON_H */
index f428c4db2b60e60f2c21761859aaec3e4401eea3..d791f10eeac7ee4e26f1a072e7769d3e0a149b22 100644 (file)
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2010  Paul Mundt
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
-#include <mach/irqs.h>
-
-#define INTCA_BASE     0xe6980000
-#define INTFLGA_OFFS   0x00000018 /* accept pending interrupt */
-#define INTEVTA_OFFS   0x00000020 /* vector number of accepted interrupt */
-#define INTLVLA_OFFS   0x00000030 /* priority level of accepted interrupt */
-#define INTLVLB_OFFS   0x00000034 /* previous priority level */
 
        .macro  disable_fiq
        .endm
 
        .macro  get_irqnr_preamble, base, tmp
-       ldr     \base, =INTCA_BASE
-       .endm
-
-       .macro  arch_ret_to_user, tmp1, tmp2
        .endm
 
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-       /* The single INTFLGA read access below results in the following:
-        *
-        * 1. INTLVLB is updated with old priority value from INTLVLA
-        * 2. Highest priority interrupt is accepted
-        * 3. INTLVLA is updated to contain priority of accepted interrupt
-        * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
-        */
-       ldr     \irqnr, [\base, #INTFLGA_OFFS]
-
-       /* Restore INTLVLA with the value saved in INTLVLB.
-        * This is required to support interrupt priorities properly.
-        */
-       ldrb    \tmp, [\base, #INTLVLB_OFFS]
-       strb    \tmp, [\base, #INTLVLA_OFFS]
+       .endm
 
-       /* Handle invalid vector number case */
-       cmp     \irqnr, #0
-       beq     1000f
+       .macro  test_for_ipi, irqnr, irqstat, base, tmp
+       .endm
 
-       /* Convert vector to irq number, same as the evt2irq() macro */
-       lsr     \irqnr, \irqnr, #0x5
-       subs    \irqnr, \irqnr, #16
+       .macro  test_for_ltirq, irqnr, irqstat, base, tmp
+       .endm
 
-1000:
+       .macro  arch_ret_to_user, tmp1, tmp2
        .endm
index 3f0ef194603ef3469c42dd09c015406ec3931018..99264a5ce5e40db4158063301b66733bc2de1760 100644 (file)
@@ -1,7 +1,4 @@
 #ifndef __ASM_MACH_HARDWARE_H
 #define __ASM_MACH_HARDWARE_H
 
-/* INTFLGA register - used by low level interrupt code in entry-macro.S */
-#define INTFLGA                        0xe6980018
-
 #endif /* __ASM_MACH_HARDWARE_H */
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
new file mode 100644 (file)
index 0000000..e3ebfa7
--- /dev/null
@@ -0,0 +1,87 @@
+LIST "partner-jet-setup.txt"
+LIST "(C) Copyright 2010 Renesas Solutions Corp"
+LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
+
+LIST "RWT Setting"
+EW 0xE6020004, 0xA500
+EW 0xE6030004, 0xA500
+
+DD 0x01001000, 0x01001000
+
+LIST "GPIO Setting"
+EB 0xE6051013, 0xA2
+
+LIST "CPG"
+ED 0xE6150080, 0x00000180
+ED 0xE61500C0, 0x00000002
+
+WAIT 1, 0xFE40009C
+
+LIST "FRQCR"
+ED 0xE6150000, 0x2D1305C3
+ED 0xE61500E0, 0x9E40358E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE61500E4, 0x00002000
+
+WAIT 1, 0xFE40009C
+
+LIST "PLL"
+ED 0xE6150028, 0x00004000
+
+WAIT 1, 0xFE40009C
+
+ED 0xE615002C, 0x93000040
+
+WAIT 1, 0xFE40009C
+
+LIST "BSC"
+ED 0xFEC10000, 0x00E0001B
+
+LIST "SBSC1"
+ED 0xFE400354, 0x01AD8000
+ED 0xFE400354, 0x01AD8001
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400008, 0xBCC90151
+ED 0xFE400040, 0x41774113
+ED 0xFE400044, 0x2712E229
+ED 0xFE400048, 0x20C18505
+ED 0xFE40004C, 0x00110209
+ED 0xFE400010, 0x00000087
+
+WAIT 10, 0xFE40009C
+
+ED 0xFE400084, 0x0000003F
+EB 0xFE500000, 0x00
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400084, 0x0000FF0A
+EB 0xFE500000, 0x00
+
+WAIT 1, 0xFE40009C
+
+ED 0xFE400084, 0x00002201
+EB 0xFE500000, 0x00
+ED 0xFE400084, 0x00000302
+EB 0xFE500000, 0x00
+EB 0xFE5C0000, 0x00
+ED 0xFE400008, 0xBCC90159
+ED 0xFE40008C, 0x88800004
+ED 0xFE400094, 0x00000004
+ED 0xFE400028, 0xA55A0032
+ED 0xFE40002C, 0xA55A000C
+ED 0xFE400020, 0xA55A2048
+ED 0xFE400008, 0xBCC90959
+
+LIST "Change CPGA setting"
+ED 0xE61500E0, 0x9E40352E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE6150354, 0x00000002
index fa15b5f8a001127ca114b3fef16c39984adf88e1..dcb714f4d75ab15c2dca37bc0843ad1de73872d6 100644 (file)
@@ -1,7 +1,10 @@
 #ifndef __ASM_MACH_IRQS_H
 #define __ASM_MACH_IRQS_H
 
-#define NR_IRQS         512
+#define NR_IRQS         1024
+
+/* GIC */
+#define gic_spi(nr)            ((nr) + 32)
 
 /* INTCA */
 #define evt2irq(evt)           (((evt) >> 5) - 16)
index e4f9004e710382574fcf5e23cb67339fa0f53148..5736efcca60c484d7762e346a16cee2d18ad7759 100644 (file)
@@ -455,6 +455,8 @@ enum {
        SHDMA_SLAVE_SDHI1_TX,
        SHDMA_SLAVE_SDHI2_RX,
        SHDMA_SLAVE_SDHI2_TX,
+       SHDMA_SLAVE_MMCIF_RX,
+       SHDMA_SLAVE_MMCIF_TX,
 };
 
 extern struct clk sh7372_extal1_clk;
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
new file mode 100644 (file)
index 0000000..ceb2cdc
--- /dev/null
@@ -0,0 +1,467 @@
+#ifndef __ASM_SH73A0_H__
+#define __ASM_SH73A0_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+       /* Hardware manual Table 25-1 (GPIO) */
+       GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+       GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+       GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+       GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+       GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+       GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+       GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+       GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+       GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+       GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+       GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+       GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+       GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+       GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+       GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+       GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+       GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+       GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+       GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+       GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+       GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+       GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+       GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+       GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+
+       GPIO_PORT128, GPIO_PORT129,
+
+       GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+       GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+       GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+       GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+       GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+       GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+       GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+
+       GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+       GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+       GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+       GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+       GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+       GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+       GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+       GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+       GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+       GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+       GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+       GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+       GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+       GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+       GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+       GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+       GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+       GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+
+       GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
+
+       GPIO_PORT288, GPIO_PORT289,
+
+       GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+       GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+
+       GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+       GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
+
+       /* Table 25-1 (Function 0-7) */
+       GPIO_FN_VBUS_0,
+       GPIO_FN_GPI0,
+       GPIO_FN_GPI1,
+       GPIO_FN_GPI2,
+       GPIO_FN_GPI3,
+       GPIO_FN_GPI4,
+       GPIO_FN_GPI5,
+       GPIO_FN_GPI6,
+       GPIO_FN_GPI7,
+       GPIO_FN_SCIFA7_RXD,
+       GPIO_FN_SCIFA7_CTS_,
+       GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
+       GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
+       GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+       GPIO_FN_PORT16_VIO_CKOR,
+       GPIO_FN_SCIFA0_TXD,
+       GPIO_FN_SCIFA7_TXD,
+       GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+       GPIO_FN_GPO0,
+       GPIO_FN_GPO1,
+       GPIO_FN_GPO2, GPIO_FN_STATUS0,
+       GPIO_FN_GPO3, GPIO_FN_STATUS1,
+       GPIO_FN_GPO4, GPIO_FN_STATUS2,
+       GPIO_FN_VINT,
+       GPIO_FN_TCKON,
+       GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+       GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
+       GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+       GPIO_FN_PORT28_TPU1TO1,
+       GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
+       GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
+       GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
+       GPIO_FN_SCIFA4_TXD,
+       GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+       GPIO_FN_SCIFA4_RTS_,
+       GPIO_FN_SCIFA4_CTS_,
+       GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
+       GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
+       GPIO_FN_FSIBOSLD,
+       GPIO_FN_FSIBISLD,
+       GPIO_FN_VACK,
+       GPIO_FN_XTAL1L,
+       GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
+       GPIO_FN_SCIFA0_RXD,
+       GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+       GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
+       GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
+       GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
+       GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
+       GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
+       GPIO_FN_FSIAOMC,
+       GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
+
+       GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
+       GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
+       GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
+       GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
+       GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
+       GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
+       GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+       GPIO_FN_A0, GPIO_FN_BS_,
+       GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
+       GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
+       GPIO_FN_A14, GPIO_FN_KEYOUT5,
+       GPIO_FN_A15, GPIO_FN_KEYOUT4,
+       GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+       GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+       GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+       GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+       GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+       GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+       GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+       GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+       GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
+       GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
+       GPIO_FN_A26, GPIO_FN_KEYIN6,
+       GPIO_FN_KEYIN7,
+       GPIO_FN_D0_NAF0,
+       GPIO_FN_D1_NAF1,
+       GPIO_FN_D2_NAF2,
+       GPIO_FN_D3_NAF3,
+       GPIO_FN_D4_NAF4,
+       GPIO_FN_D5_NAF5,
+       GPIO_FN_D6_NAF6,
+       GPIO_FN_D7_NAF7,
+       GPIO_FN_D8_NAF8,
+       GPIO_FN_D9_NAF9,
+       GPIO_FN_D10_NAF10,
+       GPIO_FN_D11_NAF11,
+       GPIO_FN_D12_NAF12,
+       GPIO_FN_D13_NAF13,
+       GPIO_FN_D14_NAF14,
+       GPIO_FN_D15_NAF15,
+       GPIO_FN_CS4_,
+       GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
+       GPIO_FN_CS5B_, GPIO_FN_FCE1_,
+       GPIO_FN_CS6B_, GPIO_FN_DACK0,
+       GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+       GPIO_FN_WAIT_, GPIO_FN_DREQ0,
+       GPIO_FN_RD__FSC,
+       GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
+       GPIO_FN_WE1_,
+       GPIO_FN_FRB,
+       GPIO_FN_CKO,
+       GPIO_FN_NBRSTOUT_,
+       GPIO_FN_NBRST_,
+       GPIO_FN_BBIF2_TXD,
+       GPIO_FN_BBIF2_RXD,
+       GPIO_FN_BBIF2_SYNC,
+       GPIO_FN_BBIF2_SCK,
+       GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
+       GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
+       GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
+       GPIO_FN_SCIFA3_TXD,
+       GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
+       GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
+       GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
+       GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
+       GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
+       GPIO_FN_PORT115_I2C_SCL3,
+       GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
+       GPIO_FN_PORT116_I2C_SDA3,
+       GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
+       GPIO_FN_HSI_TX_FLAG,
+       GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
+       GPIO_FN_LCD2D0,
+
+       GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
+       GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
+       GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+       GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
+       GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+       GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
+       GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
+       GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
+       GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
+       GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
+       GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
+       GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+       GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
+       GPIO_FN_LCD2D6,
+       GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+       GPIO_FN_LCD2D7,
+       GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
+       GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+       GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
+       GPIO_FN_LCD2D2,
+       GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+       GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+       GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+       GPIO_FN_LCD2D4,
+       GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
+       GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
+       GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
+       GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
+       GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+       GPIO_FN_VIO_CKO,
+       GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+       GPIO_FN_PORT149_KEYOUT9,
+       GPIO_FN_MFG0_IN2,
+       GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+       GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+       GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+       GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+       GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+       GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
+       GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
+       GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+       GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+       GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
+       GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
+       GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
+       GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+       GPIO_FN_TPU3TO0,
+       GPIO_FN_LCDD0,
+       GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+       GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+       GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+       GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
+       GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+       GPIO_FN_TPU2TO1,
+       GPIO_FN_LCDD6,
+       GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+       GPIO_FN_LCDD8, GPIO_FN_D16,
+       GPIO_FN_LCDD9, GPIO_FN_D17,
+       GPIO_FN_LCDD10, GPIO_FN_D18,
+       GPIO_FN_LCDD11, GPIO_FN_D19,
+       GPIO_FN_LCDD12, GPIO_FN_D20,
+       GPIO_FN_LCDD13, GPIO_FN_D21,
+       GPIO_FN_LCDD14, GPIO_FN_D22,
+       GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+       GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+       GPIO_FN_LCDD17, GPIO_FN_D25,
+       GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+       GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+       GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+       GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+       GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+       GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+       GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
+       GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
+       GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
+       GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+       GPIO_FN_PORT218_VIO_CKOR,
+       GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
+       GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
+       GPIO_FN_LCD2DCK_2,
+       GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
+       GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+       GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
+       GPIO_FN_PORT221_LCD2HSYN,
+       GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
+       GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+
+       GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+       GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
+       GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
+       GPIO_FN_SCIFA1_RXD,
+       GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
+       GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
+       GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
+       GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
+       GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
+       GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+       GPIO_FN_LCD2D20,
+       GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
+       GPIO_FN_LCD2D21,
+       GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
+       GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+       GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
+       GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+       GPIO_FN_SCIFA6_TXD,
+       GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+       GPIO_FN_TPU4TO0,
+       GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+       GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+       GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
+       GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
+       GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
+       GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
+       GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
+       GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+       GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
+       GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+       GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
+       GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+       GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+       GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
+       GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+       GPIO_FN_SDHICLK0,
+       GPIO_FN_SDHICD0,
+       GPIO_FN_SDHID0_0,
+       GPIO_FN_SDHID0_1,
+       GPIO_FN_SDHID0_2,
+       GPIO_FN_SDHID0_3,
+       GPIO_FN_SDHICMD0,
+       GPIO_FN_SDHIWP0,
+       GPIO_FN_SDHICLK1,
+       GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
+       GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
+       GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
+       GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
+       GPIO_FN_SDHICMD1,
+       GPIO_FN_SDHICLK2,
+       GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
+       GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
+       GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
+       GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
+       GPIO_FN_SDHICMD2,
+       GPIO_FN_MMCCLK0,
+       GPIO_FN_MMCD0_0,
+       GPIO_FN_MMCD0_1,
+       GPIO_FN_MMCD0_2,
+       GPIO_FN_MMCD0_3,
+       GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
+       GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
+       GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
+       GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
+       GPIO_FN_MMCCMD0,
+       GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
+       GPIO_FN_MCP_WAIT__MCP_FRB,
+       GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
+       GPIO_FN_MCP_D15_MCP_NAF15,
+       GPIO_FN_MCP_D14_MCP_NAF14,
+       GPIO_FN_MCP_D13_MCP_NAF13,
+       GPIO_FN_MCP_D12_MCP_NAF12,
+       GPIO_FN_MCP_D11_MCP_NAF11,
+       GPIO_FN_MCP_D10_MCP_NAF10,
+       GPIO_FN_MCP_D9_MCP_NAF9,
+       GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
+       GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
+
+       GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
+       GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
+       GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
+       GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
+       GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
+       GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
+       GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
+       GPIO_FN_MCP_NBRSTOUT_,
+       GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
+
+       /* MSEL2 special case */
+       GPIO_FN_TSIF2_TS_XX1,
+       GPIO_FN_TSIF2_TS_XX2,
+       GPIO_FN_TSIF2_TS_XX3,
+       GPIO_FN_TSIF2_TS_XX4,
+       GPIO_FN_TSIF2_TS_XX5,
+       GPIO_FN_TSIF1_TS_XX1,
+       GPIO_FN_TSIF1_TS_XX2,
+       GPIO_FN_TSIF1_TS_XX3,
+       GPIO_FN_TSIF1_TS_XX4,
+       GPIO_FN_TSIF1_TS_XX5,
+       GPIO_FN_TSIF0_TS_XX1,
+       GPIO_FN_TSIF0_TS_XX2,
+       GPIO_FN_TSIF0_TS_XX3,
+       GPIO_FN_TSIF0_TS_XX4,
+       GPIO_FN_TSIF0_TS_XX5,
+       GPIO_FN_MST1_TS_XX1,
+       GPIO_FN_MST1_TS_XX2,
+       GPIO_FN_MST1_TS_XX3,
+       GPIO_FN_MST1_TS_XX4,
+       GPIO_FN_MST1_TS_XX5,
+       GPIO_FN_MST0_TS_XX1,
+       GPIO_FN_MST0_TS_XX2,
+       GPIO_FN_MST0_TS_XX3,
+       GPIO_FN_MST0_TS_XX4,
+       GPIO_FN_MST0_TS_XX5,
+
+       /* MSEL3 special cases */
+       GPIO_FN_SDHI0_VCCQ_MC0_ON,
+       GPIO_FN_SDHI0_VCCQ_MC0_OFF,
+       GPIO_FN_DEBUG_MON_VIO,
+       GPIO_FN_DEBUG_MON_LCDD,
+       GPIO_FN_LCDC_LCDC0,
+       GPIO_FN_LCDC_LCDC1,
+
+       /* MSEL4 special cases */
+       GPIO_FN_IRQ9_MEM_INT,
+       GPIO_FN_IRQ9_MCP_INT,
+       GPIO_FN_A11,
+       GPIO_FN_KEYOUT8,
+       GPIO_FN_TPU4TO3,
+       GPIO_FN_RESETA_N_PU_ON,
+       GPIO_FN_RESETA_N_PU_OFF,
+       GPIO_FN_EDBGREQ_PD,
+       GPIO_FN_EDBGREQ_PU,
+
+       /* Functions with pull-ups */
+       GPIO_FN_KEYIN0_PU,
+       GPIO_FN_KEYIN1_PU,
+       GPIO_FN_KEYIN2_PU,
+       GPIO_FN_KEYIN3_PU,
+       GPIO_FN_KEYIN4_PU,
+       GPIO_FN_KEYIN5_PU,
+       GPIO_FN_KEYIN6_PU,
+       GPIO_FN_KEYIN7_PU,
+       GPIO_FN_SDHID1_0_PU,
+       GPIO_FN_SDHID1_1_PU,
+       GPIO_FN_SDHID1_2_PU,
+       GPIO_FN_SDHID1_3_PU,
+       GPIO_FN_SDHICMD1_PU,
+       GPIO_FN_MMCCMD0_PU,
+       GPIO_FN_MMCCMD1_PU,
+       GPIO_FN_FSIACK_PU,
+       GPIO_FN_FSIAILR_PU,
+       GPIO_FN_FSIAIBT_PU,
+       GPIO_FN_FSIAISLD_PU,
+};
+
+#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h
new file mode 100644 (file)
index 0000000..f4a35ff
--- /dev/null
@@ -0,0 +1,16 @@
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+#if defined(CONFIG_ARM_GIC)
+       gic_raise_softirq(mask, 1);
+#endif
+}
+#endif
index 3ad86b7708e9dcc52064728914564e34ec130a1e..6d6a205bcf90091aec506b6cae8d0af2c2d09767 100644 (file)
@@ -13,6 +13,9 @@
 #ifdef CONFIG_MACH_AP4EVB
 #define MACH_TYPE      MACH_TYPE_AP4EVB
 #include "mach/head-ap4evb.txt"
+#elif CONFIG_MACH_MACKEREL
+#define MACH_TYPE      MACH_TYPE_MACKEREL
+#include "mach/head-mackerel.txt"
 #else
 #error "unsupported board."
 #endif
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
new file mode 100644 (file)
index 0000000..5af2be0
--- /dev/null
@@ -0,0 +1,267 @@
+/*
+ * sh73a0 processor support - INTC hardware block
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sh_intc.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+enum {
+       UNUSED = 0,
+
+       /* interrupt sources INTCS */
+       PINTCS_PINT1, PINTCS_PINT2,
+       RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
+       CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
+       RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
+       KEYSC_KEY, VINT, MSIOF,
+       TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
+       CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
+       CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
+       RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
+       RTDMAC_3_DEI10, RTDMAC_3_DEI11,
+       FRC, GCU, LCDC1, CSIRX,
+       DSITX0_DSITX00, DSITX0_DSITX01,
+       SPU2_SPU0, SPU2_SPU1, FSI,
+       TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
+       TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
+       VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
+       DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
+       MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
+       SPUV,
+
+       /* interrupt groups INTCS */
+       RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
+       DSITX0, SPU2, TMU1, MSU,
+};
+
+static struct intc_vect intcs_vectors[] = {
+       INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
+       INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
+       INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
+       INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
+       INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
+       INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
+       INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
+       INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
+       INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
+       INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
+       INTCS_VECT(MSIOF, 0x0d20),
+       INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
+       INTCS_VECT(TMU0_TUNI02, 0x0ec0),
+       INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
+       INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
+       INTCS_VECT(MSUG, 0x0f80),
+       INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
+       INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
+       INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
+       INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
+       INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
+       INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
+       INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
+       INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
+       INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
+       INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
+       INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
+       INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
+       INTCS_VECT(FSI, 0x1840),
+       INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
+       INTCS_VECT(TMU1_TUNI12, 0x1940),
+       INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
+       INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
+       INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
+       INTCS_VECT(SCUW, 0x1b40),
+       INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
+       INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
+       INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
+       INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
+       INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
+       INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
+       INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
+       INTCS_VECT(SPUV, 0x2300),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+       INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
+                  RTDMAC_0_DEI2, RTDMAC_0_DEI3),
+       INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
+       INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
+                  RTDMAC_2_DEI8, RTDMAC_2_DEI9),
+       INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
+       INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
+       INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
+       INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
+       INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] = {
+       { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
+         { 0, 0, 0, CEU,
+           0, 0, 0, 0 } },
+       { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
+         { 0, 0, 0, VPU,
+           BBIF2, 0, 0, MFI } },
+       { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
+         { 0, 0, 0, _2DDMAC_2DDM0,
+           0, ASA, PEP, ICB } },
+       { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
+         { 0, 0, 0, CTI,
+           JPU_JPEG, 0, LCRC, LCDC } },
+       { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
+         { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
+           RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
+       { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
+         { 0, 0, MSIOF, 0,
+           _3DG_SGX543, 0, 0, 0 } },
+       { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
+         { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
+           0, 0, 0, 0 } },
+       { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
+         { 0, 0, 0, 0,
+           0, MSU_MSU, MSU_MSU2, MSUG } },
+       { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
+         { 0, RWDT0, CMT2, CMT0,
+           0, 0, 0, 0 } },
+       { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
+         { 0, 0, 0, 0,
+           0, TSIF1, LMB, TSIF0 } },
+       { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
+         { 0, 0, 0, 0,
+           0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
+       { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
+         { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
+           RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
+       { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
+         { FRC, 0, 0, GCU,
+           LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
+       { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
+         { SPU2_SPU0, SPU2_SPU1, FSI, 0,
+           0, 0, 0, 0 } },
+       { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
+         { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
+           TSIF2, CMT4, 0, 0 } },
+       { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
+         { MFIS2, CPORTS2R, 0, 0,
+           0, 0, 0, TSG } },
+       { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
+         { DMASCH1, 0, SCUW, VIO60,
+           VIO61, CEU21, 0, CSI21 } },
+       { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
+         { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
+           EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
+       { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
+         { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
+           0, 0, 0, 0  } },
+       { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
+         { SPUV, 0, 0, 0,
+           0, 0, 0, 0  } },
+};
+
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+       { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
+       { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
+       { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
+       { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
+                                             0, 0 } },
+       { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
+       { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
+                                             CMT2, CMT0 } },
+       { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
+                                             TMU0_TUNI02, TSIF1 } },
+       { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
+       { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
+       { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
+       { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
+       { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
+       { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
+       { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
+       { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
+       { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
+       { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
+       { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
+       { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
+       { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
+       { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
+       { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
+       { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
+                                              DISP, DSRV } },
+       { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
+                                              MSTIF0_MST00I, MSTIF0_MST01I } },
+       { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
+                                              0, 0 } },
+       { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+       [0] = {
+               .start  = 0xffd20000,
+               .end    = 0xffd201ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = 0xffd50000,
+               .end    = 0xffd501ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [2] = {
+               .start  = 0xffd60000,
+               .end    = 0xffd601ff,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+       .name = "sh73a0-intcs",
+       .resource = intcs_resources,
+       .num_resources = ARRAY_SIZE(intcs_resources),
+       .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+                          intcs_prio_registers, NULL, NULL),
+};
+
+static struct irqaction sh73a0_intcs_cascade;
+
+static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
+{
+       unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
+
+       generic_handle_irq(intcs_evt2irq(evtcodeas));
+
+       return IRQ_HANDLED;
+}
+
+void __init sh73a0_init_irq(void)
+{
+       void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+
+       gic_dist_init(0, __io(0xf0001000), 29);
+       gic_cpu_init(0, __io(0xf0000100));
+
+       register_intc_controller(&intcs_desc);
+
+       /* demux using INTEVTSA */
+       sh73a0_intcs_cascade.name = "INTCS cascade";
+       sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
+       sh73a0_intcs_cascade.dev_id = intevtsa;
+       setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
+}
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
new file mode 100644 (file)
index 0000000..2111c28
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile - local timer portion
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+       evt->irq = 29;
+       twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
new file mode 100644 (file)
index 0000000..3eed44e
--- /dev/null
@@ -0,0 +1,2746 @@
+/*
+ * sh73a0 processor support - PFC hardware block
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Copyright (C) 2010 NISHIMOTO Hiroki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/sh73a0.h>
+
+#define _1(fn, pfx, sfx) fn(pfx, sfx)
+
+#define _10(fn, pfx, sfx)                              \
+       _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx),       \
+       _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx),       \
+       _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx),       \
+       _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx),       \
+       _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
+
+#define _310(fn, pfx, sfx)                             \
+       _10(fn, pfx,    sfx), _10(fn, pfx##1, sfx),     \
+       _10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx),     \
+       _10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx),     \
+       _10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx),     \
+       _10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx),     \
+       _10(fn, pfx##10, sfx),                          \
+       _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx),   \
+       _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx),   \
+       _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx),   \
+       _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx),   \
+       _1(fn, pfx##118, sfx),                          \
+       _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx),   \
+       _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx),   \
+       _10(fn, pfx##15, sfx),                          \
+       _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx),   \
+       _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx),   \
+       _1(fn, pfx##164, sfx),                          \
+       _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx),   \
+       _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx),   \
+       _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx),   \
+       _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx),   \
+       _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx),   \
+       _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx),   \
+       _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx),   \
+       _10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx),   \
+       _1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx),   \
+       _1(fn, pfx##282, sfx),                          \
+       _1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx),   \
+       _10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx)
+
+#define _PORT(pfx, sfx) pfx##_##sfx
+#define PORT_310(str) _310(_PORT, PORT, str)
+
+enum {
+       PINMUX_RESERVED = 0,
+
+       PINMUX_DATA_BEGIN,
+       PORT_310(DATA),                 /* PORT0_DATA -> PORT309_DATA */
+       PINMUX_DATA_END,
+
+       PINMUX_INPUT_BEGIN,
+       PORT_310(IN),                   /* PORT0_IN -> PORT309_IN */
+       PINMUX_INPUT_END,
+
+       PINMUX_INPUT_PULLUP_BEGIN,
+       PORT_310(IN_PU),                /* PORT0_IN_PU -> PORT309_IN_PU */
+       PINMUX_INPUT_PULLUP_END,
+
+       PINMUX_INPUT_PULLDOWN_BEGIN,
+       PORT_310(IN_PD),                /* PORT0_IN_PD -> PORT309_IN_PD */
+       PINMUX_INPUT_PULLDOWN_END,
+
+       PINMUX_OUTPUT_BEGIN,
+       PORT_310(OUT),                  /* PORT0_OUT -> PORT309_OUT */
+       PINMUX_OUTPUT_END,
+
+       PINMUX_FUNCTION_BEGIN,
+       PORT_310(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
+       PORT_310(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
+       PORT_310(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
+       PORT_310(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
+       PORT_310(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
+       PORT_310(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
+       PORT_310(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
+       PORT_310(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
+       PORT_310(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
+       PORT_310(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
+
+       MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+       MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+       MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+       MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+       MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+       MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+       MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+       MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+       MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+       MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+       MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+       MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+       MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+       MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+       MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+       MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+       MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+       MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+       MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+       MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+       MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+       MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+       MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+       MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+       MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+       MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+       MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+       MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+       MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+       MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+       MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+       MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+       MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+       MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+       MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+       MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+       MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+       MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+       MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+       MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+       MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+       MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+       PINMUX_FUNCTION_END,
+
+       PINMUX_MARK_BEGIN,
+       /* Hardware manual Table 25-1 (Function 0-7) */
+       VBUS_0_MARK,
+       GPI0_MARK,
+       GPI1_MARK,
+       GPI2_MARK,
+       GPI3_MARK,
+       GPI4_MARK,
+       GPI5_MARK,
+       GPI6_MARK,
+       GPI7_MARK,
+       SCIFA7_RXD_MARK,
+       SCIFA7_CTS__MARK,
+       GPO7_MARK, MFG0_OUT2_MARK,
+       GPO6_MARK, MFG1_OUT2_MARK,
+       GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
+       SCIFA0_TXD_MARK,
+       SCIFA7_TXD_MARK,
+       SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
+       GPO0_MARK,
+       GPO1_MARK,
+       GPO2_MARK, STATUS0_MARK,
+       GPO3_MARK, STATUS1_MARK,
+       GPO4_MARK, STATUS2_MARK,
+       VINT_MARK,
+       TCKON_MARK,
+       XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
+       MFG0_OUT1_MARK, PORT27_IROUT_MARK,
+       XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
+       PORT28_TPU1TO1_MARK,
+       SIM_RST_MARK, PORT29_TPU1TO1_MARK,
+       SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
+       SIM_D_MARK, PORT31_IROUT_MARK,
+       SCIFA4_TXD_MARK,
+       SCIFA4_RXD_MARK, XWUP_MARK,
+       SCIFA4_RTS__MARK,
+       SCIFA4_CTS__MARK,
+       FSIBOBT_MARK, FSIBIBT_MARK,
+       FSIBOLR_MARK, FSIBILR_MARK,
+       FSIBOSLD_MARK,
+       FSIBISLD_MARK,
+       VACK_MARK,
+       XTAL1L_MARK,
+       SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
+       SCIFA0_RXD_MARK,
+       SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
+       FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
+       FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
+       FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
+       FSICISLD_MARK, FSIDISLD_MARK,
+       FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
+       FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
+
+       FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
+       FSIAOSLD_MARK, BBIF2_TXD2_MARK,
+       FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
+       PORT53_FSICSPDIF_MARK,
+       FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
+       FSICCK_MARK, FSICOMC_MARK,
+       FSIAISLD_MARK, TPU0TO0_MARK,
+       A0_MARK, BS__MARK,
+       A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
+       A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
+       A14_MARK, KEYOUT5_MARK,
+       A15_MARK, KEYOUT4_MARK,
+       A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
+       A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
+       A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
+       A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
+       A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
+       A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
+       A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
+       A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
+       A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
+       A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
+       A26_MARK, KEYIN6_MARK,
+       KEYIN7_MARK,
+       D0_NAF0_MARK,
+       D1_NAF1_MARK,
+       D2_NAF2_MARK,
+       D3_NAF3_MARK,
+       D4_NAF4_MARK,
+       D5_NAF5_MARK,
+       D6_NAF6_MARK,
+       D7_NAF7_MARK,
+       D8_NAF8_MARK,
+       D9_NAF9_MARK,
+       D10_NAF10_MARK,
+       D11_NAF11_MARK,
+       D12_NAF12_MARK,
+       D13_NAF13_MARK,
+       D14_NAF14_MARK,
+       D15_NAF15_MARK,
+       CS4__MARK,
+       CS5A__MARK, PORT91_RDWR_MARK,
+       CS5B__MARK, FCE1__MARK,
+       CS6B__MARK, DACK0_MARK,
+       FCE0__MARK, CS6A__MARK,
+       WAIT__MARK, DREQ0_MARK,
+       RD__FSC_MARK,
+       WE0__FWE_MARK, RDWR_FWE_MARK,
+       WE1__MARK,
+       FRB_MARK,
+       CKO_MARK,
+       NBRSTOUT__MARK,
+       NBRST__MARK,
+       BBIF2_TXD_MARK,
+       BBIF2_RXD_MARK,
+       BBIF2_SYNC_MARK,
+       BBIF2_SCK_MARK,
+       SCIFA3_CTS__MARK, MFG3_IN2_MARK,
+       SCIFA3_RXD_MARK, MFG3_IN1_MARK,
+       BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
+       SCIFA3_TXD_MARK,
+       HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
+       HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
+       HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
+       HSI_TX_READY_MARK, BBIF1_TXD_MARK,
+       HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
+       PORT115_I2C_SCL3_MARK,
+       HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
+       PORT116_I2C_SDA3_MARK,
+       HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
+       HSI_TX_FLAG_MARK,
+       VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
+
+       VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
+       VIO2_HD_MARK, LCD2D1_MARK,
+       VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
+       VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
+       PORT131_KEYOUT11_MARK, LCD2D11_MARK,
+       VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
+       PORT132_KEYOUT10_MARK, LCD2D12_MARK,
+       VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
+       VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
+       VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
+       VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
+       VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
+       VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
+       VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
+       VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
+       VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
+       VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
+       VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
+       VIO2_D5_MARK, LCD2D3_MARK,
+       VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
+       VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
+       PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
+       VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
+       LCD2D18_MARK,
+       VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
+       VIO_CKO_MARK,
+       A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
+       MFG0_IN2_MARK,
+       TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
+       TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
+       TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
+       SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
+       SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
+       SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
+       SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
+       DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
+       PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
+       PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
+       PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
+       PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
+       PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
+       LCDD0_MARK,
+       LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
+       LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
+       LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
+       LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
+       LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
+       LCDD6_MARK,
+       LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
+       LCDD8_MARK, D16_MARK,
+       LCDD9_MARK, D17_MARK,
+       LCDD10_MARK, D18_MARK,
+       LCDD11_MARK, D19_MARK,
+       LCDD12_MARK, D20_MARK,
+       LCDD13_MARK, D21_MARK,
+       LCDD14_MARK, D22_MARK,
+       LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
+       LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
+       LCDD17_MARK, D25_MARK,
+       LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
+       LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
+       LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
+       LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
+       LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
+       LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
+       LCDDCK_MARK, LCDWR__MARK,
+       LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
+       VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
+       LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
+       PORT218_VIO_CKOR_MARK,
+       LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
+       MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
+       LCDVSYN_MARK, LCDVSYN2_MARK,
+       LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
+       MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
+       LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
+       VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
+
+       SCIFA1_TXD_MARK, OVCN2_MARK,
+       EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
+       SCIFA1_RTS__MARK, IDIN_MARK,
+       SCIFA1_RXD_MARK,
+       SCIFA1_CTS__MARK, MFG1_IN1_MARK,
+       MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
+       MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
+       MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
+       MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
+       MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
+       MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
+       MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
+       MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
+       MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
+       MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
+       SCIFA6_TXD_MARK,
+       PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
+       PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
+       PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
+       PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
+       MSIOF2R_RXD_MARK,
+       PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
+       MSIOF2R_TXD_MARK,
+       PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
+       TPU1TO0_MARK,
+       PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
+       TPU3TO1_MARK,
+       PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
+       TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
+       PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
+       MSIOF2R_TSYNC_MARK,
+       SDHICLK0_MARK,
+       SDHICD0_MARK,
+       SDHID0_0_MARK,
+       SDHID0_1_MARK,
+       SDHID0_2_MARK,
+       SDHID0_3_MARK,
+       SDHICMD0_MARK,
+       SDHIWP0_MARK,
+       SDHICLK1_MARK,
+       SDHID1_0_MARK, TS_SPSYNC2_MARK,
+       SDHID1_1_MARK, TS_SDAT2_MARK,
+       SDHID1_2_MARK, TS_SDEN2_MARK,
+       SDHID1_3_MARK, TS_SCK2_MARK,
+       SDHICMD1_MARK,
+       SDHICLK2_MARK,
+       SDHID2_0_MARK, TS_SPSYNC4_MARK,
+       SDHID2_1_MARK, TS_SDAT4_MARK,
+       SDHID2_2_MARK, TS_SDEN4_MARK,
+       SDHID2_3_MARK, TS_SCK4_MARK,
+       SDHICMD2_MARK,
+       MMCCLK0_MARK,
+       MMCD0_0_MARK,
+       MMCD0_1_MARK,
+       MMCD0_2_MARK,
+       MMCD0_3_MARK,
+       MMCD0_4_MARK, TS_SPSYNC5_MARK,
+       MMCD0_5_MARK, TS_SDAT5_MARK,
+       MMCD0_6_MARK, TS_SDEN5_MARK,
+       MMCD0_7_MARK, TS_SCK5_MARK,
+       MMCCMD0_MARK,
+       RESETOUTS__MARK, EXTAL2OUT_MARK,
+       MCP_WAIT__MCP_FRB_MARK,
+       MCP_CKO_MARK, MMCCLK1_MARK,
+       MCP_D15_MCP_NAF15_MARK,
+       MCP_D14_MCP_NAF14_MARK,
+       MCP_D13_MCP_NAF13_MARK,
+       MCP_D12_MCP_NAF12_MARK,
+       MCP_D11_MCP_NAF11_MARK,
+       MCP_D10_MCP_NAF10_MARK,
+       MCP_D9_MCP_NAF9_MARK,
+       MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
+       MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
+
+       MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
+       MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
+       MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
+       MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
+       MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
+       MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
+       MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
+       MCP_NBRSTOUT__MARK,
+       MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
+
+       /* MSEL2 special cases */
+       TSIF2_TS_XX1_MARK,
+       TSIF2_TS_XX2_MARK,
+       TSIF2_TS_XX3_MARK,
+       TSIF2_TS_XX4_MARK,
+       TSIF2_TS_XX5_MARK,
+       TSIF1_TS_XX1_MARK,
+       TSIF1_TS_XX2_MARK,
+       TSIF1_TS_XX3_MARK,
+       TSIF1_TS_XX4_MARK,
+       TSIF1_TS_XX5_MARK,
+       TSIF0_TS_XX1_MARK,
+       TSIF0_TS_XX2_MARK,
+       TSIF0_TS_XX3_MARK,
+       TSIF0_TS_XX4_MARK,
+       TSIF0_TS_XX5_MARK,
+       MST1_TS_XX1_MARK,
+       MST1_TS_XX2_MARK,
+       MST1_TS_XX3_MARK,
+       MST1_TS_XX4_MARK,
+       MST1_TS_XX5_MARK,
+       MST0_TS_XX1_MARK,
+       MST0_TS_XX2_MARK,
+       MST0_TS_XX3_MARK,
+       MST0_TS_XX4_MARK,
+       MST0_TS_XX5_MARK,
+
+       /* MSEL3 special cases */
+       SDHI0_VCCQ_MC0_ON_MARK,
+       SDHI0_VCCQ_MC0_OFF_MARK,
+       DEBUG_MON_VIO_MARK,
+       DEBUG_MON_LCDD_MARK,
+       LCDC_LCDC0_MARK,
+       LCDC_LCDC1_MARK,
+
+       /* MSEL4 special cases */
+       IRQ9_MEM_INT_MARK,
+       IRQ9_MCP_INT_MARK,
+       A11_MARK,
+       KEYOUT8_MARK,
+       TPU4TO3_MARK,
+       RESETA_N_PU_ON_MARK,
+       RESETA_N_PU_OFF_MARK,
+       EDBGREQ_PD_MARK,
+       EDBGREQ_PU_MARK,
+
+       /* Functions with pull-ups */
+       KEYIN0_PU_MARK,
+       KEYIN1_PU_MARK,
+       KEYIN2_PU_MARK,
+       KEYIN3_PU_MARK,
+       KEYIN4_PU_MARK,
+       KEYIN5_PU_MARK,
+       KEYIN6_PU_MARK,
+       KEYIN7_PU_MARK,
+       SDHID1_0_PU_MARK,
+       SDHID1_1_PU_MARK,
+       SDHID1_2_PU_MARK,
+       SDHID1_3_PU_MARK,
+       SDHICMD1_PU_MARK,
+       MMCCMD0_PU_MARK,
+       MMCCMD1_PU_MARK,
+       FSIACK_PU_MARK,
+       FSIAILR_PU_MARK,
+       FSIAIBT_PU_MARK,
+       FSIAISLD_PU_MARK,
+
+       PINMUX_MARK_END,
+};
+
+#define PORT_DATA_I(nr)        \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
+
+#define PORT_DATA_I_PD(nr)     \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                               PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_I_PU(nr)     \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                               PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_I_PU_PD(nr)  \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                               PORT##nr##_IN, PORT##nr##_IN_PD,        \
+                               PORT##nr##_IN_PU)
+
+#define PORT_DATA_O(nr)        \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                               PORT##nr##_OUT)
+
+#define PORT_DATA_IO(nr)       \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                               PORT##nr##_OUT, PORT##nr##_IN)
+
+#define PORT_DATA_IO_PD(nr)    \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                               PORT##nr##_OUT, PORT##nr##_IN,          \
+                               PORT##nr##_IN_PD)
+
+#define PORT_DATA_IO_PU(nr)    \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                               PORT##nr##_OUT, PORT##nr##_IN,          \
+                               PORT##nr##_IN_PU)
+
+#define PORT_DATA_IO_PU_PD(nr) \
+       PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                               PORT##nr##_OUT, PORT##nr##_IN,          \
+                               PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+static pinmux_enum_t pinmux_data[] = {
+       /* specify valid pin states for each pin in GPIO mode */
+
+       /* Table 25-1 (I/O and Pull U/D) */
+       PORT_DATA_I_PD(0),
+       PORT_DATA_I_PU(1),
+       PORT_DATA_I_PU(2),
+       PORT_DATA_I_PU(3),
+       PORT_DATA_I_PU(4),
+       PORT_DATA_I_PU(5),
+       PORT_DATA_I_PU(6),
+       PORT_DATA_I_PU(7),
+       PORT_DATA_I_PU(8),
+       PORT_DATA_I_PD(9),
+       PORT_DATA_I_PD(10),
+       PORT_DATA_I_PU_PD(11),
+       PORT_DATA_IO_PU_PD(12),
+       PORT_DATA_IO_PU_PD(13),
+       PORT_DATA_IO_PU_PD(14),
+       PORT_DATA_IO_PU_PD(15),
+       PORT_DATA_IO_PD(16),
+       PORT_DATA_IO_PD(17),
+       PORT_DATA_IO_PU(18),
+       PORT_DATA_IO_PU(19),
+       PORT_DATA_O(20),
+       PORT_DATA_O(21),
+       PORT_DATA_O(22),
+       PORT_DATA_O(23),
+       PORT_DATA_O(24),
+       PORT_DATA_I_PD(25),
+       PORT_DATA_I_PD(26),
+       PORT_DATA_IO_PU(27),
+       PORT_DATA_IO_PU(28),
+       PORT_DATA_IO_PD(29),
+       PORT_DATA_IO_PD(30),
+       PORT_DATA_IO_PU(31),
+       PORT_DATA_IO_PD(32),
+       PORT_DATA_I_PU_PD(33),
+       PORT_DATA_IO_PD(34),
+       PORT_DATA_I_PU_PD(35),
+       PORT_DATA_IO_PD(36),
+       PORT_DATA_IO(37),
+       PORT_DATA_O(38),
+       PORT_DATA_I_PU(39),
+       PORT_DATA_I_PU_PD(40),
+       PORT_DATA_O(41),
+       PORT_DATA_IO_PD(42),
+       PORT_DATA_IO_PU_PD(43),
+       PORT_DATA_IO_PU_PD(44),
+       PORT_DATA_IO_PD(45),
+       PORT_DATA_IO_PD(46),
+       PORT_DATA_IO_PD(47),
+       PORT_DATA_I_PD(48),
+       PORT_DATA_IO_PU_PD(49),
+       PORT_DATA_IO_PD(50),
+
+       PORT_DATA_IO_PD(51),
+       PORT_DATA_O(52),
+       PORT_DATA_IO_PU_PD(53),
+       PORT_DATA_IO_PU_PD(54),
+       PORT_DATA_IO_PD(55),
+       PORT_DATA_I_PU_PD(56),
+       PORT_DATA_IO(57),
+       PORT_DATA_IO(58),
+       PORT_DATA_IO(59),
+       PORT_DATA_IO(60),
+       PORT_DATA_IO(61),
+       PORT_DATA_IO_PD(62),
+       PORT_DATA_IO_PD(63),
+       PORT_DATA_IO_PU_PD(64),
+       PORT_DATA_IO_PD(65),
+       PORT_DATA_IO_PU_PD(66),
+       PORT_DATA_IO_PU_PD(67),
+       PORT_DATA_IO_PU_PD(68),
+       PORT_DATA_IO_PU_PD(69),
+       PORT_DATA_IO_PU_PD(70),
+       PORT_DATA_IO_PU_PD(71),
+       PORT_DATA_IO_PU_PD(72),
+       PORT_DATA_I_PU_PD(73),
+       PORT_DATA_IO_PU(74),
+       PORT_DATA_IO_PU(75),
+       PORT_DATA_IO_PU(76),
+       PORT_DATA_IO_PU(77),
+       PORT_DATA_IO_PU(78),
+       PORT_DATA_IO_PU(79),
+       PORT_DATA_IO_PU(80),
+       PORT_DATA_IO_PU(81),
+       PORT_DATA_IO_PU(82),
+       PORT_DATA_IO_PU(83),
+       PORT_DATA_IO_PU(84),
+       PORT_DATA_IO_PU(85),
+       PORT_DATA_IO_PU(86),
+       PORT_DATA_IO_PU(87),
+       PORT_DATA_IO_PU(88),
+       PORT_DATA_IO_PU(89),
+       PORT_DATA_O(90),
+       PORT_DATA_IO_PU(91),
+       PORT_DATA_O(92),
+       PORT_DATA_IO_PU(93),
+       PORT_DATA_O(94),
+       PORT_DATA_I_PU_PD(95),
+       PORT_DATA_IO(96),
+       PORT_DATA_IO(97),
+       PORT_DATA_IO(98),
+       PORT_DATA_I_PU(99),
+       PORT_DATA_O(100),
+       PORT_DATA_O(101),
+       PORT_DATA_I_PU(102),
+       PORT_DATA_IO_PD(103),
+       PORT_DATA_I_PU_PD(104),
+       PORT_DATA_I_PD(105),
+       PORT_DATA_I_PD(106),
+       PORT_DATA_I_PU_PD(107),
+       PORT_DATA_I_PU_PD(108),
+       PORT_DATA_IO_PD(109),
+       PORT_DATA_IO_PD(110),
+       PORT_DATA_IO_PU_PD(111),
+       PORT_DATA_IO_PU_PD(112),
+       PORT_DATA_IO_PU_PD(113),
+       PORT_DATA_IO_PD(114),
+       PORT_DATA_IO_PU(115),
+       PORT_DATA_IO_PU(116),
+       PORT_DATA_IO_PU_PD(117),
+       PORT_DATA_IO_PU_PD(118),
+       PORT_DATA_IO_PD(128),
+
+       PORT_DATA_IO_PD(129),
+       PORT_DATA_IO_PU_PD(130),
+       PORT_DATA_IO_PD(131),
+       PORT_DATA_IO_PD(132),
+       PORT_DATA_IO_PD(133),
+       PORT_DATA_IO_PU_PD(134),
+       PORT_DATA_IO_PU_PD(135),
+       PORT_DATA_IO_PU_PD(136),
+       PORT_DATA_IO_PU_PD(137),
+       PORT_DATA_IO_PD(138),
+       PORT_DATA_IO_PD(139),
+       PORT_DATA_IO_PD(140),
+       PORT_DATA_IO_PD(141),
+       PORT_DATA_IO_PD(142),
+       PORT_DATA_IO_PD(143),
+       PORT_DATA_IO_PU_PD(144),
+       PORT_DATA_IO_PD(145),
+       PORT_DATA_IO_PU_PD(146),
+       PORT_DATA_IO_PU_PD(147),
+       PORT_DATA_IO_PU_PD(148),
+       PORT_DATA_IO_PU_PD(149),
+       PORT_DATA_I_PU_PD(150),
+       PORT_DATA_IO_PU_PD(151),
+       PORT_DATA_IO_PU_PD(152),
+       PORT_DATA_IO_PD(153),
+       PORT_DATA_IO_PD(154),
+       PORT_DATA_I_PU_PD(155),
+       PORT_DATA_IO_PU_PD(156),
+       PORT_DATA_I_PD(157),
+       PORT_DATA_IO_PD(158),
+       PORT_DATA_IO_PU_PD(159),
+       PORT_DATA_IO_PU_PD(160),
+       PORT_DATA_I_PU_PD(161),
+       PORT_DATA_I_PU_PD(162),
+       PORT_DATA_IO_PU_PD(163),
+       PORT_DATA_I_PU_PD(164),
+       PORT_DATA_IO_PD(192),
+       PORT_DATA_IO_PU_PD(193),
+       PORT_DATA_IO_PD(194),
+       PORT_DATA_IO_PU_PD(195),
+       PORT_DATA_IO_PD(196),
+       PORT_DATA_IO_PD(197),
+       PORT_DATA_IO_PD(198),
+       PORT_DATA_IO_PD(199),
+       PORT_DATA_IO_PU_PD(200),
+       PORT_DATA_IO_PU_PD(201),
+       PORT_DATA_IO_PU_PD(202),
+       PORT_DATA_IO_PU_PD(203),
+       PORT_DATA_IO_PU_PD(204),
+       PORT_DATA_IO_PU_PD(205),
+       PORT_DATA_IO_PU_PD(206),
+       PORT_DATA_IO_PD(207),
+       PORT_DATA_IO_PD(208),
+       PORT_DATA_IO_PD(209),
+       PORT_DATA_IO_PD(210),
+       PORT_DATA_IO_PD(211),
+       PORT_DATA_IO_PD(212),
+       PORT_DATA_IO_PD(213),
+       PORT_DATA_IO_PU_PD(214),
+       PORT_DATA_IO_PU_PD(215),
+       PORT_DATA_IO_PD(216),
+       PORT_DATA_IO_PD(217),
+       PORT_DATA_O(218),
+       PORT_DATA_IO_PD(219),
+       PORT_DATA_IO_PD(220),
+       PORT_DATA_IO_PU_PD(221),
+       PORT_DATA_IO_PU_PD(222),
+       PORT_DATA_I_PU_PD(223),
+       PORT_DATA_I_PU_PD(224),
+
+       PORT_DATA_IO_PU_PD(225),
+       PORT_DATA_O(226),
+       PORT_DATA_IO_PU_PD(227),
+       PORT_DATA_I_PU_PD(228),
+       PORT_DATA_I_PD(229),
+       PORT_DATA_IO(230),
+       PORT_DATA_IO_PU_PD(231),
+       PORT_DATA_IO_PU_PD(232),
+       PORT_DATA_I_PU_PD(233),
+       PORT_DATA_IO_PU_PD(234),
+       PORT_DATA_IO_PU_PD(235),
+       PORT_DATA_IO_PU_PD(236),
+       PORT_DATA_IO_PD(237),
+       PORT_DATA_IO_PU_PD(238),
+       PORT_DATA_IO_PU_PD(239),
+       PORT_DATA_IO_PU_PD(240),
+       PORT_DATA_O(241),
+       PORT_DATA_I_PD(242),
+       PORT_DATA_IO_PU_PD(243),
+       PORT_DATA_IO_PU_PD(244),
+       PORT_DATA_IO_PU_PD(245),
+       PORT_DATA_IO_PU_PD(246),
+       PORT_DATA_IO_PU_PD(247),
+       PORT_DATA_IO_PU_PD(248),
+       PORT_DATA_IO_PU_PD(249),
+       PORT_DATA_IO_PU_PD(250),
+       PORT_DATA_IO_PU_PD(251),
+       PORT_DATA_IO_PU_PD(252),
+       PORT_DATA_IO_PU_PD(253),
+       PORT_DATA_IO_PU_PD(254),
+       PORT_DATA_IO_PU_PD(255),
+       PORT_DATA_IO_PU_PD(256),
+       PORT_DATA_IO_PU_PD(257),
+       PORT_DATA_IO_PU_PD(258),
+       PORT_DATA_IO_PU_PD(259),
+       PORT_DATA_IO_PU_PD(260),
+       PORT_DATA_IO_PU_PD(261),
+       PORT_DATA_IO_PU_PD(262),
+       PORT_DATA_IO_PU_PD(263),
+       PORT_DATA_IO_PU_PD(264),
+       PORT_DATA_IO_PU_PD(265),
+       PORT_DATA_IO_PU_PD(266),
+       PORT_DATA_IO_PU_PD(267),
+       PORT_DATA_IO_PU_PD(268),
+       PORT_DATA_IO_PU_PD(269),
+       PORT_DATA_IO_PU_PD(270),
+       PORT_DATA_IO_PU_PD(271),
+       PORT_DATA_IO_PU_PD(272),
+       PORT_DATA_IO_PU_PD(273),
+       PORT_DATA_IO_PU_PD(274),
+       PORT_DATA_IO_PU_PD(275),
+       PORT_DATA_IO_PU_PD(276),
+       PORT_DATA_IO_PU_PD(277),
+       PORT_DATA_IO_PU_PD(278),
+       PORT_DATA_IO_PU_PD(279),
+       PORT_DATA_IO_PU_PD(280),
+       PORT_DATA_O(281),
+       PORT_DATA_O(282),
+       PORT_DATA_I_PU(288),
+       PORT_DATA_IO_PU_PD(289),
+       PORT_DATA_IO_PU_PD(290),
+       PORT_DATA_IO_PU_PD(291),
+       PORT_DATA_IO_PU_PD(292),
+       PORT_DATA_IO_PU_PD(293),
+       PORT_DATA_IO_PU_PD(294),
+       PORT_DATA_IO_PU_PD(295),
+       PORT_DATA_IO_PU_PD(296),
+       PORT_DATA_IO_PU_PD(297),
+       PORT_DATA_IO_PU_PD(298),
+
+       PORT_DATA_IO_PU_PD(299),
+       PORT_DATA_IO_PU_PD(300),
+       PORT_DATA_IO_PU_PD(301),
+       PORT_DATA_IO_PU_PD(302),
+       PORT_DATA_IO_PU_PD(303),
+       PORT_DATA_IO_PU_PD(304),
+       PORT_DATA_IO_PU_PD(305),
+       PORT_DATA_O(306),
+       PORT_DATA_O(307),
+       PORT_DATA_I_PU(308),
+       PORT_DATA_O(309),
+
+       /* Table 25-1 (Function 0-7) */
+       PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
+       PINMUX_DATA(GPI0_MARK, PORT1_FN1),
+       PINMUX_DATA(GPI1_MARK, PORT2_FN1),
+       PINMUX_DATA(GPI2_MARK, PORT3_FN1),
+       PINMUX_DATA(GPI3_MARK, PORT4_FN1),
+       PINMUX_DATA(GPI4_MARK, PORT5_FN1),
+       PINMUX_DATA(GPI5_MARK, PORT6_FN1),
+       PINMUX_DATA(GPI6_MARK, PORT7_FN1),
+       PINMUX_DATA(GPI7_MARK, PORT8_FN1),
+       PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
+       PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
+       PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
+       PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
+       PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
+       PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
+       PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
+       PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
+       PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
+       PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
+       PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
+       PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
+       PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
+       PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
+       PINMUX_DATA(GPO0_MARK, PORT20_FN1),
+       PINMUX_DATA(GPO1_MARK, PORT21_FN1),
+       PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
+       PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
+       PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
+       PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
+       PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
+       PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
+       PINMUX_DATA(VINT_MARK, PORT25_FN1),
+       PINMUX_DATA(TCKON_MARK, PORT26_FN1),
+       PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
+       PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
+               MSEL2CR_MSEL16_1), \
+       PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
+               MSEL2CR_MSEL18_0), \
+       PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
+       PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
+       PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
+       PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
+               MSEL2CR_MSEL16_1), \
+       PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
+               MSEL2CR_MSEL18_0), \
+       PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
+       PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
+       PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
+       PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
+       PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
+       PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
+       PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
+       PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
+       PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
+       PINMUX_DATA(XWUP_MARK, PORT33_FN3),
+       PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
+       PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
+       PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
+       PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
+       PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
+       PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
+       PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
+       PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
+       PINMUX_DATA(VACK_MARK, PORT40_FN1),
+       PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
+       PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
+       PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
+       PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
+       PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
+       PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
+       PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
+       PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
+       PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
+       PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
+       PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
+       PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
+       PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
+       PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
+       PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
+       PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
+       PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
+       PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
+       PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
+       PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
+       PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
+       PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
+       PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
+       PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
+       PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
+       PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
+
+       PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
+       PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
+       PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
+       PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
+       PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
+       PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
+       PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
+       PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
+       PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
+       PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
+       PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
+       PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
+       PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
+       PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
+       PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
+       PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
+       PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
+       PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
+       PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
+       PINMUX_DATA(A0_MARK, PORT57_FN1), \
+       PINMUX_DATA(BS__MARK, PORT57_FN2),
+       PINMUX_DATA(A12_MARK, PORT58_FN1), \
+       PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
+       PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
+       PINMUX_DATA(A13_MARK, PORT59_FN1), \
+       PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
+       PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
+       PINMUX_DATA(A14_MARK, PORT60_FN1), \
+       PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
+       PINMUX_DATA(A15_MARK, PORT61_FN1), \
+       PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
+       PINMUX_DATA(A16_MARK, PORT62_FN1), \
+       PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
+       PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A17_MARK, PORT63_FN1), \
+       PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
+       PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A18_MARK, PORT64_FN1), \
+       PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
+       PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A19_MARK, PORT65_FN1), \
+       PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
+       PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A20_MARK, PORT66_FN1), \
+       PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
+       PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A21_MARK, PORT67_FN1), \
+       PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
+       PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A22_MARK, PORT68_FN1), \
+       PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
+       PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A23_MARK, PORT69_FN1), \
+       PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
+       PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A24_MARK, PORT70_FN1), \
+       PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
+       PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A25_MARK, PORT71_FN1), \
+       PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
+       PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
+       PINMUX_DATA(A26_MARK, PORT72_FN1), \
+       PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
+       PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
+       PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
+       PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
+       PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
+       PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
+       PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
+       PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
+       PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
+       PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
+       PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
+       PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
+       PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
+       PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
+       PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
+       PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
+       PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
+       PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
+       PINMUX_DATA(CS4__MARK, PORT90_FN1),
+       PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
+       PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
+       PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
+       PINMUX_DATA(FCE1__MARK, PORT92_FN2),
+       PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
+       PINMUX_DATA(DACK0_MARK, PORT93_FN4),
+       PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
+       PINMUX_DATA(CS6A__MARK, PORT94_FN2),
+       PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
+       PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
+       PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
+       PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
+       PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
+       PINMUX_DATA(WE1__MARK, PORT98_FN1),
+       PINMUX_DATA(FRB_MARK, PORT99_FN1),
+       PINMUX_DATA(CKO_MARK, PORT100_FN1),
+       PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
+       PINMUX_DATA(NBRST__MARK, PORT102_FN1),
+       PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
+       PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
+       PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
+       PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
+       PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
+       PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
+       PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
+       PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
+       PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
+       PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
+       PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
+       PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
+       PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
+       PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
+       PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
+       PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
+       PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
+       PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
+       PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
+       PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
+       PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
+       PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
+       PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
+       PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
+       PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
+       PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
+       PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
+       PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
+       PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
+       PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
+       PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
+       PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
+       PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
+       PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
+       PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
+       PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
+
+       PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
+       PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
+       PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
+       PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
+       PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
+       PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
+       PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
+               MSEL4CR_MSEL10_1), \
+       PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
+       PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
+       PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
+       PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
+       PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
+       PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
+       PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
+       PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
+       PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
+       PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
+       PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
+       PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
+       PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
+       PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
+       PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
+       PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
+       PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
+       PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
+       PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
+       PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
+       PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
+       PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
+       PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
+       PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
+       PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
+       PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
+       PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
+       PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
+       PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
+       PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
+       PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
+       PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
+       PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
+       PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
+       PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
+       PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
+       PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
+       PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
+       PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
+       PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
+       PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
+       PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
+       PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
+       PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
+       PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
+       PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
+       PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
+       PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
+       PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
+       PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
+       PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
+       PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
+       PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
+       PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
+       PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
+       PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
+       PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
+       PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
+       PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
+       PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
+       PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
+       PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
+       PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
+       PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
+       PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
+       PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
+       PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
+       PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
+       PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
+       PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
+       PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
+       PINMUX_DATA(A27_MARK, PORT149_FN1), \
+       PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
+       PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
+       PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
+       PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
+       PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
+       PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
+       PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
+       PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
+       PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
+       PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
+       PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
+       PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
+       PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
+       PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
+       PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
+       PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
+       PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
+       PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
+       PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
+               MSEL4CR_MSEL10_0),
+       PINMUX_DATA(DINT__MARK, PORT158_FN1), \
+       PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
+       PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
+       PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
+       PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
+       PINMUX_DATA(NMI_MARK, PORT159_FN3),
+       PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
+       PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
+       PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
+       PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
+       PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
+       PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
+       PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
+       PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
+       PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
+       PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
+       PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
+       PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_1), \
+       PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
+       PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
+       PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_1), \
+       PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
+       PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
+       PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_1), \
+       PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
+       PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
+       PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_1),
+       PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
+       PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_1), \
+       PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
+       PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
+       PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
+       PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
+       PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
+       PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
+       PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
+       PINMUX_DATA(D16_MARK, PORT200_FN6),
+       PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
+       PINMUX_DATA(D17_MARK, PORT201_FN6),
+       PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
+       PINMUX_DATA(D18_MARK, PORT202_FN6),
+       PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
+       PINMUX_DATA(D19_MARK, PORT203_FN6),
+       PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
+       PINMUX_DATA(D20_MARK, PORT204_FN6),
+       PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
+       PINMUX_DATA(D21_MARK, PORT205_FN6),
+       PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
+       PINMUX_DATA(D22_MARK, PORT206_FN6),
+       PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
+       PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(D23_MARK, PORT207_FN6),
+       PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
+       PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(D24_MARK, PORT208_FN6),
+       PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
+       PINMUX_DATA(D25_MARK, PORT209_FN6),
+       PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
+       PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
+       PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(D26_MARK, PORT210_FN6),
+       PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
+       PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(D27_MARK, PORT211_FN6),
+       PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
+       PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
+       PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(D28_MARK, PORT212_FN6),
+       PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
+       PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
+       PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(D29_MARK, PORT213_FN6),
+       PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
+       PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
+       PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(D30_MARK, PORT214_FN6),
+       PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
+       PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
+       PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(D31_MARK, PORT215_FN6),
+       PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
+       PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
+       PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
+       PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
+       PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
+       PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
+               MSEL4CR_MSEL26_1), \
+       PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
+       PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
+       PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
+       PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
+       PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
+       PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
+       PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
+       PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
+       PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
+       PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
+       PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
+               MSEL4CR_MSEL26_1), \
+       PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
+       PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
+       PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
+       PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
+       PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
+       PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
+       PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
+       PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
+               MSEL4CR_MSEL26_1), \
+       PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
+       PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
+       PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
+       PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
+       PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
+       PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
+       PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
+               MSEL4CR_MSEL26_1), \
+       PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
+
+       PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
+       PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
+       PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
+       PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
+       PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
+       PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
+       PINMUX_DATA(IDIN_MARK, PORT227_FN4),
+       PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
+       PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
+       PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
+       PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
+       PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
+       PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
+       PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
+       PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
+       PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
+       PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
+       PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
+       PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
+       PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
+       PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
+               MSEL4CR_MSEL26_0), \
+       PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
+       PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
+       PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
+       PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
+               MSEL4CR_MSEL26_0), \
+       PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
+       PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
+       PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
+               MSEL2CR_MSEL16_0),
+       PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
+       PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
+               MSEL2CR_MSEL16_0),
+       PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
+       PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
+               MSEL4CR_MSEL26_0), \
+       PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
+       PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
+       PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
+               MSEL4CR_MSEL26_0), \
+       PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
+       PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
+       PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
+       PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
+       PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
+       PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
+       PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
+       PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
+       PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
+       PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
+       PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_0), \
+       PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
+       PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
+       PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
+       PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_0), \
+       PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
+       PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
+       PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
+       PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_0), \
+       PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
+       PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
+       PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
+       PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_0), \
+       PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
+       PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
+       PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
+       PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
+               MSEL4CR_MSEL20_0), \
+       PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
+       PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
+       PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
+       PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
+               MSEL2CR_MSEL18_0), \
+       PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
+       PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
+       PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
+       PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
+               MSEL2CR_MSEL18_0), \
+       PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
+       PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
+       PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
+       PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
+       PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
+       PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
+       PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
+       PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
+       PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
+       PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
+       PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
+       PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
+       PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
+       PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
+       PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
+       PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
+       PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
+       PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
+       PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
+       PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
+       PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
+       PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
+       PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
+       PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
+       PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
+       PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
+       PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
+       PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
+       PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
+       PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
+       PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
+       PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
+       PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
+       PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
+       PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \
+       PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
+       PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \
+       PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
+       PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \
+       PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
+       PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \
+       PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
+       PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
+       PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
+       PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
+       PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
+       PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
+       PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
+       PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
+       PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
+       PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
+       PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
+       PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
+       PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
+       PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
+       PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
+       PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
+
+       PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
+       PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
+       PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
+       PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
+       PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
+       PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
+       PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
+       PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
+       PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
+       PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
+       PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
+
+       /* MSEL2 special cases */
+       PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+               MSEL2CR_MSEL12_0),
+       PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+               MSEL2CR_MSEL12_1),
+       PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+               MSEL2CR_MSEL12_0),
+       PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+               MSEL2CR_MSEL12_1),
+       PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
+               MSEL2CR_MSEL12_0),
+       PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+               MSEL2CR_MSEL9_0),
+       PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+               MSEL2CR_MSEL9_1),
+       PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+               MSEL2CR_MSEL9_0),
+       PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+               MSEL2CR_MSEL9_1),
+       PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
+               MSEL2CR_MSEL9_0),
+       PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+               MSEL2CR_MSEL6_0),
+       PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+               MSEL2CR_MSEL6_1),
+       PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+               MSEL2CR_MSEL6_0),
+       PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+               MSEL2CR_MSEL6_1),
+       PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
+               MSEL2CR_MSEL6_0),
+       PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+               MSEL2CR_MSEL3_0),
+       PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+               MSEL2CR_MSEL3_1),
+       PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+               MSEL2CR_MSEL3_0),
+       PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+               MSEL2CR_MSEL3_1),
+       PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
+               MSEL2CR_MSEL3_0),
+       PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+               MSEL2CR_MSEL0_0),
+       PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+               MSEL2CR_MSEL0_1),
+       PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+               MSEL2CR_MSEL0_0),
+       PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+               MSEL2CR_MSEL0_1),
+       PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
+               MSEL2CR_MSEL0_0),
+
+       /* MSEL3 special cases */
+       PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
+       PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
+       PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
+       PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
+       PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
+       PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
+
+       /* MSEL4 special cases */
+       PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
+       PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
+       PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
+       PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
+       PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
+       PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
+       PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
+       PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
+       PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
+
+       /* Functions with pull-ups */
+       PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
+       PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
+       PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
+       PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
+       PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
+       PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
+       PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
+       PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
+
+       PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1),
+       PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1),
+       PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1),
+       PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1),
+       PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1),
+
+       PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
+               MSEL4CR_MSEL15_0),
+       PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU,
+               MSEL4CR_MSEL15_1),
+       PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
+       PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
+       PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
+       PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
+};
+
+#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
+#define GPIO_PORT_310() _310(_GPIO_PORT, , unused)
+#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+
+static struct pinmux_gpio pinmux_gpios[] = {
+       GPIO_PORT_310(),
+
+       /* Table 25-1 (Functions 0-7) */
+       GPIO_FN(VBUS_0),
+       GPIO_FN(GPI0),
+       GPIO_FN(GPI1),
+       GPIO_FN(GPI2),
+       GPIO_FN(GPI3),
+       GPIO_FN(GPI4),
+       GPIO_FN(GPI5),
+       GPIO_FN(GPI6),
+       GPIO_FN(GPI7),
+       GPIO_FN(SCIFA7_RXD),
+       GPIO_FN(SCIFA7_CTS_),
+       GPIO_FN(GPO7), \
+       GPIO_FN(MFG0_OUT2),
+       GPIO_FN(GPO6), \
+       GPIO_FN(MFG1_OUT2),
+       GPIO_FN(GPO5), \
+       GPIO_FN(SCIFA0_SCK), \
+       GPIO_FN(FSICOSLDT3), \
+       GPIO_FN(PORT16_VIO_CKOR),
+       GPIO_FN(SCIFA0_TXD),
+       GPIO_FN(SCIFA7_TXD),
+       GPIO_FN(SCIFA7_RTS_), \
+       GPIO_FN(PORT19_VIO_CKO2),
+       GPIO_FN(GPO0),
+       GPIO_FN(GPO1),
+       GPIO_FN(GPO2), \
+       GPIO_FN(STATUS0),
+       GPIO_FN(GPO3), \
+       GPIO_FN(STATUS1),
+       GPIO_FN(GPO4), \
+       GPIO_FN(STATUS2),
+       GPIO_FN(VINT),
+       GPIO_FN(TCKON),
+       GPIO_FN(XDVFS1), \
+       GPIO_FN(PORT27_I2C_SCL2), \
+       GPIO_FN(PORT27_I2C_SCL3), \
+       GPIO_FN(MFG0_OUT1), \
+       GPIO_FN(PORT27_IROUT),
+       GPIO_FN(XDVFS2), \
+       GPIO_FN(PORT28_I2C_SDA2), \
+       GPIO_FN(PORT28_I2C_SDA3), \
+       GPIO_FN(PORT28_TPU1TO1),
+       GPIO_FN(SIM_RST), \
+       GPIO_FN(PORT29_TPU1TO1),
+       GPIO_FN(SIM_CLK), \
+       GPIO_FN(PORT30_VIO_CKOR),
+       GPIO_FN(SIM_D), \
+       GPIO_FN(PORT31_IROUT),
+       GPIO_FN(SCIFA4_TXD),
+       GPIO_FN(SCIFA4_RXD), \
+       GPIO_FN(XWUP),
+       GPIO_FN(SCIFA4_RTS_),
+       GPIO_FN(SCIFA4_CTS_),
+       GPIO_FN(FSIBOBT), \
+       GPIO_FN(FSIBIBT),
+       GPIO_FN(FSIBOLR), \
+       GPIO_FN(FSIBILR),
+       GPIO_FN(FSIBOSLD),
+       GPIO_FN(FSIBISLD),
+       GPIO_FN(VACK),
+       GPIO_FN(XTAL1L),
+       GPIO_FN(SCIFA0_RTS_), \
+       GPIO_FN(FSICOSLDT2),
+       GPIO_FN(SCIFA0_RXD),
+       GPIO_FN(SCIFA0_CTS_), \
+       GPIO_FN(FSICOSLDT1),
+       GPIO_FN(FSICOBT), \
+       GPIO_FN(FSICIBT), \
+       GPIO_FN(FSIDOBT), \
+       GPIO_FN(FSIDIBT),
+       GPIO_FN(FSICOLR), \
+       GPIO_FN(FSICILR), \
+       GPIO_FN(FSIDOLR), \
+       GPIO_FN(FSIDILR),
+       GPIO_FN(FSICOSLD), \
+       GPIO_FN(PORT47_FSICSPDIF),
+       GPIO_FN(FSICISLD), \
+       GPIO_FN(FSIDISLD),
+       GPIO_FN(FSIACK), \
+       GPIO_FN(PORT49_IRDA_OUT), \
+       GPIO_FN(PORT49_IROUT), \
+       GPIO_FN(FSIAOMC),
+       GPIO_FN(FSIAOLR), \
+       GPIO_FN(BBIF2_TSYNC2), \
+       GPIO_FN(TPU2TO2), \
+       GPIO_FN(FSIAILR),
+
+       GPIO_FN(FSIAOBT), \
+       GPIO_FN(BBIF2_TSCK2), \
+       GPIO_FN(TPU2TO3), \
+       GPIO_FN(FSIAIBT),
+       GPIO_FN(FSIAOSLD), \
+       GPIO_FN(BBIF2_TXD2),
+       GPIO_FN(FSIASPDIF), \
+       GPIO_FN(PORT53_IRDA_IN), \
+       GPIO_FN(TPU3TO3), \
+       GPIO_FN(FSIBSPDIF), \
+       GPIO_FN(PORT53_FSICSPDIF),
+       GPIO_FN(FSIBCK), \
+       GPIO_FN(PORT54_IRDA_FIRSEL), \
+       GPIO_FN(TPU3TO2), \
+       GPIO_FN(FSIBOMC), \
+       GPIO_FN(FSICCK), \
+       GPIO_FN(FSICOMC),
+       GPIO_FN(FSIAISLD), \
+       GPIO_FN(TPU0TO0),
+       GPIO_FN(A0), \
+       GPIO_FN(BS_),
+       GPIO_FN(A12), \
+       GPIO_FN(PORT58_KEYOUT7), \
+       GPIO_FN(TPU4TO2),
+       GPIO_FN(A13), \
+       GPIO_FN(PORT59_KEYOUT6), \
+       GPIO_FN(TPU0TO1),
+       GPIO_FN(A14), \
+       GPIO_FN(KEYOUT5),
+       GPIO_FN(A15), \
+       GPIO_FN(KEYOUT4),
+       GPIO_FN(A16), \
+       GPIO_FN(KEYOUT3), \
+       GPIO_FN(MSIOF0_SS1),
+       GPIO_FN(A17), \
+       GPIO_FN(KEYOUT2), \
+       GPIO_FN(MSIOF0_TSYNC),
+       GPIO_FN(A18), \
+       GPIO_FN(KEYOUT1), \
+       GPIO_FN(MSIOF0_TSCK),
+       GPIO_FN(A19), \
+       GPIO_FN(KEYOUT0), \
+       GPIO_FN(MSIOF0_TXD),
+       GPIO_FN(A20), \
+       GPIO_FN(KEYIN0), \
+       GPIO_FN(MSIOF0_RSCK),
+       GPIO_FN(A21), \
+       GPIO_FN(KEYIN1), \
+       GPIO_FN(MSIOF0_RSYNC),
+       GPIO_FN(A22), \
+       GPIO_FN(KEYIN2), \
+       GPIO_FN(MSIOF0_MCK0),
+       GPIO_FN(A23), \
+       GPIO_FN(KEYIN3), \
+       GPIO_FN(MSIOF0_MCK1),
+       GPIO_FN(A24), \
+       GPIO_FN(KEYIN4), \
+       GPIO_FN(MSIOF0_RXD),
+       GPIO_FN(A25), \
+       GPIO_FN(KEYIN5), \
+       GPIO_FN(MSIOF0_SS2),
+       GPIO_FN(A26), \
+       GPIO_FN(KEYIN6),
+       GPIO_FN(KEYIN7),
+       GPIO_FN(D0_NAF0),
+       GPIO_FN(D1_NAF1),
+       GPIO_FN(D2_NAF2),
+       GPIO_FN(D3_NAF3),
+       GPIO_FN(D4_NAF4),
+       GPIO_FN(D5_NAF5),
+       GPIO_FN(D6_NAF6),
+       GPIO_FN(D7_NAF7),
+       GPIO_FN(D8_NAF8),
+       GPIO_FN(D9_NAF9),
+       GPIO_FN(D10_NAF10),
+       GPIO_FN(D11_NAF11),
+       GPIO_FN(D12_NAF12),
+       GPIO_FN(D13_NAF13),
+       GPIO_FN(D14_NAF14),
+       GPIO_FN(D15_NAF15),
+       GPIO_FN(CS4_),
+       GPIO_FN(CS5A_), \
+       GPIO_FN(PORT91_RDWR),
+       GPIO_FN(CS5B_), \
+       GPIO_FN(FCE1_),
+       GPIO_FN(CS6B_), \
+       GPIO_FN(DACK0),
+       GPIO_FN(FCE0_), \
+       GPIO_FN(CS6A_),
+       GPIO_FN(WAIT_), \
+       GPIO_FN(DREQ0),
+       GPIO_FN(RD__FSC),
+       GPIO_FN(WE0__FWE), \
+       GPIO_FN(RDWR_FWE),
+       GPIO_FN(WE1_),
+       GPIO_FN(FRB),
+       GPIO_FN(CKO),
+       GPIO_FN(NBRSTOUT_),
+       GPIO_FN(NBRST_),
+       GPIO_FN(BBIF2_TXD),
+       GPIO_FN(BBIF2_RXD),
+       GPIO_FN(BBIF2_SYNC),
+       GPIO_FN(BBIF2_SCK),
+       GPIO_FN(SCIFA3_CTS_), \
+       GPIO_FN(MFG3_IN2),
+       GPIO_FN(SCIFA3_RXD), \
+       GPIO_FN(MFG3_IN1),
+       GPIO_FN(BBIF1_SS2), \
+       GPIO_FN(SCIFA3_RTS_), \
+       GPIO_FN(MFG3_OUT1),
+       GPIO_FN(SCIFA3_TXD),
+       GPIO_FN(HSI_RX_DATA), \
+       GPIO_FN(BBIF1_RXD),
+       GPIO_FN(HSI_TX_WAKE), \
+       GPIO_FN(BBIF1_TSCK),
+       GPIO_FN(HSI_TX_DATA), \
+       GPIO_FN(BBIF1_TSYNC),
+       GPIO_FN(HSI_TX_READY), \
+       GPIO_FN(BBIF1_TXD),
+       GPIO_FN(HSI_RX_READY), \
+       GPIO_FN(BBIF1_RSCK), \
+       GPIO_FN(PORT115_I2C_SCL2), \
+       GPIO_FN(PORT115_I2C_SCL3),
+       GPIO_FN(HSI_RX_WAKE), \
+       GPIO_FN(BBIF1_RSYNC), \
+       GPIO_FN(PORT116_I2C_SDA2), \
+       GPIO_FN(PORT116_I2C_SDA3),
+       GPIO_FN(HSI_RX_FLAG), \
+       GPIO_FN(BBIF1_SS1), \
+       GPIO_FN(BBIF1_FLOW),
+       GPIO_FN(HSI_TX_FLAG),
+       GPIO_FN(VIO_VD), \
+       GPIO_FN(PORT128_LCD2VSYN), \
+       GPIO_FN(VIO2_VD), \
+       GPIO_FN(LCD2D0),
+
+       GPIO_FN(VIO_HD), \
+       GPIO_FN(PORT129_LCD2HSYN), \
+       GPIO_FN(PORT129_LCD2CS_), \
+       GPIO_FN(VIO2_HD), \
+       GPIO_FN(LCD2D1),
+       GPIO_FN(VIO_D0), \
+       GPIO_FN(PORT130_MSIOF2_RXD), \
+       GPIO_FN(LCD2D10),
+       GPIO_FN(VIO_D1), \
+       GPIO_FN(PORT131_KEYOUT6), \
+       GPIO_FN(PORT131_MSIOF2_SS1), \
+       GPIO_FN(PORT131_KEYOUT11), \
+       GPIO_FN(LCD2D11),
+       GPIO_FN(VIO_D2), \
+       GPIO_FN(PORT132_KEYOUT7), \
+       GPIO_FN(PORT132_MSIOF2_SS2), \
+       GPIO_FN(PORT132_KEYOUT10), \
+       GPIO_FN(LCD2D12),
+       GPIO_FN(VIO_D3), \
+       GPIO_FN(MSIOF2_TSYNC), \
+       GPIO_FN(LCD2D13),
+       GPIO_FN(VIO_D4), \
+       GPIO_FN(MSIOF2_TXD), \
+       GPIO_FN(LCD2D14),
+       GPIO_FN(VIO_D5), \
+       GPIO_FN(MSIOF2_TSCK), \
+       GPIO_FN(LCD2D15),
+       GPIO_FN(VIO_D6), \
+       GPIO_FN(PORT136_KEYOUT8), \
+       GPIO_FN(LCD2D16),
+       GPIO_FN(VIO_D7), \
+       GPIO_FN(PORT137_KEYOUT9), \
+       GPIO_FN(LCD2D17),
+       GPIO_FN(VIO_D8), \
+       GPIO_FN(PORT138_KEYOUT8), \
+       GPIO_FN(VIO2_D0), \
+       GPIO_FN(LCD2D6),
+       GPIO_FN(VIO_D9), \
+       GPIO_FN(PORT139_KEYOUT9), \
+       GPIO_FN(VIO2_D1), \
+       GPIO_FN(LCD2D7),
+       GPIO_FN(VIO_D10), \
+       GPIO_FN(TPU0TO2), \
+       GPIO_FN(VIO2_D2), \
+       GPIO_FN(LCD2D8),
+       GPIO_FN(VIO_D11), \
+       GPIO_FN(TPU0TO3), \
+       GPIO_FN(VIO2_D3), \
+       GPIO_FN(LCD2D9),
+       GPIO_FN(VIO_D12), \
+       GPIO_FN(PORT142_KEYOUT10), \
+       GPIO_FN(VIO2_D4), \
+       GPIO_FN(LCD2D2),
+       GPIO_FN(VIO_D13), \
+       GPIO_FN(PORT143_KEYOUT11), \
+       GPIO_FN(PORT143_KEYOUT6), \
+       GPIO_FN(VIO2_D5), \
+       GPIO_FN(LCD2D3),
+       GPIO_FN(VIO_D14), \
+       GPIO_FN(PORT144_KEYOUT7), \
+       GPIO_FN(VIO2_D6), \
+       GPIO_FN(LCD2D4),
+       GPIO_FN(VIO_D15), \
+       GPIO_FN(TPU1TO3), \
+       GPIO_FN(PORT145_LCD2DISP), \
+       GPIO_FN(PORT145_LCD2RS), \
+       GPIO_FN(VIO2_D7), \
+       GPIO_FN(LCD2D5),
+       GPIO_FN(VIO_CLK), \
+       GPIO_FN(LCD2DCK), \
+       GPIO_FN(PORT146_LCD2WR_), \
+       GPIO_FN(VIO2_CLK), \
+       GPIO_FN(LCD2D18),
+       GPIO_FN(VIO_FIELD), \
+       GPIO_FN(LCD2RD_), \
+       GPIO_FN(VIO2_FIELD), \
+       GPIO_FN(LCD2D19),
+       GPIO_FN(VIO_CKO),
+       GPIO_FN(A27), \
+       GPIO_FN(PORT149_RDWR), \
+       GPIO_FN(MFG0_IN1), \
+       GPIO_FN(PORT149_KEYOUT9),
+       GPIO_FN(MFG0_IN2),
+       GPIO_FN(TS_SPSYNC3), \
+       GPIO_FN(MSIOF2_RSCK),
+       GPIO_FN(TS_SDAT3), \
+       GPIO_FN(MSIOF2_RSYNC),
+       GPIO_FN(TPU1TO2), \
+       GPIO_FN(TS_SDEN3), \
+       GPIO_FN(PORT153_MSIOF2_SS1),
+       GPIO_FN(SCIFA2_TXD1), \
+       GPIO_FN(MSIOF2_MCK0),
+       GPIO_FN(SCIFA2_RXD1), \
+       GPIO_FN(MSIOF2_MCK1),
+       GPIO_FN(SCIFA2_RTS1_), \
+       GPIO_FN(PORT156_MSIOF2_SS2),
+       GPIO_FN(SCIFA2_CTS1_), \
+       GPIO_FN(PORT157_MSIOF2_RXD),
+       GPIO_FN(DINT_), \
+       GPIO_FN(SCIFA2_SCK1), \
+       GPIO_FN(TS_SCK3),
+       GPIO_FN(PORT159_SCIFB_SCK), \
+       GPIO_FN(PORT159_SCIFA5_SCK), \
+       GPIO_FN(NMI),
+       GPIO_FN(PORT160_SCIFB_TXD), \
+       GPIO_FN(PORT160_SCIFA5_TXD),
+       GPIO_FN(PORT161_SCIFB_CTS_), \
+       GPIO_FN(PORT161_SCIFA5_CTS_),
+       GPIO_FN(PORT162_SCIFB_RXD), \
+       GPIO_FN(PORT162_SCIFA5_RXD),
+       GPIO_FN(PORT163_SCIFB_RTS_), \
+       GPIO_FN(PORT163_SCIFA5_RTS_), \
+       GPIO_FN(TPU3TO0),
+       GPIO_FN(LCDD0),
+       GPIO_FN(LCDD1), \
+       GPIO_FN(PORT193_SCIFA5_CTS_), \
+       GPIO_FN(BBIF2_TSYNC1),
+       GPIO_FN(LCDD2), \
+       GPIO_FN(PORT194_SCIFA5_RTS_), \
+       GPIO_FN(BBIF2_TSCK1),
+       GPIO_FN(LCDD3), \
+       GPIO_FN(PORT195_SCIFA5_RXD), \
+       GPIO_FN(BBIF2_TXD1),
+       GPIO_FN(LCDD4), \
+       GPIO_FN(PORT196_SCIFA5_TXD),
+       GPIO_FN(LCDD5), \
+       GPIO_FN(PORT197_SCIFA5_SCK), \
+       GPIO_FN(MFG2_OUT2), \
+       GPIO_FN(TPU2TO1),
+       GPIO_FN(LCDD6),
+       GPIO_FN(LCDD7), \
+       GPIO_FN(TPU4TO1), \
+       GPIO_FN(MFG4_OUT2),
+       GPIO_FN(LCDD8), \
+       GPIO_FN(D16),
+       GPIO_FN(LCDD9), \
+       GPIO_FN(D17),
+       GPIO_FN(LCDD10), \
+       GPIO_FN(D18),
+       GPIO_FN(LCDD11), \
+       GPIO_FN(D19),
+       GPIO_FN(LCDD12), \
+       GPIO_FN(D20),
+       GPIO_FN(LCDD13), \
+       GPIO_FN(D21),
+       GPIO_FN(LCDD14), \
+       GPIO_FN(D22),
+       GPIO_FN(LCDD15), \
+       GPIO_FN(PORT207_MSIOF0L_SS1), \
+       GPIO_FN(D23),
+       GPIO_FN(LCDD16), \
+       GPIO_FN(PORT208_MSIOF0L_SS2), \
+       GPIO_FN(D24),
+       GPIO_FN(LCDD17), \
+       GPIO_FN(D25),
+       GPIO_FN(LCDD18), \
+       GPIO_FN(DREQ2), \
+       GPIO_FN(PORT210_MSIOF0L_SS1), \
+       GPIO_FN(D26),
+       GPIO_FN(LCDD19), \
+       GPIO_FN(PORT211_MSIOF0L_SS2), \
+       GPIO_FN(D27),
+       GPIO_FN(LCDD20), \
+       GPIO_FN(TS_SPSYNC1), \
+       GPIO_FN(MSIOF0L_MCK0), \
+       GPIO_FN(D28),
+       GPIO_FN(LCDD21), \
+       GPIO_FN(TS_SDAT1), \
+       GPIO_FN(MSIOF0L_MCK1), \
+       GPIO_FN(D29),
+       GPIO_FN(LCDD22), \
+       GPIO_FN(TS_SDEN1), \
+       GPIO_FN(MSIOF0L_RSCK), \
+       GPIO_FN(D30),
+       GPIO_FN(LCDD23), \
+       GPIO_FN(TS_SCK1), \
+       GPIO_FN(MSIOF0L_RSYNC), \
+       GPIO_FN(D31),
+       GPIO_FN(LCDDCK), \
+       GPIO_FN(LCDWR_),
+       GPIO_FN(LCDRD_), \
+       GPIO_FN(DACK2), \
+       GPIO_FN(PORT217_LCD2RS), \
+       GPIO_FN(MSIOF0L_TSYNC), \
+       GPIO_FN(VIO2_FIELD3), \
+       GPIO_FN(PORT217_LCD2DISP),
+       GPIO_FN(LCDHSYN), \
+       GPIO_FN(LCDCS_), \
+       GPIO_FN(LCDCS2_), \
+       GPIO_FN(DACK3), \
+       GPIO_FN(PORT218_VIO_CKOR),
+       GPIO_FN(LCDDISP), \
+       GPIO_FN(LCDRS), \
+       GPIO_FN(PORT219_LCD2WR_), \
+       GPIO_FN(DREQ3), \
+       GPIO_FN(MSIOF0L_TSCK), \
+       GPIO_FN(VIO2_CLK3), \
+       GPIO_FN(LCD2DCK_2),
+       GPIO_FN(LCDVSYN), \
+       GPIO_FN(LCDVSYN2),
+       GPIO_FN(LCDLCLK), \
+       GPIO_FN(DREQ1), \
+       GPIO_FN(PORT221_LCD2CS_), \
+       GPIO_FN(PWEN), \
+       GPIO_FN(MSIOF0L_RXD), \
+       GPIO_FN(VIO2_HD3), \
+       GPIO_FN(PORT221_LCD2HSYN),
+       GPIO_FN(LCDDON), \
+       GPIO_FN(LCDDON2), \
+       GPIO_FN(DACK1), \
+       GPIO_FN(OVCN), \
+       GPIO_FN(MSIOF0L_TXD), \
+       GPIO_FN(VIO2_VD3), \
+       GPIO_FN(PORT222_LCD2VSYN),
+
+       GPIO_FN(SCIFA1_TXD), \
+       GPIO_FN(OVCN2),
+       GPIO_FN(EXTLP), \
+       GPIO_FN(SCIFA1_SCK), \
+       GPIO_FN(PORT226_VIO_CKO2),
+       GPIO_FN(SCIFA1_RTS_), \
+       GPIO_FN(IDIN),
+       GPIO_FN(SCIFA1_RXD),
+       GPIO_FN(SCIFA1_CTS_), \
+       GPIO_FN(MFG1_IN1),
+       GPIO_FN(MSIOF1_TXD), \
+       GPIO_FN(SCIFA2_TXD2),
+       GPIO_FN(MSIOF1_TSYNC), \
+       GPIO_FN(SCIFA2_CTS2_),
+       GPIO_FN(MSIOF1_TSCK), \
+       GPIO_FN(SCIFA2_SCK2),
+       GPIO_FN(MSIOF1_RXD), \
+       GPIO_FN(SCIFA2_RXD2),
+       GPIO_FN(MSIOF1_RSCK), \
+       GPIO_FN(SCIFA2_RTS2_), \
+       GPIO_FN(VIO2_CLK2), \
+       GPIO_FN(LCD2D20),
+       GPIO_FN(MSIOF1_RSYNC), \
+       GPIO_FN(MFG1_IN2), \
+       GPIO_FN(VIO2_VD2), \
+       GPIO_FN(LCD2D21),
+       GPIO_FN(MSIOF1_MCK0), \
+       GPIO_FN(PORT236_I2C_SDA2),
+       GPIO_FN(MSIOF1_MCK1), \
+       GPIO_FN(PORT237_I2C_SCL2),
+       GPIO_FN(MSIOF1_SS1), \
+       GPIO_FN(VIO2_FIELD2), \
+       GPIO_FN(LCD2D22),
+       GPIO_FN(MSIOF1_SS2), \
+       GPIO_FN(VIO2_HD2), \
+       GPIO_FN(LCD2D23),
+       GPIO_FN(SCIFA6_TXD),
+       GPIO_FN(PORT241_IRDA_OUT), \
+       GPIO_FN(PORT241_IROUT), \
+       GPIO_FN(MFG4_OUT1), \
+       GPIO_FN(TPU4TO0),
+       GPIO_FN(PORT242_IRDA_IN), \
+       GPIO_FN(MFG4_IN2),
+       GPIO_FN(PORT243_IRDA_FIRSEL), \
+       GPIO_FN(PORT243_VIO_CKO2),
+       GPIO_FN(PORT244_SCIFA5_CTS_), \
+       GPIO_FN(MFG2_IN1), \
+       GPIO_FN(PORT244_SCIFB_CTS_), \
+       GPIO_FN(MSIOF2R_RXD),
+       GPIO_FN(PORT245_SCIFA5_RTS_), \
+       GPIO_FN(MFG2_IN2), \
+       GPIO_FN(PORT245_SCIFB_RTS_), \
+       GPIO_FN(MSIOF2R_TXD),
+       GPIO_FN(PORT246_SCIFA5_RXD), \
+       GPIO_FN(MFG1_OUT1), \
+       GPIO_FN(PORT246_SCIFB_RXD), \
+       GPIO_FN(TPU1TO0),
+       GPIO_FN(PORT247_SCIFA5_TXD), \
+       GPIO_FN(MFG3_OUT2), \
+       GPIO_FN(PORT247_SCIFB_TXD), \
+       GPIO_FN(TPU3TO1),
+       GPIO_FN(PORT248_SCIFA5_SCK), \
+       GPIO_FN(MFG2_OUT1), \
+       GPIO_FN(PORT248_SCIFB_SCK), \
+       GPIO_FN(TPU2TO0), \
+       GPIO_FN(PORT248_I2C_SCL3), \
+       GPIO_FN(MSIOF2R_TSCK),
+       GPIO_FN(PORT249_IROUT), \
+       GPIO_FN(MFG4_IN1), \
+       GPIO_FN(PORT249_I2C_SDA3), \
+       GPIO_FN(MSIOF2R_TSYNC),
+       GPIO_FN(SDHICLK0),
+       GPIO_FN(SDHICD0),
+       GPIO_FN(SDHID0_0),
+       GPIO_FN(SDHID0_1),
+       GPIO_FN(SDHID0_2),
+       GPIO_FN(SDHID0_3),
+       GPIO_FN(SDHICMD0),
+       GPIO_FN(SDHIWP0),
+       GPIO_FN(SDHICLK1),
+       GPIO_FN(SDHID1_0), \
+       GPIO_FN(TS_SPSYNC2),
+       GPIO_FN(SDHID1_1), \
+       GPIO_FN(TS_SDAT2),
+       GPIO_FN(SDHID1_2), \
+       GPIO_FN(TS_SDEN2),
+       GPIO_FN(SDHID1_3), \
+       GPIO_FN(TS_SCK2),
+       GPIO_FN(SDHICMD1),
+       GPIO_FN(SDHICLK2),
+       GPIO_FN(SDHID2_0), \
+       GPIO_FN(TS_SPSYNC4),
+       GPIO_FN(SDHID2_1), \
+       GPIO_FN(TS_SDAT4),
+       GPIO_FN(SDHID2_2), \
+       GPIO_FN(TS_SDEN4),
+       GPIO_FN(SDHID2_3), \
+       GPIO_FN(TS_SCK4),
+       GPIO_FN(SDHICMD2),
+       GPIO_FN(MMCCLK0),
+       GPIO_FN(MMCD0_0),
+       GPIO_FN(MMCD0_1),
+       GPIO_FN(MMCD0_2),
+       GPIO_FN(MMCD0_3),
+       GPIO_FN(MMCD0_4), \
+       GPIO_FN(TS_SPSYNC5),
+       GPIO_FN(MMCD0_5), \
+       GPIO_FN(TS_SDAT5),
+       GPIO_FN(MMCD0_6), \
+       GPIO_FN(TS_SDEN5),
+       GPIO_FN(MMCD0_7), \
+       GPIO_FN(TS_SCK5),
+       GPIO_FN(MMCCMD0),
+       GPIO_FN(RESETOUTS_), \
+       GPIO_FN(EXTAL2OUT),
+       GPIO_FN(MCP_WAIT__MCP_FRB),
+       GPIO_FN(MCP_CKO), \
+       GPIO_FN(MMCCLK1),
+       GPIO_FN(MCP_D15_MCP_NAF15),
+       GPIO_FN(MCP_D14_MCP_NAF14),
+       GPIO_FN(MCP_D13_MCP_NAF13),
+       GPIO_FN(MCP_D12_MCP_NAF12),
+       GPIO_FN(MCP_D11_MCP_NAF11),
+       GPIO_FN(MCP_D10_MCP_NAF10),
+       GPIO_FN(MCP_D9_MCP_NAF9),
+       GPIO_FN(MCP_D8_MCP_NAF8), \
+       GPIO_FN(MMCCMD1),
+       GPIO_FN(MCP_D7_MCP_NAF7), \
+       GPIO_FN(MMCD1_7),
+
+       GPIO_FN(MCP_D6_MCP_NAF6), \
+       GPIO_FN(MMCD1_6),
+       GPIO_FN(MCP_D5_MCP_NAF5), \
+       GPIO_FN(MMCD1_5),
+       GPIO_FN(MCP_D4_MCP_NAF4), \
+       GPIO_FN(MMCD1_4),
+       GPIO_FN(MCP_D3_MCP_NAF3), \
+       GPIO_FN(MMCD1_3),
+       GPIO_FN(MCP_D2_MCP_NAF2), \
+       GPIO_FN(MMCD1_2),
+       GPIO_FN(MCP_D1_MCP_NAF1), \
+       GPIO_FN(MMCD1_1),
+       GPIO_FN(MCP_D0_MCP_NAF0), \
+       GPIO_FN(MMCD1_0),
+       GPIO_FN(MCP_NBRSTOUT_),
+       GPIO_FN(MCP_WE0__MCP_FWE), \
+       GPIO_FN(MCP_RDWR_MCP_FWE),
+
+       /* MSEL2 special cases */
+       GPIO_FN(TSIF2_TS_XX1),
+       GPIO_FN(TSIF2_TS_XX2),
+       GPIO_FN(TSIF2_TS_XX3),
+       GPIO_FN(TSIF2_TS_XX4),
+       GPIO_FN(TSIF2_TS_XX5),
+       GPIO_FN(TSIF1_TS_XX1),
+       GPIO_FN(TSIF1_TS_XX2),
+       GPIO_FN(TSIF1_TS_XX3),
+       GPIO_FN(TSIF1_TS_XX4),
+       GPIO_FN(TSIF1_TS_XX5),
+       GPIO_FN(TSIF0_TS_XX1),
+       GPIO_FN(TSIF0_TS_XX2),
+       GPIO_FN(TSIF0_TS_XX3),
+       GPIO_FN(TSIF0_TS_XX4),
+       GPIO_FN(TSIF0_TS_XX5),
+       GPIO_FN(MST1_TS_XX1),
+       GPIO_FN(MST1_TS_XX2),
+       GPIO_FN(MST1_TS_XX3),
+       GPIO_FN(MST1_TS_XX4),
+       GPIO_FN(MST1_TS_XX5),
+       GPIO_FN(MST0_TS_XX1),
+       GPIO_FN(MST0_TS_XX2),
+       GPIO_FN(MST0_TS_XX3),
+       GPIO_FN(MST0_TS_XX4),
+       GPIO_FN(MST0_TS_XX5),
+
+       /* MSEL3 special cases */
+       GPIO_FN(SDHI0_VCCQ_MC0_ON),
+       GPIO_FN(SDHI0_VCCQ_MC0_OFF),
+       GPIO_FN(DEBUG_MON_VIO),
+       GPIO_FN(DEBUG_MON_LCDD),
+       GPIO_FN(LCDC_LCDC0),
+       GPIO_FN(LCDC_LCDC1),
+
+       /* MSEL4 special cases */
+       GPIO_FN(IRQ9_MEM_INT),
+       GPIO_FN(IRQ9_MCP_INT),
+       GPIO_FN(A11),
+       GPIO_FN(KEYOUT8),
+       GPIO_FN(TPU4TO3),
+       GPIO_FN(RESETA_N_PU_ON),
+       GPIO_FN(RESETA_N_PU_OFF),
+       GPIO_FN(EDBGREQ_PD),
+       GPIO_FN(EDBGREQ_PU),
+
+       /* Functions with pull-ups */
+       GPIO_FN(KEYIN0_PU),
+       GPIO_FN(KEYIN1_PU),
+       GPIO_FN(KEYIN2_PU),
+       GPIO_FN(KEYIN3_PU),
+       GPIO_FN(KEYIN4_PU),
+       GPIO_FN(KEYIN5_PU),
+       GPIO_FN(KEYIN6_PU),
+       GPIO_FN(KEYIN7_PU),
+       GPIO_FN(SDHID1_0_PU),
+       GPIO_FN(SDHID1_1_PU),
+       GPIO_FN(SDHID1_2_PU),
+       GPIO_FN(SDHID1_3_PU),
+       GPIO_FN(SDHICMD1_PU),
+       GPIO_FN(MMCCMD0_PU),
+       GPIO_FN(MMCCMD1_PU),
+       GPIO_FN(FSIACK_PU),
+       GPIO_FN(FSIAILR_PU),
+       GPIO_FN(FSIAIBT_PU),
+       GPIO_FN(FSIAISLD_PU),
+};
+
+#define PORTCR(nr, reg)        \
+       { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
+               0, \
+               /*0001*/ PORT##nr##_OUT , \
+               /*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \
+               /*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \
+               /*1110*/ PORT##nr##_IN_PU, 0, \
+               PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
+               PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
+               PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \
+       }
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+       PORTCR(0, 0xe6050000), /* PORT0CR */
+       PORTCR(1, 0xe6050001), /* PORT1CR */
+       PORTCR(2, 0xe6050002), /* PORT2CR */
+       PORTCR(3, 0xe6050003), /* PORT3CR */
+       PORTCR(4, 0xe6050004), /* PORT4CR */
+       PORTCR(5, 0xe6050005), /* PORT5CR */
+       PORTCR(6, 0xe6050006), /* PORT6CR */
+       PORTCR(7, 0xe6050007), /* PORT7CR */
+       PORTCR(8, 0xe6050008), /* PORT8CR */
+       PORTCR(9, 0xe6050009), /* PORT9CR */
+
+       PORTCR(10, 0xe605000a), /* PORT10CR */
+       PORTCR(11, 0xe605000b), /* PORT11CR */
+       PORTCR(12, 0xe605000c), /* PORT12CR */
+       PORTCR(13, 0xe605000d), /* PORT13CR */
+       PORTCR(14, 0xe605000e), /* PORT14CR */
+       PORTCR(15, 0xe605000f), /* PORT15CR */
+       PORTCR(16, 0xe6050010), /* PORT16CR */
+       PORTCR(17, 0xe6050011), /* PORT17CR */
+       PORTCR(18, 0xe6050012), /* PORT18CR */
+       PORTCR(19, 0xe6050013), /* PORT19CR */
+
+       PORTCR(20, 0xe6050014), /* PORT20CR */
+       PORTCR(21, 0xe6050015), /* PORT21CR */
+       PORTCR(22, 0xe6050016), /* PORT22CR */
+       PORTCR(23, 0xe6050017), /* PORT23CR */
+       PORTCR(24, 0xe6050018), /* PORT24CR */
+       PORTCR(25, 0xe6050019), /* PORT25CR */
+       PORTCR(26, 0xe605001a), /* PORT26CR */
+       PORTCR(27, 0xe605001b), /* PORT27CR */
+       PORTCR(28, 0xe605001c), /* PORT28CR */
+       PORTCR(29, 0xe605001d), /* PORT29CR */
+
+       PORTCR(30, 0xe605001e), /* PORT30CR */
+       PORTCR(31, 0xe605001f), /* PORT31CR */
+       PORTCR(32, 0xe6051020), /* PORT32CR */
+       PORTCR(33, 0xe6051021), /* PORT33CR */
+       PORTCR(34, 0xe6051022), /* PORT34CR */
+       PORTCR(35, 0xe6051023), /* PORT35CR */
+       PORTCR(36, 0xe6051024), /* PORT36CR */
+       PORTCR(37, 0xe6051025), /* PORT37CR */
+       PORTCR(38, 0xe6051026), /* PORT38CR */
+       PORTCR(39, 0xe6051027), /* PORT39CR */
+
+       PORTCR(40, 0xe6051028), /* PORT40CR */
+       PORTCR(41, 0xe6051029), /* PORT41CR */
+       PORTCR(42, 0xe605102a), /* PORT42CR */
+       PORTCR(43, 0xe605102b), /* PORT43CR */
+       PORTCR(44, 0xe605102c), /* PORT44CR */
+       PORTCR(45, 0xe605102d), /* PORT45CR */
+       PORTCR(46, 0xe605102e), /* PORT46CR */
+       PORTCR(47, 0xe605102f), /* PORT47CR */
+       PORTCR(48, 0xe6051030), /* PORT48CR */
+       PORTCR(49, 0xe6051031), /* PORT49CR */
+
+       PORTCR(50, 0xe6051032), /* PORT50CR */
+       PORTCR(51, 0xe6051033), /* PORT51CR */
+       PORTCR(52, 0xe6051034), /* PORT52CR */
+       PORTCR(53, 0xe6051035), /* PORT53CR */
+       PORTCR(54, 0xe6051036), /* PORT54CR */
+       PORTCR(55, 0xe6051037), /* PORT55CR */
+       PORTCR(56, 0xe6051038), /* PORT56CR */
+       PORTCR(57, 0xe6051039), /* PORT57CR */
+       PORTCR(58, 0xe605103a), /* PORT58CR */
+       PORTCR(59, 0xe605103b), /* PORT59CR */
+
+       PORTCR(60, 0xe605103c), /* PORT60CR */
+       PORTCR(61, 0xe605103d), /* PORT61CR */
+       PORTCR(62, 0xe605103e), /* PORT62CR */
+       PORTCR(63, 0xe605103f), /* PORT63CR */
+       PORTCR(64, 0xe6051040), /* PORT64CR */
+       PORTCR(65, 0xe6051041), /* PORT65CR */
+       PORTCR(66, 0xe6051042), /* PORT66CR */
+       PORTCR(67, 0xe6051043), /* PORT67CR */
+       PORTCR(68, 0xe6051044), /* PORT68CR */
+       PORTCR(69, 0xe6051045), /* PORT69CR */
+
+       PORTCR(70, 0xe6051046), /* PORT70CR */
+       PORTCR(71, 0xe6051047), /* PORT71CR */
+       PORTCR(72, 0xe6051048), /* PORT72CR */
+       PORTCR(73, 0xe6051049), /* PORT73CR */
+       PORTCR(74, 0xe605104a), /* PORT74CR */
+       PORTCR(75, 0xe605104b), /* PORT75CR */
+       PORTCR(76, 0xe605104c), /* PORT76CR */
+       PORTCR(77, 0xe605104d), /* PORT77CR */
+       PORTCR(78, 0xe605104e), /* PORT78CR */
+       PORTCR(79, 0xe605104f), /* PORT79CR */
+
+       PORTCR(80, 0xe6051050), /* PORT80CR */
+       PORTCR(81, 0xe6051051), /* PORT81CR */
+       PORTCR(82, 0xe6051052), /* PORT82CR */
+       PORTCR(83, 0xe6051053), /* PORT83CR */
+       PORTCR(84, 0xe6051054), /* PORT84CR */
+       PORTCR(85, 0xe6051055), /* PORT85CR */
+       PORTCR(86, 0xe6051056), /* PORT86CR */
+       PORTCR(87, 0xe6051057), /* PORT87CR */
+       PORTCR(88, 0xe6051058), /* PORT88CR */
+       PORTCR(89, 0xe6051059), /* PORT89CR */
+
+       PORTCR(90, 0xe605105a), /* PORT90CR */
+       PORTCR(91, 0xe605105b), /* PORT91CR */
+       PORTCR(92, 0xe605105c), /* PORT92CR */
+       PORTCR(93, 0xe605105d), /* PORT93CR */
+       PORTCR(94, 0xe605105e), /* PORT94CR */
+       PORTCR(95, 0xe605105f), /* PORT95CR */
+       PORTCR(96, 0xe6052060), /* PORT96CR */
+       PORTCR(97, 0xe6052061), /* PORT97CR */
+       PORTCR(98, 0xe6052062), /* PORT98CR */
+       PORTCR(99, 0xe6052063), /* PORT99CR */
+
+       PORTCR(100, 0xe6052064), /* PORT100CR */
+       PORTCR(101, 0xe6052065), /* PORT101CR */
+       PORTCR(102, 0xe6052066), /* PORT102CR */
+       PORTCR(103, 0xe6052067), /* PORT103CR */
+       PORTCR(104, 0xe6052068), /* PORT104CR */
+       PORTCR(105, 0xe6052069), /* PORT105CR */
+       PORTCR(106, 0xe605206a), /* PORT106CR */
+       PORTCR(107, 0xe605206b), /* PORT107CR */
+       PORTCR(108, 0xe605206c), /* PORT108CR */
+       PORTCR(109, 0xe605206d), /* PORT109CR */
+
+       PORTCR(110, 0xe605206e), /* PORT110CR */
+       PORTCR(111, 0xe605206f), /* PORT111CR */
+       PORTCR(112, 0xe6052070), /* PORT112CR */
+       PORTCR(113, 0xe6052071), /* PORT113CR */
+       PORTCR(114, 0xe6052072), /* PORT114CR */
+       PORTCR(115, 0xe6052073), /* PORT115CR */
+       PORTCR(116, 0xe6052074), /* PORT116CR */
+       PORTCR(117, 0xe6052075), /* PORT117CR */
+       PORTCR(118, 0xe6052076), /* PORT118CR */
+
+       PORTCR(128, 0xe6052080), /* PORT128CR */
+       PORTCR(129, 0xe6052081), /* PORT129CR */
+
+       PORTCR(130, 0xe6052082), /* PORT130CR */
+       PORTCR(131, 0xe6052083), /* PORT131CR */
+       PORTCR(132, 0xe6052084), /* PORT132CR */
+       PORTCR(133, 0xe6052085), /* PORT133CR */
+       PORTCR(134, 0xe6052086), /* PORT134CR */
+       PORTCR(135, 0xe6052087), /* PORT135CR */
+       PORTCR(136, 0xe6052088), /* PORT136CR */
+       PORTCR(137, 0xe6052089), /* PORT137CR */
+       PORTCR(138, 0xe605208a), /* PORT138CR */
+       PORTCR(139, 0xe605208b), /* PORT139CR */
+
+       PORTCR(140, 0xe605208c), /* PORT140CR */
+       PORTCR(141, 0xe605208d), /* PORT141CR */
+       PORTCR(142, 0xe605208e), /* PORT142CR */
+       PORTCR(143, 0xe605208f), /* PORT143CR */
+       PORTCR(144, 0xe6052090), /* PORT144CR */
+       PORTCR(145, 0xe6052091), /* PORT145CR */
+       PORTCR(146, 0xe6052092), /* PORT146CR */
+       PORTCR(147, 0xe6052093), /* PORT147CR */
+       PORTCR(148, 0xe6052094), /* PORT148CR */
+       PORTCR(149, 0xe6052095), /* PORT149CR */
+
+       PORTCR(150, 0xe6052096), /* PORT150CR */
+       PORTCR(151, 0xe6052097), /* PORT151CR */
+       PORTCR(152, 0xe6052098), /* PORT152CR */
+       PORTCR(153, 0xe6052099), /* PORT153CR */
+       PORTCR(154, 0xe605209a), /* PORT154CR */
+       PORTCR(155, 0xe605209b), /* PORT155CR */
+       PORTCR(156, 0xe605209c), /* PORT156CR */
+       PORTCR(157, 0xe605209d), /* PORT157CR */
+       PORTCR(158, 0xe605209e), /* PORT158CR */
+       PORTCR(159, 0xe605209f), /* PORT159CR */
+
+       PORTCR(160, 0xe60520a0), /* PORT160CR */
+       PORTCR(161, 0xe60520a1), /* PORT161CR */
+       PORTCR(162, 0xe60520a2), /* PORT162CR */
+       PORTCR(163, 0xe60520a3), /* PORT163CR */
+       PORTCR(164, 0xe60520a4), /* PORT164CR */
+
+       PORTCR(192, 0xe60520c0), /* PORT192CR */
+       PORTCR(193, 0xe60520c1), /* PORT193CR */
+       PORTCR(194, 0xe60520c2), /* PORT194CR */
+       PORTCR(195, 0xe60520c3), /* PORT195CR */
+       PORTCR(196, 0xe60520c4), /* PORT196CR */
+       PORTCR(197, 0xe60520c5), /* PORT197CR */
+       PORTCR(198, 0xe60520c6), /* PORT198CR */
+       PORTCR(199, 0xe60520c7), /* PORT199CR */
+
+       PORTCR(200, 0xe60520c8), /* PORT200CR */
+       PORTCR(201, 0xe60520c9), /* PORT201CR */
+       PORTCR(202, 0xe60520ca), /* PORT202CR */
+       PORTCR(203, 0xe60520cb), /* PORT203CR */
+       PORTCR(204, 0xe60520cc), /* PORT204CR */
+       PORTCR(205, 0xe60520cd), /* PORT205CR */
+       PORTCR(206, 0xe60520ce), /* PORT206CR */
+       PORTCR(207, 0xe60520cf), /* PORT207CR */
+       PORTCR(208, 0xe60520d0), /* PORT208CR */
+       PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+       PORTCR(210, 0xe60520d2), /* PORT210CR */
+       PORTCR(211, 0xe60520d3), /* PORT211CR */
+       PORTCR(212, 0xe60520d4), /* PORT212CR */
+       PORTCR(213, 0xe60520d5), /* PORT213CR */
+       PORTCR(214, 0xe60520d6), /* PORT214CR */
+       PORTCR(215, 0xe60520d7), /* PORT215CR */
+       PORTCR(216, 0xe60520d8), /* PORT216CR */
+       PORTCR(217, 0xe60520d9), /* PORT217CR */
+       PORTCR(218, 0xe60520da), /* PORT218CR */
+       PORTCR(219, 0xe60520db), /* PORT219CR */
+
+       PORTCR(220, 0xe60520dc), /* PORT220CR */
+       PORTCR(221, 0xe60520dd), /* PORT221CR */
+       PORTCR(222, 0xe60520de), /* PORT222CR */
+       PORTCR(223, 0xe60520df), /* PORT223CR */
+       PORTCR(224, 0xe60530e0), /* PORT224CR */
+       PORTCR(225, 0xe60530e1), /* PORT225CR */
+       PORTCR(226, 0xe60530e2), /* PORT226CR */
+       PORTCR(227, 0xe60530e3), /* PORT227CR */
+       PORTCR(228, 0xe60530e4), /* PORT228CR */
+       PORTCR(229, 0xe60530e5), /* PORT229CR */
+
+       PORTCR(230, 0xe60530e6), /* PORT230CR */
+       PORTCR(231, 0xe60530e7), /* PORT231CR */
+       PORTCR(232, 0xe60530e8), /* PORT232CR */
+       PORTCR(233, 0xe60530e9), /* PORT233CR */
+       PORTCR(234, 0xe60530ea), /* PORT234CR */
+       PORTCR(235, 0xe60530eb), /* PORT235CR */
+       PORTCR(236, 0xe60530ec), /* PORT236CR */
+       PORTCR(237, 0xe60530ed), /* PORT237CR */
+       PORTCR(238, 0xe60530ee), /* PORT238CR */
+       PORTCR(239, 0xe60530ef), /* PORT239CR */
+
+       PORTCR(240, 0xe60530f0), /* PORT240CR */
+       PORTCR(241, 0xe60530f1), /* PORT241CR */
+       PORTCR(242, 0xe60530f2), /* PORT242CR */
+       PORTCR(243, 0xe60530f3), /* PORT243CR */
+       PORTCR(244, 0xe60530f4), /* PORT244CR */
+       PORTCR(245, 0xe60530f5), /* PORT245CR */
+       PORTCR(246, 0xe60530f6), /* PORT246CR */
+       PORTCR(247, 0xe60530f7), /* PORT247CR */
+       PORTCR(248, 0xe60530f8), /* PORT248CR */
+       PORTCR(249, 0xe60530f9), /* PORT249CR */
+
+       PORTCR(250, 0xe60530fa), /* PORT250CR */
+       PORTCR(251, 0xe60530fb), /* PORT251CR */
+       PORTCR(252, 0xe60530fc), /* PORT252CR */
+       PORTCR(253, 0xe60530fd), /* PORT253CR */
+       PORTCR(254, 0xe60530fe), /* PORT254CR */
+       PORTCR(255, 0xe60530ff), /* PORT255CR */
+       PORTCR(256, 0xe6053100), /* PORT256CR */
+       PORTCR(257, 0xe6053101), /* PORT257CR */
+       PORTCR(258, 0xe6053102), /* PORT258CR */
+       PORTCR(259, 0xe6053103), /* PORT259CR */
+
+       PORTCR(260, 0xe6053104), /* PORT260CR */
+       PORTCR(261, 0xe6053105), /* PORT261CR */
+       PORTCR(262, 0xe6053106), /* PORT262CR */
+       PORTCR(263, 0xe6053107), /* PORT263CR */
+       PORTCR(264, 0xe6053108), /* PORT264CR */
+       PORTCR(265, 0xe6053109), /* PORT265CR */
+       PORTCR(266, 0xe605310a), /* PORT266CR */
+       PORTCR(267, 0xe605310b), /* PORT267CR */
+       PORTCR(268, 0xe605310c), /* PORT268CR */
+       PORTCR(269, 0xe605310d), /* PORT269CR */
+
+       PORTCR(270, 0xe605310e), /* PORT270CR */
+       PORTCR(271, 0xe605310f), /* PORT271CR */
+       PORTCR(272, 0xe6053110), /* PORT272CR */
+       PORTCR(273, 0xe6053111), /* PORT273CR */
+       PORTCR(274, 0xe6053112), /* PORT274CR */
+       PORTCR(275, 0xe6053113), /* PORT275CR */
+       PORTCR(276, 0xe6053114), /* PORT276CR */
+       PORTCR(277, 0xe6053115), /* PORT277CR */
+       PORTCR(278, 0xe6053116), /* PORT278CR */
+       PORTCR(279, 0xe6053117), /* PORT279CR */
+
+       PORTCR(280, 0xe6053118), /* PORT280CR */
+       PORTCR(281, 0xe6053119), /* PORT281CR */
+       PORTCR(282, 0xe605311a), /* PORT282CR */
+
+       PORTCR(288, 0xe6052120), /* PORT288CR */
+       PORTCR(289, 0xe6052121), /* PORT289CR */
+
+       PORTCR(290, 0xe6052122), /* PORT290CR */
+       PORTCR(291, 0xe6052123), /* PORT291CR */
+       PORTCR(292, 0xe6052124), /* PORT292CR */
+       PORTCR(293, 0xe6052125), /* PORT293CR */
+       PORTCR(294, 0xe6052126), /* PORT294CR */
+       PORTCR(295, 0xe6052127), /* PORT295CR */
+       PORTCR(296, 0xe6052128), /* PORT296CR */
+       PORTCR(297, 0xe6052129), /* PORT297CR */
+       PORTCR(298, 0xe605212a), /* PORT298CR */
+       PORTCR(299, 0xe605212b), /* PORT299CR */
+
+       PORTCR(300, 0xe605212c), /* PORT300CR */
+       PORTCR(301, 0xe605212d), /* PORT301CR */
+       PORTCR(302, 0xe605212e), /* PORT302CR */
+       PORTCR(303, 0xe605212f), /* PORT303CR */
+       PORTCR(304, 0xe6052130), /* PORT304CR */
+       PORTCR(305, 0xe6052131), /* PORT305CR */
+       PORTCR(306, 0xe6052132), /* PORT306CR */
+       PORTCR(307, 0xe6052133), /* PORT307CR */
+       PORTCR(308, 0xe6052134), /* PORT308CR */
+       PORTCR(309, 0xe6052135), /* PORT309CR */
+
+       { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+                       MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+                       MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+                       MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+                       0, 0,
+                       MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+                       MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+                       MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+                       MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+                       MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+                       MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+                       MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+                       MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+                       MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+                       MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+                       MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+                       MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+                       MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+                       MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+                       MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+               }
+       },
+       { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+                       0, 0,
+                       MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+                       0, 0,
+                       0, 0,
+                       MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+                       0, 0,
+                       0, 0,
+               }
+       },
+       { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
+                       0, 0,
+                       0, 0,
+                       MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+                       0, 0,
+                       MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+                       MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+                       MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+                       MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+                       MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+                       0, 0,
+                       0, 0,
+                       0, 0,
+                       MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+                       0, 0,
+                       MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+                       MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+                       MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+                       MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+                       MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+                       MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+                       MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+                       0, 0,
+                       0, 0,
+                       MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+                       0, 0,
+                       0, 0,
+                       MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+                       0, 0,
+               }
+       },
+       { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+       { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+                       PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+                       PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+                       PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+                       PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+                       PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+                       PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+                       PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+                       PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+       },
+       { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
+                       PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+                       PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+                       PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+                       PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+                       PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+                       PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+                       PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+                       PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+       },
+       { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
+                       PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+                       PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+                       PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+                       PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+                       PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+                       PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+                       PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+                       PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+       },
+       { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
+                       0, 0, 0, 0,
+                       0, 0, 0, 0,
+                       0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+                       PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+                       PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+                       PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+                       PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+                       PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+       },
+       { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
+                       PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+                       PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+                       PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+                       PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+                       PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+                       PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+                       PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+                       PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+       },
+       { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
+                       0, 0, 0, 0,
+                       0, 0, 0, 0,
+                       0, 0, 0, 0,
+                       0, 0, 0, 0,
+                       0, 0, 0, 0,
+                       0, 0, 0, 0,
+                       0, 0, 0, PORT164_DATA,
+                       PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+       },
+       { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
+                       PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+                       PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+                       PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+                       PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+                       PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+                       PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+                       PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+                       PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+       },
+       { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
+                       PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
+                       PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+                       PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+                       PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+                       PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+                       PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+                       PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+                       PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
+       },
+       { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
+                       0, 0, 0, 0,
+                       0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
+                       PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
+                       PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
+                       PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+                       PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+                       PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+                       PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
+       },
+       { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
+                       0, 0, 0, 0,
+                       0, 0, 0, 0,
+                       0, 0, PORT309_DATA, PORT308_DATA,
+                       PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
+                       PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
+                       PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
+                       PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
+                       PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
+       },
+       { },
+};
+
+static struct pinmux_info sh73a0_pinmux_info = {
+       .name = "sh73a0_pfc",
+       .reserved_id = PINMUX_RESERVED,
+       .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+       .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+       .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+       .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+       .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+       .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+       .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+       .first_gpio = GPIO_PORT0,
+       .last_gpio = GPIO_FN_FSIAISLD_PU,
+
+       .gpios = pinmux_gpios,
+       .cfg_regs = pinmux_config_regs,
+       .data_regs = pinmux_data_regs,
+
+       .gpio_data = pinmux_data,
+       .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void sh73a0_pinmux_init(void)
+{
+       register_pinmux(&sh73a0_pinmux_info);
+}
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
new file mode 100644 (file)
index 0000000..3c2c0f4
--- /dev/null
@@ -0,0 +1,85 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/localtimer.h>
+#include <asm/mach-types.h>
+#include <mach/common.h>
+
+static unsigned int __init shmobile_smp_get_core_count(void)
+{
+       if (machine_is_ag5evm())
+               return sh73a0_get_core_count();
+
+       return 1;
+}
+
+static void __init shmobile_smp_prepare_cpus(void)
+{
+       if (machine_is_ag5evm())
+               sh73a0_smp_prepare_cpus();
+}
+
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+       trace_hardirqs_off();
+
+       if (machine_is_ag5evm())
+               sh73a0_secondary_init(cpu);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+       if (machine_is_ag5evm())
+               return sh73a0_boot_secondary(cpu);
+
+       return -ENOSYS;
+}
+
+void __init smp_init_cpus(void)
+{
+       unsigned int ncores = shmobile_smp_get_core_count();
+       unsigned int i;
+
+       for (i = 0; i < ncores; i++)
+               set_cpu_possible(i, true);
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+       unsigned int ncores = shmobile_smp_get_core_count();
+       unsigned int cpu = smp_processor_id();
+       int i;
+
+       smp_store_cpu_info(cpu);
+
+       if (max_cpus > ncores)
+               max_cpus = ncores;
+
+       for (i = 0; i < max_cpus; i++)
+               set_cpu_present(i, true);
+
+       if (max_cpus > 1) {
+               shmobile_smp_prepare_cpus();
+
+               /*
+                * Enable the local timer or broadcast device for the
+                * boot CPU, but only if we have more than one CPU.
+                */
+               percpu_timer_setup();
+       }
+}
index 564a6d0be473b738d149f56bdfd775563301016f..2e3e11ee7c431d22f863cba1b2027ad388a07008 100644 (file)
@@ -416,6 +416,16 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
                .addr           = 0xe6870030,
                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
                .mid_rid        = 0xce,
+       }, {
+               .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+               .addr           = 0xe6bd0034,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+               .mid_rid        = 0xd1,
+       }, {
+               .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+               .addr           = 0xe6bd0034,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+               .mid_rid        = 0xd2,
        },
 };
 
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
new file mode 100644 (file)
index 0000000..f1eff8b
--- /dev/null
@@ -0,0 +1,412 @@
+/*
+ * sh73a0 processor support
+ *
+ * Copyright (C) 2010  Takashi Yoshii
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_intc.h>
+#include <linux/sh_timer.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static struct plat_sci_port scif0_platform_data = {
+       .mapbase        = 0xe6c40000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFA,
+       .irqs           = { gic_spi(72), gic_spi(72),
+                           gic_spi(72), gic_spi(72) },
+};
+
+static struct platform_device scif0_device = {
+       .name           = "sh-sci",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &scif0_platform_data,
+       },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+       .mapbase        = 0xe6c50000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFA,
+       .irqs           = { gic_spi(73), gic_spi(73),
+                           gic_spi(73), gic_spi(73) },
+};
+
+static struct platform_device scif1_device = {
+       .name           = "sh-sci",
+       .id             = 1,
+       .dev            = {
+               .platform_data  = &scif1_platform_data,
+       },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+       .mapbase        = 0xe6c60000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFA,
+       .irqs           = { gic_spi(74), gic_spi(74),
+                           gic_spi(74), gic_spi(74) },
+};
+
+static struct platform_device scif2_device = {
+       .name           = "sh-sci",
+       .id             = 2,
+       .dev            = {
+               .platform_data  = &scif2_platform_data,
+       },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+       .mapbase        = 0xe6c70000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFA,
+       .irqs           = { gic_spi(75), gic_spi(75),
+                           gic_spi(75), gic_spi(75) },
+};
+
+static struct platform_device scif3_device = {
+       .name           = "sh-sci",
+       .id             = 3,
+       .dev            = {
+               .platform_data  = &scif3_platform_data,
+       },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+       .mapbase        = 0xe6c80000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFA,
+       .irqs           = { gic_spi(78), gic_spi(78),
+                           gic_spi(78), gic_spi(78) },
+};
+
+static struct platform_device scif4_device = {
+       .name           = "sh-sci",
+       .id             = 4,
+       .dev            = {
+               .platform_data  = &scif4_platform_data,
+       },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+       .mapbase        = 0xe6cb0000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFA,
+       .irqs           = { gic_spi(79), gic_spi(79),
+                           gic_spi(79), gic_spi(79) },
+};
+
+static struct platform_device scif5_device = {
+       .name           = "sh-sci",
+       .id             = 5,
+       .dev            = {
+               .platform_data  = &scif5_platform_data,
+       },
+};
+
+static struct plat_sci_port scif6_platform_data = {
+       .mapbase        = 0xe6cc0000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFA,
+       .irqs           = { gic_spi(156), gic_spi(156),
+                           gic_spi(156), gic_spi(156) },
+};
+
+static struct platform_device scif6_device = {
+       .name           = "sh-sci",
+       .id             = 6,
+       .dev            = {
+               .platform_data  = &scif6_platform_data,
+       },
+};
+
+static struct plat_sci_port scif7_platform_data = {
+       .mapbase        = 0xe6cd0000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFA,
+       .irqs           = { gic_spi(143), gic_spi(143),
+                           gic_spi(143), gic_spi(143) },
+};
+
+static struct platform_device scif7_device = {
+       .name           = "sh-sci",
+       .id             = 7,
+       .dev            = {
+               .platform_data  = &scif7_platform_data,
+       },
+};
+
+static struct plat_sci_port scif8_platform_data = {
+       .mapbase        = 0xe6c30000,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .type           = PORT_SCIFB,
+       .irqs           = { gic_spi(80), gic_spi(80),
+                           gic_spi(80), gic_spi(80) },
+};
+
+static struct platform_device scif8_device = {
+       .name           = "sh-sci",
+       .id             = 8,
+       .dev            = {
+               .platform_data  = &scif8_platform_data,
+       },
+};
+
+static struct sh_timer_config cmt10_platform_data = {
+       .name = "CMT10",
+       .channel_offset = 0x10,
+       .timer_bit = 0,
+       .clockevent_rating = 125,
+       .clocksource_rating = 125,
+};
+
+static struct resource cmt10_resources[] = {
+       [0] = {
+               .name   = "CMT10",
+               .start  = 0xe6138010,
+               .end    = 0xe613801b,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(65),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device cmt10_device = {
+       .name           = "sh_cmt",
+       .id             = 10,
+       .dev = {
+               .platform_data  = &cmt10_platform_data,
+       },
+       .resource       = cmt10_resources,
+       .num_resources  = ARRAY_SIZE(cmt10_resources),
+};
+
+/* TMU */
+static struct sh_timer_config tmu00_platform_data = {
+       .name = "TMU00",
+       .channel_offset = 0x4,
+       .timer_bit = 0,
+       .clockevent_rating = 200,
+};
+
+static struct resource tmu00_resources[] = {
+       [0] = {
+               .name   = "TMU00",
+               .start  = 0xfff60008,
+               .end    = 0xfff60013,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device tmu00_device = {
+       .name           = "sh_tmu",
+       .id             = 0,
+       .dev = {
+               .platform_data  = &tmu00_platform_data,
+       },
+       .resource       = tmu00_resources,
+       .num_resources  = ARRAY_SIZE(tmu00_resources),
+};
+
+static struct sh_timer_config tmu01_platform_data = {
+       .name = "TMU01",
+       .channel_offset = 0x10,
+       .timer_bit = 1,
+       .clocksource_rating = 200,
+};
+
+static struct resource tmu01_resources[] = {
+       [0] = {
+               .name   = "TMU01",
+               .start  = 0xfff60014,
+               .end    = 0xfff6001f,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device tmu01_device = {
+       .name           = "sh_tmu",
+       .id             = 1,
+       .dev = {
+               .platform_data  = &tmu01_platform_data,
+       },
+       .resource       = tmu01_resources,
+       .num_resources  = ARRAY_SIZE(tmu01_resources),
+};
+
+static struct resource i2c0_resources[] = {
+       [0] = {
+               .name   = "IIC0",
+               .start  = 0xe6820000,
+               .end    = 0xe6820425 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(167),
+               .end    = gic_spi(170),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct resource i2c1_resources[] = {
+       [0] = {
+               .name   = "IIC1",
+               .start  = 0xe6822000,
+               .end    = 0xe6822425 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(51),
+               .end    = gic_spi(54),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct resource i2c2_resources[] = {
+       [0] = {
+               .name   = "IIC2",
+               .start  = 0xe6824000,
+               .end    = 0xe6824425 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(171),
+               .end    = gic_spi(174),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct resource i2c3_resources[] = {
+       [0] = {
+               .name   = "IIC3",
+               .start  = 0xe6826000,
+               .end    = 0xe6826425 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(183),
+               .end    = gic_spi(186),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct resource i2c4_resources[] = {
+       [0] = {
+               .name   = "IIC4",
+               .start  = 0xe6828000,
+               .end    = 0xe6828425 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(187),
+               .end    = gic_spi(190),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device i2c0_device = {
+       .name           = "i2c-sh_mobile",
+       .id             = 0,
+       .resource       = i2c0_resources,
+       .num_resources  = ARRAY_SIZE(i2c0_resources),
+};
+
+static struct platform_device i2c1_device = {
+       .name           = "i2c-sh_mobile",
+       .id             = 1,
+       .resource       = i2c1_resources,
+       .num_resources  = ARRAY_SIZE(i2c1_resources),
+};
+
+static struct platform_device i2c2_device = {
+       .name           = "i2c-sh_mobile",
+       .id             = 2,
+       .resource       = i2c2_resources,
+       .num_resources  = ARRAY_SIZE(i2c2_resources),
+};
+
+static struct platform_device i2c3_device = {
+       .name           = "i2c-sh_mobile",
+       .id             = 3,
+       .resource       = i2c3_resources,
+       .num_resources  = ARRAY_SIZE(i2c3_resources),
+};
+
+static struct platform_device i2c4_device = {
+       .name           = "i2c-sh_mobile",
+       .id             = 4,
+       .resource       = i2c4_resources,
+       .num_resources  = ARRAY_SIZE(i2c4_resources),
+};
+
+static struct platform_device *sh73a0_early_devices[] __initdata = {
+       &scif0_device,
+       &scif1_device,
+       &scif2_device,
+       &scif3_device,
+       &scif4_device,
+       &scif5_device,
+       &scif6_device,
+       &scif7_device,
+       &scif8_device,
+       &cmt10_device,
+       &tmu00_device,
+       &tmu01_device,
+};
+
+static struct platform_device *sh73a0_late_devices[] __initdata = {
+       &i2c0_device,
+       &i2c1_device,
+       &i2c2_device,
+       &i2c3_device,
+       &i2c4_device,
+};
+
+void __init sh73a0_add_standard_devices(void)
+{
+       platform_add_devices(sh73a0_early_devices,
+                           ARRAY_SIZE(sh73a0_early_devices));
+       platform_add_devices(sh73a0_late_devices,
+                           ARRAY_SIZE(sh73a0_late_devices));
+}
+
+void __init sh73a0_add_early_devices(void)
+{
+       early_platform_add_devices(sh73a0_early_devices,
+                                  ARRAY_SIZE(sh73a0_early_devices));
+}
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
new file mode 100644 (file)
index 0000000..4e71fd4
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile - sh73a0 portion
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2010  Takashi Yoshii
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <mach/common.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/gic.h>
+
+#define WUPCR          0xe6151010
+#define SRESCR         0xe6151018
+#define PSTR           0xe6151040
+#define SBAR            0xe6180020
+#define APARMBAREA      0xe6f10020
+
+static void __iomem *scu_base_addr(void)
+{
+       return (void __iomem *)0xf0000000;
+}
+
+static DEFINE_SPINLOCK(scu_lock);
+static unsigned long tmp;
+
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+       void __iomem *scu_base = scu_base_addr();
+
+       spin_lock(&scu_lock);
+       tmp = __raw_readl(scu_base + 8);
+       tmp &= ~clr;
+       tmp |= set;
+       spin_unlock(&scu_lock);
+
+       /* disable cache coherency after releasing the lock */
+       __raw_writel(tmp, scu_base + 8);
+}
+
+unsigned int __init sh73a0_get_core_count(void)
+{
+       void __iomem *scu_base = scu_base_addr();
+
+       return scu_get_core_count(scu_base);
+}
+
+void __cpuinit sh73a0_secondary_init(unsigned int cpu)
+{
+       gic_cpu_init(0, __io(0xf0000100));
+}
+
+int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
+{
+       /* enable cache coherency */
+       modify_scu_cpu_psr(0, 3 << (cpu * 8));
+
+       if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
+               __raw_writel(1 << cpu, __io(WUPCR));    /* wake up */
+       else
+               __raw_writel(1 << cpu, __io(SRESCR));   /* reset */
+
+       return 0;
+}
+
+void __init sh73a0_smp_prepare_cpus(void)
+{
+#ifdef CONFIG_HAVE_ARM_TWD
+       twd_base = (void __iomem *)0xf0000600;
+#endif
+
+       scu_enable(scu_base_addr());
+
+       /* Map the reset vector (in headsmp.S) */
+       __raw_writel(0, __io(APARMBAREA));      /* 4k */
+       __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
+
+       /* enable cache coherency on CPU0 */
+       modify_scu_cpu_psr(0, 3 << (0 * 8));
+}
index 49db8b3e4a497643ce3c9ec08268ca217e3d3b10..fcc1e628e050471d7bfde79e772075dbb0735b97 100644 (file)
@@ -813,7 +813,7 @@ config CACHE_L2X0
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
                   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
-                  ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+                  ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
        default y
        select OUTER_CACHE
        select OUTER_CACHE_SYNC
index 08fb42269ecd1c836c29d7b85b993a4796764dcf..3670455faaac907687c8d5598c958a29c419c27e 100644 (file)
@@ -4,7 +4,7 @@
 
 #else /* __ASSEMBLY__ */
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
 }
 
index 1dcf5e6c8d83239966df26af919fa5fa2300bccb..d63ef51ec186f7cf2fd5ce73779d88ec332306c0 100644 (file)
@@ -35,7 +35,7 @@
 #define HIZCRA         0xa4050158
 #define PGDR           0xa405012c
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
        /* disable Hi-Z for LED pins */
        __raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);
index 976256a323f2c4a85e1bdd9dbd18b1209f5e5ba0..7a883167c84619f5a5a3e064c5183582842eea47 100644 (file)
@@ -23,7 +23,7 @@
 
 #else /* __ASSEMBLY__ */
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
 }
 
index ddd09840520b69c5cba9d5673c3d6e1b51abeed4..12884c270171d2e81e5a87c2854e0005cdf085cb 100644 (file)
  *
  */
 
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
 #include <linux/dma-mapping.h>
-#include <linux/mmc/host.h>
+#include <linux/dmaengine.h>
 #include <linux/mmc/card.h>
 #include <linux/mmc/core.h>
+#include <linux/mmc/host.h>
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/sdio.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
 #include <linux/mmc/sh_mmcif.h>
+#include <linux/pagemap.h>
+#include <linux/platform_device.h>
 
 #define DRIVER_NAME    "sh_mmcif"
 #define DRIVER_VERSION "2010-04-28"
 /* CE_BLOCK_SET */
 #define BLOCK_SIZE_MASK                0x0000ffff
 
-/* CE_CLK_CTRL */
-#define CLK_ENABLE             (1 << 24) /* 1: output mmc clock */
-#define CLK_CLEAR              ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
-#define CLK_SUP_PCLK           ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
-#define SRSPTO_256             ((1 << 13) | (0 << 12)) /* resp timeout */
-#define SRBSYTO_29             ((1 << 11) | (1 << 10) |        \
-                                (1 << 9) | (1 << 8)) /* resp busy timeout */
-#define SRWDTO_29              ((1 << 7) | (1 << 6) |          \
-                                (1 << 5) | (1 << 4)) /* read/write timeout */
-#define SCCSTO_29              ((1 << 3) | (1 << 2) |          \
-                                (1 << 1) | (1 << 0)) /* ccs timeout */
-
-/* CE_BUF_ACC */
-#define BUF_ACC_DMAWEN         (1 << 25)
-#define BUF_ACC_DMAREN         (1 << 24)
-#define BUF_ACC_BUSW_32                (0 << 17)
-#define BUF_ACC_BUSW_16                (1 << 17)
-#define BUF_ACC_ATYP           (1 << 16)
-
 /* CE_INT */
 #define INT_CCSDE              (1 << 29)
 #define INT_CMD12DRE           (1 << 26)
                                 STS2_AC12BSYTO | STS2_RSPBSYTO |       \
                                 STS2_AC12RSPTO | STS2_RSPTO)
 
-/* CE_VERSION */
-#define SOFT_RST_ON            (1 << 31)
-#define SOFT_RST_OFF           (0 << 31)
-
 #define CLKDEV_EMMC_DATA       52000000 /* 52MHz */
 #define CLKDEV_MMC_DATA                20000000 /* 20MHz */
 #define CLKDEV_INIT            400000   /* 400 KHz */
 struct sh_mmcif_host {
        struct mmc_host *mmc;
        struct mmc_data *data;
-       struct mmc_command *cmd;
        struct platform_device *pd;
        struct clk *hclk;
        unsigned int clk;
        int bus_width;
-       u16 wait_int;
-       u16 sd_error;
+       bool sd_error;
        long timeout;
        void __iomem *addr;
-       wait_queue_head_t intr_wait;
-};
+       struct completion intr_wait;
 
+       /* DMA support */
+       struct dma_chan         *chan_rx;
+       struct dma_chan         *chan_tx;
+       struct completion       dma_complete;
+       unsigned int            dma_sglen;
+};
 
 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
                                        unsigned int reg, u32 val)
@@ -201,6 +184,188 @@ static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
        writel(~val & readl(host->addr + reg), host->addr + reg);
 }
 
+static void mmcif_dma_complete(void *arg)
+{
+       struct sh_mmcif_host *host = arg;
+       dev_dbg(&host->pd->dev, "Command completed\n");
+
+       if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
+                dev_name(&host->pd->dev)))
+               return;
+
+       if (host->data->flags & MMC_DATA_READ)
+               dma_unmap_sg(&host->pd->dev, host->data->sg, host->dma_sglen,
+                            DMA_FROM_DEVICE);
+       else
+               dma_unmap_sg(&host->pd->dev, host->data->sg, host->dma_sglen,
+                            DMA_TO_DEVICE);
+
+       complete(&host->dma_complete);
+}
+
+static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
+{
+       struct scatterlist *sg = host->data->sg;
+       struct dma_async_tx_descriptor *desc = NULL;
+       struct dma_chan *chan = host->chan_rx;
+       dma_cookie_t cookie = -EINVAL;
+       int ret;
+
+       ret = dma_map_sg(&host->pd->dev, sg, host->data->sg_len, DMA_FROM_DEVICE);
+       if (ret > 0) {
+               host->dma_sglen = ret;
+               desc = chan->device->device_prep_slave_sg(chan, sg, ret,
+                       DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+       }
+
+       if (desc) {
+               desc->callback = mmcif_dma_complete;
+               desc->callback_param = host;
+               cookie = desc->tx_submit(desc);
+               if (cookie < 0) {
+                       desc = NULL;
+                       ret = cookie;
+               } else {
+                       sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
+                       chan->device->device_issue_pending(chan);
+               }
+       }
+       dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
+               __func__, host->data->sg_len, ret, cookie);
+
+       if (!desc) {
+               /* DMA failed, fall back to PIO */
+               if (ret >= 0)
+                       ret = -EIO;
+               host->chan_rx = NULL;
+               host->dma_sglen = 0;
+               dma_release_channel(chan);
+               /* Free the Tx channel too */
+               chan = host->chan_tx;
+               if (chan) {
+                       host->chan_tx = NULL;
+                       dma_release_channel(chan);
+               }
+               dev_warn(&host->pd->dev,
+                        "DMA failed: %d, falling back to PIO\n", ret);
+               sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
+       }
+
+       dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
+               desc, cookie, host->data->sg_len);
+}
+
+static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
+{
+       struct scatterlist *sg = host->data->sg;
+       struct dma_async_tx_descriptor *desc = NULL;
+       struct dma_chan *chan = host->chan_tx;
+       dma_cookie_t cookie = -EINVAL;
+       int ret;
+
+       ret = dma_map_sg(&host->pd->dev, sg, host->data->sg_len, DMA_TO_DEVICE);
+       if (ret > 0) {
+               host->dma_sglen = ret;
+               desc = chan->device->device_prep_slave_sg(chan, sg, ret,
+                       DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+       }
+
+       if (desc) {
+               desc->callback = mmcif_dma_complete;
+               desc->callback_param = host;
+               cookie = desc->tx_submit(desc);
+               if (cookie < 0) {
+                       desc = NULL;
+                       ret = cookie;
+               } else {
+                       sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
+                       chan->device->device_issue_pending(chan);
+               }
+       }
+       dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
+               __func__, host->data->sg_len, ret, cookie);
+
+       if (!desc) {
+               /* DMA failed, fall back to PIO */
+               if (ret >= 0)
+                       ret = -EIO;
+               host->chan_tx = NULL;
+               host->dma_sglen = 0;
+               dma_release_channel(chan);
+               /* Free the Rx channel too */
+               chan = host->chan_rx;
+               if (chan) {
+                       host->chan_rx = NULL;
+                       dma_release_channel(chan);
+               }
+               dev_warn(&host->pd->dev,
+                        "DMA failed: %d, falling back to PIO\n", ret);
+               sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
+       }
+
+       dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
+               desc, cookie);
+}
+
+static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
+{
+       dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
+       chan->private = arg;
+       return true;
+}
+
+static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
+                                struct sh_mmcif_plat_data *pdata)
+{
+       host->dma_sglen = 0;
+
+       /* We can only either use DMA for both Tx and Rx or not use it at all */
+       if (pdata->dma) {
+               dma_cap_mask_t mask;
+
+               dma_cap_zero(mask);
+               dma_cap_set(DMA_SLAVE, mask);
+
+               host->chan_tx = dma_request_channel(mask, sh_mmcif_filter,
+                                                   &pdata->dma->chan_priv_tx);
+               dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
+                       host->chan_tx);
+
+               if (!host->chan_tx)
+                       return;
+
+               host->chan_rx = dma_request_channel(mask, sh_mmcif_filter,
+                                                   &pdata->dma->chan_priv_rx);
+               dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
+                       host->chan_rx);
+
+               if (!host->chan_rx) {
+                       dma_release_channel(host->chan_tx);
+                       host->chan_tx = NULL;
+                       return;
+               }
+
+               init_completion(&host->dma_complete);
+       }
+}
+
+static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
+{
+       sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
+       /* Descriptors are freed automatically */
+       if (host->chan_tx) {
+               struct dma_chan *chan = host->chan_tx;
+               host->chan_tx = NULL;
+               dma_release_channel(chan);
+       }
+       if (host->chan_rx) {
+               struct dma_chan *chan = host->chan_rx;
+               host->chan_rx = NULL;
+               dma_release_channel(chan);
+       }
+
+       host->dma_sglen = 0;
+}
 
 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 {
@@ -239,13 +404,12 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
        u32 state1, state2;
        int ret, timeout = 10000000;
 
-       host->sd_error = 0;
-       host->wait_int = 0;
+       host->sd_error = false;
 
        state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
        state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
-       pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
-       pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
+       dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
+       dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 
        if (state1 & STS1_CMDSEQ) {
                sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
@@ -253,8 +417,8 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
                while (1) {
                        timeout--;
                        if (timeout < 0) {
-                               pr_err(DRIVER_NAME": Forceed end of " \
-                                       "command sequence timeout err\n");
+                               dev_err(&host->pd->dev,
+                                       "Forceed end of command sequence timeout err\n");
                                return -EIO;
                        }
                        if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
@@ -263,18 +427,18 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
                        mdelay(1);
                }
                sh_mmcif_sync_reset(host);
-               pr_debug(DRIVER_NAME": Forced end of command sequence\n");
+               dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
                return -EIO;
        }
 
        if (state2 & STS2_CRC_ERR) {
-               pr_debug(DRIVER_NAME": Happened CRC error\n");
+               dev_dbg(&host->pd->dev, ": Happened CRC error\n");
                ret = -EIO;
        } else if (state2 & STS2_TIMEOUT_ERR) {
-               pr_debug(DRIVER_NAME": Happened Timeout error\n");
+               dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
                ret = -ETIMEDOUT;
        } else {
-               pr_debug(DRIVER_NAME": Happened End/Index error\n");
+               dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
                ret = -EIO;
        }
        return ret;
@@ -287,17 +451,13 @@ static int sh_mmcif_single_read(struct sh_mmcif_host *host,
        long time;
        u32 blocksize, i, *p = sg_virt(data->sg);
 
-       host->wait_int = 0;
-
        /* buf read enable */
        sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
-       time = wait_event_interruptible_timeout(host->intr_wait,
-                       host->wait_int == 1 ||
-                       host->sd_error == 1, host->timeout);
-       if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
+       time = wait_for_completion_interruptible_timeout(&host->intr_wait,
+                       host->timeout);
+       if (time <= 0 || host->sd_error)
                return sh_mmcif_error_manage(host);
 
-       host->wait_int = 0;
        blocksize = (BLOCK_SIZE_MASK &
                        sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
        for (i = 0; i < blocksize / 4; i++)
@@ -305,13 +465,11 @@ static int sh_mmcif_single_read(struct sh_mmcif_host *host,
 
        /* buffer read end */
        sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
-       time = wait_event_interruptible_timeout(host->intr_wait,
-                       host->wait_int == 1 ||
-                       host->sd_error == 1, host->timeout);
-       if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
+       time = wait_for_completion_interruptible_timeout(&host->intr_wait,
+                       host->timeout);
+       if (time <= 0 || host->sd_error)
                return sh_mmcif_error_manage(host);
 
-       host->wait_int = 0;
        return 0;
 }
 
@@ -326,19 +484,15 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
                                                     MMCIF_CE_BLOCK_SET);
        for (j = 0; j < data->sg_len; j++) {
                p = sg_virt(data->sg);
-               host->wait_int = 0;
                for (sec = 0; sec < data->sg->length / blocksize; sec++) {
                        sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
                        /* buf read enable */
-                       time = wait_event_interruptible_timeout(host->intr_wait,
-                               host->wait_int == 1 ||
-                               host->sd_error == 1, host->timeout);
+                       time = wait_for_completion_interruptible_timeout(&host->intr_wait,
+                               host->timeout);
 
-                       if (host->wait_int != 1 &&
-                           (time == 0 || host->sd_error != 0))
+                       if (time <= 0 || host->sd_error)
                                return sh_mmcif_error_manage(host);
 
-                       host->wait_int = 0;
                        for (i = 0; i < blocksize / 4; i++)
                                *p++ = sh_mmcif_readl(host->addr,
                                                      MMCIF_CE_DATA);
@@ -356,17 +510,14 @@ static int sh_mmcif_single_write(struct sh_mmcif_host *host,
        long time;
        u32 blocksize, i, *p = sg_virt(data->sg);
 
-       host->wait_int = 0;
        sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 
        /* buf write enable */
-       time = wait_event_interruptible_timeout(host->intr_wait,
-                       host->wait_int == 1 ||
-                       host->sd_error == 1, host->timeout);
-       if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
+       time = wait_for_completion_interruptible_timeout(&host->intr_wait,
+                       host->timeout);
+       if (time <= 0 || host->sd_error)
                return sh_mmcif_error_manage(host);
 
-       host->wait_int = 0;
        blocksize = (BLOCK_SIZE_MASK &
                        sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
        for (i = 0; i < blocksize / 4; i++)
@@ -375,13 +526,11 @@ static int sh_mmcif_single_write(struct sh_mmcif_host *host,
        /* buffer write end */
        sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 
-       time = wait_event_interruptible_timeout(host->intr_wait,
-                       host->wait_int == 1 ||
-                       host->sd_error == 1, host->timeout);
-       if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
+       time = wait_for_completion_interruptible_timeout(&host->intr_wait,
+                       host->timeout);
+       if (time <= 0 || host->sd_error)
                return sh_mmcif_error_manage(host);
 
-       host->wait_int = 0;
        return 0;
 }
 
@@ -397,19 +546,15 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
 
        for (j = 0; j < data->sg_len; j++) {
                p = sg_virt(data->sg);
-               host->wait_int = 0;
                for (sec = 0; sec < data->sg->length / blocksize; sec++) {
                        sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
                        /* buf write enable*/
-                       time = wait_event_interruptible_timeout(host->intr_wait,
-                               host->wait_int == 1 ||
-                               host->sd_error == 1, host->timeout);
+                       time = wait_for_completion_interruptible_timeout(&host->intr_wait,
+                               host->timeout);
 
-                       if (host->wait_int != 1 &&
-                           (time == 0 || host->sd_error != 0))
+                       if (time <= 0 || host->sd_error)
                                return sh_mmcif_error_manage(host);
 
-                       host->wait_int = 0;
                        for (i = 0; i < blocksize / 4; i++)
                                sh_mmcif_writel(host->addr,
                                                MMCIF_CE_DATA, *p++);
@@ -457,7 +602,7 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
                tmp |= CMD_SET_RTYP_17B;
                break;
        default:
-               pr_err(DRIVER_NAME": Not support type response.\n");
+               dev_err(&host->pd->dev, "Unsupported response type.\n");
                break;
        }
        switch (opc) {
@@ -485,7 +630,7 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
                        tmp |= CMD_SET_DATW_8;
                        break;
                default:
-                       pr_err(DRIVER_NAME": Not support bus width.\n");
+                       dev_err(&host->pd->dev, "Unsupported bus width.\n");
                        break;
                }
        }
@@ -513,10 +658,10 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
        return opc = ((opc << 24) | tmp);
 }
 
-static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
+static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
                                struct mmc_request *mrq, u32 opc)
 {
-       u32 ret;
+       int ret;
 
        switch (opc) {
        case MMC_READ_MULTIPLE_BLOCK:
@@ -533,7 +678,7 @@ static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
                ret = sh_mmcif_single_read(host, mrq);
                break;
        default:
-               pr_err(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
+               dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
                ret = -EINVAL;
                break;
        }
@@ -547,8 +692,6 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
        int ret = 0, mask = 0;
        u32 opc = cmd->opcode;
 
-       host->cmd = cmd;
-
        switch (opc) {
        /* respons busy check */
        case MMC_SWITCH:
@@ -579,13 +722,12 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
        sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
        /* set arg */
        sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
-       host->wait_int = 0;
        /* set cmd */
        sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 
-       time = wait_event_interruptible_timeout(host->intr_wait,
-               host->wait_int == 1 || host->sd_error == 1, host->timeout);
-       if (host->wait_int != 1 && time == 0) {
+       time = wait_for_completion_interruptible_timeout(&host->intr_wait,
+               host->timeout);
+       if (time <= 0) {
                cmd->error = sh_mmcif_error_manage(host);
                return;
        }
@@ -597,26 +739,34 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
                        cmd->error = -ETIMEDOUT;
                        break;
                default:
-                       pr_debug("%s: Cmd(d'%d) err\n",
-                                       DRIVER_NAME, cmd->opcode);
+                       dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
+                                       cmd->opcode);
                        cmd->error = sh_mmcif_error_manage(host);
                        break;
                }
-               host->sd_error = 0;
-               host->wait_int = 0;
+               host->sd_error = false;
                return;
        }
        if (!(cmd->flags & MMC_RSP_PRESENT)) {
-               cmd->error = ret;
-               host->wait_int = 0;
+               cmd->error = 0;
                return;
        }
-       if (host->wait_int == 1) {
-               sh_mmcif_get_response(host, cmd);
-               host->wait_int = 0;
-       }
+       sh_mmcif_get_response(host, cmd);
        if (host->data) {
-               ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
+               if (!host->dma_sglen) {
+                       ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
+               } else {
+                       long time =
+                               wait_for_completion_interruptible_timeout(&host->dma_complete,
+                                                                         host->timeout);
+                       if (!time)
+                               ret = -ETIMEDOUT;
+                       else if (time < 0)
+                               ret = time;
+                       sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
+                                       BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
+                       host->dma_sglen = 0;
+               }
                if (ret < 0)
                        mrq->data->bytes_xfered = 0;
                else
@@ -636,20 +786,18 @@ static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
        else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
                sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
        else {
-               pr_err(DRIVER_NAME": not support stop cmd\n");
+               dev_err(&host->pd->dev, "unsupported stop cmd\n");
                cmd->error = sh_mmcif_error_manage(host);
                return;
        }
 
-       time = wait_event_interruptible_timeout(host->intr_wait,
-                       host->wait_int == 1 ||
-                       host->sd_error == 1, host->timeout);
-       if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) {
+       time = wait_for_completion_interruptible_timeout(&host->intr_wait,
+                       host->timeout);
+       if (time <= 0 || host->sd_error) {
                cmd->error = sh_mmcif_error_manage(host);
                return;
        }
        sh_mmcif_get_cmd12response(host, cmd);
-       host->wait_int = 0;
        cmd->error = 0;
 }
 
@@ -676,6 +824,15 @@ static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
                break;
        }
        host->data = mrq->data;
+       if (mrq->data) {
+               if (mrq->data->flags & MMC_DATA_READ) {
+                       if (host->chan_rx)
+                               sh_mmcif_start_dma_rx(host);
+               } else {
+                       if (host->chan_tx)
+                               sh_mmcif_start_dma_tx(host);
+               }
+       }
        sh_mmcif_start_cmd(host, mrq, mrq->cmd);
        host->data = NULL;
 
@@ -735,7 +892,7 @@ static void sh_mmcif_detect(struct mmc_host *mmc)
 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
 {
        struct sh_mmcif_host *host = dev_id;
-       u32 state = 0;
+       u32 state;
        int err = 0;
 
        state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
@@ -774,17 +931,19 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
                sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
                err = 1;
        } else {
-               pr_debug("%s: Not support int\n", DRIVER_NAME);
+               dev_dbg(&host->pd->dev, "Not support int\n");
                sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
                sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
                err = 1;
        }
        if (err) {
-               host->sd_error = 1;
-               pr_debug("%s: int err state = %08x\n", DRIVER_NAME, state);
+               host->sd_error = true;
+               dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
        }
-       host->wait_int = 1;
-       wake_up(&host->intr_wait);
+       if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
+               complete(&host->intr_wait);
+       else
+               dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
 
        return IRQ_HANDLED;
 }
@@ -793,8 +952,8 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
 {
        int ret = 0, irq[2];
        struct mmc_host *mmc;
-       struct sh_mmcif_host *host = NULL;
-       struct sh_mmcif_plat_data *pd = NULL;
+       struct sh_mmcif_host *host;
+       struct sh_mmcif_plat_data *pd;
        struct resource *res;
        void __iomem *reg;
        char clk_name[8];
@@ -802,7 +961,7 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
        irq[0] = platform_get_irq(pdev, 0);
        irq[1] = platform_get_irq(pdev, 1);
        if (irq[0] < 0 || irq[1] < 0) {
-               pr_err(DRIVER_NAME": Get irq error\n");
+               dev_err(&pdev->dev, "Get irq error\n");
                return -ENXIO;
        }
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -815,7 +974,7 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
                dev_err(&pdev->dev, "ioremap error.\n");
                return -ENOMEM;
        }
-       pd = (struct sh_mmcif_plat_data *)(pdev->dev.platform_data);
+       pd = pdev->dev.platform_data;
        if (!pd) {
                dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
                ret = -ENXIO;
@@ -842,7 +1001,7 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
        host->clk = clk_get_rate(host->hclk);
        host->pd = pdev;
 
-       init_waitqueue_head(&host->intr_wait);
+       init_completion(&host->intr_wait);
 
        mmc->ops = &sh_mmcif_ops;
        mmc->f_max = host->clk;
@@ -858,33 +1017,37 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
        mmc->caps = MMC_CAP_MMC_HIGHSPEED;
        if (pd->caps)
                mmc->caps |= pd->caps;
-       mmc->max_segs = 128;
+       mmc->max_segs = 32;
        mmc->max_blk_size = 512;
-       mmc->max_blk_count = 65535;
-       mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+       mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
+       mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
        mmc->max_seg_size = mmc->max_req_size;
 
        sh_mmcif_sync_reset(host);
        platform_set_drvdata(pdev, host);
+
+       /* See if we also get DMA */
+       sh_mmcif_request_dma(host, pd);
+
        mmc_add_host(mmc);
 
        ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
        if (ret) {
-               pr_err(DRIVER_NAME": request_irq error (sh_mmc:error)\n");
+               dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
                goto clean_up2;
        }
        ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
        if (ret) {
                free_irq(irq[0], host);
-               pr_err(DRIVER_NAME": request_irq error (sh_mmc:int)\n");
+               dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
                goto clean_up2;
        }
 
        sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
        sh_mmcif_detect(host->mmc);
 
-       pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
-       pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
+       dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
+       dev_dbg(&pdev->dev, "chip ver H'%04x\n",
                sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
        return ret;
 
@@ -903,20 +1066,22 @@ static int __devexit sh_mmcif_remove(struct platform_device *pdev)
        struct sh_mmcif_host *host = platform_get_drvdata(pdev);
        int irq[2];
 
-       sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
-
-       irq[0] = platform_get_irq(pdev, 0);
-       irq[1] = platform_get_irq(pdev, 1);
+       mmc_remove_host(host->mmc);
+       sh_mmcif_release_dma(host);
 
        if (host->addr)
                iounmap(host->addr);
 
-       platform_set_drvdata(pdev, NULL);
-       mmc_remove_host(host->mmc);
+       sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
+
+       irq[0] = platform_get_irq(pdev, 0);
+       irq[1] = platform_get_irq(pdev, 1);
 
        free_irq(irq[0], host);
        free_irq(irq[1], host);
 
+       platform_set_drvdata(pdev, NULL);
+
        clk_disable(host->hclk);
        mmc_free_host(host->mmc);
 
@@ -947,5 +1112,5 @@ module_exit(sh_mmcif_exit);
 
 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS(DRIVER_NAME);
+MODULE_ALIAS("platform:" DRIVER_NAME);
 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
index d2352ac437c58db944b0848d1fcc8dde10da0ce7..4bc614e4221cdc425ee1aeb91a3a241b9756340c 100644 (file)
@@ -31,6 +31,7 @@
 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
       defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+      defined(CONFIG_ARCH_SH73A0) || \
       defined(CONFIG_ARCH_SH7367) || \
       defined(CONFIG_ARCH_SH7377) || \
       defined(CONFIG_ARCH_SH7372)
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_ARCH_SH73A0) || \
     defined(CONFIG_ARCH_SH7367) || \
     defined(CONFIG_ARCH_SH7377) || \
     defined(CONFIG_ARCH_SH7372)
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_ARCH_SH73A0) || \
     defined(CONFIG_ARCH_SH7367) || \
     defined(CONFIG_ARCH_SH7377) || \
     defined(CONFIG_ARCH_SH7372)
   }
 
 #if defined(CONFIG_CPU_SH3) || \
+    defined(CONFIG_ARCH_SH73A0) || \
     defined(CONFIG_ARCH_SH7367) || \
     defined(CONFIG_ARCH_SH7377) || \
     defined(CONFIG_ARCH_SH7372)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
       defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+      defined(CONFIG_ARCH_SH73A0) || \
       defined(CONFIG_ARCH_SH7367) || \
       defined(CONFIG_ARCH_SH7377)
 #define SCIF_FNS(name, scif_offset, scif_size) \
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_ARCH_SH73A0) || \
     defined(CONFIG_ARCH_SH7367) || \
     defined(CONFIG_ARCH_SH7377)
 
@@ -632,6 +638,7 @@ static inline int sci_rxd_in(struct uart_port *port)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
       defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+      defined(CONFIG_ARCH_SH73A0) || \
       defined(CONFIG_ARCH_SH7367) || \
       defined(CONFIG_ARCH_SH7377) || \
       defined(CONFIG_ARCH_SH7372)
index 5c99da1078aa2e2906e0cc8f06428c231f76970a..44fc5348fd5d7c33dec9f28f1c3227904f8776c1 100644 (file)
@@ -14,8 +14,9 @@
 #ifndef __SH_MMCIF_H__
 #define __SH_MMCIF_H__
 
-#include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/sh_dma.h>
 
 /*
  * MMCIF : CE_CLK_CTRL [19:16]
  * 1111 : Peripheral clock (sup_pclk set '1')
  */
 
+struct sh_mmcif_dma {
+       struct sh_dmae_slave chan_priv_tx;
+       struct sh_dmae_slave chan_priv_rx;
+};
+
 struct sh_mmcif_plat_data {
        void (*set_pwr)(struct platform_device *pdev, int state);
        void (*down_pwr)(struct platform_device *pdev);
        int (*get_cd)(struct platform_device *pdef);
-       u8      sup_pclk;       /* 1 :SH7757, 0: SH7724/SH7372 */
-       unsigned long caps;
-       u32     ocr;
+       struct sh_mmcif_dma     *dma;
+       u8                      sup_pclk;       /* 1 :SH7757, 0: SH7724/SH7372 */
+       unsigned long           caps;
+       u32                     ocr;
 };
 
 #define MMCIF_CE_CMD_SET       0x00000000
@@ -59,6 +66,32 @@ struct sh_mmcif_plat_data {
 #define MMCIF_CE_HOST_STS2     0x0000004C
 #define MMCIF_CE_VERSION       0x0000007C
 
+/* CE_BUF_ACC */
+#define BUF_ACC_DMAWEN         (1 << 25)
+#define BUF_ACC_DMAREN         (1 << 24)
+#define BUF_ACC_BUSW_32                (0 << 17)
+#define BUF_ACC_BUSW_16                (1 << 17)
+#define BUF_ACC_ATYP           (1 << 16)
+
+/* CE_CLK_CTRL */
+#define CLK_ENABLE             (1 << 24) /* 1: output mmc clock */
+#define CLK_CLEAR              ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
+#define CLK_SUP_PCLK           ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
+#define CLKDIV_4               (1<<16) /* mmc clock frequency.
+                                        * n: bus clock/(2^(n+1)) */
+#define CLKDIV_256             (7<<16) /* mmc clock frequency. (see above) */
+#define SRSPTO_256             ((1 << 13) | (0 << 12)) /* resp timeout */
+#define SRBSYTO_29             ((1 << 11) | (1 << 10) |        \
+                                (1 << 9) | (1 << 8)) /* resp busy timeout */
+#define SRWDTO_29              ((1 << 7) | (1 << 6) |          \
+                                (1 << 5) | (1 << 4)) /* read/write timeout */
+#define SCCSTO_29              ((1 << 3) | (1 << 2) |          \
+                                (1 << 1) | (1 << 0)) /* ccs timeout */
+
+/* CE_VERSION */
+#define SOFT_RST_ON            (1 << 31)
+#define SOFT_RST_OFF           0
+
 static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
 {
        return readl(addr + reg);
@@ -145,21 +178,20 @@ static inline int sh_mmcif_boot_do_read(void __iomem *base,
 
 static inline void sh_mmcif_boot_init(void __iomem *base)
 {
-       unsigned long tmp;
-
        /* reset */
-       tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
-       sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000);
-       sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
+       sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
+       sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
 
        /* byte swap */
-       sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000);
+       sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 
        /* Set block size in MMCIF hardware */
        sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
 
-       /* Enable the clock, set it to Bus clock/256 (about 325Khz)*/
-       sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff);
+       /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
+       sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
+                       CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
+                       SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 
        /* CMD0 */
        sh_mmcif_boot_cmd(base, 0x00000040, 0);
@@ -184,7 +216,9 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base,
        unsigned long tmp;
 
        /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
-       sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
+       sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
+                       CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
+                       SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 
        /* CMD9 - Get CSD */
        sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);