]> git.openfabrics.org - ~shefty/rdma-dev.git/commitdiff
Merge branch 'ux500/devel' into next/devel
authorOlof Johansson <olof@lixom.net>
Tue, 20 Dec 2011 18:05:29 +0000 (10:05 -0800)
committerOlof Johansson <olof@lixom.net>
Tue, 20 Dec 2011 18:05:29 +0000 (10:05 -0800)
* ux500/devel:
  ARM: ux500: fix the smp_twd clock calculation
  ARM: ux500: remove support for early silicon revisions
  ARM: ux500: update register files
  ARM: ux500: register DB5500 PMU dynamically
  ARM: ux500: update ASIC detection for U5500
  ARM: ux500: support DB8520

829 files changed:
CREDITS
Documentation/arm/memory.txt
Documentation/devicetree/bindings/arm/gic.txt
Documentation/devicetree/bindings/arm/vic.txt [new file with mode: 0644]
Documentation/kernel-parameters.txt
Documentation/networking/ip-sysctl.txt
Documentation/sound/alsa/soc/machine.txt
Documentation/usb/linux-cdc-acm.inf
MAINTAINERS
Makefile
arch/arm/Kconfig
arch/arm/boot/compressed/head.S
arch/arm/boot/dts/highbank.dts
arch/arm/common/Kconfig
arch/arm/common/gic.c
arch/arm/common/vic.c
arch/arm/configs/omap1_defconfig
arch/arm/include/asm/assembler.h
arch/arm/include/asm/cti.h [new file with mode: 0644]
arch/arm/include/asm/entry-macro-vic2.S [deleted file]
arch/arm/include/asm/hardware/entry-macro-gic.S [deleted file]
arch/arm/include/asm/hardware/gic.h
arch/arm/include/asm/hardware/vic.h
arch/arm/include/asm/idmap.h [new file with mode: 0644]
arch/arm/include/asm/mach/arch.h
arch/arm/include/asm/page.h
arch/arm/include/asm/perf_event.h
arch/arm/include/asm/pgalloc.h
arch/arm/include/asm/pgtable-2level.h
arch/arm/include/asm/pgtable-3level-hwdef.h [new file with mode: 0644]
arch/arm/include/asm/pgtable-3level-types.h [new file with mode: 0644]
arch/arm/include/asm/pgtable-3level.h [new file with mode: 0644]
arch/arm/include/asm/pgtable-hwdef.h
arch/arm/include/asm/pgtable.h
arch/arm/include/asm/pmu.h
arch/arm/include/asm/proc-fns.h
arch/arm/include/asm/system.h
arch/arm/include/asm/tlb.h
arch/arm/kernel/entry-armv.S
arch/arm/kernel/head.S
arch/arm/kernel/hw_breakpoint.c
arch/arm/kernel/machine_kexec.c
arch/arm/kernel/perf_event.c
arch/arm/kernel/perf_event_v6.c
arch/arm/kernel/perf_event_v7.c
arch/arm/kernel/perf_event_xscale.c
arch/arm/kernel/process.c
arch/arm/kernel/setup.c
arch/arm/kernel/sleep.S
arch/arm/kernel/smp.c
arch/arm/kernel/suspend.c
arch/arm/kernel/vmlinux.lds.S
arch/arm/lib/Makefile
arch/arm/lib/call_with_stack.S [new file with mode: 0644]
arch/arm/mach-at91/at91rm9200_devices.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9260_devices.c
arch/arm/mach-at91/at91sam9261_devices.c
arch/arm/mach-at91/at91sam9263_devices.c
arch/arm/mach-at91/include/mach/io.h
arch/arm/mach-at91/include/mach/system_rev.h
arch/arm/mach-at91/include/mach/vmalloc.h [deleted file]
arch/arm/mach-at91/setup.c
arch/arm/mach-bcmring/dma.c
arch/arm/mach-bcmring/include/mach/vmalloc.h [deleted file]
arch/arm/mach-clps711x/Makefile
arch/arm/mach-clps711x/common.c [new file with mode: 0644]
arch/arm/mach-clps711x/include/mach/system.h
arch/arm/mach-clps711x/include/mach/vmalloc.h [deleted file]
arch/arm/mach-clps711x/irq.c [deleted file]
arch/arm/mach-clps711x/mm.c [deleted file]
arch/arm/mach-clps711x/time.c [deleted file]
arch/arm/mach-cns3xxx/cns3420vb.c
arch/arm/mach-cns3xxx/include/mach/entry-macro.S
arch/arm/mach-cns3xxx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-davinci/Makefile
arch/arm/mach-davinci/board-da850-evm.c
arch/arm/mach-davinci/board-dm365-evm.c
arch/arm/mach-davinci/board-dm646x-evm.c
arch/arm/mach-davinci/clock.c
arch/arm/mach-davinci/clock.h
arch/arm/mach-davinci/dm644x.c
arch/arm/mach-davinci/dm646x.c
arch/arm/mach-davinci/include/mach/io.h
arch/arm/mach-davinci/include/mach/psc.h
arch/arm/mach-davinci/include/mach/vmalloc.h [deleted file]
arch/arm/mach-davinci/io.c [deleted file]
arch/arm/mach-davinci/psc.c
arch/arm/mach-dove/addr-map.c
arch/arm/mach-dove/common.c
arch/arm/mach-dove/common.h
arch/arm/mach-dove/include/mach/dove.h
arch/arm/mach-dove/include/mach/vmalloc.h [deleted file]
arch/arm/mach-dove/pcie.c
arch/arm/mach-ebsa110/core.c
arch/arm/mach-ebsa110/include/mach/system.h
arch/arm/mach-ebsa110/include/mach/vmalloc.h [deleted file]
arch/arm/mach-ep93xx/adssphere.c
arch/arm/mach-ep93xx/edb93xx.c
arch/arm/mach-ep93xx/gesbc9312.c
arch/arm/mach-ep93xx/include/mach/entry-macro.S
arch/arm/mach-ep93xx/include/mach/system.h
arch/arm/mach-ep93xx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-ep93xx/micro9.c
arch/arm/mach-ep93xx/simone.c
arch/arm/mach-ep93xx/snappercl15.c
arch/arm/mach-ep93xx/ts72xx.c
arch/arm/mach-exynos/cpu.c
arch/arm/mach-exynos/include/mach/entry-macro.S
arch/arm/mach-exynos/include/mach/vmalloc.h [deleted file]
arch/arm/mach-exynos/mach-armlex4210.c
arch/arm/mach-exynos/mach-nuri.c
arch/arm/mach-exynos/mach-origen.c
arch/arm/mach-exynos/mach-smdk4x12.c
arch/arm/mach-exynos/mach-smdkv310.c
arch/arm/mach-exynos/mach-universal_c210.c
arch/arm/mach-exynos/platsmp.c
arch/arm/mach-footbridge/cats-hw.c
arch/arm/mach-footbridge/include/mach/system.h
arch/arm/mach-footbridge/include/mach/vmalloc.h [deleted file]
arch/arm/mach-gemini/include/mach/vmalloc.h [deleted file]
arch/arm/mach-h720x/include/mach/vmalloc.h [deleted file]
arch/arm/mach-highbank/highbank.c
arch/arm/mach-highbank/include/mach/entry-macro.S
arch/arm/mach-highbank/include/mach/vmalloc.h [deleted file]
arch/arm/mach-imx/mach-imx6q.c
arch/arm/mach-integrator/include/mach/vmalloc.h [deleted file]
arch/arm/mach-iop13xx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-iop32x/include/mach/io.h
arch/arm/mach-iop32x/include/mach/system.h
arch/arm/mach-iop32x/include/mach/vmalloc.h [deleted file]
arch/arm/mach-iop33x/include/mach/io.h
arch/arm/mach-iop33x/include/mach/system.h
arch/arm/mach-iop33x/include/mach/vmalloc.h [deleted file]
arch/arm/mach-ixp2000/include/mach/system.h
arch/arm/mach-ixp2000/include/mach/vmalloc.h [deleted file]
arch/arm/mach-ixp23xx/include/mach/io.h
arch/arm/mach-ixp23xx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-ixp4xx/include/mach/system.h
arch/arm/mach-ixp4xx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-kirkwood/addr-map.c
arch/arm/mach-kirkwood/common.c
arch/arm/mach-kirkwood/common.h
arch/arm/mach-kirkwood/include/mach/io.h
arch/arm/mach-kirkwood/include/mach/kirkwood.h
arch/arm/mach-kirkwood/include/mach/vmalloc.h [deleted file]
arch/arm/mach-kirkwood/mpp.c
arch/arm/mach-kirkwood/mpp.h
arch/arm/mach-kirkwood/pcie.c
arch/arm/mach-ks8695/include/mach/system.h
arch/arm/mach-ks8695/include/mach/vmalloc.h [deleted file]
arch/arm/mach-lpc32xx/include/mach/system.h
arch/arm/mach-lpc32xx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-mmp/include/mach/system.h
arch/arm/mach-mmp/include/mach/vmalloc.h [deleted file]
arch/arm/mach-msm/board-msm8960.c
arch/arm/mach-msm/board-msm8x60.c
arch/arm/mach-msm/devices-iommu.c
arch/arm/mach-msm/include/mach/entry-macro-qgic.S [deleted file]
arch/arm/mach-msm/include/mach/entry-macro-vic.S [deleted file]
arch/arm/mach-msm/include/mach/entry-macro.S
arch/arm/mach-msm/include/mach/vmalloc.h [deleted file]
arch/arm/mach-mv78xx0/addr-map.c
arch/arm/mach-mv78xx0/common.c
arch/arm/mach-mv78xx0/common.h
arch/arm/mach-mv78xx0/include/mach/vmalloc.h [deleted file]
arch/arm/mach-mv78xx0/mpp.c
arch/arm/mach-mv78xx0/pcie.c
arch/arm/mach-mx5/imx51-dt.c
arch/arm/mach-mx5/imx53-dt.c
arch/arm/mach-mxs/include/mach/mx28.h
arch/arm/mach-mxs/include/mach/mxs.h
arch/arm/mach-mxs/include/mach/vmalloc.h [deleted file]
arch/arm/mach-mxs/mach-m28evk.c
arch/arm/mach-mxs/mach-stmp378x_devb.c
arch/arm/mach-mxs/module-tx28.c
arch/arm/mach-mxs/system.c
arch/arm/mach-netx/include/mach/entry-macro.S
arch/arm/mach-netx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-netx/nxdb500.c
arch/arm/mach-netx/nxdkn.c
arch/arm/mach-netx/nxeb500hmi.c
arch/arm/mach-nomadik/board-nhk8815.c
arch/arm/mach-nomadik/include/mach/entry-macro.S
arch/arm/mach-nomadik/include/mach/vmalloc.h [deleted file]
arch/arm/mach-omap1/Kconfig
arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-fsample.c
arch/arm/mach-omap1/board-generic.c
arch/arm/mach-omap1/board-h2.c
arch/arm/mach-omap1/board-h3.c
arch/arm/mach-omap1/board-htcherald.c
arch/arm/mach-omap1/board-innovator.c
arch/arm/mach-omap1/board-nokia770.c
arch/arm/mach-omap1/board-osk.c
arch/arm/mach-omap1/board-palmte.c
arch/arm/mach-omap1/board-palmtt.c
arch/arm/mach-omap1/board-palmz71.c
arch/arm/mach-omap1/board-perseus2.c
arch/arm/mach-omap1/board-sx1.c
arch/arm/mach-omap1/board-voiceblue.c
arch/arm/mach-omap1/clock.c
arch/arm/mach-omap1/clock.h
arch/arm/mach-omap1/clock_data.c
arch/arm/mach-omap1/common.h [new file with mode: 0644]
arch/arm/mach-omap1/devices.c
arch/arm/mach-omap1/include/mach/vmalloc.h [deleted file]
arch/arm/mach-omap1/io.c
arch/arm/mach-omap1/opp.h
arch/arm/mach-omap1/opp_data.c
arch/arm/mach-omap1/time.c
arch/arm/mach-omap1/timer32k.c
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/board-2430sdp.c
arch/arm/mach-omap2/board-3430sdp.c
arch/arm/mach-omap2/board-3630sdp.c
arch/arm/mach-omap2/board-4430sdp.c
arch/arm/mach-omap2/board-am3517crane.c
arch/arm/mach-omap2/board-am3517evm.c
arch/arm/mach-omap2/board-apollon.c
arch/arm/mach-omap2/board-cm-t35.c
arch/arm/mach-omap2/board-cm-t3517.c
arch/arm/mach-omap2/board-devkit8000.c
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/board-h4.c
arch/arm/mach-omap2/board-igep0020.c
arch/arm/mach-omap2/board-ldp.c
arch/arm/mach-omap2/board-n8x0.c
arch/arm/mach-omap2/board-omap3beagle.c
arch/arm/mach-omap2/board-omap3evm.c
arch/arm/mach-omap2/board-omap3logic.c
arch/arm/mach-omap2/board-omap3pandora.c
arch/arm/mach-omap2/board-omap3stalker.c
arch/arm/mach-omap2/board-omap3touchbook.c
arch/arm/mach-omap2/board-omap4panda.c
arch/arm/mach-omap2/board-overo.c
arch/arm/mach-omap2/board-rm680.c
arch/arm/mach-omap2/board-rx51-peripherals.c
arch/arm/mach-omap2/board-rx51.c
arch/arm/mach-omap2/board-ti8168evm.c
arch/arm/mach-omap2/board-zoom-peripherals.c
arch/arm/mach-omap2/board-zoom.c
arch/arm/mach-omap2/cm2xxx_3xxx.c
arch/arm/mach-omap2/cm44xx.c
arch/arm/mach-omap2/cminst44xx.c
arch/arm/mach-omap2/common.c
arch/arm/mach-omap2/common.h [new file with mode: 0644]
arch/arm/mach-omap2/control.c
arch/arm/mach-omap2/cpuidle34xx.c
arch/arm/mach-omap2/display.c
arch/arm/mach-omap2/i2c.c
arch/arm/mach-omap2/id.c
arch/arm/mach-omap2/include/mach/entry-macro.S
arch/arm/mach-omap2/include/mach/omap4-common.h [deleted file]
arch/arm/mach-omap2/include/mach/vmalloc.h [deleted file]
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/irq.c
arch/arm/mach-omap2/omap-hotplug.c
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-omap2/omap4-common.c
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/pm.c
arch/arm/mach-omap2/pm24xx.c
arch/arm/mach-omap2/pm34xx.c
arch/arm/mach-omap2/pm44xx.c
arch/arm/mach-omap2/prcm.c
arch/arm/mach-omap2/prcm_mpu44xx.c
arch/arm/mach-omap2/prm2xxx_3xxx.c
arch/arm/mach-omap2/prm44xx.c
arch/arm/mach-omap2/prminst44xx.c
arch/arm/mach-omap2/sdram-nokia.c
arch/arm/mach-omap2/sdrc.c
arch/arm/mach-omap2/sdrc2xxx.c
arch/arm/mach-omap2/serial.c
arch/arm/mach-omap2/smartreflex.c
arch/arm/mach-omap2/timer.c
arch/arm/mach-omap2/vc3xxx_data.c
arch/arm/mach-omap2/vc44xx_data.c
arch/arm/mach-omap2/voltage.c
arch/arm/mach-omap2/voltagedomains3xxx_data.c
arch/arm/mach-omap2/voltagedomains44xx_data.c
arch/arm/mach-omap2/vp.c
arch/arm/mach-omap2/vp3xxx_data.c
arch/arm/mach-omap2/vp44xx_data.c
arch/arm/mach-orion5x/addr-map.c
arch/arm/mach-orion5x/common.c
arch/arm/mach-orion5x/common.h
arch/arm/mach-orion5x/include/mach/io.h
arch/arm/mach-orion5x/include/mach/orion5x.h
arch/arm/mach-orion5x/include/mach/vmalloc.h [deleted file]
arch/arm/mach-orion5x/mpp.c
arch/arm/mach-orion5x/pci.c
arch/arm/mach-picoxcell/Makefile
arch/arm/mach-picoxcell/common.c
arch/arm/mach-picoxcell/common.h
arch/arm/mach-picoxcell/include/mach/entry-macro.S
arch/arm/mach-picoxcell/include/mach/irqs.h
arch/arm/mach-picoxcell/include/mach/memory.h [deleted file]
arch/arm/mach-picoxcell/include/mach/vmalloc.h [deleted file]
arch/arm/mach-picoxcell/io.c [deleted file]
arch/arm/mach-pnx4008/include/mach/system.h
arch/arm/mach-pnx4008/include/mach/vmalloc.h [deleted file]
arch/arm/mach-prima2/include/mach/map.h
arch/arm/mach-prima2/include/mach/vmalloc.h [deleted file]
arch/arm/mach-prima2/pm.c
arch/arm/mach-prima2/prima2.c
arch/arm/mach-pxa/include/mach/entry-macro.S
arch/arm/mach-pxa/include/mach/vmalloc.h [deleted file]
arch/arm/mach-pxa/mioa701.c
arch/arm/mach-pxa/poodle.c
arch/arm/mach-pxa/reset.c
arch/arm/mach-pxa/spitz.c
arch/arm/mach-pxa/tosa.c
arch/arm/mach-realview/include/mach/entry-macro.S
arch/arm/mach-realview/include/mach/vmalloc.h [deleted file]
arch/arm/mach-realview/realview_eb.c
arch/arm/mach-realview/realview_pb1176.c
arch/arm/mach-realview/realview_pb11mp.c
arch/arm/mach-realview/realview_pba8.c
arch/arm/mach-realview/realview_pbx.c
arch/arm/mach-rpc/include/mach/system.h
arch/arm/mach-rpc/include/mach/vmalloc.h [deleted file]
arch/arm/mach-s3c2410/include/mach/system-reset.h
arch/arm/mach-s3c2410/include/mach/vmalloc.h [deleted file]
arch/arm/mach-s3c64xx/dev-spi.c
arch/arm/mach-s3c64xx/include/mach/entry-macro.S
arch/arm/mach-s3c64xx/include/mach/system.h
arch/arm/mach-s3c64xx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-s3c64xx/mach-anw6410.c
arch/arm/mach-s3c64xx/mach-crag6410.c
arch/arm/mach-s3c64xx/mach-hmt.c
arch/arm/mach-s3c64xx/mach-mini6410.c
arch/arm/mach-s3c64xx/mach-ncp.c
arch/arm/mach-s3c64xx/mach-real6410.c
arch/arm/mach-s3c64xx/mach-smartq5.c
arch/arm/mach-s3c64xx/mach-smartq7.c
arch/arm/mach-s3c64xx/mach-smdk6400.c
arch/arm/mach-s3c64xx/mach-smdk6410.c
arch/arm/mach-s3c64xx/s3c6400.c
arch/arm/mach-s3c64xx/setup-fb-24bpp.c
arch/arm/mach-s5p64x0/include/mach/entry-macro.S
arch/arm/mach-s5p64x0/include/mach/vmalloc.h [deleted file]
arch/arm/mach-s5p64x0/mach-smdk6440.c
arch/arm/mach-s5p64x0/mach-smdk6450.c
arch/arm/mach-s5pc100/include/mach/entry-macro.S
arch/arm/mach-s5pc100/include/mach/vmalloc.h [deleted file]
arch/arm/mach-s5pc100/mach-smdkc100.c
arch/arm/mach-s5pv210/include/mach/entry-macro.S
arch/arm/mach-s5pv210/include/mach/vmalloc.h [deleted file]
arch/arm/mach-s5pv210/mach-aquila.c
arch/arm/mach-s5pv210/mach-goni.c
arch/arm/mach-s5pv210/mach-smdkc110.c
arch/arm/mach-s5pv210/mach-smdkv210.c
arch/arm/mach-s5pv210/mach-torbreck.c
arch/arm/mach-sa1100/Makefile.boot
arch/arm/mach-sa1100/include/mach/system.h
arch/arm/mach-sa1100/include/mach/vmalloc.h [deleted file]
arch/arm/mach-shark/core.c
arch/arm/mach-shark/include/mach/vmalloc.h [deleted file]
arch/arm/mach-shmobile/Makefile
arch/arm/mach-shmobile/board-ag5evm.c
arch/arm/mach-shmobile/board-kota2.c
arch/arm/mach-shmobile/entry-gic.S [deleted file]
arch/arm/mach-shmobile/include/mach/common.h
arch/arm/mach-shmobile/include/mach/entry-macro.S
arch/arm/mach-shmobile/include/mach/system.h
arch/arm/mach-shmobile/include/mach/vmalloc.h [deleted file]
arch/arm/mach-spear3xx/include/mach/entry-macro.S
arch/arm/mach-spear3xx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-spear3xx/spear300_evb.c
arch/arm/mach-spear3xx/spear310_evb.c
arch/arm/mach-spear3xx/spear320_evb.c
arch/arm/mach-spear6xx/include/mach/entry-macro.S
arch/arm/mach-spear6xx/include/mach/vmalloc.h [deleted file]
arch/arm/mach-spear6xx/spear600_evb.c
arch/arm/mach-tegra/board-dt.c
arch/arm/mach-tegra/board-harmony.c
arch/arm/mach-tegra/board-paz00.c
arch/arm/mach-tegra/board-seaboard.c
arch/arm/mach-tegra/board-trimslice.c
arch/arm/mach-tegra/include/mach/entry-macro.S
arch/arm/mach-tegra/include/mach/io.h
arch/arm/mach-tegra/include/mach/vmalloc.h [deleted file]
arch/arm/mach-tegra/io.c
arch/arm/mach-u300/include/mach/entry-macro.S
arch/arm/mach-u300/include/mach/system.h
arch/arm/mach-u300/include/mach/vmalloc.h [deleted file]
arch/arm/mach-u300/u300.c
arch/arm/mach-ux500/board-mop500.c
arch/arm/mach-ux500/board-u5500.c
arch/arm/mach-ux500/include/mach/entry-macro.S
arch/arm/mach-ux500/include/mach/vmalloc.h [deleted file]
arch/arm/mach-versatile/core.c
arch/arm/mach-versatile/include/mach/entry-macro.S
arch/arm/mach-versatile/include/mach/vmalloc.h [deleted file]
arch/arm/mach-versatile/versatile_ab.c
arch/arm/mach-versatile/versatile_dt.c
arch/arm/mach-versatile/versatile_pb.c
arch/arm/mach-vexpress/include/mach/entry-macro.S
arch/arm/mach-vexpress/include/mach/vmalloc.h [deleted file]
arch/arm/mach-vexpress/v2m.c
arch/arm/mach-vt8500/include/mach/vmalloc.h [deleted file]
arch/arm/mach-w90x900/include/mach/system.h
arch/arm/mach-w90x900/include/mach/vmalloc.h [deleted file]
arch/arm/mach-w90x900/irq.c
arch/arm/mach-w90x900/nuc910.h
arch/arm/mach-w90x900/nuc950.h
arch/arm/mach-w90x900/nuc960.h
arch/arm/mach-w90x900/nuc9xx.h [new file with mode: 0644]
arch/arm/mach-w90x900/time.c
arch/arm/mach-zynq/common.c
arch/arm/mach-zynq/include/mach/entry-macro.S
arch/arm/mach-zynq/include/mach/vmalloc.h [deleted file]
arch/arm/mm/Kconfig
arch/arm/mm/alignment.c
arch/arm/mm/context.c
arch/arm/mm/fault.c
arch/arm/mm/fault.h
arch/arm/mm/fsr-2level.c [new file with mode: 0644]
arch/arm/mm/fsr-3level.c [new file with mode: 0644]
arch/arm/mm/idmap.c
arch/arm/mm/init.c
arch/arm/mm/ioremap.c
arch/arm/mm/mm.h
arch/arm/mm/mmu.c
arch/arm/mm/nommu.c
arch/arm/mm/pgd.c
arch/arm/mm/proc-arm1020.S
arch/arm/mm/proc-arm1020e.S
arch/arm/mm/proc-arm1022.S
arch/arm/mm/proc-arm1026.S
arch/arm/mm/proc-arm6_7.S
arch/arm/mm/proc-arm720.S
arch/arm/mm/proc-arm740.S
arch/arm/mm/proc-arm7tdmi.S
arch/arm/mm/proc-arm920.S
arch/arm/mm/proc-arm922.S
arch/arm/mm/proc-arm925.S
arch/arm/mm/proc-arm926.S
arch/arm/mm/proc-arm940.S
arch/arm/mm/proc-arm946.S
arch/arm/mm/proc-arm9tdmi.S
arch/arm/mm/proc-fa526.S
arch/arm/mm/proc-feroceon.S
arch/arm/mm/proc-macros.S
arch/arm/mm/proc-mohawk.S
arch/arm/mm/proc-sa110.S
arch/arm/mm/proc-sa1100.S
arch/arm/mm/proc-v6.S
arch/arm/mm/proc-v7-2level.S [new file with mode: 0644]
arch/arm/mm/proc-v7-3level.S [new file with mode: 0644]
arch/arm/mm/proc-v7.S
arch/arm/mm/proc-xsc3.S
arch/arm/mm/proc-xscale.S
arch/arm/plat-iop/Makefile
arch/arm/plat-iop/io.c [deleted file]
arch/arm/plat-mxc/Makefile
arch/arm/plat-mxc/gic.c [deleted file]
arch/arm/plat-mxc/include/mach/common.h
arch/arm/plat-mxc/include/mach/entry-macro.S
arch/arm/plat-mxc/include/mach/mx1.h
arch/arm/plat-mxc/include/mach/vmalloc.h [deleted file]
arch/arm/plat-mxc/system.c
arch/arm/plat-omap/Makefile
arch/arm/plat-omap/common.c
arch/arm/plat-omap/include/plat/clkdev_omap.h
arch/arm/plat-omap/include/plat/common.h
arch/arm/plat-omap/include/plat/io.h
arch/arm/plat-omap/include/plat/irqs.h
arch/arm/plat-omap/io.c [deleted file]
arch/arm/plat-omap/sram.c
arch/arm/plat-orion/Makefile
arch/arm/plat-orion/addr-map.c [new file with mode: 0644]
arch/arm/plat-orion/common.c
arch/arm/plat-orion/include/plat/addr-map.h [new file with mode: 0644]
arch/arm/plat-orion/include/plat/audio.h
arch/arm/plat-orion/include/plat/common.h
arch/arm/plat-orion/include/plat/ehci-orion.h
arch/arm/plat-orion/include/plat/mv_xor.h
arch/arm/plat-orion/include/plat/mvsdio.h
arch/arm/plat-orion/include/plat/pcie.h
arch/arm/plat-orion/pcie.c
arch/arm/plat-s5p/Kconfig
arch/arm/plat-spear/include/plat/system.h
arch/arm/plat-spear/include/plat/vmalloc.h [deleted file]
arch/arm/plat-tcc/include/mach/vmalloc.h [deleted file]
arch/m68k/include/asm/unistd.h
arch/m68k/kernel/syscalltable.S
arch/mips/kernel/perf_event_mipsxx.c
arch/s390/include/asm/pgtable.h
arch/s390/kernel/ptrace.c
arch/s390/kernel/setup.c
arch/s390/kernel/signal.c
arch/tile/include/asm/irq.h
arch/tile/kernel/irq.c
arch/tile/kernel/pci-dma.c
arch/tile/kernel/pci.c
arch/tile/kernel/sysfs.c
arch/tile/lib/exports.c
arch/tile/mm/homecache.c
arch/x86/Kconfig
arch/x86/include/asm/e820.h
arch/x86/include/asm/efi.h
arch/x86/include/asm/intel_scu_ipc.h
arch/x86/include/asm/mrst.h
arch/x86/include/asm/msr.h
arch/x86/include/asm/system.h
arch/x86/include/asm/timer.h
arch/x86/include/asm/uv/uv_mmrs.h
arch/x86/kernel/apic/x2apic_uv_x.c
arch/x86/kernel/cpu/amd.c
arch/x86/kernel/cpu/mtrr/generic.c
arch/x86/kernel/cpu/perf_event.c
arch/x86/kernel/cpu/perf_event_amd_ibs.c
arch/x86/kernel/cpu/perf_event_intel.c
arch/x86/kernel/cpu/perf_event_intel_ds.c
arch/x86/kernel/cpu/perf_event_p4.c
arch/x86/kernel/e820.c
arch/x86/kernel/hpet.c
arch/x86/kernel/irq_64.c
arch/x86/kernel/microcode_core.c
arch/x86/kernel/mpparse.c
arch/x86/kernel/process.c
arch/x86/kernel/quirks.c
arch/x86/kernel/reboot.c
arch/x86/kernel/rtc.c
arch/x86/kernel/setup.c
arch/x86/mm/gup.c
arch/x86/mm/highmem_32.c
arch/x86/oprofile/init.c
arch/x86/platform/efi/efi.c
arch/x86/platform/efi/efi_64.c
arch/x86/platform/mrst/mrst.c
arch/x86/xen/setup.c
drivers/ata/sata_mv.c
drivers/base/core.c
drivers/dma/mv_xor.c
drivers/firmware/sigma.c
drivers/gpio/Makefile
drivers/gpu/drm/drm_crtc_helper.c
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/nouveau/nouveau_display.c
drivers/gpu/drm/nouveau/nouveau_drv.c
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_object.c
drivers/gpu/drm/nouveau/nouveau_sgdma.c
drivers/gpu/drm/nouveau/nv50_display.c
drivers/gpu/drm/nouveau/nvc0_graph.c
drivers/gpu/drm/nouveau/nvd0_display.c
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/evergreen_cs.c
drivers/gpu/drm/radeon/evergreen_reg.h
drivers/gpu/drm/radeon/evergreend.h
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/radeon_acpi.c
drivers/gpu/drm/radeon/radeon_encoders.c
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
drivers/hid/hid-core.c
drivers/hid/hid-ids.h
drivers/iommu/intel-iommu.c
drivers/iommu/intr_remapping.c
drivers/isdn/divert/divert_procfs.c
drivers/isdn/i4l/isdn_net.c
drivers/md/bitmap.c
drivers/md/md.c
drivers/md/raid5.c
drivers/mmc/host/mvsdio.c
drivers/net/arcnet/Kconfig
drivers/net/bonding/bond_main.c
drivers/net/can/sja1000/peak_pci.c
drivers/net/ethernet/broadcom/b44.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
drivers/net/ethernet/davicom/dm9000.c
drivers/net/ethernet/freescale/Kconfig
drivers/net/ethernet/ibm/ehea/ehea.h
drivers/net/ethernet/ibm/ehea/ehea_main.c
drivers/net/ethernet/ibm/iseries_veth.c
drivers/net/ethernet/jme.c
drivers/net/ethernet/jme.h
drivers/net/ethernet/marvell/mv643xx_eth.c
drivers/net/ethernet/pasemi/Makefile
drivers/net/ethernet/qlogic/qlge/qlge.h
drivers/net/ethernet/realtek/r8169.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
drivers/net/ethernet/tile/tilepro.c
drivers/net/phy/Kconfig
drivers/net/wireless/iwlwifi/iwl-1000.c
drivers/net/wireless/iwlwifi/iwl-5000.c
drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
drivers/net/wireless/iwlwifi/iwl-agn-sta.c
drivers/net/wireless/iwlwifi/iwl-agn.c
drivers/net/wireless/iwlwifi/iwl-agn.h
drivers/net/wireless/iwlwifi/iwl-core.c
drivers/net/wireless/iwlwifi/iwl-core.h
drivers/net/wireless/iwlwifi/iwl-shared.h
drivers/net/wireless/p54/p54spi.c
drivers/net/wireless/prism54/isl_ioctl.c
drivers/net/wireless/rt2x00/rt2800lib.c
drivers/net/wireless/rtlwifi/ps.c
drivers/net/xen-netback/netback.c
drivers/of/irq.c
drivers/oprofile/oprof.c
drivers/oprofile/timer_int.c
drivers/platform/x86/toshiba_acpi.c
drivers/power/intel_mid_battery.c
drivers/ptp/ptp_clock.c
drivers/rapidio/devices/tsi721.c
drivers/rapidio/devices/tsi721.h
drivers/rtc/class.c
drivers/rtc/interface.c
drivers/rtc/rtc-s3c.c
drivers/s390/cio/chsc.c
drivers/s390/cio/cio.h
drivers/s390/cio/css.c
drivers/s390/cio/device.c
drivers/s390/cio/device_fsm.c
drivers/s390/cio/device_ops.c
drivers/s390/cio/io_sch.h
drivers/s390/crypto/ap_bus.c
drivers/spi/Kconfig
drivers/spi/spi-ath79.c
drivers/spi/spi-gpio.c
drivers/spi/spi-nuc900.c
drivers/staging/comedi/comedi_fops.c
drivers/staging/comedi/drivers/usbduxsigma.c
drivers/staging/rts_pstor/rtsx.c
drivers/staging/usbip/vhci_rx.c
drivers/target/iscsi/iscsi_target.c
drivers/target/iscsi/iscsi_target_auth.c
drivers/target/iscsi/iscsi_target_core.h
drivers/target/iscsi/iscsi_target_erl1.c
drivers/target/iscsi/iscsi_target_login.c
drivers/target/iscsi/iscsi_target_nego.c
drivers/target/loopback/tcm_loop.c
drivers/target/target_core_alua.c
drivers/target/target_core_cdb.c
drivers/target/target_core_configfs.c
drivers/target/target_core_device.c
drivers/target/target_core_file.c
drivers/target/target_core_iblock.c
drivers/target/target_core_pr.c
drivers/target/target_core_pscsi.c
drivers/target/target_core_rd.c
drivers/target/target_core_tmr.c
drivers/target/target_core_transport.c
drivers/target/tcm_fc/tfc_cmd.c
drivers/target/tcm_fc/tfc_conf.c
drivers/usb/gadget/amd5536udc.c
drivers/usb/gadget/f_serial.c
drivers/usb/gadget/fsl_mxc_udc.c
drivers/usb/gadget/fsl_qe_udc.c
drivers/usb/gadget/fsl_udc_core.c
drivers/usb/gadget/fsl_usb2_udc.h
drivers/usb/gadget/m66592-udc.c
drivers/usb/gadget/net2280.c
drivers/usb/gadget/r8a66597-udc.c
drivers/usb/gadget/s3c-hsotg.c
drivers/usb/gadget/s3c-hsudc.c
drivers/usb/host/ehci-orion.c
drivers/usb/host/ehci-sched.c
drivers/usb/host/whci/qset.c
drivers/usb/host/xhci.c
drivers/usb/musb/musb_core.c
drivers/usb/musb/musb_gadget.c
drivers/usb/renesas_usbhs/mod_gadget.c
drivers/usb/serial/ftdi_sio.c
drivers/usb/serial/ftdi_sio_ids.h
drivers/usb/serial/option.c
drivers/usb/storage/unusual_devs.h
fs/btrfs/extent-tree.c
fs/btrfs/extent_io.c
fs/btrfs/volumes.c
fs/cifs/connect.c
fs/cifs/file.c
fs/cifs/readdir.c
fs/cifs/smbencrypt.c
fs/dcache.c
fs/namespace.c
fs/proc/meminfo.c
fs/proc/stat.c
fs/seq_file.c
fs/xfs/xfs_acl.c
fs/xfs/xfs_attr_leaf.c
fs/xfs/xfs_bmap.c
fs/xfs/xfs_export.c
fs/xfs/xfs_inode.c
fs/xfs/xfs_inode.h
fs/xfs/xfs_log.c
fs/xfs/xfs_sync.c
fs/xfs/xfs_trace.h
include/asm-generic/unistd.h
include/drm/drm_pciids.h
include/linux/ata_platform.h
include/linux/compat.h
include/linux/dcache.h
include/linux/fs.h
include/linux/ftrace_event.h
include/linux/init_task.h
include/linux/mbus.h
include/linux/mm.h
include/linux/netdevice.h
include/linux/pci_ids.h
include/linux/perf_event.h
include/linux/pkt_sched.h
include/linux/shrinker.h
include/linux/sigma.h
include/linux/vmalloc.h
include/net/dst.h
include/net/dst_ops.h
include/net/inet_sock.h
include/net/inetpeer.h
include/net/netfilter/nf_conntrack_ecache.h
include/net/netns/conntrack.h
include/net/red.h
include/net/route.h
include/target/target_core_base.h
include/target/target_core_transport.h
kernel/events/core.c
kernel/events/internal.h
kernel/events/ring_buffer.c
kernel/irq/manage.c
kernel/jump_label.c
kernel/lockdep.c
kernel/printk.c
kernel/sched.c
kernel/sched_fair.c
kernel/sched_features.h
kernel/sched_rt.c
kernel/time/alarmtimer.c
kernel/time/clockevents.c
kernel/time/clocksource.c
kernel/time/tick-broadcast.c
kernel/timer.c
kernel/trace/ftrace.c
kernel/trace/trace_events.c
kernel/trace/trace_events_filter.c
lib/dma-debug.c
mm/huge_memory.c
mm/hugetlb.c
mm/migrate.c
mm/page_alloc.c
mm/slab.c
mm/vmalloc.c
mm/vmscan.c
net/bridge/br_netlink.c
net/bridge/br_stp.c
net/caif/cffrml.c
net/core/dev.c
net/core/dev_addr_lists.c
net/core/neighbour.c
net/core/request_sock.c
net/core/secure_seq.c
net/core/skbuff.c
net/dccp/ipv4.c
net/decnet/dn_route.c
net/decnet/dn_timer.c
net/ipv4/devinet.c
net/ipv4/igmp.c
net/ipv4/inet_diag.c
net/ipv4/ip_forward.c
net/ipv4/ip_options.c
net/ipv4/netfilter.c
net/ipv4/netfilter/Kconfig
net/ipv4/route.c
net/ipv4/udp.c
net/ipv6/inet6_connection_sock.c
net/ipv6/ipv6_sockglue.c
net/ipv6/ndisc.c
net/ipv6/netfilter/Kconfig
net/ipv6/route.c
net/ipv6/tcp_ipv6.c
net/ipv6/udp.c
net/l2tp/l2tp_core.c
net/mac80211/agg-tx.c
net/mac80211/debugfs_sta.c
net/mac80211/main.c
net/mac80211/status.c
net/mac80211/util.c
net/netfilter/Kconfig
net/netfilter/ipset/ip_set_hash_ipport.c
net/netfilter/ipset/ip_set_hash_ipportip.c
net/netfilter/ipset/ip_set_hash_ipportnet.c
net/netfilter/nf_conntrack_ecache.c
net/netfilter/nf_conntrack_netlink.c
net/netlabel/netlabel_kapi.c
net/sched/sch_red.c
net/sched/sch_teql.c
net/sctp/auth.c
net/unix/af_unix.c
net/wireless/nl80211.c
net/wireless/reg.c
net/xfrm/xfrm_policy.c
security/apparmor/path.c
security/tomoyo/realpath.c
sound/pci/hda/hda_intel.c
sound/pci/hda/patch_realtek.c
sound/pci/hda/patch_sigmatel.c
sound/pci/sis7019.c
sound/soc/atmel/Kconfig
sound/soc/atmel/Makefile
sound/soc/atmel/playpaq_wm8510.c [deleted file]
sound/soc/codecs/ad1836.h
sound/soc/codecs/cs4270.c
sound/soc/codecs/cs42l51.c
sound/soc/codecs/max9877.c
sound/soc/codecs/uda1380.c
sound/soc/codecs/wm8994.c
sound/soc/fsl/mpc8610_hpcd.c
sound/soc/imx/Kconfig
sound/soc/kirkwood/Kconfig
sound/soc/kirkwood/kirkwood-dma.c
sound/soc/pxa/Kconfig
sound/soc/samsung/smdk_wm8994.c
sound/soc/samsung/speyside.c
sound/soc/soc-core.c
sound/soc/soc-utils.c
sound/usb/quirks-table.h
tools/perf/builtin-stat.c
tools/perf/util/evsel.c
tools/perf/util/header.c
tools/perf/util/hist.c
tools/perf/util/hist.h
tools/perf/util/session.c
tools/perf/util/trace-event-parse.c

diff --git a/CREDITS b/CREDITS
index 07e32a87d956808fbb8b979fb38d434d93c879fc..44fce988eaac8cd22bfe5a5e753ae1bb58b3476d 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -688,10 +688,13 @@ S: Oxfordshire, UK.
 
 N: Kees Cook
 E: kees@outflux.net
-W: http://outflux.net/
-P: 1024D/17063E6D 9FA3 C49C 23C9 D1BC 2E30  1975 1FFF 4BA9 1706 3E6D
-D: Minor updates to SCSI types, added /proc/pid/maps protection
+E: kees@ubuntu.com
+E: keescook@chromium.org
+W: http://outflux.net/blog/
+P: 4096R/DC6DC026 A5C3 F68F 229D D60F 723E  6E13 8972 F4DF DC6D C026
+D: Various security things, bug fixes, and documentation.
 S: (ask for current address)
+S: Portland, Oregon
 S: USA
 
 N: Robin Cornelius
index 771d48d3b335a1419f1ec363d540c77ad6d75fbc..208a2d465b922ec826049243abc8c6ac2a724813 100644 (file)
@@ -51,15 +51,14 @@ ffc00000    ffefffff        DMA memory mapping region.  Memory returned
 ff000000       ffbfffff        Reserved for future expansion of DMA
                                mapping region.
 
-VMALLOC_END    feffffff        Free for platform use, recommended.
-                               VMALLOC_END must be aligned to a 2MB
-                               boundary.
-
 VMALLOC_START  VMALLOC_END-1   vmalloc() / ioremap() space.
                                Memory returned by vmalloc/ioremap will
                                be dynamically placed in this region.
-                               VMALLOC_START may be based upon the value
-                               of the high_memory variable.
+                               Machine specific static mappings are also
+                               located here through iotable_init().
+                               VMALLOC_START is based upon the value
+                               of the high_memory variable, and VMALLOC_END
+                               is equal to 0xff000000.
 
 PAGE_OFFSET    high_memory-1   Kernel direct-mapped RAM region.
                                This maps the platforms RAM, and typically
index 52916b4aa1fe9b70201b2fd44f3b91893c76600b..9b4b82a721b64b5cea6309b2d81ab09c0f4f47aa 100644 (file)
@@ -42,6 +42,10 @@ Optional
 - interrupts   : Interrupt source of the parent interrupt controller. Only
   present on secondary GICs.
 
+- cpu-offset   : per-cpu offset within the distributor and cpu interface
+  regions, used when the GIC doesn't have banked registers. The offset is
+  cpu-offset * cpu-nr.
+
 Example:
 
        intc: interrupt-controller@fff11000 {
diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
new file mode 100644 (file)
index 0000000..266716b
--- /dev/null
@@ -0,0 +1,29 @@
+* ARM Vectored Interrupt Controller
+
+One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
+system for interrupt routing.  For multiple controllers they can either be
+nested or have the outputs wire-OR'd together.
+
+Required properties:
+
+- compatible : should be one of
+       "arm,pl190-vic"
+       "arm,pl192-vic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : The number of cells to define the interrupts.  Must be 1 as
+  the VIC has no configuration options for interrupt sources.  The cell is a u32
+  and defines the interrupt number.
+- reg : The register bank for the VIC.
+
+Optional properties:
+
+- interrupts : Interrupt source for parent controllers if the VIC is nested.
+
+Example:
+
+       vic0: interrupt-controller@60000 {
+               compatible = "arm,pl192-vic";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               reg = <0x60000 0x1000>;
+       };
index a0c5c5f4fce6e9587346a4a049c9725e5ca45de5..81c287fad79d6370d0d697d5ddf33b8af756a036 100644 (file)
@@ -315,12 +315,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                        CPU-intensive style benchmark, and it can vary highly in
                        a microbenchmark depending on workload and compiler.
 
-                       1: only for 32-bit processes
-                       2: only for 64-bit processes
+                       32: only for 32-bit processes
+                       64: only for 64-bit processes
                        on: enable for both 32- and 64-bit processes
                        off: disable for both 32- and 64-bit processes
 
-       amd_iommu=      [HW,X86-84]
+       amd_iommu=      [HW,X86-64]
                        Pass parameters to the AMD IOMMU driver in the system.
                        Possible values are:
                        fullflush - enable flushing of IO/TLB entries when
index f049a1ca186fbf6eb5e55ed9eb3a65bb8601b1f8..589f2da5d5454dd96f828c01168aecb84770473f 100644 (file)
@@ -282,11 +282,11 @@ tcp_max_ssthresh - INTEGER
        Default: 0 (off)
 
 tcp_max_syn_backlog - INTEGER
-       Maximal number of remembered connection requests, which are
-       still did not receive an acknowledgment from connecting client.
-       Default value is 1024 for systems with more than 128Mb of memory,
-       and 128 for low memory machines. If server suffers of overload,
-       try to increase this number.
+       Maximal number of remembered connection requests, which have not
+       received an acknowledgment from connecting client.
+       The minimal value is 128 for low memory machines, and it will
+       increase in proportion to the memory of machine.
+       If server suffers from overload, try increasing this number.
 
 tcp_max_tw_buckets - INTEGER
        Maximal number of timewait sockets held by system simultaneously.
index 3e2ec9cbf3976d0d21c6ee90d7fe075a210a33eb..d50c14df34112ed2095942062bcaab90d90697bd 100644 (file)
@@ -50,8 +50,7 @@ Machine DAI Configuration
 The machine DAI configuration glues all the codec and CPU DAIs together. It can
 also be used to set up the DAI system clock and for any machine related DAI
 initialisation e.g. the machine audio map can be connected to the codec audio
-map, unconnected codec pins can be set as such. Please see corgi.c, spitz.c
-for examples.
+map, unconnected codec pins can be set as such.
 
 struct snd_soc_dai_link is used to set up each DAI in your machine. e.g.
 
@@ -83,8 +82,7 @@ Machine Power Map
 The machine driver can optionally extend the codec power map and to become an
 audio power map of the audio subsystem. This allows for automatic power up/down
 of speaker/HP amplifiers, etc. Codec pins can be connected to the machines jack
-sockets in the machine init function. See soc/pxa/spitz.c and dapm.txt for
-details.
+sockets in the machine init function.
 
 
 Machine Controls
index 37a02ce5484176670fde42a5bb915427316587f3..f0ffc27d4c0ac9d52efa62ecc0f775fd877b7387 100644 (file)
@@ -90,10 +90,10 @@ ServiceBinary=%12%\USBSER.sys
 [SourceDisksFiles]
 [SourceDisksNames]
 [DeviceList]
-%DESCRIPTION%=DriverInstall, USB\VID_0525&PID_A4A7, USB\VID_1D6B&PID_0104&MI_02
+%DESCRIPTION%=DriverInstall, USB\VID_0525&PID_A4A7, USB\VID_1D6B&PID_0104&MI_02, USB\VID_1D6B&PID_0106&MI_00
 
 [DeviceList.NTamd64]
-%DESCRIPTION%=DriverInstall, USB\VID_0525&PID_A4A7, USB\VID_1D6B&PID_0104&MI_02
+%DESCRIPTION%=DriverInstall, USB\VID_0525&PID_A4A7, USB\VID_1D6B&PID_0104&MI_02, USB\VID_1D6B&PID_0106&MI_00
 
 
 ;------------------------------------------------------------------------------
index 447560284996b3dfe8025180efdc87b1371906fd..796d67a584916f7ad484c330c5596bffd0911855 100644 (file)
@@ -511,8 +511,8 @@ M:  Joerg Roedel <joerg.roedel@amd.com>
 L:     iommu@lists.linux-foundation.org
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/joro/linux-2.6-iommu.git
 S:     Supported
-F:     arch/x86/kernel/amd_iommu*.c
-F:     arch/x86/include/asm/amd_iommu*.h
+F:     drivers/iommu/amd_iommu*.[ch]
+F:     include/linux/amd-iommu.h
 
 AMD MICROCODE UPDATE SUPPORT
 M:     Andreas Herrmann <andreas.herrmann3@amd.com>
@@ -1054,35 +1054,18 @@ ARM/SAMSUNG ARM ARCHITECTURES
 M:     Ben Dooks <ben-linux@fluff.org>
 M:     Kukjin Kim <kgene.kim@samsung.com>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:     linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
 W:     http://www.fluff.org/ben/linux/
 S:     Maintained
 F:     arch/arm/plat-samsung/
 F:     arch/arm/plat-s3c24xx/
 F:     arch/arm/plat-s5p/
+F:     arch/arm/mach-s3c24*/
+F:     arch/arm/mach-s3c64xx/
 F:     drivers/*/*s3c2410*
 F:     drivers/*/*/*s3c2410*
-
-ARM/S3C2410 ARM ARCHITECTURE
-M:     Ben Dooks <ben-linux@fluff.org>
-L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-W:     http://www.fluff.org/ben/linux/
-S:     Maintained
-F:     arch/arm/mach-s3c2410/
-
-ARM/S3C244x ARM ARCHITECTURE
-M:     Ben Dooks <ben-linux@fluff.org>
-L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-W:     http://www.fluff.org/ben/linux/
-S:     Maintained
-F:     arch/arm/mach-s3c2440/
-F:     arch/arm/mach-s3c2443/
-
-ARM/S3C64xx ARM ARCHITECTURE
-M:     Ben Dooks <ben-linux@fluff.org>
-L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-W:     http://www.fluff.org/ben/linux/
-S:     Maintained
-F:     arch/arm/mach-s3c64xx/
+F:     drivers/spi/spi-s3c*
+F:     sound/soc/samsung/*
 
 ARM/S5P EXYNOS ARM ARCHITECTURES
 M:     Kukjin Kim <kgene.kim@samsung.com>
@@ -4319,8 +4302,9 @@ F:        include/linux/mm.h
 F:     mm/
 
 MEMORY RESOURCE CONTROLLER
+M:     Johannes Weiner <hannes@cmpxchg.org>
+M:     Michal Hocko <mhocko@suse.cz>
 M:     Balbir Singh <bsingharora@gmail.com>
-M:     Daisuke Nishimura <nishimura@mxp.nes.nec.co.jp>
 M:     KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
 L:     cgroups@vger.kernel.org
 L:     linux-mm@kvack.org
@@ -5133,6 +5117,15 @@ L:       linux-mtd@lists.infradead.org
 S:     Maintained
 F:     drivers/mtd/devices/phram.c
 
+PICOXCELL SUPPORT
+M:     Jamie Iles <jamie@jamieiles.com>
+L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+T:     git git://github.com/jamieiles/linux-2.6-ji.git
+S:     Supported
+F:     arch/arm/mach-picoxcell
+F:     drivers/*/picoxcell*
+F:     drivers/*/*/picoxcell*
+
 PIN CONTROL SUBSYSTEM
 M:     Linus Walleij <linus.walleij@linaro.org>
 S:     Maintained
index 12aafc20efbd0d610430d3a88df4e6359093cfc1..d1ea73f74c2f42b2c4297fc6d45b75e38d561853 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 2
 SUBLEVEL = 0
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
 NAME = Saber-toothed Squirrel
 
 # *DOCUMENTATION*
index e084b7e981e8ff301aaae64ef3a2dc7e66701247..0d961cb7be9a096b4f8a64150117b78d39b8f06d 100644 (file)
@@ -650,6 +650,7 @@ config ARCH_PICOXCELL
        select HAVE_SCHED_CLOCK
        select HAVE_TCM
        select NO_IOPORT
+       select SPARSE_IRQ
        select USE_OF
        help
          This enables support for systems based on the Picochip picoXcell
@@ -1971,7 +1972,7 @@ endchoice
 
 config XIP_KERNEL
        bool "Kernel Execute-In-Place from ROM"
-       depends on !ZBOOT_ROM
+       depends on !ZBOOT_ROM && !ARM_LPAE
        help
          Execute-In-Place allows the kernel to run from non-volatile storage
          directly addressable by the CPU, such as NOR flash. This saves RAM
@@ -2001,7 +2002,7 @@ config XIP_PHYS_ADDR
 
 config KEXEC
        bool "Kexec system call (EXPERIMENTAL)"
-       depends on EXPERIMENTAL
+       depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
        help
          kexec is a system call that implements the ability to shutdown your
          current kernel, and to start another kernel.  It is like a reboot
index c2effc91725452dcaa93af7b3dc1b0ce20d979c2..c5d60250d43daf44205cd830de3ca6ed941ed348 100644 (file)
@@ -659,6 +659,7 @@ __armv7_mmu_cache_on:
                mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
 #endif
+               mcr     p15, 0, r0, c7, c5, 4   @ ISB
                mcr     p15, 0, r0, c1, c0, 0   @ load control register
                mrc     p15, 0, r0, c1, c0, 0   @ and read it back
                mov     r0, #0
index aeb1a7578fad49e70e767358d57e602220c6c7e6..305635bd45c01a91f178ee3e9d69ad3feea4644e 100644 (file)
                        reg = <0xfff3d000 0x1000>;
                        interrupts = <0 92 4>;
                };
+
+               ethernet@fff50000 {
+                       compatible = "calxeda,hb-xgmac";
+                       reg = <0xfff50000 0x1000>;
+                       interrupts = <0 77 4  0 78 4  0 79 4>;
+               };
+
+               ethernet@fff51000 {
+                       compatible = "calxeda,hb-xgmac";
+                       reg = <0xfff51000 0x1000>;
+                       interrupts = <0 80 4  0 81 4  0 82 4>;
+               };
        };
 };
index 74df9ca2be316e2df49f164df3ec680366a41a6b..81a933eb0903bf446c4722bd645aa2ec0573bf47 100644 (file)
@@ -1,8 +1,14 @@
 config ARM_GIC
        select IRQ_DOMAIN
+       select MULTI_IRQ_HANDLER
+       bool
+
+config GIC_NON_BANKED
        bool
 
 config ARM_VIC
+       select IRQ_DOMAIN
+       select MULTI_IRQ_HANDLER
        bool
 
 config ARM_VIC_NR
index 410a546060a2eecf82859d76c528223e8796f9f4..b2dc2dd7f1df6d25fbba306e0822563883b18859 100644 (file)
 #include <linux/slab.h>
 
 #include <asm/irq.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 
-static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+union gic_base {
+       void __iomem *common_base;
+       void __percpu __iomem **percpu_base;
+};
 
-/* Address of GIC 0 CPU interface */
-void __iomem *gic_cpu_base_addr __read_mostly;
+struct gic_chip_data {
+       unsigned int irq_offset;
+       union gic_base dist_base;
+       union gic_base cpu_base;
+#ifdef CONFIG_CPU_PM
+       u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+       u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
+       u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
+       u32 __percpu *saved_ppi_enable;
+       u32 __percpu *saved_ppi_conf;
+#endif
+#ifdef CONFIG_IRQ_DOMAIN
+       struct irq_domain domain;
+#endif
+       unsigned int gic_irqs;
+#ifdef CONFIG_GIC_NON_BANKED
+       void __iomem *(*get_base)(union gic_base *);
+#endif
+};
+
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 
 /*
  * Supported arch specific GIC irq extension.
@@ -67,16 +90,48 @@ struct irq_chip gic_arch_extn = {
 
 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
 
+#ifdef CONFIG_GIC_NON_BANKED
+static void __iomem *gic_get_percpu_base(union gic_base *base)
+{
+       return *__this_cpu_ptr(base->percpu_base);
+}
+
+static void __iomem *gic_get_common_base(union gic_base *base)
+{
+       return base->common_base;
+}
+
+static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
+{
+       return data->get_base(&data->dist_base);
+}
+
+static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
+{
+       return data->get_base(&data->cpu_base);
+}
+
+static inline void gic_set_base_accessor(struct gic_chip_data *data,
+                                        void __iomem *(*f)(union gic_base *))
+{
+       data->get_base = f;
+}
+#else
+#define gic_data_dist_base(d)  ((d)->dist_base.common_base)
+#define gic_data_cpu_base(d)   ((d)->cpu_base.common_base)
+#define gic_set_base_accessor(d,f)
+#endif
+
 static inline void __iomem *gic_dist_base(struct irq_data *d)
 {
        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-       return gic_data->dist_base;
+       return gic_data_dist_base(gic_data);
 }
 
 static inline void __iomem *gic_cpu_base(struct irq_data *d)
 {
        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-       return gic_data->cpu_base;
+       return gic_data_cpu_base(gic_data);
 }
 
 static inline unsigned int gic_irq(struct irq_data *d)
@@ -215,6 +270,32 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
 #define gic_set_wake   NULL
 #endif
 
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+       u32 irqstat, irqnr;
+       struct gic_chip_data *gic = &gic_data[0];
+       void __iomem *cpu_base = gic_data_cpu_base(gic);
+
+       do {
+               irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
+               irqnr = irqstat & ~0x1c00;
+
+               if (likely(irqnr > 15 && irqnr < 1021)) {
+                       irqnr = irq_domain_to_irq(&gic->domain, irqnr);
+                       handle_IRQ(irqnr, regs);
+                       continue;
+               }
+               if (irqnr < 16) {
+                       writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+                       handle_IPI(irqnr, regs);
+#endif
+                       continue;
+               }
+               break;
+       } while (1);
+}
+
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
        struct gic_chip_data *chip_data = irq_get_handler_data(irq);
@@ -225,7 +306,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
        chained_irq_enter(chip, desc);
 
        raw_spin_lock(&irq_controller_lock);
-       status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
+       status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
        raw_spin_unlock(&irq_controller_lock);
 
        gic_irq = (status & 0x3ff);
@@ -270,7 +351,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
        u32 cpumask;
        unsigned int gic_irqs = gic->gic_irqs;
        struct irq_domain *domain = &gic->domain;
-       void __iomem *base = gic->dist_base;
+       void __iomem *base = gic_data_dist_base(gic);
        u32 cpu = 0;
 
 #ifdef CONFIG_SMP
@@ -330,8 +411,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
 
 static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
 {
-       void __iomem *dist_base = gic->dist_base;
-       void __iomem *base = gic->cpu_base;
+       void __iomem *dist_base = gic_data_dist_base(gic);
+       void __iomem *base = gic_data_cpu_base(gic);
        int i;
 
        /*
@@ -368,7 +449,7 @@ static void gic_dist_save(unsigned int gic_nr)
                BUG();
 
        gic_irqs = gic_data[gic_nr].gic_irqs;
-       dist_base = gic_data[gic_nr].dist_base;
+       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
 
        if (!dist_base)
                return;
@@ -403,7 +484,7 @@ static void gic_dist_restore(unsigned int gic_nr)
                BUG();
 
        gic_irqs = gic_data[gic_nr].gic_irqs;
-       dist_base = gic_data[gic_nr].dist_base;
+       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
 
        if (!dist_base)
                return;
@@ -439,8 +520,8 @@ static void gic_cpu_save(unsigned int gic_nr)
        if (gic_nr >= MAX_GIC_NR)
                BUG();
 
-       dist_base = gic_data[gic_nr].dist_base;
-       cpu_base = gic_data[gic_nr].cpu_base;
+       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
+       cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
 
        if (!dist_base || !cpu_base)
                return;
@@ -465,8 +546,8 @@ static void gic_cpu_restore(unsigned int gic_nr)
        if (gic_nr >= MAX_GIC_NR)
                BUG();
 
-       dist_base = gic_data[gic_nr].dist_base;
-       cpu_base = gic_data[gic_nr].cpu_base;
+       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
+       cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
 
        if (!dist_base || !cpu_base)
                return;
@@ -491,6 +572,11 @@ static int gic_notifier(struct notifier_block *self, unsigned long cmd,    void *v)
        int i;
 
        for (i = 0; i < MAX_GIC_NR; i++) {
+#ifdef CONFIG_GIC_NON_BANKED
+               /* Skip over unused GICs */
+               if (!gic_data[i].get_base)
+                       continue;
+#endif
                switch (cmd) {
                case CPU_PM_ENTER:
                        gic_cpu_save(i);
@@ -564,8 +650,9 @@ const struct irq_domain_ops gic_irq_domain_ops = {
 #endif
 };
 
-void __init gic_init(unsigned int gic_nr, int irq_start,
-       void __iomem *dist_base, void __iomem *cpu_base)
+void __init gic_init_bases(unsigned int gic_nr, int irq_start,
+                          void __iomem *dist_base, void __iomem *cpu_base,
+                          u32 percpu_offset)
 {
        struct gic_chip_data *gic;
        struct irq_domain *domain;
@@ -575,8 +662,36 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
 
        gic = &gic_data[gic_nr];
        domain = &gic->domain;
-       gic->dist_base = dist_base;
-       gic->cpu_base = cpu_base;
+#ifdef CONFIG_GIC_NON_BANKED
+       if (percpu_offset) { /* Frankein-GIC without banked registers... */
+               unsigned int cpu;
+
+               gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
+               gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
+               if (WARN_ON(!gic->dist_base.percpu_base ||
+                           !gic->cpu_base.percpu_base)) {
+                       free_percpu(gic->dist_base.percpu_base);
+                       free_percpu(gic->cpu_base.percpu_base);
+                       return;
+               }
+
+               for_each_possible_cpu(cpu) {
+                       unsigned long offset = percpu_offset * cpu_logical_map(cpu);
+                       *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
+                       *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
+               }
+
+               gic_set_base_accessor(gic, gic_get_percpu_base);
+       } else
+#endif
+       {                       /* Normal, sane GIC... */
+               WARN(percpu_offset,
+                    "GIC_NON_BANKED not enabled, ignoring %08x offset!",
+                    percpu_offset);
+               gic->dist_base.common_base = dist_base;
+               gic->cpu_base.common_base = cpu_base;
+               gic_set_base_accessor(gic, gic_get_common_base);
+       }
 
        /*
         * For primary GICs, skip over SGIs.
@@ -584,8 +699,6 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
         */
        domain->hwirq_base = 32;
        if (gic_nr == 0) {
-               gic_cpu_base_addr = cpu_base;
-
                if ((irq_start & 31) > 0) {
                        domain->hwirq_base = 16;
                        if (irq_start != -1)
@@ -597,7 +710,7 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
         * Find out how many interrupts are supported.
         * The GIC only supports up to 1020 interrupt sources.
         */
-       gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
+       gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
        gic_irqs = (gic_irqs + 1) * 32;
        if (gic_irqs > 1020)
                gic_irqs = 1020;
@@ -645,7 +758,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
        dsb();
 
        /* this always happens on GIC0 */
-       writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
+       writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 }
 #endif
 
@@ -656,6 +769,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
 {
        void __iomem *cpu_base;
        void __iomem *dist_base;
+       u32 percpu_offset;
        int irq;
        struct irq_domain *domain = &gic_data[gic_cnt].domain;
 
@@ -668,9 +782,12 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
        cpu_base = of_iomap(node, 1);
        WARN(!cpu_base, "unable to map gic cpu registers\n");
 
+       if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
+               percpu_offset = 0;
+
        domain->of_node = of_node_get(node);
 
-       gic_init(gic_cnt, -1, dist_base, cpu_base);
+       gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
 
        if (parent) {
                irq = irq_of_parse_and_map(node, 0);
index 01f18a421b17c6e20c6b0bf07a10c75378accc02..77287504c8b40e31e3789d1e27dcc824003b2af6 100644 (file)
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/syscore_ops.h>
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
 
-#ifdef CONFIG_PM
 /**
  * struct vic_device - VIC PM device
  * @irq: The IRQ number for the base of the VIC.
@@ -40,6 +45,7 @@
  * @int_enable: Save for VIC_INT_ENABLE.
  * @soft_int: Save for VIC_INT_SOFT.
  * @protect: Save for VIC_PROTECT.
+ * @domain: The IRQ domain for the VIC.
  */
 struct vic_device {
        void __iomem    *base;
@@ -50,13 +56,13 @@ struct vic_device {
        u32             int_enable;
        u32             soft_int;
        u32             protect;
+       struct irq_domain domain;
 };
 
 /* we cannot allocate memory when VICs are initially registered */
 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
 
 static int vic_id;
-#endif /* CONFIG_PM */
 
 /**
  * vic_init2 - common initialisation code
@@ -156,39 +162,50 @@ static int __init vic_pm_init(void)
        return 0;
 }
 late_initcall(vic_pm_init);
+#endif /* CONFIG_PM */
 
 /**
- * vic_pm_register - Register a VIC for later power management control
+ * vic_register() - Register a VIC.
  * @base: The base address of the VIC.
  * @irq: The base IRQ for the VIC.
  * @resume_sources: bitmask of interrupts allowed for resume sources.
+ * @node: The device tree node associated with the VIC.
  *
  * Register the VIC with the system device tree so that it can be notified
  * of suspend and resume requests and ensure that the correct actions are
  * taken to re-instate the settings on resume.
+ *
+ * This also configures the IRQ domain for the VIC.
  */
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+static void __init vic_register(void __iomem *base, unsigned int irq,
+                               u32 resume_sources, struct device_node *node)
 {
        struct vic_device *v;
 
-       if (vic_id >= ARRAY_SIZE(vic_devices))
+       if (vic_id >= ARRAY_SIZE(vic_devices)) {
                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-       else {
-               v = &vic_devices[vic_id];
-               v->base = base;
-               v->resume_sources = resume_sources;
-               v->irq = irq;
-               vic_id++;
+               return;
        }
+
+       v = &vic_devices[vic_id];
+       v->base = base;
+       v->resume_sources = resume_sources;
+       v->irq = irq;
+       vic_id++;
+
+       v->domain.irq_base = irq;
+       v->domain.nr_irq = 32;
+#ifdef CONFIG_OF_IRQ
+       v->domain.of_node = of_node_get(node);
+       v->domain.ops = &irq_domain_simple_ops;
+#endif /* CONFIG_OF */
+       irq_domain_add(&v->domain);
 }
-#else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
-#endif /* CONFIG_PM */
 
 static void vic_ack_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-       unsigned int irq = d->irq & 31;
+       unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
        /* moreover, clear the soft-triggered, in case it was the reason */
        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
@@ -197,14 +214,14 @@ static void vic_ack_irq(struct irq_data *d)
 static void vic_mask_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-       unsigned int irq = d->irq & 31;
+       unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 }
 
 static void vic_unmask_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-       unsigned int irq = d->irq & 31;
+       unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE);
 }
 
@@ -226,7 +243,7 @@ static struct vic_device *vic_from_irq(unsigned int irq)
 static int vic_set_wake(struct irq_data *d, unsigned int on)
 {
        struct vic_device *v = vic_from_irq(d->irq);
-       unsigned int off = d->irq & 31;
+       unsigned int off = d->hwirq;
        u32 bit = 1 << off;
 
        if (!v)
@@ -301,7 +318,7 @@ static void __init vic_set_irq_sources(void __iomem *base,
  *  and 020 within the page. We call this "second block".
  */
 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
-                               u32 vic_sources)
+                              u32 vic_sources, struct device_node *node)
 {
        unsigned int i;
        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
@@ -328,17 +345,12 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
        }
 
        vic_set_irq_sources(base, irq_start, vic_sources);
+       vic_register(base, irq_start, 0, node);
 }
 
-/**
- * vic_init - initialise a vectored interrupt controller
- * @base: iomem base address
- * @irq_start: starting interrupt number, must be muliple of 32
- * @vic_sources: bitmask of interrupt sources to allow
- * @resume_sources: bitmask of interrupt sources to allow for resume
- */
-void __init vic_init(void __iomem *base, unsigned int irq_start,
-                    u32 vic_sources, u32 resume_sources)
+static void __init __vic_init(void __iomem *base, unsigned int irq_start,
+                             u32 vic_sources, u32 resume_sources,
+                             struct device_node *node)
 {
        unsigned int i;
        u32 cellid = 0;
@@ -356,7 +368,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
        switch(vendor) {
        case AMBA_VENDOR_ST:
-               vic_init_st(base, irq_start, vic_sources);
+               vic_init_st(base, irq_start, vic_sources, node);
                return;
        default:
                printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
@@ -375,5 +387,81 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
        vic_set_irq_sources(base, irq_start, vic_sources);
 
-       vic_pm_register(base, irq_start, resume_sources);
+       vic_register(base, irq_start, resume_sources, node);
+}
+
+/**
+ * vic_init() - initialise a vectored interrupt controller
+ * @base: iomem base address
+ * @irq_start: starting interrupt number, must be muliple of 32
+ * @vic_sources: bitmask of interrupt sources to allow
+ * @resume_sources: bitmask of interrupt sources to allow for resume
+ */
+void __init vic_init(void __iomem *base, unsigned int irq_start,
+                    u32 vic_sources, u32 resume_sources)
+{
+       __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
+}
+
+#ifdef CONFIG_OF
+int __init vic_of_init(struct device_node *node, struct device_node *parent)
+{
+       void __iomem *regs;
+       int irq_base;
+
+       if (WARN(parent, "non-root VICs are not supported"))
+               return -EINVAL;
+
+       regs = of_iomap(node, 0);
+       if (WARN_ON(!regs))
+               return -EIO;
+
+       irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
+       if (WARN_ON(irq_base < 0))
+               goto out_unmap;
+
+       __vic_init(regs, irq_base, ~0, ~0, node);
+
+       return 0;
+
+ out_unmap:
+       iounmap(regs);
+
+       return -EIO;
+}
+#endif /* CONFIG OF */
+
+/*
+ * Handle each interrupt in a single VIC.  Returns non-zero if we've
+ * handled at least one interrupt.  This does a single read of the
+ * status register and handles all interrupts in order from LSB first.
+ */
+static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
+{
+       u32 stat, irq;
+       int handled = 0;
+
+       stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
+       while (stat) {
+               irq = ffs(stat) - 1;
+               handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
+               stat &= ~(1 << irq);
+               handled = 1;
+       }
+
+       return handled;
+}
+
+/*
+ * Keep iterating over all registered VIC's until there are no pending
+ * interrupts.
+ */
+asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
+{
+       int i, handled;
+
+       do {
+               for (i = 0, handled = 0; i < vic_id; ++i)
+                       handled |= handle_one_vic(&vic_devices[i], regs);
+       } while (handled);
 }
index a7e77758137881bf52067b145ae220f0447b7fdc..dde2a1af7b39bd73cec54cf22417a9e53920f792 100644 (file)
@@ -48,12 +48,6 @@ CONFIG_MACH_SX1=y
 CONFIG_MACH_NOKIA770=y
 CONFIG_MACH_AMS_DELTA=y
 CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_216MHZ=y
-CONFIG_OMAP_ARM_195MHZ=y
-CONFIG_OMAP_ARM_192MHZ=y
-CONFIG_OMAP_ARM_182MHZ=y
-CONFIG_OMAP_ARM_168MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
 CONFIG_OMAP_CF=y
index 29035e86a59db0d4c46ab315a9350780dbfe2999..b6e65dedfd716db5e336451868af811e34a684dc 100644 (file)
 #define ALT_UP_B(label) b label
 #endif
 
+/*
+ * Instruction barrier
+ */
+       .macro  instr_sync
+#if __LINUX_ARM_ARCH__ >= 7
+       isb
+#elif __LINUX_ARM_ARCH__ == 6
+       mcr     p15, 0, r0, c7, c5, 4
+#endif
+       .endm
+
 /*
  * SMP data memory barrier
  */
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
new file mode 100644 (file)
index 0000000..a0ada3e
--- /dev/null
@@ -0,0 +1,179 @@
+#ifndef __ASMARM_CTI_H
+#define __ASMARM_CTI_H
+
+#include       <asm/io.h>
+
+/* The registers' definition is from section 3.2 of
+ * Embedded Cross Trigger Revision: r0p0
+ */
+#define                CTICONTROL              0x000
+#define                CTISTATUS               0x004
+#define                CTILOCK                 0x008
+#define                CTIPROTECTION           0x00C
+#define                CTIINTACK               0x010
+#define                CTIAPPSET               0x014
+#define                CTIAPPCLEAR             0x018
+#define                CTIAPPPULSE             0x01c
+#define                CTIINEN                 0x020
+#define                CTIOUTEN                0x0A0
+#define                CTITRIGINSTATUS         0x130
+#define                CTITRIGOUTSTATUS        0x134
+#define                CTICHINSTATUS           0x138
+#define                CTICHOUTSTATUS          0x13c
+#define                CTIPERIPHID0            0xFE0
+#define                CTIPERIPHID1            0xFE4
+#define                CTIPERIPHID2            0xFE8
+#define                CTIPERIPHID3            0xFEC
+#define                CTIPCELLID0             0xFF0
+#define                CTIPCELLID1             0xFF4
+#define                CTIPCELLID2             0xFF8
+#define                CTIPCELLID3             0xFFC
+
+/* The below are from section 3.6.4 of
+ * CoreSight v1.0 Architecture Specification
+ */
+#define                LOCKACCESS              0xFB0
+#define                LOCKSTATUS              0xFB4
+
+/* write this value to LOCKACCESS will unlock the module, and
+ * other value will lock the module
+ */
+#define                LOCKCODE                0xC5ACCE55
+
+/**
+ * struct cti - cross trigger interface struct
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out_for_irq: triger out number which will cause
+ *     the @irq happen
+ *
+ * cti struct used to operate cti registers.
+ */
+struct cti {
+       void __iomem *base;
+       int irq;
+       int trig_out_for_irq;
+};
+
+/**
+ * cti_init - initialize the cti instance
+ * @cti: cti instance
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out: triger out number which will cause
+ *     the @irq happen
+ *
+ * called by machine code to pass the board dependent
+ * @base, @irq and @trig_out to cti.
+ */
+static inline void cti_init(struct cti *cti,
+       void __iomem *base, int irq, int trig_out)
+{
+       cti->base = base;
+       cti->irq  = irq;
+       cti->trig_out_for_irq = trig_out;
+}
+
+/**
+ * cti_map_trigger - use the @chan to map @trig_in to @trig_out
+ * @cti: cti instance
+ * @trig_in: trigger in number
+ * @trig_out: trigger out number
+ * @channel: channel number
+ *
+ * This function maps one trigger in of @trig_in to one trigger
+ * out of @trig_out using the channel @chan.
+ */
+static inline void cti_map_trigger(struct cti *cti,
+       int trig_in, int trig_out, int chan)
+{
+       void __iomem *base = cti->base;
+       unsigned long val;
+
+       val = __raw_readl(base + CTIINEN + trig_in * 4);
+       val |= BIT(chan);
+       __raw_writel(val, base + CTIINEN + trig_in * 4);
+
+       val = __raw_readl(base + CTIOUTEN + trig_out * 4);
+       val |= BIT(chan);
+       __raw_writel(val, base + CTIOUTEN + trig_out * 4);
+}
+
+/**
+ * cti_enable - enable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_enable(struct cti *cti)
+{
+       __raw_writel(0x1, cti->base + CTICONTROL);
+}
+
+/**
+ * cti_disable - disable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_disable(struct cti *cti)
+{
+       __raw_writel(0, cti->base + CTICONTROL);
+}
+
+/**
+ * cti_irq_ack - clear the cti irq
+ * @cti: cti instance
+ *
+ * clear the cti irq
+ */
+static inline void cti_irq_ack(struct cti *cti)
+{
+       void __iomem *base = cti->base;
+       unsigned long val;
+
+       val = __raw_readl(base + CTIINTACK);
+       val |= BIT(cti->trig_out_for_irq);
+       __raw_writel(val, base + CTIINTACK);
+}
+
+/**
+ * cti_unlock - unlock cti module
+ * @cti: cti instance
+ *
+ * unlock the cti module, or else any writes to the cti
+ * module is not allowed.
+ */
+static inline void cti_unlock(struct cti *cti)
+{
+       void __iomem *base = cti->base;
+       unsigned long val;
+
+       val = __raw_readl(base + LOCKSTATUS);
+
+       if (val & 1) {
+               val = LOCKCODE;
+               __raw_writel(val, base + LOCKACCESS);
+       }
+}
+
+/**
+ * cti_lock - lock cti module
+ * @cti: cti instance
+ *
+ * lock the cti module, so any writes to the cti
+ * module will be not allowed.
+ */
+static inline void cti_lock(struct cti *cti)
+{
+       void __iomem *base = cti->base;
+       unsigned long val;
+
+       val = __raw_readl(base + LOCKSTATUS);
+
+       if (!(val & 1)) {
+               val = ~LOCKCODE;
+               __raw_writel(val, base + LOCKACCESS);
+       }
+}
+#endif
diff --git a/arch/arm/include/asm/entry-macro-vic2.S b/arch/arm/include/asm/entry-macro-vic2.S
deleted file mode 100644 (file)
index 3ceb85e..0000000
+++ /dev/null
@@ -1,57 +0,0 @@
-/* arch/arm/include/asm/entry-macro-vic2.S
- *
- * Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *     http://armlinux.simtec.co.uk/
- *     Ben Dooks <ben@simtec.co.uk>
- *
- * Low-level IRQ helper macros for a device with two VICs
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-/* This should be included from <mach/entry-macro.S> with the necessary
- * defines for virtual addresses and IRQ bases for the two vics.
- *
- * The code needs the following defined:
- *     IRQ_VIC0_BASE   IRQ number of VIC0's first IRQ
- *     IRQ_VIC1_BASE   IRQ number of VIC1's first IRQ
- *     VA_VIC0         Virtual address of VIC0
- *     VA_VIC1         Virtual address of VIC1
- *
- * Note, code assumes VIC0's virtual address is an ARM immediate constant
- * away from VIC1.
-*/
-
-#include <asm/hardware/vic.h>
-
-       .macro  disable_fiq
-       .endm
-
-       .macro  get_irqnr_preamble, base, tmp
-       ldr     \base, =VA_VIC0
-       .endm
-
-       .macro  arch_ret_to_user, tmp1, tmp2
-       .endm
-
-       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-       @ check the vic0
-       mov     \irqnr, #IRQ_VIC0_BASE + 31
-       ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
-       teq     \irqstat, #0
-
-       @ otherwise try vic1
-       addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
-       addeq   \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE)
-       ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-       teqeq   \irqstat, #0
-
-       clzne   \irqstat, \irqstat
-       subne   \irqnr, \irqnr, \irqstat
-       .endm
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
deleted file mode 100644 (file)
index 74ebc80..0000000
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/entry-macro-gic.S
- *
- * Low-level IRQ helper macros for GIC
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/gic.h>
-
-#ifndef HAVE_GET_IRQNR_PREAMBLE
-       .macro  get_irqnr_preamble, base, tmp
-       ldr     \base, =gic_cpu_base_addr
-       ldr     \base, [\base]
-       .endm
-#endif
-
-/*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec.  To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-31 are local.  We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt.  We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
-       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-       ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-       /* bits 12-10 = src CPU, 9-0 = int # */
-
-       ldr     \tmp, =1021
-       bic     \irqnr, \irqstat, #0x1c00
-       cmp     \irqnr, #15
-       cmpcc   \irqnr, \irqnr
-       cmpne   \irqnr, \tmp
-       cmpcs   \irqnr, \irqnr
-       .endm
-
-/* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
-       .macro test_for_ipi, irqnr, irqstat, base, tmp
-       bic     \irqnr, \irqstat, #0x1c00
-       cmp     \irqnr, #16
-       strcc   \irqstat, [\base, #GIC_CPU_EOI]
-       cmpcs   \irqnr, \irqnr
-       .endm
index 3e91f22046f55d602550c1a0961312f2c9d4ba33..4bdfe0018696610f30fdfc41d197bd6c096d9777 100644 (file)
 #include <linux/irqdomain.h>
 struct device_node;
 
-extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
 
-void gic_init(unsigned int, int, void __iomem *, void __iomem *);
+void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
+                   u32 offset);
 int gic_of_init(struct device_node *node, struct device_node *parent);
 void gic_secondary_init(unsigned int);
+void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 
-struct gic_chip_data {
-       void __iomem *dist_base;
-       void __iomem *cpu_base;
-#ifdef CONFIG_CPU_PM
-       u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
-       u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
-       u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
-       u32 __percpu *saved_ppi_enable;
-       u32 __percpu *saved_ppi_conf;
-#endif
-#ifdef CONFIG_IRQ_DOMAIN
-       struct irq_domain domain;
-#endif
-       unsigned int gic_irqs;
-};
+static inline void gic_init(unsigned int nr, int start,
+                           void __iomem *dist , void __iomem *cpu)
+{
+       gic_init_bases(nr, start, dist, cpu, 0);
+}
+
 #endif
 
 #endif
index 5d72550a809766cd98d6006221fd142af86cb815..f42ebd619590cf1fed99befda12624f074d16a08 100644 (file)
 #define VIC_PL192_VECT_ADDR            0xF00
 
 #ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+struct device_node;
+struct pt_regs;
+
 void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
-#endif
+int vic_of_init(struct device_node *node, struct device_node *parent);
+void vic_handle_irq(struct pt_regs *regs);
 
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h
new file mode 100644 (file)
index 0000000..bf863ed
--- /dev/null
@@ -0,0 +1,14 @@
+#ifndef __ASM_IDMAP_H
+#define __ASM_IDMAP_H
+
+#include <linux/compiler.h>
+#include <asm/pgtable.h>
+
+/* Tag a function as requiring to be executed via an identity mapping. */
+#define __idmap __section(.idmap.text) noinline notrace
+
+extern pgd_t *idmap_pgd;
+
+void setup_mm_for_reboot(void);
+
+#endif /* __ASM_IDMAP_H */
index 2b0efc3104ac6f73846fb89cdf0761c400676540..bcb0c883e21ed06aa18c9f48354314c877523a8b 100644 (file)
@@ -31,10 +31,10 @@ struct machine_desc {
        unsigned int            video_start;    /* start of video RAM   */
        unsigned int            video_end;      /* end of video RAM     */
 
-       unsigned int            reserve_lp0 :1; /* never has lp0        */
-       unsigned int            reserve_lp1 :1; /* never has lp1        */
-       unsigned int            reserve_lp2 :1; /* never has lp2        */
-       unsigned int            soft_reboot :1; /* soft reboot          */
+       unsigned char           reserve_lp0 :1; /* never has lp0        */
+       unsigned char           reserve_lp1 :1; /* never has lp1        */
+       unsigned char           reserve_lp2 :1; /* never has lp2        */
+       char                    restart_mode;   /* default restart mode */
        void                    (*fixup)(struct tag *, char **,
                                         struct meminfo *);
        void                    (*reserve)(void);/* reserve mem blocks  */
@@ -46,6 +46,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        void                    (*handle_irq)(struct pt_regs *);
 #endif
+       void                    (*restart)(char, const char *);
 };
 
 /*
index ca94653f1ecbd7ebcbab8079db0d0b74de497ea8..97b440c25c5855977481a40ba18977f1f988dd09 100644 (file)
@@ -151,7 +151,11 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
 #define clear_page(page)       memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
 
+#ifdef CONFIG_ARM_LPAE
+#include <asm/pgtable-3level-types.h>
+#else
 #include <asm/pgtable-2level-types.h>
+#endif
 
 #endif /* CONFIG_MMU */
 
index 0f8e3827a89b314aa47ea827e9d109cbeb8406d9..99cfe36079893101b382acf9a5fefd6279f206aa 100644 (file)
@@ -32,7 +32,4 @@ enum arm_perf_pmu_ids {
 extern enum arm_perf_pmu_ids
 armpmu_get_pmu_id(void);
 
-extern int
-armpmu_get_max_events(void);
-
 #endif /* __ARM_PERF_EVENT_H__ */
index 3e08fd3fbb6bc5772688b8001aebfb5ad1e16acd..943504f53f579e58c878165c595d5a110dae00ed 100644 (file)
 #define _PAGE_USER_TABLE       (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
 #define _PAGE_KERNEL_TABLE     (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
 
+#ifdef CONFIG_ARM_LPAE
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+       return (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+       BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
+       free_page((unsigned long)pmd);
+}
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+       set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
+}
+
+#else  /* !CONFIG_ARM_LPAE */
+
 /*
  * Since we have only two-level page tables, these are trivial
  */
 #define pmd_alloc_one(mm,addr)         ({ BUG(); ((pmd_t *)2); })
 #define pmd_free(mm, pmd)              do { } while (0)
-#define pgd_populate(mm,pmd,pte)       BUG()
+#define pud_populate(mm,pmd,pte)       BUG()
+
+#endif /* CONFIG_ARM_LPAE */
 
 extern pgd_t *pgd_alloc(struct mm_struct *mm);
 extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
@@ -109,7 +131,9 @@ static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte,
 {
        pmdval_t pmdval = (pte + PTE_HWTABLE_OFF) | prot;
        pmdp[0] = __pmd(pmdval);
+#ifndef CONFIG_ARM_LPAE
        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
+#endif
        flush_pmd_entry(pmdp);
 }
 
index 470457e1cfc5e121158037e6a1db6fead1eb3602..2317a71c8f8ec4c2cbc5404d96d1c3953877eda8 100644 (file)
 #define L_PTE_MT_DEV_CACHED    (_AT(pteval_t, 0x0b) << 2)      /* 1011 */
 #define L_PTE_MT_MASK          (_AT(pteval_t, 0x0f) << 2)
 
+#ifndef __ASSEMBLY__
+
+/*
+ * The "pud_xxx()" functions here are trivial when the pmd is folded into
+ * the pud: the pud entry is never bad, always exists, and can't be set or
+ * cleared.
+ */
+#define pud_none(pud)          (0)
+#define pud_bad(pud)           (0)
+#define pud_present(pud)       (1)
+#define pud_clear(pudp)                do { } while (0)
+#define set_pud(pud,pudp)      do { } while (0)
+
+static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
+{
+       return (pmd_t *)pud;
+}
+
+#define pmd_bad(pmd)           (pmd_val(pmd) & 2)
+
+#define copy_pmd(pmdpd,pmdps)          \
+       do {                            \
+               pmdpd[0] = pmdps[0];    \
+               pmdpd[1] = pmdps[1];    \
+               flush_pmd_entry(pmdpd); \
+       } while (0)
+
+#define pmd_clear(pmdp)                        \
+       do {                            \
+               pmdp[0] = __pmd(0);     \
+               pmdp[1] = __pmd(0);     \
+               clean_pmd_entry(pmdp);  \
+       } while (0)
+
+/* we don't need complex calculations here as the pmd is folded into the pgd */
+#define pmd_addr_end(addr,end) (end)
+
+#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* _ASM_PGTABLE_2LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
new file mode 100644 (file)
index 0000000..d795282
--- /dev/null
@@ -0,0 +1,77 @@
+/*
+ * arch/arm/include/asm/pgtable-3level-hwdef.h
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H
+#define _ASM_PGTABLE_3LEVEL_HWDEF_H
+
+/*
+ * Hardware page table definitions.
+ *
+ * + Level 1/2 descriptor
+ *   - common
+ */
+#define PMD_TYPE_MASK          (_AT(pmdval_t, 3) << 0)
+#define PMD_TYPE_FAULT         (_AT(pmdval_t, 0) << 0)
+#define PMD_TYPE_TABLE         (_AT(pmdval_t, 3) << 0)
+#define PMD_TYPE_SECT          (_AT(pmdval_t, 1) << 0)
+#define PMD_BIT4               (_AT(pmdval_t, 0))
+#define PMD_DOMAIN(x)          (_AT(pmdval_t, 0))
+
+/*
+ *   - section
+ */
+#define PMD_SECT_BUFFERABLE    (_AT(pmdval_t, 1) << 2)
+#define PMD_SECT_CACHEABLE     (_AT(pmdval_t, 1) << 3)
+#define PMD_SECT_S             (_AT(pmdval_t, 3) << 8)
+#define PMD_SECT_AF            (_AT(pmdval_t, 1) << 10)
+#define PMD_SECT_nG            (_AT(pmdval_t, 1) << 11)
+#define PMD_SECT_XN            (_AT(pmdval_t, 1) << 54)
+#define PMD_SECT_AP_WRITE      (_AT(pmdval_t, 0))
+#define PMD_SECT_AP_READ       (_AT(pmdval_t, 0))
+#define PMD_SECT_TEX(x)                (_AT(pmdval_t, 0))
+
+/*
+ * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
+ */
+#define PMD_SECT_UNCACHED      (_AT(pmdval_t, 0) << 2) /* strongly ordered */
+#define PMD_SECT_BUFFERED      (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */
+#define PMD_SECT_WT            (_AT(pmdval_t, 2) << 2) /* normal inner write-through */
+#define PMD_SECT_WB            (_AT(pmdval_t, 3) << 2) /* normal inner write-back */
+#define PMD_SECT_WBWA          (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */
+
+/*
+ * + Level 3 descriptor (PTE)
+ */
+#define PTE_TYPE_MASK          (_AT(pteval_t, 3) << 0)
+#define PTE_TYPE_FAULT         (_AT(pteval_t, 0) << 0)
+#define PTE_TYPE_PAGE          (_AT(pteval_t, 3) << 0)
+#define PTE_BUFFERABLE         (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
+#define PTE_CACHEABLE          (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
+#define PTE_EXT_SHARED         (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
+#define PTE_EXT_AF             (_AT(pteval_t, 1) << 10)        /* Access Flag */
+#define PTE_EXT_NG             (_AT(pteval_t, 1) << 11)        /* nG */
+#define PTE_EXT_XN             (_AT(pteval_t, 1) << 54)        /* XN */
+
+/*
+ * 40-bit physical address supported.
+ */
+#define PHYS_MASK_SHIFT                (40)
+#define PHYS_MASK              ((1ULL << PHYS_MASK_SHIFT) - 1)
+
+#endif
diff --git a/arch/arm/include/asm/pgtable-3level-types.h b/arch/arm/include/asm/pgtable-3level-types.h
new file mode 100644 (file)
index 0000000..921aa30
--- /dev/null
@@ -0,0 +1,70 @@
+/*
+ * arch/arm/include/asm/pgtable-3level-types.h
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_PGTABLE_3LEVEL_TYPES_H
+#define _ASM_PGTABLE_3LEVEL_TYPES_H
+
+#include <asm/types.h>
+
+typedef u64 pteval_t;
+typedef u64 pmdval_t;
+typedef u64 pgdval_t;
+
+#undef STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { pteval_t pte; } pte_t;
+typedef struct { pmdval_t pmd; } pmd_t;
+typedef struct { pgdval_t pgd; } pgd_t;
+typedef struct { pteval_t pgprot; } pgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define pmd_val(x)      ((x).pmd)
+#define pgd_val(x)     ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgd(x)       ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+#else  /* !STRICT_MM_TYPECHECKS */
+
+typedef pteval_t pte_t;
+typedef pmdval_t pmd_t;
+typedef pgdval_t pgd_t;
+typedef pteval_t pgprot_t;
+
+#define pte_val(x)     (x)
+#define pmd_val(x)     (x)
+#define pgd_val(x)     (x)
+#define pgprot_val(x)  (x)
+
+#define __pte(x)       (x)
+#define __pmd(x)       (x)
+#define __pgd(x)       (x)
+#define __pgprot(x)    (x)
+
+#endif /* STRICT_MM_TYPECHECKS */
+
+#endif /* _ASM_PGTABLE_3LEVEL_TYPES_H */
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
new file mode 100644 (file)
index 0000000..759af70
--- /dev/null
@@ -0,0 +1,155 @@
+/*
+ * arch/arm/include/asm/pgtable-3level.h
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_PGTABLE_3LEVEL_H
+#define _ASM_PGTABLE_3LEVEL_H
+
+/*
+ * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
+ * 8 bytes each, occupying a 4K page. The first level table covers a range of
+ * 512GB, each entry representing 1GB. Since we are limited to 4GB input
+ * address range, only 4 entries in the PGD are used.
+ *
+ * There are enough spare bits in a page table entry for the kernel specific
+ * state.
+ */
+#define PTRS_PER_PTE           512
+#define PTRS_PER_PMD           512
+#define PTRS_PER_PGD           4
+
+#define PTE_HWTABLE_PTRS       (PTRS_PER_PTE)
+#define PTE_HWTABLE_OFF                (0)
+#define PTE_HWTABLE_SIZE       (PTRS_PER_PTE * sizeof(u64))
+
+/*
+ * PGDIR_SHIFT determines the size a top-level page table entry can map.
+ */
+#define PGDIR_SHIFT            30
+
+/*
+ * PMD_SHIFT determines the size a middle-level page table entry can map.
+ */
+#define PMD_SHIFT              21
+
+#define PMD_SIZE               (1UL << PMD_SHIFT)
+#define PMD_MASK               (~(PMD_SIZE-1))
+#define PGDIR_SIZE             (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK             (~(PGDIR_SIZE-1))
+
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT          21
+#define SECTION_SIZE           (1UL << SECTION_SHIFT)
+#define SECTION_MASK           (~(SECTION_SIZE-1))
+
+#define USER_PTRS_PER_PGD      (PAGE_OFFSET / PGDIR_SIZE)
+
+/*
+ * "Linux" PTE definitions for LPAE.
+ *
+ * These bits overlap with the hardware bits but the naming is preserved for
+ * consistency with the classic page table format.
+ */
+#define L_PTE_PRESENT          (_AT(pteval_t, 3) << 0)         /* Valid */
+#define L_PTE_FILE             (_AT(pteval_t, 1) << 2)         /* only when !PRESENT */
+#define L_PTE_BUFFERABLE       (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
+#define L_PTE_CACHEABLE                (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
+#define L_PTE_USER             (_AT(pteval_t, 1) << 6)         /* AP[1] */
+#define L_PTE_RDONLY           (_AT(pteval_t, 1) << 7)         /* AP[2] */
+#define L_PTE_SHARED           (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
+#define L_PTE_YOUNG            (_AT(pteval_t, 1) << 10)        /* AF */
+#define L_PTE_XN               (_AT(pteval_t, 1) << 54)        /* XN */
+#define L_PTE_DIRTY            (_AT(pteval_t, 1) << 55)        /* unused */
+#define L_PTE_SPECIAL          (_AT(pteval_t, 1) << 56)        /* unused */
+
+/*
+ * To be used in assembly code with the upper page attributes.
+ */
+#define L_PTE_XN_HIGH          (1 << (54 - 32))
+#define L_PTE_DIRTY_HIGH       (1 << (55 - 32))
+
+/*
+ * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
+ */
+#define L_PTE_MT_UNCACHED      (_AT(pteval_t, 0) << 2) /* strongly ordered */
+#define L_PTE_MT_BUFFERABLE    (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
+#define L_PTE_MT_WRITETHROUGH  (_AT(pteval_t, 2) << 2) /* normal inner write-through */
+#define L_PTE_MT_WRITEBACK     (_AT(pteval_t, 3) << 2) /* normal inner write-back */
+#define L_PTE_MT_WRITEALLOC    (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
+#define L_PTE_MT_DEV_SHARED    (_AT(pteval_t, 4) << 2) /* device */
+#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
+#define L_PTE_MT_DEV_WC                (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
+#define L_PTE_MT_DEV_CACHED    (_AT(pteval_t, 3) << 2) /* normal inner write-back */
+#define L_PTE_MT_MASK          (_AT(pteval_t, 7) << 2)
+
+/*
+ * Software PGD flags.
+ */
+#define L_PGD_SWAPPER          (_AT(pgdval_t, 1) << 55)        /* swapper_pg_dir entry */
+
+#ifndef __ASSEMBLY__
+
+#define pud_none(pud)          (!pud_val(pud))
+#define pud_bad(pud)           (!(pud_val(pud) & 2))
+#define pud_present(pud)       (pud_val(pud))
+
+#define pud_clear(pudp)                        \
+       do {                            \
+               *pudp = __pud(0);       \
+               clean_pmd_entry(pudp);  \
+       } while (0)
+
+#define set_pud(pudp, pud)             \
+       do {                            \
+               *pudp = pud;            \
+               flush_pmd_entry(pudp);  \
+       } while (0)
+
+static inline pmd_t *pud_page_vaddr(pud_t pud)
+{
+       return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
+}
+
+/* Find an entry in the second-level page table.. */
+#define pmd_index(addr)                (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
+static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
+{
+       return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
+}
+
+#define pmd_bad(pmd)           (!(pmd_val(pmd) & 2))
+
+#define copy_pmd(pmdpd,pmdps)          \
+       do {                            \
+               *pmdpd = *pmdps;        \
+               flush_pmd_entry(pmdpd); \
+       } while (0)
+
+#define pmd_clear(pmdp)                        \
+       do {                            \
+               *pmdp = __pmd(0);       \
+               clean_pmd_entry(pmdp);  \
+       } while (0)
+
+#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_PGTABLE_3LEVEL_H */
index 183111164ce93cc3c3ec3e1502c9b4fb8c53934c..8426229ba29282582a20bf65a2c08253f914edf3 100644 (file)
 #ifndef _ASMARM_PGTABLE_HWDEF_H
 #define _ASMARM_PGTABLE_HWDEF_H
 
+#ifdef CONFIG_ARM_LPAE
+#include <asm/pgtable-3level-hwdef.h>
+#else
 #include <asm/pgtable-2level-hwdef.h>
+#endif
 
 #endif
index 9451dce3a5530f9c50c9a34d9ef84e2366a9bbab..3f2f0eb7621112daf7f7bf93a2f12d22582f9de3 100644 (file)
 #define _ASMARM_PGTABLE_H
 
 #include <linux/const.h>
-#include <asm-generic/4level-fixup.h>
 #include <asm/proc-fns.h>
 
 #ifndef CONFIG_MMU
 
+#include <asm-generic/4level-fixup.h>
 #include "pgtable-nommu.h"
 
 #else
 
+#include <asm-generic/pgtable-nopud.h>
 #include <asm/memory.h>
-#include <mach/vmalloc.h>
 #include <asm/pgtable-hwdef.h>
 
+#ifdef CONFIG_ARM_LPAE
+#include <asm/pgtable-3level.h>
+#else
 #include <asm/pgtable-2level.h>
+#endif
 
 /*
  * Just any arbitrary offset to the start of the vmalloc VM area: the
  * any out-of-bounds memory accesses will hopefully be caught.
  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  * area for the same reason. ;)
- *
- * Note that platforms may override VMALLOC_START, but they must provide
- * VMALLOC_END.  VMALLOC_END defines the (exclusive) limit of this space,
- * which may not overlap IO space.
  */
-#ifndef VMALLOC_START
 #define VMALLOC_OFFSET         (8*1024*1024)
 #define VMALLOC_START          (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END            0xff000000UL
+
+/* This is a temporary hack until shmobile's DMA area size is sorted out */
+#ifdef CONFIG_ARCH_SHMOBILE
+#warning "SH-Mobile's consistent DMA size conflicts with VMALLOC_END by 144MB"
+#undef VMALLOC_END
+#define VMALLOC_END            0xF6000000UL
 #endif
 
 #define LIBRARY_TEXT_START     0x0c000000
@@ -163,39 +169,8 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(addr)     pgd_offset(&init_mm, addr)
 
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-#define pgd_none(pgd)          (0)
-#define pgd_bad(pgd)           (0)
-#define pgd_present(pgd)       (1)
-#define pgd_clear(pgdp)                do { } while (0)
-#define set_pgd(pgd,pgdp)      do { } while (0)
-#define set_pud(pud,pudp)      do { } while (0)
-
-
-/* Find an entry in the second-level page table.. */
-#define pmd_offset(dir, addr)  ((pmd_t *)(dir))
-
 #define pmd_none(pmd)          (!pmd_val(pmd))
 #define pmd_present(pmd)       (pmd_val(pmd))
-#define pmd_bad(pmd)           (pmd_val(pmd) & 2)
-
-#define copy_pmd(pmdpd,pmdps)          \
-       do {                            \
-               pmdpd[0] = pmdps[0];    \
-               pmdpd[1] = pmdps[1];    \
-               flush_pmd_entry(pmdpd); \
-       } while (0)
-
-#define pmd_clear(pmdp)                        \
-       do {                            \
-               pmdp[0] = __pmd(0);     \
-               pmdp[1] = __pmd(0);     \
-               clean_pmd_entry(pmdp);  \
-       } while (0)
 
 static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 {
@@ -204,10 +179,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 
 #define pmd_page(pmd)          pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
 
-/* we don't need complex calculations here as the pmd is folded into the pgd */
-#define pmd_addr_end(addr,end) (end)
-
-
 #ifndef CONFIG_HIGHPTE
 #define __pte_map(pmd)         pmd_page_vaddr(*(pmd))
 #define __pte_unmap(pte)       do { } while (0)
@@ -229,7 +200,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 #define pte_page(pte)          pfn_to_page(pte_pfn(pte))
 #define mk_pte(page,prot)      pfn_pte(page_to_pfn(page), prot)
 
-#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 #define pte_clear(mm,addr,ptep)        set_pte_ext(ptep, __pte(0), 0)
 
 #if __LINUX_ARM_ARCH__ < 6
@@ -346,9 +316,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 
 #define pgtable_cache_init() do { } while (0)
 
-void identity_mapping_add(pgd_t *, unsigned long, unsigned long);
-void identity_mapping_del(pgd_t *, unsigned long, unsigned long);
-
 #endif /* !__ASSEMBLY__ */
 
 #endif /* CONFIG_MMU */
index 0bda22c094a6dd1b70100444d6e29fa1a41688ef..b5a5be2536c1158acf5a9c979eccb0f5588bb97c 100644 (file)
@@ -27,13 +27,22 @@ enum arm_pmu_type {
 /*
  * struct arm_pmu_platdata - ARM PMU platform data
  *
- * @handle_irq: an optional handler which will be called from the interrupt and
- * passed the address of the low level handler, and can be used to implement
- * any platform specific handling before or after calling it.
+ * @handle_irq: an optional handler which will be called from the
+ *     interrupt and passed the address of the low level handler,
+ *     and can be used to implement any platform specific handling
+ *     before or after calling it.
+ * @enable_irq: an optional handler which will be called after
+ *     request_irq and be used to handle some platform specific
+ *     irq enablement
+ * @disable_irq: an optional handler which will be called before
+ *     free_irq and be used to handle some platform specific
+ *     irq disablement
  */
 struct arm_pmu_platdata {
        irqreturn_t (*handle_irq)(int irq, void *dev,
                                  irq_handler_t pmu_handler);
+       void (*enable_irq)(int irq);
+       void (*disable_irq)(int irq);
 };
 
 #ifdef CONFIG_CPU_HAS_PMU
index 9e92cb205e656e61d1b47a3aed9268dd343db205..f3628fb3d2b331a9dba24fc29fdb8bf4b3c6b3d1 100644 (file)
@@ -65,7 +65,11 @@ extern struct processor {
         * Set a possibly extended PTE.  Non-extended PTEs should
         * ignore 'ext'.
         */
+#ifdef CONFIG_ARM_LPAE
+       void (*set_pte_ext)(pte_t *ptep, pte_t pte);
+#else
        void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext);
+#endif
 
        /* Suspend/resume */
        unsigned int suspend_size;
@@ -79,7 +83,11 @@ extern void cpu_proc_fin(void);
 extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+#ifdef CONFIG_ARM_LPAE
+extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
+#else
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
+#endif
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
 
 /* These three are private to arch/arm/kernel/suspend.c */
@@ -107,6 +115,18 @@ extern void cpu_resume(void);
 
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
 
+#ifdef CONFIG_ARM_LPAE
+#define cpu_get_pgd()  \
+       ({                                              \
+               unsigned long pg, pg2;                  \
+               __asm__("mrrc   p15, 0, %0, %1, c2"     \
+                       : "=r" (pg), "=r" (pg2)         \
+                       :                               \
+                       : "cc");                        \
+               pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);  \
+               (pgd_t *)phys_to_virt(pg);              \
+       })
+#else
 #define cpu_get_pgd()  \
        ({                                              \
                unsigned long pg;                       \
@@ -115,6 +135,7 @@ extern void cpu_resume(void);
                pg &= ~0x3fff;                          \
                (pgd_t *)phys_to_virt(pg);              \
        })
+#endif
 
 #endif
 
index 984014b92647a8a1a093f8b46ce05dfd729ca473..53785828744ca687be6a6aec35176289d1a2cbe4 100644 (file)
@@ -80,6 +80,14 @@ struct siginfo;
 void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
                unsigned long err, unsigned long trap);
 
+#ifdef CONFIG_ARM_LPAE
+#define FAULT_CODE_ALIGNMENT   33
+#define FAULT_CODE_DEBUG       34
+#else
+#define FAULT_CODE_ALIGNMENT   1
+#define FAULT_CODE_DEBUG       2
+#endif
+
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                       struct pt_regs *),
                     int sig, int code, const char *name);
@@ -101,6 +109,7 @@ extern int __pure cpu_architecture(void);
 extern void cpu_init(void);
 
 void arm_machine_restart(char mode, const char *cmd);
+void soft_restart(unsigned long);
 extern void (*arm_pm_restart)(char str, const char *cmd);
 
 #define UDBG_UNDEFINED (1 << 0)
index 265f908c4a6e79b98e07d43b7614c5164e86da53..5d3ed7e38561dd43553d1d3bf1b2af07e0d2b747 100644 (file)
@@ -202,8 +202,18 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
        tlb_remove_page(tlb, pte);
 }
 
+static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
+                                 unsigned long addr)
+{
+#ifdef CONFIG_ARM_LPAE
+       tlb_add_flush(tlb, addr);
+       tlb_remove_page(tlb, virt_to_page(pmdp));
+#endif
+}
+
 #define pte_free_tlb(tlb, ptep, addr)  __pte_free_tlb(tlb, ptep, addr)
-#define pmd_free_tlb(tlb, pmdp, addr)  pmd_free((tlb)->mm, pmdp)
+#define pmd_free_tlb(tlb, pmdp, addr)  __pmd_free_tlb(tlb, pmdp, addr)
+#define pud_free_tlb(tlb, pudp, addr)  pud_free((tlb)->mm, pudp)
 
 #define tlb_migrate_finish(mm)         do { } while (0)
 
index b145f16c91bc786db82fcd3cd66ccdee7b740aa4..3a456c6c70056f9267f592792193d2176c045802 100644 (file)
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        ldr     r1, =handle_arch_irq
        mov     r0, sp
-       ldr     r1, [r1]
        adr     lr, BSYM(9997f)
-       teq     r1, #0
-       movne   pc, r1
-#endif
+       ldr     pc, [r1]
+#else
        arch_irq_handler_default
+#endif
 9997:
        .endm
 
index 08c82fd844a8683533216048b54ff2f210729fb6..14e277d2ff911ec7690c4223c5acea4b602e3450 100644 (file)
 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
 #endif
 
+#ifdef CONFIG_ARM_LPAE
+       /* LPAE requires an additional page for the PGD */
+#define PG_DIR_SIZE    0x5000
+#define PMD_ORDER      3
+#else
 #define PG_DIR_SIZE    0x4000
 #define PMD_ORDER      2
+#endif
 
        .globl  swapper_pg_dir
        .equ    swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
@@ -164,17 +170,36 @@ __create_page_tables:
        teq     r0, r6
        bne     1b
 
+#ifdef CONFIG_ARM_LPAE
+       /*
+        * Build the PGD table (first level) to point to the PMD table. A PGD
+        * entry is 64-bit wide.
+        */
+       mov     r0, r4
+       add     r3, r4, #0x1000                 @ first PMD table address
+       orr     r3, r3, #3                      @ PGD block type
+       mov     r6, #4                          @ PTRS_PER_PGD
+       mov     r7, #1 << (55 - 32)             @ L_PGD_SWAPPER
+1:     str     r3, [r0], #4                    @ set bottom PGD entry bits
+       str     r7, [r0], #4                    @ set top PGD entry bits
+       add     r3, r3, #0x1000                 @ next PMD table
+       subs    r6, r6, #1
+       bne     1b
+
+       add     r4, r4, #0x1000                 @ point to the PMD tables
+#endif
+
        ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 
        /*
         * Create identity mapping to cater for __enable_mmu.
         * This identity mapping will be removed by paging_init().
         */
-       adr     r0, __enable_mmu_loc
+       adr     r0, __turn_mmu_on_loc
        ldmia   r0, {r3, r5, r6}
        sub     r0, r0, r3                      @ virt->phys offset
-       add     r5, r5, r0                      @ phys __enable_mmu
-       add     r6, r6, r0                      @ phys __enable_mmu_end
+       add     r5, r5, r0                      @ phys __turn_mmu_on
+       add     r6, r6, r0                      @ phys __turn_mmu_on_end
        mov     r5, r5, lsr #SECTION_SHIFT
        mov     r6, r6, lsr #SECTION_SHIFT
 
@@ -219,8 +244,8 @@ __create_page_tables:
 #endif
 
        /*
-        * Then map boot params address in r2 or
-        * the first 1MB of ram if boot params address is not specified.
+        * Then map boot params address in r2 or the first 1MB (2MB with LPAE)
+        * of ram if boot params address is not specified.
         */
        mov     r0, r2, lsr #SECTION_SHIFT
        movs    r0, r0, lsl #SECTION_SHIFT
@@ -251,7 +276,15 @@ __create_page_tables:
        mov     r3, r7, lsr #SECTION_SHIFT
        ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
        orr     r3, r7, r3, lsl #SECTION_SHIFT
+#ifdef CONFIG_ARM_LPAE
+       mov     r7, #1 << (54 - 32)             @ XN
+#else
+       orr     r3, r3, #PMD_SECT_XN
+#endif
 1:     str     r3, [r0], #4
+#ifdef CONFIG_ARM_LPAE
+       str     r7, [r0], #4
+#endif
        add     r3, r3, #1 << SECTION_SHIFT
        cmp     r0, r6
        blo     1b
@@ -282,15 +315,18 @@ __create_page_tables:
        add     r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
        str     r3, [r0]
 #endif
+#endif
+#ifdef CONFIG_ARM_LPAE
+       sub     r4, r4, #0x1000         @ point to the PGD table
 #endif
        mov     pc, lr
 ENDPROC(__create_page_tables)
        .ltorg
        .align
-__enable_mmu_loc:
+__turn_mmu_on_loc:
        .long   .
-       .long   __enable_mmu
-       .long   __enable_mmu_end
+       .long   __turn_mmu_on
+       .long   __turn_mmu_on_end
 
 #if defined(CONFIG_SMP)
        __CPUINIT
@@ -374,12 +410,17 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
        bic     r0, r0, #CR_I
 #endif
+#ifdef CONFIG_ARM_LPAE
+       mov     r5, #0
+       mcrr    p15, 0, r4, r5, c2              @ load TTBR0
+#else
        mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
        mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
        mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
+#endif
        b       __turn_mmu_on
 ENDPROC(__enable_mmu)
 
@@ -398,15 +439,19 @@ ENDPROC(__enable_mmu)
  * other registers depend on the function called upon completion
  */
        .align  5
-__turn_mmu_on:
+       .pushsection    .idmap.text, "ax"
+ENTRY(__turn_mmu_on)
        mov     r0, r0
+       instr_sync
        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
        mrc     p15, 0, r3, c0, c0, 0           @ read id reg
+       instr_sync
        mov     r3, r3
        mov     r3, r13
        mov     pc, r3
-__enable_mmu_end:
+__turn_mmu_on_end:
 ENDPROC(__turn_mmu_on)
+       .popsection
 
 
 #ifdef CONFIG_SMP_ON_UP
index 814a52a9dc39abf401629e429879080ca1e2173a..d6a95ef9131d5a567b257c056b6f932ce7b0ac23 100644 (file)
@@ -1016,10 +1016,10 @@ static int __init arch_hw_breakpoint_init(void)
        }
 
        /* Register debug fault handler. */
-       hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
-                       "watchpoint debug exception");
-       hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
-                       "breakpoint debug exception");
+       hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
+                       TRAP_HWBKPT, "watchpoint debug exception");
+       hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
+                       TRAP_HWBKPT, "breakpoint debug exception");
 
        /* Register hotplug notifier. */
        register_cpu_notifier(&dbg_reset_nb);
index e59bbd496c39174da0a6ee4094fe6f717df97a67..764bd456d84f10580b142f0fc44e8a47c97a5a68 100644 (file)
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
+#include <asm/system.h>
 
 extern const unsigned char relocate_new_kernel[];
 extern const unsigned int relocate_new_kernel_size;
 
-extern void setup_mm_for_reboot(char mode);
-
 extern unsigned long kexec_start_address;
 extern unsigned long kexec_indirection_page;
 extern unsigned long kexec_mach_type;
@@ -111,14 +110,6 @@ void machine_kexec(struct kimage *image)
 
        if (kexec_reinit)
                kexec_reinit();
-       local_irq_disable();
-       local_fiq_disable();
-       setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
-       flush_cache_all();
-       outer_flush_all();
-       outer_disable();
-       cpu_proc_fin();
-       outer_inv_all();
-       flush_cache_all();
-       cpu_reset(reboot_code_buffer_phys);
+
+       soft_restart(reboot_code_buffer_phys);
 }
index c475379199b1d149adc4f8e33e00f1d544e4b595..a4f192cc51b23b3d75935a0e550c7f8a4cd6b12d 100644 (file)
@@ -59,8 +59,7 @@ armpmu_get_pmu_id(void)
 }
 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
 
-int
-armpmu_get_max_events(void)
+int perf_num_counters(void)
 {
        int max_events = 0;
 
@@ -69,12 +68,6 @@ armpmu_get_max_events(void)
 
        return max_events;
 }
-EXPORT_SYMBOL_GPL(armpmu_get_max_events);
-
-int perf_num_counters(void)
-{
-       return armpmu_get_max_events();
-}
 EXPORT_SYMBOL_GPL(perf_num_counters);
 
 #define HW_OP_UNSUPPORTED              0xFFFF
@@ -353,15 +346,15 @@ validate_group(struct perf_event *event)
        fake_pmu.used_mask = fake_used_mask;
 
        if (!validate_event(&fake_pmu, leader))
-               return -ENOSPC;
+               return -EINVAL;
 
        list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
                if (!validate_event(&fake_pmu, sibling))
-                       return -ENOSPC;
+                       return -EINVAL;
        }
 
        if (!validate_event(&fake_pmu, event))
-               return -ENOSPC;
+               return -EINVAL;
 
        return 0;
 }
@@ -380,6 +373,8 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
 {
        int i, irq, irqs;
        struct platform_device *pmu_device = armpmu->plat_device;
+       struct arm_pmu_platdata *plat =
+               dev_get_platdata(&pmu_device->dev);
 
        irqs = min(pmu_device->num_resources, num_possible_cpus());
 
@@ -387,8 +382,11 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
                if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
                        continue;
                irq = platform_get_irq(pmu_device, i);
-               if (irq >= 0)
+               if (irq >= 0) {
+                       if (plat && plat->disable_irq)
+                               plat->disable_irq(irq);
                        free_irq(irq, armpmu);
+               }
        }
 
        release_pmu(armpmu->type);
@@ -448,7 +446,8 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
                                irq);
                        armpmu_release_hardware(armpmu);
                        return err;
-               }
+               } else if (plat && plat->enable_irq)
+                       plat->enable_irq(irq);
 
                cpumask_set_cpu(i, &armpmu->active_irqs);
        }
index e63d8115c01b2fc9cabef9a23749cdc60e9ad0e7..533be9930ec22f803e672a2e57217b8c65bfc40b 100644 (file)
@@ -65,13 +65,15 @@ enum armv6_counters {
  * accesses/misses in hardware.
  */
 static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
-       [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
-       [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
-       [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-       [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
-       [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
-       [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_CPU_CYCLES]              = ARMV6_PERFCTR_CPU_CYCLES,
+       [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV6_PERFCTR_INSTR_EXEC,
+       [PERF_COUNT_HW_CACHE_REFERENCES]        = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_CACHE_MISSES]            = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV6_PERFCTR_BR_EXEC,
+       [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV6_PERFCTR_BR_MISPREDICT,
+       [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL,
+       [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV6_PERFCTR_LSU_FULL_STALL,
 };
 
 static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -218,13 +220,15 @@ enum armv6mpcore_perf_types {
  * accesses/misses in hardware.
  */
 static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
-       [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
-       [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
-       [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-       [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
-       [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
-       [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_CPU_CYCLES]              = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
+       [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
+       [PERF_COUNT_HW_CACHE_REFERENCES]        = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_CACHE_MISSES]            = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV6MPCORE_PERFCTR_BR_EXEC,
+       [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
+       [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
+       [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
 };
 
 static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
index 1ef6d0034b85d1172c8efe1d1659e82dbced1032..460bbbb6b88536ba18ded4983b6ee18baf1a4bf4 100644 (file)
@@ -28,165 +28,87 @@ static struct arm_pmu armv7pmu;
  * they are not available.
  */
 enum armv7_perf_types {
-       ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
-       ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
-       ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
-       ARMV7_PERFCTR_DCACHE_REFILL             = 0x03, /* L1 */
-       ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04, /* L1 */
-       ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
-       ARMV7_PERFCTR_DREAD                     = 0x06,
-       ARMV7_PERFCTR_DWRITE                    = 0x07,
-       ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
-       ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
-       ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
-       ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
-       /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
+       ARMV7_PERFCTR_PMNC_SW_INCR                      = 0x00,
+       ARMV7_PERFCTR_L1_ICACHE_REFILL                  = 0x01,
+       ARMV7_PERFCTR_ITLB_REFILL                       = 0x02,
+       ARMV7_PERFCTR_L1_DCACHE_REFILL                  = 0x03,
+       ARMV7_PERFCTR_L1_DCACHE_ACCESS                  = 0x04,
+       ARMV7_PERFCTR_DTLB_REFILL                       = 0x05,
+       ARMV7_PERFCTR_MEM_READ                          = 0x06,
+       ARMV7_PERFCTR_MEM_WRITE                         = 0x07,
+       ARMV7_PERFCTR_INSTR_EXECUTED                    = 0x08,
+       ARMV7_PERFCTR_EXC_TAKEN                         = 0x09,
+       ARMV7_PERFCTR_EXC_EXECUTED                      = 0x0A,
+       ARMV7_PERFCTR_CID_WRITE                         = 0x0B,
+
+       /*
+        * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
         * It counts:
-        *  - all branch instructions,
+        *  - all (taken) branch instructions,
         *  - instructions that explicitly write the PC,
         *  - exception generating instructions.
         */
-       ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
-       ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
-       ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
-       ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
+       ARMV7_PERFCTR_PC_WRITE                          = 0x0C,
+       ARMV7_PERFCTR_PC_IMM_BRANCH                     = 0x0D,
+       ARMV7_PERFCTR_PC_PROC_RETURN                    = 0x0E,
+       ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS              = 0x0F,
+       ARMV7_PERFCTR_PC_BRANCH_MIS_PRED                = 0x10,
+       ARMV7_PERFCTR_CLOCK_CYCLES                      = 0x11,
+       ARMV7_PERFCTR_PC_BRANCH_PRED                    = 0x12,
 
        /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
-       ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
-       ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
-       ARMV7_PERFCTR_PC_BRANCH_PRED            = 0x12,
-       ARMV7_PERFCTR_MEM_ACCESS                = 0x13,
-       ARMV7_PERFCTR_L1_ICACHE_ACCESS          = 0x14,
-       ARMV7_PERFCTR_L1_DCACHE_WB              = 0x15,
-       ARMV7_PERFCTR_L2_DCACHE_ACCESS          = 0x16,
-       ARMV7_PERFCTR_L2_DCACHE_REFILL          = 0x17,
-       ARMV7_PERFCTR_L2_DCACHE_WB              = 0x18,
-       ARMV7_PERFCTR_BUS_ACCESS                = 0x19,
-       ARMV7_PERFCTR_MEMORY_ERROR              = 0x1A,
-       ARMV7_PERFCTR_INSTR_SPEC                = 0x1B,
-       ARMV7_PERFCTR_TTBR_WRITE                = 0x1C,
-       ARMV7_PERFCTR_BUS_CYCLES                = 0x1D,
-
-       ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
+       ARMV7_PERFCTR_MEM_ACCESS                        = 0x13,
+       ARMV7_PERFCTR_L1_ICACHE_ACCESS                  = 0x14,
+       ARMV7_PERFCTR_L1_DCACHE_WB                      = 0x15,
+       ARMV7_PERFCTR_L2_CACHE_ACCESS                   = 0x16,
+       ARMV7_PERFCTR_L2_CACHE_REFILL                   = 0x17,
+       ARMV7_PERFCTR_L2_CACHE_WB                       = 0x18,
+       ARMV7_PERFCTR_BUS_ACCESS                        = 0x19,
+       ARMV7_PERFCTR_MEM_ERROR                         = 0x1A,
+       ARMV7_PERFCTR_INSTR_SPEC                        = 0x1B,
+       ARMV7_PERFCTR_TTBR_WRITE                        = 0x1C,
+       ARMV7_PERFCTR_BUS_CYCLES                        = 0x1D,
+
+       ARMV7_PERFCTR_CPU_CYCLES                        = 0xFF
 };
 
 /* ARMv7 Cortex-A8 specific event types */
 enum armv7_a8_perf_types {
-       ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
-       ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
-       ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
-       ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
-       ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
-       ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
-       ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
-       ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
-       ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
-       ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
-       ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
-       ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
-       ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
-       ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
-       ARMV7_PERFCTR_L2_NEON                   = 0x4E,
-       ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
-       ARMV7_PERFCTR_L1_INST                   = 0x50,
-       ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
-       ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
-       ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
-       ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
-       ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
-       ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
-       ARMV7_PERFCTR_CYCLES_INST               = 0x57,
-       ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
-       ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
-       ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
-
-       ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
-       ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
-       ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
+       ARMV7_A8_PERFCTR_L2_CACHE_ACCESS                = 0x43,
+       ARMV7_A8_PERFCTR_L2_CACHE_REFILL                = 0x44,
+       ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS               = 0x50,
+       ARMV7_A8_PERFCTR_STALL_ISIDE                    = 0x56,
 };
 
 /* ARMv7 Cortex-A9 specific event types */
 enum armv7_a9_perf_types {
-       ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
-       ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
-       ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
-
-       ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
-       ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
-
-       ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
-       ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
-       ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
-       ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
-       ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
-       ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
-       ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
-       ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
-       ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
-
-       ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
-
-       ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
-       ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
-       ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
-       ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
-       ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
-
-       ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
-       ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
-       ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
-       ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
-       ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
-       ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
-       ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
-
-       ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
-       ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
-
-       ARMV7_PERFCTR_ISB_INST                  = 0x90,
-       ARMV7_PERFCTR_DSB_INST                  = 0x91,
-       ARMV7_PERFCTR_DMB_INST                  = 0x92,
-       ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
-
-       ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
-       ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
-       ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
-       ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
-       ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
-       ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
+       ARMV7_A9_PERFCTR_INSTR_CORE_RENAME              = 0x68,
+       ARMV7_A9_PERFCTR_STALL_ICACHE                   = 0x60,
+       ARMV7_A9_PERFCTR_STALL_DISPATCH                 = 0x66,
 };
 
 /* ARMv7 Cortex-A5 specific event types */
 enum armv7_a5_perf_types {
-       ARMV7_PERFCTR_IRQ_TAKEN                 = 0x86,
-       ARMV7_PERFCTR_FIQ_TAKEN                 = 0x87,
-
-       ARMV7_PERFCTR_EXT_MEM_RQST              = 0xc0,
-       ARMV7_PERFCTR_NC_EXT_MEM_RQST           = 0xc1,
-       ARMV7_PERFCTR_PREFETCH_LINEFILL         = 0xc2,
-       ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP    = 0xc3,
-       ARMV7_PERFCTR_ENTER_READ_ALLOC          = 0xc4,
-       ARMV7_PERFCTR_READ_ALLOC                = 0xc5,
-
-       ARMV7_PERFCTR_STALL_SB_FULL             = 0xc9,
+       ARMV7_A5_PERFCTR_PREFETCH_LINEFILL              = 0xc2,
+       ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP         = 0xc3,
 };
 
 /* ARMv7 Cortex-A15 specific event types */
 enum armv7_a15_perf_types {
-       ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS     = 0x40,
-       ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS    = 0x41,
-       ARMV7_PERFCTR_L1_DCACHE_READ_REFILL     = 0x42,
-       ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL    = 0x43,
+       ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ         = 0x40,
+       ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE        = 0x41,
+       ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ         = 0x42,
+       ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE        = 0x43,
 
-       ARMV7_PERFCTR_L1_DTLB_READ_REFILL       = 0x4C,
-       ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL      = 0x4D,
+       ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ           = 0x4C,
+       ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE          = 0x4D,
 
-       ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS     = 0x50,
-       ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS    = 0x51,
-       ARMV7_PERFCTR_L2_DCACHE_READ_REFILL     = 0x52,
-       ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL    = 0x53,
+       ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ          = 0x50,
+       ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE         = 0x51,
+       ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ          = 0x52,
+       ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE         = 0x53,
 
-       ARMV7_PERFCTR_SPEC_PC_WRITE             = 0x76,
+       ARMV7_A15_PERFCTR_PC_WRITE_SPEC                 = 0x76,
 };
 
 /*
@@ -197,13 +119,15 @@ enum armv7_a15_perf_types {
  * accesses/misses in hardware.
  */
 static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
-       [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
-       [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
-       [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-       [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
-       [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-       [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+       [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
+       [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
+       [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+       [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
+       [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+       [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
+       [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 
 static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -217,12 +141,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                 * combined.
                 */
                [C(OP_READ)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -231,12 +155,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(L1I)] = {
                [C(OP_READ)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                       [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                       [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -245,12 +169,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(LL)] = {
                [C(OP_READ)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                       [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                       [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -274,11 +198,11 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -287,14 +211,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(BPU)] = {
                [C(OP_READ)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                       [C(RESULT_MISS)]
-                                       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                       [C(RESULT_MISS)]
-                                       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -321,14 +243,15 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  * Cortex-A9 HW events mapping
  */
 static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
-       [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
-       [PERF_COUNT_HW_INSTRUCTIONS]        =
-                                       ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
-       [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_DCACHE_ACCESS,
-       [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_DCACHE_REFILL,
-       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
-       [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-       [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+       [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
+       [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
+       [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+       [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
+       [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+       [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
+       [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV7_A9_PERFCTR_STALL_DISPATCH,
 };
 
 static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -342,12 +265,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                 * combined.
                 */
                [C(OP_READ)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -357,11 +280,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(L1I)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -399,11 +322,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -412,14 +335,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(BPU)] = {
                [C(OP_READ)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                       [C(RESULT_MISS)]
-                                       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                       [C(RESULT_MISS)]
-                                       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -446,13 +367,15 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  * Cortex-A5 HW events mapping
  */
 static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
-       [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
-       [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
-       [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-       [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
-       [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-       [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
+       [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
+       [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+       [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
+       [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+       [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
+       [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 
 static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -460,42 +383,34 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
        [C(L1D)] = {
                [C(OP_READ)] = {
-                       [C(RESULT_ACCESS)]
-                                       = ARMV7_PERFCTR_DCACHE_ACCESS,
-                       [C(RESULT_MISS)]
-                                       = ARMV7_PERFCTR_DCACHE_REFILL,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+                       [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)]
-                                       = ARMV7_PERFCTR_DCACHE_ACCESS,
-                       [C(RESULT_MISS)]
-                                       = ARMV7_PERFCTR_DCACHE_REFILL,
+                       [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+