]> git.openfabrics.org - ~shefty/rdma-dev.git/commitdiff
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorLinus Torvalds <torvalds@linux-foundation.org>
Sun, 9 Aug 2009 21:57:09 +0000 (14:57 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sun, 9 Aug 2009 21:57:09 +0000 (14:57 -0700)
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86: fix buffer overflow in efi_init()
  x86: Add quirk to make Apple MacBookPro5,1 use reboot=pci
  x86: Fix MSI-X initialization by using online_mask for x2apic target_cpus
  x86: Fix VMI && stack protector

154 files changed:
Documentation/arm/memory.txt
Documentation/lockdep-design.txt
arch/arm/boot/compressed/misc.c
arch/arm/common/clkdev.c
arch/arm/configs/mx27_defconfig
arch/arm/configs/mx3_defconfig
arch/arm/configs/omap3_evm_defconfig
arch/arm/include/asm/atomic.h
arch/arm/kernel/entry-common.S
arch/arm/kernel/signal.c
arch/arm/mach-davinci/board-dm355-evm.c
arch/arm/mach-davinci/board-dm355-leopard.c
arch/arm/mach-davinci/board-dm644x-evm.c
arch/arm/mach-davinci/board-dm646x-evm.c
arch/arm/mach-davinci/board-sffsdr.c
arch/arm/mach-ep93xx/include/mach/ts72xx.h
arch/arm/mach-ep93xx/ts72xx.c
arch/arm/mach-ks8695/include/mach/hardware.h
arch/arm/mach-ks8695/include/mach/timex.h
arch/arm/mach-ks8695/pci.c
arch/arm/mach-omap1/mcbsp.c
arch/arm/mach-omap2/board-omap3evm.c
arch/arm/mach-omap2/mcbsp.c
arch/arm/mach-omap2/usb-musb.c
arch/arm/mach-pxa/em-x270.c
arch/arm/mach-pxa/palmld.c
arch/arm/mach-pxa/palmt5.c
arch/arm/mach-pxa/palmtx.c
arch/arm/mach-pxa/treo680.c
arch/arm/mach-pxa/zylonite_pxa300.c
arch/arm/mach-pxa/zylonite_pxa320.c
arch/arm/mach-s3c2410/include/mach/gpio-core.h
arch/arm/plat-s3c24xx/pwm.c
arch/arm/plat-s3c64xx/pm.c
arch/arm/plat-s3c64xx/s3c6400-clock.c
arch/arm/plat-stmp3xxx/pinmux.c
arch/powerpc/kernel/mpc7450-pmu.c
arch/powerpc/kernel/power4-pmu.c
arch/powerpc/kernel/power5+-pmu.c
arch/powerpc/kernel/power5-pmu.c
arch/powerpc/kernel/power6-pmu.c
arch/powerpc/kernel/power7-pmu.c
arch/powerpc/kernel/ppc970-pmu.c
arch/s390/kernel/early.c
arch/s390/kvm/sigp.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_debugfs.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_suspend.c
drivers/gpu/drm/i915/intel_bios.c
drivers/gpu/drm/i915/intel_bios.h
drivers/gpu/drm/i915/intel_crt.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/i915/intel_lvds.c
drivers/gpu/drm/i915/intel_sdvo.c
drivers/gpu/drm/i915/intel_tv.c
drivers/gpu/drm/radeon/r600_cp.c
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_drv.h
drivers/gpu/drm/radeon/radeon_object.c
drivers/input/keyboard/matrix_keypad.c
drivers/input/misc/wistron_btns.c
drivers/input/serio/i8042-x86ia64io.h
drivers/mmc/host/sdhci-of.c
drivers/mtd/maps/Kconfig
drivers/mtd/maps/Makefile
drivers/mtd/maps/sbc8240.c
drivers/mtd/mtd_blkdevs.c
drivers/mtd/mtdblock.c
drivers/mtd/mtdcore.c
drivers/mtd/onenand/omap2.c
drivers/pci/intel-iommu.c
drivers/serial/s3c2400.c
drivers/serial/s3c2410.c
drivers/serial/s3c2412.c
drivers/serial/s3c2440.c
drivers/serial/s3c24a0.c
drivers/serial/s3c6400.c
drivers/serial/serial_ks8695.c
drivers/staging/b3dfg/Kconfig
drivers/staging/heci/Kconfig
drivers/staging/rspiusb/rspiusb.c
drivers/staging/rt2860/rt_linux.h
drivers/staging/rt2870/2870_main_dev.c
drivers/staging/rt2870/common/2870_rtmp_init.c
drivers/staging/rt2870/common/rtusb_io.c
drivers/staging/rt2870/rt2870.h
drivers/staging/rtl8192su/ieee80211.h
drivers/staging/rtl8192su/ieee80211/ieee80211.h
drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
drivers/staging/rtl8192su/r8192U_core.c
drivers/usb/class/cdc-acm.c
drivers/usb/class/cdc-acm.h
drivers/usb/core/devio.c
drivers/usb/host/ehci-hcd.c
drivers/usb/host/ehci-q.c
drivers/usb/host/ehci-sched.c
drivers/usb/musb/Kconfig
drivers/usb/serial/ftdi_sio.c
drivers/usb/serial/ftdi_sio.h
drivers/usb/serial/pl2303.c
drivers/usb/serial/pl2303.h
drivers/usb/storage/unusual_devs.h
drivers/video/console/fbcon.c
drivers/video/console/fbcon_rotate.h
drivers/video/mx3fb.c
drivers/video/via/hw.c
drivers/video/via/lcd.c
drivers/video/via/viafbdev.c
drivers/video/via/viafbdev.h
drivers/w1/masters/omap_hdq.c
drivers/watchdog/ks8695_wdt.c
fs/binfmt_flat.c
fs/btrfs/extent-tree.c
fs/btrfs/free-space-cache.c
fs/btrfs/inode.c
fs/btrfs/relocation.c
fs/btrfs/zlib.c
fs/compat_ioctl.c
fs/inode.c
fs/jffs2/file.c
fs/namespace.c
fs/xfs/xfs_iget.c
fs/xfs/xfs_inode.h
include/drm/drm_pciids.h
include/linux/decompress/generic.h
include/linux/fs.h
include/linux/ftrace_event.h
include/linux/input/matrix_keypad.h
include/linux/mtd/mtd.h
include/linux/mtd/partitions.h
include/linux/nodemask.h
kernel/fork.c
kernel/lockdep_proc.c
kernel/perf_counter.c
kernel/rtmutex.c
kernel/smp.c
kernel/trace/trace_event_profile.c
kernel/trace/trace_events.c
lib/decompress_bunzip2.c
lib/decompress_inflate.c
lib/decompress_unlzma.c
mm/mempolicy.c
net/core/dev.c
tools/perf/Documentation/perf-record.txt
tools/perf/Makefile
tools/perf/builtin-report.c
tools/perf/util/symbol.c

index 43cb1004d35fb72da88424321ab108da124c52d0..9d58c7c5eddd082b9a22c087c7e0023e02fa4b02 100644 (file)
@@ -21,6 +21,8 @@ ffff8000      ffffffff        copy_user_page / clear_user_page use.
                                For SA11xx and Xscale, this is used to
                                setup a minicache mapping.
 
+ffff4000       ffffffff        cache aliasing on ARMv6 and later CPUs.
+
 ffff1000       ffff7fff        Reserved.
                                Platforms must not use this address range.
 
index e20d913d5914a29261d12f5fa4585164ed170c82..abf768c681e208c3fe5c4d7c5fc27f788c6c29c7 100644 (file)
@@ -30,9 +30,9 @@ State
 The validator tracks lock-class usage history into 4n + 1 separate state bits:
 
 - 'ever held in STATE context'
-- 'ever head as readlock in STATE context'
-- 'ever head with STATE enabled'
-- 'ever head as readlock with STATE enabled'
+- 'ever held as readlock in STATE context'
+- 'ever held with STATE enabled'
+- 'ever held as readlock with STATE enabled'
 
 Where STATE can be either one of (kernel/lockdep_states.h)
  - hardirq
index 9e6e512f0117df5227142b06299747647f2db72d..17153b54613b4c5948db2f66b1cbf7a0716b2309 100644 (file)
@@ -29,7 +29,6 @@ unsigned int __machine_arch_type;
 
 static void putstr(const char *ptr);
 
-#include <linux/compiler.h>
 #include <mach/uncompress.h>
 
 #ifdef CONFIG_DEBUG_ICEDCC
index f37afd9422f3b1905884f525b58b19fcc4dd65f9..aae5bc01acc80d20d1f4cfe46c048d78455a67cb 100644 (file)
@@ -17,6 +17,7 @@
 #include <linux/err.h>
 #include <linux/string.h>
 #include <linux/mutex.h>
+#include <linux/clk.h>
 
 #include <asm/clkdev.h>
 #include <mach/clkdev.h>
index 083516cd0d7fc8dc6dbc984ccf80ce116cdc6f0b..75263a83741c89f70ba8f1d49fec338b4e2a070c 100644 (file)
@@ -1,15 +1,15 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc1
-# Wed Apr  8 10:18:06 2009
+# Linux kernel version: 2.6.31-rc4
+# Fri Jul 24 16:08:06 2009
 #
 CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,14 +18,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -85,7 +84,12 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
@@ -99,6 +103,12 @@ CONFIG_KPROBES=y
 CONFIG_KRETPROBES=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -111,7 +121,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -138,13 +148,14 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -153,25 +164,25 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-CONFIG_ARCH_MXC=y
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
 
 #
 # Freescale MXC Implementations
@@ -188,6 +199,8 @@ CONFIG_MACH_MX27=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_PCM038=y
 CONFIG_MACH_PCM970_BASEBOARD=y
+CONFIG_MACH_MX27_3DS=y
+CONFIG_MACH_MX27LITE=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
 
@@ -213,7 +226,6 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-# CONFIG_OUTER_CACHE is not set
 CONFIG_COMMON_CLKDEV=y
 
 #
@@ -238,7 +250,6 @@ CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -253,10 +264,11 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -361,6 +373,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -474,7 +487,16 @@ CONFIG_MTD_PHYSMAP=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_MXC=y
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -485,7 +507,15 @@ CONFIG_MTD_PHYSMAP=y
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -494,7 +524,21 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MISC_DEVICES is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -508,7 +552,6 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -534,6 +577,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
 CONFIG_FEC=y
 # CONFIG_FEC2 is not set
 # CONFIG_NETDEV_1000 is not set
@@ -580,6 +625,11 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
@@ -592,6 +642,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -644,6 +695,7 @@ CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
 CONFIG_I2C_IMX=y
 # CONFIG_I2C_OCORES is not set
@@ -668,7 +720,6 @@ CONFIG_I2C_IMX=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -719,6 +770,7 @@ CONFIG_W1=y
 #
 # CONFIG_W1_MASTER_DS2482 is not set
 CONFIG_W1_MASTER_MXC=y
+# CONFIG_W1_MASTER_DS1WM is not set
 # CONFIG_W1_MASTER_GPIO is not set
 
 #
@@ -753,54 +805,16 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_SOC_CAMERA is not set
-# CONFIG_RADIO_ADAPTERS is not set
-# CONFIG_DAB is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -917,6 +931,7 @@ CONFIG_RTC_DRV_PCF8563=y
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
@@ -962,12 +977,15 @@ CONFIG_RTC_DRV_PCF8563=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
@@ -1021,6 +1039,12 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -1119,25 +1143,11 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_NOP_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
 CONFIG_TRACING=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_FTRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
@@ -1151,16 +1161,104 @@ CONFIG_ARM_UNWIND=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_RATIONAL=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
@@ -1168,6 +1266,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
index 20ada526f6de3873ed97c9db1de78466d00e21e5..a4f9a2a8149c8f228eec90f263f60e6c96858e97 100644 (file)
@@ -1,15 +1,15 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc1
-# Wed Apr  8 11:06:37 2009
+# Linux kernel version: 2.6.31-rc4
+# Tue Jul 28 14:11:34 2009
 #
 CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,14 +18,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -86,7 +85,12 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
@@ -97,6 +101,11 @@ CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -109,7 +118,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -136,13 +145,14 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -151,25 +161,25 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-CONFIG_ARCH_MXC=y
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
 
 #
 # Freescale MXC Implementations
@@ -178,6 +188,7 @@ CONFIG_ARCH_MXC=y
 # CONFIG_ARCH_MX2 is not set
 CONFIG_ARCH_MX3=y
 CONFIG_ARCH_MX31=y
+CONFIG_ARCH_MX35=y
 
 #
 # MX3 platforms:
@@ -185,12 +196,19 @@ CONFIG_ARCH_MX31=y
 CONFIG_MACH_MX31ADS=y
 CONFIG_MACH_MX31ADS_WM1133_EV1=y
 CONFIG_MACH_PCM037=y
+CONFIG_MACH_PCM037_EET=y
 CONFIG_MACH_MX31LITE=y
 CONFIG_MACH_MX31_3DS=y
 CONFIG_MACH_MX31MOBOARD=y
+CONFIG_MACH_MX31LILLY=y
 CONFIG_MACH_QONG=y
+CONFIG_MACH_PCM043=y
+CONFIG_MACH_ARMADILLO5X0=y
+CONFIG_MACH_MX35_3DS=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
+CONFIG_ARCH_HAS_RNGA=y
+CONFIG_ARCH_MXC_IOMUX_V3=y
 
 #
 # Processor Type
@@ -218,6 +236,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_OUTER_CACHE=y
 CONFIG_CACHE_L2X0=y
+# CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_COMMON_CLKDEV=y
 
 #
@@ -242,7 +261,6 @@ CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -257,10 +275,11 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -362,6 +381,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -465,7 +485,16 @@ CONFIG_MTD_PHYSMAP=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_MXC=y
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -476,10 +505,30 @@ CONFIG_MTD_PHYSMAP=y
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -493,7 +542,6 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -528,7 +576,7 @@ CONFIG_MII=y
 # CONFIG_ETHOC is not set
 # CONFIG_SMC911X is not set
 CONFIG_SMSC911X=y
-# CONFIG_DNET is not set
+CONFIG_DNET=y
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -537,8 +585,10 @@ CONFIG_SMSC911X=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
-CONFIG_CS89x0=y
-CONFIG_CS89x0_NONISA_IRQ=y
+# CONFIG_CS89x0 is not set
+# CONFIG_KS8842 is not set
+CONFIG_FEC=y
+# CONFIG_FEC2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -609,6 +659,7 @@ CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
 CONFIG_I2C_IMX=y
 # CONFIG_I2C_OCORES is not set
@@ -633,7 +684,6 @@ CONFIG_I2C_IMX=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -669,6 +719,7 @@ CONFIG_W1=y
 #
 # CONFIG_W1_MASTER_DS2482 is not set
 CONFIG_W1_MASTER_MXC=y
+# CONFIG_W1_MASTER_DS1WM is not set
 # CONFIG_W1_MASTER_GPIO is not set
 
 #
@@ -703,6 +754,8 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_MFD_WM8400 is not set
@@ -711,10 +764,8 @@ CONFIG_MFD_WM8350_CONFIG_MODE_0=y
 CONFIG_MFD_WM8352_CONFIG_MODE_0=y
 CONFIG_MFD_WM8350_I2C=y
 # CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
+# CONFIG_AB3100_CORE is not set
+CONFIG_MEDIA_SUPPORT=y
 
 #
 # Multimedia core support
@@ -758,8 +809,10 @@ CONFIG_SOC_CAMERA_MT9T031=y
 CONFIG_SOC_CAMERA_MT9V022=y
 CONFIG_SOC_CAMERA_TW9910=y
 # CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_SOC_CAMERA_OV772X=y
+CONFIG_MX3_VIDEO=y
 CONFIG_VIDEO_MX3=y
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
 # CONFIG_RADIO_ADAPTERS is not set
 # CONFIG_DAB is not set
 
@@ -847,8 +900,11 @@ CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
 # CONFIG_REGULATOR_FIXED_VOLTAGE is not set
 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
 # CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
 CONFIG_REGULATOR_WM8350=y
+# CONFIG_REGULATOR_LP3971 is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
@@ -861,10 +917,12 @@ CONFIG_REGULATOR_WM8350=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -921,6 +979,12 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -937,6 +1001,7 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
 CONFIG_ROOT_NFS=y
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=y
@@ -979,22 +1044,7 @@ CONFIG_FRAME_WARN=1024
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_FTRACE is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_ARM_UNWIND=y
@@ -1094,9 +1144,9 @@ CONFIG_CRYPTO_DES=y
 #
 # Compression
 #
-# CONFIG_CRYPTO_DEFLATE is not set
+CONFIG_CRYPTO_DEFLATE=y
 # CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_LZO=y
 
 #
 # Random Number Generation
@@ -1109,9 +1159,10 @@ CONFIG_CRYPTO_HW=y
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_RATIONAL=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
@@ -1119,6 +1170,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
index 28be17fbc1579f1f24a4c9d216fa735252861549..d5ff4776cd0a3500c1439308e54b3e57a20a6eff 100644 (file)
@@ -1107,7 +1107,7 @@ CONFIG_USB_ZERO=m
 CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_ISP1301_OMAP is not set
-CONFIG_TWL4030_USB=y
+# CONFIG_TWL4030_USB is not set
 # CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
index 9e07fe50702913f6324b21faa9dbee4640334b20..9ed2377fe8e54b26fca9fc2ec6a9b6694fb17533 100644 (file)
@@ -159,8 +159,6 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 
 #else /* ARM_ARCH_6 */
 
-#include <asm/system.h>
-
 #ifdef CONFIG_SMP
 #error SMP not supported on pre-ARMv6 CPUs
 #endif
index 366e5097a41a4f535d1d24ddccab44f13580fb64..8c3de1a350b5dd85bdf06b79f1dab163cd305743 100644 (file)
@@ -148,7 +148,7 @@ trace:
        sub r0, r0, #MCOUNT_INSN_SIZE
        mov lr, pc
        mov pc, r2
-       mov lr, r1                              @ restore lr
+       ldr lr, [fp, #-4]                       @ restore lr
        ldmia sp!, {r0-r3, pc}
 
 #endif /* CONFIG_DYNAMIC_FTRACE */
index 93bb4247b7ed019e92a6b64806c86af2fe338c7f..f6bc5d442782374bb99618702722dde5d37e1dc2 100644 (file)
@@ -133,7 +133,7 @@ sys_sigaction(int sig, const struct old_sigaction __user *act,
 }
 
 #ifdef CONFIG_CRUNCH
-static int preserve_crunch_context(struct crunch_sigframe *frame)
+static int preserve_crunch_context(struct crunch_sigframe __user *frame)
 {
        char kbuf[sizeof(*frame) + 8];
        struct crunch_sigframe *kframe;
@@ -146,7 +146,7 @@ static int preserve_crunch_context(struct crunch_sigframe *frame)
        return __copy_to_user(frame, kframe, sizeof(*frame));
 }
 
-static int restore_crunch_context(struct crunch_sigframe *frame)
+static int restore_crunch_context(struct crunch_sigframe __user *frame)
 {
        char kbuf[sizeof(*frame) + 8];
        struct crunch_sigframe *kframe;
index 5ac2f565d860e934df9a52de72a4294c1b0f7fb3..d6ab64ccd496baedad9b2fb49e217bca0ebfdf40 100644 (file)
@@ -37,7 +37,6 @@
 #include <mach/serial.h>
 #include <mach/nand.h>
 #include <mach/mmc.h>
-#include <mach/common.h>
 
 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE                0x01e10000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE       0x02000000
index 28c9008df4f45f1cd43879a83958d69845886485..84ad5d161a874133f88322e1b489fc10936c4b7b 100644 (file)
@@ -36,7 +36,6 @@
 #include <mach/serial.h>
 #include <mach/nand.h>
 #include <mach/mmc.h>
-#include <mach/common.h>
 
 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE                0x01e10000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE       0x02000000
index d9d40450bdc5d8c018b03c18305d282d1160faab..56c8cd01de9ac2feff60be46879552d143196174 100644 (file)
@@ -45,7 +45,6 @@
 #include <mach/nand.h>
 #include <mach/mmc.h>
 #include <mach/emac.h>
-#include <mach/common.h>
 
 #define DM644X_EVM_PHY_MASK            (0x2)
 #define DM644X_EVM_MDIO_FREQUENCY      (2200000) /* PHY bus frequency */
index e17de6352624c2bd4b56e9fb643fb7eb01425c74..8657e72debc1d8ab4796cc952c67a8a18ac9593a 100644 (file)
@@ -47,7 +47,6 @@
 #include <mach/i2c.h>
 #include <mach/mmc.h>
 #include <mach/emac.h>
-#include <mach/common.h>
 
 #define DM646X_EVM_PHY_MASK            (0x2)
 #define DM646X_EVM_MDIO_FREQUENCY      (2200000) /* PHY bus frequency */
index 748a8e48541e4b9788add21e111aad9a766def54..7acdfd8ac0712dc577c0e56f5a0eec26b4919ae8 100644 (file)
@@ -52,7 +52,6 @@
 #include <mach/serial.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
-#include <mach/common.h>
 
 #define SFFSDR_PHY_MASK                (0x2)
 #define SFFSDR_MDIO_FREQUENCY  (2200000) /* PHY bus frequency */
index 34ddec081c40dd817b6ca4741a020e0f3880cab4..411734422c1dd138c7743be759c8088533088436 100644 (file)
@@ -41,9 +41,6 @@
 #define TS72XX_OPTIONS2_TS9420_BOOT    0x02
 
 
-#define TS72XX_NOR_PHYS_BASE           0x60000000
-#define TS72XX_NOR2_PHYS_BASE          0x62000000
-
 #define TS72XX_NAND1_DATA_PHYS_BASE    0x60000000
 #define TS72XX_NAND2_DATA_PHYS_BASE    0x70000000
 #define TS72XX_NAND_DATA_VIRT_BASE     0xfebfc000
index 7ee024d3482984a339f854bc60df755a5ea4c781..aaf1371412afc7bf3281190b42abb14a3820bc0e 100644 (file)
@@ -112,13 +112,16 @@ static void __init ts72xx_map_io(void)
        }
 }
 
+/*************************************************************************
+ * NOR flash (TS-7200 only)
+ *************************************************************************/
 static struct physmap_flash_data ts72xx_flash_data = {
-       .width          = 1,
+       .width          = 2,
 };
 
 static struct resource ts72xx_flash_resource = {
-       .start          = TS72XX_NOR_PHYS_BASE,
-       .end            = TS72XX_NOR_PHYS_BASE + SZ_16M - 1,
+       .start          = EP93XX_CS6_PHYS_BASE,
+       .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
        .flags          = IORESOURCE_MEM,
 };
 
@@ -132,6 +135,12 @@ static struct platform_device ts72xx_flash = {
        .resource       = &ts72xx_flash_resource,
 };
 
+static void __init ts72xx_register_flash(void)
+{
+       if (board_is_ts7200())
+               platform_device_register(&ts72xx_flash);
+}
+
 static unsigned char ts72xx_rtc_readbyte(unsigned long addr)
 {
        __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE);
@@ -165,8 +174,7 @@ static struct ep93xx_eth_data ts72xx_eth_data = {
 static void __init ts72xx_init_machine(void)
 {
        ep93xx_init_devices();
-       if (board_is_ts7200())
-               platform_device_register(&ts72xx_flash);
+       ts72xx_register_flash();
        platform_device_register(&ts72xx_rtc_device);
 
        ep93xx_register_eth(&ts72xx_eth_data, 1);
index 1d640d075b7e58b68ab9b9aad62e6e9ed90adc08..e0f911d9e021711c7ff2489ac7951c114a1a74e3 100644 (file)
 
 #include <asm/sizes.h>
 
+/*
+ * Clocks are derived from MCLK, which is 25Mhz
+ */
+#define KS8695_CLOCK_RATE      25000000
+
 /*
  * Physical RAM address.
  */
index 4682e350369befa80f4163f772e6161a3446c873..10f716371bd350057e8b721690954ac1778bdebd 100644 (file)
@@ -14,7 +14,8 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
 
-/* timers are derived from MCLK, which is 25MHz */
-#define CLOCK_TICK_RATE 25000000
+#include <mach/hardware.h>
+
+#define CLOCK_TICK_RATE        KS8695_CLOCK_RATE
 
 #endif
index f5ebcc0fcab9f9c36eaaf5dcbcc6b350393fbb2a..78499667eb7b3241c3a5c1dfbbc69df4840a3991 100644 (file)
@@ -245,6 +245,9 @@ static int ks8695_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs
 
 static void __init ks8695_pci_preinit(void)
 {
+       /* make software reset to avoid freeze if PCI bus was messed up */
+       __raw_writel(0x80000000, KS8695_PCI_VA + KS8695_PBCS);
+
        /* stage 1 initialization, subid, subdevice = 0x0001 */
        __raw_writel(0x00010001, KS8695_PCI_VA + KS8695_CRCSID);
 
index a2d7814896bea8eb2f96e7eaf052a616e637a307..505d98cfe508c475539445b42a504fa5c8ad20c3 100644 (file)
@@ -19,7 +19,6 @@
 
 #include <mach/irqs.h>
 #include <mach/dma.h>
-#include <mach/irqs.h>
 #include <mach/mux.h>
 #include <mach/cpu.h>
 #include <mach/mcbsp.h>
index d3cc145814d01236bee62974f8d7630b7892ab4a..cf3dd771a6784fe751542fa993e03971a93f946d 100644 (file)
@@ -25,6 +25,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl4030.h>
+#include <linux/usb/otg.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -307,6 +308,10 @@ static void __init omap3_evm_init(void)
                                ARRAY_SIZE(omap3evm_spi_board_info));
 
        omap_serial_init();
+#ifdef CONFIG_NOP_USB_XCEIV
+       /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
+       usb_nop_xceiv_register();
+#endif
        usb_musb_init();
        ads7846_dev_init();
 }
index a5c0f0435cd6725423ededd8b47247d000773916..99b6e15463118ba198cc1cf9182b954dad19f4f8 100644 (file)
@@ -19,7 +19,6 @@
 
 #include <mach/irqs.h>
 #include <mach/dma.h>
-#include <mach/irqs.h>
 #include <mach/mux.h>
 #include <mach/cpu.h>
 #include <mach/mcbsp.h>
index d85296dc896c2090136652997a2d401c5e60e576..739e59e8025cc7b109707ac7f4b302afbb82fb14 100644 (file)
@@ -155,20 +155,6 @@ static struct platform_device musb_device = {
        .resource       = musb_resources,
 };
 
-#ifdef CONFIG_NOP_USB_XCEIV
-static u64 nop_xceiv_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device nop_xceiv_device = {
-       .name           = "nop_usb_xceiv",
-       .id             = -1,
-       .dev = {
-               .dma_mask               = &nop_xceiv_dmamask,
-               .coherent_dma_mask      = DMA_BIT_MASK(32),
-               .platform_data          = NULL,
-       },
-};
-#endif
-
 void __init usb_musb_init(void)
 {
        if (cpu_is_omap243x())
@@ -183,13 +169,6 @@ void __init usb_musb_init(void)
         */
        musb_plat.clock = "ick";
 
-#ifdef CONFIG_NOP_USB_XCEIV
-       if (platform_device_register(&nop_xceiv_device) < 0) {
-               printk(KERN_ERR "Unable to register NOP-XCEIV device\n");
-               return;
-       }
-#endif
-
        if (platform_device_register(&musb_device) < 0) {
                printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
                return;
index 63b10d9bb1d3a374908206d78fb5cc2426a408e5..9cd09465a0e8bbb9474e22d24160de5ef50500a5 100644 (file)
@@ -1141,12 +1141,16 @@ struct power_supply_info em_x270_psy_info = {
 
 static void em_x270_battery_low(void)
 {
+#if defined(CONFIG_APM_EMULATION)
        apm_queue_event(APM_LOW_BATTERY);
+#endif
 }
 
 static void em_x270_battery_critical(void)
 {
+#if defined(CONFIG_APM_EMULATION)
        apm_queue_event(APM_CRITICAL_SUSPEND);
+#endif
 }
 
 struct da9030_battery_info em_x270_batterty_info = {
index ed70f281dd090812f71dac139aaa795660b7b0dd..169fcc18154e68389f32fe35d03a5f95b44f48e1 100644 (file)
@@ -128,6 +128,10 @@ static unsigned long palmld_pin_config[] __initdata = {
        GPIO38_GPIO,    /* wifi ready */
        GPIO81_GPIO,    /* wifi reset */
 
+       /* FFUART */
+       GPIO34_FFUART_RXD,
+       GPIO39_FFUART_TXD,
+
        /* HDD */
        GPIO98_GPIO,    /* HDD reset */
        GPIO115_GPIO,   /* HDD power */
index aae64a12a734e2ce82d2e91cca54d27d0b1cd345..33f726ff55e5ec30784400847746129826bea3be 100644 (file)
@@ -111,6 +111,10 @@ static unsigned long palmt5_pin_config[] __initdata = {
        /* PWM */
        GPIO16_PWM0_OUT,
 
+       /* FFUART */
+       GPIO34_FFUART_RXD,
+       GPIO39_FFUART_TXD,
+
        /* MISC */
        GPIO10_GPIO,    /* hotsync button */
        GPIO90_GPIO,    /* power detect */
index 6c15d84bde53a4853d1ac8e8aa8c119e47ca421e..83d020879581f5438fc1165885fae3140ec11d68 100644 (file)
@@ -127,6 +127,10 @@ static unsigned long palmtx_pin_config[] __initdata = {
        GPIO76_LCD_PCLK,
        GPIO77_LCD_BIAS,
 
+       /* FFUART */
+       GPIO34_FFUART_RXD,
+       GPIO39_FFUART_TXD,
+
        /* MISC. */
        GPIO10_GPIO,    /* hotsync button */
        GPIO12_GPIO,    /* power detect */
index a06f19edebb3a201da7e33645c0e7297af97e13c..753ec4df17b9447f412fbf6edded190e74f4c098 100644 (file)
@@ -409,7 +409,7 @@ err1:
 
 static void treo680_irda_shutdown(struct device *dev)
 {
-       gpio_free(GPIO_NR_TREO680_AMP_EN);
+       gpio_free(GPIO_NR_TREO680_IR_EN);
 }
 
 static struct pxaficp_platform_data treo680_ficp_info = {
index cefd1c0a854aa920df0fdd5704dee5550a07123f..84095440a87870477e78da5cfe0349fb69993efd 100644 (file)
@@ -197,10 +197,12 @@ static void __init zylonite_detect_lcd_panel(void)
        for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
                id = id << 1;
                gpio = mfp_to_gpio(lcd_detect_pins[i]);
+               gpio_request(gpio, "LCD_ID_PINS");
                gpio_direction_input(gpio);
 
                if (gpio_get_value(gpio))
                        id = id | 0x1;
+               gpio_free(gpio);
        }
 
        /* lcd id, flush out bit 1 */
index cc5a22833605e27e99980c866781e9d0fd60b300..60d08f23f5e4ed3933e2ad9855efb8b5b9ad7332 100644 (file)
@@ -176,10 +176,12 @@ static void __init zylonite_detect_lcd_panel(void)
        for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
                id = id << 1;
                gpio = mfp_to_gpio(lcd_detect_pins[i]);
+               gpio_request(gpio, "LCD_ID_PINS");
                gpio_direction_input(gpio);
 
                if (gpio_get_value(gpio))
                        id = id | 0x1;
+               gpio_free(gpio);
        }
 
        /* lcd id, flush out bit 1 */
index 8fe192081d3a7f7720189ab81f397fa2a12b8b0b..f8b879a7973c6fd457e2b1829068a4894dd27922 100644 (file)
@@ -28,7 +28,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
                return NULL;
 
        chip = &s3c24xx_gpios[pin/32];
-       return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
+       return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL;
 }
 
 #endif /* __ASM_ARCH_GPIO_CORE_H */
index 0120b760315ba3a881fdf1829739b015829479a4..82a6d4de02a381ddfff417cf66b8c0425d107502 100644 (file)
@@ -246,6 +246,10 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 
        tcmp = duty_ns / tin_ns;
        tcmp = tcnt - tcmp;
+       /* the pwm hw only checks the compare register after a decrement,
+          so the pin never toggles if tcmp = tcnt */
+       if (tcmp == tcnt)
+               tcmp--;
 
        pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
 
index 07a6516a4f3cdfa97d26aaf71c1821ba19fca761..47632fc7eb66184cbd10ca6ef71232b195ff7f59 100644 (file)
@@ -117,8 +117,6 @@ void s3c_pm_save_core(void)
  * this.
  */
 
-#include <plat/regs-gpio.h>
-
 static void s3c64xx_cpu_suspend(void)
 {
        unsigned long tmp;
index 1debc1f9f987bd09cc96d0d2574493bd5adb9e73..febac1950d8ea658c5ba1321d56a000f01509972 100644 (file)
@@ -153,7 +153,7 @@ static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
        u32 div;
 
        if (parent < rate)
-               return rate;
+               return parent;
 
        div = (parent / rate) - 1;
        if (div > armclk_mask)
@@ -175,7 +175,7 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
        div = clk_get_rate(clk->parent) / rate;
 
        val = __raw_readl(S3C_CLK_DIV0);
-       val &= armclk_mask;
+       val &= ~armclk_mask;
        val |= (div - 1);
        __raw_writel(val, S3C_CLK_DIV0);
 
index d41200382208c6fc8918b178e991a2151ae42dd8..6d6b1a468eda765eb8425461398a5008db5f7e2e 100644 (file)
@@ -22,7 +22,6 @@
 #include <linux/sysdev.h>
 #include <linux/string.h>
 #include <linux/bitops.h>
-#include <linux/sysdev.h>
 #include <linux/irq.h>
 
 #include <mach/hardware.h>
index c244133c67a67bcdd1591b9049f7487e78974b22..cc466d039af6c8ec2a3984c2597dc6cceae2da67 100644 (file)
@@ -407,7 +407,8 @@ struct power_pmu mpc7450_pmu = {
 
 static int init_mpc7450_pmu(void)
 {
-       if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450"))
+       if (!cur_cpu_spec->oprofile_cpu_type ||
+           strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450"))
                return -ENODEV;
 
        return register_power_pmu(&mpc7450_pmu);
index db90b0c5c27bbc05f9d66dc8a70c18f108e9ecf3..3c90a3d9173e47a60109312be18603851e163c28 100644 (file)
@@ -606,7 +606,8 @@ static struct power_pmu power4_pmu = {
 
 static int init_power4_pmu(void)
 {
-       if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power4"))
+       if (!cur_cpu_spec->oprofile_cpu_type ||
+           strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power4"))
                return -ENODEV;
 
        return register_power_pmu(&power4_pmu);
index f4adca8e98a423a92941ad00c83ab6c174a7484e..31918af3e3553d551e9870fb2d4060727dab75f5 100644 (file)
@@ -678,8 +678,9 @@ static struct power_pmu power5p_pmu = {
 
 static int init_power5p_pmu(void)
 {
-       if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+")
-           && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5++"))
+       if (!cur_cpu_spec->oprofile_cpu_type ||
+           (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+")
+            && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5++")))
                return -ENODEV;
 
        return register_power_pmu(&power5p_pmu);
index 29b2c6c0e83a2a37b582fe1e98a986ff0daefaba..867f6f663963d411dfc654ddc72caf198d0ed5cb 100644 (file)
@@ -618,7 +618,8 @@ static struct power_pmu power5_pmu = {
 
 static int init_power5_pmu(void)
 {
-       if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5"))
+       if (!cur_cpu_spec->oprofile_cpu_type ||
+           strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5"))
                return -ENODEV;
 
        return register_power_pmu(&power5_pmu);
index 09ae5bf5bda78fb86b64b1d14d44f9722b63b9a6..fa21890531da732cf466e11869ff69d028188324 100644 (file)
@@ -537,7 +537,8 @@ static struct power_pmu power6_pmu = {
 
 static int init_power6_pmu(void)
 {
-       if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
+       if (!cur_cpu_spec->oprofile_cpu_type ||
+           strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
                return -ENODEV;
 
        return register_power_pmu(&power6_pmu);
index 5a9f5cbd40a48e9c19c4afaae64e86a57fd5c18d..388cf57ad827b8d187c49dc34eb0ec8deaf48db5 100644 (file)
@@ -366,7 +366,8 @@ static struct power_pmu power7_pmu = {
 
 static int init_power7_pmu(void)
 {
-       if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
+       if (!cur_cpu_spec->oprofile_cpu_type ||
+           strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
                return -ENODEV;
 
        return register_power_pmu(&power7_pmu);
index 833097ac45dc4aad00e7e3e8d43b060efccada77..75dccb71a04337fc3f26dd0902de37e279886651 100644 (file)
@@ -488,8 +488,9 @@ static struct power_pmu ppc970_pmu = {
 
 static int init_ppc970_pmu(void)
 {
-       if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970")
-           && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970MP"))
+       if (!cur_cpu_spec->oprofile_cpu_type ||
+           (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970")
+            && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970MP")))
                return -ENODEV;
 
        return register_power_pmu(&ppc970_pmu);
index 8d15314381e04640bbf227ff045b9d9a782f22cf..cae14c499511c6f5358170906764a95045ed4b39 100644 (file)
@@ -208,6 +208,9 @@ static noinline __init void detect_machine_type(void)
                machine_flags |= MACHINE_FLAG_KVM;
        else
                machine_flags |= MACHINE_FLAG_VM;
+
+       /* Store machine flags for setting up lowcore early */
+       S390_lowcore.machine_flags = machine_flags;
 }
 
 static __init void early_pgm_check_handler(void)
index 36678835034d9f49a748f448fd943073e9974564..0ef81d6776e97c934792027415267ad95d579136 100644 (file)
@@ -169,7 +169,7 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
                             unsigned long *reg)
 {
        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
-       struct kvm_s390_local_interrupt *li;
+       struct kvm_s390_local_interrupt *li = NULL;
        struct kvm_s390_interrupt_info *inti;
        int rc;
        u8 tmp;
@@ -189,9 +189,10 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
                return 2; /* busy */
 
        spin_lock(&fi->lock);
-       li = fi->local_int[cpu_addr];
+       if (cpu_addr < KVM_MAX_VCPUS)
+               li = fi->local_int[cpu_addr];
 
-       if ((cpu_addr >= KVM_MAX_VCPUS) || (li == NULL)) {
+       if (li == NULL) {
                rc = 1; /* incorrect state */
                *reg &= SIGP_STAT_INCORRECT_STATE;
                kfree(inti);
index 8c4783180bf653e9a1885b40896c711c074f78d9..50d1f782768cc99ffc1e3a844f74a4c7898fcfed 100644 (file)
@@ -1186,6 +1186,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        if (ret)
                goto out_iomapfree;
 
+       dev_priv->wq = create_workqueue("i915");
+       if (dev_priv->wq == NULL) {
+               DRM_ERROR("Failed to create our workqueue.\n");
+               ret = -ENOMEM;
+               goto out_iomapfree;
+       }
+
        /* enable GEM by default */
        dev_priv->has_gem = 1;
 
@@ -1211,7 +1218,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        if (!I915_NEED_GFX_HWS(dev)) {
                ret = i915_init_phys_hws(dev);
                if (ret != 0)
-                       goto out_iomapfree;
+                       goto out_workqueue_free;
        }
 
        i915_get_mem_freq(dev);
@@ -1245,7 +1252,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
                if (ret < 0) {
                        DRM_ERROR("failed to init modeset\n");
-                       goto out_rmmap;
+                       goto out_workqueue_free;
                }
        }
 
@@ -1256,6 +1263,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
        return 0;
 
+out_workqueue_free:
+       destroy_workqueue(dev_priv->wq);
 out_iomapfree:
        io_mapping_free(dev_priv->mm.gtt_mapping);
 out_rmmap:
@@ -1269,6 +1278,8 @@ int i915_driver_unload(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
 
+       destroy_workqueue(dev_priv->wq);
+
        io_mapping_free(dev_priv->mm.gtt_mapping);
        if (dev_priv->mm.gtt_mtrr >= 0) {
                mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
index d087528758856c78b5b8e6d6f4a1857dc5be20e4..7537f57d8a87399b43079c37adbb843970bd7b1d 100644 (file)
@@ -219,6 +219,7 @@ typedef struct drm_i915_private {
        unsigned int lvds_vbt:1;
        unsigned int int_crt_support:1;
        unsigned int lvds_use_ssc:1;
+       unsigned int edp_support:1;
        int lvds_ssc_freq;
 
        struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
@@ -229,6 +230,8 @@ typedef struct drm_i915_private {
 
        spinlock_t error_lock;
        struct drm_i915_error_state *first_error;
+       struct work_struct error_work;
+       struct workqueue_struct *wq;
 
        /* Register state */
        u8 saveLBB;
@@ -888,6 +891,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
                                                      IS_I915GM(dev)))
 #define SUPPORTS_INTEGRATED_HDMI(dev)  (IS_G4X(dev) || IS_IGDNG(dev))
 #define SUPPORTS_INTEGRATED_DP(dev)    (IS_G4X(dev) || IS_IGDNG(dev))
+#define SUPPORTS_EDP(dev)              (IS_IGDNG_M(dev))
 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
 /* dsparb controlled by hw only */
 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
index 5bf420378b6d547a8146535c36830d84dd7bc087..140bee142fc253186f80f2cdc8a4d339786efe20 100644 (file)
@@ -1570,7 +1570,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
        }
 
        if (was_empty && !dev_priv->mm.suspended)
-               schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
+               queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
        return seqno;
 }
 
@@ -1719,7 +1719,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
        i915_gem_retire_requests(dev);
        if (!dev_priv->mm.suspended &&
            !list_empty(&dev_priv->mm.request_list))
-               schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
+               queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
        mutex_unlock(&dev->struct_mutex);
 }
 
index 9a44bfcb81394c96a986b71e9b4da8ecb0ef7bee..cb3b97405fbfdd3735b91a9a60ec5108bc83c40b 100644 (file)
@@ -343,6 +343,8 @@ static int i915_error_state(struct seq_file *m, void *unused)
 
        error = dev_priv->first_error;
 
+       seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
+                  error->time.tv_usec);
        seq_printf(m, "EIR: 0x%08x\n", error->eir);
        seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);
        seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);
index 7ba23a69a0c0e39a983937a76d1178c6bea052ad..83aee80e77a6c188a8235337b7d9a1de0dfb0dfd 100644 (file)
@@ -290,6 +290,35 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
        return ret;
 }
 
+/**
+ * i915_error_work_func - do process context error handling work
+ * @work: work struct
+ *
+ * Fire an error uevent so userspace can see that a hang or error
+ * was detected.
+ */
+static void i915_error_work_func(struct work_struct *work)
+{
+       drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
+                                                   error_work);
+       struct drm_device *dev = dev_priv->dev;
+       char *event_string = "ERROR=1";
+       char *envp[] = { event_string, NULL };
+
+       DRM_DEBUG("generating error event\n");
+
+       kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, envp);
+}
+
+/**
+ * i915_capture_error_state - capture an error record for later analysis
+ * @dev: drm device
+ *
+ * Should be called when an error is detected (either a hang or an error
+ * interrupt) to capture error state from the time of the error.  Fills
+ * out a structure which becomes available in debugfs for user level tools
+ * to pick up.
+ */
 static void i915_capture_error_state(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -325,12 +354,137 @@ static void i915_capture_error_state(struct drm_device *dev)
                error->acthd = I915_READ(ACTHD_I965);
        }
 
+       do_gettimeofday(&error->time);
+
        dev_priv->first_error = error;
 
 out:
        spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 }
 
+/**
+ * i915_handle_error - handle an error interrupt
+ * @dev: drm device
+ *
+ * Do some basic checking of regsiter state at error interrupt time and
+ * dump it to the syslog.  Also call i915_capture_error_state() to make
+ * sure we get a record and make it available in debugfs.  Fire a uevent
+ * so userspace knows something bad happened (should trigger collection
+ * of a ring dump etc.).
+ */
+static void i915_handle_error(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 eir = I915_READ(EIR);
+       u32 pipea_stats = I915_READ(PIPEASTAT);
+       u32 pipeb_stats = I915_READ(PIPEBSTAT);
+
+       i915_capture_error_state(dev);
+
+       printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
+              eir);
+
+       if (IS_G4X(dev)) {
+               if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
+                       u32 ipeir = I915_READ(IPEIR_I965);
+
+                       printk(KERN_ERR "  IPEIR: 0x%08x\n",
+                              I915_READ(IPEIR_I965));
+                       printk(KERN_ERR "  IPEHR: 0x%08x\n",
+                              I915_READ(IPEHR_I965));
+                       printk(KERN_ERR "  INSTDONE: 0x%08x\n",
+                              I915_READ(INSTDONE_I965));
+                       printk(KERN_ERR "  INSTPS: 0x%08x\n",
+                              I915_READ(INSTPS));
+                       printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
+                              I915_READ(INSTDONE1));
+                       printk(KERN_ERR "  ACTHD: 0x%08x\n",
+                              I915_READ(ACTHD_I965));
+                       I915_WRITE(IPEIR_I965, ipeir);
+                       (void)I915_READ(IPEIR_I965);
+               }
+               if (eir & GM45_ERROR_PAGE_TABLE) {
+                       u32 pgtbl_err = I915_READ(PGTBL_ER);
+                       printk(KERN_ERR "page table error\n");
+                       printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
+                              pgtbl_err);
+                       I915_WRITE(PGTBL_ER, pgtbl_err);
+                       (void)I915_READ(PGTBL_ER);
+               }
+       }
+
+       if (IS_I9XX(dev)) {
+               if (eir & I915_ERROR_PAGE_TABLE) {
+                       u32 pgtbl_err = I915_READ(PGTBL_ER);
+                       printk(KERN_ERR "page table error\n");
+                       printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
+                              pgtbl_err);
+                       I915_WRITE(PGTBL_ER, pgtbl_err);
+                       (void)I915_READ(PGTBL_ER);
+               }
+       }
+
+       if (eir & I915_ERROR_MEMORY_REFRESH) {
+               printk(KERN_ERR "memory refresh error\n");
+               printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
+                      pipea_stats);
+               printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
+                      pipeb_stats);
+               /* pipestat has already been acked */
+       }
+       if (eir & I915_ERROR_INSTRUCTION) {
+               printk(KERN_ERR "instruction error\n");
+               printk(KERN_ERR "  INSTPM: 0x%08x\n",
+                      I915_READ(INSTPM));
+               if (!IS_I965G(dev)) {
+                       u32 ipeir = I915_READ(IPEIR);
+
+                       printk(KERN_ERR "  IPEIR: 0x%08x\n",
+                              I915_READ(IPEIR));
+                       printk(KERN_ERR "  IPEHR: 0x%08x\n",
+                              I915_READ(IPEHR));
+                       printk(KERN_ERR "  INSTDONE: 0x%08x\n",
+                              I915_READ(INSTDONE));
+                       printk(KERN_ERR "  ACTHD: 0x%08x\n",
+                              I915_READ(ACTHD));
+                       I915_WRITE(IPEIR, ipeir);
+                       (void)I915_READ(IPEIR);
+               } else {
+                       u32 ipeir = I915_READ(IPEIR_I965);
+
+                       printk(KERN_ERR "  IPEIR: 0x%08x\n",
+                              I915_READ(IPEIR_I965));
+                       printk(KERN_ERR "  IPEHR: 0x%08x\n",
+                              I915_READ(IPEHR_I965));
+                       printk(KERN_ERR "  INSTDONE: 0x%08x\n",
+                              I915_READ(INSTDONE_I965));
+                       printk(KERN_ERR "  INSTPS: 0x%08x\n",
+                              I915_READ(INSTPS));
+                       printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
+                              I915_READ(INSTDONE1));
+                       printk(KERN_ERR "  ACTHD: 0x%08x\n",
+                              I915_READ(ACTHD_I965));
+                       I915_WRITE(IPEIR_I965, ipeir);
+                       (void)I915_READ(IPEIR_I965);
+               }
+       }
+
+       I915_WRITE(EIR, eir);
+       (void)I915_READ(EIR);
+       eir = I915_READ(EIR);
+       if (eir) {
+               /*
+                * some errors might have become stuck,
+                * mask them.
+                */
+               DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
+               I915_WRITE(EMR, I915_READ(EMR) | eir);
+               I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
+       }
+
+       queue_work(dev_priv->wq, &dev_priv->error_work);
+}
+
 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 {
        struct drm_device *dev = (struct drm_device *) arg;
@@ -372,6 +526,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                pipea_stats = I915_READ(PIPEASTAT);
                pipeb_stats = I915_READ(PIPEBSTAT);
 
+               if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+                       i915_handle_error(dev);
+
                /*
                 * Clear the PIPE(A|B)STAT regs before the IIR
                 */
@@ -403,86 +560,13 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                        DRM_DEBUG("hotplug event received, stat 0x%08x\n",
                                  hotplug_status);
                        if (hotplug_status & dev_priv->hotplug_supported_mask)
-                               schedule_work(&dev_priv->hotplug_work);
+                               queue_work(dev_priv->wq,
+                                          &dev_priv->hotplug_work);
 
                        I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
                        I915_READ(PORT_HOTPLUG_STAT);
                }
 
-               if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) {
-                       u32 eir = I915_READ(EIR);
-
-                       i915_capture_error_state(dev);
-
-                       printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
-                              eir);
-                       if (eir & I915_ERROR_PAGE_TABLE) {
-                               u32 pgtbl_err = I915_READ(PGTBL_ER);
-                               printk(KERN_ERR "page table error\n");
-                               printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
-                                      pgtbl_err);
-                               I915_WRITE(PGTBL_ER, pgtbl_err);
-                               (void)I915_READ(PGTBL_ER);
-                       }
-                       if (eir & I915_ERROR_MEMORY_REFRESH) {
-                               printk(KERN_ERR "memory refresh error\n");
-                               printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
-                                      pipea_stats);
-                               printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
-                                      pipeb_stats);
-                               /* pipestat has already been acked */
-                       }
-                       if (eir & I915_ERROR_INSTRUCTION) {
-                               printk(KERN_ERR "instruction error\n");
-                               printk(KERN_ERR "  INSTPM: 0x%08x\n",
-                                      I915_READ(INSTPM));
-                               if (!IS_I965G(dev)) {
-                                       u32 ipeir = I915_READ(IPEIR);
-
-                                       printk(KERN_ERR "  IPEIR: 0x%08x\n",
-                                              I915_READ(IPEIR));
-                                       printk(KERN_ERR "  IPEHR: 0x%08x\n",
-                                                  I915_READ(IPEHR));
-                                       printk(KERN_ERR "  INSTDONE: 0x%08x\n",
-                                                  I915_READ(INSTDONE));
-                                       printk(KERN_ERR "  ACTHD: 0x%08x\n",
-                                                  I915_READ(ACTHD));
-                                       I915_WRITE(IPEIR, ipeir);
-                                       (void)I915_READ(IPEIR);
-                               } else {
-                                       u32 ipeir = I915_READ(IPEIR_I965);
-
-                                       printk(KERN_ERR "  IPEIR: 0x%08x\n",
-                                              I915_READ(IPEIR_I965));
-                                       printk(KERN_ERR "  IPEHR: 0x%08x\n",
-                                              I915_READ(IPEHR_I965));
-                                       printk(KERN_ERR "  INSTDONE: 0x%08x\n",
-                                              I915_READ(INSTDONE_I965));
-                                       printk(KERN_ERR "  INSTPS: 0x%08x\n",
-                                              I915_READ(INSTPS));
-                                       printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
-                                              I915_READ(INSTDONE1));
-                                       printk(KERN_ERR "  ACTHD: 0x%08x\n",
-                                              I915_READ(ACTHD_I965));
-                                       I915_WRITE(IPEIR_I965, ipeir);
-                                       (void)I915_READ(IPEIR_I965);
-                               }
-                       }
-
-                       I915_WRITE(EIR, eir);
-                       (void)I915_READ(EIR);
-                       eir = I915_READ(EIR);
-                       if (eir) {
-                               /*
-                                * some errors might have become stuck,
-                                * mask them.
-                                */
-                               DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
-                               I915_WRITE(EMR, I915_READ(EMR) | eir);
-                               I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
-                       }
-               }
-
                I915_WRITE(IIR, iir);
                new_iir = I915_READ(IIR); /* Flush posted writes */
 
@@ -830,6 +914,7 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
        atomic_set(&dev_priv->irq_received, 0);
 
        INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
+       INIT_WORK(&dev_priv->error_work, i915_error_work_func);
 
        if (IS_IGDNG(dev)) {
                igdng_irq_preinstall(dev);
index 6c08584840944d6e711386ba8b4352b8c9dcdce3..2955083aa4719edc6cccdfdacb9b6c5487baf190 100644 (file)
 #define TV_V_CHROMA_42         0x684a8
 
 /* Display Port */
+#define DP_A                           0x64000 /* eDP */
 #define DP_B                           0x64100
 #define DP_C                           0x64200
 #define DP_D                           0x64300
 /* Mystic DPCD version 1.1 special mode */
 #define   DP_ENHANCED_FRAMING          (1 << 18)
 
+/* eDP */
+#define   DP_PLL_FREQ_270MHZ           (0 << 16)
+#define   DP_PLL_FREQ_160MHZ           (1 << 16)
+#define   DP_PLL_FREQ_MASK             (3 << 16)
+
 /** locked once port is enabled */
 #define   DP_PORT_REVERSAL             (1 << 15)
 
+/* eDP */
+#define   DP_PLL_ENABLE                        (1 << 14)
+
 /** sends the clock on lane 15 of the PEG for debug */
 #define   DP_CLOCK_OUTPUT_ENABLE       (1 << 13)
 
 #define   DP_SCRAMBLING_DISABLE                (1 << 12)
+#define   DP_SCRAMBLING_DISABLE_IGDNG  (1 << 7)
 
 /** limit RGB values to avoid confusing TVs */
 #define   DP_COLOR_RANGE_16_235                (1 << 8)
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
+#define DPA_AUX_CH_CTL                 0x64010
+#define DPA_AUX_CH_DATA1               0x64014
+#define DPA_AUX_CH_DATA2               0x64018
+#define DPA_AUX_CH_DATA3               0x6401c
+#define DPA_AUX_CH_DATA4               0x64020
+#define DPA_AUX_CH_DATA5               0x64024
+
 #define DPB_AUX_CH_CTL                 0x64110
 #define DPB_AUX_CH_DATA1               0x64114
 #define DPB_AUX_CH_DATA2               0x64118
 #define I830_FIFO_LINE_SIZE    32
 #define I945_FIFO_SIZE         127 /* 945 & 965 */
 #define I915_FIFO_SIZE         95
-#define I855GM_FIFO_SIZE       255
+#define I855GM_FIFO_SIZE       127 /* In cachelines */
 #define I830_FIFO_SIZE         95
 #define I915_MAX_WM            0x3f
 
 #define PFA_CTL_1               0x68080
 #define PFB_CTL_1               0x68880
 #define  PF_ENABLE              (1<<31)
+#define PFA_WIN_SZ             0x68074
+#define PFB_WIN_SZ             0x68874
 
 /* legacy palette */
 #define LGC_PALETTE_A           0x4a000
 #define PCH_PP_OFF_DELAYS      0xc720c
 #define PCH_PP_DIVISOR         0xc7210
 
+#define PCH_DP_B               0xe4100
+#define PCH_DPB_AUX_CH_CTL     0xe4110
+#define PCH_DPB_AUX_CH_DATA1   0xe4114
+#define PCH_DPB_AUX_CH_DATA2   0xe4118
+#define PCH_DPB_AUX_CH_DATA3   0xe411c
+#define PCH_DPB_AUX_CH_DATA4   0xe4120
+#define PCH_DPB_AUX_CH_DATA5   0xe4124
+
+#define PCH_DP_C               0xe4200
+#define PCH_DPC_AUX_CH_CTL     0xe4210
+#define PCH_DPC_AUX_CH_DATA1   0xe4214
+#define PCH_DPC_AUX_CH_DATA2   0xe4218
+#define PCH_DPC_AUX_CH_DATA3   0xe421c
+#define PCH_DPC_AUX_CH_DATA4   0xe4220
+#define PCH_DPC_AUX_CH_DATA5   0xe4224
+
+#define PCH_DP_D               0xe4300
+#define PCH_DPD_AUX_CH_CTL     0xe4310
+#define PCH_DPD_AUX_CH_DATA1   0xe4314
+#define PCH_DPD_AUX_CH_DATA2   0xe4318
+#define PCH_DPD_AUX_CH_DATA3   0xe431c
+#define PCH_DPD_AUX_CH_DATA4   0xe4320
+#define PCH_DPD_AUX_CH_DATA5   0xe4324
+
 #endif /* _I915_REG_H_ */
index 9e1d16e5c3ead86f0e805f9d72a95eb7be8e293e..1d04e1904ac69c7be338897a71d25900e44927d1 100644 (file)
@@ -598,7 +598,7 @@ int i915_restore_state(struct drm_device *dev)
 
        for (i = 0; i < 16; i++) {
                I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
-               I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
+               I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
        }
        for (i = 0; i < 3; i++)
                I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
index 7cc447191028d70f11b6ea5c0082492d5d0247df..300aee3296c2435545702030d6e66405759e5963 100644 (file)
@@ -97,14 +97,13 @@ static void
 parse_lfp_panel_data(struct drm_i915_private *dev_priv,
                            struct bdb_header *bdb)
 {
-       struct drm_device *dev = dev_priv->dev;
        struct bdb_lvds_options *lvds_options;
        struct bdb_lvds_lfp_data *lvds_lfp_data;
        struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
        struct bdb_lvds_lfp_data_entry *entry;
        struct lvds_dvo_timing *dvo_timing;
        struct drm_display_mode *panel_fixed_mode;
-       int lfp_data_size;
+       int lfp_data_size, dvo_timing_offset;
 
        /* Defaults if we can't find VBT info */
        dev_priv->lvds_dither = 0;
@@ -133,14 +132,16 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
        entry = (struct bdb_lvds_lfp_data_entry *)
                ((uint8_t *)lvds_lfp_data->data + (lfp_data_size *
                                                   lvds_options->panel_type));
+       dvo_timing_offset = lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
+               lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
 
-       /* On IGDNG mobile, LVDS data block removes panel fitting registers.
-          So dec 2 dword from dvo_timing offset */
-       if (IS_IGDNG(dev))
-               dvo_timing = (struct lvds_dvo_timing *)
-                                       ((u8 *)&entry->dvo_timing - 8);
-       else
-               dvo_timing = &entry->dvo_timing;
+       /*
+        * the size of fp_timing varies on the different platform.
+        * So calculate the DVO timing relative offset in LVDS data
+        * entry to get the DVO timing entry
+        */
+       dvo_timing = (struct lvds_dvo_timing *)
+                       ((unsigned char *)entry + dvo_timing_offset);
 
        panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
 
@@ -295,6 +296,25 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
        }
        return;
 }
+
+static void
+parse_driver_features(struct drm_i915_private *dev_priv,
+                      struct bdb_header *bdb)
+{
+       struct drm_device *dev = dev_priv->dev;
+       struct bdb_driver_features *driver;
+
+       /* set default for chips without eDP */
+       if (!SUPPORTS_EDP(dev)) {
+               dev_priv->edp_support = 0;
+               return;
+       }
+
+       driver = find_section(bdb, BDB_DRIVER_FEATURES);
+       if (driver && driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
+               dev_priv->edp_support = 1;
+}
+
 /**
  * intel_init_bios - initialize VBIOS settings & find VBT
  * @dev: DRM device
@@ -345,6 +365,8 @@ intel_init_bios(struct drm_device *dev)
        parse_lfp_panel_data(dev_priv, bdb);
        parse_sdvo_panel_data(dev_priv, bdb);
        parse_sdvo_device_mapping(dev_priv, bdb);
+       parse_driver_features(dev_priv, bdb);
+
        pci_unmap_rom(pdev, bios);
 
        return 0;
index fe72e1c225d8ab1085a752f3ccbf6d298c44fca3..0f8e5f69ac7a315eb8eb8c4b9f377a87cc8e5f6c 100644 (file)
@@ -381,6 +381,51 @@ struct bdb_sdvo_lvds_options {
 } __attribute__((packed));
 
 
+#define BDB_DRIVER_FEATURE_NO_LVDS             0
+#define BDB_DRIVER_FEATURE_INT_LVDS            1
+#define BDB_DRIVER_FEATURE_SDVO_LVDS           2
+#define BDB_DRIVER_FEATURE_EDP                 3
+
+struct bdb_driver_features {
+       u8 boot_dev_algorithm:1;
+       u8 block_display_switch:1;
+       u8 allow_display_switch:1;
+       u8 hotplug_dvo:1;
+       u8 dual_view_zoom:1;
+       u8 int15h_hook:1;
+       u8 sprite_in_clone:1;
+       u8 primary_lfp_id:1;
+
+       u16 boot_mode_x;
+       u16 boot_mode_y;
+       u8 boot_mode_bpp;
+       u8 boot_mode_refresh;
+
+       u16 enable_lfp_primary:1;
+       u16 selective_mode_pruning:1;
+       u16 dual_frequency:1;
+       u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
+       u16 nt_clone_support:1;
+       u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
+       u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
+       u16 cui_aspect_scaling:1;
+       u16 preserve_aspect_ratio:1;
+       u16 sdvo_device_power_down:1;
+       u16 crt_hotplug:1;
+       u16 lvds_config:2;
+       u16 tv_hotplug:1;
+       u16 hdmi_config:2;
+
+       u8 static_display:1;
+       u8 reserved2:7;
+       u16 legacy_crt_max_x;
+       u16 legacy_crt_max_y;
+       u8 legacy_crt_max_refresh;
+
+       u8 hdmi_termination;
+       u8 custom_vbt_version;
+} __attribute__((packed));
+
 bool intel_init_bios(struct drm_device *dev);
 
 /*
index d6a1a6e5539a58da94b57ad67e3db54486963a5a..4cf8e2e88a40eb56aae2052fedab7af3c03b45c4 100644 (file)
@@ -156,6 +156,9 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
 
        temp = adpa = I915_READ(PCH_ADPA);
 
+       adpa &= ~ADPA_DAC_ENABLE;
+       I915_WRITE(PCH_ADPA, adpa);
+
        adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 
        adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
@@ -169,13 +172,14 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
        DRM_DEBUG("pch crt adpa 0x%x", adpa);
        I915_WRITE(PCH_ADPA, adpa);
 
-       /* This might not be needed as not specified in spec...*/
-       udelay(1000);
+       while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
+               ;
 
        /* Check the status to see if both blue and green are on now */
        adpa = I915_READ(PCH_ADPA);
-       if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) ==
-                       ADPA_CRT_HOTPLUG_MONITOR_COLOR)
+       adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
+       if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) ||
+               (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
                ret = true;
        else
                ret = false;
index 508838ee31e023f2ac1038236299b7ea7eb4e38b..d6fce2133413e5431bf6abda64f9e260cfca8d77 100644 (file)
@@ -34,6 +34,8 @@
 
 #include "drm_crtc_helper.h"
 
+#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
+
 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
 static void intel_update_watermarks(struct drm_device *dev);
 
@@ -88,7 +90,7 @@ struct intel_limit {
 #define I8XX_P2_SLOW                 4
 #define I8XX_P2_FAST                 2
 #define I8XX_P2_LVDS_SLOW            14
-#define I8XX_P2_LVDS_FAST            14 /* No fast option */
+#define I8XX_P2_LVDS_FAST            7
 #define I8XX_P2_SLOW_LIMIT      165000
 
 #define I9XX_DOT_MIN             20000
@@ -268,6 +270,9 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
                      int target, int refclk, intel_clock_t *best_clock);
+static bool
+intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
+                     int target, int refclk, intel_clock_t *best_clock);
 
 static const intel_limit_t intel_limits_i8xx_dvo = {
         .dot = { .min = I8XX_DOT_MIN,          .max = I8XX_DOT_MAX },
@@ -598,6 +603,23 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
     return false;
 }
 
+struct drm_connector *
+intel_pipe_get_output (struct drm_crtc *crtc)
+{
+    struct drm_device *dev = crtc->dev;
+    struct drm_mode_config *mode_config = &dev->mode_config;
+    struct drm_connector *l_entry, *ret = NULL;
+
+    list_for_each_entry(l_entry, &mode_config->connector_list, head) {
+           if (l_entry->encoder &&
+               l_entry->encoder->crtc == crtc) {
+                   ret = l_entry;
+                   break;
+           }
+    }
+    return ret;
+}
+
 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 /**
  * Returns whether the given set of divisors are valid for a given refclk with
@@ -645,7 +667,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
        int err = target;
 
        if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
-           (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
+           (I915_READ(LVDS)) != 0) {
                /*
                 * For LVDS, if the panel is on, just rely on its current
                 * settings for dual-channel.  We haven't figured out how to
@@ -751,6 +773,30 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
        return found;
 }
 
+static bool
+intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
+                     int target, int refclk, intel_clock_t *best_clock)
+{
+       struct drm_device *dev = crtc->dev;
+       intel_clock_t clock;
+       if (target < 200000) {
+               clock.n = 1;
+               clock.p1 = 2;
+               clock.p2 = 10;
+               clock.m1 = 12;
+               clock.m2 = 9;
+       } else {
+               clock.n = 2;
+               clock.p1 = 1;
+               clock.p2 = 10;
+               clock.m1 = 14;
+               clock.m2 = 8;
+       }
+       intel_clock(dev, refclk, &clock);
+       memcpy(best_clock, &clock, sizeof(intel_clock_t));
+       return true;
+}
+
 static bool
 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                        int target, int refclk, intel_clock_t *best_clock)
@@ -763,6 +809,14 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
        int err_most = 47;
        found = false;
 
+       /* eDP has only 2 clock choice, no n/m/p setting */
+       if (HAS_eDP)
+               return true;
+
+       if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+               return intel_find_pll_igdng_dp(limit, crtc, target,
+                                              refclk, best_clock);
+
        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
                    LVDS_CLKB_POWER_UP)
@@ -998,6 +1052,90 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
        return 0;
 }
 
+/* Disable the VGA plane that we never use */
+static void i915_disable_vga (struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u8 sr1;
+       u32 vga_reg;
+
+       if (IS_IGDNG(dev))
+               vga_reg = CPU_VGACNTRL;
+       else
+               vga_reg = VGACNTRL;
+
+       if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
+               return;
+
+       I915_WRITE8(VGA_SR_INDEX, 1);
+       sr1 = I915_READ8(VGA_SR_DATA);
+       I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
+       udelay(100);
+
+       I915_WRITE(vga_reg, VGA_DISP_DISABLE);
+}
+
+static void igdng_disable_pll_edp (struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 dpa_ctl;
+
+       DRM_DEBUG("\n");
+       dpa_ctl = I915_READ(DP_A);
+       dpa_ctl &= ~DP_PLL_ENABLE;
+       I915_WRITE(DP_A, dpa_ctl);
+}
+
+static void igdng_enable_pll_edp (struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 dpa_ctl;
+
+       dpa_ctl = I915_READ(DP_A);
+       dpa_ctl |= DP_PLL_ENABLE;
+       I915_WRITE(DP_A, dpa_ctl);
+       udelay(200);
+}
+
+
+static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 dpa_ctl;
+
+       DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
+       dpa_ctl = I915_READ(DP_A);
+       dpa_ctl &= ~DP_PLL_FREQ_MASK;
+
+       if (clock < 200000) {
+               u32 temp;
+               dpa_ctl |= DP_PLL_FREQ_160MHZ;
+               /* workaround for 160Mhz:
+                  1) program 0x4600c bits 15:0 = 0x8124
+                  2) program 0x46010 bit 0 = 1
+                  3) program 0x46034 bit 24 = 1
+                  4) program 0x64000 bit 14 = 1
+                  */
+               temp = I915_READ(0x4600c);
+               temp &= 0xffff0000;
+               I915_WRITE(0x4600c, temp | 0x8124);
+
+               temp = I915_READ(0x46010);
+               I915_WRITE(0x46010, temp | 1);
+
+               temp = I915_READ(0x46034);
+               I915_WRITE(0x46034, temp | (1 << 24));
+       } else {
+               dpa_ctl |= DP_PLL_FREQ_270MHZ;
+       }
+       I915_WRITE(DP_A, dpa_ctl);
+
+       udelay(500);
+}
+
 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 {
        struct drm_device *dev = crtc->dev;
@@ -1015,6 +1153,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
        int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
        int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
        int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
+       int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
        int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
        int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
        int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1028,7 +1167,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
        int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
        int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
        u32 temp;
-       int tries = 5, j;
+       int tries = 5, j, n;
 
        /* XXX: When our outputs are all unaware of DPMS modes other than off
         * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -1038,27 +1177,32 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
                DRM_DEBUG("crtc %d dpms on\n", pipe);
-               /* enable PCH DPLL */
-               temp = I915_READ(pch_dpll_reg);
-               if ((temp & DPLL_VCO_ENABLE) == 0) {
-                       I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
-                       I915_READ(pch_dpll_reg);
-               }
-
-               /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
-               temp = I915_READ(fdi_rx_reg);
-               I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
-                               FDI_SEL_PCDCLK |
-                               FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
-               I915_READ(fdi_rx_reg);
-               udelay(200);
+               if (HAS_eDP) {
+                       /* enable eDP PLL */
+                       igdng_enable_pll_edp(crtc);
+               } else {
+                       /* enable PCH DPLL */
+                       temp = I915_READ(pch_dpll_reg);
+                       if ((temp & DPLL_VCO_ENABLE) == 0) {
+                               I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
+                               I915_READ(pch_dpll_reg);
+                       }
 
-               /* Enable CPU FDI TX PLL, always on for IGDNG */
-               temp = I915_READ(fdi_tx_reg);
-               if ((temp & FDI_TX_PLL_ENABLE) == 0) {
-                       I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
-                       I915_READ(fdi_tx_reg);
-                       udelay(100);
+                       /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
+                       temp = I915_READ(fdi_rx_reg);
+                       I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
+                                       FDI_SEL_PCDCLK |
+                                       FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
+                       I915_READ(fdi_rx_reg);
+                       udelay(200);
+
+                       /* Enable CPU FDI TX PLL, always on for IGDNG */
+                       temp = I915_READ(fdi_tx_reg);
+                       if ((temp & FDI_TX_PLL_ENABLE) == 0) {
+                               I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
+                               I915_READ(fdi_tx_reg);
+                               udelay(100);
+                       }
                }
 
                /* Enable CPU pipe */
@@ -1077,122 +1221,126 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                        I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
                }
 
-               /* enable CPU FDI TX and PCH FDI RX */
-               temp = I915_READ(fdi_tx_reg);
-               temp |= FDI_TX_ENABLE;
-               temp |= FDI_DP_PORT_WIDTH_X4; /* default */
-               temp &= ~FDI_LINK_TRAIN_NONE;
-               temp |= FDI_LINK_TRAIN_PATTERN_1;
-               I915_WRITE(fdi_tx_reg, temp);
-               I915_READ(fdi_tx_reg);
+               if (!HAS_eDP) {
+                       /* enable CPU FDI TX and PCH FDI RX */
+                       temp = I915_READ(fdi_tx_reg);
+                       temp |= FDI_TX_ENABLE;
+                       temp |= FDI_DP_PORT_WIDTH_X4; /* default */
+                       temp &= ~FDI_LINK_TRAIN_NONE;
+                       temp |= FDI_LINK_TRAIN_PATTERN_1;
+                       I915_WRITE(fdi_tx_reg, temp);
+                       I915_READ(fdi_tx_reg);
 
-               temp = I915_READ(fdi_rx_reg);
-               temp &= ~FDI_LINK_TRAIN_NONE;
-               temp |= FDI_LINK_TRAIN_PATTERN_1;
-               I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
-               I915_READ(fdi_rx_reg);
+                       temp = I915_READ(fdi_rx_reg);
+                       temp &= ~FDI_LINK_TRAIN_NONE;
+                       temp |= FDI_LINK_TRAIN_PATTERN_1;
+                       I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
+                       I915_READ(fdi_rx_reg);
 
-               udelay(150);
+                       udelay(150);
 
-               /* Train FDI. */
-               /* umask FDI RX Interrupt symbol_lock and bit_lock bit
-                  for train result */
-               temp = I915_READ(fdi_rx_imr_reg);
-               temp &= ~FDI_RX_SYMBOL_LOCK;
-               temp &= ~FDI_RX_BIT_LOCK;
-               I915_WRITE(fdi_rx_imr_reg, temp);
-               I915_READ(fdi_rx_imr_reg);
-               udelay(150);
+                       /* Train FDI. */
+                       /* umask FDI RX Interrupt symbol_lock and bit_lock bit
+                          for train result */
+                       temp = I915_READ(fdi_rx_imr_reg);
+                       temp &= ~FDI_RX_SYMBOL_LOCK;
+                       temp &= ~FDI_RX_BIT_LOCK;
+                       I915_WRITE(fdi_rx_imr_reg, temp);
+                       I915_READ(fdi_rx_imr_reg);
+                       udelay(150);
 
-               temp = I915_READ(fdi_rx_iir_reg);
-               DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
+                       temp = I915_READ(fdi_rx_iir_reg);
+                       DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
 
-               if ((temp & FDI_RX_BIT_LOCK) == 0) {
-                       for (j = 0; j < tries; j++) {
-                               temp = I915_READ(fdi_rx_iir_reg);
-                               DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
-                               if (temp & FDI_RX_BIT_LOCK)
-                                       break;
-                               udelay(200);
-                       }
-                       if (j != tries)
+                       if ((temp & FDI_RX_BIT_LOCK) == 0) {
+                               for (j = 0; j < tries; j++) {
+                                       temp = I915_READ(fdi_rx_iir_reg);
+                                       DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
+                                       if (temp & FDI_RX_BIT_LOCK)
+                                               break;
+                                       udelay(200);
+                               }
+                               if (j != tries)
+                                       I915_WRITE(fdi_rx_iir_reg,
+                                                       temp | FDI_RX_BIT_LOCK);
+                               else
+                                       DRM_DEBUG("train 1 fail\n");
+                       } else {
                                I915_WRITE(fdi_rx_iir_reg,
                                                temp | FDI_RX_BIT_LOCK);
-                       else
-                               DRM_DEBUG("train 1 fail\n");
-               } else {
-                       I915_WRITE(fdi_rx_iir_reg,
-                                       temp | FDI_RX_BIT_LOCK);
-                       DRM_DEBUG("train 1 ok 2!\n");
-               }
-               temp = I915_READ(fdi_tx_reg);
-               temp &= ~FDI_LINK_TRAIN_NONE;
-               temp |= FDI_LINK_TRAIN_PATTERN_2;
-               I915_WRITE(fdi_tx_reg, temp);
-
-               temp = I915_READ(fdi_rx_reg);
-               temp &= ~FDI_LINK_TRAIN_NONE;
-               temp |= FDI_LINK_TRAIN_PATTERN_2;
-               I915_WRITE(fdi_rx_reg, temp);
+                               DRM_DEBUG("train 1 ok 2!\n");
+                       }
+                       temp = I915_READ(fdi_tx_reg);
+                       temp &= ~FDI_LINK_TRAIN_NONE;
+                       temp |= FDI_LINK_TRAIN_PATTERN_2;
+                       I915_WRITE(fdi_tx_reg, temp);
+
+                       temp = I915_READ(fdi_rx_reg);
+                       temp &= ~FDI_LINK_TRAIN_NONE;
+                       temp |= FDI_LINK_TRAIN_PATTERN_2;
+                       I915_WRITE(fdi_rx_reg, temp);
 
-               udelay(150);
+                       udelay(150);
 
-               temp = I915_READ(fdi_rx_iir_reg);
-               DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
+                       temp = I915_READ(fdi_rx_iir_reg);
+                       DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
 
-               if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
-                       for (j = 0; j < tries; j++) {
-                               temp = I915_READ(fdi_rx_iir_reg);
-                               DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
-                               if (temp & FDI_RX_SYMBOL_LOCK)
-                                       break;
-                               udelay(200);
-                       }
-                       if (j != tries) {
+                       if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
+                               for (j = 0; j < tries; j++) {
+                                       temp = I915_READ(fdi_rx_iir_reg);
+                                       DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
+                                       if (temp & FDI_RX_SYMBOL_LOCK)
+                                               break;
+                                       udelay(200);
+                               }
+                               if (j != tries) {
+                                       I915_WRITE(fdi_rx_iir_reg,
+                                                       temp | FDI_RX_SYMBOL_LOCK);
+                                       DRM_DEBUG("train 2 ok 1!\n");
+                               } else
+                                       DRM_DEBUG("train 2 fail\n");
+                       } else {
                                I915_WRITE(fdi_rx_iir_reg,
                                                temp | FDI_RX_SYMBOL_LOCK);
-                               DRM_DEBUG("train 2 ok 1!\n");
-                       } else
-                               DRM_DEBUG("train 2 fail\n");
-               } else {
-                       I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
-                       DRM_DEBUG("train 2 ok 2!\n");
-               }
-               DRM_DEBUG("train done\n");
+                               DRM_DEBUG("train 2 ok 2!\n");
+                       }
+                       DRM_DEBUG("train done\n");
 
-               /* set transcoder timing */
-               I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
-               I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
-               I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
+                       /* set transcoder timing */
+                       I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
+                       I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
+                       I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
 
-               I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
-               I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
-               I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
+                       I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
+                       I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
+                       I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
 
-               /* enable PCH transcoder */
-               temp = I915_READ(transconf_reg);
-               I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
-               I915_READ(transconf_reg);
+                       /* enable PCH transcoder */
+                       temp = I915_READ(transconf_reg);
+                       I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
+                       I915_READ(transconf_reg);
 
-               while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
-                       ;
+                       while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
+                               ;
 
-               /* enable normal */
+                       /* enable normal */
 
-               temp = I915_READ(fdi_tx_reg);
-               temp &= ~FDI_LINK_TRAIN_NONE;
-               I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
-                               FDI_TX_ENHANCE_FRAME_ENABLE);
-               I915_READ(fdi_tx_reg);
+                       temp = I915_READ(fdi_tx_reg);
+                       temp &= ~FDI_LINK_TRAIN_NONE;
+                       I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
+                                       FDI_TX_ENHANCE_FRAME_ENABLE);
+                       I915_READ(fdi_tx_reg);
 
-               temp = I915_READ(fdi_rx_reg);
-               temp &= ~FDI_LINK_TRAIN_NONE;
-               I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
-                               FDI_RX_ENHANCE_FRAME_ENABLE);
-               I915_READ(fdi_rx_reg);
+                       temp = I915_READ(fdi_rx_reg);
+                       temp &= ~FDI_LINK_TRAIN_NONE;
+                       I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
+                                       FDI_RX_ENHANCE_FRAME_ENABLE);
+                       I915_READ(fdi_rx_reg);
 
-               /* wait one idle pattern time */
-               udelay(100);
+                       /* wait one idle pattern time */
+                       udelay(100);
+
+               }
 
                intel_crtc_load_lut(crtc);
 
@@ -1200,8 +1348,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
        case DRM_MODE_DPMS_OFF:
                DRM_DEBUG("crtc %d dpms off\n", pipe);
 
-               /* Disable the VGA plane that we never use */
-               I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
+               i915_disable_vga(dev);
 
                /* Disable display plane */
                temp = I915_READ(dspcntr_reg);
@@ -1217,17 +1364,23 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                if ((temp & PIPEACONF_ENABLE) != 0) {
                        I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
                        I915_READ(pipeconf_reg);
+                       n = 0;
                        /* wait for cpu pipe off, pipe state */
-                       while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
-                               ;
+                       while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
+                               n++;
+                               if (n < 60) {
+                                       udelay(500);
+                                       continue;
+                               } else {
+                                       DRM_DEBUG("pipe %d off delay\n", pipe);
+                                       break;
+                               }
+                       }
                } else
                        DRM_DEBUG("crtc %d is disabled\n", pipe);
 
-               /* IGDNG-A : disable cpu panel fitter ? */
-               temp = I915_READ(pf_ctl_reg);
-               if ((temp & PF_ENABLE) != 0) {
-                       I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
-                       I915_READ(pf_ctl_reg);
+               if (HAS_eDP) {
+                       igdng_disable_pll_edp(crtc);
                }
 
                /* disable CPU FDI tx and PCH FDI rx */
@@ -1239,6 +1392,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
                I915_READ(fdi_rx_reg);
 
+               udelay(100);
+
                /* still set train pattern 1 */
                temp = I915_READ(fdi_tx_reg);
                temp &= ~FDI_LINK_TRAIN_NONE;
@@ -1250,14 +1405,25 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                temp |= FDI_LINK_TRAIN_PATTERN_1;
                I915_WRITE(fdi_rx_reg, temp);
 
+               udelay(100);
+
                /* disable PCH transcoder */
                temp = I915_READ(transconf_reg);
                if ((temp & TRANS_ENABLE) != 0) {
                        I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
                        I915_READ(transconf_reg);
+                       n = 0;
                        /* wait for PCH transcoder off, transcoder state */
-                       while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
-                               ;
+                       while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
+                               n++;
+                               if (n < 60) {
+                                       udelay(500);
+                                       continue;
+                               } else {
+                                       DRM_DEBUG("transcoder %d off delay\n", pipe);
+                                       break;
+                               }
+                       }
                }
 
                /* disable PCH DPLL */
@@ -1275,6 +1441,22 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                        I915_READ(fdi_rx_reg);
                }
 
+               /* Disable CPU FDI TX PLL */
+               temp = I915_READ(fdi_tx_reg);
+               if ((temp & FDI_TX_PLL_ENABLE) != 0) {
+                       I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
+                       I915_READ(fdi_tx_reg);
+                       udelay(100);
+               }
+
+               /* Disable PF */
+               temp = I915_READ(pf_ctl_reg);
+               if ((temp & PF_ENABLE) != 0) {
+                       I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
+                       I915_READ(pf_ctl_reg);
+               }
+               I915_WRITE(pf_win_size, 0);
+
                /* Wait for the clocks to turn off. */
                udelay(150);
                break;
@@ -1342,7 +1524,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                //intel_crtc_dpms_video(crtc, FALSE); TODO
 
                /* Disable the VGA plane that we never use */
-               I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
+               i915_disable_vga(dev);
 
                /* Disable display plane */
                temp = I915_READ(dspcntr_reg);
@@ -1623,48 +1805,72 @@ static struct intel_watermark_params igd_cursor_hplloff_wm = {
        IGD_FIFO_LINE_SIZE
 };
 static struct intel_watermark_params i945_wm_info = {
-       I915_FIFO_LINE_SIZE,
+       I945_FIFO_SIZE,
        I915_MAX_WM,
        1,
-       0,
-       IGD_FIFO_LINE_SIZE
+       2,
+       I915_FIFO_LINE_SIZE
 };
 static struct intel_watermark_params i915_wm_info = {
-       I945_FIFO_SIZE,
+       I915_FIFO_SIZE,
        I915_MAX_WM,
        1,
-       0,
+       2,
        I915_FIFO_LINE_SIZE
 };
 static struct intel_watermark_params i855_wm_info = {
        I855GM_FIFO_SIZE,
        I915_MAX_WM,
        1,
-       0,
+       2,
        I830_FIFO_LINE_SIZE
 };
 static struct intel_watermark_params i830_wm_info = {
        I830_FIFO_SIZE,
        I915_MAX_WM,
        1,
-       0,
+       2,
        I830_FIFO_LINE_SIZE
 };
 
+/**
+ * intel_calculate_wm - calculate watermark level
+ * @clock_in_khz: pixel clock
+ * @wm: chip FIFO params
+ * @pixel_size: display pixel size
+ * @latency_ns: memory latency for the platform
+ *
+ * Calculate the watermark level (the level at which the display plane will
+ * start fetching from memory again).  Each chip has a different display
+ * FIFO size and allocation, so the caller needs to figure that out and pass
+ * in the correct intel_watermark_params structure.
+ *
+ * As the pixel clock runs, the FIFO will be drained at a rate that depends
+ * on the pixel size.  When it reaches the watermark level, it'll start
+ * fetching FIFO line sized based chunks from memory until the FIFO fills
+ * past the watermark point.  If the FIFO drains completely, a FIFO underrun
+ * will occur, and a display engine hang could result.
+ */
 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
                                        struct intel_watermark_params *wm,
                                        int pixel_size,
                                        unsigned long latency_ns)
 {
-       unsigned long bytes_required, wm_size;
+       long entries_required, wm_size;
+
+       entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
+       entries_required /= wm->cacheline_size;
 
-       bytes_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
-       bytes_required /= wm->cacheline_size;
-       wm_size = wm->fifo_size - bytes_required - wm->guard_size;
+       DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
 
-       if (wm_size > wm->max_wm)
+       wm_size = wm->fifo_size - (entries_required + wm->guard_size);
+
+       DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
+
+       /* Don't promote wm_size to unsigned... */
+       if (wm_size > (long)wm->max_wm)
                wm_size = wm->max_wm;
-       if (wm_size == 0)
+       if (wm_size <= 0)
                wm_size = wm->default_wm;
        return wm_size;
 }
@@ -1799,8 +2005,40 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
        return;
 }
 
-const static int latency_ns = 5000; /* default for non-igd platforms */
+const static int latency_ns = 3000; /* default for non-igd platforms */
 
+static int intel_get_fifo_size(struct drm_device *dev, int plane)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       uint32_t dsparb = I915_READ(DSPARB);
+       int size;
+
+       if (IS_I9XX(dev)) {
+               if (plane == 0)
+                       size = dsparb & 0x7f;
+               else
+                       size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
+                               (dsparb & 0x7f);
+       } else if (IS_I85X(dev)) {
+               if (plane == 0)
+                       size = dsparb & 0x1ff;
+               else
+                       size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
+                               (dsparb & 0x1ff);
+               size >>= 1; /* Convert to cachelines */
+       } else if (IS_845G(dev)) {
+               size = dsparb & 0x7f;
+               size >>= 2; /* Convert to cachelines */
+       } else {
+               size = dsparb & 0x7f;
+               size >>= 1; /* Convert to cachelines */
+       }
+
+       DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
+                 size);
+
+       return size;
+}
 
 static void i965_update_wm(struct drm_device *dev)
 {
@@ -1817,101 +2055,89 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
                           int planeb_clock, int sr_hdisplay, int pixel_size)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-       uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
-       uint32_t fwater_hi = I915_READ(FW_BLC2) & LM_FIFO_WATERMARK;
-       int bsize, asize, cwm, bwm = 1, awm = 1, srwm = 1;
-       uint32_t dsparb = I915_READ(DSPARB);
-       int planea_entries, planeb_entries;
-       struct intel_watermark_params *wm_params;
+       uint32_t fwater_lo;
+       uint32_t fwater_hi;
+       int total_size, cacheline_size, cwm, srwm = 1;
+       int planea_wm, planeb_wm;
+       struct intel_watermark_params planea_params, planeb_params;
        unsigned long line_time_us;
        int sr_clock, sr_entries = 0;
 
+       /* Create copies of the base settings for each pipe */
        if (IS_I965GM(dev) || IS_I945GM(dev))
-               wm_params = &i945_wm_info;
+               planea_params = planeb_params = i945_wm_info;
        else if (IS_I9XX(dev))
-               wm_params = &i915_wm_info;
+               planea_params = planeb_params = i915_wm_info;
        else
-               wm_params = &i855_wm_info;
-
-       planea_entries = intel_calculate_wm(planea_clock, wm_params,
-                                           pixel_size, latency_ns);
-       planeb_entries = intel_calculate_wm(planeb_clock, wm_params,
-                                           pixel_size, latency_ns);
-
-       DRM_DEBUG("FIFO entries - A: %d, B: %d\n", planea_entries,
-                 planeb_entries);
+               planea_params = planeb_params = i855_wm_info;
 
-       if (IS_I9XX(dev)) {
-               asize = dsparb & 0x7f;
-               bsize = (dsparb >> DSPARB_CSTART_SHIFT) & 0x7f;
-       } else {
-               asize = dsparb & 0x1ff;
-               bsize = (dsparb >> DSPARB_BEND_SHIFT) & 0x1ff;
-       }
-       DRM_DEBUG("FIFO size - A: %d, B: %d\n", asize, bsize);
+       /* Grab a couple of global values before we overwrite them */
+       total_size = planea_params.fifo_size;
+       cacheline_size = planea_params.cacheline_size;
 
-       /* Two extra entries for padding */
-       awm = asize - (planea_entries + 2);
-       bwm = bsize - (planeb_entries + 2);
+       /* Update per-plane FIFO sizes */
+       planea_params.fifo_size = intel_get_fifo_size(dev, 0);
+       planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
 
-       /* Sanity check against potentially bad FIFO allocations */
-       if (awm <= 0) {
-               /* pipe is on but has too few FIFO entries */
-               if (planea_entries != 0)
-                       DRM_DEBUG("plane A needs more FIFO entries\n");
-               awm = 1;
-       }
-       if (bwm <= 0) {
-               if (planeb_entries != 0)
-                       DRM_DEBUG("plane B needs more FIFO entries\n");
-               bwm = 1;
-       }
+       planea_wm = intel_calculate_wm(planea_clock, &planea_params,
+                                      pixel_size, latency_ns);
+       planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
+                                      pixel_size, latency_ns);
+       DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
        /*
         * Overlay gets an aggressive default since video jitter is bad.
         */
        cwm = 2;
 
-       /* Calc sr entries for one pipe configs */
-       if (!planea_clock || !planeb_clock) {
+       /* Calc sr entries for one plane configs */
+       if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
+               /* self-refresh has much higher latency */
+               const static int sr_latency_ns = 6000;
+
                sr_clock = planea_clock ? planea_clock : planeb_clock;
-               line_time_us = (sr_hdisplay * 1000) / sr_clock;
-               sr_entries = (((latency_ns / line_time_us) + 1) * pixel_size *
-                             sr_hdisplay) / 1000;
-               sr_entries = roundup(sr_entries / wm_params->cacheline_size, 1);
-               if (sr_entries < wm_params->fifo_size)
-                       srwm = wm_params->fifo_size - sr_entries;
+               line_time_us = ((sr_hdisplay * 1000) / sr_clock);
+
+               /* Use ns/us then divide to preserve precision */
+               sr_entries = (((sr_latency_ns / line_time_us) + 1) *
+                             pixel_size * sr_hdisplay) / 1000;
+               sr_entries = roundup(sr_entries / cacheline_size, 1);
+               DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
+               srwm = total_size - sr_entries;
+               if (srwm < 0)
+                       srwm = 1;
+               if (IS_I9XX(dev))
+                       I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
        }
 
        DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
-                 awm, bwm, cwm, srwm);
+                 planea_wm, planeb_wm, cwm, srwm);
 
-       fwater_lo = fwater_lo | ((bwm & 0x3f) << 16) | (awm & 0x3f);
-       fwater_hi = fwater_hi | (cwm & 0x1f);
+       fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
+       fwater_hi = (cwm & 0x1f);
+
+       /* Set request length to 8 cachelines per fetch */
+       fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
+       fwater_hi = fwater_hi | (1 << 8);
 
        I915_WRITE(FW_BLC, fwater_lo);
        I915_WRITE(FW_BLC2, fwater_hi);
-       if (IS_I9XX(dev))
-               I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
 }
 
 static void i830_update_wm(struct drm_device *dev, int planea_clock,
                           int pixel_size)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-       uint32_t dsparb = I915_READ(DSPARB);
-       uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
-       unsigned int asize, awm;
-       int planea_entries;
-
-       planea_entries = intel_calculate_wm(planea_clock, &i830_wm_info,
-                                           pixel_size, latency_ns);
+       uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
+       int planea_wm;
 
-       asize = dsparb & 0x7f;
+       i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
 
-       awm = asize - planea_entries;
+       planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
+                                      pixel_size, latency_ns);
+       fwater_lo |= (3<<8) | planea_wm;
 
-       fwater_lo = fwater_lo | awm;
+       DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
 
        I915_WRITE(FW_BLC, fwater_lo);
 }
@@ -1984,7 +2210,7 @@ static void intel_update_watermarks(struct drm_device *dev)
        if (enabled <= 0)
                return;
 
-       /* Single pipe configs can enable self refresh */
+       /* Single plane configs can enable self refresh */
        if (enabled == 1 && IS_IGD(dev))
                igd_enable_cxsr(dev, sr_clock, pixel_size);
        else if (IS_IGD(dev))
@@ -2028,6 +2254,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        u32 dpll = 0, fp = 0, dspcntr, pipeconf;
        bool ok, is_sdvo = false, is_dvo = false;
        bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
+       bool is_edp = false;
        struct drm_mode_config *mode_config = &dev->mode_config;
        struct drm_connector *connector;
        const intel_limit_t *limit;
@@ -2043,6 +2270,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        int lvds_reg = LVDS;
        u32 temp;
        int sdvo_pixel_multiply;
+       int target_clock;
 
        drm_vblank_pre_modeset(dev, pipe);
 
@@ -2074,6 +2302,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                case INTEL_OUTPUT_DISPLAYPORT:
                        is_dp = true;
                        break;
+               case INTEL_OUTPUT_EDP:
+                       is_edp = true;
+                       break;
                }
 
                num_outputs++;
@@ -2125,11 +2356,29 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        }
 
        /* FDI link */
-       if (IS_IGDNG(dev))
-               igdng_compute_m_n(3, 4, /* lane num 4 */
-                               adjusted_mode->clock,
-                               270000, /* lane clock */
-                               &m_n);
+       if (IS_IGDNG(dev)) {
+               int lane, link_bw;
+               /* eDP doesn't require FDI link, so just set DP M/N
+                  according to current link config */
+               if (is_edp) {
+                       struct drm_connector *edp;
+                       target_clock = mode->clock;
+                       edp = intel_pipe_get_output(crtc);
+                       intel_edp_link_config(to_intel_output(edp),
+                                       &lane, &link_bw);
+               } else {
+                       /* DP over FDI requires target mode clock
+                          instead of link clock */
+                       if (is_dp)
+                               target_clock = mode->clock;
+                       else
+                               target_clock = adjusted_mode->clock;
+                       lane = 4;
+                       link_bw = 270000;
+               }
+               igdng_compute_m_n(3, lane, target_clock,
+                                 link_bw, &m_n);
+       }
 
        if (IS_IGD(dev))
                fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
@@ -2250,29 +2499,15 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                dpll_reg = pch_dpll_reg;
        }
 
-       if (dpll & DPLL_VCO_ENABLE) {
+       if (is_edp) {
+               igdng_disable_pll_edp(crtc);
+       } else if ((dpll & DPLL_VCO_ENABLE)) {
                I915_WRITE(fp_reg, fp);
                I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
                I915_READ(dpll_reg);
                udelay(150);
        }
 
-       if (IS_IGDNG(dev)) {
-               /* enable PCH clock reference source */
-               /* XXX need to change the setting for other outputs */
-               u32 temp;
-               temp = I915_READ(PCH_DREF_CONTROL);
-               temp &= ~DREF_NONSPREAD_SOURCE_MASK;
-               temp |= DREF_NONSPREAD_CK505_ENABLE;
-               temp &= ~DREF_SSC_SOURCE_MASK;
-               temp |= DREF_SSC_SOURCE_ENABLE;
-               temp &= ~DREF_SSC1_ENABLE;
-               /* if no eDP, disable source output to CPU */
-               temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
-               temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
-               I915_WRITE(PCH_DREF_CONTROL, temp);
-       }
-
        /* The LVDS pin pair needs to be on before the DPLLs are enabled.
         * This is an exception to the general rule that mode_set doesn't turn
         * things on.
@@ -2304,23 +2539,25 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        if (is_dp)
                intel_dp_set_m_n(crtc, mode, adjusted_mode);
 
-       I915_WRITE(fp_reg, fp);
-       I915_WRITE(dpll_reg, dpll);
-       I915_READ(dpll_reg);
-       /* Wait for the clocks to stabilize. */
-       udelay(150);
-
-       if (IS_I965G(dev) && !IS_IGDNG(dev)) {
-               sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
-               I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
-                          ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
-       } else {
-               /* write it again -- the BIOS does, after all */
+       if (!is_edp) {
+               I915_WRITE(fp_reg, fp);
                I915_WRITE(dpll_reg, dpll);
+               I915_READ(dpll_reg);
+               /* Wait for the clocks to stabilize. */
+               udelay(150);
+
+               if (IS_I965G(dev) && !IS_IGDNG(dev)) {
+                       sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
+                       I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
+                                       ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
+               } else {
+                       /* write it again -- the BIOS does, after all */
+                       I915_WRITE(dpll_reg, dpll);
+               }
+               I915_READ(dpll_reg);
+               /* Wait for the clocks to stabilize. */
+               udelay(150);
        }
-       I915_READ(dpll_reg);
-       /* Wait for the clocks to stabilize. */
-       udelay(150);
 
        I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
                   ((adjusted_mode->crtc_htotal - 1) << 16));
@@ -2350,10 +2587,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                I915_WRITE(link_m1_reg, m_n.link_m);
                I915_WRITE(link_n1_reg, m_n.link_n);
 
-                /* enable FDI RX PLL too */
-               temp = I915_READ(fdi_rx_reg);
-               I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
-               udelay(200);
+               if (is_edp) {
+                       igdng_set_pll_edp(crtc, adjusted_mode->clock);
+               } else {
+                       /* enable FDI RX PLL too */
+                       temp = I915_READ(fdi_rx_reg);
+                       I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
+                       udelay(200);
+               }
        }
 
        I915_WRITE(pipeconf_reg, pipeconf);
@@ -2951,12 +3192,17 @@ static void intel_setup_outputs(struct drm_device *dev)
        if (IS_IGDNG(dev)) {
                int found;
 
+               if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
+                       intel_dp_init(dev, DP_A);
+
                if (I915_READ(HDMIB) & PORT_DETECTED) {
                        /* check SDVOB */
                        /* found = intel_sdvo_init(dev, HDMIB); */
                        found = 0;
                        if (!found)
                                intel_hdmi_init(dev, HDMIB);
+                       if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
+                               intel_dp_init(dev, PCH_DP_B);
                }
 
                if (I915_READ(HDMIC) & PORT_DETECTED)
@@ -2965,6 +3211,12 @@ static void intel_setup_outputs(struct drm_device *dev)
                if (I915_READ(HDMID) & PORT_DETECTED)
                        intel_hdmi_init(dev, HDMID);
 
+               if (I915_READ(PCH_DP_C) & DP_DETECTED)
+                       intel_dp_init(dev, PCH_DP_C);
+
+               if (I915_READ(PCH_DP_D) & DP_DETECTED)
+                       intel_dp_init(dev, PCH_DP_D);
+
        } else if (IS_I9XX(dev)) {
                int found;
                u32 reg;
@@ -3039,6 +3291,10 @@ static void intel_setup_outputs(struct drm_device *dev)
                                     (1 << 1));
                        clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
                        break;
+               case INTEL_OUTPUT_EDP:
+                       crtc_mask = (1 << 1);
+                       clone_mask = (1 << INTEL_OUTPUT_EDP);
+                       break;
                }
                encoder->possible_crtcs = crtc_mask;
                encoder->possible_clones = intel_connector_clones(dev, clone_mask);
@@ -3148,6 +3404,9 @@ void intel_modeset_init(struct drm_device *dev)
        if (IS_I965G(dev)) {
                dev->mode_config.max_width = 8192;
                dev->mode_config.max_height = 8192;
+       } else if (IS_I9XX(dev)) {
+               dev->mode_config.max_width = 4096;
+               dev->mode_config.max_height = 4096;
        } else {
                dev->mode_config.max_width = 2048;
                dev->mode_config.max_height = 2048;
index 6770ae88370d6de67c437e918f559c20ddf70e48..a6ff15ac548aa9074eec2647ce377a2290dc58c0 100644 (file)
@@ -40,6 +40,8 @@
 
 #define DP_LINK_CONFIGURATION_SIZE     9
 
+#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
+
 struct intel_dp_priv {
        uint32_t output_reg;
        uint32_t DP;
@@ -63,6 +65,19 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
 static void
 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
 
+void
+intel_edp_link_config (struct intel_output *intel_output,
+               int *lane_num, int *link_bw)
+{
+       struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
+
+       *lane_num = dp_priv->lane_count;
+       if (dp_priv->link_bw == DP_LINK_BW_1_62)
+               *link_bw = 162000;
+       else if (dp_priv->link_bw == DP_LINK_BW_2_7)
+               *link_bw = 270000;
+}
+
 static int
 intel_dp_max_lane_count(struct intel_output *intel_output)
 {
@@ -206,7 +221,13 @@ intel_dp_aux_ch(struct intel_output *intel_output,
         * and would like to run at 2MHz. So, take the
         * hrawclk value and divide by 2 and use that
         */
-       aux_clock_divider = intel_hrawclk(dev) / 2;
+       if (IS_eDP(intel_output))
+               aux_clock_divider = 225; /* eDP input clock at 450Mhz */
+       else if (IS_IGDNG(dev))
+               aux_clock_divider = 62; /* IGDNG: input clock fixed at 125Mhz */
+       else
+               aux_clock_divider = intel_hrawclk(dev) / 2;
+
        /* Must try at least 3 times according to DP spec */
        for (try = 0; try < 5; try++) {
                /* Load the send data into the aux channel data registers */
@@ -236,7 +257,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
                }
        
                /* Clear done status and any errors */
-               I915_WRITE(ch_ctl, (ctl |
+               I915_WRITE(ch_ctl, (status |
                                DP_AUX_CH_CTL_DONE |
                                DP_AUX_CH_CTL_TIME_OUT_ERROR |
                                DP_AUX_CH_CTL_RECEIVE_ERROR));
@@ -295,7 +316,7 @@ intel_dp_aux_native_write(struct intel_output *intel_output,
                return -1;
        msg[0] = AUX_NATIVE_WRITE << 4;
        msg[1] = address >> 8;
-       msg[2] = address;
+       msg[2] = address & 0xff;
        msg[3] = send_bytes - 1;
        memcpy(&msg[4], send, send_bytes);
        msg_bytes = send_bytes + 4;
@@ -387,8 +408,8 @@ intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
        memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
        dp_priv->adapter.owner = THIS_MODULE;
        dp_priv->adapter.class = I2C_CLASS_DDC;
-       strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1);
-       dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0';
+       strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
+       dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
        dp_priv->adapter.algo_data = &dp_priv->algo;
        dp_priv->adapter.dev.parent = &intel_output->base.kdev;
        
@@ -493,22 +514,40 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
        intel_dp_compute_m_n(3, lane_count,
                             mode->clock, adjusted_mode->clock, &m_n);
 
-       if (intel_crtc->pipe == 0) {
-               I915_WRITE(PIPEA_GMCH_DATA_M,
-                      ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
-                      m_n.gmch_m);
-               I915_WRITE(PIPEA_GMCH_DATA_N,
-                      m_n.gmch_n);
-               I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
-               I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
+       if (IS_IGDNG(dev)) {
+               if (intel_crtc->pipe == 0) {
+                       I915_WRITE(TRANSA_DATA_M1,
+                                  ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                                  m_n.gmch_m);
+                       I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
+                       I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
+                       I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
+               } else {
+                       I915_WRITE(TRANSB_DATA_M1,
+                                  ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                                  m_n.gmch_m);
+                       I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
+                       I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
+                       I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
+               }
        } else {
-               I915_WRITE(PIPEB_GMCH_DATA_M,
-                      ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
-                      m_n.gmch_m);
-               I915_WRITE(PIPEB_GMCH_DATA_N,
-                      m_n.gmch_n);
-               I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
-               I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
+               if (intel_crtc->pipe == 0) {
+                       I915_WRITE(PIPEA_GMCH_DATA_M,
+                                  ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                                  m_n.gmch_m);
+                       I915_WRITE(PIPEA_GMCH_DATA_N,
+                                  m_n.gmch_n);
+                       I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
+                       I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
+               } else {
+                       I915_WRITE(PIPEB_GMCH_DATA_M,
+                                  ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                                  m_n.gmch_m);
+                       I915_WRITE(PIPEB_GMCH_DATA_N,
+                                       m_n.gmch_n);
+                       I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
+                       I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
+               }
        }
 }
 
@@ -556,8 +595,38 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
        if (intel_crtc->pipe == 1)
                dp_priv->DP |= DP_PIPEB_SELECT;
+
+       if (IS_eDP(intel_output)) {
+               /* don't miss out required setting for eDP */
+               dp_priv->DP |= DP_PLL_ENABLE;
+               if (adjusted_mode->clock < 200000)
+                       dp_priv->DP |= DP_PLL_FREQ_160MHZ;
+               else
+                       dp_priv->DP |= DP_PLL_FREQ_270MHZ;
+       }
 }
 
+static void igdng_edp_backlight_on (struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 pp;
+
+       DRM_DEBUG("\n");
+       pp = I915_READ(PCH_PP_CONTROL);
+       pp |= EDP_BLC_ENABLE;
+       I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
+static void igdng_edp_backlight_off (struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 pp;
+
+       DRM_DEBUG("\n");
+       pp = I915_READ(PCH_PP_CONTROL);
+       pp &= ~EDP_BLC_ENABLE;
+       I915_WRITE(PCH_PP_CONTROL, pp);
+}
 
 static void
 intel_dp_dpms(struct drm_encoder *encoder, int mode)
@@ -569,11 +638,17 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
        uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 
        if (mode != DRM_MODE_DPMS_ON) {
-               if (dp_reg & DP_PORT_EN)
+               if (dp_reg & DP_PORT_EN) {
                        intel_dp_link_down(intel_output, dp_priv->DP);
+                       if (IS_eDP(intel_output))
+                               igdng_edp_backlight_off(dev);
+               }
        } else {
-               if (!(dp_reg & DP_PORT_EN))
+               if (!(dp_reg & DP_PORT_EN)) {
                        intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
+                       if (IS_eDP(intel_output))
+                               igdng_edp_backlight_on(dev);
+               }
        }
        dp_priv->dpms_mode = mode;
 }
@@ -935,6 +1010,23 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 
+       DRM_DEBUG("\n");
+
+       if (IS_eDP(intel_output)) {
+               DP &= ~DP_PLL_ENABLE;
+               I915_WRITE(dp_priv->output_reg, DP);
+               POSTING_READ(dp_priv->output_reg);
+               udelay(100);
+       }
+
+       DP &= ~DP_LINK_TRAIN_MASK;
+       I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
+       POSTING_READ(dp_priv->output_reg);
+
+       udelay(17000);
+
+       if (IS_eDP(intel_output))
+               DP |= DP_LINK_TRAIN_OFF;
        I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
        POSTING_READ(dp_priv->output_reg);
 }
@@ -978,6 +1070,24 @@ intel_dp_check_link_status(struct intel_output *intel_output)
                intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
 }
 
+static enum drm_connector_status
+igdng_dp_detect(struct drm_connector *connector)
+{
+       struct intel_output *intel_output = to_intel_output(connector);
+       struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+       enum drm_connector_status status;
+
+       status = connector_status_disconnected;
+       if (intel_dp_aux_native_read(intel_output,
+                                    0x000, dp_priv->dpcd,
+                                    sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
+       {
+               if (dp_priv->dpcd[0] != 0)
+                       status = connector_status_connected;
+       }
+       return status;
+}
+
 /**
  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
  *
@@ -996,6 +1106,9 @@ intel_dp_detect(struct drm_connector *connector)
 
        dp_priv->has_audio = false;
 
+       if (IS_IGDNG(dev))
+               return igdng_dp_detect(connector);
+
        temp = I915_READ(PORT_HOTPLUG_EN);
 
        I915_WRITE(PORT_HOTPLUG_EN,
@@ -1039,11 +1152,27 @@ intel_dp_detect(struct drm_connector *connector)
 static int intel_dp_get_modes(struct drm_connector *connector)
 {
        struct intel_output *intel_output = to_intel_output(connector);
+       struct drm_device *dev = intel_output->base.dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       int ret;
 
        /* We should parse the EDID data and find out if it has an audio sink
         */
 
-       return intel_ddc_get_modes(intel_output);
+       ret = intel_ddc_get_modes(intel_output);
+       if (ret)
+               return ret;
+
+       /* if eDP has no EDID, try to use fixed panel mode from VBT */
+       if (IS_eDP(intel_output)) {
+               if (dev_priv->panel_fixed_mode != NULL) {
+                       struct drm_display_mode *mode;
+                       mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
+                       drm_mode_probed_add(connector, mode);
+                       return 1;
+               }
+       }
+       return 0;
 }
 
 static void
@@ -1106,6 +1235,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
        struct drm_connector *connector;
        struct intel_output *intel_output;
        struct intel_dp_priv *dp_priv;
+       const char *name = NULL;
 
        intel_output = kcalloc(sizeof(struct intel_output) + 
                               sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
@@ -1119,7 +1249,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                           DRM_MODE_CONNECTOR_DisplayPort);
        drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
 
-       intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
+       if (output_reg == DP_A)
+               intel_output->type = INTEL_OUTPUT_EDP;
+       else
+               intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
 
        connector->interlace_allowed = true;
        connector->doublescan_allowed = 0;
@@ -1139,12 +1272,41 @@ intel_dp_init(struct drm_device *dev, int output_reg)
        drm_sysfs_connector_add(connector);
 
        /* Set up the DDC bus. */
-       intel_dp_i2c_init(intel_output,
-                         (output_reg == DP_B) ? "DPDDC-B" :
-                         (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D");
+       switch (output_reg) {
+               case DP_A:
+                       name = "DPDDC-A";
+                       break;
+               case DP_B:
+               case PCH_DP_B:
+                       name = "DPDDC-B";
+                       break;
+               case DP_C:
+               case PCH_DP_C:
+                       name = "DPDDC-C";
+                       break;
+               case DP_D:
+               case PCH_DP_D:
+                       name = "DPDDC-D";
+                       break;
+       }
+
+       intel_dp_i2c_init(intel_output, name);
+
        intel_output->ddc_bus = &dp_priv->adapter;
        intel_output->hot_plug = intel_dp_hot_plug;
 
+       if (output_reg == DP_A) {
+               /* initialize panel mode from VBT if available for eDP */
+               if (dev_priv->lfp_lvds_vbt_mode) {
+                       dev_priv->panel_fixed_mode =
+                               drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
+                       if (dev_priv->panel_fixed_mode) {
+                               dev_priv->panel_fixed_mode->type |=
+                                       DRM_MODE_TYPE_PREFERRED;
+                       }
+               }
+       }
+
        /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
         * 0xd.  Failure to do so will result in spurious interrupts being
         * generated on the port when a cable is not attached.
index 004541c935a80bd61bf591c820131d3c3bd02843..d6f92ea1b5538fc0928119b600f4eaa241f66ada 100644 (file)
@@ -55,6 +55,7 @@
 #define INTEL_OUTPUT_TVOUT 5
 #define INTEL_OUTPUT_HDMI 6
 #define INTEL_OUTPUT_DISPLAYPORT 7
+#define INTEL_OUTPUT_EDP 8
 
 #define INTEL_DVO_CHIP_NONE 0
 #define INTEL_DVO_CHIP_LVDS 1
@@ -121,6 +122,8 @@ extern void intel_dp_init(struct drm_device *dev, int dp_reg);
 void
 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
                 struct drm_display_mode *adjusted_mode);
+extern void intel_edp_link_config (struct intel_output *, int *, int *);
+
 
 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 extern void intel_encoder_prepare (struct drm_encoder *encoder);
index 9e30daae37dca8c45ba0635f3e22a9d1e98da967..1842290cded3f074883a155269ceed3ae2e0b749 100644 (file)
@@ -130,16 +130,17 @@ static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 }
 
 static enum drm_connector_status
-intel_hdmi_edid_detect(struct drm_connector *connector)
+intel_hdmi_detect(struct drm_connector *connector)
 {
        struct intel_output *intel_output = to_intel_output(connector);
        struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
        struct edid *edid = NULL;
        enum drm_connector_status status = connector_status_disconnected;
 
+       hdmi_priv->has_hdmi_sink = false;
        edid = drm_get_edid(&intel_output->base,
                            intel_output->ddc_bus);
-       hdmi_priv->has_hdmi_sink = false;
+
        if (edid) {
                if (edid->input & DRM_EDID_INPUT_DIGITAL) {
                        status = connector_status_connected;
@@ -148,65 +149,8 @@ intel_hdmi_edid_detect(struct drm_connector *connector)
                intel_output->base.display_info.raw_edid = NULL;
                kfree(edid);
        }
-       return status;
-}
-
-static enum drm_connector_status
-igdng_hdmi_detect(struct drm_connector *connector)
-{
-       struct intel_output *intel_output = to_intel_output(connector);
-       struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
-
-       /* FIXME hotplug detect */
-
-       hdmi_priv->has_hdmi_sink = false;
-       return intel_hdmi_edid_detect(connector);
-}
 
-static enum drm_connector_status
-intel_hdmi_detect(struct drm_connector *connector)
-{
-       struct drm_device *dev = connector->dev;
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       struct intel_output *intel_output = to_intel_output(connector);
-       struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
-       u32 temp, bit;
-
-       if (IS_IGDNG(dev))
-               return igdng_hdmi_detect(connector);
-
-       temp = I915_READ(PORT_HOTPLUG_EN);
-
-       switch (hdmi_priv->sdvox_reg) {
-       case SDVOB:
-               temp |= HDMIB_HOTPLUG_INT_EN;
-               break;
-       case SDVOC:
-               temp |= HDMIC_HOTPLUG_INT_EN;
-               break;
-       default:
-               return connector_status_unknown;
-       }
-
-       I915_WRITE(PORT_HOTPLUG_EN, temp);
-
-       POSTING_READ(PORT_HOTPLUG_EN);
-
-       switch (hdmi_priv->sdvox_reg) {
-       case SDVOB:
-               bit = HDMIB_HOTPLUG_INT_STATUS;
-               break;
-       case SDVOC:
-               bit = HDMIC_HOTPLUG_INT_STATUS;
-               break;
-       default:
-               return connector_status_unknown;
-       }
-
-       if ((I915_READ(PORT_HOTPLUG_STAT) & bit) != 0)
-               return intel_hdmi_edid_detect(connector);
-       else
-               return connector_status_disconnected;
+       return status;
 }
 
 static int intel_hdmi_get_modes(struct drm_connector *connector)
index 9ab38efffecfeab426e48c45bbc3a7ee77bf96f4..3f445a80c552908b251cfa9d0d688c653a2f10ab 100644 (file)
@@ -778,6 +778,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
                        DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
                },
        },
+       {
+               .callback = intel_no_lvds_dmi_callback,
+               .ident = "AOpen Mini PC MP915",
+               .matches = {
+                       DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
+                       DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
+               },
+       },
        {
                .callback = intel_no_lvds_dmi_callback,
                .ident = "Aopen i945GTt-VFA",
@@ -884,6 +892,10 @@ void intel_lvds_init(struct drm_device *dev)
        if (IS_IGDNG(dev)) {
                if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
                        return;
+               if (dev_priv->edp_support) {
+                       DRM_DEBUG("disable LVDS for eDP support\n");
+                       return;
+               }
                gpio = PCH_GPIOC;
        }
 
index 4f0c30948bc43ae5626f1fa76b4368db7f2149ba..5371d9332554fe9716bb5bd8403bb177b4829fd3 100644 (file)
@@ -31,6 +31,7 @@
 #include "drm.h"
 #include "drm_crtc.h"
 #include "intel_drv.h"
+#include "drm_edid.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
 #include "intel_sdvo_regs.h"
@@ -55,6 +56,12 @@ struct intel_sdvo_priv {
        /* Pixel clock limitations reported by the SDVO device, in kHz */
        int pixel_clock_min, pixel_clock_max;
 
+       /*
+       * For multiple function SDVO device,
+       * this is for current attached outputs.
+       */
+       uint16_t attached_output;
+
        /**
         * This is set if we're going to treat the device as TV-out.
         *
@@ -114,6 +121,9 @@ struct intel_sdvo_priv {
        u32 save_SDVOX;
 };
 
+static bool
+intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
+
 /**
  * Writes the SDVOB or SDVOC with the given value, but always writes both
  * SDVOB and SDVOC to work around apparent hardware issues (according to
@@ -1435,41 +1445,96 @@ void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
        intel_sdvo_read_response(intel_output, &response, 2);
 }
 
-static void
-intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
+static bool
+intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
+{
+       struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+       int caps = 0;
+
+       if (sdvo_priv->caps.output_flags &
+               (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
+               caps++;
+       if (sdvo_priv->caps.output_flags &
+               (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
+               caps++;
+       if (sdvo_priv->caps.output_flags &
+               (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID0))
+               caps++;
+       if (sdvo_priv->caps.output_flags &
+               (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
+               caps++;
+       if (sdvo_priv->caps.output_flags &
+               (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
+               caps++;
+
+       if (sdvo_priv->caps.output_flags &
+               (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
+               caps++;
+
+       if (sdvo_priv->caps.output_flags &
+               (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
+               caps++;
+
+       return (caps > 1);
+}
+
+enum drm_connector_status
+intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
 {
        struct intel_output *intel_output = to_intel_output(connector);
        struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+       enum drm_connector_status status = connector_status_connected;
        struct edid *edid = NULL;
 
        edid = drm_get_edid(&intel_output->base,
                            intel_output->ddc_bus);
        if (edid != NULL) {
-               sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
+               /* Don't report the output as connected if it's a DVI-I
+                * connector with a non-digital EDID coming out.
+                */
+               if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
+                       if (edid->input & DRM_EDID_INPUT_DIGITAL)
+                               sdvo_priv->is_hdmi =
+                                       drm_detect_hdmi_monitor(edid);
+                       else
+                               status = connector_status_disconnected;
+               }
+
                kfree(edid);
                intel_output->base.display_info.raw_edid = NULL;
-       }
+
+       } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
+               status = connector_status_disconnected;
+
+       return status;
 }
 
 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
 {
-       u8 response[2];
+       uint16_t response;
        u8 status;
        struct intel_output *intel_output = to_intel_output(connector);
+       struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 
        intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
        status = intel_sdvo_read_response(intel_output, &response, 2);
 
-       DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
+       DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8);
 
        if (status != SDVO_CMD_STATUS_SUCCESS)
                return connector_status_unknown;
 
-       if ((response[0] != 0) || (response[1] != 0)) {
-               intel_sdvo_hdmi_sink_detect(connector);
-               return connector_status_connected;
-       } else
+       if (response == 0)
                return connector_status_disconnected;
+
+       if (intel_sdvo_multifunc_encoder(intel_output) &&
+               sdvo_priv->attached_output != response) {
+               if (sdvo_priv->controlled_output != response &&
+                       intel_sdvo_output_setup(intel_output, response) != true)
+                       return connector_status_unknown;
+               sdvo_priv->attached_output = response;
+       }
+       return intel_sdvo_hdmi_sink_detect(connector, response);
 }
 
 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
@@ -1866,16 +1931,101 @@ intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
                return 0x72;
 }
 
+static bool
+intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
+{
+       struct drm_connector *connector = &intel_output->base;
+       struct drm_encoder *encoder = &intel_output->enc;
+       struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+       bool ret = true, registered = false;
+
+       sdvo_priv->is_tv = false;
+       intel_output->needs_tv_clock = false;
+       sdvo_priv->is_lvds = false;
+
+       if (device_is_registered(&connector->kdev)) {
+               drm_sysfs_connector_remove(connector);
+               registered = true;
+       }
+
+       if (flags &
+           (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
+               if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
+                       sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
+               else
+                       sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
+
+               encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
+               connector->connector_type = DRM_MODE_CONNECTOR_DVID;
+
+               if (intel_sdvo_get_supp_encode(intel_output,
+                                              &sdvo_priv->encode) &&
+                   intel_sdvo_get_digital_encoding_mode(intel_output) &&
+                   sdvo_priv->is_hdmi) {
+                       /* enable hdmi encoding mode if supported */
+                       intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
+                       intel_sdvo_set_colorimetry(intel_output,
+                                                  SDVO_COLORIMETRY_RGB256);
+                       connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
+               }
+       } else if (flags & SDVO_OUTPUT_SVID0) {
+
+               sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
+               encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
+               connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
+               sdvo_priv->is_tv = true;
+               intel_output->needs_tv_clock = true;
+       } else if (flags & SDVO_OUTPUT_RGB0) {
+
+               sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
+               encoder->encoder_type = DRM_MODE_ENCODER_DAC;
+               connector->connector_type = DRM_MODE_CONNECTOR_VGA;
+       } else if (flags & SDVO_OUTPUT_RGB1) {
+
+               sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
+               encoder->encoder_type = DRM_MODE_ENCODER_DAC;
+               connector->connector_type = DRM_MODE_CONNECTOR_VGA;
+       } else if (flags & SDVO_OUTPUT_LVDS0) {
+
+               sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
+               encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
+               connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
+               sdvo_priv->is_lvds = true;
+       } else if (flags & SDVO_OUTPUT_LVDS1) {
+
+               sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
+               encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
+               connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
+               sdvo_priv->is_lvds = true;
+       } else {
+
+               unsigned char bytes[2];
+
+               sdvo_priv->controlled_output = 0;
+               memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
+               DRM_DEBUG_KMS(I915_SDVO,
+                               "%s: Unknown SDVO output type (0x%02x%02x)\n",
+                                 SDVO_NAME(sdvo_priv),
+                                 bytes[0], bytes[1]);
+               ret = false;
+       }
+
+       if (ret && registered)
+               ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
+
+
+       return ret;
+
+}
+
 bool intel_sdvo_init(struct drm_device *dev, int output_device)
 {
        struct drm_connector *connector;
        struct intel_output *intel_output;
        struct intel_sdvo_priv *sdvo_priv;
 
-       int connector_type;
        u8 ch[0x40];
        int i;
-       int encoder_type;
 
        intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
        if (!intel_output) {
@@ -1925,88 +2075,28 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
        intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
 
        /* In defaut case sdvo lvds is false */
-       sdvo_priv->is_lvds = false;
        intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
 
-       if (sdvo_priv->caps.output_flags &
-           (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
-               if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
-                       sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
-               else
-                       sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
-
-               encoder_type = DRM_MODE_ENCODER_TMDS;
-               connector_type = DRM_MODE_CONNECTOR_DVID;
-
-               if (intel_sdvo_get_supp_encode(intel_output,
-                                              &sdvo_priv->encode) &&
-                   intel_sdvo_get_digital_encoding_mode(intel_output) &&
-                   sdvo_priv->is_hdmi) {
-                       /* enable hdmi encoding mode if supported */
-                       intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
-                       intel_sdvo_set_colorimetry(intel_output,
-                                                  SDVO_COLORIMETRY_RGB256);
-                       connector_type = DRM_MODE_CONNECTOR_HDMIA;
-               }
-       }
-       else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
-       {
-               sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
-               encoder_type = DRM_MODE_ENCODER_TVDAC;
-               connector_type = DRM_MODE_CONNECTOR_SVIDEO;
-               sdvo_priv->is_tv = true;
-               intel_output->needs_tv_clock = true;
-       }
-       else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
-       {
-               sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
-               encoder_type = DRM_MODE_ENCODER_DAC;
-               connector_type = DRM_MODE_CONNECTOR_VGA;
-       }
-       else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
-       {
-               sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
-               encoder_type = DRM_MODE_ENCODER_DAC;
-               connector_type = DRM_MODE_CONNECTOR_VGA;
-       }
-       else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
-       {
-               sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
-               encoder_type = DRM_MODE_ENCODER_LVDS;
-               connector_type = DRM_MODE_CONNECTOR_LVDS;
-               sdvo_priv->is_lvds = true;
-       }
-       else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
-       {
-               sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
-               encoder_type = DRM_MODE_ENCODER_LVDS;
-               connector_type = DRM_MODE_CONNECTOR_LVDS;
-               sdvo_priv->is_lvds = true;
-       }
-       else
-       {
-               unsigned char bytes[2];
-
-               sdvo_priv->controlled_output = 0;
-               memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
-               DRM_DEBUG_KMS(I915_SDVO,
-                               "%s: Unknown SDVO output type (0x%02x%02x)\n",
-                                 SDVO_NAME(sdvo_priv),
-                                 bytes[0], bytes[1]);
-               encoder_type = DRM_MODE_ENCODER_NONE;
-               connector_type = DRM_MODE_CONNECTOR_Unknown;
+       if (intel_sdvo_output_setup(intel_output,
+                                   sdvo_priv->caps.output_flags) != true) {
+               DRM_DEBUG("SDVO output failed to setup on SDVO%c\n",
+                         output_device == SDVOB ? 'B' : 'C');
                goto err_i2c;
        }
 
+
        connector = &intel_output->base;
        drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
-                          connector_type);
+                          connector->connector_type);
+
        drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
        connector->interlace_allowed = 0;
        connector->doublescan_allowed = 0;
        connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 
-       drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
+       drm_encoder_init(dev, &intel_output->enc,
+                       &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
+
        drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
 
        drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
index a43c98e3f0777dc6de4416a8f00f5c9c8dedcd82..da4ab4dc16306b6fc4b7727da0954f7736a290cb 100644 (file)
@@ -1490,6 +1490,27 @@ static struct input_res {
        {"1920x1080", 1920, 1080},
 };
 
+/*
+ * Chose preferred mode  according to line number of TV format
+ */
+static void
+intel_tv_chose_preferred_modes(struct drm_connector *connector,
+                              struct drm_display_mode *mode_ptr)
+{
+       struct intel_output *intel_output = to_intel_output(connector);
+       const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output);
+
+       if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
+               mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
+       else if (tv_mode->nbr_end > 480) {
+               if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
+                       if (mode_ptr->vdisplay == 720)
+                               mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
+               } else if (mode_ptr->vdisplay == 1080)
+                               mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
+       }
+}
+
 /**
  * Stub get_modes function.
  *
@@ -1544,6 +1565,7 @@ intel_tv_get_modes(struct drm_connector *connector)
                mode_ptr->clock = (int) tmp;
 
                mode_ptr->type = DRM_MODE_TYPE_DRIVER;
+               intel_tv_chose_preferred_modes(connector, mode_ptr);
                drm_mode_probed_add(connector, mode_ptr);
                count++;
        }
index 146f3570af8e710f689d3f9823981b993a5e3632..20f17908b036d6c59b8435e354787a42295fa0d8 100644 (file)
@@ -384,8 +384,9 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
                DRM_INFO("Loading RV670 PFP Microcode\n");
                for (i = 0; i < PFP_UCODE_SIZE; i++)
                        RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
-       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
-               DRM_INFO("Loading RS780 CP Microcode\n");
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
+               DRM_INFO("Loading RS780/RS880 CP Microcode\n");
                for (i = 0; i < PM4_UCODE_SIZE; i++) {
                        RADEON_WRITE(R600_CP_ME_RAM_DATA,
                                     RS780_cp_microcode[i][0]);
@@ -396,7 +397,7 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
                }
 
                RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-               DRM_INFO("Loading RS780 PFP Microcode\n");
+               DRM_INFO("Loading RS780/RS880 PFP Microcode\n");
                for (i = 0; i < PFP_UCODE_SIZE; i++)
                        RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
        }
@@ -783,6 +784,7 @@ static void r600_gfx_init(struct drm_device *dev,
                break;
        case CHIP_RV610:
        case CHIP_RS780:
+       case CHIP_RS880:
        case CHIP_RV620:
                dev_priv->r600_max_pipes = 1;
                dev_priv->r600_max_tile_pipes = 1;
@@ -917,7 +919,8 @@ static void r600_gfx_init(struct drm_device *dev,
            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
-           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
                RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
        else
                RADEON_WRITE(R600_DB_DEBUG, 0);
@@ -935,7 +938,8 @@ static void r600_gfx_init(struct drm_device *dev,
        sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
        if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
-           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
                sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
                                    R600_FETCH_FIFO_HIWATER(0xa) |
                                    R600_DONE_FIFO_HIWATER(0xe0) |
@@ -978,7 +982,8 @@ static void r600_gfx_init(struct drm_device *dev,
                                            R600_NUM_ES_STACK_ENTRIES(0));
        } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
-                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
                /* no vertex cache */
                sq_config &= ~R600_VC_ENABLE;
 
@@ -1035,7 +1040,8 @@ static void r600_gfx_init(struct drm_device *dev,
 
        if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
-           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
                RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
        else
                RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
@@ -1078,6 +1084,7 @@ static void r600_gfx_init(struct drm_device *dev,
                break;
        case CHIP_RV610:
        case CHIP_RS780:
+       case CHIP_RS880:
        case CHIP_RV620:
                gs_prim_buffer_depth = 32;
                break;
@@ -1123,6 +1130,7 @@ static void r600_gfx_init(struct drm_device *dev,
        switch (dev_priv->flags & RADEON_FAMILY_MASK) {
        case CHIP_RV610:
        case CHIP_RS780:
+       case CHIP_RS880:
        case CHIP_RV620:
                tc_cntl = R600_TC_L2_SIZE(8);
                break;
index a162ade74b7fadf75398f60b89ba7fffe33d691a..9ff6dcb97f9daa391f004b157b82e3bea9047288 100644 (file)
@@ -152,7 +152,9 @@ int radeon_mc_setup(struct radeon_device *rdev)
                }
        } else {
                rdev->mc.vram_location = 0;
-               rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+               tmp = rdev->mc.mc_vram_size;
+               tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
+               rdev->mc.gtt_location = tmp;
        }
        DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20);
        DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
index 127d0456f628bf87ed469e5a451347c5d981f5b4..3933f8216a34d8aa43cb536b7157c0e7cc6d4c21 100644 (file)
@@ -143,6 +143,7 @@ enum radeon_family {
        CHIP_RV635,
        CHIP_RV670,
        CHIP_RS780,
+       CHIP_RS880,
        CHIP_RV770,
        CHIP_RV730,
        CHIP_RV710,
index dd9ac2fed6d69512f8696294a6ec1f062e22f250..e98cae3bf4a67959dc0b600ddeb9e47c1dac49ca 100644 (file)
@@ -106,7 +106,7 @@ static inline uint32_t radeon_object_flags_from_domain(uint32_t domain)
                flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
        }
        if (domain & RADEON_GEM_DOMAIN_GTT) {
-               flags |= TTM_PL_FLAG_TT | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
+               flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
        }
        if (domain & RADEON_GEM_DOMAIN_CPU) {
                flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
index e9b2e7cb05be2fc316227ebf0f1426ebfb969720..541b981ff0752d2a3bfeb991ad1bf866d236aa61 100644 (file)
@@ -27,6 +27,7 @@ struct matrix_keypad {
        const struct matrix_keypad_platform_data *pdata;
        struct input_dev *input_dev;
        unsigned short *keycodes;
+       unsigned int row_shift;
 
        uint32_t last_key_state[MATRIX_MAX_COLS];
        struct delayed_work work;
@@ -136,7 +137,7 @@ static void matrix_keypad_scan(struct work_struct *work)
                        if ((bits_changed & (1 << row)) == 0)
                                continue;
 
-                       code = (row << 4) + col;
+                       code = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
                        input_event(input_dev, EV_MSC, MSC_SCAN, code);
                        input_report_key(input_dev,
                                         keypad->keycodes[code],
@@ -317,6 +318,7 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
        struct matrix_keypad *keypad;
        struct input_dev *input_dev;
        unsigned short *keycodes;
+       unsigned int row_shift;
        int i;
        int err;
 
@@ -332,14 +334,11 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
                return -EINVAL;
        }
 
-       if (!keymap_data->max_keymap_size) {
-               dev_err(&pdev->dev, "invalid keymap data supplied\n");
-               return -EINVAL;
-       }
+       row_shift = get_count_order(pdata->num_col_gpios);
 
        keypad = kzalloc(sizeof(struct matrix_keypad), GFP_KERNEL);
-       keycodes = kzalloc(keymap_data->max_keymap_size *
-                               sizeof(keypad->keycodes),
+       keycodes = kzalloc((pdata->num_row_gpios << row_shift) *
+                               sizeof(*keycodes),
                           GFP_KERNEL);
        input_dev = input_allocate_device();
        if (!keypad || !keycodes || !input_dev) {
@@ -350,6 +349,7 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
        keypad->input_dev = input_dev;
        keypad->pdata = pdata;
        keypad->keycodes = keycodes;
+       keypad->row_shift = row_shift;
        keypad->stopped = true;
        INIT_DELAYED_WORK(&keypad->work, matrix_keypad_scan);
        spin_lock_init(&keypad->lock);
@@ -363,7 +363,7 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
 
        input_dev->keycode      = keycodes;
        input_dev->keycodesize  = sizeof(*keycodes);
-       input_dev->keycodemax   = keymap_data->max_keymap_size;
+       input_dev->keycodemax   = pdata->num_row_gpios << keypad->row_shift;
 
        for (i = 0; i < keymap_data->keymap_size; i++) {
                unsigned int key = keymap_data->keymap[i];
@@ -371,7 +371,7 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
                unsigned int col = KEY_COL(key);
                unsigned short code = KEY_VAL(key);
 
-               keycodes[(row << 4) + col] = code;
+               keycodes[MATRIX_SCAN_CODE(row, col, row_shift)] = code;
                __set_bit(code, input_dev->keybit);
        }
        __clear_bit(KEY_RESERVED, input_dev->keybit);
index 26e17a9a22eb7fd030edba83537a6d3b68749081..27ee976eb54cea4e561fd32665ccfa539d244b96 100644 (file)
@@ -611,6 +611,20 @@ static struct key_entry keymap_wistron_generic[] __initdata = {
        { KE_END, 0 }
 };
 
+static struct key_entry keymap_prestigio[] __initdata = {
+       { KE_KEY,  0x11, {KEY_PROG1} },
+       { KE_KEY,  0x12, {KEY_PROG2} },
+       { KE_WIFI,  0x30 },
+       { KE_KEY,  0x22, {KEY_REWIND} },
+       { KE_KEY,  0x23, {KEY_FORWARD} },
+       { KE_KEY,  0x24, {KEY_PLAYPAUSE} },
+       { KE_KEY,  0x25, {KEY_STOPCD} },
+       { KE_KEY,  0x31, {KEY_MAIL} },
+       { KE_KEY,  0x36, {KEY_WWW} },
+       { KE_END,  0 }
+};
+
+
 /*
  * If your machine is not here (which is currently rather likely), please send
  * a list of buttons and their key codes (reported when loading this module
@@ -971,6 +985,8 @@ static int __init select_keymap(void)
        if (keymap_name != NULL) {
                if (strcmp (keymap_name, "1557/MS2141") == 0)
                        keymap = keymap_wistron_ms2141;
+               else if (strcmp (keymap_name, "prestigio") == 0)
+                       keymap = keymap_prestigio;
                else if (strcmp (keymap_name, "generic") == 0)
                        keymap = keymap_wistron_generic;
                else {
index 924e8ed7f2cf777f5d48767c18d5618027c031e6..ae04d8a494e56e4e6e47f16922879177a6a13283 100644 (file)
@@ -77,6 +77,14 @@ static struct dmi_system_id __initdata i8042_dmi_noloop_table[] = {
                        DMI_MATCH(DMI_BOARD_VERSION, "Rev E"),
                },
        },
+       {
+               .ident = "ASUS G1S",
+               .matches = {
+                       DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer Inc."),
+                       DMI_MATCH(DMI_BOARD_NAME, "G1S"),
+                       DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
+               },
+       },
        {
                /* AUX LOOP command does not raise AUX IRQ */
                .ident = "ASUS P65UP5",
index 908844327db0ef3bb7dbf389d6d9e983a747ffe7..1e8aa590bb39b0a5e650037f61647860fd2b3ec1 100644 (file)
@@ -234,7 +234,7 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
                return -ENODEV;
 
        host = sdhci_alloc_host(&ofdev->dev, sizeof(*of_host));
-       if (!host)
+       if (IS_ERR(host))
                return -ENOMEM;
 
        of_host = sdhci_priv(host);
index 0b98654d8eed27831b591c3ec2575771c44166d8..7a58bd5522fd736a83584acaf9a9472b4a57e876 100644 (file)
@@ -284,13 +284,6 @@ config MTD_L440GX
 
          BE VERY CAREFUL.
 
-config MTD_SBC8240
-       tristate "Flash device on SBC8240"
-       depends on MTD_JEDECPROBE && 8260
-       help
-          Flash access on the SBC8240 board from Wind River.  See
-          <http://www.windriver.com/products/sbc8240/>
-
 config MTD_TQM8XXL
        tristate "CFI Flash device mapped on TQM8XXL"
        depends on MTD_CFI && TQM8xxL
index 8bae7f9850c0b1acbb2e782734f01bd612f8a985..5beb0662d724b7097d3bb7fd5c62169f715d6a3e 100644 (file)
@@ -50,7 +50,6 @@ obj-$(CONFIG_MTD_UCLINUX)     += uclinux.o
 obj-$(CONFIG_MTD_NETtel)       += nettel.o
 obj-$(CONFIG_MTD_SCB2_FLASH)   += scb2_flash.o
 obj-$(CONFIG_MTD_H720X)                += h720x-flash.o
-obj-$(CONFIG_MTD_SBC8240)      += sbc8240.o
 obj-$(CONFIG_MTD_IXP4XX)       += ixp4xx.o
 obj-$(CONFIG_MTD_IXP2000)      += ixp2000.o
 obj-$(CONFIG_MTD_WRSBC8260)    += wr_sbc82xx_flash.o
index d5374cdcb163bc82b3bbaa94a87062431be9cf8e..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
@@ -1,250 +0,0 @@
-/*
- * Handle mapping of the flash memory access routines on the SBC8240 board.
- *
- * Carolyn Smith, Tektronix, Inc.
- *
- * This code is GPLed
- */
-
-/*
- * The SBC8240 has 2 flash banks.
- * Bank 0 is a 512 KiB AMD AM29F040B; 8 x 64 KiB sectors.
- * It contains the U-Boot code (7 sectors) and the environment (1 sector).
- * Bank 1 is 4 x 1 MiB AMD AM29LV800BT; 15 x 64 KiB sectors, 1 x 32 KiB sector,
- * 2 x 8 KiB sectors, 1 x 16 KiB sectors.
- * Both parts are JEDEC compatible.
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <asm/io.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/cfi.h>
-
-#ifdef CONFIG_MTD_PARTITIONS
-#include <linux/mtd/partitions.h>
-#endif
-
-#define        DEBUG
-
-#ifdef DEBUG
-# define debugk(fmt,args...)   printk(fmt ,##args)
-#else
-# define debugk(fmt,args...)
-#endif
-
-
-#define WINDOW_ADDR0   0xFFF00000              /* 512 KiB */
-#define WINDOW_SIZE0   0x00080000
-#define BUSWIDTH0      1
-
-#define WINDOW_ADDR1   0xFF000000              /* 4 MiB */
-#define WINDOW_SIZE1   0x00400000
-#define BUSWIDTH1      8
-
-#define MSG_PREFIX "sbc8240:"  /* prefix for our printk()'s */
-#define MTDID     "sbc8240-%d" /* for mtdparts= partitioning */
-
-
-static struct map_info sbc8240_map[2] = {
-       {
-               .name           = "sbc8240 Flash Bank #0",
-               .size           = WINDOW_SIZE0,
-               .bankwidth       = BUSWIDTH0,
-       },
-       {
-               .name           = "sbc8240 Flash Bank #1",
-               .size           = WINDOW_SIZE1,
-               .bankwidth       = BUSWIDTH1,
-       }
-};
-
-#define NUM_FLASH_BANKS        ARRAY_SIZE(sbc8240_map)
-
-/*
- * The following defines the partition layout of SBC8240 boards.
- *
- * See include/linux/mtd/partitions.h for definition of the
- * mtd_partition structure.
- *
- * The *_max_flash_size is the maximum possible mapped flash size
- * which is not necessarily the actual flash size. It must correspond
- * to the value specified in the mapping definition defined by the
- * "struct map_desc *_io_desc" for the corresponding machine.
- */
-
-#ifdef CONFIG_MTD_PARTITIONS
-
-static struct mtd_partition sbc8240_uboot_partitions [] = {
-       /* Bank 0 */
-       {
-               .name = "U-boot",                       /* U-Boot Firmware      */
-               .offset =       0,
-               .size = 0x00070000,                     /*  7 x 64 KiB sectors  */
-               .mask_flags = MTD_WRITEABLE,            /*  force read-only     */
-       },
-       {
-               .name = "environment",                  /* U-Boot environment   */
-               .offset =       0x00070000,
-               .size = 0x00010000,                     /*  1 x 64 KiB sector   */
-       },
-};
-
-static struct mtd_partition sbc8240_fs_partitions [] = {
-       {
-               .name = "jffs",                         /* JFFS  filesystem     */
-               .offset =       0,
-               .size = 0x003C0000,                     /*  4 * 15 * 64KiB      */
-       },
-       {
-               .name = "tmp32",
-               .offset =       0x003C0000,
-               .size = 0x00020000,                     /*  4 * 32KiB           */
-       },
-       {
-               .name = "tmp8a",
-               .offset =       0x003E0000,
-               .size = 0x00008000,                     /*  4 * 8KiB            */
-       },
-       {
-               .name = "tmp8b",
-               .offset =       0x003E8000,
-               .size = 0x00008000,                     /*  4 * 8KiB            */
-       },
-       {
-               .name = "tmp16",
-               .offset =       0x003F0000,
-               .size = 0x00010000,                     /*  4 * 16KiB           */
-       }
-};
-
-/* trivial struct to describe partition information */
-struct mtd_part_def
-{
-       int nums;
-       unsigned char *type;
-       struct mtd_partition* mtd_part;
-};
-
-static struct mtd_info *sbc8240_mtd[NUM_FLASH_BANKS];
-static struct mtd_part_def sbc8240_part_banks[NUM_FLASH_BANKS];
-
-
-#endif /* CONFIG_MTD_PARTITIONS */
-
-
-static int __init init_sbc8240_mtd (void)
-{
-       static struct _cjs {
-               u_long addr;
-               u_long size;
-       } pt[NUM_FLASH_BANKS] = {
-               {
-                       .addr = WINDOW_ADDR0,
-                       .size = WINDOW_SIZE0
-               },
-               {
-                       .addr = WINDOW_ADDR1,
-                       .size = WINDOW_SIZE1
-               },
-       };
-
-       int devicesfound = 0;
-       int i,j;
-
-       for (i = 0; i < NUM_FLASH_BANKS; i++) {
-               printk (KERN_NOTICE MSG_PREFIX
-                       "Probing 0x%08lx at 0x%08lx\n", pt[i].size, pt[i].addr);
-
-               sbc8240_map[i].map_priv_1 =
-                       (unsigned long) ioremap (pt[i].addr, pt[i].size);
-               if (!sbc8240_map[i].map_priv_1) {
-                       printk (MSG_PREFIX "failed to ioremap\n");
-                       for (j = 0; j < i; j++) {
-                               iounmap((void *) sbc8240_map[j].map_priv_1);
-                               sbc8240_map[j].map_priv_1 = 0;
-                       }
-                       return -EIO;
-               }
-               simple_map_init(&sbc8240_mtd[i]);
-
-               sbc8240_mtd[i] = do_map_probe("jedec_probe", &sbc8240_map[i]);
-
-               if (sbc8240_mtd[i]) {
-                       sbc8240_mtd[i]->module = THIS_MODULE;
-                       devicesfound++;
-               } else {
-                       if (sbc8240_map[i].map_priv_1) {
-                               iounmap((void *) sbc8240_map[i].map_priv_1);
-                               sbc8240_map[i].map_priv_1 = 0;
-                       }
-               }
-       }
-
-       if (!devicesfound) {
-               printk(KERN_NOTICE MSG_PREFIX
-                      "No suppported flash chips found!\n");
-               return -ENXIO;
-       }
-
-#ifdef CONFIG_MTD_PARTITIONS
-       sbc8240_part_banks[0].mtd_part   = sbc8240_uboot_partitions;
-       sbc8240_part_banks[0].type       = "static image";
-       sbc8240_part_banks[0].nums       = ARRAY_SIZE(sbc8240_uboot_partitions);
-       sbc8240_part_banks[1].mtd_part   = sbc8240_fs_partitions;
-       sbc8240_part_banks[1].type       = "static file system";
-       sbc8240_part_banks[1].nums       = ARRAY_SIZE(sbc8240_fs_partitions);
-
-       for (i = 0; i < NUM_FLASH_BANKS; i++) {
-
-               if (!sbc8240_mtd[i]) continue;
-               if (sbc8240_part_banks[i].nums == 0) {
-                       printk (KERN_NOTICE MSG_PREFIX
-                               "No partition info available, registering whole device\n");
-                       add_mtd_device(sbc8240_mtd[i]);
-               } else {
-                       printk (KERN_NOTICE MSG_PREFIX
-                               "Using %s partition definition\n", sbc8240_part_banks[i].mtd_part->name);
-                       add_mtd_partitions (sbc8240_mtd[i],
-                                           sbc8240_part_banks[i].mtd_part,
-                                           sbc8240_part_banks[i].nums);
-               }
-       }
-#else
-       printk(KERN_NOTICE MSG_PREFIX
-              "Registering %d flash banks at once\n", devicesfound);
-
-       for (i = 0; i < devicesfound; i++) {
-               add_mtd_device(sbc8240_mtd[i]);
-       }
-#endif /* CONFIG_MTD_PARTITIONS */
-
-       return devicesfound == 0 ? -ENXIO : 0;
-}
-
-static void __exit cleanup_sbc8240_mtd (void)
-{
-       int i;
-
-       for (i = 0; i < NUM_FLASH_BANKS; i++) {
-               if (sbc8240_mtd[i]) {
-                       del_mtd_device (sbc8240_mtd[i]);
-                       map_destroy (sbc8240_mtd[i]);
-               }
-               if (sbc8240_map[i].map_priv_1) {
-                       iounmap ((void *) sbc8240_map[i].map_priv_1);
-                       sbc8240_map[i].map_priv_1 = 0;
-               }
-       }
-}
-
-module_init (init_sbc8240_mtd);
-module_exit (cleanup_sbc8240_mtd);
-
-MODULE_LICENSE ("GPL");
-MODULE_AUTHOR ("Carolyn Smith <carolyn.smith@tektronix.com>");
-MODULE_DESCRIPTION ("MTD map driver for SBC8240 boards");
-
index c3f62654b6df4bee93cc69a86ca839031186f910..7baba40c1ed225f38921e2143514822080bc67ae 100644 (file)
@@ -144,7 +144,7 @@ static int blktrans_open(struct block_device *bdev, fmode_t mode)
        struct mtd_blktrans_ops *tr = dev->tr;
        int ret = -ENODEV;
 
-       if (!try_module_get(dev->mtd->owner))
+       if (!get_mtd_device(NULL, dev->mtd->index))
                goto out;
 
        if (!try_module_get(tr->owner))
@@ -158,7 +158,7 @@ static int blktrans_open(struct block_device *bdev, fmode_t mode)
        ret = 0;
        if (tr->open && (ret = tr->open(dev))) {
                dev->mtd->usecount--;
-               module_put(dev->mtd->owner);
+               put_mtd_device(dev->mtd);
        out_tr:
                module_put(tr->owner);
        }
@@ -177,7 +177,7 @@ static int blktrans_release(struct gendisk *disk, fmode_t mode)
 
        if (!ret) {
                dev->mtd->usecount--;
-               module_put(dev->mtd->owner);
+               put_mtd_device(dev->mtd);
                module_put(tr->owner);
        }
 
index 208c6faa0358afe995608599ea7e39dc4a405e6d..77db5ce24d92b9fed41970d83bb1346a95740d85 100644 (file)
@@ -29,6 +29,8 @@ static struct mtdblk_dev {
        enum { STATE_EMPTY, STATE_CLEAN, STATE_DIRTY } cache_state;
 } *mtdblks[MAX_MTD_DEVICES];
 
+static struct mutex mtdblks_lock;
+
 /*
  * Cache stuff...
  *
@@ -270,15 +272,19 @@ static int mtdblock_open(struct mtd_blktrans_dev *mbd)
 
        DEBUG(MTD_DEBUG_LEVEL1,"mtdblock_open\n");
 
+       mutex_lock(&mtdblks_lock);
        if (mtdblks[dev]) {
                mtdblks[dev]->count++;
+               mutex_unlock(&mtdblks_lock);
                return 0;
        }
 
        /* OK, it's not open. Create cache info for it */
        mtdblk = kzalloc(sizeof(struct mtdblk_dev), GFP_KERNEL);
-       if (!mtdblk)
+       if (!mtdblk) {
+               mutex_unlock(&mtdblks_lock);
                return -ENOMEM;
+       }
 
        mtdblk->count = 1;
        mtdblk->mtd = mtd;
@@ -291,6 +297,7 @@ static int mtdblock_open(struct mtd_blktrans_dev *mbd)
        }
 
        mtdblks[dev] = mtdblk;
+       mutex_unlock(&mtdblks_lock);
 
        DEBUG(MTD_DEBUG_LEVEL1, "ok\n");
 
@@ -304,6 +311,8 @@ static int mtdblock_release(struct mtd_blktrans_dev *mbd)
 
        DEBUG(MTD_DEBUG_LEVEL1, "mtdblock_release\n");
 
+       mutex_lock(&mtdblks_lock);
+
        mutex_lock(&mtdblk->cache_mutex);
        write_cached_data(mtdblk);
        mutex_unlock(&mtdblk->cache_mutex);
@@ -316,6 +325,9 @@ static int mtdblock_release(struct mtd_blktrans_dev *mbd)
                vfree(mtdblk->cache_data);
                kfree(mtdblk);
        }
+
+       mutex_unlock(&mtdblks_lock);
+
        DEBUG(MTD_DEBUG_LEVEL1, "ok\n");
 
        return 0;
@@ -376,6 +388,8 @@ static struct mtd_blktrans_ops mtdblock_tr = {
 
 static int __init init_mtdblock(void)
 {
+       mutex_init(&mtdblks_lock);
+
        return register_mtd_blktrans(&mtdblock_tr);
 }
 
index fac54a3fa3f189c60aaf58a197be7867aed4ca80..00ebf7af7467b6b35dac1a2e2c32c432b11528ad 100644 (file)
@@ -65,8 +65,8 @@ static void mtd_release(struct device *dev)
 static int mtd_cls_suspend(struct device *dev, pm_message_t state)
 {
        struct mtd_info *mtd = dev_to_mtd(dev);
-       
-       if (mtd->suspend)
+
+       if (mtd && mtd->suspend)
                return mtd->suspend(mtd);
        else
                return 0;
@@ -76,7 +76,7 @@ static int mtd_cls_resume(struct device *dev)
 {
        struct mtd_info *mtd = dev_to_mtd(dev);
        
-       if (mtd->resume)
+       if (mtd && mtd->resume)
                mtd->resume(mtd);
        return 0;
 }
@@ -298,6 +298,7 @@ int add_mtd_device(struct mtd_info *mtd)
                        mtd->dev.class = &mtd_class;
                        mtd->dev.devt = MTD_DEVT(i);
                        dev_set_name(&mtd->dev, "mtd%d", i);
+                       dev_set_drvdata(&mtd->dev, mtd);
                        if (device_register(&mtd->dev) != 0) {
                                mtd_table[i] = NULL;
                                break;
index 38d656b9b2eecc8f5029bb0b7a6e89f921ff5a2d..0108ed42e877b628d773f4ee847bccd47c98bbc7 100644 (file)
@@ -266,7 +266,7 @@ static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 
        if (ONENAND_CURRENT_BUFFERRAM(this)) {
                if (area == ONENAND_DATARAM)
-                       return mtd->writesize;
+                       return this->writesize;
                if (area == ONENAND_SPARERAM)
                        return mtd->oobsize;
        }
@@ -770,6 +770,7 @@ static int __devexit omap2_onenand_remove(struct platform_device *pdev)
        }
        iounmap(c->onenand.base);
        release_mem_region(c->phys_base, ONENAND_IO_SIZE);
+       gpmc_cs_free(c->gpmc_cs);
        kfree(c);
 
        return 0;
index ebc9b8dca881f588e974fbcb60faabf9642902f8..2314ad7ee5fef4544ab2159cd7e253ed6e1d3889 100644 (file)
@@ -1505,7 +1505,6 @@ static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
                        }
 
                        set_bit(num, iommu->domain_ids);
-                       set_bit(iommu->seq_id, &domain->iommu_bmp);
                        iommu->domains[num] = domain;
                        id = num;
                }
@@ -1648,6 +1647,14 @@ static int domain_context_mapped(struct pci_dev *pdev)
                                             tmp->devfn);
 }
 
+/* Returns a number of VTD pages, but aligned to MM page size */
+static inline unsigned long aligned_nrpages(unsigned long host_addr,
+                                           size_t size)
+{
+       host_addr &= ~PAGE_MASK;
+       return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
+}
+
 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
                            struct scatterlist *sg, unsigned long phys_pfn,
                            unsigned long nr_pages, int prot)
@@ -1675,7 +1682,7 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
                uint64_t tmp;
 
                if (!sg_res) {
-                       sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT;
+                       sg_res = aligned_nrpages(sg->offset, sg->length);
                        sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
                        sg->dma_length = sg->length;
                        pteval = page_to_phys(sg_page(sg)) | prot;
@@ -2415,14 +2422,6 @@ error:
        return ret;
 }
 
-/* Returns a number of VTD pages, but aligned to MM page size */
-static inline unsigned long aligned_nrpages(unsigned long host_addr,
-                                           size_t size)
-{
-       host_addr &= ~PAGE_MASK;
-       return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
-}
-
 /* This takes a number of _MM_ pages, not VTD pages */
 static struct iova *intel_alloc_iova(struct device *dev,
                                     struct dmar_domain *domain,
@@ -2551,6 +2550,7 @@ static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
        int prot = 0;
        int ret;
        struct intel_iommu *iommu;
+       unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
 
        BUG_ON(dir == DMA_NONE);
 
@@ -2585,7 +2585,7 @@ static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
         * is not a big problem
         */
        ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
-                                paddr >> VTD_PAGE_SHIFT, size, prot);
+                                mm_to_dma_pfn(paddr_pfn), size, prot);
        if (ret)
                goto error;
 
@@ -2875,7 +2875,7 @@ static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int ne
 
        start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
 
-       ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot);
+       ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
        if (unlikely(ret)) {
                /*  clear the page */
                dma_pte_clear_range(domain, start_vpfn,
@@ -3408,6 +3408,7 @@ static int md_domain_init(struct dmar_domain *domain, int guest_width)
 
        domain->iommu_count = 0;
        domain->iommu_coherency = 0;
+       domain->iommu_snooping = 0;
        domain->max_addr = 0;
 
        /* always allocate the top pgd */
index fb00ed5296e6f5bb6aa42ddb5d366cd1088afe90..fed1a9a1ffb4e7db9aedae7ff0b498ed933e27f7 100644 (file)
@@ -76,7 +76,7 @@ static int s3c2400_serial_probe(struct platform_device *dev)
        return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
 }
 
-static struct platform_driver s3c2400_serial_drv = {
+static struct platform_driver s3c2400_serial_driver = {
        .probe          = s3c2400_serial_probe,
        .remove         = __devexit_p(s3c24xx_serial_remove),
        .driver         = {
@@ -85,16 +85,16 @@ static struct platform_driver s3c2400_serial_drv = {
        },
 };
 
-s3c24xx_console_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
+s3c24xx_console_init(&s3c2400_serial_driver, &s3c2400_uart_inf);
 
 static inline int s3c2400_serial_init(void)
 {
-       return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
+       return s3c24xx_serial_init(&s3c2400_serial_driver, &s3c2400_uart_inf);
 }
 
 static inline void s3c2400_serial_exit(void)
 {
-       platform_driver_unregister(&s3c2400_serial_drv);
+       platform_driver_unregister(&s3c2400_serial_driver);
 }
 
 module_init(s3c2400_serial_init);
index b5d7cbcba2ae23b6c171ccdbe5ef664d71f12b6f..c99f0821cae32d06cea9e387e795cca1ebdecbd0 100644 (file)
@@ -88,7 +88,7 @@ static int s3c2410_serial_probe(struct platform_device *dev)
        return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
 }
 
-static struct platform_driver s3c2410_serial_drv = {
+static struct platform_driver s3c2410_serial_driver = {
        .probe          = s3c2410_serial_probe,
        .remove         = __devexit_p(s3c24xx_serial_remove),
        .driver         = {
@@ -97,16 +97,16 @@ static struct platform_driver s3c2410_serial_drv = {
        },
 };
 
-s3c24xx_console_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
+s3c24xx_console_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
 
 static int __init s3c2410_serial_init(void)
 {
-       return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
+       return s3c24xx_serial_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
 }
 
 static void __exit s3c2410_serial_exit(void)
 {
-       platform_driver_unregister(&s3c2410_serial_drv);
+       platform_driver_unregister(&s3c2410_serial_driver);
 }
 
 module_init(s3c2410_serial_init);
index 11dcb90bdfefaa8fa5f6d391f01c8ba0298465e7..6e057d8809d3dbbe2095dfebeb335195f7ad5719 100644 (file)
@@ -121,7 +121,7 @@ static int s3c2412_serial_probe(struct platform_device *dev)
        return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
 }
 
-static struct platform_driver s3c2412_serial_drv = {
+static struct platform_driver s3c2412_serial_driver = {
        .probe          = s3c2412_serial_probe,
        .remove         = __devexit_p(s3c24xx_serial_remove),
        .driver         = {
@@ -130,16 +130,16 @@ static struct platform_driver s3c2412_serial_drv = {
        },
 };
 
-s3c24xx_console_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
+s3c24xx_console_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
 
 static inline int s3c2412_serial_init(void)
 {
-       return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
+       return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
 }
 
 static inline void s3c2412_serial_exit(void)
 {
-       platform_driver_unregister(&s3c2412_serial_drv);
+       platform_driver_unregister(&s3c2412_serial_driver);
 }
 
 module_init(s3c2412_serial_init);
index 06c5b0cc47a3c23b991e31bbd694bcc9d1277ba3..69ff5d340f044ac9735f525c772041e8680eade2 100644 (file)
@@ -151,7 +151,7 @@ static int s3c2440_serial_probe(struct platform_device *dev)
        return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
 }
 
-static struct platform_driver s3c2440_serial_drv = {
+static struct platform_driver s3c2440_serial_driver = {
        .probe          = s3c2440_serial_probe,
        .remove         = __devexit_p(s3c24xx_serial_remove),
        .driver         = {
@@ -160,16 +160,16 @@ static struct platform_driver s3c2440_serial_drv = {
        },
 };
 
-s3c24xx_console_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
+s3c24xx_console_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
 
 static int __init s3c2440_serial_init(void)
 {
-       return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
+       return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
 }
 
 static void __exit s3c2440_serial_exit(void)
 {
-       platform_driver_unregister(&s3c2440_serial_drv);
+       platform_driver_unregister(&s3c2440_serial_driver);
 }
 
 module_init(s3c2440_serial_init);
index 786a067d62aceed1710c5e5a5884d10803951d31..26c49e18bdd123034ebdc771a918791632c33341 100644 (file)
@@ -92,7 +92,7 @@ static int s3c24a0_serial_probe(struct platform_device *dev)
        return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
 }
 
-static struct platform_driver s3c24a0_serial_drv = {
+static struct platform_driver s3c24a0_serial_driver = {
        .probe          = s3c24a0_serial_probe,
        .remove         = __devexit_p(s3c24xx_serial_remove),
        .driver         = {
@@ -101,16 +101,16 @@ static struct platform_driver s3c24a0_serial_drv = {
        },
 };
 
-s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
+s3c24xx_console_init(&s3c24a0_serial_driver, &s3c24a0_uart_inf);
 
 static int __init s3c24a0_serial_init(void)
 {
-       return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
+       return s3c24xx_serial_init(&s3c24a0_serial_driver, &s3c24a0_uart_inf);
 }
 
 static void __exit s3c24a0_serial_exit(void)
 {
-       platform_driver_unregister(&s3c24a0_serial_drv);
+       platform_driver_unregister(&s3c24a0_serial_driver);
 }
 
 module_init(s3c24a0_serial_init);
index 48f1a3781f0de5f3af388665c4b3575d9fdadcc5..4be92ab50058284f0cf823bf4ed4ab10b5c80be9 100644 (file)
@@ -122,7 +122,7 @@ static int s3c6400_serial_probe(struct platform_device *dev)
        return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
 }
 
-static struct platform_driver s3c6400_serial_drv = {
+static struct platform_driver s3c6400_serial_driver = {
        .probe          = s3c6400_serial_probe,
        .remove         = __devexit_p(s3c24xx_serial_remove),
        .driver         = {
@@ -131,16 +131,16 @@ static struct platform_driver s3c6400_serial_drv = {
        },
 };
 
-s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
+s3c24xx_console_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
 
 static int __init s3c6400_serial_init(void)
 {
-       return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
+       return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
 }
 
 static void __exit s3c6400_serial_exit(void)
 {
-       platform_driver_unregister(&s3c6400_serial_drv);
+       platform_driver_unregister(&s3c6400_serial_driver);
 }
 
 module_init(s3c6400_serial_init);
index 998e89dc5aaf2db56eda9f18c1060ea8c9189555..e0665630e4dada82de5e3e816beaf0cb2c637b7c 100644 (file)
@@ -549,7 +549,7 @@ static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
                .mapbase        = KS8695_UART_VA,
                .iotype         = SERIAL_IO_MEM,
                .irq            = KS8695_IRQ_UART_TX,
-               .uartclk        = CLOCK_TICK_RATE * 16,
+               .uartclk        = KS8695_CLOCK_RATE * 16,
                .fifosize       = 16,
                .ops            = &ks8695uart_pops,
                .flags          = ASYNC_BOOT_AUTOCONF,
index 524231047de5cfe5a8f56a53de320e6e7d8c0b91..9e6573cf97d3864a0490a9f4296404cba94046e6 100644 (file)
@@ -1,5 +1,6 @@
 config B3DFG
        tristate "Brontes 3d Frame Framegrabber"
+       depends on PCI
        default n
        ---help---
          This driver provides support for the Brontes 3d Framegrabber
index ae8d588d3a2774d67f94440a48cb40d360a597c7..c7206f8bcd9388ca1b72d9b17754318e11f28149 100644 (file)
@@ -1,5 +1,6 @@
 config HECI
        tristate "Intel Management Engine Interface (MEI) Support"
+       depends on PCI
        ---help---
          The Intel Management Engine Interface (Intel MEI) driver allows
          applications to access the Active Management Technology
index 2f8155c1968b31652f63f781c0e15071fd25afe6..04e2f92c0f6293292d55d5a56822a936d0a4ba52 100644 (file)
@@ -716,6 +716,8 @@ static int MapUserBuffer(struct ioctl_struct *io, struct device_extension *pdx)
                pdx->PixelUrb[frameInfo][i]->transfer_flags =
                    URB_NO_TRANSFER_DMA_MAP | URB_NO_INTERRUPT;
        }
+       if (i == 0)
+               return -EINVAL;
        /* only interrupt when last URB completes */
        pdx->PixelUrb[frameInfo][--i]->transfer_flags &= ~URB_NO_INTERRUPT;
        pdx->pendedPixelUrbs[frameInfo] =
index 85175c1824328f58d3aa652de7240bdd6ab5bf2b..25b53ac3f8204f9484e002beaedf77db6d5acb3e 100644 (file)
@@ -43,9 +43,6 @@
 #include "rtmp_type.h"
 #include <linux/module.h>
 #include <linux/kernel.h>
-#if !defined(RT2860) && !defined(RT30xx)
-#include <linux/kthread.h>
-#endif
 
 #include <linux/spinlock.h>
 #include <linux/init.h>
@@ -166,9 +163,7 @@ typedef int (*HARD_START_XMIT_FUNC)(struct sk_buff *skb, struct net_device *net_
 
 #ifndef RT30xx
 typedef        struct pid *    THREAD_PID;
-#ifdef RT2860
 #define        THREAD_PID_INIT_VALUE   NULL
-#endif
 #define        GET_PID(_v)     find_get_pid(_v)
 #define        GET_PID_NUMBER(_v)      pid_nr(_v)
 #define CHECK_PID_LEGALITY(_pid)       if (pid_nr(_pid) >= 0)
@@ -188,12 +183,12 @@ struct os_cookie {
        dma_addr_t                              pAd_pa;
 #endif
 #ifdef RT2870
-       struct usb_device       *pUsb_Dev;
+       struct usb_device               *pUsb_Dev;
 
 #ifndef RT30xx
-       struct task_struct      *MLMEThr_task;
-       struct task_struct      *RTUSBCmdThr_task;
-       struct task_struct      *TimerQThr_task;
+       THREAD_PID                              MLMEThr_pid;
+       THREAD_PID                              RTUSBCmdThr_pid;
+       THREAD_PID                              TimerQThr_pid;
 #endif
 #ifdef RT30xx
        struct pid      *MLMEThr_pid;
index dd01c64fbf61fd09432cc6d0452213239d4801eb..a4e8696ca39c4dba233fb9851af7146a2cc88ab7 100644 (file)
@@ -235,7 +235,7 @@ INT MlmeThread(
        DBGPRINT(RT_DEBUG_TRACE,( "<---%s\n",__func__));
 
 #ifndef RT30xx
-       pObj->MLMEThr_task = NULL;
+       pObj->MLMEThr_pid = THREAD_PID_INIT_VALUE;
 #endif
 #ifdef RT30xx
        pObj->MLMEThr_pid = NULL;
@@ -348,7 +348,7 @@ INT RTUSBCmdThread(
        DBGPRINT(RT_DEBUG_TRACE,( "<---RTUSBCmdThread\n"));
 
 #ifndef RT30xx
-       pObj->RTUSBCmdThr_task = NULL;
+       pObj->RTUSBCmdThr_pid = THREAD_PID_INIT_VALUE;
 #endif
 #ifdef RT30xx
        pObj->RTUSBCmdThr_pid = NULL;
@@ -447,7 +447,7 @@ INT TimerQThread(
        DBGPRINT(RT_DEBUG_TRACE,( "<---%s\n",__func__));
 
 #ifndef RT30xx
-       pObj->TimerQThr_task = NULL;
+       pObj->TimerQThr_pid = THREAD_PID_INIT_VALUE;
 #endif
 #ifdef RT30xx
        pObj->TimerQThr_pid = NULL;
@@ -883,46 +883,69 @@ VOID RT28xxThreadTerminate(
 
        // Terminate Threads
 #ifndef RT30xx
-       BUG_ON(pObj->TimerQThr_task == NULL);
-       CHECK_PID_LEGALITY(task_pid(pObj->TimerQThr_task))
+       CHECK_PID_LEGALITY(pObj->TimerQThr_pid)
        {
                POS_COOKIE pObj = (POS_COOKIE)pAd->OS_Cookie;
 
-               printk(KERN_DEBUG "Terminate the TimerQThr pid=%d!\n",
-                       pid_nr(task_pid(pObj->TimerQThr_task)));
+               printk("Terminate the TimerQThr_pid=%d!\n", GET_PID_NUMBER(pObj->TimerQThr_pid));
                mb();
                pAd->TimerFunc_kill = 1;
                mb();
-               kthread_stop(pObj->TimerQThr_task);
-               pObj->TimerQThr_task = NULL;
+               ret = KILL_THREAD_PID(pObj->TimerQThr_pid, SIGTERM, 1);
+               if (ret)
+               {
+                       printk(KERN_WARNING "%s: unable to stop TimerQThread, pid=%d, ret=%d!\n",
+                                       pAd->net_dev->name, GET_PID_NUMBER(pObj->TimerQThr_pid), ret);
+               }
+               else
+               {
+                       wait_for_completion(&pAd->TimerQComplete);
+                       pObj->TimerQThr_pid = THREAD_PID_INIT_VALUE;
+               }
        }
 
-       BUG_ON(pObj->MLMEThr_task == NULL);
-       CHECK_PID_LEGALITY(task_pid(pObj->MLMEThr_task))
+       CHECK_PID_LEGALITY(pObj->MLMEThr_pid)
        {
-               printk(KERN_DEBUG "Terminate the MLMEThr pid=%d!\n",
-                       pid_nr(task_pid(pObj->MLMEThr_task)));
+               printk("Terminate the MLMEThr_pid=%d!\n", GET_PID_NUMBER(pObj->MLMEThr_pid));
                mb();
                pAd->mlme_kill = 1;
                //RT28XX_MLME_HANDLER(pAd);
                mb();
-               kthread_stop(pObj->MLMEThr_task);
-               pObj->MLMEThr_task = NULL;
+               ret = KILL_THREAD_PID(pObj->MLMEThr_pid, SIGTERM, 1);
+               if (ret)
+               {
+                       printk (KERN_WARNING "%s: unable to Mlme thread, pid=%d, ret=%d!\n",
+                                       pAd->net_dev->name, GET_PID_NUMBER(pObj->MLMEThr_pid), ret);
+               }
+               else
+               {
+                       //wait_for_completion (&pAd->notify);
+                       wait_for_completion (&pAd->mlmeComplete);
+                       pObj->MLMEThr_pid = THREAD_PID_INIT_VALUE;
+               }
        }
 
-       BUG_ON(pObj->RTUSBCmdThr_task == NULL);
-       CHECK_PID_LEGALITY(task_pid(pObj->RTUSBCmdThr_task))
+       CHECK_PID_LEGALITY(pObj->RTUSBCmdThr_pid)
        {
-               printk(KERN_DEBUG "Terminate the RTUSBCmdThr pid=%d!\n",
-                       pid_nr(task_pid(pObj->RTUSBCmdThr_task)));
+               printk("Terminate the RTUSBCmdThr_pid=%d!\n", GET_PID_NUMBER(pObj->RTUSBCmdThr_pid));
                mb();
                NdisAcquireSpinLock(&pAd->CmdQLock);
                pAd->CmdQ.CmdQState = RT2870_THREAD_STOPED;
                NdisReleaseSpinLock(&pAd->CmdQLock);
                mb();
                //RTUSBCMDUp(pAd);
-               kthread_stop(pObj->RTUSBCmdThr_task);
-               pObj->RTUSBCmdThr_task = NULL;
+               ret = KILL_THREAD_PID(pObj->RTUSBCmdThr_pid, SIGTERM, 1);
+               if (ret)
+               {
+                       printk(KERN_WARNING "%s: unable to RTUSBCmd thread, pid=%d, ret=%d!\n",
+                                       pAd->net_dev->name, GET_PID_NUMBER(pObj->RTUSBCmdThr_pid), ret);
+               }
+               else
+               {
+                       //wait_for_completion (&pAd->notify);
+                       wait_for_completion (&pAd->CmdQComplete);
+                       pObj->RTUSBCmdThr_pid = THREAD_PID_INIT_VALUE;
+               }
        }
 #endif
 #ifdef RT30xx
@@ -1045,7 +1068,7 @@ BOOLEAN RT28XXChipsetCheck(
                        dev_p->descriptor.idProduct == rtusb_usb_id[i].idProduct)
                {
 #ifndef RT30xx
-                       printk(KERN_DEBUG "rt2870: idVendor = 0x%x, idProduct = 0x%x\n",
+                       printk("rt2870: idVendor = 0x%x, idProduct = 0x%x\n",
 #endif
 #ifdef RT30xx
                        printk("rt2870: idVendor = 0x%x, idProduct = 0x%x\n",
index 0f4c8af97e47f5c5b06f4f4b80ebbddcc7ed81b9..80909e9ab5aea5469dd2b60a29f35e8edef7b93f 100644 (file)
@@ -700,8 +700,8 @@ NDIS_STATUS AdapterBlockAllocateMemory(
        usb_dev = pObj->pUsb_Dev;
 
 #ifndef RT30xx
-       pObj->MLMEThr_task              = NULL;
-       pObj->RTUSBCmdThr_task  = NULL;
+       pObj->MLMEThr_pid               = THREAD_PID_INIT_VALUE;
+       pObj->RTUSBCmdThr_pid   = THREAD_PID_INIT_VALUE;
 #endif
 #ifdef RT30xx
        pObj->MLMEThr_pid       = NULL;
@@ -743,7 +743,7 @@ NDIS_STATUS  CreateThreads(
        PRTMP_ADAPTER pAd = net_dev->ml_priv;
        POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie;
 #ifndef RT30xx
-       struct task_struct *tsk;
+       pid_t pid_number = -1;
 #endif
 #ifdef RT30xx
        pid_t pid_number;
@@ -762,10 +762,10 @@ NDIS_STATUS        CreateThreads(
 
        // Creat MLME Thread
 #ifndef RT30xx
-       pObj->MLMEThr_task = NULL;
-       tsk = kthread_run(MlmeThread, pAd, "%s", pAd->net_dev->name);
-
-       if (IS_ERR(tsk)) {
+       pObj->MLMEThr_pid= THREAD_PID_INIT_VALUE;
+       pid_number = kernel_thread(MlmeThread, pAd, CLONE_VM);
+       if (pid_number < 0)
+       {
 #endif
 #ifdef RT30xx
        pObj->MLMEThr_pid = NULL;
@@ -778,7 +778,7 @@ NDIS_STATUS  CreateThreads(
        }
 
 #ifndef RT30xx
-       pObj->MLMEThr_task = tsk;
+       pObj->MLMEThr_pid = GET_PID(pid_number);
 #endif
 #ifdef RT30xx
        pObj->MLMEThr_pid = find_get_pid(pid_number);
@@ -788,10 +788,9 @@ NDIS_STATUS         CreateThreads(
 
        // Creat Command Thread
 #ifndef RT30xx
-       pObj->RTUSBCmdThr_task = NULL;
-       tsk = kthread_run(RTUSBCmdThread, pAd, "%s", pAd->net_dev->name);
-
-       if (IS_ERR(tsk) < 0)
+       pObj->RTUSBCmdThr_pid= THREAD_PID_INIT_VALUE;
+       pid_number = kernel_thread(RTUSBCmdThread, pAd, CLONE_VM);
+       if (pid_number < 0)
 #endif
 #ifdef RT30xx
        pObj->RTUSBCmdThr_pid = NULL;
@@ -804,7 +803,7 @@ NDIS_STATUS  CreateThreads(
        }
 
 #ifndef RT30xx
-       pObj->RTUSBCmdThr_task = tsk;
+       pObj->RTUSBCmdThr_pid = GET_PID(pid_number);
 #endif
 #ifdef RT30xx
        pObj->RTUSBCmdThr_pid = find_get_pid(pid_number);
@@ -812,9 +811,9 @@ NDIS_STATUS  CreateThreads(
        wait_for_completion(&(pAd->CmdQComplete));
 
 #ifndef RT30xx
-       pObj->TimerQThr_task = NULL;
-       tsk = kthread_run(TimerQThread, pAd, "%s", pAd->net_dev->name);
-       if (IS_ERR(tsk) < 0)
+       pObj->TimerQThr_pid= THREAD_PID_INIT_VALUE;
+       pid_number = kernel_thread(TimerQThread, pAd, CLONE_VM);
+       if (pid_number < 0)
 #endif
 #ifdef RT30xx
        pObj->TimerQThr_pid = NULL;
@@ -826,7 +825,7 @@ NDIS_STATUS  CreateThreads(
                return NDIS_STATUS_FAILURE;
        }
 #ifndef RT30xx
-       pObj->TimerQThr_task = tsk;
+       pObj->TimerQThr_pid = GET_PID(pid_number);
 #endif
 #ifdef RT30xx
        pObj->TimerQThr_pid = find_get_pid(pid_number);
index fd1b0c18f2a007633a733807e76cb8e2620c9a13..704b5c2d5091a1327492f509c16e2b4d4a798075 100644 (file)
@@ -984,8 +984,7 @@ NDIS_STATUS RTUSBEnqueueCmdFromNdis(
        POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie;
 
 #ifndef RT30xx
-       BUG_ON(pObj->RTUSBCmdThr_task == NULL);
-       CHECK_PID_LEGALITY(task_pid(pObj->RTUSBCmdThr_task))
+       CHECK_PID_LEGALITY(pObj->RTUSBCmdThr_pid)
 #endif
 #ifdef RT30xx
        if (pObj->RTUSBCmdThr_pid < 0)
index 29e3b53e52a1be04c06797344ed95ff810d23e40..2b8872b2fd9dcf116522cd90efe206e9f9ae51ff 100644 (file)
@@ -79,6 +79,7 @@
 {      \
        {USB_DEVICE(0x148F,0x2770)}, /* Ralink */               \
        {USB_DEVICE(0x1737,0x0071)}, /* Linksys WUSB600N */     \
+       {USB_DEVICE(0x1737,0x0070)}, /* Linksys */      \
        {USB_DEVICE(0x148F,0x2870)}, /* Ralink */               \
        {USB_DEVICE(0x148F,0x3070)}, /* Ralink */               \
        {USB_DEVICE(0x0B05,0x1731)}, /* Asus */                 \
        {USB_DEVICE(0x14B2,0x3C06)}, /* Conceptronic */         \
        {USB_DEVICE(0x14B2,0x3C28)}, /* Conceptronic */         \
        {USB_DEVICE(0x2019,0xED06)}, /* Planex Communications, Inc. */          \
+       {USB_DEVICE(0x2019,0xED14)}, /* Planex Communications, Inc. */          \
        {USB_DEVICE(0x2019,0xAB25)}, /* Planex Communications, Inc. RT3070 */           \
        {USB_DEVICE(0x07D1,0x3C09)}, /* D-Link */               \
        {USB_DEVICE(0x07D1,0x3C11)}, /* D-Link */               \
        {USB_DEVICE(0x14B2,0x3C07)}, /* AL */                   \
        {USB_DEVICE(0x14B2,0x3C12)}, /* AL */           \
        {USB_DEVICE(0x050D,0x8053)}, /* Belkin */               \
+       {USB_DEVICE(0x050D,0x815C)}, /* Belkin */               \
        {USB_DEVICE(0x14B2,0x3C23)}, /* Airlink */              \
        {USB_DEVICE(0x14B2,0x3C27)}, /* Airlink */              \
        {USB_DEVICE(0x07AA,0x002F)}, /* Corega */               \
@@ -587,16 +590,14 @@ VOID RTUSBBulkRxComplete(purbb_t pUrb, struct pt_regs *pt_regs);
 #define RTUSBMlmeUp(pAd)               \
 {                                                                  \
        POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie;  \
-       BUG_ON(pObj->MLMEThr_task == NULL);                 \
-       CHECK_PID_LEGALITY(task_pid(pObj->MLMEThr_task))                    \
+       CHECK_PID_LEGALITY(pObj->MLMEThr_pid)               \
         up(&(pAd->mlme_semaphore)); \
 }
 
 #define RTUSBCMDUp(pAd)                        \
 {                                                                          \
        POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie;  \
-       BUG_ON(pObj->RTUSBCmdThr_task == NULL);     \
-       CHECK_PID_LEGALITY(task_pid(pObj->RTUSBCmdThr_task))        \
+       CHECK_PID_LEGALITY(pObj->RTUSBCmdThr_pid)           \
            up(&(pAd->RTUSBCmd_semaphore)); \
 }
 #endif
index 0edb09a536f999bfefe40ef4b40c98329804e90d..ea9739318037e847f21dc955785d3fbb29529ec0 100644 (file)
@@ -2645,7 +2645,7 @@ extern int ieee80211_encrypt_fragment(
        struct sk_buff *frag,
        int hdr_len);
 
-extern int ieee80211_xmit(struct sk_buff *skb,
+extern int rtl8192_ieee80211_xmit(struct sk_buff *skb,
                          struct net_device *dev);
 extern void ieee80211_txb_free(struct ieee80211_txb *);
 
index 720bfcbfadc1dbdd805c2ffed373b986910d6fce..5e3a2cbed2b1324dbd883c7457780e34c824bf1c 100644 (file)
@@ -2645,7 +2645,7 @@ extern int ieee80211_encrypt_fragment(
        struct sk_buff *frag,
        int hdr_len);
 
-extern int ieee80211_xmit(struct sk_buff *skb,
+extern int rtl8192_ieee80211_xmit(struct sk_buff *skb,
                          struct net_device *dev);
 extern void ieee80211_txb_free(struct ieee80211_txb *);
 
index 7294572b990f7fecf9c0f43df3f50a2f6528bcdd..cba12b84be5c1dab2c767f0fa4ff496a9ed41478 100644 (file)
@@ -618,7 +618,7 @@ void ieee80211_query_seqnum(struct ieee80211_device*ieee, struct sk_buff* skb, u
        }
 }
 
-int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev)
+int rtl8192_ieee80211_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0))
        struct ieee80211_device *ieee = netdev_priv(dev);
@@ -943,5 +943,6 @@ int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev)
        return 1;
 
 }
+EXPORT_SYMBOL(rtl8192_ieee80211_xmit);
 
 EXPORT_SYMBOL(ieee80211_txb_free);
index 4ab250743e81984c0dbcf9282bffc23ee7248984..70f81a8f12913b7e2ccda789331f2343fc28eda5 100644 (file)
@@ -12142,7 +12142,7 @@ static const struct net_device_ops rtl8192_netdev_ops = {
        .ndo_set_mac_address    = r8192_set_mac_adr,
        .ndo_validate_addr      = eth_validate_addr,
        .ndo_change_mtu         = eth_change_mtu,
-       .ndo_start_xmit         = ieee80211_xmit,
+       .ndo_start_xmit         = rtl8192_ieee80211_xmit,
 };
 
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
index e1f89416ef8cdf6235b2cfcebdbda23ab213f7e7..2bfc41ece0e1d2df04ab058f742e76fd7b7749e9 100644 (file)
@@ -387,7 +387,6 @@ static void acm_rx_tasklet(unsigned long _acm)
        struct acm_ru *rcv;
        unsigned long flags;
        unsigned char throttled;
-       struct usb_host_endpoint *ep;
 
        dbg("Entering acm_rx_tasklet");
 
@@ -463,14 +462,12 @@ urbs:
 
                rcv->buffer = buf;
 
-               ep = (usb_pipein(acm->rx_endpoint) ? acm->dev->ep_in : acm->dev->ep_out)
-                               [usb_pipeendpoint(acm->rx_endpoint)];
-               if (usb_endpoint_xfer_int(&ep->desc))
+               if (acm->is_int_ep)
                        usb_fill_int_urb(rcv->urb, acm->dev,
                                         acm->rx_endpoint,
                                         buf->base,
                                         acm->readsize,
-                                        acm_read_bulk, rcv, ep->desc.bInterval);
+                                        acm_read_bulk, rcv, acm->bInterval);
                else
                        usb_fill_bulk_urb(rcv->urb, acm->dev,
                                          acm->rx_endpoint,
@@ -1183,6 +1180,9 @@ made_compressed_probe:
        spin_lock_init(&acm->read_lock);
        mutex_init(&acm->mutex);
        acm->rx_endpoint = usb_rcvbulkpipe(usb_dev, epread->bEndpointAddress);
+       acm->is_int_ep = usb_endpoint_xfer_int(epread);
+       if (acm->is_int_ep)
+               acm->bInterval = epread->bInterval;
        tty_port_init(&acm->port);
        acm->port.ops = &acm_port_ops;
 
index 1602324808bafb510e374520b9eb0a264617dc02..c4a0ee8ffccfb3ae4203c8cac4d091d88177b478 100644 (file)
@@ -126,6 +126,8 @@ struct acm {
        unsigned int ctrl_caps;                         /* control capabilities from the class specific header */
        unsigned int susp_count;                        /* number of suspended interfaces */
        int combined_interfaces:1;                      /* control and data collapsed */
+       int is_int_ep:1;                                /* interrupt endpoints contrary to spec used */
+       u8 bInterval;
        struct acm_wb *delayed_wb;                      /* write queued for a device about to be woken */
 };
 
index 38b8bce782d6d12cbcb01a8b83452948e48570f7..4247eccf858c62c656cc58e91a40591eb3789786 100644 (file)
@@ -595,7 +595,7 @@ static int usbdev_open(struct inode *inode, struct file *file)
        if (!ps)
                goto out;
 
-       ret = -ENOENT;
+       ret = -ENODEV;
 
        /* usbdev device-node */
        if (imajor(inode) == USB_DEVICE_MAJOR)
@@ -1321,7 +1321,8 @@ static int get_urb32(struct usbdevfs_urb *kurb,
                     struct usbdevfs_urb32 __user *uurb)
 {
        __u32  uptr;
-       if (get_user(kurb->type, &uurb->type) ||
+       if (!access_ok(VERIFY_READ, uurb, sizeof(*uurb)) ||
+           __get_user(kurb->type, &uurb->type) ||
            __get_user(kurb->endpoint, &uurb->endpoint) ||
            __get_user(kurb->status, &uurb->status) ||
            __get_user(kurb->flags, &uurb->flags) ||
@@ -1536,8 +1537,9 @@ static int proc_ioctl_compat(struct dev_state *ps, compat_uptr_t arg)
        u32 udata;
 
        uioc = compat_ptr((long)arg);
-       if (get_user(ctrl.ifno, &uioc->ifno) ||
-           get_user(ctrl.ioctl_code, &uioc->ioctl_code) ||
+       if (!access_ok(VERIFY_READ, uioc, sizeof(*uioc)) ||
+           __get_user(ctrl.ifno, &uioc->ifno) ||
+           __get_user(ctrl.ioctl_code, &uioc->ioctl_code) ||
            __get_user(udata, &uioc->data))
                return -EFAULT;
        ctrl.data = compat_ptr(udata);
index 7d03549c3339ecc5ebdc5025db1d9f3b6d42f148..11c627ce60224754978bf495e40cd94496c3b7c7 100644 (file)
@@ -903,7 +903,8 @@ static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
                        /* already started */
                        break;
                case QH_STATE_IDLE:
-                       WARN_ON(1);
+                       /* QH might be waiting for a Clear-TT-Buffer */
+                       qh_completions(ehci, qh);
                        break;
                }
                break;
index 9a1384747f3bc8ca092b226d6de8fed5d6850276..7673554fa64df28317e4edb9e97eecedd3272fc8 100644 (file)
@@ -375,12 +375,11 @@ qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh)
                                 */
                                if ((token & QTD_STS_XACT) &&
                                                QTD_CERR(token) == 0 &&
-                                               --qh->xacterrs > 0 &&
+                                               ++qh->xacterrs < QH_XACTERR_MAX &&
                                                !urb->unlinked) {
                                        ehci_dbg(ehci,
        "detected XactErr len %zu/%zu retry %d\n",
-       qtd->length - QTD_LENGTH(token), qtd->length,
-       QH_XACTERR_MAX - qh->xacterrs);
+       qtd->length - QTD_LENGTH(token), qtd->length, qh->xacterrs);
 
                                        /* reset the token in the qtd and the
                                         * qh overlay (which still contains
@@ -494,7 +493,7 @@ halt:
                last = qtd;
 
                /* reinit the xacterr counter for the next qtd */
-               qh->xacterrs = QH_XACTERR_MAX;
+               qh->xacterrs = 0;
        }
 
        /* last urb's completion might still need calling */
@@ -940,7 +939,8 @@ static void qh_link_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
        head->qh_next.qh = qh;
        head->hw_next = dma;
 
-       qh->xacterrs = QH_XACTERR_MAX;
+       qh_get(qh);
+       qh->xacterrs = 0;
        qh->qh_state = QH_STATE_LINKED;
        /* qtd completions reported later by interrupt */
 }
@@ -1080,7 +1080,7 @@ submit_async (
         * the HC and TT handle it when the TT has a buffer ready.
         */
        if (likely (qh->qh_state == QH_STATE_IDLE))
-               qh_link_async (ehci, qh_get (qh));
+               qh_link_async(ehci, qh);
  done:
        spin_unlock_irqrestore (&ehci->lock, flags);
        if (unlikely (qh == NULL))
@@ -1115,8 +1115,6 @@ static void end_unlink_async (struct ehci_hcd *ehci)
                        && HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
                qh_link_async (ehci, qh);
        else {
-               qh_put (qh);            // refcount from async list
-
                /* it's not free to turn the async schedule on/off; leave it
                 * active but idle for a while once it empties.
                 */
@@ -1124,6 +1122,7 @@ static void end_unlink_async (struct ehci_hcd *ehci)
                                && ehci->async->qh_next.qh == NULL)
                        timer_action (ehci, TIMER_ASYNC_OFF);
        }
+       qh_put(qh);                     /* refcount from async list */
 
        if (next) {
                ehci->reclaim = NULL;
index 74f7f83b29ad9485ec9242afdbc1f91115a98f76..edd61ee90323ce99a5b8fe9eba5fec0c18b2fd23 100644 (file)
@@ -542,6 +542,7 @@ static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
                }
        }
        qh->qh_state = QH_STATE_LINKED;
+       qh->xacterrs = 0;
        qh_get (qh);
 
        /* update per-qh bandwidth for usbfs */
index 70073b157f0ab7e875ab1fdad3bedaa4e97e5c8c..803adcb5ac1d3e358f481963b1c1d20e6d23e260 100644 (file)
@@ -12,6 +12,7 @@ config USB_MUSB_HDRC
        depends on !SUPERH
        select NOP_USB_XCEIV if ARCH_DAVINCI
        select TWL4030_USB if MACH_OMAP_3430SDP
+       select NOP_USB_XCEIV if MACH_OMAP3EVM
        select USB_OTG_UTILS
        tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
        help
index b574878c78b27b633a056d96cf3eb36a25d098b6..8fec5d4455c94334eaa12ab8c80c3f47566fd84b 100644 (file)
@@ -699,6 +699,9 @@ static struct usb_device_id id_table_combined [] = {
                .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
        { USB_DEVICE(LARSENBRUSGAARD_VID, LB_ALTITRACK_PID) },
        { USB_DEVICE(GN_OTOMETRICS_VID, AURICAL_USB_PID) },
+       { USB_DEVICE(BAYER_VID, BAYER_CONTOUR_CABLE_PID) },
+       { USB_DEVICE(FTDI_VID, MARVELL_OPENRD_PID),
+               .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
        { },                                    /* Optional parameter entry */
        { }                                     /* Terminating entry */
 };
index 24dbd99e87d722a95beac152af27a475c46cac2b..8c92b88166aec7a50be1f14aba009b802d518193 100644 (file)
 #define GN_OTOMETRICS_VID      0x0c